WO2025246712A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置

Info

Publication number
WO2025246712A1
WO2025246712A1 PCT/CN2025/089325 CN2025089325W WO2025246712A1 WO 2025246712 A1 WO2025246712 A1 WO 2025246712A1 CN 2025089325 W CN2025089325 W CN 2025089325W WO 2025246712 A1 WO2025246712 A1 WO 2025246712A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
light
driving structure
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/089325
Other languages
English (en)
French (fr)
Other versions
WO2025246712A9 (zh
Inventor
张凡
张锴
孙华平
颜海龙
陈亚菲
张钧
付强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025246712A1 publication Critical patent/WO2025246712A1/zh
Publication of WO2025246712A9 publication Critical patent/WO2025246712A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This disclosure relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device.
  • OLEDs Organic light-emitting diodes
  • QLEDs quantum dot light-emitting diodes
  • TFTs thin-film transistors
  • this disclosure provides a display substrate having a display area and a non-display area.
  • the display substrate includes: a substrate and a driving structure layer group and a light-emitting structure layer sequentially stacked on the substrate.
  • the driving structure layer group is provided with a plurality of pixel driving circuits located in the display area.
  • the light-emitting structure layer is provided with a plurality of light-emitting devices located in the display area. The light-emitting devices are electrically connected to the pixel driving circuits.
  • the driving structure layer group includes: K driving structure layers stacked sequentially along the substrate, at least one driving structure layer including: at least one pixel driving circuit, the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit on the substrate in at least two of the K driving structure layers, and the orthographic projection of at least one pixel driving circuit in at least one of the at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate, wherein K is a positive integer greater than or equal to 2.
  • At least one driving structure layer includes: an M-row N-column pixel driving circuit
  • the orthographic projections of the pixel driving circuits in the m-th row and n-th column of at least two of the K driving structure layers onto the substrate at least partially overlap, 1 ⁇ m ⁇ M, 1 ⁇ n ⁇ N.
  • the light-emitting device includes: a first electrode electrically connected to a pixel driving circuit; the first electrodes of the plurality of light-emitting devices are arranged in an array; the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same row are located in the same driving circuit layer; and the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same column are located in different driving circuit layers.
  • At least one driving structure layer includes: a plurality of anode connection electrodes, the plurality of anode connection electrodes corresponding one-to-one with a plurality of pixel driving circuits in at least one driving structure layer, the pixel driving circuit including: at least one transistor, the transistor including: an active layer, a gate electrode, a first electrode and a second electrode.
  • At least one anode connection electrode is electrically connected to a corresponding pixel driving circuit and a light-emitting device connected to the corresponding pixel driving circuit.
  • the film layer in which the anode connection electrode is located is on the side of the film layer in which at least one of the active layer, gate electrode, first electrode, and second electrode of at least one transistor is located, away from the substrate.
  • the orthogonal projections of the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers on the substrate at least partially overlap.
  • At least one anode connection electrode extends at least partially along a first direction.
  • the drive structure layer group further includes: a plurality of vias exposing the anode connection electrode;
  • the orthographic projection of the via of at least one anode connection electrode in the r-th driving structure layer on the substrate does not overlap with the orthographic projection of the structure in at least two driving structure layers from the (r+1)-th to the K-th driving structure layers on the substrate, and 1 ⁇ r ⁇ K-1.
  • the structure in the at least one driving structure layer includes: a pixel driving circuit in the driving structure layer and a signal line connected to the pixel driving circuit.
  • vias exposing the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers are arranged along the first direction.
  • the orthographic projection of at least one anode connection electrode on the substrate and the orthographic projection of the first signal line connected to the pixel driving circuit corresponding to the anode connection electrode on the substrate do not overlap.
  • the first signal line includes a first power line and a data signal line.
  • the drive structure layer group further includes: K-1 protective layers;
  • the r-th protection layer is located between the r-th driving structure layer and the (r+1)-th driving structure layer, where 1 ⁇ r ⁇ K-1.
  • the at least one driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;
  • the pixel driving circuit includes: at least one transistor and a capacitor;
  • the capacitor includes: two plates; and the signal lines connected to the pixel driving circuit include: a scan signal line, a reset signal line, a first initial signal line, a second initial signal line, a light emission signal line, a data signal line, and a first power supply line.
  • the semiconductor layer includes at least: an active layer of at least one transistor;
  • the first conductive layer includes at least: a gate electrode of at least one transistor, one of the plates of a capacitor, a scan signal line, a reset signal line, and a light emission signal line;
  • the second conductive layer includes at least: the other electrode of the capacitor, a first initial signal line, and a second initial signal line;
  • the third conductive layer includes at least: a first and second electrode of at least one transistor, a data signal line, and a first power supply line;
  • the fourth conductive layer includes at least an anode connection electrode.
  • the at least one driving circuit layer further includes: a first flattening layer and a second flattening layer;
  • the first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.
  • it further includes: K source driver chip groups located in the non-display area, wherein at least one source driver chip group includes: at least one source driver chip;
  • the data signal lines connecting the k-th source driver chip group and the pixel driver circuit in the k-th driver structure layer are electrically connected, where 1 ⁇ k ⁇ K.
  • the data signal line connected to at least one column of pixel driving circuits in the r-th driving structure layer is electrically connected to the data signal line connected to at least one column of pixel driving circuits in the (r+1)-th driving structure layer, where 1 ⁇ r ⁇ K-1.
  • it further includes: K gate driving circuits located in the non-display area;
  • the kth gate driving circuit is located on the kth driving structure layer, and the kth gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the kth driving structure layer; the K gate driving circuits are stacked sequentially along the substrate direction, 1 ⁇ k ⁇ K.
  • At least one gate driving circuit is electrically connected to an initial signal line, and different gate driving circuits are connected to different initial signal lines.
  • the kth first light-emitting power line is located on the kth driving structure layer, and the kth first light-emitting power line is electrically connected to the first power line connected to the pixel driving circuit located in the kth driving structure layer.
  • At least two of the K first light-emitting power lines are electrically connected to each other.
  • it further includes: K first driving power lines and K second driving power lines located in the non-display area.
  • the kth first driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive; the kth second driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive.
  • the first drive power lines in at least two of the K drive structure layers are electrically connected to each other.
  • the second drive power lines in at least two of the K drive structure layers are electrically connected to each other.
  • this disclosure also provides a display device, including: the aforementioned display substrate.
  • Figure 1 is a schematic diagram of the structure of a display device
  • Figure 2 is a schematic diagram of a planar structure of a display substrate
  • Figure 3 is a schematic diagram of a planar structure of a display substrate
  • Figure 4 is a schematic diagram of a planar structure of a display substrate
  • Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit
  • Figure 6 is a timing diagram of a pixel driving circuit.
  • Figure 7A is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure.
  • Figure 7B is a schematic diagram of the driving structure layer group
  • Figure 8 is a top view of the display substrate provided in an embodiment of this disclosure.
  • Figure 9A is a top view of the first driving structure layer in Figure 8.
  • Figure 9B is a top view of the first driving structure layer in Figure 8.
  • Figure 10 is a top view of the second driving structure layer in Figure 8.
  • Figure 11 is a schematic diagram of part of the film layers in Figure 8.
  • Figure 12 is another schematic diagram of the display substrate structure
  • Figure 13 is a schematic diagram after the semiconductor layer pattern of the first driving structure layer is formed
  • Figure 14 is a schematic diagram after the first conductive layer pattern of the first driving structure layer is formed
  • Figure 15 is a schematic diagram after the second conductive layer pattern of the first driving structure layer is formed
  • Figure 16 is a schematic diagram after the formation of the third conductive layer pattern of the first driving structure layer
  • Figure 17 is a schematic diagram of the fourth conductive layer pattern after the formation of the first driving structure layer
  • Figure 18 is a schematic diagram after the semiconductor layer pattern of the second driving structure layer is formed
  • Figure 19 is a schematic diagram after the first conductive layer pattern of the second driving structure layer is formed
  • Figure 20 is a schematic diagram after the second conductive layer pattern of the second driving structure layer is formed
  • Figure 21 is a schematic diagram after the formation of the third conductive layer pattern of the second driving structure layer
  • Figure 22 is a schematic diagram after the fourth conductive layer pattern of the second driving structure layer is formed
  • Figure 23 is a schematic diagram after the second planarization layer pattern of the second driving structure layer is formed
  • Figure 24 is a schematic diagram after the formation of the anodic conductive layer in the light-emitting structure layer.
  • the scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto.
  • the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures.
  • the figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values shown in the figures.
  • connection should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
  • a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • electrical connection includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an “electrical function,” as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of “electrical functions” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
  • the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different.
  • the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.
  • Figure 1 is a schematic diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is connected to the data driver, the scan driver, and the light-emitting driver.
  • the data driver is connected to multiple data signal lines (D1 to Dn)
  • the scan driver is connected to multiple scan signal lines (S1 to Sm)
  • the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo).
  • the pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers.
  • At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit.
  • the circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively.
  • the timing controller can provide grayscale values and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver.
  • the data driver can use the grayscale values and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn.
  • the data driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number.
  • the scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller.
  • the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm.
  • a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number.
  • An LED driver can generate transmit signals to be provided to LED signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller.
  • an LED driver can sequentially provide transmit signals with off-level pulses to LED signal lines E1 to Eo.
  • an LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.
  • Figure 2 is a schematic diagram of a planar structure of a display substrate (one type)
  • Figure 3 is a schematic diagram of a planar structure of a display substrate (two types)
  • Figure 4 is a schematic diagram of a planar structure of a display substrate (three types).
  • the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.
  • Each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light-emitting device.
  • the pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line.
  • the pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device.
  • the light-emitting devices in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels.
  • the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.
  • the first sub-pixel P1 can be a red sub-pixel (R) emitting red light
  • the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light
  • the third sub-pixel P3 can be a green sub-pixel (G) emitting green light.
  • the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.
  • a pixel unit may include three sub-pixels.
  • the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement, etc., and this disclosure does not limit the arrangement.
  • Figure 2 illustrates the arrangement of three sub-pixels horizontally side by side as an example
  • Figure 3 illustrates the arrangement of three sub-pixels in a triangular arrangement as an example.
  • a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the specific arrangement.
  • Figure 4 illustrates an example of four sub-pixels arranged in a square manner.
  • the light-emitting device may include a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.
  • the anode of the light-emitting device is electrically connected to a pixel driving circuit
  • the cathode of the light-emitting device is electrically connected to a second power line.
  • the light-emitting device L may include a current-driven device, such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED).
  • a current-driven device such as a current-driven light-emitting diode, like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-emitting diode (QLED).
  • a current-driven light-emitting diode like a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum light-
  • the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • HIL stacked hole injection layer
  • HTL hole transport layer
  • EBL electron block layer
  • EML emitting layer
  • HBL hole block layer
  • ETL electron transport layer
  • EIL electron injection layer
  • the hole injection layer of all sub-pixels can be a common layer connected together
  • the electron injection layer of all sub-pixels can be a common layer connected together
  • the hole transport layer of all sub-pixels can be a common layer connected together
  • the electron transport layer of all sub-pixels can be a common layer connected together
  • the hole blocking layer of all sub-pixels can be a common layer connected together
  • the light emission layer of adjacent sub-pixels can have a small overlap or can be isolated
  • the electron blocking layer of adjacent sub-pixels can have a small overlap or can be isolated.
  • the first power line VDD continuously provides a high-level signal, and the signal of the first power line VDD is a DC signal.
  • the second power line VSS continuously provides a low-level signal, and the signal of the second power line VSS is a DC signal.
  • Figure 5 is an equivalent circuit diagram of a pixel driving circuit.
  • the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.
  • the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T7) and one capacitor C.
  • the pixel driving circuit can be connected to the data signal line Data, the scan signal line Gate, the reset signal line Reset, the light emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, and the first power supply line VDD, respectively.
  • the pixel driving circuit may include a first node N1, a second node N2, and a third node N3.
  • the first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively.
  • the second node N2 is connected to the second terminal of the first transistor T1, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the capacitor C, respectively.
  • the third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.
  • the first end of capacitor C is connected to the first power line VDD, and the second end of capacitor C is connected to the second node N2, that is, the second end of capacitor C is connected to the control electrode of the third transistor T3.
  • the control electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2.
  • the first transistor T1 transmits the initialization voltage of the first initial signal line INIT1 to the control electrode of the third transistor T3, so as to initialize the charge of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the scan signal line Gate, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of capacitor C.
  • the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3.
  • the third transistor T3 can be called the driving transistor.
  • the third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.
  • the control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line Data, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 can be called a switching transistor, scan transistor, etc. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line Data to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device.
  • the fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.
  • the control electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device.
  • the seventh transistor T7 transmits the initialization voltage of the second initial signal line INIT2 to the first electrode of the light-emitting device, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device.
  • the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.
  • the scan signal line Gate is the scan signal line Gate in the pixel driving circuit of this display row
  • the reset signal line Reset is the scan signal line Gate in the pixel driving circuit of the previous display row. That is, the reset signal line Reset of this display row and the scan signal line Gate in the pixel driving circuit of the previous display row are the same signal line, which can reduce the number of signal lines on the display panel and achieve a narrow bezel on the display panel.
  • transistors can be classified into N-type transistors and P-type transistors.
  • a transistor When a transistor is P-type, its turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and its turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage).
  • a transistor When a transistor is N-type, its turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and its turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage).
  • the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both.
  • the active layer of the LTPS is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide (Oxide).
  • LTPS has advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.
  • the scan signal line Gate, the reset signal line Reset, the light emission signal line EM, the first initial signal line INIT1, and the second initial signal line INIT2 can extend in the horizontal direction, while the second power line VSS, the first power line VDD, and the data signal line Data can extend in the vertical direction.
  • the first initial signal line INIT1 and the second initial signal line INIT2 can be the same signal line.
  • FIG 6 is a timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of this disclosure through the operation of the pixel driving circuit illustrated in Figure 5.
  • the pixel driving circuit in Figure 5 includes 7 transistors (first transistor T1 to seventh transistor T7) and 1 capacitor C. All 7 transistors are P-type transistors.
  • the operation of the pixel driving circuit may include:
  • the first stage, A1 is called the reset stage.
  • the Reset signal is low, while the Gate and EM signals are high.
  • transistors T1 and T7 are turned on.
  • the INIT1 signal is sent to node N2 to initialize (reset) capacitor C, clearing its charge.
  • the INIT2 signal is sent to the anode of the light-emitting device to initialize (reset) its first electrode, clearing its charge.
  • transistors T2, T4, T5, and T6 are turned off. During this stage, the light-emitting device does not emit light.
  • the second stage, A2 is called the data writing stage or threshold compensation stage.
  • the Gate signal is low, while the Reset and EM signals are high.
  • the Data signal outputs a data voltage.
  • the third transistor T3 is turned on.
  • the low Gate signal turns on the second and fourth transistors T4.
  • the turn on T2 and T4 allows the data voltage output from the Data signal to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2.
  • the difference between the data voltage output from the Data signal and the threshold voltage of the third transistor T3 is charged into capacitor C.
  • the voltage at the second terminal of capacitor C (second node N2) is Vd -
  • the Reset signal is high, turning off the first transistor T1 and the seventh transistor T7.
  • the signal on the luminous signal line EM is a high-level signal, which disconnects the fifth transistor T5 and the sixth transistor T6.
  • the third stage, A3, is called the light-emitting stage.
  • the light-emitting signal line EM is at a low level, while the scan signal line Gate and the reset signal line Reset are at a high level.
  • the low-level signal on the light-emitting signal line EM turns on the fifth transistor T5 and the sixth transistor T6.
  • the power supply voltage output from the first power supply line VDD then provides a driving voltage to the first electrode of the light-emitting device through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vd -
  • )-Vth] 2 K*(Vdd-Vd) 2
  • I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the threshold voltage of the third transistor T3
  • Vd is the data voltage output by the data signal line Data
  • Vdd is the power supply voltage output by the first power supply line VDD.
  • the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current. This ensures uniform display brightness of the display product and improves the overall display effect of the display product.
  • the low density of light-emitting devices in display devices makes it difficult to achieve a high PPI.
  • Figure 7A is a schematic diagram of the structure of the display substrate provided in the embodiment of this disclosure
  • Figure 7B is a schematic diagram of the structure of the driving structure layer group
  • Figure 8 is a top view of the display substrate provided in the embodiment of this disclosure.
  • the display substrate provided in the embodiment of this disclosure has a display area and a non-display area.
  • the display substrate includes: a substrate 10 and a driving structure layer group 20 and a light-emitting structure layer 30 sequentially stacked on the substrate.
  • the driving structure layer group 20 is provided with a plurality of pixel driving circuits located in the display area
  • the light-emitting structure layer 30 is provided with a plurality of light-emitting devices located in the display area.
  • the light-emitting devices are electrically connected to the pixel driving circuits.
  • the driving structure layer group 20 includes: K driving structure layers 21 sequentially stacked along the substrate 10.
  • At least one driving structure layer includes: at least one pixel driving circuit.
  • the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit in at least two of the K driving structure layers on the substrate.
  • the orthographic projection of at least one pixel driving circuit in at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate.
  • K is a positive integer greater than or equal to 2.
  • this disclosure provides a driving structure layer group comprising K driving structure layers stacked sequentially along a substrate, wherein the orthographic projection of at least one light-emitting device on the substrate at least partially overlaps with the orthographic projection of at least one pixel driving circuit in at least two of the K driving structure layers on the substrate, and the orthographic projection of at least one pixel driving circuit in at least one driving structure layer on the substrate at least partially overlaps with the orthographic projection of at least two light-emitting devices on the substrate.
  • the substrate may be a flexible substrate or a rigid substrate.
  • the rigid substrate may include, but is not limited to, one or more of glass and quartz
  • the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.
  • the pixel driving circuits located in different driving structure layers may have the same structure or different structures. Having the same structure for the pixel driving circuits in different driving structure layers can reduce the number of photomasks used in the display substrate, thus lowering manufacturing costs.
  • Figure 8 illustrates an example where the pixel driving circuits in different driving structure layers have the same structure.
  • At least one driving structure layer may include: an M-row N-column pixel driving circuit; the orthographic projections of the m-th row and n-th column pixel driving circuits in at least two of the K driving structure layers on the substrate at least partially overlap, 1 ⁇ m ⁇ M, 1 ⁇ n ⁇ N.
  • the light-emitting device includes: a first electrode 31 electrically connected to a pixel driving circuit; an array of first electrodes 31 of multiple light-emitting devices are arranged; the pixel driving circuits connected to the first electrodes 31 of adjacent light-emitting devices in the same row are located in the same driving circuit layer; and the pixel driving circuits connected to the first electrodes of adjacent light-emitting devices in the same column are located in different driving circuit layers.
  • At least one driving structure layer includes: a plurality of anode connection electrodes AL, the plurality of anode connection electrodes AL corresponding one-to-one with a plurality of pixel driving circuits in at least one driving structure layer, and the pixel driving circuit includes: at least one transistor, the transistor including: an active layer, a gate electrode, a first electrode and a second electrode.
  • At least one anode connection electrode AL is electrically connected to a corresponding pixel driving circuit and a light-emitting device connected to the corresponding pixel driving circuit.
  • the film layer in which the anode connection electrode AL is located is on the side of the film layer in which at least one of the active layer, gate electrode, first electrode, and second electrode of at least one transistor is located, away from the substrate.
  • Figure 9A is a top view of the first driving structure layer in Figure 8
  • Figure 9B is a top view of the first driving structure layer in Figure 8
  • Figure 10 is a top view of the second driving structure layer in Figure 8.
  • AL1 in Figures 9A and 9B refers to the anode connection electrode in the first driving structure layer
  • AL2 in Figure 10 refers to the anode connection electrode in the second driving structure layer.
  • Figure 11 is a schematic diagram of a portion of the film layers in Figure 8.
  • Figure 11 includes the film layer containing the anode connection electrode in the first driving structure layer and the film layer containing the anode connection electrode in the second driving structure layer.
  • the orthographic projections of the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers on the substrate at least partially overlap.
  • At least one anode connection electrode AL extends at least partially along a first direction D1.
  • At least one anode connection electrode AL located in the first drive structure layer may extend at least partially along the second direction D2.
  • the drive structure layer group further includes: a plurality of vias V exposing the anode connection electrode.
  • the orthographic projection of the via exposing at least one anode connection electrode in the r-th driving structure layer onto the substrate does not overlap with the orthographic projection of the structures in at least two of the driving structure layers from the (r+1)-th to the K-th driving structure layers onto the substrate, where 1 ⁇ r ⁇ K-1.
  • the structure in at least one driving structure layer includes a pixel driving circuit within the driving structure layer and signal lines connected to the pixel driving circuit.
  • V1 refers to the via exposing the anode connection electrode in the first driving structure layer
  • V2 refers to the via exposing the anode connection electrode in the second driving structure layer.
  • the absence of an overlap between the orthographic projection of the via exposing at least one anode connection electrode in the r-th driving structure layer and the orthographic projection of the structures in at least two of the driving structure layers from the (r+1)-th to the K-th driving structure layers on the substrate ensures that the first electrode of the light-emitting device located in the light-emitting structure layer can be accurately and reliably electrically connected to the anode connection electrode through the via exposing at least one anode connection electrode in the r-th driving structure layer.
  • the anode connection electrode is electrically connected to the film layer where the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) is located through the via V.
  • the anode connection electrode can serve as the second electrode of the sixth transistor (which is also the second electrode of the seventh transistor) and be electrically connected to the film layer containing the active layers of the sixth and seventh transistors through a via. This disclosure does not limit this in any way.
  • the anode connection electrodes in the first to the (K-1)th driving structure layers may be at least partially disposed in the blank area, wherein the blank area refers to the area where there is no overlap between any structure of the pixel driving circuit and the orthogonal projection of the signal connected to the pixel driving circuit on the substrate.
  • the anode connection electrode in the Kth driving structure layer can be located at any position, and it is not necessary to set blank areas in some regions.
  • the signal lines connected to the pixel driving circuit may include: a first initial signal line INIT1, a second initial signal line INIT2, an EM light emission signal line, a Gate scan signal line, a Reset reset signal line, a Data signal line Data, and a first power supply line VDD.
  • vias exposing the anode connection electrodes corresponding to the pixel driving circuits in the m-th row and n-th column of two adjacent driving structure layers in the K driving structure layers are arranged along the first direction D1.
  • at least one via V1 and at least one via V2 are arranged along the first direction D1, wherein the orthographic projection of the pixel driving circuit connected to the anode connection electrode exposed by the via V1 arranged along the first direction D1 on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuit connected to the anode connection electrode exposed by the via V2 on the substrate.
  • the orthographic projection of at least one anode connection electrode AL on the substrate and the orthographic projection of the first signal line connected to the pixel driving circuit corresponding to the anode connection electrode AL on the substrate do not overlap;
  • the first signal line includes: a first power line VDD and a data signal line Data.
  • FIG12 is another structural schematic diagram of the display substrate, wherein the driving structure layer group 20 further includes: K-1 protective layers 22.
  • the r-th protective layer is located between the r-th driving structure layer and the (r+1)-th driving structure layer, and 1 ⁇ r ⁇ K-1.
  • the protective layer may be a single-layer structure or a multi-layer structure.
  • the protective layer may be made of inorganic materials, such as silicon oxide and silicon nitride, or it may be made of organic materials. This disclosure does not limit the application of these materials.
  • At least one driving circuit layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer; the pixel driving circuit includes: at least one transistor and a capacitor; the capacitor includes: two plates; and the signal lines connected to the pixel driving circuit include: a scan signal line, a reset signal line, a first initial signal line, a second initial signal line, a light emission signal line, a data signal line, and a first power supply line.
  • the semiconductor layer includes at least: an active layer for at least one transistor;
  • the first conductive layer includes at least: the gate electrode of at least one transistor, one of the plates of a capacitor, a scan signal line, a reset signal line, and a light emission signal line;
  • the second conductive layer includes at least: the other electrode of the capacitor, a first initial signal line, and a second initial signal line;
  • the third conductive layer includes at least: a first and second electrode of at least one transistor, a data signal line, and a first power supply line;
  • the fourth conductive layer includes at least an anode connection electrode.
  • the film structure of different driving circuit layers may be the same or different, and this disclosure does not limit this in any way.
  • At least one driving circuit layer further includes: a first planarization layer and a second planarization layer; wherein the first planarization layer is located between the third conductive layer and the fourth conductive layer, and the second planarization layer is located on the side of the fourth conductive layer away from the substrate.
  • At least a portion of the via exposing the anode connection electrode is formed on the second planar layer.
  • the sides of the display area may include a first side, a second side, a third side, and a fourth side, wherein the first side and the second side are arranged opposite to each other, and the third side and the fourth side are arranged opposite to each other.
  • the display substrate may further include: K source driver chip groups located in the non-display area, at least one source driver chip group including: at least one source driver chip; the kth source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the kth driving structure layer, 1 ⁇ k ⁇ K.
  • the first source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the first driving structure layer
  • the second source driver chip group is electrically connected to the data signal line connected to the pixel driver circuit in the second driving structure layer, and so on.
  • the display substrate may further include: a source driver chipset, wherein the data signal lines connected to at least one column of pixel driver circuits in at least one driving structure layer are electrically connected to the source driver chipset, and the data signal lines connected to at least one column of pixel driver circuits in the r-th driving structure layer are electrically connected to the data signal lines connected to at least one column of pixel driver circuits in the (r+1)-th driving structure layer, where 1 ⁇ r ⁇ K-1.
  • the data signal lines connected to at least one column of pixel driving circuits in the r-th driving structure layer can be electrically connected to the data signal lines connected to at least one column of pixel driving circuits in the (r+1)-th driving structure layer through vias located in the non-display area.
  • the vias can be located on the third or fourth side of the display area.
  • the source driver chipset may be located on the third or fourth side of the display area.
  • the display substrate further includes K gate driving circuits located in the non-display area.
  • the kth gate driving circuit is located on the kth driving structure layer, and the kth gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the kth driving structure layer; the K gate driving circuits are stacked sequentially along the substrate direction, 1 ⁇ k ⁇ K.
  • the first gate driving circuit is electrically connected to the scan signal line connected to the pixel driving circuit in the first driving structure layer
  • the second group of gate driving circuits is electrically connected to the scan signal line connected to the pixel driving circuit in the second driving structure layer.
  • the gate driving circuit may be located on at least one of the first and second sides of the display area.
  • At least one gate driving circuit is electrically connected to an initial signal line, and different gate driving circuits are connected to different initial signal lines.
  • the output signals of at least two of the K gate driving circuits are at the same time or may be different, that is, the timing of the pixel driving circuits in different driving structure layers may be controlled together or individually.
  • the display substrate further includes: K first light-emitting power lines located in the non-display area; the signal lines connected to at least one pixel driving circuit include: first power lines; the kth first light-emitting power line is located on the kth driving structure layer, and the kth first light-emitting power line is electrically connected to the first power line connected to the pixel driving circuit located in the kth driving structure layer. At least two of the K first light-emitting power lines are electrically connected to each other.
  • the display substrate further includes a second light-emitting power line located in the non-display area, and the second electrode of at least one light-emitting device is electrically connected to the second light-emitting power line through a via.
  • the second light-emitting power line may be located in at least one driving structure layer.
  • the display substrate further includes: K first driving power lines and K second driving power lines located in the non-display area, wherein the kth first driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive, and the kth second driving power line is located on the kth driving structure layer and is electrically connected to the kth gate drive.
  • the first drive power lines in at least two of the K drive structure layers are electrically connected to each other.
  • the first drive power lines in at least two of the K drive structure layers can be electrically connected to each other through vias.
  • the second drive power lines in at least two of the K drive structure layers are electrically connected to each other.
  • the second drive power lines in at least two of the K drive structure layers can be electrically connected to each other through vias.
  • the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode.
  • the anode is connected to the pixel driving circuit via a via
  • the organic light-emitting layer is connected to the anode
  • the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode.
  • the display substrate may further include isolation pillars.
  • the organic light-emitting layer may include an emissive layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).
  • EML emissive layer
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL hole blocking layer
  • HBL hole blocking layer
  • HBL hole blocking layer
  • ETL electron transport layer
  • EIL electron injection layer
  • one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.
  • the display substrate may also include other film layers, such as an encapsulation structure layer and a touch structure layer, which are not limited herein.
  • the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.
  • the first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.
  • the touch structure layer may include a first touch insulating layer disposed on the encapsulation structure layer, a first touch metal layer disposed on the first touch insulating layer, a second touch insulating layer covering the first touch metal layer, a second touch metal layer disposed on the second touch insulating layer, and a touch protective layer covering the second touch metal layer.
  • the first touch metal layer may include a plurality of bridging electrodes
  • the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes. The first touch electrodes or the second touch electrodes may be connected to the bridging electrodes through vias.
  • the display substrate disclosed herein can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.
  • pixel driving circuits such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc.
  • the substrate fabrication process is illustrated below with reference to Figure 8, which illustrates an example of a driving structure layer group comprising two driving structure layers with identical film structures.
  • the "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include organic material coating, mask exposure, and development.
  • Deposition can be performed using sputtering, evaporation, or chemical vapor deposition; coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used.
  • a “thin film” refers to a thin film made of a material on a substrate using deposition, coating, or other processes. If the "thin film” does not require a patterning process during the entire fabrication process, it can also be called a “layer.” If the "thin film” requires a patterning process during the entire fabrication process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern.”
  • the phrase “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the orthographic projection of A includes the orthographic projection of B means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • Forming a semiconductor layer pattern for the first driving structure layer may include: sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer covering the substrate and a semiconductor layer pattern located on the first insulating layer of the first driving structure layer, as shown in FIG13, FIG13 being a schematic diagram after forming the semiconductor layer pattern of the first driving structure layer.
  • the semiconductor layer pattern of the first driving structure layer may include at least the active pattern T11-1 of the first transistor to the active pattern T71-1 of the seventh transistor of at least one pixel driving circuit located in the first driving structure layer.
  • forming a first conductive layer pattern of the first driving structure layer may include: depositing a second insulating film and a first conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the first conductive film by a patterning process to form a second insulating layer covering the semiconductor layer pattern of the first driving structure layer and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG14, FIG14 being a schematic diagram after forming the first conductive layer pattern of the first driving structure layer.
  • the first conductive layer pattern of the first driving structure layer may include at least: the gate electrode T21-1 to the gate electrode T72-1 of the first transistor of at least one pixel driving circuit located in the first driving structure layer and the first plate C1-1 of the capacitor, as well as the reset signal line Reset-1, the light emission signal line EM-1 and the scan signal line Gate-1 connected to at least one pixel driving circuit located in the first driving structure layer.
  • Forming a second conductive layer pattern of the first driving structure layer includes: depositing a third insulating film and a second conductive film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the third insulating film and the second conductive film through a patterning process to form a third insulating layer of the first driving structure layer and a second conductive layer pattern located on the third insulating layer, as shown in Figure 15.
  • Figure 15 is a schematic diagram after the formation of the second conductive layer pattern of the first driving structure layer.
  • the second conductive layer pattern may include at least: the second plate C2-1 of the capacitor of at least one pixel driving circuit located in the first driving structure layer, and the first initial signal line INIT1-1 and the second initial signal line INIT2-1 connected to at least one pixel driving circuit in the first driving structure layer.
  • Forming a third conductive layer pattern of the first driving structure layer includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer including multiple vias, depositing a third conductive film on the fourth insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the fourth insulating layer of the first driving structure layer, as shown in Figure 16.
  • Figure 16 is a schematic diagram after forming the third conductive layer pattern of the first driving structure layer.
  • the third conductive layer pattern of the first driving structure layer may include at least: the first pole T13-1 and the second pole T14-1 of the first transistor of at least one pixel driving circuit located in the first driving structure layer to the first pole T73-1 and the second pole T74-2 of the seventh transistor.
  • Forming a fourth conductive layer pattern of the first driving structure layer includes: coating a first planar thin film on the substrate on which the aforementioned pattern is formed, patterning the first planar thin film by a patterning process to form a first planar layer including vias, depositing a fourth conductive thin film on the first planar layer, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern located on the first planar layer of the first driving structure layer, as shown in FIG17.
  • FIG17 is a schematic diagram after forming the fourth conductive layer pattern of the first driving structure layer.
  • the fourth conductive layer pattern of the first driving structure layer may include at least: an anode connection electrode AL1 connected to at least one pixel driving circuit located in the first driving structure layer.
  • forming a semiconductor layer pattern for the second driving structure layer may include: coating a second planar thin film on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating thin film and a second semiconductor thin film, and patterning the second semiconductor thin film using a patterning process to form a first insulating layer of the second driving structure layer and a semiconductor layer pattern located on the first insulating layer, as shown in FIG18, FIG18 being a schematic diagram after forming the semiconductor layer pattern of the second driving structure layer.
  • the semiconductor layer pattern of the second driving structure layer may include at least the active pattern T11-2 of the first transistor to the active pattern T71-2 of the seventh transistor of at least one pixel driving circuit located in the second driving structure layer.
  • Forming a first conductive layer pattern for the second driving structure layer may include: depositing a sixth insulating film and a fifth conductive film sequentially on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern of the second driving structure layer and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG19, FIG19 being a schematic diagram after forming the first conductive layer pattern of the second driving structure layer.
  • the first conductive layer pattern of the second driving structure layer may include at least: the gate electrode T21-2 to the gate electrode T72-2 of the first transistor of at least one pixel driving circuit located in the second driving structure layer and the first plate C1-2 of the capacitor, as well as the reset signal line Reset-2, the light emission signal line EM-2 and the scan signal line Gate-2 connected to at least one pixel driving circuit located in the second driving structure layer.
  • Forming a second conductive layer pattern of the second driving structure layer includes: depositing a seventh insulating film and a sixth conductive film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the seventh insulating film and the sixth conductive film by a patterning process to form a third insulating layer of the second driving structure layer and a second conductive layer pattern located on the third insulating layer, as shown in Figure 20.
  • Figure 20 is a schematic diagram after the second conductive layer pattern of the second driving structure layer is formed.
  • the second conductive layer pattern of the second driving structure layer may include at least: the second plate C2-2 of the capacitor of at least one pixel driving circuit located in the second driving structure layer, and the first initial signal line INIT1-2 and the second initial signal line INIT2-2 connected to at least one pixel driving circuit of the second driving structure layer.
  • Forming a third conductive layer pattern of the second driving structure layer includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film through a patterning process to form a fourth insulating layer including multiple vias, depositing a third conductive film on the fourth insulating layer, and patterning the third conductive film through a patterning process to form a third conductive layer pattern located on the fourth insulating layer of the second driving structure layer, as shown in Figure 21.
  • Figure 21 is a schematic diagram after forming the third conductive layer pattern of the second driving structure layer.
  • the third conductive layer pattern of the second driving structure layer may include at least: the first pole T13-2 and the second pole T14-2 of the first transistor of at least one pixel driving circuit located in the second driving structure layer to the first pole T73-2 and the second pole T74-2 of the seventh transistor.
  • Forming a fourth conductive layer pattern of the second driving structure layer includes: coating a third planar thin film on a substrate on which the aforementioned pattern is formed; patterning the third planar thin film using a patterning process to form a first planar layer of the second driving structure layer including vias; depositing a fourth conductive thin film on the first planar layer; and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern located on the first planar layer of the second driving structure layer, as shown in FIG22.
  • FIG22 is a schematic diagram after forming the fourth conductive layer pattern of the second driving structure layer.
  • the fourth conductive layer pattern of the second driving structure layer may include at least: an anode connection electrode AL2 connected to at least one pixel driving circuit located in the second driving structure layer.
  • Forming a second planarization layer pattern for the second driving structure layer may include: coating a fourth planarization film on a substrate on which the aforementioned pattern is formed, and patterning the fourth planarization film by a patterning process to form a second planarization layer of the second driving structure layer, as shown in FIG23, FIG23 being a schematic diagram after forming the second planarization layer pattern of the second driving structure layer.
  • the second planarization layer of the second driving structure layer may include a plurality of vias, including via V1 exposing the anode connection electrode of the first driving structure layer and via V2 exposing the anode connection electrode of the second driving structure layer.
  • the driving structure layer assembly is complete on the substrate.
  • the driving structure layer assembly may include multiple driving structure layers, and at least one driving structure layer may include multiple pixel driving circuits.
  • the pixel driving circuits are connected to scan signal lines, light emission signal lines, reset signal lines, first initial signal lines, second initial signal lines, data signal lines, and a first power supply line.
  • the driving structure layer may be disposed on the substrate.
  • the driving structure layer may include, sequentially disposed on the substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planarization layer, a fourth conductive layer, and a second planarization layer.
  • the semiconductor layer can be an amorphous silicon layer, a polycrystalline silicon layer, or a metal oxide layer.
  • the metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc.
  • the metal oxide layer can be a single layer, a double layer, or a multilayer.
  • the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may be single-layer structures or multi-layer composite structures, such as Mo/Cu/Mo.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.
  • the first planarization layer and the second planarization layer may be made of organic materials, such as resin.
  • a light-emitting structure layer is prepared on the driving structure layer.
  • the preparation process of the light-emitting structure layer may include the following operations.
  • forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the driving structure layer group.
  • FIG24 is a schematic diagram after forming the anode conductive layer in the light-emitting structure layer.
  • the anode conductive layer includes at least a first electrode 31 of at least one light-emitting device.
  • the first electrode may include the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device.
  • the first electrode of the first light-emitting device is located in the red sub-pixel that emits red light
  • the first electrode of the second light-emitting device may be located in the blue sub-pixel that emits blue light
  • the first electrode of the third light-emitting device may be located in the first green sub-pixel that emits green light
  • the first electrode of the fourth light-emitting device may be located in the second green sub-pixel that emits green light.
  • the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a second direction, and the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the second direction.
  • the first electrode of the first light-emitting device and the first electrode of the second light-emitting device may be alternately arranged along a first direction
  • the first electrode of the third light-emitting device and the first electrode of the fourth light-emitting device may be alternately arranged along the first direction.
  • the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device can be electrically connected to the anode connection electrode through vias that expose the anode connection electrode.
  • the shape and area of the first electrode of at least one light-emitting device may be the same or different.
  • At least one of the first electrode of the first light-emitting device, the first electrode of the second light-emitting device, the first electrode of the third light-emitting device, and the first electrode of the fourth light-emitting device may include an anode body portion and an anode connection portion connected to each other, with the anode connection portion connected to a connection electrode.
  • the first electrode of the first light-emitting device may include a first anode body portion and a first anode connecting portion connected to each other.
  • the first anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers.
  • the first anode connecting portion may be strip-shaped.
  • the first electrode of the second light-emitting device may include a second anode body portion and a second anode connecting portion connected to each other.
  • the second anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers.
  • the second anode connecting portion may be strip-shaped.
  • the first electrode of the third light-emitting device may include a third anode body portion and a third anode connecting portion connected to each other.
  • the third anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers.
  • the third anode connecting portion may be strip-shaped.
  • the first electrode of the fourth light-emitting device may include a fourth anode body portion and a fourth anode connecting portion connected to each other.
  • the fourth anode body portion may be rectangular in shape, and the corners of the rectangle may be provided with rounded chamfers.
  • the fourth anode connecting portion may be strip-shaped.
  • the anode conductive layer adopts a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can adopt a multi-layer composite structure, such as ITO/Ag/ITO.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • Forming a cathode conductive layer pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed; depositing a pixel definition film on the substrate on which the aforementioned pattern is formed; patterning the pixel definition film using a patterning process to form a pixel definition layer pattern that exposes the anode conductive layer pattern; coating an organic light-emitting material on a substrate on which the pixel definition layer pattern is formed; patterning the organic light-emitting material using a patterning process to form an organic structure layer pattern; depositing a cathode conductive film on a substrate on which the organic material layer pattern is formed; and patterning the cathode conductive film using a patterning process to form a cathode conductive layer.
  • the subsequent preparation process may include: forming an encapsulation structure layer on the cathode conductive layer.
  • the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.
  • the first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.
  • the organic structure layer may include at least an organic light-emitting layer of a light-emitting device.
  • the cathode conductive layer may include at least: a second electrode (cathode) of a plurality of light-emitting devices.
  • the cathode conductive layer in at least one light-emitting structural layer may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or the aforementioned conductive alloy materials, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Mo/Cu/Mo.
  • This disclosure also provides a display device, including: a display substrate provided in any of the foregoing embodiments.
  • the display device can be any product or component with display function, such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.
  • display function such as electronic paper, OLED panel, active-matrix organic light emitting diode (AMOLED) panel, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, etc.

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Abstract

一种显示基板和显示装置，其中，显示基板具有显示区和非显示区，显示基板包括：基底以及依次叠设在基底上的驱动结构层组和发光结构层，驱动结构层组上设置有位于显示区的多个像素驱动电路，发光结构层上设置有位于显示区的多个发光器件，发光器件与像素驱动电路电连接；驱动结构层组包括：K个沿基底依次叠设的驱动结构层，至少一个驱动结构层包括：至少一个像素驱动电路，至少一个发光器件在基底上的正投影与K个驱动结构层中的至少两个驱动结构层中的至少一个像素驱动电路在基底上的正投影至少部分交叠，位于至少一个驱动结构层中的至少一个像素驱动电路在基底上的正投影与至少两个发光器件在基底上的正投影至少部分交叠。

Description

显示基板和显示装置
本申请要求于2024年5月31日提交的、申请号为202410705272.5、发明名称为“显示基板和显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及但不限于显示技术领域，具体涉及一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本申请详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种显示基板，具有显示区和非显示区，所述显示基板包括：基底以及依次叠设在所述基底上的驱动结构层组和发光结构层，所述驱动结构层组上设置有位于所述显示区的多个像素驱动电路，所述发光结构层上设置有位于显示区的多个发光器件，所述发光器件与像素驱动电路电连接；
所述驱动结构层组包括：K个沿所述基底依次叠设的驱动结构层，至少一个驱动结构层包括：至少一个像素驱动电路，至少一个发光器件在基底上的正投影与K个驱动结构层中的至少两个驱动结构层中的至少一个像素驱动电路在基底上的正投影至少部分交叠，位于至少一个驱动结构层中的至少一个像素驱动电路在基底上的正投影与至少两个发光器件在基底上的正投影至少部分交叠，其中，K为大于或者等于2的正整数。
在示例性实施方式中，至少一个驱动结构层包括：M行N列像素驱动电路；
K个驱动结构层中的至少两个驱动结构层中的第m行第n列像素驱动电路在基底上的正投影至少部分交叠，1≤m≤M，1≤n≤N。
在示例性实施方式中，所述发光器件包括：与像素驱动电路电连接的第一电极，所述多个发光器件的第一电极阵列排布，位于同一行的相邻发光器件的第一电极所连接的像素驱动电路位于同一驱动电路层，位于同一列的相邻发光器件的第一电极所连接的像素驱动电路位于不同驱动电路层。
在示例性实施方式中，至少一个驱动结构层包括：多个阳极连接电极，多个阳极连接电极与至少一个驱动结构层中的多个像素驱动电路一一对应，所述像素驱动电路包括：至少一个晶体管，晶体管包括：有源层、栅电极、第一极和第二极；
至少一个阳极连接电极与对应的像素驱动电路以及与对应的像素驱动电路连接的发光器件电连接，所述阳极连接电极所在的膜层位于至少一个晶体管的有源层、栅电极、第一极和第二极中的至少一个结构所在的膜层远离基底的一侧。
在示例性实施方式中，K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个阳极连接电极至少部分沿第一方向延伸。
在示例性实施方式中，所述驱动结构层组还包括：多个暴露出阳极连接电极的过孔；
暴露出第r个驱动结构层中的至少一个阳极连接电极的过孔在基底上的正投影与第r+1个驱动结构层至第K个驱动结构层中的至少两个驱动结构层中的结构在基底上的正投影在基底上的正投影不存在交叠区域，1≤r≤K-1；
所述至少一个驱动结构层中的结构包括：驱动结构层中的像素驱动电路以及所述像素驱动电路所连接的信号线。
在示例性实施方式中，暴露出K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极的过孔沿所述第一方向排布。
在示例性实施方式中，至少一个阳极连接电极在基底上的正投影与所述阳极连接电极对应的像素驱动电路所连接的第一信号线在基底上的正投影不存在交叠区域；
所述第一信号线包括：第一电源线和数据信号线。
在示例性实施方式中，所述驱动结构层组还包括：K-1个保护层；
第r个保护层位于第r个驱动结构层和第r+1个驱动结构层之间，1≤r≤K-1。
在示例性实施方式中，所述至少一个驱动电路层包括：半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述像素驱动电路包括：至少一个晶体管和电容，所述电容包括：两个极板，所述像素驱动电路所连接的信号线包括：扫描信号线、复位信号线、第一初始信号线、第二初始信号线、发光信号线、数据信号线和第一电源线；
所述半导体层至少包括：至少一个晶体管的有源层；
所述第一导电层至少包括：至少一个晶体管的栅电极、电容的其中一个极板、扫描信号线、复位信号线和发光信号线；
所述第二导电层至少包括：电容的另一个极板、第一初始信号线和第二初始信号线；
所述第三导电层至少包括：至少一个晶体管的第一极和第二极、数据信号线和第一电源线；
所述第四导电层至少包括：阳极连接电极。
在示例性实施方式中，所述至少一个驱动电路层还包括：第一平坦层和第二平坦层；
所述第一平坦层位于所述第三导电层和所述第四导电层之间，所述第二平坦层位于所述第四导电层远离所述基底的一侧。
在示例性实施方式中，还包括：位于所述非显示区的K个源极驱动芯片组，至少一个源极驱动芯片组包括：至少一个源极驱动芯片；
第k个源极驱动芯片组与第k个驱动结构层中的像素驱动电路所连接的数据信号线电连接连接，1≤k≤K。
在示例性实施方式中，第r个驱动结构层中的至少一列像素驱动电路所连接的数据信号线与第r+1个驱动结构层中的至少一列像素驱动电路所连接的数据信号线电连接，1≤r≤K-1。
在示例性实施方式中，还包括：位于所述非显示区的K个栅极驱动电路；
第k个栅极驱动电路位于所述第k个驱动结构层上，且第k个栅极驱动电路与第k个驱动结构层中的像素驱动电路所连接的扫描信号线电连接连接；K个栅极驱动电路沿基底方向依次叠设，1≤k≤K。
在示例性实施方式中，至少一个栅极驱动电路与初始信号线电连接，不同栅极驱动电路连接不同初始信号线。
在示例性实施方式中，还包括：位于所述非显示区的K条第一发光电源线，至少一个像素驱动电路所连接的信号线包括：第一电源线；
第k个第一发光电源线位于所述第k个驱动结构层上，且第k条第一发光电源线与位于第k个驱动结构层中的像素驱动电路所连接的第一电源线电连接；
K条第一发光电源线中的至少两条相互电连接。
在示例性实施方式中，还包括：位于所述非显示区的K条第一驱动电源线和K条第二驱动电源线，
第k条第一驱动电源线位于所述第k个驱动结构层上，且与第k个栅极驱动电连接，第k条第二驱动电源线位于所述第k个驱动结构层上，且与第k个栅极驱动电连接；
K个驱动结构层中的至少两个驱动结构层中的第一驱动电源线相互电连接；
K个驱动结构层中的至少两个驱动结构层中的第二驱动电源线相互电连接。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图一；
图3为一种显示基板的平面结构示意图二；
图4为一种显示基板的平面结构示意图三；
图5为一种像素驱动电路的等效电路示意图；
图6为一种像素驱动电路的工作时序图；
图7A为本公开实施例提供的显示基板的结构示意图；
图7B为驱动结构层组的结构示意图；
图8为本公开实施例提供的显示基板的俯视图；
图9A为图8中的第一个驱动结构层的俯视图一；
图9B为图8中的第一个驱动结构层的俯视图二；
图10为图8中的第二个驱动结构层的俯视图；
图11为图8中的部分膜层示意图；
图12为显示基板的另一结构示意图；
图13为形成第一驱动结构层的半导体层图案后的示意图；
图14为形成第一驱动结构层的第一导电层图案后的示意图；
图15为形成第一驱动结构层的第二导电层图案后的示意图；
图16为形成第一驱动结构层的第三导电层图案后的示意图；
图17为形成第一驱动结构层的第四导电层图案后的示意图；
图18为形成第二驱动结构层的半导体层图案后的示意图；
图19为形成第二驱动结构层的第一导电层图案后的示意图；
图20为形成第二驱动结构层的第二导电层图案后的示意图；
图21为形成第二驱动结构层的第三导电层图案后的示意图；
图22为形成第二驱动结构层的第四导电层图案后的示意图；
图23为形成第二驱动结构层的第二平坦层图案后的示意图；
图24为形成发光结构层中的阳极导电层后的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，所采用的“同层设置”是指两种(或两种以上)结构通过同一次图案化工艺得以图案化而形成的结构，它们的材料可以相同或不同。例如，形成同层设置的多种结构的前驱体的材料是相同的，最终形成的材料可以相同或不同。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括像素驱动电路，像素驱动电路可以分别与扫描信号线、发光信号线和数据信号线连接。
在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
图2为一种显示基板的平面结构示意图一，图3为一种显示基板的平面结构示意图二，图4为一种显示基板的平面结构示意图三。如图2至图4所示，显示基板可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，第一子像素P1、第二子像素P2和第三子像素P3均包括像素驱动电路和发光器件。第一子像素P1、第二子像素P2和第三子像素P3中的像素驱动电路分别与扫描信号线、数据信号线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向所述发光器件输出相应的电流。第一子像素P1、第二子像素P2和第三子像素P3中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，三个子像素可以采用水平并列、竖直并列或品字方式排列，本公开在此不做限定。
在示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列、竖直并列或品字方式等排列，本公开在此不做限定。图2是以三个子像素水平采用并列排列方式为例进行说明的，图3是以三个子像素采用品字方式排列方式为例进行说明的。
在其它示例性实施方式中，像素单元可以包括四个子像素，四个子像素可以采用水平并列、竖直并列或正方形等方式排列，本公开在此不做限定。图4是以四个子像素采用正方形方式排列为例进行说明的。
在示例性实施方式中，发光器件可以包括叠设的第一极(阳极)、有机发光层和第二极(阴极)。示例性地，发光器件的阳极与像素驱动电路电连接，发光器件的阴极与第二电源线电连接。
在示例性实施方式中，发光器件L可以包括电流驱动型器件，可以采用电流型发光二极管，如微型发光二极管(Micro Light Emitting Diode，简称Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，简称Mini LED)或者有机电致发光二极管(Organic Light Emitting Diode，简称OLED)或者量子点发光二极管(Quantum Light Emitting Diode，简称QLED)。Micro LED的典型尺寸(例如长度)可以小于100μm，例如10μm至50μm。Mini LED的典型尺寸(例如长度)可以约为100μm至300μm，例如120μm至260μm。
在示例性实施方式中，有机发光层可以包括叠设的空穴注入层(Hole Injection Layer，简称HIL)、空穴传输层(Hole Transport Layer，简称HTL)、电子阻挡层(Electron Block Layer，简称EBL)、发光层(Emitting Layer，简称EML)、空穴阻挡层(Hole Block Layer，简称HBL)、电子传输层(Electron Transport Layer，简称ETL)和电子注入层(Electron Injection Layer，简称EIL)。在示例性实施方式中，所有子像素的空穴注入层可以是连接在一起的共通层，所有子像素的电子注入层可以是连接在一起的共通层，所有子像素的空穴传输层可以是连接在一起的共通层，所有子像素的电子传输层可以是连接在一起的共通层，所有子像素的空穴阻挡层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的，相邻子像素的电子阻挡层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，第一电源线VDD持续提供高电平信号，且第一电源线VDD的信号为直流信号。
在示例性实施方式中，第二电源线VSS持续提供低电平信号，且第二电源线VSS的信号为直流信号。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)、1个电容C，像素驱动电路可以分别与数据信号线Data、扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2和第一电源线VDD连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管T1的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，电容C的第一端与第一电源线VDD连接，电容C的第二端与第二节点N2连接，即电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与复位信号线Reset连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到复位信号线Reset时，第一晶体管T1将第一初始信号线INIT1的初始化电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与扫描信号线Gate连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到扫描信号线Gate时，第二晶体管T2使第三晶体管T3的控制极与第二极连通。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的大小。
第四晶体管T4的控制极与扫描信号线Gate连接，第四晶体管T4的第一极与数据信号线Data连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到扫描信号线Gate时，第四晶体管T4使数据信号线Data的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一电极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线EM时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与复位信号线Reset连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与发光器件的第一电极连接。当导通电平扫描信号施加到复位信号线Reset时，第七晶体管T7将第二初始信号线INIT2初始化电压传输到发光器件的第一电极，以使发光器件的第一电极中累积的电荷量初始化或释放发光器件的第一电极中累积的电荷量。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。扫描信号线Gate为本显示行像素驱动电路中的扫描信号线Gate，复位信号线Reset为上一显示行像素驱动电路中的扫描信号线Gate，即本显示行的复位信号线Reset与上一显示行像素驱动电路中的扫描信号线Gate为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)，关闭电压为高电平电压(例如，5V、10V或其它合适的电压)。当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其它合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其它合适的电压)。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，扫描信号线Gate、复位信号线Reset、发光信号线EM、第一初始信号线INIT1和第二初始信号线INIT2可以沿水平方向延伸，第二电源线VSS、第一电源线VDD和数据信号线Data可以沿竖直方向延伸。
在示例性实施方式中，第一初始信号线INIT1和第二初始信号线INIT2可以为同一信号线。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个电容C，7个晶体管均为P型晶体管。
在示例性实施方式中，像素驱动电路的工作过程可以包括：
第一阶段A1，称为复位阶段，复位信号线Reset的信号为低电平信号，扫描信号线Gate和发光信号线EM的信号为高电平信号。复位信号线Reset的信号为低电平信号，使第一晶体管T1和第七晶体管T7导通，第一初始信号线INIT1的信号提供至第二节点N2，对电容C进行初始化(复位)，清除电容中原有电荷，第二初始信号线INIT2的信号提供至发光器件的阳极，对发光器件的第一电极进行初始化(复位)，清除电容中原有电荷。扫描信号线Gate和发光信号线EM的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6断开，此阶段发光器件不发光。
第二阶段A2、称为数据写入阶段或者阈值补偿阶段，扫描信号线Gate的信号为低电平信号，复位信号线Reset和发光信号线EM的信号为高电平信号，数据信号线Data输出数据电压。此阶段由于电容C的第二端为低电平，因此第三晶体管T3导通。扫描信号线Gate的信号为低电平信号使第二晶体管T2和第四晶体管T4导通。第二晶体管T2和第四晶体管T4导通使得数据信号线Data输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据信号线Data输出的数据电压与第三晶体管T3的阈值电压之差充入电容C，电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据信号线Data输出的数据电压，Vth为第三晶体管T3的阈值电压。复位信号线Reset的信号为高电平信号，使第一晶体管T1和第七晶体管T7断开。发光信号线EM的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段A3、称为发光阶段，发光信号线EM的信号为低电平信号，扫描信号线Gate和复位信号线Reset的信号为高电平信号。发光信号线EM的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向发光器件的第一电极提供驱动电压，驱动发光器件发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vd-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth)2＝K*[(Vdd-Vd+|Vth|)-Vth]2＝K*(Vdd-Vd)2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据信号线Data输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
由上述电流公式的推导结果可以看出，在发光阶段，第三晶体管T3的驱动电流已经不受第三晶体管T3的阈值电压的影响，从而消除了第三晶体管T3的阈值电压对驱动电流的影响，可以保证显示产品的显示亮度均匀，提升了整个显示产品的显示效果。
显示装置中发光器件的密集度较小，使得显示装置很难实现高PPI。
图7A为本公开实施例提供的显示基板的结构示意图，图7B为驱动结构层组的结构示意图，图8为本公开实施例提供的显示基板的俯视图。如图7A、图7B和图8所示，本公开实施例提供的显示基板，具有显示区和非显示区，显示基板包括：基底10以及依次叠设在基底上的驱动结构层组20和发光结构层30，驱动结构层组20上设置有位于显示区的多个像素驱动电路，发光结构层30上设置有位于显示区的多个发光器件，发光器件与像素驱动电路电连接。驱动结构层组20包括：K个沿基底10依次叠设的驱动结构层21，至少一个驱动结构层包括：至少一个像素驱动电路，至少一个发光器件在基底上的正投影与K个驱动结构层中的至少两个驱动结构层中的至少一个像素驱动电路在基底上的正投影至少部分交叠，位于至少一个驱动结构层中的至少一个像素驱动电路在基底上的正投影与至少两个发光器件在基底上的正投影至少部分交叠，其中，K为大于或者等于2的正整数。图7A、图7B和图8是以K＝2为例进行说明的。
在示例性实施方式中，本公开通过设置驱动结构层组包括：K个沿基底依次叠设的驱动结构层，且至少一个发光器件在基底上的正投影与K个驱动结构层中的至少两个驱动结构层中的至少一个像素驱动电路在基底上的正投影至少部分交叠，位于至少一个驱动结构层中的至少一个像素驱动电路在基底上的正投影与至少两个发光器件在基底上的正投影至少部分交叠，可以实现多个像素驱动电路沿基底方式层叠设置，与多个像素驱动电路所连接的发光器件在基底上的正投影可以与多个像素驱动电路在基底上的正投影至少部分交叠，增大了发光器件的密集度，进而可以实现显示装置的高PPI。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在示例性实施方式中，位于不同驱动结构层中的像素驱动电路的结构可以相同，或者可以不同。位于不同驱动结构层中的像素驱动电路的结构可以相同可以减少显示基板所使用的掩膜版的数量可以降低制作成本。图8是以位于不同驱动结构层中的像素驱动电路的结构相同为例进行说明的。
在示例性实施方式中，如图8所示，至少一个驱动结构层可以包括：M行N列像素驱动电路；K个驱动结构层中的至少两个驱动结构层中的第m行第n列像素驱动电路在基底上的正投影至少部分交叠，1≤m≤M，1≤n≤N。
在示例性实施方式中，如图8所示，发光器件包括：与像素驱动电路电连接的第一电极31，多个发光器件的第一电极31阵列排布，位于同一行的相邻发光器件的第一电极31所连接的像素驱动电路位于同一驱动电路层，位于同一列的相邻发光器件的第一电极所连接的像素驱动电路位于不同驱动电路层。
在示例性实施方式中，至少一个驱动结构层包括：多个阳极连接电极AL，多个阳极连接电极AL与至少一个驱动结构层中的多个像素驱动电路一一对应，像素驱动电路包括：至少一个晶体管，晶体管包括：有源层、栅电极、第一极和第二极；
在示例性实施方式中，至少一个阳极连接电极AL与对应的像素驱动电路以及与对应的像素驱动电路连接的发光器件电连接，阳极连接电极AL所在的膜层位于至少一个晶体管的有源层、栅电极、第一极和第二极中的至少一个结构所在的膜层远离基底的一侧。
图9A为图8中的第一个驱动结构层的俯视图一，图9B是图8中跟的第一个驱动结构层的俯视图二，图10为图8中的第二个驱动结构层的俯视图，图9A和图9B中的AL1指的是第一个驱动结构层中的阳极连接电极，图10中的AL2指的是第二驱动结构层中的阳极连接电极。
图11为图8中的部分膜层示意图。图11中包括了第一个驱动结构层中的阳极连接电极所在的膜层和第二个驱动结构层中的阳极连接电极所在的膜层。在示例性实施方式中，如图11所示，K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极在基底上的正投影至少部分交叠。
在示例性实施方式中，如图9A至图11所示，至少一个阳极连接电极AL至少部分沿第一方向D1延伸。
在示例性实施方式中，位于第一个驱动结构层的至少一个阳极连接电极AL可以至少部分沿第二方向D2延伸。
在示例性实施方式中，如图8所示，驱动结构层组还包括：多个暴露出阳极连接电极的过孔V。
在示例性实施方式中，如图8至图11所示，暴露出第r个驱动结构层中的至少一个阳极连接电极的过孔在基底上的正投影与第r+1个驱动结构层至第K个驱动结构层中的至少两个驱动结构层中的结构在基底上的正投影在基底上的正投影不存在交叠区域，1≤r≤K-1；至少一个驱动结构层中的结构包括：驱动结构层中的像素驱动电路以及像素驱动电路所连接的信号线。图9和图11中的V1指的是暴露出第一个驱动结构层中的阳极连接电极的过孔，图10和图11中的V2指的是暴露出第二个驱动结构层中的阳极连接电极的过孔。
在示例性实施方式中，暴露出第r个驱动结构层中的至少一个阳极连接电极的过孔在基底上的正投影与第r+1个驱动结构层至第K个驱动结构层中的至少两个驱动结构层中的结构在基底上的正投影在基底上的正投影不存在交叠区域可以保证位于发光结构层中的发光器件的第一电极可以通过暴露出第r个驱动结构层中的至少一个阳极连接电极的过孔可以准确无误的与阳极连接电极电连接。
在示例性实施方式中，如图11所示，阳极连接电极是通过过孔V与第六晶体管的第二极(也是第七晶体管的第二极)所在的膜层电连接。
在示例性实施方式中，阳极连接电极可以作为第六晶体管的第二极(也是第七晶体管的第二极)通过过孔与第六晶体管和第七晶体管的有源层所在的膜层电连接，本公开对此不做任何限定。
在示例性实施例方式中，第一个驱动结构层至第K-1个驱动结构层中的阳极连接电极至少部分可以设置在空白区域，其中，空白区域指的是像素驱动电路的任一结构以及像素驱动电路所连接的信号在基底上的正投影均不存在交叠区域的区域。
在示例性实施方式中，第K个驱动结构层中的阳极连接电极可以设置在任一位置处，可以不必部分区域设置空白区域。
在示例性实施方式中，如图9A、图9B和图10所示，像素驱动电路所连接的信号线可以包括：第一初始信号线INIT1、第二初始信号线INIT2、发光信号线EM、扫描信号线Gate、复位信号线Reset、数据信号线Data和第一电源线VDD。
在示例性实施方式中，如图11所示，暴露出K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极的过孔沿第一方向D1排布。在示例性实施方式中，至少一个过孔V1和至少一个过孔V2沿第一方向D1排布，其中沿第一方向D1排布的过孔V1所暴露出的阳极连接电极所连接的像素驱动电路在基底上的正投影与过孔V2所暴露出的阳极连接电极所连接的像素驱动电路在基底上的正投影至少部分交叠。
在示例性实施方式中，如图9和图10所示，至少一个阳极连接电极AL在基底上的正投影与阳极连接电极AL对应的像素驱动电路所连接的第一信号线在基底上的正投影不存在交叠区域；第一信号线包括：第一电源线VDD和数据信号线Data。
在示例性实施方式中，图12为显示基板的另一结构示意图，驱动结构层组20还包括：K-1个保护层22。第r个保护层位于第r个驱动结构层和第r+1个驱动结构层之间，1≤r≤K-1。
在示例性实施方式中，保护层可以为单层结构，或者可以为多层结构。
在示例性实施方式中，保护层的制作材料可以为无机材料，氧化硅和氮化硅，或者还可为有机材料，本公开对此不做任何限定。
在示例性实施方式中，至少一个驱动电路层包括：半导体层、第一导电层、第二导电层、第三导电层和第四导电层，像素驱动电路包括：至少一个晶体管和电容，电容包括：两个极板，像素驱动电路所连接的信号线包括：扫描信号线、复位信号线、第一初始信号线、第二初始信号线、发光信号线、数据信号线和第一电源线；
半导体层至少包括：至少一个晶体管的有源层；
第一导电层至少包括：至少一个晶体管的栅电极、电容的其中一个极板、扫描信号线、复位信号线和发光信号线；
第二导电层至少包括：电容的另一个极板、第一初始信号线和第二初始信号线；
第三导电层至少包括：至少一个晶体管的第一极和第二极、数据信号线和第一电源线；
第四导电层至少包括：阳极连接电极。
在示例性实施方式中，不同驱动电路层的膜层结构可以相同，或者可以不同，本公开对此不做任何限定。
在示例性实施方式中，至少一个驱动电路层还包括：第一平坦层和第二平坦层；其中，第一平坦层位于第三导电层和第四导电层之间，第二平坦层位于第四导电层远离基底的一侧。
在示例性实施方式中，暴露出阳极连接电极的过孔的至少部分开设在第二平坦层上。
在示例性实施方式中，显示区的侧面可以包括：第一侧、第二侧、第三侧和第四侧，其中，第一侧和第二侧相对设置，第三侧和第四侧相对设置。
在示例性实施方式中，显示基板还可以包括：位于非显示区的K个源极驱动芯片组，至少一个源极驱动芯片组包括：至少一个源极驱动芯片；第k个源极驱动芯片组与第k个驱动结构层中的像素驱动电路所连接的数据信号线电连接连接，1≤k≤K。示例性地，第一个源极驱动芯片组与第一个驱动结构层中的像素驱动电路所连接的数据信号线电连接连接，第二个源极驱动芯片组与第二个驱动结构层中的像素驱动电路所连接的数据信号线电连接连接，依次类推。
在示例性实施方式中，显示基板还可以包括：一个源极驱动芯片组，至少一个驱动结构层中的至少一列像素驱动电路所连接的数据信号线与源极驱动芯片组电连接，第r个驱动结构层中的至少一列像素驱动电路所连接的数据信号线与第r+1个驱动结构层中的至少一列像素驱动电路所连接的数据信号线电连接，1≤r≤K-1。
在示例性实施方式中，第r个驱动结构层中的至少一列像素驱动电路所连接的数据信号线可以通过位于非显示区的过孔与第r+1个驱动结构层中的至少一列像素驱动电路所连接的数据信号线电连接，示例性地，过孔可以位于显示区的第三侧或者第四侧。
在示例性实施方式中，源极驱动芯片组可以位于显示区的第三侧或者第四侧。
在示例性实施方式中，显示基板还包括：位于非显示区的K个栅极驱动电路。第k个栅极驱动电路位于第k个驱动结构层上，且第k个栅极驱动电路与第k个驱动结构层中的像素驱动电路所连接的扫描信号线电连接连接；K个栅极驱动电路沿基底方向依次叠设，1≤k≤K。示例性地，第一个栅极驱动电路与第一个驱动结构层中的像素驱动电路所连接的扫描信号线电连接连接，第二个栅极驱动电路组与第二个驱动结构层中的像素驱动电路所连接的扫描信号线电电连接。
在示例性实施方式中，栅极驱动电路可以位于显示区的第一侧和第二侧中的至少一侧。
在示例性实施方式中，至少一个栅极驱动电路与初始信号线电连接，不同栅极驱动电路连接不同初始信号线。
在示例性实施方式中，K个栅极驱动电路中的至少两个栅极驱动电路的输出信号的时间相同，或者可以不同，即不同驱动结构层中的像素驱动电路的时序可以一起被调控，或者可以单独调控。
在示例性实施方式中，显示基板还包括：位于非显示区的K条第一发光电源线，至少一个像素驱动电路所连接的信号线包括：第一电源线；第k个第一发光电源线位于第k个驱动结构层上，且第k条第一发光电源线与位于第k个驱动结构层中的像素驱动电路所连接的第一电源线电连接。K条第一发光电源线中的至少两条相互电连接。
在示例性实施方式中，显示基板还包括：位于非显示区的第二发光电源线，至少一个发光器件的第二极通过过孔与第二发光电源线电连接。
在示例性实施方式中，第二发光电源线可以位于至少一个驱动结构层中。
在示例性实施方式中，显示基板还包括：位于非显示区的K条第一驱动电源线和K条第二驱动电源线，第k条第一驱动电源线位于第k个驱动结构层上，且与第k个栅极驱动电连接，第k条第二驱动电源线位于第k个驱动结构层上，且与第k个栅极驱动电连接。
在示例性实施方式中，K个驱动结构层中的至少两个驱动结构层中的第一驱动电源线相互电连接，示例性地，K个驱动结构层中的至少两个驱动结构层中的第一驱动电源线可以通过过孔相互电连接。
在示例性实施方式中，K个驱动结构层中的至少两个驱动结构层中的第二驱动电源线相互电连接，示例性地，K个驱动结构层中的至少两个驱动结构层中的第二驱动电源线可以通过过孔相互电连接。
在示例性实施方式中，发光结构层可以包括阳极、像素定义层、有机发光层和阴极。阳极通过过孔与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，显示基板还可以包括隔离柱。
在示例性实施方式中，有机发光可以包括发光层(EML)以及如下任意一层或多层：空穴注入层HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层中的一层或多层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是隔离的。
在示例性实施方式中，显示基板还可以包括其他膜层，例如：封装结构层和触控结构层，本公开在此不做限定。
在示例性实施方式中，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，触控结构层可以包括设置在封装结构层上的第一触控绝缘层、设置在第一触控绝缘层上的第一触控金属层、覆盖第一触控金属层的第二触控绝缘层、设置在第二触控绝缘层上的第二触控金属层和覆盖第二触控金属层的触控保护层，第一触控金属层可以包括多个桥接电极，第二触控金属层可以包括多个第一触控电极和第二触控电极，第一触控电极或第二触控电极可以通过过孔与桥接电极连接。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
下面通过图8显示基板的制备过程进行示例性说明，图8是以驱动结构层组包括：两个驱动结构层，且两个驱动结构层的膜层结构相同为例进行说明的。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
(1)形成第一驱动结构层的半导体层图案。在示例性实施方式中，形成第一驱动结构层的半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成第一驱动结构层的覆盖基底的第一绝缘层以及位于第一绝缘层上的半导体层图案，如图13所示，图13为形成第一驱动结构层的半导体层图案后的示意图。
在示例性实施方式中，如图13所示，第一驱动结构层的半导体层图案至少可以包括：位于第一驱动结构层的至少一个像素驱动电路的第一晶体管的有源图案T11-1至第七晶体管的有源图案T71-1。
(2)形成第一驱动结构层的第一导电层图案。在示例性实施方式中，形成第一驱动结构层的第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成第一驱动结构层的覆盖半导体层图案的第二绝缘层以及设置在第二绝缘层上的第一导电层图案，如图14所示，图14为形成第一驱动结构层的第一导电层图案后的示意图。
在示例性实施方式中，如图14所示，第一驱动结构层的第一导电层图案至少可以包括：位于第一驱动结构层的至少一个像素驱动电路的第一晶体管的栅电极T21-1至第七晶体管的栅电极T72-1和电容的第一极板C1-1、以及位于第一驱动结构层的至少一个像素驱动电路所连接的复位信号线Reset-1、发光信号线EM-1和扫描信号线Gate-1。
(3)形成第一驱动结构层的第二导电层图案，包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，通过图案化工艺对第三绝缘薄膜和第二导电薄膜进行图案化，形成第一驱动结构层的第三绝缘层以及位于第三绝缘层上的第二导电层图案，如图15所示，图15为形成第一驱动结构层的第二导电层图案后的示意图。
在示例性实施方式中，如图15所示，第二导电层图案至少可以包括：位于第一驱动结构层的至少一个像素驱动电路的电容的第二极板C2-1以及与第一驱动结构层的至少一个像素驱动电路连接的第一初始信号线INIT1-1和第二初始信号线INIT2-1。
(4)形成第一驱动结构层的第三导电层图案，包括：在形成前述图案的基底上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成包括多个过孔的第四绝缘层，在第四绝缘层上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，形成位于第一驱动结构层的第四绝缘层上的第三导电层图案，如图16所示，图16为形成第一驱动结构层的第三导电层图案后的示意图。
在示例性实施方式中，如图16所示，第一驱动结构层的第三导电层图案至少可以包括：位于第一驱动结构层的至少一个像素驱动电路的第一晶体管的第一极T13-1和第二极T14-1至第七晶体管的第一极T73-1和第二极T74-2。
(5)形成第一驱动结构层的第四导电层图案，包括：在形成前述图案的基底上，涂覆第一平坦薄膜，通过图案化工艺对第一平坦薄膜进行图案化，形成包括过孔的第一平坦层，在第一平坦层上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，形成位于第一驱动结构层的第一平坦层上的第四导电层图案，如图17所示，图17为形成第一驱动结构层的第四导电层图案后的示意图。
在示例性实施方式中，如图17所示，第一驱动结构层的第四导电层图案至少可以包括：位于第一驱动结构层的至少一个像素驱动电路连接的阳极连接电极AL1。
(6)形成第二驱动结构层的半导体层图案。在示例性实施方式中，形成第二驱动结构层的半导体层图案可以包括：在形成前述图案的基底上涂覆第二平坦薄膜，依次沉积第五绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成第二驱动结构层的第一绝缘层以及位于第一绝缘层上的半导体层图案，如图18所示，图18为形成第二驱动结构层的半导体层图案后的示意图。
在示例性实施方式中，如图18所示，第二驱动结构层的半导体层图案至少可以包括：位于第二驱动结构层的至少一个像素驱动电路的第一晶体管的有源图案T11-2至第七晶体管的有源图案T71-2。
(7)形成第二驱动结构层的第一导电层图案。在示例性实施方式中，形成第二驱动结构层的第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第六绝缘薄膜和第五导电薄膜，通过图案化工艺对第五导电薄膜进行图案化，形成第二驱动结构层的覆盖半导体层图案的第二绝缘层以及设置在第二绝缘层上的第一导电层图案，如图19所示，图19为形成第二驱动结构层的第一导电层图案后的示意图。
在示例性实施方式中，如图19所示，第二驱动结构层的第一导电层图案至少可以包括：位于第二驱动结构层的至少一个像素驱动电路的第一晶体管的栅电极T21-2至第七晶体管的栅电极T72-2和电容的第一极板C1-2、以及位于第二驱动结构层的至少一个像素驱动电路所连接的复位信号线Reset-2、发光信号线EM-2和扫描信号线Gate-2。
(8)形成第二驱动结构层的第二导电层图案，包括：在形成前述图案的基底上，依次沉积第七绝缘薄膜和第六导电薄膜，通过图案化工艺对第七绝缘薄膜和第六导电薄膜进行图案化，形成第二驱动结构层的第三绝缘层以及位于第三绝缘层上的第二导电层图案，如图20所示，图20为形成第二驱动结构层的第二导电层图案后的示意图。
在示例性实施方式中，如图20所示，第二驱动结构层的第二导电层图案至少可以包括：位于第二驱动结构层的至少一个像素驱动电路的电容的第二极板C2-2以及与第二驱动结构层的至少一个像素驱动电路连接的第一初始信号线INIT1-2和第二初始信号线INIT2-2。
(9)形成第二驱动结构层的第三导电层图案，包括：在形成前述图案的基底上，沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成包括多个过孔的第四绝缘层，在第四绝缘层上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，形成位于第二驱动结构层的第四绝缘层上的第三导电层图案，如图21所示，图21为形成第二驱动结构层的第三导电层图案后的示意图。
在示例性实施方式中，如图21所示，第二驱动结构层的第三导电层图案至少可以包括：位于第二驱动结构层的至少一个像素驱动电路的第一晶体管的第一极T13-2和第二极T14-2至第七晶体管的第一极T73-2和第二极T74-2。
(10)形成第二驱动结构层的第四导电层图案，包括：在形成前述图案的基底上，涂覆第三平坦薄膜，通过图案化工艺对第三平坦薄膜进行图案化，形成包括过孔的第二驱动结构层的第一平坦层，在第一平坦层上沉积第四导电薄膜，通过图案化工艺对第四导电薄膜进行图案化，形成位于第二驱动结构层的第一平坦层上的第四导电层图案，如图22所示，图22为形成第二驱动结构层的第四导电层图案后的示意图。
在示例性实施方式中，如图22所示，第二驱动结构层的第四导电层图案至少可以包括：位于第二驱动结构层的至少一个像素驱动电路连接的阳极连接电极AL2。
(11)形成第二驱动结构层的第二平坦层图案。在示例性实施方式中，形成第二驱动结构层的第二平坦层图案可以包括：在形成前述图案的基底上涂覆第四平坦薄膜，通过图案化工艺对第四平坦薄膜进行图案化，形成第二驱动结构层的第二平坦层，如图23所示，图23为形成第二驱动结构层的第二平坦层图案后的示意图。
在示例性实施方式中，如图23所示，第二驱动结构层的第二平坦层可以包括多个过孔，暴露出第一驱动结构层的阳极连接电极的过孔V1和暴露出第二驱动结构层的阳极连接电极的过孔V2。
至此，在基底上制备完成驱动结构层组。在平行于显示基板的平面内，驱动结构层组可以包括多个驱动结构层，至少一个驱动结构层可以包括多个像素驱动电路，像素驱动电路与扫描信号线、发光信号线、复位信号线、第一初始信号线、第二初始信号线、数据信号线和第一电源线连接。驱动结构层可以设置在基底上。驱动结构层可以包括在基底上依次设置的第一绝缘层、半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第三导电层、第一平坦层、第四导电层和第二平坦层。
在示例性实施方式中，半导体层可以为可以为非晶硅层、多晶硅层或者金属氧化物层。其中，金属氧化物层可以采用包含铟和锡的氧化物、包含钨和铟的氧化物、包含钨和铟和锌的氧化物、包含钛和铟的氧化物、包含钛和铟和锡的氧化物、包含铟和锌的氧化物、包含硅和铟和锡的氧化物或者包含铟或镓和锌的氧化物。金属氧化物层可以单层，或者可以是双层，或者可以是多层。
在示例性实施方式中，第一导电层、第二导电层、第三导电层和第四导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。
在示例性实施方式中，第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，制备完成驱动结构层后，在驱动结构层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
(12)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置驱动结构层组上的阳极导电层。如图24所示，图24为形成发光结构层中的阳极导电层后的示意图。
在示例性实施方式中，阳极导电层至少包括至少一个发光器件的第一电极31。
在示例性实施方式中，第一电极可以包括第一发光器件的第一电极、第二发光器件的第一电极、第三发光器件的第一电极和第四发光器件的第一电极，第一发光器件的第一电极位于出射红色光线的红色子像素，第二发光器件的第一电极可以位于出射蓝色光线的蓝色子像素，第三发光器件的第一电极可以位于出射绿色光线的第一绿色子像素，第四发光器件的第一电极可以位于出射绿色光线的第二绿色子像素。
在示例性实施方式中，第一发光器件的第一电极和第二发光器件的第一电极可以沿着第二方向交替设置，第三发光器件的第一电极和第四发光器件的第一电极可以沿着第二方向交替设置。或者，第一发光器件的第一电极和第二发光器件的第一电极可以沿着第一方向交替设置，第三发光器件的第一电极和第四发光器件的第一电极可以沿着第一方向交替设置。
在示例性实施方式中，第一发光器件的第一电极、第二发光器件的第一电极、第三发光器件的第一电极和第四发光器件的第一电极可以分别通过暴露出阳极连接电极的过孔与阳极连接电极电连接。
在示例性实施方式中，至少一个发光器件的第一电极的形状和面积可以相同，或者可以不同。
在示例性实施方式中，第一发光器件的第一电极、第二发光器件的第一电极、第三发光器件的第一电极和第四发光器件的第一电极中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极连接部与连接电极连接。
在示例性实施方式中，第一发光器件的第一电极可以包括相互连接的第一阳极主体部和第一阳极连接部，第一阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第一阳极连接部的形状可以为条形状。在示例性实施方式中，第二发光器件的第一电极可以包括相互连接的第二阳极主体部和第二阳极连接部，第二阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第二阳极连接部的形状可以为条形状。在示例性实施方式中，第三发光器件的第一电极可以包括相互连接的第三阳极主体部和第三阳极连接部，第三阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第三阳极连接部的形状可以为条形状。在示例性实施方式中，第四发光器件的第一电极可以包括相互连接的第四阳极主体部和第四阳极连接部，第四阳极主体部的形状可以为矩形状，矩形状的角部可以设置圆弧状的倒角，第四阳极连接部的形状可以为条形状。
在示例性实施方式中，阳极导电层采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
(13)形成阴极导电层图案。在示例性实施方式中，形成阴极导电层可以包括：在形成前述图案的基底上，涂覆像素定义薄膜，在形成前述图案的基底上，沉积像素定义薄膜，通过图案化工艺对像素定义薄膜进行图案化，形成暴露出阳极导电层图案的像素定义层图案，在形成有像素定义层图案的基底上，涂覆有机发光材料，通过图案化工艺对有机发光材料进行图案化，形成有机结构层图案，在形成有机材料层图案的基底上，沉积阴极导电薄膜，通过图案化工艺对阴极导电薄膜进行图案化，形成阴极导电层。
在示例性实施方式中，后续制备流程可以包括：在阴极导电层上形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
在示例性实施方式中，有机结构层至少可以包括：发光器件的有机发光层。
在示例性实施方式中，阴极导电层至少可以包括：多个发光器件的第二电极(阴极)。
在示例性实施方式中，至少一个发光结构层中的阴极导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或更多种，或上述导电的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。
本公开还提供了一种显示装置，包括：前述任一个实施例提供的显示基板。
在示例性实施方式中，显示装置可以为：电子纸、OLED面板、有源矩阵有机发光二极管(active-matrix organic light emitting diode，简称AMOLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (19)

  1. 一种显示基板，具有显示区和非显示区，所述显示基板包括：基底以及依次叠设在所述基底上的驱动结构层组和发光结构层，所述驱动结构层组上设置有位于所述显示区的多个像素驱动电路，所述发光结构层上设置有位于显示区的多个发光器件，所述发光器件与像素驱动电路电连接；
    所述驱动结构层组包括：K个沿所述基底依次叠设的驱动结构层，至少一个驱动结构层包括：至少一个像素驱动电路，至少一个发光器件在基底上的正投影与K个驱动结构层中的至少两个驱动结构层中的至少一个像素驱动电路在基底上的正投影至少部分交叠，位于至少一个驱动结构层中的至少一个像素驱动电路在基底上的正投影与至少两个发光器件在基底上的正投影至少部分交叠，其中，K为大于或者等于2的正整数。
  2. 根据权利要求1所述的显示基板，其中，至少一个驱动结构层包括：M行N列像素驱动电路；
    K个驱动结构层中的至少两个驱动结构层中的第m行第n列像素驱动电路在基底上的正投影至少部分交叠，1≤m≤M，1≤n≤N。
  3. 根据权利要求2所述的显示基板，其中，所述发光器件包括：与像素驱动电路电连接的第一电极，所述多个发光器件的第一电极阵列排布，位于同一行的相邻发光器件的第一电极所连接的像素驱动电路位于同一驱动电路层，位于同一列的相邻发光器件的第一电极所连接的像素驱动电路位于不同驱动电路层。
  4. 根据权利要求3所述的显示基板，其中，至少一个驱动结构层包括：多个阳极连接电极，多个阳极连接电极与至少一个驱动结构层中的多个像素驱动电路一一对应，所述像素驱动电路包括：至少一个晶体管，晶体管包括：有源层、栅电极、第一极和第二极；
    至少一个阳极连接电极与对应的像素驱动电路以及与对应的像素驱动电路连接的发光器件电连接，所述阳极连接电极所在的膜层位于至少一个晶体管的有源层、栅电极、第一极和第二极中的至少一个结构所在的膜层远离基底的一侧。
  5. 根据权利要求4所述的显示基板，其中，K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极在基底上的正投影至少部分交叠。
  6. 根据权利要求4或5所述的显示基板，其中，至少一个阳极连接电极至少部分沿第一方向延伸。
  7. 根据权利要求6所述的显示基板，其中，所述驱动结构层组还包括：多个暴露出阳极连接电极的过孔；
    暴露出第r个驱动结构层中的至少一个阳极连接电极的过孔在基底上的正投影与第r+1个驱动结构层至第K个驱动结构层中的至少两个驱动结构层中的结构在基底上的正投影在基底上的正投影不存在交叠区域，1≤r≤K-1；
    所述至少一个驱动结构层中的结构包括：驱动结构层中的像素驱动电路以及所述像素驱动电路所连接的信号线。
  8. 根据权利要求7所述的显示基板，其中，暴露出K个驱动结构层中的相邻两个驱动结构层中的第m行第n列像素驱动电路对应的阳极连接电极的过孔沿所述第一方向排布。
  9. 根据权利要求7所述的显示基板，其中，至少一个阳极连接电极在基底上的正投影与所述阳极连接电极对应的像素驱动电路所连接的第一信号线在基底上的正投影不存在交叠区域；
    所述第一信号线包括：第一电源线和数据信号线。
  10. 根据权利要求1所述的显示基板，其中，所述驱动结构层组还包括：K-1个保护层；
    第r个保护层位于第r个驱动结构层和第r+1个驱动结构层之间，1≤r≤K-1。
  11. 根据权利要求7所述的显示基板，其中，所述至少一个驱动电路层包括：半导体层、第一导电层、第二导电层、第三导电层和第四导电层，所述像素驱动电路包括：至少一个晶体管和电容，所述电容包括：两个极板，所述像素驱动电路所连接的信号线包括：扫描信号线、复位信号线、第一初始信号线、第二初始信号线、发光信号线、数据信号线和第一电源线；
    所述半导体层至少包括：至少一个晶体管的有源层；
    所述第一导电层至少包括：至少一个晶体管的栅电极、电容的其中一个极板、扫描信号线、复位信号线和发光信号线；
    所述第二导电层至少包括：电容的另一个极板、第一初始信号线和第二初始信号线；
    所述第三导电层至少包括：至少一个晶体管的第一极和第二极、数据信号线和第一电源线；
    所述第四导电层至少包括：阳极连接电极。
  12. 根据权利要求11所述的显示基板，其中，所述至少一个驱动电路层还包括：第一平坦层和第二平坦层；
    所述第一平坦层位于所述第三导电层和所述第四导电层之间，所述第二平坦层位于所述第四导电层远离所述基底的一侧。
  13. 根据权利要求11所述的显示基板，还包括：位于所述非显示区的K个源极驱动芯片组，至少一个源极驱动芯片组包括：至少一个源极驱动芯片；
    第k个源极驱动芯片组与第k个驱动结构层中的像素驱动电路所连接的数据信号线电连接连接，1≤k≤K。
  14. 根据权利要求11所述的显示基板，其中，第r个驱动结构层中的至少一列像素驱动电路所连接的数据信号线与第r+1个驱动结构层中的至少一列像素驱动电路所连接的数据信号线电连接，1≤r≤K-1。
  15. 根据权利要求11所述的显示基板，还包括：位于所述非显示区的K个栅极驱动电路；
    第k个栅极驱动电路位于所述第k个驱动结构层上，且第k个栅极驱动电路与第k个驱动结构层中的像素驱动电路所连接的扫描信号线电连接连接；K个栅极驱动电路沿基底方向依次叠设，1≤k≤K。
  16. 根据权利要求15所述的显示基板，其中，至少一个栅极驱动电路与初始信号线电连接，不同栅极驱动电路连接不同初始信号线。
  17. 根据权利要求11所述的显示基板，还包括：位于所述非显示区的K条第一发光电源线，至少一个像素驱动电路所连接的信号线包括：第一电源线；
    第k个第一发光电源线位于所述第k个驱动结构层上，且第k条第一发光电源线与位于第k个驱动结构层中的像素驱动电路所连接的第一电源线电连接；
    K条第一发光电源线中的至少两条相互电连接。
  18. 根据权利要求11所述的显示基板，还包括：位于所述非显示区的K条第一驱动电源线和K条第二驱动电源线，
    第k条第一驱动电源线位于所述第k个驱动结构层上，且与第k个栅极驱动电连接，第k条第二驱动电源线位于所述第k个驱动结构层上，且与第k个栅极驱动电连接；
    K个驱动结构层中的至少两个驱动结构层中的第一驱动电源线相互电连接；
    K个驱动结构层中的至少两个驱动结构层中的第二驱动电源线相互电连接。
  19. 一种显示装置，包括：如权利要求1至18任一项所述的显示基板。
PCT/CN2025/089325 2024-05-31 2025-04-16 显示基板和显示装置 Pending WO2025246712A1 (zh)

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