WO2025231968A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置

Info

Publication number
WO2025231968A1
WO2025231968A1 PCT/CN2024/100242 CN2024100242W WO2025231968A1 WO 2025231968 A1 WO2025231968 A1 WO 2025231968A1 CN 2024100242 W CN2024100242 W CN 2024100242W WO 2025231968 A1 WO2025231968 A1 WO 2025231968A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
line
voltage signal
row
display panel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/100242
Other languages
English (en)
French (fr)
Other versions
WO2025231968A9 (zh
Inventor
于子阳
邱海军
胡明
郑海
王本莲
唐国强
孙阔
何庆
王梦奇
刘庭良
徐元杰
青海刚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202480001180.7A priority Critical patent/CN121312303A/zh
Publication of WO2025231968A1 publication Critical patent/WO2025231968A1/zh
Publication of WO2025231968A9 publication Critical patent/WO2025231968A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • This disclosure relates to the field of display technology, and more particularly to a display panel and display device.
  • OLED organic light-emitting diode
  • OLED display devices include multiple sub-pixels, each of which includes a pixel circuit and a light-emitting device.
  • the pixel circuit drives the light-emitting device to emit light, thereby realizing the display.
  • a display panel having a display area and a peripheral area surrounding the display area; the peripheral area includes a first sub-area and a second sub-area, the first sub-area and the second sub-area being located on opposite sides of the display area in a first direction.
  • the display panel includes: a substrate; at least two conductive layers stacked on one side of the substrate; at least one first signal line, at least a portion of which extends along the first direction within the display area; the first signal line includes at least two signal sub-lines connected sequentially, any two adjacent signal sub-lines being located in different conductive layers of the at least two conductive layers.
  • the display panel includes a plurality of sub-pixels arranged in an array, the plurality of sub-pixels including at least one row of first edge sub-pixels, the at least one row of first edge sub-pixels being closer to the first sub-area of the peripheral area than other rows of sub-pixels; the connection point of two adjacent signal sub-lines is located in the area where the at least one row of first edge sub-pixels is located.
  • the at least one first signal line includes at least one first data line, the first data line including a first main data line, a first adapter cable, and a second adapter cable located in the display area and connected in sequence, the second adapter cable including at least two sub-adapter cables connected in sequence, the first main data line, the first adapter cable, and the first data line being the first ...
  • At least two sub-connectors serve as signal sub-lines; the first data main line and the second connector extend along the first direction, with the first data main line being farther from the centerline of the display panel along the first direction compared to the second connector.
  • the first connector extends along a second direction, which intersects the first direction.
  • the second adapter line includes a first sub-adapter line and a second sub-adapter line connected sequentially in the first direction, wherein the first sub-adapter line is closer to the first sub-region than the second sub-adapter line; the connection point of the first sub-adapter line and the second sub-adapter line is located in the region where the at least one row of first edge sub-pixels is located.
  • the second adapter line includes a first sub-adapter line, a second sub-adapter line, a third sub-adapter line, and a fourth sub-adapter line connected sequentially in the first direction, wherein the first sub-adapter line is closer to the first sub-region than the second sub-adapter line; the connection point of the first sub-adapter line and the second sub-adapter line is located in the region where the at least one row of first edge sub-pixels is located; and/or, the connection point of the second sub-adapter line and the third sub-adapter line is located in the region where the at least one row of first edge sub-pixels is located; and/or, the connection point of the third sub-adapter line and the fourth sub-adapter line is located in the region where the at least one row of first edge sub-pixels is located.
  • the display panel includes at least one row of first edge anodes, and the connection point of the first sub-adapter cable and the second sub-adapter cable is covered by the at least one row of first edge anodes.
  • the display panel further includes: at least one first fan-out trace located in a first sub-region of the peripheral area, wherein the first fan-out trace is connected to a sub-adapter wire of a second adapter wire of the first data line; wherein the first fan-out trace and the connected sub-adapter wire are located in different conductive layers.
  • the display panel further includes: at least one second data line extending along the first direction; the at least one first data line being farther from the centerline of the display panel along the first direction than the at least one second data line; at least one second fan-out trace located in a first sub-area of the peripheral area, the second fan-out trace being connected to the second data line; wherein, the second adapter line is located between two adjacent second data lines, and a first voltage signal line is further disposed between the two adjacent second data lines, the second adapter line and the first voltage signal line being spaced apart in the first direction.
  • a first voltage signal line is provided between two adjacent first data main lines, and there are at least two first voltage signal lines of unequal lengths, wherein the length of the first voltage signal line between two adjacent first data main lines is greater than the length of the first voltage signal line between two adjacent second data lines.
  • the at least one first signal line includes at least one first voltage signal line, the first voltage signal line including a first voltage signal sub-line and a second voltage signal sub-line connected sequentially along the first direction, the first voltage signal sub-line being closer to the first sub-region than the second voltage signal sub-line; the first voltage signal sub-line Both the first voltage signal sub-line and the second voltage signal sub-line serve as signal sub-lines; wherein the first voltage signal sub-line and the second voltage signal sub-line are located in different conductive layers, and the connection point of the first voltage signal sub-line and the second voltage signal sub-line is located in the region where the at least one row of first edge sub-pixels is located.
  • the display panel includes at least one row of first edge anodes, and the connection point of the first voltage signal sub-line and the second voltage signal sub-line is covered by the at least one row of first edge anodes.
  • the display panel further includes: a voltage signal first bus, disposed in a first sub-region of the peripheral area, wherein a voltage signal first sub-line of the first voltage signal line is connected to the voltage signal first bus; wherein the voltage signal first bus and the voltage signal first sub-line are located in the same conductive layer.
  • the first voltage signal line further includes a third voltage signal sub-line and a fourth voltage signal sub-line connected sequentially along the first direction, the third voltage signal sub-line being connected to the second voltage signal sub-line; both the third and fourth voltage signal sub-lines serve as signal sub-lines; the plurality of sub-pixels include at least one row of second edge sub-pixels, the at least one row of second edge sub-pixels being closer to the second sub-region of the peripheral region than other rows of sub-pixels.
  • connection point of the third voltage signal sub-line and the second voltage signal sub-line is located in the region where the at least one row of second edge sub-pixels is located; or; the connection point of the third voltage signal sub-line and the second voltage signal sub-line is located in the region where the at least one row of second edge sub-pixels is located, and the connection point of the third voltage signal sub-line and the fourth voltage signal sub-line is located in the region where the at least one row of second edge sub-pixels is located.
  • the display panel includes a plurality of anodes arranged in an array, the plurality of anodes including at least one row of second edge anodes, the at least one row of second edge anodes being closer to the second sub-region than other rows of anodes; the region where the at least one row of second edge sub-pixels is located includes the region where the at least one row of second edge anodes is located, and the connection point of the third voltage signal sub-line and the fourth voltage signal sub-line is covered by the at least one row of second edge anodes.
  • the display panel further includes: a first horizontal voltage signal line extending along a second direction, the first horizontal voltage signal line being located in the region where the at least one row of second edge sub-pixels is located, and being connected to the third voltage signal sub-line.
  • the display panel further includes a second voltage signal bus disposed in a second sub-area of the peripheral area, and a fourth voltage signal sub-line connected to the second voltage signal bus; the first voltage signal sub-line and the third voltage signal sub-line are located in the same conductive layer, and the second voltage signal bus, the second voltage signal sub-line, and the fourth voltage signal sub-line are located in another conductive layer.
  • a display device including a display panel as described in any of the preceding aspects.
  • Figure 1 is a structural diagram of a display panel according to some embodiments.
  • Figure 2 is another structural diagram of a display panel according to some embodiments.
  • Figure 4 is another structural diagram of a display panel according to some embodiments.
  • Figure 5 is another structural diagram of a display panel according to some embodiments.
  • Figure 6 is another structural diagram of a display panel according to some embodiments.
  • Figure 7 is another structural diagram of a display panel according to some embodiments.
  • Figure 9 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 10 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 11A is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 11B is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 11C is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 12 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 13 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 14 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 15 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 16 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 17A is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 17B is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 17C is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 18A is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 18B is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 19 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 20 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 21 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 22A is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 22B is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 23 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 24 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 25 is a diagram of another film layer arrangement in a display panel according to some embodiments.
  • Figure 26 is a structural diagram of a display device according to some embodiments.
  • first and second are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of that feature.
  • a plurality of means two or more.
  • Coupled and “connected,” and their derivative expressions, may be used.
  • the term “connected” should be interpreted broadly; for example, a “connection” can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.
  • the term “coupled,” for example, indicates that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).
  • parallel includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°
  • equal includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
  • a layer or element when referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
  • ESD Electro-Static Discharge
  • the display panel 1000 includes a display area AA (Active Area, abbreviated as AA area; also referred to as effective display area) and a peripheral area BB located on at least one side of the display area AA.
  • the display panel 1000 may be, for example, an Organic Light-Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diodes (QLED) display panel, or a Mini Light Emitting Diodes (MLED) display panel, etc.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • MLED Mini Light Emitting Diodes
  • the display area AA of the display panel 1000 is provided with multiple sub-pixels P.
  • the multiple sub-pixels P are arranged in a matrix form as an example.
  • the multiple sub-pixels P are arranged in N rows and M columns.
  • the sub-pixels P arranged in a row along the second direction X are called a row of sub-pixels P
  • the sub-pixels P arranged in a column along the first direction Y are called a column of sub-pixels P.
  • Each sub-pixel P is provided with a pixel circuit 11 for controlling the display of the sub-pixel P, and a light-emitting device 12 connected to the pixel circuit 11.
  • the light-emitting device 12 emits light under the control of the pixel circuit 11, thereby enabling the display panel 1000 to display.
  • the display panel 1000 also includes multiple signal lines, such as multiple longitudinal lines extending along the first direction Y.
  • the first direction Y and the second direction X are intersected, for example, perpendicularly, by a signal line YL and multiple horizontal signal lines XL.
  • Each sub-pixel is connected to at least one corresponding vertical signal line YL and at least one horizontal signal line XL, thereby receiving signals provided by the vertical signal line YL and the horizontal signal lines XL.
  • the display panel 1000 also includes data lines and DC voltage signal lines extending along the first direction Y.
  • the data lines are connected to a column of sub-pixels to provide data signals to the sub-pixels
  • the DC voltage signal lines are connected to a column of sub-pixels P to provide DC voltage signals to the sub-pixels.
  • multiple vertical signal lines YL need to be introduced from the peripheral area BB to the display area AA, meaning the vertical signal lines YL are located in the peripheral area BB and the display area AA.
  • Longer signal lines are prone to ESD problems, which can damage the display panel 1000. For example, it can affect the sub-pixels located in the display area AA, causing the pixel circuits in the sub-pixels to malfunction or the light-emitting devices to fail to emit light properly, affecting display quality, such as causing ghosting.
  • Some embodiments of this disclosure provide a display panel 1000, which solves the ESD problem that is prone to occur with long traces by improving the film layer setting and access method of the signal lines in the display panel 1000, thereby ensuring the display effect.
  • some embodiments of this disclosure provide a display panel 1000 having a display area AA and a peripheral area BB disposed on at least one side of the display area AA.
  • the peripheral area BB includes a first sub-area BB1 and a second sub-area BB2, which are respectively located on both sides of the display area AA in a first direction.
  • the peripheral area BB also includes two third sub-areas BB3, which are respectively located on both sides of the display area AA in a second direction X.
  • the display panel 1000 includes a substrate and at least two conductive layers disposed on one side of the substrate.
  • the display panel 1000 includes a first conductive layer 14 and a second conductive layer 13 sequentially disposed on the substrate, with an insulating layer disposed between adjacent conductive layers.
  • the display panel 1000 further includes at least one first signal line L, at least a portion of which extends along a first direction Y within the display area AA.
  • the first signal line L includes at least two signal sub-lines connected in sequence, with any two adjacent signal sub-lines located in different conductive layers of the at least two conductive layers.
  • the dotted pattern at the connection point of the first conductive layer 14 and the second conductive layer 13 represents a connection point 14' for connecting the signal sub-lines located in the first conductive layer 14 and the signal sub-lines located in the second conductive layer 13.
  • the connection point 14' is disposed in a via in the insulating layer between the two conductive layers, and the connection point 14' is a cross-layer connection structure, such as a columnar shape.
  • the display panel 1000 includes a plurality of sub-pixels arranged in an array.
  • the plurality of sub-pixels includes at least one row of first edge sub-pixels P1.
  • the at least one row of first edge sub-pixels P1 is closer to the first sub-region BB1 of the peripheral region BB than the other rows of sub-pixels P3.
  • the connection point of two adjacent signal sub-lines is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • first edge subpixels P1 is one or more rows of subpixels that are closest to the first sub-region BB1 of the peripheral area in the multiple rows of subpixels, that is, the first edge subpixel is close to the bottom edge of the display panel.
  • the first edge subpixel P1 can be a subpixel that can be displayed normally, or the first edge subpixel P1 can be a dummy subpixel, which is a subpixel that does not need to be displayed.
  • the displayed sub-pixels have the same film structure as the other row of sub-pixels P3.
  • the other row of sub-pixels P3 are sub-pixels that can be displayed normally. This is mainly to ensure the uniformity of the film layer during the manufacturing process of the display panel 1000.
  • the display panel 1000 includes at least one first signal line L.
  • the first signal line L can be a first voltage signal line (VSS signal line) or a data line. At least a portion of the first signal line L extends along a first direction Y, and at least a portion of the first signal line L is located in the display area AA.
  • the first signal line L extends entirely along the first direction Y, or the first signal line L includes a portion extending along the first direction Y and another portion extending along other directions.
  • the first signal line L includes a portion located in the display area AA and a portion located in the peripheral area BB.
  • the first signal line L is located in the display area AA and the first sub-area BB1, or the first signal line L is located in the display area AA and the second sub-area BB2, or the first signal line L is located in the display area AA, the first sub-area BB1, and the second sub-area BB2.
  • the first signal line L comprises at least two signal sub-lines connected in sequence. Any two adjacent signal sub-lines are located in different conductive layers. That is, the first signal line L is divided into at least two signal sub-lines. At least one of the at least two signal sub-lines extends along a first direction Y, and adjacent signal sub-lines are connected in sequence.
  • the connection point of two adjacent signal sub-lines located in the region where the at least one row of first edge sub-pixels P1 is located means that the first signal line L comprises at least two signal sub-lines, and there is a connection point between each pair of adjacent signal sub-lines. For example, if the first signal line comprises N signal sub-lines, then it has N-1 connection points, and these N-1 connection points are located in the region where the at least one row of first edge sub-pixels P1 is located.
  • the first signal line L includes at least two signal sub-lines. Each pair of adjacent connected signal sub-lines is called a group of adjacent signal sub-lines. For example, if the first signal line includes N signal sub-lines, then it includes N-1 groups of adjacent signal sub-lines. Among the connection points of multiple groups of adjacent signal sub-lines, the connection point of at least one group of adjacent signal sub-lines is located in the region where the first edge sub-pixel P1 of the at least one row is located, and the connection points of the remaining adjacent signal sub-lines are located in the regions where sub-pixels P3 of other rows are located. For example, a connection point of the first sub-region BB1 closest to the peripheral region is located in the region where the first edge sub-pixel P1 of the at least one row is located.
  • the display panel 1000 includes a first conductive layer 14 and a second conductive layer 13.
  • one signal sub-line is located in the first conductive layer 14 and the other signal sub-line is located in the second conductive layer 13.
  • the two adjacent signal sub-lines are connected by a connection point in a through hole in an insulating layer between the first conductive layer 14 and the second conductive layer 13.
  • the first signal sub-line L1 is located in the first conductive layer 14, and the second signal sub-line L2 is located in the second conductive layer 13, thereby splitting the long first signal line L, with the signal sub-lines jumping from the first conductive layer 14 to the second conductive layer 13.
  • the connection point 14' of the first signal sub-line L1 and the second signal sub-line L2 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • Some embodiments of this disclosure provide a display panel 1000, which includes a first signal line L.
  • a first signal line L By dividing the first signal line L into at least two signal sub-lines, and connecting the at least two signal sub-lines sequentially, a long signal line can be displayed.
  • the trace is split into at least two signal sub-lines. Compared to the first signal line L, each signal sub-line is shorter, and adjacent signal sub-lines are placed in different conductive layers.
  • the first signal line L jumps between different conductive layers at least twice. There are no excessively long signal lines in the same conductive layer, which is equivalent to reducing the length of signal lines in the same conductive layer.
  • each signal sub-line is not too long, this can avoid the problem of static electricity accumulation caused by excessively long traces during the manufacturing or use of the display panel 1000. This avoids the damage to the display panel 1000 caused by the instantaneous high voltage generated by ESD. It ensures that the sub-pixels set in the display area AA of the display panel 1000 are not affected. For example, the pixel circuits or light-emitting devices in the sub-pixels can work normally, ensuring display quality and avoiding the phenomenon of ghosting.
  • connection point of two adjacent signal sub-lines is located in the area where the first edge sub-pixel P1 of at least one row is located, that is, the jump connection point of signal sub-lines in different conductive layers is located in the area where the first edge sub-pixel P1 of at least one row is located
  • the jump hole design in the first sub-area near the periphery of the display area, the bottom sub-pixel row or the dummy sub-pixel row can minimize the impact of the jump hole design on the normal display of the sub-pixels in the display area while preventing ESD damage caused by the accumulation of static electricity in long traces.
  • it can avoid designing jump holes in other rows of sub-pixels that are displaying normally, and avoid affecting the layout of the pattern of the same film layer in other rows of sub-pixels P3, thereby ensuring the normal display function of other rows of sub-pixels P3 and ensuring the display quality of the display panel.
  • each of the plurality of sub-pixels P includes a pixel circuit 11;
  • the display panel includes a plurality of the pixel circuits arranged in an array, the plurality of pixel circuits including at least one row of first edge pixel circuits 111, the at least one row of first edge pixel circuits 111 being closer to the first sub-region than other rows of pixel circuits 113; the region where the at least one row of first edge sub-pixels is located includes the region where the at least one row of first edge pixel circuits is located.
  • multiple pixel circuit arrays are arranged in multiple rows along the second direction X and multiple columns along the first direction Y.
  • at least one row of first edge pixel circuits 111 is one or more rows of pixel circuits that are closest to the first sub-region BB1 of the peripheral area in the multiple rows of sub-pixels, that is, the first edge pixel circuits 111 are close to the bottom edge of the display panel.
  • At least one row of first edge pixel circuits 111 is, for example, a pixel circuit that can perform normal driving function, and the function of at least one row of first edge pixel circuits 111 is the same as the function of other rows of pixel circuits 113, all of which can drive the light-emitting device connected to it to emit light; or, at least one row of first edge pixel circuits 111 is, for example, a dummy pixel circuit, the structure of which is the same as the structure of other pixel circuits, does not perform normal driving function, and cannot drive the light-emitting device connected to it to emit light.
  • the display panel includes a semiconductor layer, a gate layer, a first source/drain metal layer, and a second source/drain metal layer disposed on a substrate.
  • the pixel circuit includes multiple transistors and a storage capacitor.
  • the transistors include an active layer located in the semiconductor layer, a gate located in the gate layer, and a source and a drain located in the first source/drain metal layer. That is, the pixel circuit is located in a film layer from the semiconductor to the second source/drain metal layer.
  • Figure 8 illustrates the film structure of the first source/drain metal layer SD1, the planarization layer PLN, and the second source/drain metal layer SD2 in the display panel.
  • the first source/drain metal layer SD1 includes multiple patterns
  • the second source/drain metal layer SD2 includes...
  • the multiple signal lines, the first source-drain metal layer SD1, and the second source-drain metal layer SD2 include a portion of the structure of multiple pixel circuits 11 arranged in an array.
  • Figure 8 illustrates a display panel including two rows of first edge sub-pixels P1, that is, two rows of first edge pixel circuits 111, and the area where the two rows of first edge sub-pixels are located includes the area where the two rows of first edge pixel circuits are located.
  • connection point of two adjacent signal sub-lines is located in the region where the at least one row of first edge sub-pixels is located. This can be understood as the connection point of two adjacent signal sub-lines being located in the region where the at least one row of first edge pixel circuits is located.
  • connection point of a group of adjacent signal sub-lines in the first sub-region BB1 closest to the peripheral area is located in the region where the at least one row of first edge pixel circuits 111 is located. This setting can minimize the impact of the jump hole design on the normal driving function of other row pixel circuits in the display area.
  • each of the plurality of sub-pixels includes a light-emitting device 12, which is connected to the pixel circuit 11; the light-emitting device includes an anode, a light-emitting layer, and a cathode stacked together.
  • FIG11C shows a schematic diagram of the film structure of the first source/drain metal layer SD1, the planarization layer PLN, the second source/drain metal layer SD2, and the anode layer Ano in the display panel.
  • the display panel 1000 includes a plurality of anodes Ano arranged in an array.
  • the plurality of anodes Ano includes at least one row of first edge anodes Ano1.
  • the at least one row of first edge anodes Ano1 is closer to the first sub-region BB1 than the other rows of anodes Ano3.
  • the anode Ano is connected to the pixel circuit 11.
  • multiple anode arrays are arranged in multiple rows along the second direction X and multiple columns along the first direction Y.
  • at least one row of first edge anodes Ano1 is one or more rows of anodes closest to the first sub-region BB1 of the peripheral area, i.e., the first edge anodes Ano1 are close to the bottom edge of the display panel.
  • At least one row of first edge anodes Ano1 is, for example, an anode that can normally receive anode signals, and its corresponding light-emitting device can emit light normally; or, at least one row of first edge anodes Ano1 is, for example, a dummy anode, whose arrangement and shape are consistent with the arrangement and shape of other rows of anodes. Since it does not receive signals, the light-emitting device where the dummy anode is located does not emit light.
  • the region where at least one row of first edge sub-pixels P1 is located includes the region where at least one row of first edge anodes Ano1 is located, and the connection point of two adjacent signal sub-lines overlaps with the at least one row of first edge anodes.
  • connection point of two adjacent signal sub-lines is located in the region where the at least one row of first edge sub-pixels is located.
  • This can be understood as the connection point of two adjacent signal sub-lines being located in the region where the at least one row of first edge anodes is located.
  • connection point of a group of adjacent signal sub-lines in the first sub-region BB1 closest to the peripheral region is located in the region where the at least one row of first edge anodes is located.
  • the first signal line L can be located in a conductive layer in the display panel, for example, it can be located in the first source/drain metal layer SD1 or the second source/drain metal layer SD2.
  • the anode layer is located on the side of the first source/drain metal layer SD1 or the second source/drain metal layer SD2 away from the substrate. Therefore, the anode layer ANO is located above the connection point of adjacent signal sub-lines in the first signal line L.
  • the connection point of the two adjacent signal sub-lines overlaps with the at least one row of first edge anodes. For example, adjacent The connection point of the two signal sub-lines is covered by one of the anodes in at least one row of first edge anodes.
  • the pixel circuit 11 and the light-emitting device 12 are not strictly aligned in the third direction Z.
  • the third direction Z is perpendicular to the first direction Y and perpendicular to the second direction X.
  • the outline of the orthographic projection of the area where a pixel circuit 11 is located on the substrate can be considered as a rectangle.
  • Multiple pixel circuits are arranged in rows and columns in close proximity.
  • the arrangement of multiple anodes is, for example, a diamond-shaped arrangement, and there is a gap between each anode. At least one row of first edge anodes Ano1 is closer to the boundary between the display area AA and the peripheral area BB than at least one row of first edge pixel circuits 111.
  • the following describes one embodiment of the first signal line L.
  • the display panel 1000 includes a plurality of data lines 3.
  • the plurality of data lines 3 extend along a first direction Y and are arranged along a second direction X.
  • the plurality of data lines 3 include at least one first data line 31 and at least one second data line 32.
  • the at least one first data line 31 is farther away from the center line K of the display panel 1000 along the first direction than the at least one second data line 32.
  • the center line K divides the display panel 1000 into two parts with approximately equal areas.
  • the data lines 3 are divided into two categories.
  • the first data line 31 is located near the peripheral area BB of the display area AA, and the second data line 32 is located in the middle area of the display area AA.
  • the multiple data lines 3 may include multiple first data lines 31 and multiple second data lines 32.
  • the multiple first data lines 31 are respectively located on both sides of the multiple second data lines 32 along the first direction.
  • the display panel 1000 also includes multiple fan-out traces 33 located in the first sub-area BB1 of the peripheral area BB.
  • the multiple fan-out traces include at least one first fan-out trace 331 and at least one second fan-out trace 332.
  • the first fan-out trace 331 is connected to the first data line 31, and the second fan-out trace 332 is connected to the second data line 32.
  • the first fan-out trace 331 and the second fan-out trace 332 converge at a position close to the center line of the display panel 1000 along the first direction.
  • the display panel 1000 further includes a plurality of bonding electrodes 34 located in a first sub-region BB1 of the peripheral region BB.
  • the bonding electrodes 34 are correspondingly connected to fan-out traces 33.
  • the plurality of bonding electrodes 34 are configured to be connected to a source driver chip, which is used to transmit data signals to multiple data lines through the plurality of bonding electrodes and the multiple fan-out traces, thereby providing data signals to multiple sub-pixels of the display panel 1000.
  • a first bonding electrode 341 is connected to a first fan-out trace 331
  • a second bonding electrode 342 is connected to a second fan-out trace 332.
  • At least one first signal line L includes at least one first data line 31.
  • the first data line 31 includes a first main data line 311, a first adapter line 312, and a second adapter line 313 located in the display area AA and connected in sequence.
  • the second adapter line 313 includes at least two sub-adapter lines connected in sequence, and the at least two sub-adapter lines of the second adapter line 313 serve as signal sub-lines.
  • the first data main line 311 and the second adapter line 313 extend along the first direction Y, with the first data main line 311 being farther away from the center line K of the display panel 1000 along the first direction compared to the second adapter line 313.
  • Wiring 312 extends along a second direction, which intersects with the first direction.
  • the first data main line 311 and the first adapter line 312 are located in different conductive layers.
  • the sub-adapter lines connected to the first adapter line 312 in the first adapter line 312 and the second adapter line 313 are located in different conductive layers. Two adjacent sub-adapter lines are located in different conductive layers.
  • connection point of two adjacent sub-transfer lines is located in the region where the first edge sub-pixel of the at least one row is located.
  • the first data main line 311 is connected to a column of sub-pixels.
  • the data signal is transmitted from the second adapter line 313 to the first adapter line 312, and then from the first adapter line 312 to the first data main line 311.
  • the first data main line 311 transmits the data signal to the connected column of sub-pixels.
  • the first data line 31 includes three sub-lines connected in sequence, and adjacent first data main lines 311 and first adapter lines 312 are located in different conductive layers.
  • the sub-adapter lines connected to the first adapter line 312 in adjacent first adapter lines 312 and second adapter lines 313 are located in different conductive layers.
  • the first data line 31 is located in the second conductive layer 13
  • the first adapter line 312 is located in the first conductive layer 14
  • one sub-adapter line in the second adapter line 313 is located in the second conductive layer 13
  • the other sub-adapter line is located in the first conductive layer 14.
  • first data main line 311 and the second adapter line 313 are located in the same conductive layer.
  • both the first data main line 311 and the second adapter line 313 are located in the second conductive layer 13.
  • Figures 8-13 represent one embodiment of this disclosure, showing a display panel employing an FIP (Fiber-in-the-Pack) and SIP (Single-in-the-Pack) design, with improvements made to the film layer configuration for the data lines and the first voltage signal lines.
  • Figures 14-19 represent another embodiment of this disclosure, showing a display panel employing an FIP and SIP design, with improvements made to the film layer configuration for the data lines and the first voltage signal lines.
  • Figures 20-24 represent yet another embodiment of this disclosure, showing a display panel employing a SIP design, with improvements made to the film layer configuration for the first voltage signal lines.
  • Figure 25 represents one embodiment of this disclosure.
  • the designs of the film layers in each embodiment can be combined with each other, and the combination of film layer designs among multiple embodiments is not limited.
  • Figures 8 to 11C illustrate wiring diagrams of the various film layers of the display panel 1000 in some embodiments
  • Figures 14 to 17C illustrate wiring diagrams of the various film layers of the display panel 1000 in other embodiments.
  • the display panel 1000 includes a substrate, a first source/drain metal layer SD1 and a second source/drain metal layer SD2 disposed on one side of the substrate, wherein a first data main line 311 is located in the second source/drain metal layer SD2, a first adapter line 312 is located in the first source/drain metal layer SD1, and a portion of the sub-adapter lines of the second adapter line 313 are located in the second source/drain metal layer SD2 and a portion of the sub-adapter lines are located in the first source/drain metal layer SD1.
  • the display panel 1000 also includes a planarization layer PLN located between the first source/drain metal layer SD1 and the second source/drain metal layer SD2.
  • the planarization layer PLN includes a plurality of vias.
  • the first adapter cable 312 and the second adapter cable 313 are connected through the vias penetrating the planarization layer PLN.
  • the first adapter cable 312 and the first data main line 311 are connected through the vias penetrating the planarization layer PLN.
  • the connection point of two adjacent sub-adapter cables is located at the first edge sub-pixel of the at least one row.
  • the second adapter 313 includes a first sub-adapter 3131, a second sub-adapter 3132, a third sub-adapter 3133, and a fourth sub-adapter 3134, wherein at least the connection point 313a of the first sub-adapter 3131 and the second sub-adapter 3132 is located in the area where the at least one row of first edge sub-pixels P1 is located.
  • the second adapter 313 includes a first sub-adapter 3131 and a second sub-adapter 3132, and at least the connection point 313a of the first sub-adapter 3131 and the second sub-adapter 3132 is located in the area where the at least one row of first edge sub-pixels P1 is located.
  • the above-described routing design for the first data line 31 divides it into a first main data line 311, a first adapter line 312, and a second adapter line 313.
  • the second adapter line 313 is further divided into multiple sub-adapter lines, with the connected sub-lines located on different conductive layers. This achieves the splitting of the relatively long first data line 31.
  • the first data line 31 jumps from the first conductive layer 14 to the second conductive layer 13 and then back to the first conductive layer 14.
  • the first data line 31 undergoes at least two jumps between different conductive layers. This avoids the problem of static electricity accumulation caused by excessively long routing during the fabrication or use of the display panel 1000, thereby preventing damage to the display panel 1000 caused by the instantaneous high voltage generated during ESD.
  • the first data line 31 can normally provide data signals to the sub-pixels, thus guaranteeing the display effect.
  • the connection point of two adjacent sub-transfer lines is located in the area where the first edge sub-pixel of at least one row is located, this can avoid the jump hole design from affecting the layout of the pattern of the same film layer in other row sub-pixels P3.
  • it can compress the pattern setting space of the first source drain metal layer SD1 in other row sub-pixels P3, avoid affecting the structure of other row sub-pixels P3, and thus ensure the normal display function of other row sub-pixels P3.
  • the first outgoing line 331 is connected to the first data line 31 in the following manner: the first outgoing line 331 is connected to the second adapter cable 313 of the first data line 31, and the data signal is transmitted from the first outgoing line 331 to the second adapter cable 313, then laterally to the first adapter cable 312, and then to the first data main line 311.
  • the second outgoing line 332 is directly connected to the second data line 32. In this way, the first data line 31 is farther away from the center line of the display panel 1000 than the second adapter line 313. Connecting the first fan-out line 331 to the second adapter line 313 allows the first fan-out line 331 to be located closer to the center line of the display panel 1000.
  • the first fan-out line 331 does not need to be connected to the edge of the display panel 1000.
  • the size between the first end of each first fan-out line 331 connected to the bonding electrode and the second end connected to the second adapter line 313 in the first direction is smaller.
  • Multiple fan-out lines can be more compact, and the size in the first direction can be narrowed, thereby reducing the area of the second sub-area BB2 of the display panel 1000. This is beneficial for narrowing the bottom bezel of the display panel 1000.
  • This technology is called FIP (fanout line in pixel) technology.
  • the routing design of the first data line 31 provided by some embodiments of this disclosure can solve the ESD problem caused by long routing while achieving a narrow bezel based on FIP technology, and ensure that the punch-hole design does not affect the normal display of the display panel.
  • the second adapter cable 313 includes components sequentially connected in the first direction.
  • the system comprises a first sub-connector 3131, a second sub-connector 3132, a third sub-connector 3133, and a fourth sub-connector 3134.
  • the first sub-connector 3131 is closer to the first sub-region BB1 than the second sub-connector 3132.
  • the fourth sub-connector 3134 is connected to the first sub-connector 312.
  • the first sub-connector 3131 and the third sub-connector 3133 are located on the same conductive layer, as are the second sub-connector 3132 and the fourth sub-connector 3134.
  • first sub-connector 3131 and the third sub-connector 3133 are located on the first source/drain metal layer SD1
  • the second sub-connector 3132 and the fourth sub-connector 3134 are located on the second source/drain metal layer SD2.
  • connection point 313a of the first sub-connector 3131 and the second sub-connector 3132 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • connection point 313a of the first sub-adapter line 3131 and the second sub-adapter line 3132 is located in the region where the first edge sub-pixel P1 of the at least one row is located, and the connection point 313b of the second sub-adapter line 3132 and the third sub-adapter line 3133 is located in the region where the first edge sub-pixel of the at least one row is located; in this case, the first sub-adapter line 3131 and the second sub-adapter line 3132 are located in the region where the first edge sub-pixel P1 of the at least one row is located.
  • connection point 313a of the first sub-adapter line 3131 and the second sub-adapter line 3132 is located in the region where the at least one row of first edge sub-pixels P1 is located; and the connection point 313b of the second sub-adapter line 3132 and the third sub-adapter line 3133 is located in the region where the at least one row of first edge sub-pixels P1 is located; and the connection point 313c of the third sub-adapter line 3133 and the fourth sub-adapter line 3134 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • the first sub-adapter line 3131, the second sub-adapter line 3132, and the third sub-adapter line 3133 are located in the region where the at least one row of first edge sub-pixels P1 is located.
  • connection point 313a of the first sub-connector 3131 and the second sub-connector 3132 is the first sub-region BB1 connection point closest to the peripheral area among the connection points of the second connector.
  • the connection point 313a of the first sub-connector 3131 and the second sub-connector 3132 is located in the area where the at least one row of first edge sub-pixels P1 is located.
  • the second adapter line 313 includes a first sub-adapter line 3131 and a second sub-adapter line 3132 connected sequentially in the first direction.
  • the first sub-adapter line 3131 is closer to the first sub-region BB1 than the second sub-adapter line 3132.
  • the connection point 313a of the first sub-adapter line 3131 and the second sub-adapter line 3132 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • the first sub-adapter wire 3131 is located on the first source/drain metal layer SD1, and the second sub-adapter wire 3132 is located on the second source/drain metal layer.
  • Layer SD2 The connection point 313a between the first sub-adapter cable 3131 and the second sub-adapter cable 3132 is disposed in a via through the planar layer PLN.
  • connection point of adjacent sub-adapter lines in the area where at least one row of first edge sub-pixels P1 is located that is, placing the jumper as close as possible to the first sub-area BB1 of the peripheral area—avoids the jumper design from interfering with the layout of the same film layer pattern in other rows of sub-pixels P3, ensuring the normal display function of the display panel.
  • the display panel includes at least one row of first edge anodes Ano1, and the connection point 313a of the first sub-adapter cable 3131 and the second sub-adapter cable 3132 is covered by the at least one row of first edge anodes Ano1.
  • the display panel includes one row of first edge anodes Ano1, and the connection point 313a of the first sub-adapter cable 3131 and the second sub-adapter cable 3132 overlaps with and is covered by the first edge anodes Ano1.
  • a first adapter line 312 of at least one first data line 31 is located in the region where at least one row of first edge sub-pixels P1 is located, and a portion of a second adapter line 313 of at least one first data line 31 (e.g., a first sub-adapter line 3131) is located in the region where at least one row of first edge sub-pixels P1 is located.
  • the configuration of the first adapter 312 of at least one first data line 31 can be avoided from affecting the layout of the pattern of the same film layer in other row sub-pixels P3.
  • the pattern setting space of the first source drain metal layer SD1 in other row sub-pixels P3 or the pattern setting space of the second source drain metal layer SD2 in other row sub-pixels P3 can be compressed to avoid affecting the structure of other row sub-pixels P3, thereby ensuring the normal display function of other row sub-pixels P3.
  • the display panel 1000 includes a first outgoing trace 331.
  • the first outgoing trace 331 is connected to a sub-transfer line of the second adapter line 313 of the first data line 31.
  • the first outgoing trace 331 is connected to the first sub-transfer line 3131.
  • the first outgoing trace 331 and the connected sub-transfer line are located in different conductive layers, that is, the first sub-transfer line 3131 and the first outgoing trace 331 are located in different conductive layers.
  • the first fan-out trace 331 is located in the gate metal layer, as shown in Figures 9 and 15, and the first sub-transfer line 3131 is located in the first source-drain metal layer SD1.
  • the first fan-out trace 331, the first sub-adapter line 3131 and the second sub-adapter line 3132, which are connected in sequence, are located on different film layers. This avoids the ESD problem of long traces caused by placing the three on the same conductive layer, thereby preventing ESD from affecting the display panel 1000.
  • the display panel 1000 includes a plurality of second data lines 32, a second adapter line 313 is located between two adjacent second data lines 32, and a first voltage signal line 2 is also provided between two adjacent second data lines 32.
  • the second adapter line 313 and the first voltage signal line 2 are spaced apart in the first direction.
  • the second data line 32 runs through the entire display area AA along the first direction Y.
  • One second data line 32 is connected to a column of sub-pixels.
  • a signal line is provided between adjacent second data lines 32.
  • a second adapter line 313 is provided between adjacent second data lines 32 near the first sub-area BB1 in the display area AA.
  • a first voltage signal line 2 for example, is provided between adjacent second data lines 32 at a location in the display area AA away from the first sub-area BB1.
  • the first voltage signal line 2 is, for example, a VSS signal line.
  • the first voltage signal line 2 and the second adapter line 313 do not contact each other; there is a gap between them.
  • the second adapter line 313 effectively occupies part of the space between adjacent second data lines 32, preventing the first voltage signal line 2 from extending to the location near the first sub-area BB1.
  • the first voltage signal line 2 provides a first voltage signal to other rows of sub-pixels P3 in the display area AA, but not to at least one row of first edge sub-pixels P1.
  • the display panel 1000 further includes a plurality of second voltage signal lines 41 extending along the first direction Y.
  • the second voltage signal lines 41 are, for example, VDD signal lines, and are located in the second source-drain metal layer SD2.
  • two adjacent second data lines 32 are located between two adjacent second voltage signal lines 41.
  • the display panel 1000 further includes a plurality of initialization signal vertical lines 42 extending along the first direction Y. The initialization signal vertical lines 42 are located in the second source-drain metal layer SD2, and are located between two adjacent second voltage signal lines.
  • This configuration allows for efficient use of the conductive layer's space, eliminating the need for a separate location for the second adapter cable 313.
  • This enables the arrangement of more signal lines within the limited space of the same conductive layer.
  • the second source/drain metal layer SD2 can simultaneously accommodate the second data line 32, the portion of the first voltage signal line 2 located between two adjacent second data lines 32, and the second adapter cable 313, which can accommodate the second voltage signal line and the initialization signal vertical line. This optimizes the spatial layout, with more signal lines corresponding to more sub-pixels, thereby increasing the pixel density of the display panel 1000 and enabling high-definition display.
  • a first voltage signal line 2 is provided between two adjacent first data main lines 311, and there are at least two first voltage signal lines 2 of unequal length.
  • the length of the first voltage signal line 2 located between two adjacent first data main lines 311 is greater than that of the first voltage signal line 2 located between two adjacent second data lines 32.
  • a first voltage signal line 2 and a second adapter line 313 are provided between two adjacent second data lines 32.
  • the second adapter line 313 and the first voltage signal line 2 are spaced apart in the first direction. In this case, since the second adapter line 313 occupies part of the space between two adjacent second data lines 32, the length of the first voltage signal line 2 is relatively short.
  • the first data main line 311 runs through the entire display area AA along the first direction Y.
  • One first data main line 311 is connected to a column of sub-pixels.
  • a first voltage signal line 2 is provided between two adjacent second data lines 32.
  • the first voltage signal line 2 located between two adjacent second data lines 32 can run through the entire display area AA.
  • the first voltage signal line 2 can be extended as close as possible to the first sub-area BB1.
  • the length of the first voltage signal line 2 located between two adjacent first data main lines 311 is longer than the length of the first voltage signal line 2 located between two adjacent second data lines 32.
  • the first voltage signal sub-line 21 and the second voltage signal sub-line 22 are located in different conductive layers, and the connection point 2a of the first voltage signal sub-line 21 and the second voltage signal sub-line 22 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • the first voltage signal sub-line 21 is located in the second conductive layer 13
  • the second voltage signal sub-line 22 is located in the first conductive layer 14.
  • the first voltage signal sub-line 21 is located in the second source-drain metal layer SD2, and the second voltage signal sub-line 22 is located in the first source-drain metal layer SD1.
  • the connection point 2a between the first voltage signal sub-line 21 and the second voltage signal sub-line 22 is located in the region where the at least one row of first edge sub-pixels P1 is located.
  • At least a portion of the first voltage signal line 2 is located in the display area AA.
  • the second voltage signal sub-line 22 is located in the display area AA
  • a portion of the first voltage signal sub-line 21 is located in the display area AA
  • another portion of the first voltage signal sub-line 21 is located in the first sub-area BB1.
  • the above-described routing design for the first voltage signal line 2 by dividing the first voltage signal line 2 into a first voltage signal sub-line 21 and a second voltage signal sub-line 22, with the connected sub-lines located in different conductive layers, achieves the splitting of the relatively long first voltage signal line 2.
  • the first voltage signal line 2 is then connected to different conductive layers. Compared to placing the entire first voltage signal line 2 in the same conductive layer, each sub-line is shorter, and adjacent sub-lines are placed in different conductive layers.
  • the first voltage signal line 2 undergoes at least two jumps between different conductive layers.
  • connection point 2a of the voltage signal first sub-line 21 and the voltage signal second sub-line 22 is located in the area where the first edge sub-pixel P1 of the at least one row is located.
  • the jump hole is set as close as possible to the first sub-area BB1 of the peripheral area, which can avoid the jump hole design from affecting the layout of the pattern of the same film layer in other row sub-pixels P3, and ensure the normal display function of the display panel.
  • the display panel 1000 includes at least one first voltage signal line 2, for example, multiple first voltage signal lines 2, arranged along the second direction X, and located in the display area AA.
  • This design is called SIP (ELVSS in pixel) design.
  • Arranging multiple first voltage signal lines 2 in the display area AA can reduce the trace resistance and signal loss during the transmission of the first voltage signal, thereby reducing the power consumption of the display panel 1000.
  • the display panel 1000 provided in some embodiments of this disclosure, by implementing SIP design on the first voltage signal lines 2 and dividing the first voltage signal lines 2 into multiple segments located in different conductive layers, achieves the solution of ESD problems caused by long traces while reducing the power consumption of the display panel 1000.
  • At least one first signal line L includes at least one first data line 31 and at least one first voltage signal line 2.
  • the display panel 1000 is based on FIP and SIP design, which can achieve the benefits of narrow bezel and low power consumption while avoiding ESD problems caused by long traces and solving shadow removal.
  • the connection point of adjacent sub-transfer lines in the first data line 31 is set in the area where at least one row of first edge sub-pixels P1 is located.
  • the connection point of two adjacent voltage signal sub-lines in the first voltage signal line 2 is located in the area where at least one row of first edge sub-pixels P1 is located, which can avoid the impact of the punch-hole design on the normal display of the display panel.
  • the display panel 1000 includes at least one row of first edge anodes Ano1, and the connection point 2a of the voltage signal first sub-line 21 and the voltage signal second sub-line 22 is covered by the at least one row of first edge anodes Ano1.
  • the display panel includes a row of first edge anodes Ano1, and the connection point 2a of the voltage signal first sub-line 21 and voltage signal second sub-line 22 overlaps with the row of first edge anodes Ano1, for example, is covered by the first edge anodes Ano1.
  • the display panel 1000 further includes a voltage signal first bus 25 disposed in a first sub-area BB1 of the peripheral area BB, and the voltage signal first sub-line 21 of the first voltage signal line 2 is connected to the voltage signal first bus 25.
  • the voltage signal first bus 25 and the voltage signal first sub-line 21 are located in the same conductive layer.
  • the voltage signal first bus 25 extends along the second direction X.
  • the voltage signal first bus 25 is located, for example, in the first source-drain metal layer SD1.
  • the voltage signal first sub-line 21 is located in the first source-drain metal layer SD1.
  • the first voltage signal vss is transmitted from the voltage signal first bus 25 to the voltage signal first sub-line 21, and then jumps to the voltage signal second sub-line 22 in the second source-drain metal layer SD2, thereby realizing the introduction of the first voltage signal from the peripheral area BB to the display area AA.
  • the first voltage signal bus 25 and the first voltage signal sub-line 21 are located in the same conductive layer, and the second voltage signal sub-line 22 is located in another conductive layer.
  • first voltage signal bus 25 and the first voltage signal sub-line 21 are both located in the first source-drain metal layer SD1, and the second voltage signal sub-line 22 is located in the second source-drain metal layer SD2.
  • the first voltage signal line 2 further includes a third voltage signal sub-line 23 and a fourth voltage signal sub-line 24 connected sequentially along the first direction Y.
  • the third voltage signal sub-line 23 is connected to the second voltage signal sub-line 22. Both the third voltage signal sub-line 23 and the fourth voltage signal sub-line 24 serve as signal sub-lines.
  • the plurality of sub-pixels includes at least one row of second edge sub-pixels P2, wherein the at least one row of second edge sub-pixels P2 is closer to the second sub-region of the peripheral area P3 than other rows of sub-pixels; in some embodiments, as shown in FIG12, FIG18A and FIG23, the display panel 1000 includes a plurality of sub-pixels arranged in an array, wherein the plurality of sub-pixels includes at least one row of second edge sub-pixels P2, wherein the at least one row of second edge sub-pixels P2 is closer to the second sub-region BB2 of the peripheral area BB than other rows of sub-pixels P3.
  • At least one row of second edge sub-pixels P2 is a sub-pixel close to the top border of the display panel 1000, such as a dummy sub-pixel.
  • a dummy sub-pixel is a sub-pixel that does not need to be displayed normally, and its film structure is the same as that of the other rows of sub-pixels P3.
  • the other rows of sub-pixels P3 are sub-pixels that are displayed normally, mainly to ensure the uniformity of the film layer during the fabrication of the display panel 1000.
  • connection point 2b between the third sub-line 23 and the second sub-line 22 of the voltage signal is located in the region where the at least one row of second edge sub-pixels is located. In other examples, the connection point 2b between the third sub-line 23 and the second sub-line 22 of the voltage signal is located in the region where the at least one row of second edge sub-pixels P2 is located, and the connection point 2c between the third sub-line 23 and the fourth sub-line 24 of the voltage signal is located in the region where the at least one row of second edge sub-pixels P2 is located.
  • the first voltage signal sub-line 21 is at least partially located in the second sub-region BB2 of the peripheral region BB, and the third voltage signal sub-line 23 is located in the display region AA.
  • the display panel further includes a second voltage signal bus 26, located in the second sub-area BB2 of the peripheral area BB, and a fourth voltage signal bus 24 connected to the voltage signal bus.
  • the second bus 26 is connected.
  • connection point 2b between the third voltage signal sub-line 23 and the second voltage signal sub-line 22 is located in the region where the at least one row of second edge sub-pixels P2 is located.
  • a part of the third voltage signal sub-line 23 is located in the display area AA, and another part is located in the second sub-region BB2, and the fourth voltage signal sub-line 24 is entirely located in the second sub-region BB2 of the peripheral area BB, that is, between the boundary of the second voltage signal bus 26 and the display area AA.
  • connection point 2b between the third sub-line 23 and the second sub-line 22 of the voltage signal is located in the area where at least one row of second edge sub-pixels P2 is located. That is, the connection point 2b between the third sub-line 23 and the second sub-line 22 of the voltage signal is located in the display area AA near the second sub-area BB2.
  • the connection point 2b is only provided in the area where the second edge sub-pixel P2 is located. No cross-layer connection points are needed in the areas where other rows of sub-pixels P3 are located.
  • each of the plurality of sub-pixels P includes a pixel circuit 11;
  • the display panel includes a plurality of the pixel circuits arranged in an array, the plurality of pixel circuits including at least one row of second edge pixel circuits 112, the at least one row of second edge pixel circuits 112 being closer to the second sub-region BB2 than other rows of pixel circuits 113;
  • the area where the at least one row of second edge sub-pixels P2 is located includes the area where the at least one row of first edge pixel circuits 112 is located.
  • multiple pixel circuit arrays are arranged in multiple rows along the second direction X and multiple columns along the first direction Y.
  • at least one row of second edge pixel circuits 112 is one or more rows of pixel circuits that are closest to the second sub-region BB2 of the peripheral area in the multiple rows of sub-pixels, that is, the second edge pixel circuits 112 are close to the upper edge of the display panel.
  • the display panel includes multiple anodes arranged in an array.
  • Each anode includes at least one row of second edge anodes Ano2, which are closer to the second sub-region BB2 than the other rows of anodes Ano3.
  • the region where the at least one row of second edge sub-pixels P2 is located includes the region where the at least one row of second edge anodes Ano2 is located, and the connection point 2c of the third sub-line of voltage signal 23 and the fourth sub-line of voltage signal 24 is covered by the at least one row of second edge anodes Ano2.
  • multiple anode arrays are arranged, with at least one row of second edge anodes Ano2 being one or more rows of anodes closest to the second sub-region BB2 of the peripheral area among the multiple rows of anodes, that is, the second edge anodes Ano2 are close to the top bezel of the display panel.
  • at least one row of second edge anodes Ano2 can normally receive anode signals, and the corresponding light-emitting device can emit light normally.
  • at least one row of second edge anodes Ano2 can be, for example, dummy anodes, whose arrangement and shape are consistent with the arrangement and shape of the other rows of anodes. Since no signal is received, the light-emitting device containing the dummy anode does not emit light.
  • connection point 2c between the third sub-line 23 and the fourth sub-line 24 of the voltage signal is the connection point closest to the second sub-region BB2 in the first voltage signal line 2.
  • the display panel for example, includes only one row of second edge anodes Ano2.
  • the connection point 2c between the third sub-line 23 and the fourth sub-line 24 of the voltage signal overlaps with and is covered by the second edge anodes Ano2.
  • the first voltage signal line 2 includes a fourth voltage signal sub-line 24, a third voltage signal sub-line 23, and a second voltage signal sub-line 22 connected in sequence.
  • the fourth voltage signal sub-line 24 is connected to a second voltage signal bus 26.
  • the first voltage signal VSS is transmitted from the second voltage signal bus 26 to the first voltage signal line 2 and introduced into the display area AA.
  • the configuration of the fourth voltage signal sub-line 24, the third voltage signal sub-line 23, and the second voltage signal sub-line 22 can be referred to the foregoing description.
  • the display panel 1000 further includes a lateral first voltage signal line 29 extending along a second direction X, the lateral first voltage signal line 29 being located in the region where at least one row of second edge sub-pixels P2 is located, and being connected to a voltage signal second sub-line 22.
  • Both the horizontal first voltage signal line 29 and the first voltage signal line 2 transmit the first voltage signal vss, only their extension directions are different.
  • a portion of the horizontal first voltage signal line 29 and the voltage signal second sub-line 22 are located in the area where at least one row of second edge sub-pixels P2 are located, and the horizontal first voltage signal line 29 and the voltage signal second sub-line 22 are connected, so that the horizontal first voltage signal line 29 and the first voltage signal line 2 transmit the same first voltage signal vss.
  • the display panel 1000 includes multiple first voltage signal lines 2, each of which is connected to a first voltage signal bus 25, and the second voltage signal sub-lines 22 of each of the multiple first voltage signal lines 2 are connected to a horizontal first voltage signal line 29.
  • the VSS signal lines of the entire display panel 1000 can form a mesh structure, which helps to reduce the overall trace resistance, reduce the loss of the first voltage signal transmission, facilitate the transmission of the first voltage signal, and further reduce the power consumption of the display panel 1000.
  • the first horizontal voltage signal line 29 and the second voltage signal sub-line 22 are located in the same conductive layer, and the first horizontal voltage signal line 29 and the second voltage signal sub-line 22 are arranged to cross each other and connected to each other.
  • the first lateral voltage signal line 29 and the second voltage signal sub-line 22 are located in the first source-drain metal layer SD1.
  • the first lateral voltage signal line 29 extends along the second direction X
  • the second voltage signal sub-line 22 extends along the first direction Y. They are intersecting and directly connected to each other in the first source-drain metal layer SD1.
  • the first lateral voltage signal line 29 and the second voltage signal sub-line 22 can be formed simultaneously by performing a patterning process on the first source-drain metal layer SD1, without the need for via connections, thus simplifying the process.
  • the first voltage signal line 2 includes a first voltage signal sub-line 21, a second voltage signal sub-line 22, a third voltage signal sub-line 23 and a fourth voltage signal sub-line 24 connected sequentially along the first direction Y.
  • the third voltage signal sub-line 23 and the fourth voltage signal sub-line 24 are located in different conductive layers.
  • the first voltage signal sub-line 21 and the third voltage signal sub-line 23 are located in the first conductive layer 14, and the second voltage signal sub-line 22 and the fourth voltage signal sub-line 24 are located in the second conductive layer 13.
  • the second voltage signal bus 26 extends along the second direction X.
  • the second voltage signal bus 26 transmits the first voltage signal VSS.
  • the first voltage signal VSS is transmitted from the second voltage signal bus 26 to the fourth voltage signal sub-line 24 and then to the third voltage signal sub-line 23, thus realizing the introduction of the first voltage signal from the peripheral area BB to the display area AA.
  • the display panel 1000 includes a second voltage signal bus 26 located in the second sub-area BB2 and a first voltage signal bus 25 located in the first sub-area BB1.
  • One end of the first voltage signal line 2 is connected to the second voltage signal bus 26 in the second sub-area BB2, and the other end is connected to the first voltage signal bus 25 in the first sub-area BB1.
  • the first voltage signal VSS is transmitted to the first voltage signal line 2 simultaneously through the first voltage signal bus 25 and the second voltage signal bus 26, thus realizing a more stable connection of the first voltage signal to the display area AA and lower signal loss.
  • first voltage signal sub-line 21 and the third voltage signal sub-line 23 are located in the first source-drain metal layer SD1
  • the second voltage signal bus 26, the second voltage signal sub-line 22 and the fourth voltage signal sub-line 24 are located in the second source-drain metal layer SD2.
  • the first voltage signal sub-line 21 is located in the first sub-region BB1 of the peripheral region BB. That is, when the first voltage signal line 2 includes the first voltage signal sub-line 21, the second voltage signal sub-line 22, the third voltage signal sub-line 23 and the fourth voltage signal sub-line 24 connected in sequence, the second voltage signal sub-line 22 extends along the first direction Y to the boundary of the display area AA, the first voltage signal sub-line 21 is located between the boundary of the display area AA and the first voltage signal bus 25, the third voltage signal sub-line 23 extends along the first direction Y to the boundary of the display area AA, and the fourth voltage signal sub-line 24 is located between the boundary of the display area AA and the second voltage signal bus 26.
  • the second adapter cable 313 is located between two adjacent second data lines 32.
  • the first voltage signal line 2 includes a fourth voltage signal sub-line 24, a third voltage signal sub-line 23, and a second voltage signal sub-line 22 connected in sequence, and the third voltage signal sub-line 23 does not extend to the boundary of the display area AA, that is, the first voltage signal line 2 does not include the first voltage signal sub-line 21.
  • the second voltage signal sub-line 22 extends to the boundary position of at least one row of first edge sub-pixels P1 and other row sub-pixels P3 in the display area AA.
  • the first voltage signal line 2 when a first voltage signal line 2 is provided between two adjacent first data main lines 311, in conjunction with FIG18A, FIG20 and FIG21, the first voltage signal line 2 includes a voltage signal first sub-line 21, a voltage signal second sub-line 22, a voltage signal third sub-line 23 and a voltage signal fourth sub-line 24 connected in sequence.
  • the first voltage signal line 2 extends from the second sub-area BB2 to the display area AA, and then extends to the first sub-area BB1.
  • the peripheral area BB includes two third sub-areas BB3, which are located on both sides of the display area AA in the second direction X.
  • the display panel 1000 also includes a voltage signal third bus 27, located in at least one third sub-region BB3 of the peripheral area BB.
  • the voltage signal third bus 27 may include one line located in one third sub-region BB3, for example, located in the left border area of the display panel 1000; or the voltage signal third bus 27 may include two lines located in two third sub-regions BB3, for example, located in the left border area and the right border area of the display panel 1000, respectively.
  • the voltage signal third bus 27 transmits a first voltage signal vss.
  • the display panel 1000 also includes at least one voltage conversion line 28, located in the third sub-area BB3 and between the voltage signal third bus 27 and the display area AA; the voltage conversion line 28 extends along the second direction X, the first end of the voltage conversion line 28 is connected to the voltage signal third bus 27, and the second end of the voltage conversion line 28 is connected to the first voltage signal line 2 closest to the voltage signal third bus 27.
  • the display panel 1000 includes a voltage adapter line 28 located in a third sub-region BB3, for example, the voltage adapter line 28 is located in the left frame area of the display panel 1000; or, the display panel 1000 includes voltage adapter lines 28 located in two third sub-regions BB3 respectively, for example, at least one voltage adapter line 28 is located in the left frame area of the display panel 1000, for example, the voltage adapter line 28 is located in the right frame area of the display panel 1000.
  • the second end of the voltage adapter line 28 is connected to a first voltage signal line 2 closest to the third voltage signal bus 27, and the first voltage signal line 2 closest to the third voltage signal bus 27 is, for example, a first voltage signal line 2 near the boundary of the display area AA.
  • the first voltage signal vss of the peripheral area BB is introduced into the display area AA.
  • the first voltage signal vss can be transmitted in multiple paths, which helps to reduce signal loss.
  • the display panel 1000 also includes multiple peripheral signal lines 51. These peripheral signal lines 51 extend along the first direction Y and are located between the third voltage signal bus 27 and the first voltage signal line 2 closest to the third voltage signal bus 27. That is, the peripheral signal lines 51 are located between the third voltage signal bus 27 and the display area AA.
  • the second end of the voltage conversion cable 28 is connected to at least one peripheral signal line 51, at which time the peripheral signal line 51 also transmits the first voltage signal vss.
  • Peripheral signal lines 51 are set around the display area, and the peripheral signal lines 51 form a ring connection around the display area AA. This can prevent the display area from being damaged by static electricity.
  • the third bus 27 is connected to the peripheral signal lines 51.
  • the peripheral signal lines 51 can also slightly share the VSS current of the peripheral area BB and reduce the cross-voltage power consumption.
  • the third voltage signal bus 27 and the voltage adapter line 28 are located on different conductive layers, and the voltage adapter line 28 and the first voltage signal line 2 are located on different conductive layers.
  • the third voltage signal bus 27 is located on the second source-drain metal layer SD2
  • the voltage adapter line 28 is located on the first source-drain metal layer SD1
  • the first voltage signal line 2 is located on the second source-drain metal layer SD2.
  • the voltage signal third bus 27 and the voltage adapter 28 are located on different conductive layers, and the voltage adapter 28 and the peripheral signal line 51 are located on different conductive layers.
  • the third voltage signal bus 27 is located on the second source-drain metal layer SD2
  • the voltage adapter line 28 is located on the first source-drain metal layer SD1
  • the peripheral signal line 51 is located on the second source-drain metal layer SD2.
  • the display panel 1000 further includes a horizontal first voltage signal line 29 extending along the second direction, the horizontal first voltage signal line 29 being located in the display area AA; the horizontal first voltage signal line 29 is connected to the voltage conversion cable 28.
  • the first horizontal voltage signal line 29 is connected to the voltage adapter line 28 located on one side of the display area AA, for example. Alternatively, both ends of the first horizontal voltage signal line 29 are connected to the voltage adapter lines 28 located on both sides of the display area AA.
  • the third voltage signal bus 27 is connected to the first horizontal voltage signal line 29 through the voltage adapter line 28, so that the first voltage signal VSS is introduced from the peripheral area BB into the display area AA. This realizes the multi-path transmission of the first voltage signal, which helps to reduce the trace impedance, reduce signal transmission loss, and reduce the power consumption of the display panel 1000.
  • the voltage adapter line 28 and the lateral first voltage signal line 29 are located in the same conductive layer.
  • the voltage adapter line 28 and the lateral first voltage signal line 29 are both located in the first source-drain metal layer SD1.
  • the display panel 1000 includes a first voltage signal bus 25, a second voltage signal bus 26, and two third voltage signal buses 27.
  • the first voltage signal bus 25, one third voltage signal bus 27, the second voltage signal bus 26, and the other third voltage signal bus 27 are connected sequentially and end-to-end to form a ring bus around the display area AA.
  • the first voltage signal bus 25 and the two third voltage signal buses 27 are connected in a ring.
  • the third bus 27 is located in the second source-drain metal layer SD2, and the second voltage signal bus 26 is located in the first source-drain metal layer SD1.
  • both the first voltage signal bus 25 and the second voltage signal bus 26 are located in the first source-drain metal layer SD1 or both are located in the second source-drain metal layer SD2.
  • some embodiments of the present disclosure also provide a display device 10000, which includes the display panel 1000 as described above.
  • the display device can be any device that displays either moving (e.g., video) or stationary (e.g., still image), and whether it is text or image. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, including but not limited to televisions, mobile phones, wearable devices, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, clocks, calculators, television monitors, flat panel displays, computer monitors, in-vehicle displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. Exemplarily, as shown in FIG26, display device 10000
  • the display device includes the display panel 1000 as described above.
  • the beneficial effects of the display device are consistent with those of the display panel 1000, namely, the display device is less prone to ESD phenomena caused by long traces.
  • the display device has the advantages of narrow bezels and low power consumption.

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Abstract

一种显示面板，具有显示区和围绕所述显示区的周边区,周边区包括第一子区和第二子区，第一子区和第二子区分别位于显示区在第一方向上的两侧；所述显示面板包括：衬底；层叠设置于所述衬底一侧的至少两个导电层；至少一条第一信号线，所述第一信号线的至少部分在所述显示区内沿第一方向延伸设置；所述第一信号线包括依次连接的至少两条信号子线，任意相邻的两条所述信号子线分别位于所述至少两个导电层中不同的导电层中。显示面板包括阵列式排布的多个子像素，多个子像素包括至少一行第一边缘子像素，至少一行第一边缘子像素相比其他行子像素靠近第一子区；相邻的两条信号子线的连接点位于至少一行第一边缘子像素所在的区域。

Description

显示面板及显示装置
本申请要求于2024年5月7日提交的、申请号为PCT/CN2024/091294的国际专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及显示装置。
背景技术
目前，有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置，因其具有自发光、快速响应、高对比度、宽视角和可制作在柔性衬底上等特点，受到广泛应用。
OLED显示装置包括多个子像素，各子像素包括像素电路和发光器件，通过像素电路驱动发光器件发光，从而实现显示。
发明内容
一方面，提供一种显示面板，具有显示区和围绕所述显示区的周边区；所述周边区包括第一子区和第二子区，所述第一子区和所述第二子区分别位于所述显示区在所述第一方向上的两侧。所述显示面板包括：衬底；层叠设置于所述衬底一侧的至少两个导电层；至少一条第一信号线，所述第一信号线的至少部分在所述显示区内沿第一方向延伸设置；所述第一信号线包括依次连接的至少两条信号子线，任意相邻的两条所述信号子线分别位于所述至少两个导电层中不同的导电层中。所述显示面板包括阵列式排布的多个子像素，所述多个子像素包括至少一行第一边缘子像素，所述至少一行第一边缘子像素相比其他行子像素靠近所述周边区的第一子区；相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素所在的区域。
在一些实施例中，所述多个子像素中的每个子像素包括像素电路；所述显示面板包括阵列式排布的多个所述像素电路，所述多个像素电路包括至少一行第一边缘像素电路，所述至少一行第一边缘像素电路相比其他行像素电路靠近所述第一子区；所述至少一行第一边缘子像素所在的区域包括所述至少一行第一边缘像素电路所在的区域。
在一些实施例中，所述多个子像素中的每个子像素包括发光器件；所述显示面板包括阵列式排布的多个阳极，所述多个阳极包括至少一行第一边缘阳极，所述至少一行第一边缘阳极相比其他行阳极靠近所述第一子区；所述至少一行第一边缘子像素所在的区域包括所述至少一行第一边缘阳极所在的区域，所述相邻的两条信号子线的连接点与所述至少一行第一边缘阳极有交叠。
在一些实施例中，所述至少一条第一信号线包括至少一条第一数据线，所述第一数据线包括位于所述显示区且依次连接的第一数据主线、第一转接线和第二转接线，所述第二转接线包括依次连接的至少两条子转接线，所述第一数据主线、所述第一转接线和所述至 少两条子转接线均作为所述信号子线；所述第一数据主线和所述第二转接线沿所述第一方向延伸，所述第一数据主线相比所述第二转接线远离所述显示面板的沿所述第一方向的中线。所述第一转接线沿第二方向延伸，所述第二方向与所述第一方向相交叉。其中，所述第一数据主线和所述第一转接线位于不同的所述导电层中，所述第一转接线和所述第二转接线中与所述第一转接线连接的子转接线位于不同的所述导电层中；相邻的两条子转接线位于不同的所述导电层中；相邻的两条子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
在一些实施例中，所述第二转接线包括在所述第一方向上依次连接的第一子转接线和第二子转接线，所述第一子转接线相比所述第二子转接线靠近所述第一子区；所述第一子转接线和所述第二子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
在一些实施例中，所述第二转接线包括在所述第一方向上依次连接的第一子转接线、第二子转接线、第三子转接线和第四子转接线，所述第一子转接线相比所述第二子转接线靠近所述第一子区；所述第一子转接线和所述第二子转接线的连接点位于所述至少一行第一边缘子像素所在的区域；和/或，所述第二子转接线和所述第三子转接线的连接点位于所述至少一行第一边缘子像素所在的区域；和/或，所述第三子转接线和所述第四子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
在一些实施例中，所述显示面板包括至少一行第一边缘阳极，所述第一子转接线和所述第二子转接线的连接点被所述至少一行第一边缘阳极覆盖。
在一些实施例中，显示面板还包括：位于所述周边区的第一子区的至少一条第一扇出走线，所述第一扇出走线与所述第一数据线的第二转接线的一条子转接线连接；其中，所述第一扇出走线与所连接的子转接线分别位于不同的所述导电层。
在一些实施例中，显示面板还包括：至少一条第二数据线，所述第二数据线沿所述第一方向延伸；所述至少一条第一数据线相比所述至少一条第二数据线远离所述显示面板的沿所述第一方向的中线；位于所述周边区的第一子区的至少一条第二扇出走线，所述第二扇出走线与所述第二数据线连接；其中，所述第二转接线位于相邻两条所述第二数据线之间，所述相邻两条第二数据线之间还设置有第一电压信号线，所述第二转接线和所述第一电压信号线在所述第一方向上间隔设置。
在一些实施例中，相邻两条所述第一数据主线之间设置有第一电压信号线，至少存在两条长度不等的第一电压信号线，位于相邻两条所述第一数据主线之间的第一电压信号线的长度大于位于相邻两条所述第二数据线之间的第一电压信号线的长度。
在一些实施例中，所述至少一条第一信号线包括至少一条第一电压信号线，所述第一电压信号线包括沿所述第一方向依次连接的电压信号第一子线和电压信号第二子线，所述电压信号第一子线相比所述电压信号第二子线靠近所述第一子区；所述电压信号第一子线 和所述电压信号第二子线均作为所述信号子线；其中，所述电压信号第一子线和所述电压信号第二子线位于不同的所述导电层，所述电压信号第一子线和所述电压信号第二子线的连接点位于所述至少一行第一边缘子像素所在的区域。
在一些实施例中，所述显示面板包括至少一行第一边缘阳极，所述电压信号第一子线和所述电压信号第二子线的连接点被所述至少一行第一边缘阳极覆盖。
在一些实施例中，显示面板还包括：电压信号第一总线，设置于所述周边区的第一子区，所述第一电压信号线的电压信号第一子线与所述电压信号第一总线连接；其中，所述电压信号第一总线与所述电压信号第一子线位于同一所述导电层。
在一些实施例中，所述第一电压信号线还包括沿所述第一方向依次连接的电压信号第三子线和电压信号第四子线，所述电压信号第三子线和所述电压信号第二子线连接；所述电压信号第三子线和所述电压信号第四子线均作为所述信号子线；所述多个子像素包括至少一行第二边缘子像素，所述至少一行第二边缘子像素相比其他行子像素靠近所述周边区的第二子区。所述电压信号第三子线和所述电压信号第二子线的连接点位于所述至少一行第二边缘子像素所在区域；或者；所述电压信号第三子线和所述电压信号第二子线的连接点位于所述至少一行第二边缘子像素所在区域，所述电压信号第三子线和所述电压信号第四子线的连接点位于所述至少一行第二边缘子像素所在区域。
在一些实施例中，所述显示面板包括阵列式排布的多个阳极，所述多个阳极包括至少一行第二边缘阳极，所述至少一行第二边缘阳极相比其他行阳极靠近所述第二子区；所述至少一行第二边缘子像素所在的区域包括所述至少一行第二边缘阳极所在的区域，所述电压信号第三子线和所述电压信号第四子线的连接点被所述至少一行第二边缘阳极覆盖。
在一些实施例中，显示面板还包括：沿第二方向延伸的横向第一电压信号线，所述横向第一电压信号线位于所述至少一行第二边缘子像素所在的区域，且与所述电压信号第三子线连接。
在一些实施例中，所述显示面板还包括电压信号第二总线，设置于所述周边区的第二子区，所述电压信号第四子线与所述电压信号第二总线连接；所述电压信号第一子线和所述电压信号第三子线位于同一所述导电层，所述电压信号第二总线、所述电压信号第二子线和所述电压信号第四子线位于另一所述导电层。
另一方面，提供一种显示装置，包括如上一方面任一项所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实 际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的一种结构图；
图2为根据一些实施例的显示面板的另一种结构图；
图3为根据一些实施例的显示面板的另一种结构图；
图4为根据一些实施例的显示面板的另一种结构图；
图5为根据一些实施例的显示面板的另一种结构图；
图6为根据一些实施例的显示面板的另一种结构图；
图7为根据一些实施例的显示面板的另一种结构图；
图8为根据一些实施例的显示面板中的一种膜层设置图；
图9为根据一些实施例的显示面板中的另一种膜层设置图；
图10为根据一些实施例的显示面板中的另一种膜层设置图；
图11A为根据一些实施例的显示面板中的另一种膜层设置图；
图11B为根据一些实施例的显示面板中的另一种膜层设置图；
图11C为根据一些实施例的显示面板中的另一种膜层设置图；
图12为根据一些实施例的显示面板中的另一种膜层设置图；
图13为根据一些实施例的显示面板中的另一种膜层设置图；
图14为根据一些实施例的显示面板中的另一种膜层设置图；
图15为根据一些实施例的显示面板中的另一种膜层设置图；
图16为根据一些实施例的显示面板中的另一种膜层设置图；
图17A为根据一些实施例的显示面板中的另一种膜层设置图；
图17B为根据一些实施例的显示面板中的另一种膜层设置图；
图17C为根据一些实施例的显示面板中的另一种膜层设置图；
图18A为根据一些实施例的显示面板中的另一种膜层设置图；
图18B为根据一些实施例的显示面板中的另一种膜层设置图；
图19为根据一些实施例的显示面板中的另一种膜层设置图；
图20为根据一些实施例的显示面板中的另一种膜层设置图；
图21为根据一些实施例的显示面板中的另一种膜层设置图；
图22A为根据一些实施例的显示面板中的另一种膜层设置图；
图22B为根据一些实施例的显示面板中的另一种膜层设置图；
图23为根据一些实施例的显示面板中的另一种膜层设置图；
图24为根据一些实施例的显示面板中的另一种膜层设置图；
图25为根据一些实施例的显示面板中的另一种膜层设置图；
图26为根据一些实施例的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到 正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在显示装置的制造和使用过程中，不可避免地会产生静电，如果静电进入显示面板1000中，积累到一定程度会发生ESD(Electro-Static Discharge，静电释放)现象，ESD发生的瞬间产生高电压，会对显示面板1000内部电极和走线造成损伤，进而影响显示面板1000的正常显示。
在一些实施例中，如图1所示，显示面板1000包括显示区AA(Active Area，简称AA区；也可称为有效显示区)和位于显示区AA至少一侧的周边区BB。显示面板1000例如可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板、量子点电致发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板和微型发光二极管(Mini Light Emitting Diodes，或Micro Light Emitting Diodes，MLED)显示面板等。
如图1所示，显示面板1000的显示区AA内设置有多个子像素P，为了方便说明，上述多个子像素P是以矩阵形式排列为例进行的说明，示例性地，多个子像素P排成N行M列。此时，沿第二方向X排列成一行的子像素P称为一行子像素P，沿第一方向Y排列成一列的子像素P称为一列子像素P，子像素P内设置有用于控制子像素P进行显示的像素电路11，以及与像素电路11连接的发光器件12，发光器件12在像素电路11的控制下发光，从而使显示面板1000实现显示。
在一些示例中，显示面板1000还包括多条信号线，例如沿第一方向Y延伸的多条纵 向信号线YL和沿第二方向X延伸的多条横向信号线XL，其中，第一方向Y和第二方向X交叉，例如垂直。子像素与相对应的至少一条纵向信号线YL、至少一条横向信号线XL连接，从而接收纵向信号线YL提供的信号和横向信号线XL提供的信号，例如显示面板1000还包括沿第一方向Y延伸的数据线和直流电压信号线，数据线与一列子像素连接，为子像素提供数据信号，直流电压信号线与一列子像素P连接，为子像素提供直流电压信号。示例性地，多条纵向信号线YL需要从周边区BB引入至显示区AA，即纵向信号线YL位于周边区BB和显示区AA，较长的信号线容易产生ESD问题，从而对显示面板1000造成损伤，例如会对显示面板1000中显示区AA内设置的子像素产生影响，导致子像素中像素电路无法正常工作或发光器件无法正常发光，影响显示品质，例如会出现消影现象。
本公开的一些实施例提供一种显示面板1000，通过改进显示面板1000中的信号线的膜层设置以及接入方式，解决长走线易出现的ESD问题，从而保证显示效果。
如图2所示，本公开的一些实施例提供一种显示面板1000，具有显示区AA和设置于所述显示区AA至少一侧的周边区BB。示例性地，周边区BB包括第一子区BB1和第二子区BB2，第一子区BB1和第二子区BB2分别位于显示区AA的在第一方向上的两侧，示例性地，周边区BB还包括两个第三子区BB3，两个第三子区BB3分别位于显示区AA在第二方向X上的两侧。
显示面板1000包括：衬底、设置于所述衬底一侧的至少两个导电层。示例性地，显示面板1000包括依次设置于衬底上的第一导电层14和第二导电层13，相邻两个导线层之间设置有绝缘层。
显示面板1000还包括至少一条第一信号线L，第一信号线L的至少部分在所述显示区AA内沿第一方向Y延伸设置；所述第一信号线L包括依次连接的至少两条信号子线，任意相邻的两条信号子线位于所述至少两个导电层中不同的导电层中。其中，第一导电层14和第二导电层13连接位置处的圆点图案表示用于连接位于第一导电层14的信号子线和位于第二导电层13的信号子线的连接点14’，连接点14’设置于两个导电层之间的绝缘层中的过孔中，连接点14’为跨层连接的的连接结构，例如为柱状。
显示面板1000包括阵列式排布的多个子像素，所述多个子像素包括至少一行第一边缘子像素P1，所述至少一行第一边缘子像素P1相比其他行子像素P3靠近周边区BB的第一子区BB1；相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素P1所在的区域。
需要说明的是，多个子像素排列成沿第二方向X延伸的多行子像素，至少一行第一边缘子像素P1为多行子像素中最靠近周边区的第一子区BB1的一行或多行子像素，即第一边缘子像素靠近显示面板的下边框。第一边缘子像素P1可以为能够进行正常显示的子像素，或者第一边缘子像素P1为虚设子像素(dummy子像素)，dummy子像素为无需进行 显示的子像素，其膜层结构与其他行子像素P3一致，其他行子像素P3为能够进行正常显示的子像素，主要为了保证显示面板1000制备过程中膜层的均一性。
如图2所示，显示面板1000包括至少一条第一信号线L，示例性地，第一信号线L可以为第一电压信号线(VSS信号线)，或者数据线。第一信号线L的至少部分沿第一方向Y延伸，且第一信号线L的至少部分位于显示区AA，示例性地，第一信号线L整体沿第一方向Y延伸，或者，第一信号线L包括沿第一方向Y延伸的一部分，还包括沿其他方向延伸的另一部分。第一信号线L包括位于显示区AA的部分，还包括位于周边区BB的部分，例如第一信号线L位于显示区AA和第一子区BB1，或者，第一信号线L位于显示区AA和第二子区BB2，或者，第一信号线L位于显示区AA、第一子区BB1和第二子区BB2。
第一信号线L包括依次连接的至少两条信号子线，任意相邻的两条信号子线分别位于不同的导电层中，即第一信号线L被分为至少两条信号子线，至少两条信号子线中至少一条信号子线沿第一方向Y延伸，且至少两条信号子线中相邻两个信号子线依次连接。相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素P1所在的区域是指，第一信号线L包括至少两条信号子线，每相邻两条信号子线之间具有连接点，示例性地，第一信号线包括N条信号子线，则具有N-1个连接点，该N-1个连接点位于至少一行第一边缘子像素P1所在的区域。
作为一种可能的实现方式，第一信号线L包括至少两条信号子线，每相邻两条连接的信号子线称为一组相邻的两条信号子线，示例性地，第一信号线包括N条信号子线，则包括N-1组相邻的两条信号子线，多组相邻的两条信号子线的连接点中，至少一组相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素P1所在的区域，其余的相邻的两条信号子线的连接点位于其他行子像素P3所在的区域；示例性地，最靠近周边区的第一子区BB1的一个连接点位于所述至少一行第一边缘子像素P1所在的区域。
示例性地，显示面板1000包括第一导电层14和第二导电层13，相邻的两个信号子线中，其中一个信号子线位于第一导电层14，另一个信号子线位于第二导电层13，且相邻的两个信号子线之间通过贯穿第一导电层14和第二导电层13之间的绝缘层的过孔中的连接点连接。
示例性地，如图2所示，第一信号线L中，其中第一条信号子线L1位于第一导电层14，第二条信号子线L2位于第二导电层13，实现了将较长的第一信号线L进行拆分，信号子线由第一导电层14跳接至第二导电层13。其中，第一条信号子线L1和第二条信号子线L2的连接点14’位于所述至少一行第一边缘子像素P1所在的区域。
本公开的一些实施例提供一种显示面板1000，显示面板1000包括第一信号线L，通过将第一信号线L划分为至少两条信号子线，且至少两条信号子线依次相连，实现了将长 走线拆分为至少两条信号子线，相比第一信号线L，每条信号子线的长度较短，且将相邻的信号子线设置于不同的导电层中，第一信号线L进行至少两次不同导电层的跳转，同一导电层中不会出现长度过长的信号线，相当于减少了同一层导电层中信号线的长度，由于每条信号子线的长度都不会过长，这样可以避免在显示面板1000的制备或使用过程中，由于走线过长导致的静电积累问题，从而避免了ESD发生的瞬间产生高电压对显示面板1000造成损伤，保证了显示面板1000中显示区AA内设置的子像素不会受到影响，例如子像素中像素电路或发光器件均能正常工作，保证显示品质，避免出现消影现象。
由于相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素P1所在的区域，即位于不同导电层的信号子线进行跳接的位置位于至少一行第一边缘子像素P1所在的区域，在显示区的靠近周边区的第一子区的位置、最下方子像素行或dummy子像素行进行跳孔设计，可以在防止长走线存在静电累积发生ESD损伤的基础上，尽量降低跳孔设计对显示区子像素进行正常显示的影响，例如尽量避免在进行正常显示的其他行子像素中设计跳孔，避免对其他行子像素P3中同一膜层的图案的布局的影响，从而保证其他行子像素P3的正常显示功能，保证显示面板的显示质量。
在一些实施例中，如图2和图8所示，多个子像素P中的每个子像素P包括像素电路11；所述显示面板包括阵列式排布的多个所述像素电路，所述多个像素电路包括至少一行第一边缘像素电路111，所述至少一行第一边缘像素电路111相比其他行像素电路113靠近所述第一子区；所述至少一行第一边缘子像素所在的区域包括所述至少一行第一边缘像素电路所在的区域。
示例性地，多个像素电路阵列排布，沿第二方向X排列成多行，沿第一方向Y排列成多列，多行像素电路中，至少一行第一边缘像素电路111为多行子像素中最靠近周边区的第一子区BB1的一行或多行像素电路，即第一边缘像素电路111靠近显示面板的下边框。在一些示例中，至少一行第一边缘像素电路111例如为可以实现正常驱动功能的像素电路，至少一行第一边缘像素电路111的功能与其他行像素电路113的功能一致，均能驱动其所连接的发光器件发光；或者，至少一行第一边缘像素电路111例如为dummy像素电路，dummy像素电路的结构与其他像素电路的结构一致，不发挥正常的驱动功能，无法驱动器所连接的发光器件发光。
显示面板包括设置于衬底上的半导体层、栅极层和第一源漏金属层、第二源漏金属层，像素电路包括多个晶体管和存储电容器，晶体管包括位于半导体层的有源层、位于栅极层的栅极、位于第一源漏金属层的源极和漏极，即像素电路位于从半导体至第二源漏金属层的膜层中。
如图8所示，图8示意出显示面板中第一源漏金属层SD1、平坦层PLN和第二源漏金属层SD2的膜层结构图，第一源漏金属层SD1包括多个图案，第二源漏金属层SD2包括 多条信号线，第一源漏金属层SD1和第二源漏金属层SD2包括阵列排布的多个像素电路11的部分结构。示例性地，图8中示意出显示面板包括两行第一边缘子像素P1，即包括两行第一边缘像素电路111，两行第一边缘子像素所在的区域包括所述两行第一边缘像素电路所在的区域。
相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素所在的区域，可以理解为相邻的两条信号子线的连接点位于至少一行第一边缘像素电路所在的区域，例如，最靠近周边区的第一子区BB1的一组相邻的信号子线的连接点位于所述至少一行第一边缘像素电路111所在的区域。这样设置，能够尽量降低跳孔设计对显示区中其他行像素电路进行正常发挥驱动功能的影响，例如尽量避免在进行正常显示的其他行像素电路所在区域中设计跳孔，避免对其他行像素电路中同一膜层的图案(例如晶体管的源极、漏极图案等)的布局的影响，从而保证其他行子像素P3的正常显示功能，保证显示面板的显示质量。
在另一些实施例中，如图2所示，所述多个子像素中的每个子像素包括发光器件12，发光器件12与像素电路11连接；发光器件包括堆叠设置的阳极、发光层和阴极。请参照图11C，图11C示意出显示面板中第一源漏金属层SD1、平坦层PLN、第二源漏金属层SD2和阳极层Ano的膜层结构图，显示面板1000包括阵列式排布的多个阳极Ano，多个阳极Ano包括至少一行第一边缘阳极Ano1，至少一行第一边缘阳极Ano1相比其他行阳极Ano3靠近第一子区BB1。
一个子像素P中，阳极Ano与像素电路11连接，示例性地，多个阳极阵列排布，沿第二方向X排列成多行，沿第一方向Y排列成多列，多行阳极中，至少一行第一边缘阳极Ano1为多行阳极中最靠近周边区的第一子区BB1的一行或多行阳极，即第一边缘阳极Ano1靠近显示面板的下边框。在一些示例中，至少一行第一边缘阳极Ano1例如为可以正常接入阳极信号的阳极，其所对应的发光器件能够正常发光，或者，至少一行第一边缘阳极Ano1例如为dummy阳极，dummy阳极的排布、形状与其他行阳极的排布、形状一致，由于不接入信号，dummy阳极所在的发光器件不发光。
至少一行第一边缘子像素P1所在的区域包括所述至少一行第一边缘阳极Ano1所在的区域，相邻的两条信号子线的连接点与所述至少一行第一边缘阳极有交叠。
示例性地，相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素所在的区域，可以理解为相邻的两条信号子线的连接点位于至少一行第一边缘阳极所在的区域，例如，最靠近周边区的第一子区BB1的一组相邻的信号子线的连接点位于所述至少一行第一边缘阳极所在的区域。由于第一信号线L可位于显示面板中的导电层，例如可位于第一源漏金属层SD1或第二源漏金属层SD2，阳极层位于第一源漏金属层SD1或第二源漏金属层SD2远离衬底一侧，因此阳极层ANO位于第一信号线L中相邻信号子线的连接点的上方，所述相邻的两条信号子线的连接点与所述至少一行第一边缘阳极有交叠，例如相邻的 两条信号子线的连接点被至少一行第一边缘阳极中的一个阳极覆盖。
需要说明的是，如图2、图11B和图11C所示，一个子像素P中，像素电路11和发光器件12在第三方向Z上并不是严格的正对关系，第三方向Z垂直于第一方向Y，且垂直于第二方向X，一个像素电路11所在的区域在衬底上的正投影的轮廓可认为是矩形，多个像素电路成行成列紧密排布，多个阳极的排布方式例如为钻石型排布，且各阳极之间具有间隔，至少一行第一边缘阳极Ano1相比至少一行第一边缘像素电路111更靠近显示区AA和周边区BB的交界。
以下介绍第一信号线L的一种实施例。
在一些实施例中，如图3所示，显示面板1000包括多条数据线3，示例性地，多条数据线3沿第一方向Y延伸，且沿第二方向X排列，多条数据线3包括至少一条第一数据线31和至少一条第二数据线32，其中，至少一条第一数据线31相比至少一条第二数据线32远离所述显示面板1000的沿第一方向的中线K，中线K将显示面板1000分为面积大致相等的两部分。
示例性地，数据线3分为两类，其中，第一数据线31位于显示区AA的靠近周边区BB的位置，第二数据线32位于显示区AA的中间区域，多条数据线3可以包括多条第一数据线31和多条第二数据线32，多条第一数据线31分别位于多条第二数据线32的沿第一方向上的两侧。
第一数据线31和第二数据线32接入信号的方式不同，如图3所示，显示面板1000还包括位于所述周边区BB的第一子区BB1的多条扇出走线33，多条扇出走线包括至少一条第一扇出走线331和至少一条第二扇出走线332，所述第一扇出走线331与所述第一数据线31连接，第二扇出走线332与第二数据线32连接。第一扇出走线331和第二扇出走线332聚拢在靠近显示面板1000的沿第一方向的中线的位置。
在一些实施例中，显示面板1000还包括位于周边区BB的第一子区BB1的多个绑定电极34，绑定电极34与扇出走线33对应连接，其中，多个绑定电极34被配置为与源极驱动芯片连接，源极驱动芯片用于将数据信号通过多个绑定电极、多条扇出走线传输至多条数据线，进而为显示面板1000的多个子像素提供数据信号。其中，第一绑定电极341与第一扇出走线331连接，第二绑定电极342与第二扇出走线332连接。
在一些实施例中，如图3和图4所示，至少一条第一信号线L包括至少一条第一数据线31，所述第一数据线31包括位于所述显示区AA且依次连接的第一数据主线311、第一转接线312和第二转接线313，第二转接线313包括依次连接的至少两条子转接线，第二转接线313的至少两条子转接线作为信号子线。
所述第一数据主线311和所述第二转接线313沿所述第一方向Y延伸，第一数据主线311相比所述第二转接线313远离所述显示面板1000的沿所述第一方向的中线K。第一转 接线312沿第二方向延伸，第二方向与第一方向相交叉。
其中，第一数据主线311和第一转接线312位于不同的所述导电层中，第一转接线312和第二转接线313中与第一转接线312连接的子转接线位于不同的所述导电层中，相邻的两条子转接线位于不同的所述导电层中。
相邻的两条子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
第一数据主线311与一列子像素连接，数据信号由第二转接线313传输至第一转接线312，进而由第一转接线312传输至第一数据主线311，第一数据主线311将数据信号传输至所连接的一列子像素。
第一数据线31包括依次相连接的三段子线，且相邻的第一数据主线311和第一转接线312位于不同的所述导电层中，相邻的第一转接线312和第二转接线313中与第一转接线312连接的子转接线位于不同的所述导电层中，例如第一数据线31位于第二导电层13，第一转接线312位于第一导电层14，第二转接线313中的一条子转接线位于第二导电层13，另一条子转接线位于第一导电层14。
示例性地，第一数据主线311和第二转接线313位于相同的导电层中。例如，第一数据主线311和第二转接线313均位于第二导电层13。
以下结合显示面板中的LAYOUT膜层布局图介绍本申请方案，需要说明的是，图8～图13属于本公开的一种实施例，图8～图13表示出显示面板采用FIP设计和SIP设计，在此基础上，对数据线和第一电压信号线的膜层设置进行了改进。图14～图19属于本公开的另一种实施例，图14～图19表示出显示面板采用FIP设计和SIP设计，在此基础上，对数据线和第一电压信号线的膜层设置进行了改进。图20～图24属于本公开的又一种实施例，图20～图24表示出显示面板采用SIP设计，在此基础上，对第一电压信号线的膜层设置进行了改进。图25属于本公开的一种实施例。各实施例中的各膜层的设计可以相互组合，多个实施例之间的膜层设计组合方式并不做限定。
如图8～图11C所示，以及图14～图17C所示，图8～图11C示意出一些实施例中显示面板1000的各膜层的布线图，图14～图17C示意出另一些实施例中显示面板1000的各膜层的布线图。显示面板1000包括衬底、设置于衬底一侧的第一源漏金属层SD1和第二源漏金属层SD2，其中，第一数据主线311位于第二源漏金属层SD2，第一转接线312位于第一源漏金属层SD1，第二转接线313中部分子转接线位于第二源漏金属层SD2，部分子转接线位于第一源漏金属层SD1。显示面板1000还包括位于第一源漏金属层SD1和第二源漏金属层SD2之间的平坦层PLN，平坦层PLN包括多个过孔，第一转接线312和第二转接线313通过贯穿平坦层PLN的过孔连接，第一转接线312和第一数据主线311通过贯穿平坦层PLN的过孔连接。
第二转接线313中，相邻的两条子转接线的连接点位于所述至少一行第一边缘子像素 所在的区域。例如，如图8～图11C所示，第二转接线313包括第一子转接线3131、第二子转接线3132、第三子转接线3133和第四子转接线3134，其中，至少第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域。例如，如图14～图17C所示，第二转接线313包括第一子转接线3131和第二子转接线3132，至少第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域。
上述对于第一数据线31的走线设计，通过将第一数据线31分为第一数据主线311、第一转接线312和第二转接线313，第二转接线313分为多个子转接线，且相连接的子线位于不同导电层，实现了将较长的第一数据线31进行拆分，第一数据线31由第一导电层14跳接至第二导电层13，再跳接回第一导电层14，第一数据线31进行至少两次不同导电层的跳转，这样可以避免在显示面板1000的制备或使用过程中，由于走线过长导致的静电积累问题，从而避免了ESD发生的瞬间产生高电压对显示面板1000造成损伤，保证第一数据线31能够正常为子像素提供数据信号，进而保证显示效果。同时，由于相邻的两条子转接线的连接点位于所述至少一行第一边缘子像素所在的区域，这样能够避免跳孔设计影响其他行子像素P3中同一膜层的图案的布局，例如压缩其他行子像素P3中第一源漏金属层SD1的图案设置空间，避免对其他行子像素P3的结构造成影响，从而保证其他行子像素P3的正常显示功能。
在一些实施例中，如图3所示，第一扇出走线331与第一数据线31连接的方式为：第一扇出走线331与第一数据线31的第二转接线313连接，数据信号由第一扇出走线331传输至第二转接线313，再横向传输至第一转接线312，再传输至第一数据主线311上。第二扇出走线332与第二数据线32的连接方式为，第二扇出走线332直接与第二数据线32连接。这样，第一数据线31相比第二转接线313更远离显示面板1000的中线，将第一扇出走线331与第二转接线313连接，可以使得第一扇出走线331位于靠近显示面板1000的中线的位置，相比第一扇出走线331直接与第一数据主线311连接，第一扇出走线331无需跨接至靠近显示面板1000的边缘的位置，每条第一扇出走线331的与绑定电极连接的第一端和与第二转接线313连接的第二端之间在第一方向上的尺寸变小，多条扇出走线可以更加收拢，在第一方向上的尺寸可以收窄，从而显示面板1000的第二子区BB2的面积可以减小，有利于实现显示面板1000的下边框的窄化，此技术称为FIP(fanout line in pixel)技术。
综上，本公开的一些实施例提供的第一数据线31的走线设计，可以在基于FIP技术，实现窄边框的基础上，解决长走线带来的ESD问题，以及使得跳孔设计不影响显示面板的正常显示。
在一些实施例中，如图8～图11C所示，第二转接线313包括在第一方向上依次连接的 第一子转接线3131、第二子转接线3132、第三子转接线3133和第四子转接线3134，第一子转接线3131相比第二子转接线3132靠近所述第一子区BB1，第四子转接线3134与第一转接线312连接；其中，第一子转接线3131和第三子转接线3133位于同一导电层，第二子转接线3132和第四子转接线3134位于同一导电层。例如，第一子转接线3131和第三子转接线3133位于第一源漏金属层SD1，第二子转接线3132和第四子转接线3134位于第二源漏金属层SD2。
在一些示例中，第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域。
在一些示例中，第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域，并且，第二子转接线3132和所述第三子转接线3133的连接点313b位于所述至少一行第一边缘子像素所在的区域；此时，第一子转接线3131和第二子转接线3132位于所述至少一行第一边缘子像素P1所在的区域。
在一些示例中，第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域，并且，第二子转接线3132和第三子转接线3133的连接点313b位于所述至少一行第一边缘子像素所在的区域；并且，第三子转接线3133和第四子转接线3134的连接点313c位于至少一行第一边缘子像素P1所在的区域。此时，第一子转接线3131和第二子转接线3132、第三子转接线3133位于所述至少一行第一边缘子像素P1所在的区域。
其中，第一子转接线3131和第二子转接线3132的连接点313a为第二转接线的连接点中最靠近周边区的第一子区BB1连接点，在所述至少一行第一边缘子像素P1仅包括一行第一边缘子像素P1的情况下，仅第一子转接线3131和第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域。
第二子转接线3132和第三子转接线3133的连接点313b相比连接点313a远离周边区的第一子区BB1，第三子转接线3133和第四子转接线3134的连接点313c相比连接点313b远离周边区的第一子区BB1，在所述至少一行第一边缘子像素P1包括两行或者更多行第一边缘子像素P1的情况下，第二子转接线3132和第三子转接线3133的连接点313b位于所述至少一行第一边缘子像素所在的区域；和/或，第三子转接线3133和第四子转接线3134的连接点313c位于至少一行第一边缘子像素P1所在的区域。
在另一些实施例中，如图14～图17C所示，第二转接线313包括在所述第一方向上依次连接的第一子转接线3131和第二子转接线3132，第一子转接线3131相比第二子转接线3132靠近所述第一子区BB1；所述第一子转接线3131和所述第二子转接线3132的连接点313a位于所述至少一行第一边缘子像素P1所在的区域。
第一子转接线3131位于第一源漏金属层SD1，第二子转接线3132位于第二源漏金属 层SD2。第一子转接线3131和所述第二子转接线3132的连接点313a设置于贯穿平坦层PLN的过孔中。
通过将第二转接线313分为至少两条子转接线，且通过跳孔设计连接位于不同导电层的相邻的子转接线，实现了将较长的第二转接线313拆分为多段，且进行至少两次不同导电层的跳转，可以避免较长的第二转接线313可能导致的静电积累问题，进一步避免了ESD发生的瞬间产生高电压对显示面板1000造成损伤。同时，将相邻子转接线的连接点设置于至少一行第一边缘子像素P1所在的区域，即尽可能将跳孔设置在靠近周边区的第一子区BB1的位置，能够避免跳孔设计对其他行子像素P3中同一膜层的图案的布局，保证显示面板的正常显示功能。
在一些实施例中，如图11C、图17C所示，显示面板包括至少一行第一边缘阳极Ano1，第一子转接线3131和第二子转接线3132的连接点313a被所述至少一行第一边缘阳极Ano1覆盖。例如，显示面板包括一行第一边缘阳极Ano1，第一子转接线3131和第二子转接线3132的连接点313a与一行第一边缘阳极Ano1有交叠，且被第一边缘阳极Ano1覆盖。
在一些实施例中，如图8～图11C、以及图14～图17C所示，至少一条第一数据线31的第一转接线312位于至少一行第一边缘子像素P1所在的区域，至少一条第一数据线31的第二转接线313的一部分(例如第一子转接线3131)位于至少一行第一边缘子像素P1所在的区域。
如图8～图11C、以及图14～图17C所示，至少一条第一数据线31的第一转接线312和第二转接线313位于显示区AA中靠近第一子区BB1的位置，例如显示面板1000包括至少两行第一边缘子像素P1(例如dummy子像素)，第一转接线312位于从下至上的第二行第一边缘子像素P1所在的区域，第二转接线313的至少一部分位于两行第一边缘子像素P1所在的区域，第二转接线313的另一部分位于其他行子像素P3所在的区域。其他第一数据线31的第一转接线312位于其他行子像素P3所在区域。
通过这样设置，能够避免至少一条第一数据线31的第一转接线312的设置影响其他行子像素P3中同一膜层的图案的布局，例如压缩其他行子像素P3中第一源漏金属层SD1的图案设置空间或者压缩其他行子像素P3中第二源漏金属层SD2的图案设置空间，避免对其他行子像素P3的结构造成影响，从而保证其他行子像素P3的正常显示功能。
在一些实施例中，如图3所示，显示面板1000包括第一扇出走线331，如图8～图11C、以及图14～图17C所示，第一扇出走线331与第一数据线31的第二转接线313的一条子转接线连接，例如，第一扇出走线331与第一子转接线3131连接。第一扇出走线331与所连接的子转接线分别位于不同的导电层中，即第一子转接线3131与第一扇出走线331分别位于不同的导电层。
示例性地，第一扇出走线331位于栅极金属层，如图9和图15所示，第一子转接线3131位于第一源漏金属层SD1。
通过这样设置，使得依次连接的第一扇出走线331、第一子转接线3131和第二子转接线3132分别位于不同的膜层，可以避免将三者位于同一导电层带来的长走线ESD问题，从而避免ESD对显示面板1000造成影响。
在一些实施例中，如图7和图11A所示，显示面板1000包括多条第二数据线32，第二转接线313位于相邻两条所述第二数据线32之间，相邻两条第二数据线32之间还设置有第一电压信号线2，第二转接线313和第一电压信号线2在所述第一方向上间隔设置。
其中，第二数据线32沿第一方向Y贯穿整个显示区AA，一条第二数据线32与一列子像素连接，相邻两条第二数据线32之间设置有信号线，其中，在显示区AA的靠近第一子区BB1的位置，相邻两条所述第二数据线32之间设置有第二转接线313，在显示区AA的远离第一子区BB1的位置，相邻两条第二数据线32之间还设置有第一电压信号线2，第一电压信号线2例如为VSS信号线，第一电压信号线2和第二转接线313不接触，二者之间有间隔。从而，第二转接线313相当于占用了相邻两条第二数据线32之间的部分空间，使得第一电压信号线2未延伸至靠近第一子区BB1的位置，例如第一电压信号线2为显示区AA的其他行子像素P3提供第一电压信号，并未为至少一行第一边缘子像素P1提供第一电压信号。
示例性地，如图11A所示，第二数据线32、第一电压信号线2位于相邻两条第二数据线32之间的部分、第二转接线313均位于第二源漏金属层SD2。如图11A和图22A所示，在一些示例中，显示面板1000还包括沿第一方向Y延伸的多条第二电压信号线41，第二电压信号线41例如为VDD信号线，第二电压信号线41位于第二源漏金属层SD2，例如，相邻两条第二数据线32位于相邻两条第二电压信号线41之间。在一些示例中，显示面板1000还包括沿第一方向Y延伸的多条初始化信号纵向线42，初始化信号纵向线42位于第二源漏金属层SD2，初始化信号纵向线位于相邻两条第二电压信号线之间。
这样设置，能够合理利用导电层的空间，无需单独设置用于放置第二转接线313的位置，使得在同一导电层的有限空间内，布置更多的信号线，例如使得第二源漏金属层SD2能够同时容纳第二数据线32、第一电压信号线2位于相邻两条第二数据线32之间的部分、第二转接线313，能够容纳第二电压信号线和初始化信号纵向线，从而优化了空间布局，更多的信号线对应更多的子像素，显示面板1000的像素密度得以提高，能够实现高清晰度显示。
在一些实施例中，如图7和图11A所示，相邻两条所述第一数据主线311之间设置有第一电压信号线2，至少存在两条长度不等的第一电压信号线2，位于相邻两条第一数据主线311之间的第一电压信号线2的长度大于位于相邻两条第二数据线32之间的第一电压 信号线2的长度。
相邻两条第二数据线32之间设置有第一电压信号线2和第二转接线313，第二转接线313和第一电压信号线2在所述第一方向上间隔设置，在这种情况下，由于第二转接线313占据了相邻两条第二数据线32之间的部分空间，第一电压信号线2的长度较短。
示例性地，第一数据主线311沿第一方向Y贯穿整个显示区AA，一条第一数据主线311与一列子像素连接，相邻两条第二数据线32之间设置有第一电压信号线2，位于相邻两条第二数据线32之间的第一电压信号线2可以贯穿整个显示区AA。
示例性地，第一数据主线311和第一电压信号线2位于相邻两条第一数据主线311之间的部分均位于第二源漏金属层SD2。在一些示例中，如图11A和图22A所示，显示面板1000还包括沿第一方向Y延伸的多条第二电压信号线41，第二电压信号线41例如为VDD信号线，第二电压信号线41位于第二源漏金属层SD2，例如，相邻两条第一数据主线311位于两条第二电压信号线41之间。在一些示例中，显示面板1000还包括沿第一方向Y延伸多条初始化信号纵向线，初始化信号纵向线位于第二源漏金属层SD2，初始化信号纵向线位于相邻两条第二电压信号线之间。
由于第一数据主线311所在区域无需设置第二转接线313，第一电压信号线2可以尽可能延伸至靠近第一子区BB1的位置，位于相邻两条第一数据主线311之间的第一电压信号线2的长度相比位于相邻两条第二数据线32之间的第一电压信号线2的长度更长。
以下介绍第一信号线L的另一种实施例。
如图5～图7所示，至少一条第一信号线L包括至少一条第一电压信号线2，第一电压信号线2例如为VSS信号线，第一电压信号线2包括沿第一方向Y依次连接的电压信号第一子线21和电压信号第二子线22，电压信号第一子线21相比所述电压信号第二子线22靠近所述第一子区BB1；所述电压信号第一子线21、所述电压信号第二子线22均作为所述信号子线。其中，电压信号第一子线21和所述电压信号第二子线22位于不同的导电层，电压信号第一子线21和电压信号第二子线22的连接点2a位于所述至少一行第一边缘子像素P1所在的区域。
示例性地，电压信号第一子线21位于第二导电层13，电压信号第二子线22位于第一导电层14。
如图20～图22B所示，在一些示例中，电压信号第一子线21位于第二源漏金属层SD2，电压信号第二子线22位于第一源漏金属层SD1。电压信号第一子线21和电压信号第二子线22的连接点2a位于所述至少一行第一边缘子像素P1所在的区域。
第一电压信号线2的至少部分位于显示区AA，例如电压信号第二子线22位于显示区AA，电压信号第一子线21的一部分位于显示区AA，电压信号第一子线21的另一部分位于第一子区BB1。
上述对于第一电压信号线2的走线设计，通过将第一电压信号线2分为电压信号第一子线21、所述电压信号第二子线22，且相连接的子线位于不同导电层，实现了将较长的第一电压信号线2进行拆分，第一电压信号线2在不同导电层进行跳接，相比第一电压信号线2整体均放入同一导电层中，每条子线的长度较短，且将相邻的子线设置于不同的导电层中，第一电压信号线2进行至少两次不同导电层的跳转，这样可以避免在显示面板1000的制备或使用过程中，由于走线过长导致的静电积累问题，从而避免了ESD发生的瞬间产生高电压对显示面板1000造成损伤，保证第一数据线31能够正常为子像素提供数据信号，进而保证显示效果。并且，电压信号第一子线21和电压信号第二子线22的连接点2a位于所述至少一行第一边缘子像素P1所在的区域，即尽可能将跳孔设置在靠近周边区的第一子区BB1的位置，能够避免跳孔设计对其他行子像素P3中同一膜层的图案的布局，保证显示面板的正常显示功能。
同时，显示面板1000包括至少一条第一电压信号线2，例如包括多条第一电压信号线2，多条第一电压信号线2沿第二方向X排布，且第一电压信号线2位于显示区AA，该设计称为SIP(ELVSS in pixel)设计，将多条第一电压信号线2布置在显示区AA中，能够降低走线电阻，降低第一电压信号传输时的信号损耗，从而降低显示面板1000的功耗。本公开的一些实施例提供的显示面板1000，通过对第一电压信号线2进行SIP设计，以及将第一电压信号线2分为多个子段且位于不同导电层，实现了在降低显示面板1000的功耗的基础上，解决长走线带来的ESD问题。
在一些实施例中，至少一条第一信号线L包括至少一条第一数据线31，以及至少一条第一电压信号线2，该显示面板1000基于FIP和SIP设计，可以实现在下窄边框和低功耗收益的基础上，避免长走线产生的ESD问题，解决消影，且第一数据线31中相邻子转接线的连接点设置于至少一行第一边缘子像素P1所在的区域，第一电压信号线2中相邻两个电压信号子线的连接点位于至少一行第一边缘子像素P1所在的区域，能够避免跳孔设计对显示面板正常显示的影响。
在一些实施例中，如图22B所示，显示面板1000包括至少一行第一边缘阳极Ano1，电压信号第一子线21和电压信号第二子线22的连接点2a被所述至少一行第一边缘阳极覆盖Ano1。
例如，显示面板包括一行第一边缘阳极Ano1，电压信号第一子线21和电压信号第二子线22的连接点2a与一行第一边缘阳极Ano1有交叠，例如被第一边缘阳极Ano1覆盖。
在一些实施例中，如图5～图7所示、以及图20、图21所示，显示面板1000还包括电压信号第一总线25，设置于周边区BB的第一子区BB1，第一电压信号线2的电压信号第一子线21与电压信号第一总线25连接。其中，所述电压信号第一总线25与所述电压信号第一子线21位于同一所述导电层。
示例性地，电压信号第一总线25沿第二方向X延伸，电压信号第一总线25例如位于第一源漏金属层SD1，电压信号第一子线21位于第一源漏金属层SD1，第一电压信号vss由电压信号第一总线25传输至电压信号第一子线21，再跳接至第二源漏金属层SD2的电压信号第二子线22，实现了将第一电压信号由周边区BB引入至显示区AA。
在一些实施例中，如图5～图7、以及图20～图22B所示，电压信号第一总线25、电压信号第一子线21位于同一导电层，电压信号第二子线22位于另一所述导电层。
示例性地，电压信号第一总线25、电压信号第一子线21均位于第一源漏金属层SD1，电压信号第二子线22位于第二源漏金属层SD2。
在一些实施例中，如图12、图18A和图23所示，所述第一电压信号线2还包括沿第一方向Y依次连接的电压信号第三子线23和电压信号第四子线24，电压信号第三子线23和所述电压信号第二子线22连接；电压信号第三子线23和所述电压信号第四子线24均作为信号子线。
所述多个子像素包括至少一行第二边缘子像素P2，所述至少一行第二边缘子像素P2相比其他行子像素靠P3近所述周边区的第二子区；在一些实施例中，如图12、图18A和图23所示，显示面板1000包括阵列式排布的多个子像素，所述多个子像素包括至少一行第二边缘子像素P2，至少一行第二边缘子像素P2相比其他行子像素P3靠近周边区BB的第二子区BB2。
其中，至少一行第二边缘子像素P2为靠近显示面板1000的上边框的子像素，例如为dummy子像素。dummy子像素为无需进行正常显示的子像素，其膜层结构与其他行子像素P3一致，其他行子像素P3为正常显示子像素，主要为了保证显示面板1000制备过程中膜层的均一性。
示例性地，显示面板1000沿第一方向包括依次排布的至少一行第二边缘子像素P2、多行其他行子像素P3、至少一行第一边缘子像素P1，至少一行第二边缘子像素P2和至少一行第一边缘子像素P1分别位于多行其他行子像素P3的沿第一方向的两侧。
在一些示例中，电压信号第三子线23和电压信号第二子线22的连接点2b位于所述至少一行第二边缘子像素所在区域。在另一些示例中，电压信号第三子线23和所述电压信号第二子线22的连接点2b位于所述至少一行第二边缘子像素P2所在区域，电压信号第三子线23和电压信号第四子线24的连接点2c位于所述至少一行第二边缘子像素P2所在区域。
电压信号第一子线21至少部分位于所述周边区BB的第二子区BB2，电压信号第三子线23位于所述显示区AA。
在一些示例中，如图5～图7、如图12、图18A和图23所示，显示面板还包括电压信号第二总线26，设置于周边区BB的第二子区BB2，电压信号第四子线24与所述电压信 号第二总线26连接。
如图12所示，电压信号第三子线23和所述电压信号第二子线22的连接点2b位于所述至少一行第二边缘子像素P2所在区域，电压信号第三子线23和电压信号第四子线24的连接点2c位于所述至少一行第二边缘子像素P2所在区域。在这种情况下，电压信号第三子线23位于显示区AA，电压信号第四子线24至少部分位于所述周边区BB的第二子区BB2，即位于电压信号第二总线26和显示区AA的边界之间，电压信号第四子线24的另一部分位于显示区AA。或者，如图18A和图23所示，电压信号第三子线23和电压信号第二子线22的连接点2b位于所述至少一行第二边缘子像素P2所在区域，在这种情况下，电压信号第三子线23的一部分位于显示区AA，另一部分位于第二子区BB2，电压信号第四子线24全部位于所述周边区BB的第二子区BB2，即位于电压信号第二总线26和显示区AA的边界之间。
在一些示例中，如图12、图18A和图23所示，电压信号第三子线23和电压信号第二子线22的连接点2b位于至少一行第二边缘子像素P2所在的区域。也就是说，电压信号第三子线23和电压信号第二子线22的连接点2b位于显示区AA的靠近第二子区BB2的位置，在电压信号第二子线22所在的导电层(第一源漏金属层SD1)中，仅在第二边缘子像素P2所在的区域设置有连接点2b，在其他行子像素P3所在区域无需设置跨层连接的连接点，这样能够避免跳孔的设置影响其他行子像素P3中同一膜层的图案的布局，例如压缩其他行子像素P3中第一源漏金属层SD1的图案设置空间，避免对其他行子像素P3的结构造成影响，从而保证其他行子像素P3的正常显示功能。
在一些实施例中，如图18A所示，多个子像素P中的每个子像素P包括像素电路11；所述显示面板包括阵列式排布的多个所述像素电路，所述多个像素电路包括至少一行第二边缘像素电路112，所述至少一行第二边缘像素电路112相比其他行像素电路113靠近所述第二子区BB2；所述至少一行第二边缘子像素P2所在的区域包括所述至少一行第一边缘像素电路112所在的区域。
示例性地，多个像素电路阵列排布，沿第二方向X排列成多行，沿第一方向Y排列成多列，多行像素电路中，至少一行第二边缘像素电路112为多行子像素中最靠近周边区的第二子区BB2的一行或多行像素电路，即第二边缘像素电路112靠近显示面板的上边框。在一些示例中，至少一行第二边缘像素电路112例如为可以实现正常驱动功能的像素电路，至少一行第二边缘像素电路112的功能与其他行像素电路113的功能一致，均能驱动其所连接的发光器件发光；或者，至少一行第二边缘像素电路112例如为dummy像素电路，dummy像素电路的结构与其他像素电路的结构一致，不发挥正常的驱动功能，无法驱动器所连接的发光器件发光。
在另一些示例中，如图18B所示，所述显示面板包括阵列式排布的多个阳极Ano，多 个阳极包括至少一行第二边缘阳极Ano2，所述至少一行第二边缘阳极Ano2相比其他行阳极Ano3靠近所述第二子区BB2。
所述至少一行第二边缘子像素P2所在的区域包括所述至少一行第二边缘阳极Ano2所在的区域，所述电压信号第三子线23和所述电压信号第四子线24的连接点2c被所述至少一行第二边缘阳极Ano2覆盖。
在阳极层ANO中，多个阳极阵列排布，至少一行第二边缘阳极Ano2为多行阳极中最靠近周边区的第二子区BB2的一行或多行阳极，即第二边缘阳极Ano2靠近显示面板的上边框。至少一行第二边缘阳极Ano2例如为可以正常接入阳极信号的阳极，其所对应的发光器件能够正常发光，或者，至少一行第二边缘阳极Ano2例如为dummy阳极，dummy阳极的排布、形状与其他行阳极的排布、形状一致，由于不接入信号，dummy阳极所在的发光器件不发光。
电压信号第三子线23和所述电压信号第四子线24的连接点2c为第一电压信号线2中最靠近第二子区BB2的连接点，显示面板例如仅包括一行第二边缘阳极Ano2，电压信号第三子线23和所述电压信号第四子线24的连接点2c与一行第二边缘阳极Ano2有交叠，且被第二边缘阳极Ano2覆盖。
在一些实施例中，如图12、图18A和图23所示，第一电压信号线2包括依次连接的电压信号第四子线24、电压信号第三子线23和电压信号第二子线22，电压信号第四子线24与电压信号第二总线26连接，第一电压信号vss由电压信号第二总线26传输至第一电压信号线2，引入显示区AA，电压信号第四子线24、电压信号第三子线23和电压信号第二子线22的设置可参照前述介绍。
在一些实施例中，如图6、图7和图18A所示，显示面板1000还包括沿第二方向X延伸的横向第一电压信号线29，所述横向第一电压信号线29位于至少一行第二边缘子像素P2所在的区域，且与电压信号第二子线22连接。
横向第一电压信号线29与第一电压信号线2均传输第一电压信号vss，仅延伸方向不同，横向第一电压信号线29和电压信号第二子线22的一部分均位于至少一行第二边缘子像素P2所在的区域，且横向第一电压信号线29与电压信号第二子线22连接，实现横向第一电压信号线29与第一电压信号线2传输一致的第一电压信号vss。
在一些示例中，显示面板1000包括多条第一电压信号线2，多条第一电压信号线2均与电压信号第一总线25连接，且多条第一电压信号线2的电压信号第二子线22均与一条横向第一电压信号线29连接。
通过在显示区AA设置横向第一电压信号线29，配合第一电压信号线2，可以使得整个显示面板1000的VSS信号线形成网状结构，有利于降低整体走线电阻，降低第一电压信号传输的损耗，有利于第一电压信号的传输，进一步降低显示面板1000的功耗。
在一些实施例中，如图18A所示，横向第一电压信号线29与电压信号第二子线22位于同一所述导电层，横向第一电压信号线29与电压信号第二子线22交叉设置且相连接。
示例性地，横向第一电压信号线29与电压信号第二子线22位于第一源漏金属层SD1，横向第一电压信号线29沿第二方向X延伸，电压信号第二子线22沿第一方向Y延伸，二者交叉设置，且在第一源漏金属层SD1直接相连接。在制备过程中，通过对第一源漏金属层SD1进行一次构图工艺，能够同步形成横向第一电压信号线29与电压信号第二子线22，无需通过过孔连接，简化了工艺。
在一些实施例中，结合图18A、图20和图21，第一电压信号线2包括沿第一方向Y依次连接的电压信号第一子线21、电压信号第二子线22、电压信号第三子线23和电压信号第四子线24，电压信号第三子线23和电压信号第四子线24位于不同的导电层，例如，电压信号第一子线21和电压信号第三子线23位于第一导电层14，电压信号第二子线22和电压信号第四子线24位于第二导电层13。
电压信号第二总线26沿第二方向X延伸，电压信号第二总线26传输第一电压信号vss，第一电压信号vss由电压信号第二总线26传输至电压信号第四子线24，传输至电压信号第三子线23，实现了将第一电压信号由周边区BB引入至显示区AA。显示面板1000包括位于第二子区BB2的电压信号第二总线26和位于第一子区BB1的电压信号第一总线25，第一电压信号线2的一端连接第二子区BB2的电压信号第二总线26，另一端连接位于第一子区BB1的电压信号第一总线25，第一电压信号vss通过电压信号第一总线25和电压信号第二总线26同时传输至第一电压信号线2，实现将第一电压信号更稳定地接入显示区AA，信号损耗更低。
在一些实施例中，如图18A、图20和图21所示，电压信号第一子线21和电压信号第三子线23位于同一所述导电层，电压信号第二总线26、电压信号第二子线22和电压信号第四子线24位于另一所述导电层。
示例性地，电压信号第一子线21和电压信号第三子线23位于第一源漏金属层SD1，电压信号第二总线26、电压信号第二子线22和电压信号第四子线24位于第二源漏金属层SD2。
在一些实施例中，如图18A、图20和图21所示，电压信号第一子线21位于所述周边区BB的第一子区BB1，即在第一电压信号线2包括依次连接的电压信号第一子线21、电压信号第二子线22、电压信号第三子线23和电压信号第四子线24的情况下，电压信号第二子线22沿第一方向Y延伸至显示区AA的边界，电压信号第一子线21位于显示区AA的边界和电压信号第一总线25之间，电压信号第三子线23沿第一方向Y延伸至显示区AA的边界，电压信号第四子线24位于显示区AA的边界和电压信号第二总线26之间。
在一些示例中，如图11A所示，在第二转接线313位于相邻两条所述第二数据线32 之间，相邻两条第二数据线32之间还设置有第一电压信号线2的情况下，结合图18A，第一电压信号线2包括依次连接的电压信号第四子线24、电压信号第三子线23和电压信号第二子线22，且电压信号第三子线23未延伸至显示区AA的边界，即第一电压信号线2不包括电压信号第一子线21，例如电压信号第二子线22延伸至显示区AA中至少一行第一边缘子像素P1与其他行子像素P3的交界位置。
在另一些示例中，如图11A所示，在相邻两条所述第一数据主线311之间设置有第一电压信号线2的情况下，结合图18A、图20和图21，第一电压信号线2包括依次连接的电压信号第一子线21、电压信号第二子线22、电压信号第三子线23和电压信号第四子线24，第一电压信号线2由第二子区BB2延伸至显示区AA，再延伸至第一子区BB1。
在一些实施例中，如图2～图7、图13、图19和图24、图25所示，周边区BB包括两个第三子区BB3，两个第三子区BB3分别位于所述显示区AA在第二方向X上的两侧。
显示面板1000还包括电压信号第三总线27，位于所述周边区BB的至少一个第三子区BB3；电压信号第三总线27可以包括一条，位于一个第三子区BB3，例如位于显示面板1000的左边框区，电压信号第三总线27可以包括两条，分别位于两个第三子区BB3，例如分别位于显示面板1000的左边框区和右边框区。电压信号第三总线27传输第一电压信号vss。
显示面板1000还包括至少一条电压转接线28，位于第三子区BB3，且位于电压信号第三总线27和显示区AA之间；所述电压转接线28沿第二方向X延伸，电压转接线28的第一端与电压信号第三总线27连接，电压转接线28的第二端与最靠近所述电压信号第三总线27的所述第一电压信号线2连接。
例如，显示面板1000包括位于一个第三子区BB3的电压转接线28，例如电压转接线28位于显示面板1000的左边框区，或者，显示面板1000包括分别位于两个第三子区BB3的电压转接线28，例如至少一条电压转接线28位于显示面板1000的左边框区，例如电压转接线28位于显示面板1000的右边框区。如图13、图19所示，电压转接线28的第二端与最靠近所述电压信号第三总线27的一条所述第一电压信号线2连接，最靠近所述电压信号第三总线27的一条所述第一电压信号线2例如为靠近显示区AA的边界的第一电压信号线2。
通过电压转接线28将电压信号第三总线27与最靠近所述电压信号第三总线27的至少一条所述第一电压信号线2连接，实现了将周边区BB的第一电压信号vss引入显示区AA，第一电压信号vss能够实现多路传输，有利于降低信号损耗。
如图24和图25所示，显示面板1000还包括多条外围信号线51，外围信号线51沿第一方向Y延伸，且位于电压信号第三总线27和最靠近所述电压信号第三总线27的所述第一电压信号线2之间，即外围信号线51位于电压信号第三总线27和显示区AA之间，所 述电压转接线28的第二端与至少一条外围信号线51连接，此时，外围信号线51也传输第一电压信号vss。
在显示区周围设置外围信号线51，且外围信号线51在显示区AA周围形成环状连接，可以防止外围静电破坏显示区，第三总线27与外围信号线51连接，外围信号线51也可以稍微分担周边区BB的vss电流，降低跨压功耗。
在一些示例中，电压信号第三总线27与电压转接线28位于不同的导电层，电压转接线28和第一电压信号线2位于不同的所述导电层。
例如，如图13、图19和图24、图25所示，电压信号第三总线27位于第二源漏金属层SD2，电压转接线28位于第一源漏金属层SD1，第一电压信号线2位于第二源漏金属层SD2。通过将相连接的电压信号第三总线27、电压转接线28和第一电压信号线2两两设置位于不同的导电层，能够避免三者均位于同一导电层造成的走线长度过长，导致的ESD问题。
在一些示例中，电压信号第三总线27与电压转接线28位于不同的导电层，电压转接线28和外围信号线51位于不同的所述导电层。
例如，如图13、图19和图24、图25所示，电压信号第三总线27位于第二源漏金属层SD2，电压转接线28位于第一源漏金属层SD1，外围信号线51位于第二源漏金属层SD2。通过将相连接的电压信号第三总线27、电压转接线28和外围信号线51两两设置位于不同的导电层，能够避免三者均位于同一导电层造成的走线长度过长，导致的ESD问题。
在一些实施例中，如图6、图7、图13、图19所示，显示面板1000还包括沿所述第二方向延伸的横向第一电压信号线29，横向第一电压信号线29位于所述显示区AA；横向第一电压信号线29与电压转接线28连接。
横向第一电压信号线29例如与位于显示区AA一侧的电压转接线28连接，或者，横向第一电压信号线29的两端分别与位于显示区AA两侧的电压转接线28连接，电压信号第三总线27通过电压转接线28与横向第一电压信号线29连接，将第一电压信号vss由周边区BB引入显示区AA，实现了第一电压信号的多路传输，有利于降低走线阻抗，减少信号传输损耗，降低显示面板1000功耗。
在一些实施例中，电压转接线28与横向第一电压信号线29位于同一所述导电层，例如，电压转接线28与横向第一电压信号线29均位于第一源漏金属层SD1。
在一些实施例中，如图5～图7所示，显示面板1000包括电压信号第一总线25、电压信号第二总线26和两条电压信号第三总线27，电压信号第一总线25、一条电压信号第三总线27、电压信号第二总线26和另一条条电压信号第三总线27依次连接且首尾连接，形成围绕显示区AA的环形总线，其中，在一些示例中，电压信号第一总线25和两条电压信 号第三总线27位于第二源漏金属层SD2，电压信号第二总线26位于第一源漏金属层SD1。在一些示例中，电压信号第一总线25和电压信号第二总线26均位于第一源漏金属层SD1或者均位于第二源漏金属层SD2。
如图26所示，本公开的一些实施例还提供一种显示装置10000，显示装置包括如上所述的显示面板1000。
示例性地，显示装置可以是显示不论运动的(例如，视频)还是固定的(例如，静止图像)，且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置包括但不限于电视、移动电话、可穿戴设备、个人数字助理(Personal Digital Assistant，PDA)、增强现实(Augmented Reality，AR)设备、虚拟现实(Virtual Reality，VR)设备、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、时钟、计算器、电视监视器、平板显示器、计算机监视器、车载显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。示例性地，如图26所示，显示装置10000可以为手机。
显示装置包括如上所述的显示面板1000，显示装置的有益效果与显示面板1000的有益效果一致，即显示装置中不易出现长走线造成的ESD现象，同时，该显示装置具备窄边框和低功耗的优势。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种显示面板，具有显示区和围绕所述显示区的周边区；所述周边区包括第一子区和第二子区，所述第一子区和所述第二子区分别位于所述显示区在第一方向上的两侧；
    所述显示面板包括：
    衬底；
    层叠设置于所述衬底一侧的至少两个导电层；
    至少一条第一信号线，所述第一信号线的至少部分在所述显示区内沿所述第一方向延伸设置；所述第一信号线包括依次连接的至少两条信号子线，任意相邻的两条所述信号子线分别位于所述至少两个导电层中不同的导电层中；
    所述显示面板包括阵列式排布的多个子像素，所述多个子像素包括至少一行第一边缘子像素，所述至少一行第一边缘子像素相比其他行子像素靠近所述周边区的第一子区；相邻的两条信号子线的连接点位于所述至少一行第一边缘子像素所在的区域。
  2. 根据权利要求1所述的显示面板，其中，所述多个子像素中的每个子像素包括像素电路；所述显示面板包括阵列式排布的多个所述像素电路，所述多个像素电路包括至少一行第一边缘像素电路，所述至少一行第一边缘像素电路相比其他行像素电路靠近所述第一子区；
    所述至少一行第一边缘子像素所在的区域包括所述至少一行第一边缘像素电路所在的区域。
  3. 根据权利要求1所述的显示面板，其中，所述多个子像素中的每个子像素包括发光器件；所述显示面板包括阵列式排布的多个阳极，所述多个阳极包括至少一行第一边缘阳极，所述至少一行第一边缘阳极相比其他行阳极靠近所述第一子区；
    所述至少一行第一边缘子像素所在的区域包括所述至少一行第一边缘阳极所在的区域，所述相邻的两条信号子线的连接点与所述至少一行第一边缘阳极有交叠。
  4. 根据权利要求1～3中任一项所述的显示面板，其中，所述至少一条第一信号线包括至少一条第一数据线，所述第一数据线包括位于所述显示区且依次连接的第一数据主线、第一转接线和第二转接线，所述第二转接线包括依次连接的至少两条子转接线，所述至少两条子转接线作为所述信号子线；
    所述第一数据主线和所述第二转接线沿所述第一方向延伸，所述第一数据主线相比所述第二转接线远离所述显示面板的沿所述第一方向的中线；
    所述第一转接线沿第二方向延伸，所述第二方向与所述第一方向相交叉；
    其中，所述第一数据主线和所述第一转接线位于不同的所述导电层中，所述第一转接线和所述第二转接线中与所述第一转接线连接的子转接线位于不同的所述导电层中；相邻的两条子转接线位于不同的所述导电层中；
    相邻的两条子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
  5. 根据权利要求4所述的显示面板，其中，所述第二转接线包括在所述第一方向上依次连接的第一子转接线和第二子转接线，所述第一子转接线相比所述第二子转接线靠近所述第一子区；
    所述第一子转接线和所述第二子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
  6. 根据权利要求4所述的显示面板，其中，所述第二转接线包括在所述第一方向上依次连接的第一子转接线、第二子转接线、第三子转接线和第四子转接线，所述第一子转接线相比所述第二子转接线靠近所述第一子区；
    所述第一子转接线和所述第二子转接线的连接点位于所述至少一行第一边缘子像素所在的区域；
    和/或，所述第二子转接线和所述第三子转接线的连接点位于所述至少一行第一边缘子像素所在的区域；
    和/或，所述第三子转接线和所述第四子转接线的连接点位于所述至少一行第一边缘子像素所在的区域。
  7. 根据权利要求5或6所述的显示面板，其中，所述显示面板包括至少一行第一边缘阳极，所述第一子转接线和所述第二子转接线的连接点被所述至少一行第一边缘阳极覆盖。
  8. 根据权利要求4～7中任一项所述的显示面板，还包括：
    位于所述周边区的第一子区的至少一条第一扇出走线，所述第一扇出走线与所述第一数据线的第二转接线的一条子转接线连接；
    其中，所述第一扇出走线与所连接的子转接线分别位于不同的所述导电层。
  9. 根据权利要求4～8中任一项所述的显示面板，其中，还包括：
    至少一条第二数据线，所述第二数据线沿所述第一方向延伸；所述至少一条第一数据线相比所述至少一条第二数据线远离所述显示面板的沿所述第一方向的中线；
    位于所述周边区的第一子区的至少一条第二扇出走线，所述第二扇出走线与所述第二数据线连接；
    其中，所述第二转接线位于相邻两条所述第二数据线之间，相邻两条所述第二数据线之间还设置有第一电压信号线，所述第二转接线和所述第一电压信号线在所述第一方向上间隔设置。
  10. 根据权利要求9所述的显示面板，其中，相邻两条所述第一数据主线之间设置有第一电压信号线，至少存在两条长度不等的第一电压信号线，位于相邻两条所述第一数据主线之间的第一电压信号线的长度大于位于相邻两条所述第二数据线之间的第一电压信号线的长度。
  11. 根据权利要求1～8中任一项所述的显示面板，其中，所述至少一条第一信号线包 括至少一条第一电压信号线，所述第一电压信号线包括沿所述第一方向依次连接的电压信号第一子线和电压信号第二子线，所述电压信号第一子线相比所述电压信号第二子线靠近所述第一子区；所述电压信号第一子线和所述电压信号第二子线均作为所述信号子线；
    其中，所述电压信号第一子线和所述电压信号第二子线位于不同的所述导电层，所述电压信号第一子线和所述电压信号第二子线的连接点位于所述至少一行第一边缘子像素所在的区域。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板包括至少一行第一边缘阳极，所述电压信号第一子线和所述电压信号第二子线的连接点被所述至少一行第一边缘阳极覆盖。
  13. 根据权利要求11或12所述的显示面板，还包括：
    电压信号第一总线，设置于所述周边区的第一子区，所述第一电压信号线的电压信号第一子线与所述电压信号第一总线连接；
    其中，所述电压信号第一总线与所述电压信号第一子线位于同一所述导电层。
  14. 根据权利要求11～13中任一项所述的显示面板，其中，所述第一电压信号线还包括沿所述第一方向依次连接的电压信号第三子线和电压信号第四子线，所述电压信号第三子线和所述电压信号第二子线连接；所述电压信号第三子线和所述电压信号第四子线均作为所述信号子线；
    所述多个子像素包括至少一行第二边缘子像素，所述至少一行第二边缘子像素相比其他行子像素靠近所述周边区的第二子区；
    所述电压信号第三子线和所述电压信号第二子线的连接点位于所述至少一行第二边缘子像素所在区域；或者，所述电压信号第三子线和所述电压信号第二子线的连接点位于所述至少一行第二边缘子像素所在区域，所述电压信号第三子线和所述电压信号第四子线的连接点位于所述至少一行第二边缘子像素所在区域。
  15. 根据权利要求14所述的显示面板，其中，所述显示面板包括阵列式排布的多个阳极，所述多个阳极包括至少一行第二边缘阳极，所述至少一行第二边缘阳极相比其他行阳极靠近所述第二子区；
    所述至少一行第二边缘子像素所在的区域包括所述至少一行第二边缘阳极所在的区域，所述电压信号第三子线和所述电压信号第四子线的连接点被所述至少一行第二边缘阳极覆盖。
  16. 根据权利要求14或15所述的显示面板，还包括：
    沿第二方向延伸的横向第一电压信号线，所述横向第一电压信号线位于所述至少一行第二边缘子像素所在的区域，且与所述电压信号第三子线连接。
  17. 根据权利要求14～16中任一项所述的显示面板，其中，
    所述显示面板还包括电压信号第二总线，设置于所述周边区的第二子区，所述电压信号第四子线与所述电压信号第二总线连接；
    所述电压信号第一子线和所述电压信号第三子线位于同一所述导电层，所述电压信号第二总线、所述电压信号第二子线和所述电压信号第四子线位于另一所述导电层。
  18. 一种显示装置，包括如权利要求1～17中任一项所述的显示面板。
PCT/CN2024/100242 2024-05-07 2024-06-19 显示面板及显示装置 Pending WO2025231968A1 (zh)

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