WO2025217879A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置

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Publication number
WO2025217879A1
WO2025217879A1 PCT/CN2024/088618 CN2024088618W WO2025217879A1 WO 2025217879 A1 WO2025217879 A1 WO 2025217879A1 CN 2024088618 W CN2024088618 W CN 2024088618W WO 2025217879 A1 WO2025217879 A1 WO 2025217879A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel
test
data
adapter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/088618
Other languages
English (en)
French (fr)
Other versions
WO2025217879A9 (zh
Inventor
王远果
屈忆
张波
徐鹏
魏立恒
王威
廖茂颖
李斌
冯翱远
初志文
牛戈
李祥艺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202480000756.8A priority Critical patent/CN121176185A/zh
Priority to PCT/CN2024/088618 priority patent/WO2025217879A1/zh
Publication of WO2025217879A1 publication Critical patent/WO2025217879A1/zh
Publication of WO2025217879A9 publication Critical patent/WO2025217879A9/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device.
  • OLED Organic light-emitting diodes
  • QLED quantum-dot light-emitting diodes
  • This embodiment provides a display substrate and a display device.
  • this embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data transfer lines, a plurality of data lead-out lines, a plurality of data contact pads, and a plurality of transfer units.
  • the substrate comprises a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising: a first signal access area and a wiring lead-out area located between the first signal access area and the display area.
  • a plurality of sub-pixels are arranged on one side of the substrate and located in the display area.
  • a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines.
  • a plurality of data lead-out lines are located in the wiring lead-out area.
  • a plurality of data contact pads are located in the first signal access area.
  • Multiple groups of first adapter units and multiple groups of second adapter units are located in the wiring lead-out area, the multiple groups of first adapter units are located on a side of the multiple groups of second adapter units away from the display area, the multiple groups of first adapter units are arranged along a second direction, and the multiple groups of second adapter units are arranged along the second direction, with the second direction intersecting the first direction.
  • the multiple data lead-out lines are connected to the multiple data contact pads through the multiple groups of first adapter units, and are also connected to the multiple second data lines and the multiple data connection lines through the multiple groups of second adapter units, such that the order of data signals provided by the multiple data contact pads matches the order of data signals required by the multiple second data lines and the multiple data connection lines arranged along the second direction.
  • each group of first adapter units includes: m first connection terminals, m second connection terminals, and m first adapter wires; each first adapter wire is connected between a first connection terminal and a second connection terminal; each first connection terminal is connected to a data lead wire, and each second connection terminal is connected to a data contact pad; the m first connection terminals are arranged along the second direction and correspond to different first arrangement numbers, and the m second connection terminals are arranged along the second direction and correspond to different second arrangement numbers.
  • the m first adapter wires in each group of first adapter units include: a plug-in sequence adapter wires, the first arrangement number corresponding to the first connection terminal connected to each plug-in sequence adapter wire is different from the second arrangement number corresponding to the second connection terminal connected to it; m and a are both integers greater than 1, and m is greater than or equal to a. Wherein, the second direction intersects with the first direction.
  • the a-patch cables in each group of the first patch unit include: a1 first-patch cable and a2 second-patch cable, a1 and a2 are both integers greater than 0, and the sum of a1 and a2 is a; the first arrangement number corresponding to the first connection end connected to the first patch cable is less than the second arrangement number corresponding to the second connection end connected to the first patch cable; the first arrangement number corresponding to the first connection end connected to the second patch cable is greater than The second arrangement sequence number corresponding to the connected second connection end.
  • the difference between the second arrangement number corresponding to the second connection end connected to the first plug-in sequence adapter cable and the first arrangement number corresponding to the first connection end connected thereto is greater than or equal to the difference between the first arrangement number corresponding to the first connection end connected to the second plug-in sequence adapter cable and the second arrangement number corresponding to the second connection end connected thereto.
  • an orthographic projection of the first plug-in sequence patch cord on the substrate overlaps with an orthographic projection of at least one second plug-in sequence patch cord on the substrate.
  • the m adapter wires within each group of first adapter units further include: b first-sequence adapter wires, the first arrangement number corresponding to the first connection end connected to each first-sequence adapter wire is the same as the second arrangement number corresponding to the second connection end connected to it; b is an integer greater than 1, and b is less than or equal to a.
  • the b first-sequence patch cords and the first plug-in sequence patch cord are in the same layer structure, or at least one first-sequence patch cord is located on a side of the first plug-in sequence patch cord and the second plug-in sequence patch cord close to the substrate.
  • each group of first transfer units includes: eight first connection terminals, eight second connection terminals, and eight first transfer lines; the eight first connection terminals are arranged in sequence along the second direction, the eight second connection terminals are arranged in sequence along the second direction and are located on the side of the eight first connection terminals close to the first signal access area, and the eight first transfer lines include two first-sequence transfer lines, two second-sequence transfer lines, and four first-sequence transfer lines; the first-sequence transfer line is configured to connect the i-th first connection terminal with the i+1-th second connection terminal; the second-sequence transfer line is configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the values of i include: 1, 5.
  • a pixel unit located in the display area includes: a first subpixel emitting a first color light, a second subpixel emitting a second color light, and two third subpixels emitting a third color light.
  • the plurality of data contact pads are configured to provide data signals to subpixels of pixel units in the e-th row within the display area during a first time period, and to provide data signals to subpixels of pixel units in the e+1-th row within the display area during a second time period, where e is an integer greater than 0.
  • the data signals transmitted by the eight second connection terminals within each group of first adapter units are configured to correspond to the third subpixel, the first subpixel, the second subpixel, the third subpixel, the third subpixel, the second subpixel, the first subpixel, and the third subpixel, or to correspond to the first subpixel, the third subpixel, the third subpixel, the second subpixel, the third subpixel, the third subpixel, and the first subpixel, respectively.
  • the data signals transmitted by the eight second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence.
  • Each group of first adapter units includes: twelve first connection terminals, twelve second connection terminals, and twelve first adapter cables; the twelve first connection terminals are arranged sequentially along the second direction, the twelve second connection terminals are arranged sequentially along the second direction and are located on a side of the twelve first connection terminals close to the first signal access area, the twelve first adapter cables include four first-order plug-in adapter cables, four second-order plug-in adapter cables, and four first-order plug-in adapter cables; the first-order plug-in adapter cable is configured to connect the i-th first connection terminal with the i+1-th second connection terminal; the second-order plug-in adapter cable is configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i includes: 1, 3, 7, and 9.
  • a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light.
  • the plurality of data contact pads are configured to provide data signals to sub-pixels of pixel units in the e-th row within the display area in a first period, and to provide data signals to sub-pixels of pixel units in the e+1-th row within the display area in a second period. signal, wherein e is an integer greater than 0.
  • the data signals transmitted by the twelve second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, and the first sub-pixel in sequence.
  • the data signals transmitted by the twelve second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel and the second sub-pixel in sequence.
  • Each group of first adapter units includes: sixteen first connection terminals, sixteen second connection terminals, and sixteen first adapter lines; the sixteen first connection terminals are arranged sequentially along the second direction, the sixteen second connection terminals are arranged sequentially along the second direction and are located on a side of the sixteen first connection terminals close to the first signal access area, the sixteen first adapter lines include four first-pitch sequence adapter lines, four second-pitch sequence adapter lines, and eight first-sequence adapter lines; the first-pitch sequence adapter line is configured to connect the i-th first connection terminal with the i+1-th second connection terminal; the second-pitch sequence adapter line is configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i includes: 1, 3, 9, and 11.
  • a pixel unit located in the display area includes: a first subpixel emitting a first color light, a second subpixel emitting a second color light, and two third subpixels emitting a third color light.
  • the plurality of data contact pads are configured to provide data signals to subpixels of pixel units in an e-th row within the display area during a first time period, and to provide data signals to subpixels of pixel units in an e+1-th row within the display area during a second time period, where e is an integer greater than 0.
  • the data signals transmitted by the sixteen second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel
  • the data signals transmitted by the sixteen second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third ... and the second sub-pixel in sequence.
  • Each group of first adapter units includes: twenty first connection terminals, twenty second connection terminals, and twenty first adapter lines; the twenty first connection terminals are arranged sequentially along the second direction, the twenty second connection terminals are arranged sequentially along the second direction and are located on a side of the twenty first connection terminals close to the first signal access area, the twenty first adapter lines include six first-order plug-in adapter lines, six second-order plug-in adapter lines, and eight first-order plug-in adapter lines; the first-order plug-in adapter line is configured to connect the i-th first connection terminal with the i+1-th second connection terminal; the second-order plug-in adapter line is configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i includes: 1, 3, 5, 11, 13, and 15.
  • a pixel unit located in the display area includes: a pixel unit emitting a first color
  • the plurality of data contact pads are configured to provide data signals to sub-pixels of pixel units in the e-th row within the display area during a first period, and to provide data signals to sub-pixels of pixel units in the e+1-th row within the display area during a second period, where e is an integer greater than 0.
  • the data signals transmitted by the twenty second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the second sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel and the third sub-pixel in sequence; or, are configured to correspond to the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel
  • the data signals transmitted by the sixteen second connection terminals in each group of first adapter units are configured to correspond to the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel and the third sub-pixel in sequence, or are configured to correspond to the second sub-pixel, the third sub-pixel, the first sub-pixel, the third sub-pixel, the third sub-pixel, the second sub-pixel, the third sub-pixel, the first sub-pixel, the first sub-pixel, the third sub-pixel, the second sub-pixel, the third ... and the second sub-pixel in sequence.
  • a pixel unit located in the display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light.
  • the plurality of data lead lines connected to the plurality of groups of first connection ends of the first adapter units include: a first group of data lead lines and a second group of data lead lines, wherein the first group of data lead lines and the second group of data lead lines are located in different conductive layers and are alternately arranged along the second direction.
  • the first group of data lead lines is configured to transmit data signals required by the third sub-pixel
  • the second group of data lead lines is configured to transmit data signals required by the first and second sub-pixels.
  • the display substrate further comprises: a plurality of test circuits located in the routing lead-out region and arranged sequentially along a second direction; the plurality of test circuits located in the first direction on a side of the plurality of first adapter units away from the first signal access region; wherein a group of test circuits is connected to m data lead-out lines connected to a group of first adapter units; the second direction intersects the first direction; each group of test circuits comprises: a first test circuit and b second test circuits; twice the sum of a and b equals m, and a and b are both integers greater than 0.
  • the first test circuit comprises: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected to a first test control line, the first electrode of the first test transistor is connected to a first test data line, the gate of the second test transistor is connected to a second test control line, the first electrode of the second test transistor is connected to a second test data line, and the second electrodes of the first test transistor and the second test transistor are connected to the same data lead-out line; the gate of the third test transistor is connected to a third test control line, and the first electrode of the third test transistor is connected to a third test data line.
  • the second test circuit includes: a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected to the second test control line, the first electrode of the fourth test transistor is connected to the first test data line, the gate of the fifth test transistor is connected to the first test control line, the first electrode of the fifth test transistor is connected to the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected to the same data lead-out line; the gate of the sixth test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line; the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor and the second electrode of the sixth test transistor are connected to different data lead-out lines.
  • the first test transistor, the second test transistor, and the The third test transistor is arranged along the first direction; the fourth test transistor, the fifth test transistor, and the sixth test transistor of the second test circuit are arranged along the first direction.
  • the first test transistor and the fourth test transistor are aligned in the second direction, the second test transistor and the fifth test transistor are aligned in the second direction, and the third test transistor and the sixth test transistor are aligned in the second direction.
  • Each group of test circuits includes: two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits, and one first test circuit are arranged along the second direction.
  • Each group of test circuits includes: three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, or two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits, and one first test circuit are arranged in a direction opposite to the second direction.
  • Each group of test circuits includes: four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits, and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit, and one first test circuit are arranged in a direction opposite to the second direction.
  • Each group of test circuits includes: five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits, and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit, and one first test circuit are arranged in a direction opposite to the second direction.
  • a single pixel unit of the display area includes: c sub-pixels, m is k times of c, and k is an integer greater than 1.
  • this embodiment provides a display device including the display substrate as described above.
  • this embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, and a plurality of test circuits.
  • the substrate comprises: a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising: a first signal access area and a wiring lead-out area located between the first signal access area and the display area.
  • a plurality of sub-pixels are arranged on one side of the substrate and located in the display area.
  • a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines.
  • a plurality of data lead-out lines are located in the wiring lead-out area, and the plurality of data lead-out lines are connected to the plurality of second data lines and the plurality of data connection lines.
  • Multiple groups of test circuits are located in the routing lead-out area and arranged sequentially along a second direction.
  • Each group of test circuits is connected to m consecutively arranged data lead-out lines, and the second direction intersects the first direction; m is an integer greater than 1.
  • Each group of test circuits includes: a first test circuit and b second test circuits, where a and b are both integers greater than 0, and twice the sum of a and b equals m.
  • the first test circuit includes: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected to a first test control line, the first electrode of the first test transistor is connected to a first test data line, the gate of the second test transistor is connected to a second test control line, the first electrode of the second test transistor is connected to a second test data line, and the second electrodes of the first test transistor and the second electrode of the second test transistor are connected to the same data lead-out line; the gate of the third test transistor is connected to a third test control line, and the first electrode of the third test transistor is connected to a third test data line.
  • the second test circuit includes: a fourth test transistor, a fifth test transistor and a sixth test transistor; the gate of the fourth test transistor is connected to the second test control line, the first electrode of the fourth test transistor is connected to the first test data line, the gate of the fifth test transistor is connected to the first test control line, the first electrode of the fifth test transistor is connected to the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected to the same data lead-out line; the gate of the sixth test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line; the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor and the second electrode of the sixth test transistor are connected to different data lead-out lines.
  • the first test transistor, the second test transistor, and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor, and the sixth test transistor of the second test circuit are arranged along the first direction.
  • the first test transistor and the fourth test transistor are aligned in the second direction, the second test transistor and the fifth test transistor are aligned in the second direction, and the third test transistor and the sixth test transistor are aligned in the second direction.
  • Each group of test circuits includes: two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits, and one first test circuit are arranged along the second direction.
  • Each group of test circuits includes: three first test circuits and three second test circuits; wherein one first test circuit, two second test circuits, or two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits, and one first test circuit are arranged in a direction opposite to the second direction.
  • Each group of test circuits includes: four first test circuits and four second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits, and one second test circuit are arranged along the second direction; or one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit, and one first test circuit are arranged in a direction opposite to the second direction.
  • Each group of test circuits includes: five first test circuits and five second test circuits; wherein one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits, and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit, and one first test circuit are arranged in a direction opposite to the second direction.
  • FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure.
  • FIG2 is a schematic diagram of a first border area according to at least one embodiment of the present disclosure.
  • FIG3A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure
  • FIG3B is another partial cross-sectional schematic diagram of the display area of at least one embodiment of the present disclosure.
  • FIG4 is a schematic diagram of an arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure
  • FIG5 is a schematic diagram of local wiring in a first border area according to at least one embodiment of the present disclosure
  • FIG6 is a schematic diagram of multiple groups of first-side first adapter units according to at least one embodiment of the present disclosure
  • FIG7A is a schematic diagram of the first gate metal layer and the second gate metal layer in FIG6 ;
  • FIG7B is a schematic diagram of the first source/drain metal layer in FIG6 ;
  • FIG7C is a schematic diagram of the second source/drain metal layer in FIG6 ;
  • FIG8 is a schematic partial cross-sectional view along the Q-Q' direction in FIG6;
  • 9A and 9B are schematic diagrams showing the principle of inserting sequence of data signals transmitted by the second connection end of a group of first-side first adapter units shown in FIG. 6 ;
  • FIG10 is a schematic diagram of multiple sets of second-side first adapter units according to at least one embodiment of the present disclosure
  • FIG11 is a schematic diagram showing the principle of inserting a sequence of data signals transmitted by the second connection ends of a group of first adapter units on the second side shown in FIG10 ;
  • FIG12 is a schematic diagram of a group of first-side second adapter units according to at least one embodiment of the present disclosure
  • FIG13 is an equivalent circuit diagram of a first test circuit and a second test circuit according to at least one embodiment of the present disclosure
  • FIG14A is a schematic plan view of a first set of test circuits according to at least one embodiment of the present disclosure
  • FIG14B is a schematic diagram of the first source/drain metal layer in FIG14A ;
  • FIG14C is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG14A ;
  • FIG15 is an equivalent circuit diagram of a third test circuit according to at least one embodiment of the present disclosure.
  • FIG16 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • FIG17 is a schematic diagram of the first gate metal layer and the second gate metal layer in FIG16 ;
  • FIG18 is a schematic diagram illustrating the principle of inserting a sequence of data signals transmitted by the second connection end of a group of first-side first adapter units shown in FIG16 ;
  • FIG19 is a schematic diagram of a group of first-side second adapter units according to at least one embodiment of the present disclosure.
  • FIG20 is a schematic plan view of a first set of test circuits according to at least one embodiment of the present disclosure.
  • FIG21 is a schematic diagram of a group of second-side first adapter units according to at least one embodiment of the present disclosure
  • FIG22 is a schematic diagram illustrating the principle of inserting a sequence of data signals transmitted by the second connection terminals of a group of first adapter units on the second side shown in FIG21 ;
  • FIG23 is a schematic plan view of a second set of test circuits according to at least one embodiment of the present disclosure.
  • FIG24 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • FIG25 is a schematic diagram illustrating the principle of inserting and sequencing data signals transmitted by the second connection terminals of a group of first-side first adapter units shown in FIG24 ;
  • FIG26 is a plan view of a first set of test circuits corresponding to a set of first-side first adapter units shown in FIG24 ;
  • FIG27 is a schematic diagram of a group of second-side first adapter units according to at least one embodiment of the present disclosure
  • FIG28 is a schematic diagram illustrating the principle of inserting a sequence of data signals transmitted by the second connection terminals of a group of first adapter units on the second side shown in FIG27 ;
  • FIG29 is a schematic plan view of a second set of test circuits according to at least one embodiment of the present disclosure.
  • FIG30 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • FIG31 is a schematic diagram illustrating the principle of inserting a sequence of data signals transmitted by the second connection end of a group of first-side first adapter units shown in FIG30 ;
  • FIG32 is a plan view of a first group of test circuits corresponding to a group of first adapter units on the first side shown in FIG30 ;
  • FIG33 is a schematic diagram of a group of second-side first adapter units according to at least one embodiment of the present disclosure
  • FIG34 is a schematic diagram illustrating the principle of inserting and sequencing data signals transmitted by the second connection terminals of a group of first adapter units on the second side shown in FIG33 ;
  • FIG35 is a schematic plan view of a second set of test circuits according to at least one embodiment of the present disclosure.
  • 36A to 36C are diagrams illustrating exemplary connection methods of multiple first adapter units according to at least one embodiment of the present disclosure
  • FIG37 is a schematic diagram showing another arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure.
  • 38A to 38F are diagrams illustrating exemplary connection methods of multiple first adapter units according to at least one embodiment of the present disclosure
  • FIG39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • orientation or positional relationships such as “middle,” “upper,” “lower,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings.
  • This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure.
  • the positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.
  • connection can include “electrical connection”, and “electrical connection” can include the situation where constituent elements are connected together through an element with some electrical function.
  • elements with some electrical function There is no special restriction on “elements with some electrical function” as long as they can transmit electrical signals between connected constituent elements. Examples of “elements with some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.
  • a transistor refers to an element having at least three terminals: a gate (gate electrode), a drain, and a source.
  • a transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source.
  • the channel region refers to a region through which current mainly flows.
  • the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain.
  • the gate electrode can also be referred to as a control electrode.
  • parallel refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.
  • circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.
  • a extends along direction B means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions.
  • a extends along direction B means “the main portion of A extends along direction B.”
  • a and B are in the same layer
  • a and B are formed simultaneously through the same patterning process.
  • “Same layer” does not always mean that the thickness or height of the layer is the same in a cross-sectional view.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.
  • Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure.
  • the display substrate may be a closed polygon including linear edges.
  • the display substrate may include: a display area AA and a frame area BB located around the display area AA.
  • the display area AA may include: a first display edge (lower display edge) and a second display edge (upper display edge) arranged opposite to each other in a first direction D1, and a third display edge (left display edge) and a fourth display edge (right display edge) arranged opposite to each other in a second direction D2.
  • the first display edge and the second display edge may be linear edges parallel to each other, and the third display edge and the fourth display edge may be linear edges parallel to each other. Adjacent linear edges may be connected by curved edges (e.g., arcuate edges).
  • the border area BB may include: a first border area B1 and a fourth border area B4 located on both sides of the display area AA along the first direction D1, and a second border area B2 and a third border area B3 located on both sides of the display area AA along the second direction D2.
  • the first border area B1 may connect to the first display edge
  • the second border area B2 may connect to the third display edge
  • the third border area B3 may connect to the fourth display edge
  • the fourth border area B4 may connect to the second display edge.
  • the first border area B1 may be connected to the second border area B2 and the third border area B3, and the third border area B4 may be connected to the second border area B2 and the third border area B3.
  • the first border area B1 may also be referred to as the lower border area of the display substrate
  • the second border area B2 may also be referred to as the left border area of the display substrate
  • the third border area B3 may also be referred to as the right border area of the display substrate
  • the fourth border area B4 may also be referred to as the upper border area of the display substrate.
  • this embodiment is not limited to this.
  • FIG2 is a schematic diagram of the first border area of at least one embodiment of the present disclosure.
  • the first border area B1 may include: The first sub-area B11, the bending area B12, and the second sub-area B13 are arranged.
  • the first sub-area B11 can also be referred to as the first fan-out area.
  • the first sub-area B11 can be connected to the second frame area B2 and the third frame area B3, and connected to the display area AA.
  • the bending area B12 can be connected between the first sub-area B11 and the second sub-area B13.
  • the bending area B12 can be configured to bend the second sub-area B13 to the back of the display area AA.
  • the second sub-area B13 of the first border area B1 may include: a second fan-out area B131, a circuit setting area B132, a third fan-out area B133, a first signal access area B134, and a second signal access area B135, which are arranged in sequence along the first direction D1 along the direction away from the bending area B12.
  • the area of the first signal access area B134 close to the side of the display area AA can also be called a wiring lead-out area.
  • the wiring lead-out area of this example may include: a first sub-area B11, a bending area B12, a second fan-out area B131, a circuit setting area B132, and a third fan-out area B133.
  • this embodiment is not limited to this.
  • the circuit configuration area B132 may be provided with multiple test circuits, which may be configured to provide test data signals to the data lines of the display area AA.
  • the circuit configuration area may also be provided with multiple electrostatic discharge circuits, which may be configured to eliminate static electricity and prevent electrostatic damage to the display substrate. This embodiment is not limited to this.
  • the first signal access area B134 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to connect to an integrated circuit (IC).
  • the second signal access area B135 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the display area AA of the display substrate may include at least: a plurality of sub-pixels PX, a plurality of gate lines GL, and a plurality of data lines (e.g., a plurality of first data lines DLa and a plurality of second data lines DLb).
  • the plurality of gate lines GL may extend along the second direction D2 and be arranged along the first direction D1; the plurality of data lines may extend along the first direction D1 and be arranged along the second direction D2.
  • the plurality of first data lines DLa may be located outside the plurality of second data lines DLb in the second direction D2.
  • the plurality of data lines may be electrically connected to the plurality of sub-pixels PX, and the plurality of data lines may be configured to provide data signals to the plurality of sub-pixels PX.
  • the plurality of gate lines GL may be electrically connected to the plurality of sub-pixels PX, and the plurality of gate lines GL may be configured to provide pixel control signals to the plurality of sub-pixels PX.
  • the pixel control signals may include scan signals, or may include scan signals and light-emitting control signals, or may include scan signals, reset control signals, and light-emitting control signals.
  • the second direction D2 may be the extending direction of the gate lines GL in the display area AA (e.g., the row direction); the first direction D1 may be the extending direction of the data lines in the display area AA (e.g., the column direction).
  • the first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.
  • the display area AA may further include multiple data connection lines 25.
  • the first data line DLa may be connected to the first data lead line of the first sub-area B11 via the data connection line 25.
  • the second data line DLb may extend directly to the first sub-area B11 and connect to the first data lead line of the first sub-area B11.
  • the data connection line 25 may include a first data connection segment 251 extending along the second direction D2 and a second data connection segment 252 extending along the first direction D1.
  • the first data connection segment 251 may be connected between the first data line DLa and the second data connection segment 252, and the second data connection segment 252 may be connected to the first data lead line of the first sub-area B11.
  • the second data connection segment 252 may be located on a side of the first data line DLa that is connected to the second data line DLa away from the edge of the display substrate.
  • the first and second data connection segments 251 and 252 may be located on the side of the first and second data lines DLa and DLb that is away from the substrate.
  • this embodiment is not limited to this.
  • a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., blue light), and a third sub-pixel emitting a third color light (e.g., green light).
  • a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light.
  • a pixel unit may include four sub-pixels, and the four sub-pixels may include one sub-pixel emitting red light, one sub-pixel emitting blue light, and two sub-pixels emitting green light.
  • a sub-pixel may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit.
  • the pixel circuit may include multiple transistors and at least one capacitor.
  • the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • T refers to a thin film transistor
  • C refers to a capacitor
  • the number before T represents the number of thin film transistors in the circuit
  • the number before C represents the number of capacitors in the circuit.
  • the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.
  • the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.
  • the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal.
  • the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern.
  • this embodiment is not limited to this.
  • the light-emitting element can be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc.
  • the light-emitting element can be an OLED, and the light-emitting element can emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit.
  • the color of the light emitted by the light-emitting element can be determined according to needs.
  • the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode.
  • the anode of the light-emitting element can be electrically connected to the corresponding pixel circuit.
  • this embodiment is not limited to this.
  • FIG3A is a partial cross-sectional diagram of a display region according to at least one embodiment of the present disclosure.
  • FIG3A illustrates the structure of a sub-pixel in the display region as an example.
  • a pixel circuit including a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor is used as an example for illustration.
  • the display area of the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on substrate 10.
  • Circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor.
  • Light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.
  • the display substrate may further include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.
  • FIG3A illustrates each sub-pixel as including a first-type transistor 21, a second-type transistor 22, and a capacitor 23.
  • the first-type transistor 21 may be a low-temperature polysilicon thin-film transistor
  • the second-type transistor 22 may be an oxide thin-film transistor.
  • the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, provided on the substrate 10.
  • a first insulating layer 101 may be provided between the first semiconductor layer and the first gate metal layer
  • a second insulating layer 102 may be provided between the first gate metal layer and the second gate metal layer
  • a second insulating layer 102 may be provided between the second gate metal layer and the second semiconductor layer.
  • a third insulating layer 103 may be provided; a fourth insulating layer 104 may be provided between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be provided between the third gate metal layer and the first source/drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarization layer) may be provided between the first source/drain metal layer and the second source/drain metal layer, and the seventh insulating layer 107 may be located on the side of the sixth insulating layer 106 away from the substrate 10; an eighth insulating layer 108 (also referred to as a second planarization layer) may be provided on the side of the second source/drain metal layer away from the substrate 10.
  • the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105, and the sixth insulating layer 106 may be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers.
  • this embodiment is not limited thereto.
  • a buffer layer may be further provided on the side of the first semiconductor layer close to the substrate, and the buffer layer may prevent harmful substances in the substrate from invading the interior of the display substrate, and may also increase the adhesion of the film layer in the display substrate to the substrate.
  • a bottom shielding metal layer may be further provided on the side of the buffer layer close to the substrate, and the bottom shielding metal layer may be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor.
  • the sixth insulating layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the seventh insulating layer may be provided between the first source-drain metal layer and the second source-drain metal layer.
  • the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21.
  • the first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102.
  • the first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23.
  • the orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10.
  • the second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22.
  • the orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap.
  • the second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22.
  • the third gate metal layer may include at least a second gate 223 of the second-type transistor 22.
  • the orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.
  • the orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10.
  • the third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.
  • the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22.
  • the fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area.
  • the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210.
  • the fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210.
  • the fifth insulating layer 105, fourth insulating layer 104, and third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220.
  • the first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via.
  • the second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via.
  • the second source-drain metal layer can include at least a first connecting electrode 241.
  • the first connecting electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107.
  • the first switching electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.
  • the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer
  • the data lines of the display area may be located in the second source-drain metal layer
  • the first power lines of the display area may be located in the second source-drain metal layer
  • the first data connection segment of the data connection line of the display area may be located in the first source-drain metal layer
  • the second data connection segment may be located in the second source-drain metal layer.
  • the circuit structure layer of the display area may further include: a third source-drain metal layer located on the side of the second source-drain metal layer away from the substrate, and the data connection line may be located in the third source-drain metal layer.
  • the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements.
  • each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133.
  • the first electrode 131 of the light-emitting element may be an anode.
  • the first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108.
  • the pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108.
  • the pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131.
  • the second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.
  • the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML) and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL).
  • EML emitting layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL hole blocking layer
  • EBL electron blocking layer
  • EIL electron injection layer
  • ETL electron transport layer
  • the light-emitting layers of light-emitting elements of different colors may be different.
  • a red light-emitting element includes a red light-emitting layer
  • a green light-emitting element includes a green light-emitting layer
  • a blue light-emitting element includes a blue light-emitting layer.
  • the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer
  • the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be produced by a single process (a single evaporation process or a single inkjet printing process), and isolation can be achieved by means of a surface step difference of the formed film layer or by surface treatment.
  • any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels can be isolated.
  • the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.
  • FMM fine metal mask
  • Open Mask open mask
  • the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143.
  • the first and third encapsulation layers 141 and 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like.
  • the second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141 and 143 to prevent external moisture from entering the light-emitting element.
  • the second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display substrate and relieve stress in the first and third encapsulation layers 141 and 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this.
  • the encapsulation structure layer may have a five-layer stacked structure: inorganic/organic/inorganic/organic/inorganic/inorganic.
  • Figure 3B is another partial cross-sectional schematic diagram of the display region of at least one embodiment of the present disclosure.
  • the multiple pixel transistors in the pixel circuit can be of the same transistor type, for example, all low-temperature polysilicon thin-film transistors.
  • Figure 3B illustrates an example of a sub-pixel including one first-type transistor 21 and one capacitor 23.
  • the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the substrate 10.
  • a first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer
  • a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer
  • a third insulating layer 103 may be disposed between the second gate metal layer and the first source-drain metal layer
  • a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source-drain metal layer and the second source-drain metal layer
  • an eighth insulating layer 108 may be disposed on the side of the second source-drain metal layer away from the substrate 10.
  • the seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers.
  • the remaining structure of the display area of the display substrate of this example can be referred to the description of the embodiment shown in FIG3A , and will not be repeated here.
  • the data lead line of the first border area can be connected to the first data line through the data connection line, which can effectively reduce the length of the first sub-area, thereby greatly reducing the size of the lower border.
  • the order of the data lead lines in the first border area will be disrupted, so that the order of the data lead lines in the first border area is different from the order of the data lines in the display area.
  • the jumpers set in the second fan-out area are prone to various problems.
  • some jumpers in the second fan-out area may overlap with other data lead lines or power lines, which can easily cause problems such as sudden load changes of data signals and difficulty in resistance compensation.
  • the jumpers in the second fan-out area are densely wired and have small gaps, which can easily lead to metal material etching residue (Remain), resulting in short circuits (Short).
  • This embodiment provides a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data transfer lines, a plurality of data lead-out lines, a plurality of data contact pads, a plurality of groups of first transfer units, and a plurality of groups of second transfer units.
  • the substrate comprises a display area and a first frame area located on one side of the display area along a first direction, the first frame area comprising: a first signal access area and a wiring lead-out area located between the first signal access area and the display area.
  • a plurality of sub-pixels are arranged on one side of the substrate and located in the display area.
  • a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines.
  • a plurality of data lead-out lines are located in the wiring lead-out area.
  • a plurality of data contact pads are located in the first signal access area. Multiple groups of first adapter units and multiple groups of second adapter units are located in a wiring lead-out area, with the multiple groups of first adapter units located on a side of the multiple groups of second adapter units away from the display area.
  • the multiple groups of first adapter units are arranged along a second direction, and the multiple groups of second adapter units are arranged along the second direction.
  • the second direction intersects the first direction; for example, the second direction may be perpendicular to the first direction.
  • Multiple data lead-out lines are connected to the multiple data contact pads through the multiple groups of first adapter units, and are also connected to the multiple second data lines and the multiple data connection lines through the multiple groups of second adapter units, so that the order of data signals provided by the multiple data contact pads matches the order of data signals required by the multiple second data lines and the multiple data connection lines arranged along the second direction.
  • the display substrate provided in this embodiment connects multiple data lead lines and multiple data contact pads through multiple groups of first adapter units, and connects multiple data lead lines with multiple second data lines and multiple data connection lines through multiple groups of second adapter units. This can ensure that the order of data signals transmitted by the multiple data contact pads matches the order of data signals required by the multiple second data lines and the multiple data connection lines, avoids the jumper design in the second fan-out area, and helps reduce the defects caused by the jumper design, thereby improving the reliability of the display substrate.
  • the order of the data signals provided by the plurality of data contact pads can be adapted to the second data of the display area.
  • the data signals provided by the plurality of data contact pads have a first order. After passing through the plurality of sets of first adapter units, the order of the data signals changes, for example, to a second order. After passing through the plurality of sets of second adapter units, the order of the data signals changes again, for example, back to the first order, so that the second data lines and the data connection lines in the display area can receive the required data signals.
  • each group of first adapter units includes: m first connection terminals, m second connection terminals, and m first adapter wires; each first adapter wire is connected between a first connection terminal and a second connection terminal; each first connection terminal is connected to a data lead-out line, and each second connection terminal is connected to a data contact pad; the m first connection terminals are arranged along the second direction and correspond to different first arrangement numbers, and the m second connection terminals are arranged along the second direction and correspond to different second arrangement numbers.
  • the m first adapter wires in each group of first adapter units include: a plug-in sequence adapter wires, the first arrangement number corresponding to the first connection terminal connected to each plug-in sequence adapter wire is different from the second arrangement number corresponding to the second connection terminal connected to it; wherein m and a are both integers greater than 1, and m is greater than or equal to a.
  • a first adapter unit may include: a first connection terminal, a first adapter wire, and a second connection terminal connected in sequence, and a first adapter unit can realize the transmission of one data signal between a data contact pad and a data lead-out line.
  • a second adapter unit may include a second adapter line, and a second adapter unit may enable transmission of a single data signal between a data lead line and a second data line or a data connection line.
  • the display substrate provided in this embodiment, by providing multiple sets of first adapter units to connect multiple data lead lines and multiple data contact pads, can utilize multiple sets of first adapter units to adjust the order of data signals transmitted by the data contact pads. Simultaneously, multiple sets of second adapter units are used to adjust the order of data signals. This avoids the need for a jumper design in the second fan-out area, helps reduce defects caused by the jumper design, and thereby improves the reliability of the display substrate.
  • a single pixel unit in a display area may include c sub-pixels, where m is k times c, and k is an integer greater than 1. For example, if a pixel unit includes four sub-pixels, m may be an integer multiple of 4, such as 8, 12, 16, or 20; if a pixel unit includes three sub-pixels, m may be an integer multiple of 3, such as 6, 9, 12, or 15.
  • the a-patch wiring harnesses within each group of first adapter units may include: a1 first-patch wiring harnesses and a2 second-patch wiring harnesses, where a1 and a2 are both integers greater than 0, and the sum of a1 and a2 is a.
  • the first arrangement number corresponding to the first connection end to which the first patch wiring harness is connected is less than the second arrangement number corresponding to the second connection end to which it is connected; the first arrangement number corresponding to the first connection end to which the second patch wiring harness is connected is greater than the second arrangement number corresponding to the second connection end to which it is connected.
  • the difference between the second arrangement number corresponding to the second connection end to which the first patch wiring harness is connected and the first arrangement number corresponding to the first connection end to which the second patch wiring harness is connected may be greater than or equal to the difference between the first arrangement number corresponding to the first connection end to which the second patch wiring harness is connected and the second arrangement number corresponding to the second connection end to which the second patch wiring harness is connected.
  • the m first transfer lines in each group of first transfer units may further include: b first sequence transfer lines, the first arrangement number corresponding to the first connection end to which each first sequence transfer line is connected is the same as the second arrangement number corresponding to the second connection end to which it is connected; b is an integer greater than 1, and b is less than or equal to a.
  • the b sequence transfer lines and the first plug-in sequence transfer line may be of the same layer structure, or at least one first sequence transfer line may be located on the side of the first plug-in sequence transfer line and the second plug-in sequence transfer line close to the substrate.
  • This example adjusts the transmission order of the data signal by utilizing the cooperation of the first sequence transfer lines and the plug-in sequence transfer lines in each group of first transfer units, thereby avoiding the jumper design in the second fan-out area, helping to reduce the defects caused by the jumper design, and thus improving the reliability of the display substrate.
  • m may be 8, and each group of first patch cords may include two first-order patch cords, two second-order patch cords, and four first-order patch cords.
  • i first connection terminals and i+1th second connection terminals; the second plug-in adapter can be configured to connect the i+1th first connection terminal and the ith second connection terminal; wherein the value of i can include 1 and 5.
  • m may be 12, and each group of first patch cords may include four first-order patch cords, four second-order patch cords, and four first-order patch cords.
  • the first-order patch cord may be configured to connect the i-th first connection terminal with the i+1-th second connection terminal;
  • the second-order patch cord may be configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i may include 1, 3, 7, or 9.
  • m may be 16, and each group of first patch cords may include four first-order patch cords, four second-order patch cords, and eight first-order patch cords.
  • the first-order patch cord may be configured to connect the i-th first connection terminal with the i+1-th second connection terminal;
  • the second-order patch cord may be configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i may include 1, 3, 9, and 11.
  • m may be 20, and each group of first patch cords may include six first-order patch cords, six second-order patch cords, and eight first-order patch cords.
  • the first-order patch cord may be configured to connect the i-th first connection terminal with the i+1-th second connection terminal;
  • the second-order patch cord may be configured to connect the i+1-th first connection terminal with the i-th second connection terminal; wherein the value of i may include 1, 3, 5, 11, 13, and 15.
  • a pixel unit located in a display area includes: a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and two third sub-pixels emitting a third color light.
  • the plurality of data lead lines connected to the plurality of first connection terminals of the plurality of first adapter units may include: a first group of data lead lines and a second group of data lead lines, wherein the first group of data lead lines and the second group of data lead lines are located in different conductive layers and are alternately arranged along the second direction.
  • the first group of data lead lines is configured to transmit data signals required by the third sub-pixel
  • the second group of data lead lines is configured to transmit data signals required by the first and second sub-pixels.
  • the data signal corresponding to the third sub-pixel may be transmitted by a data lead line located in the first gate metal layer
  • the data signals corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) may be transmitted by data lead lines located in the second gate metal layer.
  • the display substrate may further include: multiple groups of test circuits located in the trace lead-out region and arranged sequentially along the second direction.
  • the multiple groups of test circuits may be located in the first direction on a side of the multiple groups of first adapter units away from the first signal access region.
  • a group of test circuits is connected to m data lead-out lines connected to a group of first adapter units.
  • Each group of test circuits may include: a first test circuit and b second test circuits; twice the sum of a and b equals m, and a and b are both integers greater than 0.
  • the first test circuit may include: a first test transistor, a second test transistor, and a third test transistor.
  • the gate of the first test transistor is connected to the first test control line, the first electrode of the first test transistor is connected to the first test data line, the gate of the second test transistor is connected to the second test control line, the first electrode of the second test transistor is connected to the second test data line, and the second electrodes of the first and second test transistors are connected to the same data lead-out line; the gate of the third test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line.
  • the second test circuit may include: a fourth test transistor, a fifth test transistor, and a sixth test transistor.
  • the gate of the fourth test transistor is connected to the second test control line, the first electrode of the fourth test transistor is connected to the first test data line, the gate of the fifth test transistor is connected to the first test control line, the first electrode of the fifth test transistor is connected to the second test data line, the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected to the same data lead-out line; the gate of the sixth test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line.
  • the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor and the second electrode of the sixth test transistor are connected to different data lead-out lines. This example adjusts the transmission order of the test data signal by setting multiple groups of test circuits, which can avoid the jumper design in the second fan-out area, help reduce the defects caused by the jumper design, and thus improve the display substrate. reliability.
  • FIG4 is a schematic diagram of an arrangement of sub-pixels in a display area of at least one embodiment of the present disclosure.
  • each pixel unit in the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and two third sub-pixels 17a and 17b emitting a third color light.
  • Multiple pixel units may be arranged in an array within the display area AA.
  • the pixel circuits of the multiple sub-pixels may be arranged in an array along the first direction D1 and the second direction D2.
  • the light-emitting elements of the four sub-pixels may be arranged in different columns along the second direction D2, the light-emitting elements of the first sub-pixel 15 and the second sub-pixel 16 may be arranged in the same row, and the light-emitting elements of the two third sub-pixels 17a and 17b may be arranged in the same row.
  • the rows in which the light-emitting elements of the first sub-pixel 15 and the light-emitting elements of the third sub-pixel 17a are located may be spaced apart along the first direction D1.
  • the first sub-pixel 15 can be a red sub-pixel (R)
  • the second sub-pixel 16 can be a blue sub-pixel (B)
  • the third sub-pixels 17a and 17b can be green sub-pixels (G).
  • the third sub-pixel 17a can be the first green sub-pixel (G1)
  • the third sub-pixel 17b can be the second green sub-pixel (G2).
  • the plurality of pixel units arranged along the second direction D2 may be a row of pixel units, and the plurality of pixel units arranged along the first direction D1 may be a column of pixel units.
  • the plurality of pixel units may include a plurality of first pixel units and a plurality of second pixel units, and the arrangement order of the four sub-pixels within the first pixel units and the second pixel units may be different.
  • the e-th row of pixel units may include: a plurality of first pixel units arranged sequentially along the second direction D2; the first sub-pixel 15, the third sub-pixel 17a, the second sub-pixel 16, and the third sub-pixel 17b of the first pixel units are arranged sequentially along the second direction D2.
  • the e+1-th row of pixel units may include: a plurality of second pixel units arranged sequentially along the second direction D2; the second sub-pixel 16, the third sub-pixel 17b, the first sub-pixel 15, and the third sub-pixel 17a of the second pixel units may be arranged sequentially along the second direction D2.
  • a column of pixel units may include: first pixel units and second pixel units arranged alternately along the first direction D1.
  • e may be an integer greater than 0.
  • the sub-pixels of odd-numbered pixel units in the display area can be arranged in RG1BG2, and the sub-pixels of even-numbered pixel units can be arranged in BG2RG1; or, the sub-pixels of odd-numbered pixel units in the display area can be arranged in BG2RG1, and the sub-pixels of even-numbered pixel units can be arranged in RG1BG2.
  • the plurality of subpixels arranged along the first direction D1 may be a column of subpixels.
  • the jth column of subpixels may include first subpixels 15 and second subpixels 16 alternately arranged along the first direction D1; the j+1th column of subpixels may include third subpixels 17a and 17b alternately arranged along the first direction D1.
  • j may be an integer greater than 1.
  • the pixel circuits of each column of subpixels may be connected to the same data line.
  • the jth column of subpixels may be connected to data line DLj
  • the j+1th column of subpixels may be connected to data line DLj+1.
  • Figure 5 is a schematic diagram of partial wiring of the first frame area of at least one embodiment of the present disclosure.
  • Figure 5 mainly illustrates the data lead-out lines of the first frame area, and omits the remaining wiring of the first frame area.
  • the first sub-region B11 may be provided with a plurality of first data lead lines 261.
  • the plurality of first data lead lines 261 may be configured to connect the plurality of second data lines DLb and the plurality of data connection lines 25 in the display region AA in a fan-out routing manner.
  • the plurality of first data lead lines 261 may be electrically connected to the plurality of second data lines DLb and the plurality of data connection lines 25 in a one-to-one correspondence.
  • the plurality of first data lead lines 261 may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the bend region B12 may be provided with multiple bend data connection lines 264.
  • the multiple bend data connection lines 264 may be electrically connected to the multiple first data lead lines 261 in a one-to-one correspondence.
  • the multiple bend data connection lines 264 may be located in the second source/drain metal layer.
  • this embodiment is not limited to this.
  • the multiple bend data connection lines in the bend region may be located in the first source/drain metal layer.
  • the second fan-out region B131 may be provided with a plurality of second data lead-out lines 262.
  • the data lead lines 262 may be electrically connected to the plurality of data bending connection lines 264 in a one-to-one correspondence.
  • the plurality of second data lead lines 262 may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the third fan-out region B133 may be provided with a plurality of third data lead lines 263.
  • the plurality of third data lead lines 263 may be connected to the plurality of second data lead lines 262, for example, in a one-to-one electrical connection.
  • the plurality of third data lead lines 263 may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the routing lead-out region may include: a first sub-region B11, a bending region B12, a second fan-out region B131, a circuit configuration region B132, and a third fan-out region B133.
  • a data lead line in the routing lead-out region may include: a first data lead line 261, a data bending connection line 264, a second data lead line 262, and a third data lead line 263, which are connected in sequence.
  • the circuit arrangement area B132 may be provided with multiple test circuits, and the multiple third data lead lines 263 may be electrically connected to the multiple test circuits.
  • the multiple test circuits may be used to provide test data signals to the multiple second data lines DLb in the display area AA via the multiple data lead lines (for example, each data lead line includes a third data lead line 263, a second data lead line 262, a data bend connection line 264, and a first data lead line 261 connected in sequence).
  • Test data signals may also be provided to the multiple first data lines DLa via the multiple data lead lines and the multiple data connection lines 25 in the display area AA.
  • the first signal access area B134 may be provided with a plurality of first contact pads, and the plurality of first contact pads may include a plurality of data contact pads 27.
  • the plurality of data contact pads 27 may be configured to provide data signals.
  • the plurality of data contact pads 27 may be arranged in a row along the second direction D2, and a plurality of rows (e.g., two or three rows) of data contact pads 27 may be arranged along the first direction D1.
  • the plurality of data contact pads 27 may be connected to a plurality of third data lead lines 263, for example, and may be electrically connected one to one.
  • the plurality of data contact pads 27 may provide data signals to the plurality of second data lines DLb of the display area AA through a plurality of data lead lines (e.g., each data lead line includes a third data lead line 263, a second data lead line 262, a data bend connection line 264, and a first data lead line 261 connected in sequence), and may also provide data signals to the plurality of first data lines DLa through the plurality of data lead lines and the plurality of data connection lines 25 of the display area AA.
  • each data lead line includes a third data lead line 263, a second data lead line 262, a data bend connection line 264, and a first data lead line 261 connected in sequence
  • the first sub-area B11 may be provided with multiple sets of second transfer units
  • the third fan-out area B133 may be provided with multiple sets of first transfer units.
  • the multiple sets of second transfer units may be arranged sequentially along the second direction D2 and located on a side of the multiple first data lead lines 261 close to the display area AA.
  • the multiple first data lead lines 261 may be connected to the multiple second data lines DLb and the multiple data connection lines 25 in the display area AA via the multiple sets of second transfer units.
  • the multiple sets of first transfer units may be arranged sequentially along the second direction D2 and located on a side of the multiple third data lead lines 263 close to the first signal access area B134.
  • the multiple third data lead lines 263 may be connected to the multiple data contact pads 27 in the first signal access area B134 via the multiple sets of first transfer units.
  • the multiple sets of first adapter units may include: multiple sets of first-side first adapter units 300a and multiple sets of second-side first adapter units 300b.
  • the multiple sets of first-side first adapter units 300a and the multiple sets of second-side first adapter units 300b may be located on both sides of a midline of the first border area B1 that is parallel to the first direction D1.
  • the multiple sets of first-side first adapter units 300a may be connected to data lines in the left half of the display area AA
  • the multiple sets of second-side first adapter units 300b may be connected to data lines in the right half of the display area.
  • the plurality of data contact pads 27 of the first signal access area B134 may include a first group of data contact pads and a second group of data contact pads.
  • the first group of data contact pads and the second group of data contact pads may be arranged along the second direction D2.
  • the first group of data contact pads may be connected to the plurality of third data lead lines 263 via a plurality of first-side first adapter units 300a, and the second group of data contact pads may be connected to the plurality of third data lead lines 263 via a plurality of second-side first adapter units 300b.
  • the plurality of groups of second switching units may include: a plurality of groups of first-side second switching units 32a and multiple groups of second-side second adapter units 32b.
  • Multiple groups of first-side second adapter units 32a and multiple groups of second-side second adapter units 32b can be located on both sides of the midline of the first frame area B1 parallel to the first direction D1.
  • multiple groups of first-side second adapter units 32a can be connected to the second data lines and data connection lines in the left half of the display area AA
  • multiple groups of second-side second adapter units 32b can be connected to the second data lines and data connection lines in the right half of the display area.
  • multiple groups of first-side second adapter units 32a can be connected to multiple groups of first-side first adapter units 300a through multiple data lead lines
  • multiple groups of second-side second adapter units 32b can be connected to multiple groups of second-side first adapter units 300b through multiple data lead lines.
  • the number of groups of first-side second adapter units can be the same as the number of groups of first-side first adapter units
  • the number of groups of second-side second adapter units can be the same as the number of groups of second-side first adapter units.
  • FIG6 is a schematic diagram of multiple groups of first-side first transfer units of at least one embodiment of the present disclosure.
  • FIG6 is an example of two groups of first-side first transfer units.
  • FIG7A is a schematic diagram of the first gate metal layer and the second gate metal layer in FIG6.
  • FIG7B is a schematic diagram of the first source-drain metal layer in FIG6.
  • FIG7C is a schematic diagram of the second source-drain metal layer in FIG6.
  • FIG8 is a schematic diagram of a partial cross-section along the Q-Q’ direction in FIG6.
  • the number m of first transfer lines included in each group of first transfer units can be 8.
  • a set of first-side first adapter units 300a can include eight first connection terminals 311, eight second connection terminals 312, and eight first adapter lines.
  • the eight first connection terminals 311 can be arranged sequentially along the second direction D2.
  • the first arrangement sequence of the eight first connection terminals 311 arranged sequentially along the second direction D2 can correspond to 1 to 8.
  • the eight first connection terminals 311 can be connected to eight consecutively arranged third data lead lines (for example, including third data lead lines 263-1, 263-2, 263-3, 263-4, 263-5, 263-6, 263-7, and 263-8) in a one-to-one correspondence.
  • the third data lead lines 263-1, 263-3, 263-5, and 263-7 may be located in the second gate metal layer, and the third data lead lines 263-2, 263-4, 263-6, and 263-8 may be located in the first gate metal layer.
  • the third data lead lines located in the first gate metal layer may include third data lead lines 263a.
  • a single first connection terminal 311 may include: a first connection electrode 311-1 and a second connection electrode 311-2 located in different conductive layers.
  • the orthographic projections of the first connection electrode 311-1 and the second connection electrode 311-2 on the substrate may be roughly strip-shaped extending along the first direction D1.
  • the length of the first connection electrode 311-1 along the first direction D1 may be greater than the length of the second connection electrode 311-2 along the first direction D1.
  • the first connection electrode 311-1 may be located in the first source-drain metal layer
  • the second connection electrode 311-2 may be located in the second source-drain metal layer.
  • the first connection electrode 311-1 may be connected to the third data lead located in the first gate metal layer through multiple vias opened in the third insulating layer 103 and the second insulating layer 102, or may be connected to the third data lead located in the second gate metal layer through multiple vias opened in the third insulating layer 103.
  • the second connection electrode 311-2 can be connected to the first connection electrode 311-1 through a plurality of via holes formed in the seventh insulating layer 107 and the sixth insulating layer 106.
  • the orthographic projection of the second connection electrode 311-2 on the substrate may not overlap with the orthographic projection of the third data lead line on the substrate, or may partially overlap. This embodiment is not limited to this.
  • the eight second connection terminals 312 can be located on a side of the eight first connection terminals 311 close to the first signal access area B134 in the first direction D1.
  • the eight second connection terminals 312 can be arranged sequentially along the second direction D2.
  • the second arrangement sequence numbers of the eight second connection terminals 312 arranged sequentially along the second direction D2 can correspond to 1 to 8.
  • the eight second connection terminals 312 and the eight first connection terminals 311 can be aligned in the first direction D1.
  • the eight second connection terminals 312 can be connected one-to-one with eight continuously arranged contact pad connection lines 265.
  • multiple contact pad connection lines 265 can be located in the first gate metal layer.
  • the multiple contact pad connection lines 265 can be electrically connected one-to-one with multiple data contact pads 27 continuously arranged in the first signal access area B134.
  • a single second connection terminal 312 may include a third connection electrode 312-1 and a fourth connection electrode 312-2 located in different conductive layers.
  • the orthographic projections of the third connection electrode 312-1 and the fourth connection electrode 312-2 on the substrate may be It is roughly in the shape of a strip extending along the first direction D1.
  • the length of the third connection electrode 312-1 along the first direction D1 can be greater than the length of the fourth connection electrode 312-2 along the first direction D1.
  • the third connection electrode 312-1 can be located in the first source-drain metal layer
  • the fourth connection electrode 312-2 can be located in the second source-drain metal layer.
  • the third connection electrode 312-1 can be connected to the contact pad connection line 265 located in the first gate metal layer through multiple vias opened in the third insulating layer 103 and the second insulating layer 102.
  • the fourth connection electrode 312-2 can be connected to the third connection electrode 312-1 through multiple vias opened in the seventh insulating layer 107 and the sixth insulating layer 106.
  • the orthographic projection of the fourth connection electrode 312-2 on the substrate may not overlap with the orthographic projection of the contact pad connection line 265 on the substrate, or may partially overlap. This embodiment is not limited to this.
  • first adapter lines can be located between eight first connection ends 311 and eight second connection ends 312. Each first adapter line can be connected between one first connection end 311 and one second connection end 312.
  • the eight first adapter lines can include: four first-sequence adapter lines 314, two first-push-sequence adapter lines 313a, and two second-push-sequence adapter lines 313b.
  • the eight first adapter lines can include two first-order switching units, each of which can include: at least one first-order plug-in sequence adapter line (for example, including one first-order plug-in sequence adapter line 313a) and at least one second-order plug-in sequence adapter line (for example, including one second-order plug-in sequence adapter line 313b) that overlap in the orthographic projection of the substrate.
  • one first-order switching unit, two first-sequence adapter lines 314, one first-order switching unit, and two first-sequence adapter lines 314 can be arranged in sequence.
  • the orthographic projection of the first sequence patch line 314 onto the substrate can be roughly strip-shaped, extending along the first direction D1.
  • the orthographic projection of the first insertion sequence patch line 313a and the second insertion sequence patch line 313b onto the substrate can be roughly zigzag-shaped, extending along the first direction D1.
  • the orthographic projection of a first sequence-changing unit onto the substrate can be roughly X-shaped. This embodiment is not limited to this.
  • the first first-pitch sequence adapter line 313a can connect the first first connection terminal and the second second connection terminal; the first second-pitch sequence adapter line 313b can connect the second first connection terminal and the first second connection terminal; the second first-pitch sequence adapter line 313a can connect the fifth first connection terminal and the sixth second connection terminal; the second second-pitch sequence adapter line 313b can connect the sixth first connection terminal and the fifth second connection terminal.
  • the first first-sequence adapter line 314 can connect the third first connection terminal and the third second connection terminal; the second first-sequence adapter line 314 can connect the fourth first connection terminal and the fourth second connection terminal; the third first-sequence adapter line 314 can connect the seventh first connection terminal and the seventh second connection terminal; and the fourth first-sequence adapter line 314 can connect the eighth first connection terminal and the eighth second connection terminal.
  • the plurality of first-order jumper wires 314 may be arranged in the same layer, for example, in the second source/drain metal layer.
  • the first-order jumper wire 314 and the second connection electrode 311-2 of the first connection terminal 311 to which it is connected, and the fourth connection electrode 312-2 of the second connection terminal 312 to which it is connected may be an integrated structure connected to each other.
  • the first plug-in sequence adapter 313a and the second plug-in sequence adapter 313b can be located in different conductive layers.
  • the first plug-in sequence adapter 313a can be located in the first source-drain metal layer
  • the second plug-in sequence adapter 313b can be located in the second source-drain metal layer.
  • the first plug-in sequence adapter 313a and the first connection electrode 311-1 of the first connection end 311 connected thereto and the third connection electrode 312-1 of the second connection end 312 connected thereto can be an integrated structure connected to each other.
  • the second plug-in sequence adapter 313b and the second connection electrode 311-2 of the first connection end 311 connected thereto and the fourth connection electrode 312-2 of the second connection end 312 connected thereto can be an integrated structure connected to each other.
  • FIGS. 9A and 9B are schematic diagrams of the principle of interleaving of data signals transmitted by the second connection end of a group of first-side first adapter units shown in FIG6.
  • FIG9A and FIG9B taking the sub-pixel arrangement of the display area as shown in FIG4, eight data signals transmitted by the second connection end of a group of first-side first adapter units are used as an example for explanation, and each data signal can be configured to be provided to a data line of the display area.
  • the order that has not been adjusted for interleaving corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the sub-pixels arranged in the same column are connected to the same data line.
  • Three sub-pixels eg, a first green sub-pixel G1 and a second green sub-pixel G2 ) are connected to the same data line.
  • the eight data lines can be arranged along the second direction, and the data connection lines connected to the n-3 to n-1 data lines can be inserted between the n+1 to n+4 data lines in a manner of inserting one data line every other data line (i.e., a 1-in-1 manner).
  • the data connection line connected to the n-1 data line can be inserted between the n+1 data line and the n+2 data line
  • the data connection line connected to the n-2 data line can be inserted between the n+2 and n+3 data lines
  • the data connection line connected to the n-3 data line can be inserted between the n+3 and n+4 data lines.
  • the minimum number of cycles of the data signal obtained by adjusting according to the 1-in-1 manner is 8.
  • the sub-pixel cycle corresponding to the eight data lines (the nth to the n+4th after the insertion order is adjusted) obtained using a 1-in-1 method is: G2RBG1 G1BRG2.
  • the sub-pixel cycle corresponding to the eight data lines (the nth to the n+4th after the insertion order is adjusted) obtained using a 1-in-1 method is: G1BRG2 G2RBG1.
  • a first data line in the display area is connected to a data lead-out line in the first border area via a data connection line. Therefore, the order of data signals required by the multiple data lines in the display area is different from the order in which the multiple data lines are arranged.
  • multiple data contact pads can provide data signals that satisfy the order of the multiple second data lines and the multiple data connection lines. Because the sub-pixels of the odd- and even-row pixel units in the display area are arranged in different orders, the multiple data contact pads can provide corresponding data signals to the sub-pixels of the odd- and even-row pixel units in different time periods.
  • the multiple data contact pads can provide corresponding data signals to G2RBG1 and G1BRG2 in a sub-pixel cyclic order along the second direction D2 to satisfy the data signals required by the odd-row pixel units in the display area.
  • the multiple data contact pads can provide corresponding data signals to G1BRG2 and G2RBG1 in a sub-pixel cyclic order along the second direction D2 in a second time period to satisfy the data signals required by the even-row pixel units in the display area.
  • the multiple data contact pads can sequentially provide data signals to multiple rows of pixel units in the display area in a cyclic order of a first time period and a second time period.
  • the multiple data contact pads can provide data signals to sub-pixels of a row of pixel units in the display area (e.g., a first row of pixel units) in the first first time period, and can provide data signals to sub-pixels of a row of pixel units in the display area (e.g., a second row of pixel units) in the first second time period; the multiple data contact pads can provide data signals to sub-pixels of a row of pixel units in the display area (e.g., a third row of pixel units) in the second first time period, and can provide data signals to sub-pixels of a row of pixel units in the display area (e.g., a fourth row of pixel units) in the second second time period, and so on, thereby respectively providing the required data signals to sub-pixels of multiple rows of pixel units in the display area.
  • the multiple data contact pads can provide data signals to sub-pixels of a row of pixel units in the display area (e.g., a first row of pixel
  • the multiple data contact pads can provide corresponding data signals to G2RBG1 G1BRG2 in a sub-pixel cycle order along the second direction D2 in a first time period to meet the data signals required by the even-numbered rows of pixel units in the display area; the multiple data contact pads can provide corresponding data signals to G1BRG2 G2RBG1 in a sub-pixel cycle order along the second direction D2 in a second time period to meet the data signals required by the odd-numbered rows of pixel units in the display area.
  • the data signals transmitted by the multiple data contact pads may have a sub-pixel cycle corresponding to the second direction D2 of: G2RBG1 G1BRG2, and the data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of the multiple first-side first adapter units 300a.
  • the minimum number of cycles of the data signal output by the first connection terminal 311 of the first-side first adapter unit 300a is still 8, and the sub-pixel cycle corresponding to the data signal output by the first connection terminal 311 may be: RG2BG1 BG1RG2.
  • the data signals transmitted by the multiple data contact pads may have a sub-pixel cycle corresponding to the second direction D2 of:
  • the cycle may be: G1BRG2 G2RBG1.
  • the sub-pixel cycle corresponding to the data signal outputted by the multiple sets of first-side first adapter units 300a may be: BG1RG2 RG2BG1.
  • the data signal corresponding to the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead-out line located on the first gate metal layer, and the data signal corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) can be transmitted by the third data lead-out line located on the second gate metal layer, thereby ensuring uniform arrangement of the signal transmission lines and avoiding load differences caused by arranging the data lead-out lines transmitting the data signals corresponding to the third sub-pixels in different conductive layers, thereby affecting the display effect.
  • the first sub-pixel e.g., the red sub-pixel R
  • the second sub-pixel e.g., the blue sub-pixel B
  • Figure 10 is a schematic diagram of multiple sets of second-side first adapter units according to at least one embodiment of the present disclosure.
  • Figure 10 illustrates two sets of second-side first adapter units as an example.
  • a set of second-side first adapter units 300b may include eight first connection terminals 311, eight second connection terminals 312, and eight first adapter cables.
  • the eight first connection terminals 311 may be arranged sequentially in a direction opposite to the second direction D2.
  • the first arrangement sequence of the eight first connection terminals 311 arranged sequentially in a direction opposite to the second direction D2 may correspond to 1 to 8.
  • the eight first connection terminals 311 may be connected one-to-one to eight consecutively arranged third data lead lines.
  • the third data lead lines connected to the first, third, fifth, and seventh first connection terminals may be located in the first gate metal layer, and the third data lead lines connected to the second, fourth, sixth, and eighth first connection terminals may be located in the second gate metal layer.
  • the eight second connection terminals 312 can be located on the side of the eight first connection terminals 311 close to the first signal access area in the first direction D1.
  • the eight second connection terminals 312 can be arranged in sequence in the opposite direction of the second direction D2.
  • the second arrangement sequence numbers of the eight second connection terminals 312 arranged in sequence in the opposite direction of the second direction D2 can correspond to 1 to 8.
  • the eight second connection terminals 312 and the eight first connection terminals 311 can be aligned in the first direction D1.
  • the eight second connection terminals 312 can be connected one-to-one with eight continuously arranged contact pad connection lines 265.
  • multiple contact pad connection lines 265 can be located in the first gate metal layer.
  • the multiple contact pad connection lines 265 can be electrically connected one-to-one with multiple data contact pads 27 continuously arranged in the first signal access area B134.
  • the eight first adapter lines may include four first-sequence adapter lines 314, two first-pitch-sequence adapter lines 313a, and two second-pitch-sequence adapter lines 313b.
  • the first arrangement number of the first connection terminal 311 connected to the first-pitch-sequence adapter line 313a is smaller than the second arrangement number of the second connection terminal 312 to which it is connected; the first arrangement number of the first connection terminal 311 connected to the second-pitch-sequence adapter line 313b is larger than the second arrangement number of the second connection terminal 312 to which it is connected.
  • the first-pitch-sequence adapter line 313a may be located in the second source-drain metal layer, and the second-pitch-sequence adapter line 313b may be located in the first source-drain metal layer.
  • the eight first patch cords may include two first sequence-changing units, each of which may include a first plug-in sequence patch cord (e.g., including a first plug-in sequence patch cord 313a) and a second plug-in sequence patch cord (e.g., including a second plug-in sequence patch cord 313b) that overlap in orthographic projection on the substrate.
  • first plug-in sequence patch cord e.g., including a first plug-in sequence patch cord 313a
  • a second plug-in sequence patch cord e.g., including a second plug-in sequence patch cord 313b
  • one first sequence-changing unit, two first sequence patch cords 314, one first sequence-changing unit, and two first sequence patch cords 314 may be arranged in sequence.
  • the insertion order of the data signals transmitted by the second connection ends of the multiple sets of first-side first adapter units 300a and the insertion order of the data signals transmitted by the second connection ends of the multiple sets of second-side first adapter units 300b can be mirrored to match the arrangement of the data lines and data connection lines in the display area.
  • the multiple data lines and the multiple data connection lines in the display area can be arranged symmetrically about a center line of the display area parallel to the first direction.
  • FIG11 is a schematic diagram of the principle of interleaving of data signals transmitted by the second connection end of a group of first adapter units on the second side shown in FIG10 .
  • the order that has not been adjusted for interleaving corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) arranged in the same column are connected to the same data line.
  • the first sub-pixel e.g., red sub-pixel R
  • the second sub-pixel e.g., blue sub-pixel B
  • the third sub-pixel e.g., including the first green sub-pixel G1 and the second green sub-pixel G2 arranged in the same column are connected to the same data line.
  • eight data lines that have not been adjusted for interleaving are arranged in the opposite direction of the second direction D2, and can be adjusted in sequence by inserting one data line every other data line.
  • the minimum number of cycles of the data signal obtained by adjusting in a 1-in-1 manner is 8.
  • the sub-pixel cycle corresponding to the eight data lines (the nth to the n+4th after the insertion order adjustment) obtained in a 1-in-1 manner along the reverse direction of the second direction D2 is: RG2G1B BG1G2R.
  • the sub-pixel cycle corresponding to the data signals provided by the multiple data contact pads along the reverse direction of the second direction D2 can be: RG2G1B BG1G2R.
  • the data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of the multiple sets of second-side first adapter units 300b.
  • the minimum number of cycles of the data signals output by the first connection terminals 311 of the multiple sets of second-side first adapter units 300b remains 8, and the sub-pixel cycle corresponding to the data signals output by the first connection terminals 311 can be: G2RG1B G1BG2R.
  • the sub-pixel cycle corresponding to the eight data lines (the nth to the n+4th after the insertion order adjustment) obtained in a 1-in-1 manner along the opposite direction of the second direction D2 is: BG1G2R RG2G1B; the sub-pixel cycle corresponding to the data signals provided by the multiple data contact pads along the opposite direction of the second direction D2 is: BG1G2R RG2G1B.
  • the sub-pixel cycle corresponding to the data signal output by the first connection end can be: G1BG2R G2RG1B.
  • the remaining description of the insertion order principle can refer to the description of the aforementioned embodiment, and thus will not be repeated here.
  • the data signal corresponding to the third sub-pixel (e.g., including the first green sub-pixel G1 and the second green sub-pixel G2) can be transmitted by the third data lead line located on the first gate metal layer, and the data signal corresponding to the first sub-pixel (e.g., the red sub-pixel R) and the second sub-pixel (e.g., the blue sub-pixel B) can be transmitted by the third data lead line located on the second gate metal layer, thereby ensuring the uniform arrangement of the signal transmission lines and avoiding load differences caused by arranging the data lead lines that transmit the data signals corresponding to the third sub-pixels in different conductive layers, thereby affecting the display effect.
  • the first sub-pixel e.g., the red sub-pixel R
  • the second sub-pixel e.g., the blue sub-pixel B
  • Figure 12 is a schematic diagram of a group of first-side second transfer units according to at least one embodiment of the present disclosure.
  • each group of second transfer units may include m second transfer lines, and m in this example may be 8.
  • a group of first-side second transfer units 32a may include eight second transfer lines (for example, including: four second-sequence transfer lines 324, two third-sequence transfer lines 323a, and two fourth-sequence transfer lines 323b).
  • the eight second transfer lines may include two second sequence switching units, and each second sequence switching unit may include: at least one third-sequence transfer line (for example, including one third-sequence transfer line 323a) and at least one fourth-sequence transfer line (for example, including one fourth-sequence transfer line 323b) that overlap in the orthographic projection of the substrate.
  • each second sequence switching unit may include: at least one third-sequence transfer line (for example, including one third-sequence transfer line 323a) and at least one fourth-sequence transfer line (for example, including one fourth-sequence transfer line 323b) that overlap in the orthographic projection of the substrate.
  • one second sequence switching unit, two second-sequence transfer lines 324, one second sequence switching unit, and two second-sequence transfer lines 324 may be arranged in sequence.
  • each second transfer line can be connected to a second data line DLb or a data connection line 25, and the other end can be connected to a first data lead line 261.
  • the sub-pixel cycles corresponding to the data signals transmitted by the multiple first data lead lines 261 along the second direction D2 can be: RG2BG1 BG1RG2, and the corresponding sub-pixel cycles after being transferred and output by the second transfer unit 32a on the first side can be G2RBG1 G1BRG2, so that the order of the data signals transmitted by the multiple data contact pads along the second direction corresponds to the second data line and the data line connected to the corresponding pixel unit row in the display area.
  • the order of data signals required by the data connection lines along the second direction D2 is matched.
  • the data signals transmitted by the multiple first data lines 261 along the second direction D2 correspond to the following sub-pixel cycles: BG1RG2 RG2BG1.
  • the corresponding sub-pixel cycles may be G1BRG2 G2RBG1.
  • This embodiment does not limit the film layer of the second adapter line of the second adapter unit; for example, the film layer configuration may be similar to that of the first adapter line, and therefore will not be further described here.
  • a set of second-side second adapter units 32b can adjust the order of data signals output from the first connection terminals of a set of second-side first adapter units 300b to be the same as the order of data signals input from the second connection terminals.
  • the structure of the second-side second adapter units 32b in this example can refer to the structure of the first-side second adapter units 32a, and therefore will not be further described here.
  • this example ensures that the order of data signals transmitted by multiple data contact pads matches the order of data signals required by the second data lines and data connection lines within the display area. This avoids the need for jumper wires in the second fan-out area and ensures the reliability of the display product.
  • This example's configuration can ensure the display quality of display products with Full High Definition (FHD) resolution and an RGBG sub-pixel layout.
  • FHD Full High Definition
  • the circuit setting area may be provided with a plurality of groups of test circuits arranged in sequence along the second direction, and the plurality of groups of test circuits may be located on a side of the plurality of groups of first switching units away from the first signal access area in the first direction.
  • a group of test circuits may be connected to a plurality of (e.g., eight) data lead lines connected to a group of first switching units.
  • Each group of test circuits may include: at least one first test circuit and at least one second test circuit, and twice the sum of the number of first test circuits and second test circuits in each group of test circuits may be the same as the number of data lead lines connected to each group of first switching units.
  • each first test circuit may be connected to two data lead lines
  • each second test circuit may be connected to two data lead lines.
  • FIG13 is an equivalent circuit diagram of a first test circuit and a second test circuit according to at least one embodiment of the present disclosure.
  • the first test circuit 401 may include a first test transistor CT1, a second test transistor CT2, and a third test transistor CT3.
  • the gate of the first test transistor CT1 may be connected to the first test control line SW1, and the first electrode of the first test transistor CT1 may be connected to the first test data line DR.
  • the gate of the second test transistor CT2 may be connected to the second test control line SW2, and the first electrode of the second test transistor CT2 may be connected to the second test data line DB.
  • the gate of the third test transistor CT3 may be connected to the third test control line SW3, and the first electrode of the third test transistor CT3 may be connected to the third test data line DG.
  • the second electrode of the first test transistor CT1 and the second electrode of the second test transistor CT2 may be connected to the same data lead line (e.g., data lead line DA-n).
  • the second electrode of the third test transistor CT3 may be connected to another data lead line (e.g., data lead line DA-n+1).
  • the second test circuit 402 may include a fourth test transistor CT4, a fifth test transistor CT5, and a sixth test transistor CT6.
  • the gate of the fourth test transistor CT4 may be connected to the second test control line SW2, and the first electrode of the fourth test transistor CT4 may be connected to the first test data line DR.
  • the gate of the fifth test transistor CT5 may be connected to the first test control line SW1, and the first electrode of the fifth test transistor CT5 may be connected to the second test data line DB.
  • the gate of the sixth test transistor CT6 may be connected to the third test control line SW3, and the first electrode of the sixth test transistor CT6 may be connected to the third test data line DG.
  • the second electrode of the fourth test transistor CT4 and the second electrode of the fifth test transistor CT5 may be connected to the same data lead line (e.g., data lead line DA-n+2).
  • the second electrode of the sixth test transistor CT6 may be connected to another data lead line (e.g., data lead line DA-n+3).
  • the sub-pixels connected to the data lead line DA-n may include a red sub-pixel (R) and a blue sub-pixel (B)
  • the sub-pixels connected to the data lead line DA-n+2 may include a red sub-pixel (R) and a blue sub-pixel (B)
  • the sub-pixels connected to the data lead lines DA-n+1 and DA-n+3 may include a first green sub-pixel (G1). and a second green sub-pixel (G2).
  • the second electrodes of the first test transistor CT1 , the third test transistor CT3 , the fourth test transistor CT4 , and the sixth test transistor CT6 may be connected to different data lines through different data lead-out lines.
  • the first test control line SW1 can be configured to control the first test transistor CT1 in the first test circuit 401 and the fifth test transistor CT5 in the second test circuit 402 to be turned on
  • the second test control line SW2 can be configured to control the second test transistor CT2 in the first test circuit 401 and the fourth test transistor CT4 in the second test circuit 402 to be turned on, so that the first test data signal transmitted by the first test data line DR and the second test data signal transmitted by the second test data line DB can be written to different data lines.
  • a control device when performing a display test (such as a color display test), can provide a conduction signal to the first test control line SW1 (or the second test control line SW2) and the third test control line SW3, and provide the required test data signals to multiple test data lines respectively, so that multiple data lines in the display area obtain the test data signals, and determine whether there are defective sub-pixels and locate the defective sub-pixels through the color of the display screen.
  • a display test such as a color display test
  • a group of first adapter units may correspond to a group of test circuits.
  • the multiple groups of test circuits may include: multiple first-group test circuits and multiple second-group test circuits; multiple data pinouts connected to a group of first-side first adapter units may be connected to one first-group test circuit, and multiple data pinouts connected to a group of second-side first adapter units may be connected to one second-group test circuit.
  • a group of first-side first adapter units corresponds to one first-group test circuit
  • a group of second-side first adapter units corresponds to one second-group test circuit.
  • Figure 14A is a schematic plan view of a first set of test circuits according to at least one embodiment of the present disclosure.
  • Figure 14B is a schematic view of the first source/drain metal layer in Figure 14A.
  • Figure 14C is a schematic view of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 14A.
  • the first group of test circuits may include two first test circuits 401 and two second test circuits 402.
  • the first test circuit 401, the two second test circuits 402, and the first test circuit 401 may be arranged sequentially along the second direction D2.
  • the first test transistor CT1, the second test transistor CT2, and the third test transistor CT3 of each first test circuit 401 may be arranged along the first direction D1
  • the fourth test transistor CT4, the fifth test transistor CT5, and the sixth test transistor CT6 of each second test circuit 402 may be arranged along the first direction D1.
  • first test transistor CT1 and the fourth test transistor CT4 may be aligned along the second direction D2
  • second test transistor CT2 and the fifth test transistor CT5 may be aligned along the second direction D2
  • third test transistor CT3 and the sixth test transistor CT6 may be aligned along the second direction D2.
  • a first first test circuit 401 may be located between third data pins 263-1 and 263-2; a first second test circuit 402 may be located between third data pins 263-3 and 263-4; a second second test circuit 402 may be located between third data pins 263-5 and 263-6, and a second first test circuit 401 may be located between third data pins 263-7 and 263-8.
  • the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected to the third data lead line 263-1, and the third test transistor CT3 can be connected to the third data lead line 263-2.
  • the fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected to the third data lead line 263-3, and the sixth test transistor CT6 can be connected to the third data lead line 263-4.
  • the fourth test transistor CT4 and the fifth test transistor CT5 of the second second test circuit 402 can be connected to the third data lead line 263-5, and the sixth test transistor CT6 can be connected to the third data lead line 263-6.
  • the first test transistor CT1 and the second test transistor CT2 of the second first test circuit 401 can be connected to the third data lead line 263-7, and the third test transistor CT3 can be connected to the third data lead line 263-8.
  • the first semiconductor layer of the first bezel region of the display substrate may include active layers 411 and 412 of the first test transistor CT1 of the first test circuit 401, active layers 421 and 422 of the second test transistor CT2, an active layer 431 of the third test transistor CT3, active layers 441 and 442 of the fourth test transistor CT4 of the second test circuit 402, active layers 451 and 452 of the fifth test transistor CT5, and an active layer 461 of the sixth test transistor CT6.
  • the active layers 411 and 412 of the first test transistor CT1, the active layers 421 and 422 of the second test transistor CT2, and the active layer 431 of the third test transistor CT3 may be arranged along a first direction D1; the active layers 441 and 442 of the fourth test transistor CT4, the active layers 451 and 452 of the fifth test transistor CT5, and the active layer 461 of the sixth test transistor CT6 may be arranged along the first direction D1.
  • the first gate metal layer in the first border region of the display substrate may include: gates 413a and 413b of a first test transistor CT1, gates 423a and 423b of a second test transistor CT2, a gate 433 of a third test transistor CT3, gates 443a and 443b of a fourth test transistor CT4, gates 453a and 453b of a fifth test transistor CT5, and a gate 463 of a sixth test transistor CT6.
  • Gates 413a and 413b of the first test transistor CT1 may be interconnected as an integrated structure
  • gates 423a and 423b of the second test transistor CT2 may be interconnected as an integrated structure
  • gates 443a and 443b of the fourth test transistor CT4 may be interconnected as an integrated structure
  • gates 453a and 453b of the fifth test transistor CT5 may be interconnected as an integrated structure.
  • the first gate metal layer of the first border region of the display substrate may further include third data lead lines 263-2, 263-4, 263-6, and 263-8.
  • the second gate metal layer of the display substrate may include third data lead lines 263-1, 263-3, 263-5, and 263-7.
  • the first source-drain metal layer in the first border area of the display substrate may include: a first test control line SW1, a second test control line SW2, a third test control line SW3, first test data lines DR1 and DR2, second test data lines DB1 and DB2, a third test data line DG, a second electrode 414 of the first test transistor CT1, a second electrode 424 of the second test transistor CT2, a second electrode 434 and a first electrode 435 of the third test transistor CT3, a second electrode 444 of the fourth test transistor CT4, a second electrode 454 of the fifth test transistor CT5, and a second electrode 464 and a first electrode 465 of the sixth test transistor CT6.
  • the first test control line SW1, the second test control line SW2, the third test control line SW3, the first test data lines DR1 and DR2, the second test data lines DB1 and DB2, and the third test data line DG may extend at least along the second direction D2.
  • the first test transistor CT1 and the fourth test transistor CT4 may be located between the first test data lines DR1 and DR2 in the first direction D1
  • the second test transistor CT2 and the fifth test transistor CT5 may be located between the second test data lines DB1 and DB2 in the first direction D1.
  • the third test transistor CT3 and the sixth test transistor CT6 may be located on one side of the third test data line DG in the first direction D1.
  • the first test control line SW1 and the second test control line SW2 may be located between the first test data line DR2 and the second test data line DB1, and the third test control line SW3 may be located between the second test data line DB2 and the third test data line DG.
  • the second electrode 414 of the first test transistor CT1 of the first first test circuit 401 can be connected to the third data lead line 263-1 and the active layers 411 and 412 of the first test transistor CT1; the second electrode 424 of the second test transistor CT2 can be connected to the third data lead line 263-1 and the active layers 421 and 422 of the second test transistor CT2; the second electrode 434 of the third test transistor CT3 can be connected to the third data lead line 263-2 and the active layer 431 of the third test transistor CT3; and the first electrode 435 of the third test transistor CT3 can be connected to the active layer 431 of the third test transistor CT3.
  • the second electrode 444 of the fourth test transistor CT4 of the first second test circuit 402 can be connected to the third data lead line 263-3 and the active layers 441 and 442 of the fourth test transistor CT4; the second electrode 454 of the fifth test transistor CT5 can be connected to the third data lead line 263-3 and the active layers 451 and 452 of the fifth test transistor CT5; the second electrode 464 of the sixth test transistor CT6 can be connected to the third data lead line 263-4 and the active layer 461 of the sixth test transistor CT6; the first electrode 465 of the sixth test transistor CT6 can be connected to the sixth test transistor CT6.
  • the active layer 461 of the tube CT6 is connected.
  • the first test data line DR1 can be connected to the active layer 411 of the first test transistor CT1 and the active layer 441 of the fourth test transistor CT4, and the first test data line DR2 can be connected to the active layer 412 of the first test transistor CT1 and the active layer 442 of the fourth test transistor CT4.
  • the second test data line DB1 can be connected to the active layer 421 of the second test transistor CT2 and the active layer 451 of the fifth test transistor CT5, and the second test data line DB2 can be connected to the active layer 422 of the second test transistor CT2 and the active layer 452 of the fifth test transistor CT5.
  • the third test data line DG and the first electrode 435 of the third test transistor CT3 and the first electrode 465 of the sixth test transistor CT6 can be an integrated structure connected to each other.
  • the test circuitry can provide test data signals to sub-pixels in different rows of pixel units within the display area in time periods.
  • the first group of test circuits can provide corresponding test data signals to multiple third data lead lines (e.g., including third data lead lines 263-1 to 263-8) in a cyclical order of RGBG/BGRG.
  • These test data signals after being reordered by multiple groups of second adapter units, are provided to the second data lines and data connection lines of the display area to detect the display conditions of odd-numbered (or even-numbered) pixel units.
  • the first group of test circuits can provide corresponding test data signals to multiple third data lead lines in a cyclical order of BGRG/RGBG.
  • These test data signals after being reordered by multiple groups of second adapter units, are provided to the second data lines and data connection lines of the display area to detect the display conditions of even-numbered (or odd-numbered) pixel units.
  • the test data signals corresponding to the first green sub-pixel G1 and the second green sub-pixel G2 can be the same.
  • the order of the data signals provided by the first group of test circuits can be the same as the order of the data signals output by the first output terminals of the first-side first adapter units.
  • the first group of test circuits can provide test data signals to the sub-pixels of the first row of pixel units during a first first test period, and to the sub-pixels of the second row of pixel units during a first second test period; provide test data signals to the sub-pixels of the third row of pixel units during a second first test period, and provide test data signals to the sub-pixels of the fourth row of pixel units during a second second test period, and so on, providing corresponding test data signals to multiple rows of pixel units.
  • test data signals can be provided in the order of data signals corresponding to the first output ends of multiple groups of first-side first adapter units to meet the data line's requirements for test data signals.
  • the structure of the second group of test circuits corresponding to each group of second-side first adapter units is similar to the structure of the first group of test circuits, and therefore is not described again here.
  • This embodiment adjusts the transmission order of the test data signals by providing multiple test circuits, thereby avoiding the jumper design in the second fan-out area, and is beneficial for reducing defects caused by the jumper design, thereby improving the reliability of the display substrate.
  • FIG15 is an equivalent circuit diagram of a third test circuit according to at least one embodiment of the present disclosure.
  • the third test circuit may include a seventh test transistor CT7 , an eighth test transistor CT8 , a ninth test transistor CT9 , and a tenth test transistor CT10 .
  • the gates of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 are all connected to the fourth test control line SW4, the first electrode of the seventh test transistor CT7 and the first electrode of the eighth test transistor CT8 are connected to the fourth test data line DD1, and the first electrode of the ninth test transistor CT9 and the first electrode of the tenth test transistor CT10 are connected to the fifth test data line DD2.
  • the second electrodes of the seventh test transistor CT7, the eighth test transistor CT8, the ninth test transistor CT9, and the tenth test transistor CT10 can be connected to different data lines via different data lead lines.
  • the second electrode of the seventh test transistor CT7 can be connected to the data lead line DA-n
  • the second electrode of the eighth test transistor CT8 can be connected to the data lead line DA-n
  • a second electrode of the ninth test transistor CT9 may be connected to the data lead line DA-n+1
  • a second electrode of the tenth test transistor CT10 may be connected to the data lead line DA-n+3.
  • the third test circuit may be located on a side of the first test circuit and the second test circuit close to the first signal access area in the circuit arrangement area, or may be located on a side close to the bending area, which is not limited in this embodiment.
  • the third test circuit can be configured to provide a test data signal to the data line during a black and white display test to perform a black and white display test.
  • Figure 16 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of the first gate metal layer and the second gate metal layer in Figure 16.
  • Figure 18 is a schematic diagram of the principle of interleaving the data signals transmitted by the second connection terminals of the set of first-side first adapter units shown in Figure 16.
  • m can be 12.
  • the data signals required by the first green sub-pixel G1 and the second green sub-pixel G2 are the same, and the required test data signals are the same.
  • a set of first-side first transfer units 300a may include: twelve first connection terminals 311, twelve second connection terminals 312, and twelve first transfer lines.
  • the twelve first transfer lines may include: four first sequence transfer lines 314, four first plug-in sequence transfer lines 313a, and four second plug-in sequence transfer lines 313b.
  • the twelve first transfer lines may include four first sequence switching units, each of which may include: a first plug-in sequence transfer line (for example, including one first plug-in sequence transfer line 313a) and a second plug-in sequence transfer line (for example, including one second plug-in sequence transfer line 313b) that overlap in the orthographic projection of the substrate.
  • two first sequence switching units, two first sequence transfer lines 314, two first sequence switching units, and two first sequence transfer lines 314 may be arranged in sequence.
  • the twelve first connection terminals 311 may be connected to twelve consecutively arranged third data lead lines 263-1 to 263-12 in a one-to-one correspondence.
  • the third data lead lines 263-1, 263-3, 263-5, 263-7, 263-9, and 263-11 may be located in the second gate metal layer, and the third data lead lines 263-2, 263-4, 263-6, 263-8, 263-10, and 263-12 may be located in the first gate metal layer.
  • the first first-patch adapter line 313a can connect the first first connection end and the second second connection end; the second first-patch adapter line 313a can connect the third first connection end and the fourth second connection end; the third first-patch adapter line 313a can connect the seventh first connection end and the eighth second connection end; the fourth first-patch adapter line 313a can connect the ninth first connection end and the tenth second connection end.
  • the first second-patch adapter line 313b can connect the second first connection end and the first second connection end; the second second-patch adapter line 313b can connect the fourth first connection end and the third second connection end; the third second-patch adapter line 313b can connect the eighth first connection end and the seventh second connection end; and the fourth second-patch adapter line 313b can connect the tenth first connection end and the ninth second connection end.
  • first first-sequence patch cord 314 can connect the fifth first connection end and the fifth second connection end; the second first-sequence patch cord 314 can connect the sixth first connection end and the sixth second connection end; the third first-sequence patch cord 314 can connect the eleventh first connection end and the eleventh second connection end; and the fourth first-sequence patch cord 314 can connect the twelfth first connection end and the twelfth second connection end.
  • the sub-pixel arrangement of the display area is shown in FIG4 , and the sub-pixel arrangement order of the odd-numbered rows of pixel units in the display area is RGBG as an example, and twelve data lines that have not been adjusted in insertion order (for example, serial numbers n-3 to n+8) are used as an example, the twelve data lines can be arranged along the second direction D2, and according to the method of inserting one data line every two data lines (i.e., 2-in-1 method), the data connection lines connected to the n-3th to n-1th data lines can be inserted between the n+1th data line to the n+8th data line.
  • the data line connected to the n-1th data line can be inserted between the n+2th data line and the n+3th data line, the n-2th data line can be inserted between the n+4th and n+5th data lines, and the n-3th data line can be inserted between the n+6th and n+7th data lines.
  • the minimum number of cycles of the data signal obtained using the 2-into-1 method is 12.
  • the sub-pixel cycle corresponding to the twelve data lines obtained using the 2-into-1 method is: GRGB BGGR GRBG.
  • the sub-pixel cycle corresponding to the twelve data lines obtained using the 2-into-1 method can be: GBGR RGGB GBRG.
  • multiple data contact pads can provide data signals to sub-pixels in different rows of pixel units in the display area in different time periods.
  • the data signals transmitted by the multiple data contact pads may have a corresponding sub-pixel cycle along the second direction D2 of: GRGB BGGR GRBG.
  • the data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of the multiple sets of first-side first adapter units 300a.
  • the sub-pixel cycle corresponding to the data signal output by the first connection terminal 311 may be: RGBG BGRG RGBG.
  • the sub-pixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: GBGR RGGB GBRG
  • the sub-pixel cycle corresponding to the data signals output by the multiple groups of first-side first adapter units 300a can be: BGRG RGBG BGRG.
  • Figure 19 is a schematic diagram of a group of first-side second transfer units according to at least one embodiment of the present disclosure.
  • each group of second transfer units can include m second transfer lines, and m in this example can be 12.
  • a group of first-side second transfer units 32a can include twelve second transfer lines (for example, including: four second-sequence transfer lines 324, two third-sequence transfer lines 323a, and two fourth-sequence transfer lines 323b).
  • the twelve second transfer lines can include four second sequence-changing units, and each second sequence-changing unit can include: at least one third-sequence transfer line (for example, including one third-sequence transfer line 323a) and at least one fourth-sequence transfer line (for example, including one fourth-sequence transfer line 323b) that overlap in the orthographic projection of the substrate.
  • each second sequence-changing unit can include: at least one third-sequence transfer line (for example, including one third-sequence transfer line 323a) and at least one fourth-sequence transfer line (for example, including one fourth-sequence transfer line 323b) that overlap in the orthographic projection of the substrate.
  • two second sequence-changing units, two second sequence transfer lines 324, two second sequence-changing units, and two second sequence transfer lines 324 can be arranged in sequence.
  • each second adapter line can be connected to a second data line DLb or a data connection line 25, and the other end can be connected to a first data lead-out line 261.
  • the data signals transmitted by the multiple first data lead-out lines 261 along the second direction D2 may correspond to a sub-pixel cycle of RGBG BGRG RGBG.
  • the corresponding sub-pixel cycle may be GRGB BGGR GRBG.
  • the data signals transmitted by the multiple first data lead-out lines 261 along the second direction D2 may correspond to a sub-pixel cycle of BGRG RGBG BGRG.
  • the corresponding sub-pixel cycle may be GBGR RGGB GBRG.
  • the first time period can be configured to provide data signals to odd-numbered rows of pixel units in the display area
  • the second time period can be configured to provide data signals to even-numbered rows of pixel units in the display area.
  • This embodiment does not limit the film layer of the second adapter wire of the second adapter unit.
  • the film layer is configured similarly to the first adapter wire, so it is not further described here.
  • the first data contact pad arranged along the second direction can transmit the 384th data signal, and provide it to the third data lead line located in the first gate metal layer through the second connection end of the first adapter unit, a first adapter line, and the first connection end.
  • the third data lead line transmits the signal to the first data lead line through the second data lead line and the data bend connection line, and the first data lead line transmits the signal to a data line connected to the green sub-pixel (for example, a data line numbered 384 arranged along the second direction) through the second adapter line of the second adapter unit.
  • Figure 20 is a planar schematic diagram of a first set of test circuits according to at least one embodiment of the present disclosure.
  • the first set of test circuits is connected to a set of twelve third data lead lines (e.g., third data lead lines 263-1 to 263-12) connected to the first adapter unit on the first side.
  • the first set of test circuits may include: three first test circuits 401 and three second test circuits 402. One first test circuit 401, two second test circuits 402, or two first test circuits 401 and one second test circuit 402 may be arranged sequentially along the second direction D2.
  • the first test transistor CT1 and the second test transistor CT2 of the first first test circuit 401 can be connected to the third data pin 263-1, and the third test transistor CT3 can be connected to the third data pin 263-2.
  • the first test transistor CT1 and the second test transistor CT2 of the second first test circuit 401 can be connected to the third data pin 263-7, and the third test transistor CT3 can be connected to the third data pin 263-8.
  • the first test transistor CT1 and the second test transistor CT2 of the third first test circuit 401 can be connected to the third data pin 263-9, and the third test transistor CT3 can be connected to the third data pin 263-10.
  • the fourth test transistor CT4 and the fifth test transistor CT5 of the first second test circuit 402 can be connected to the third data lead line 263-3, and the sixth test transistor CT6 can be connected to the third data lead line 263-4.
  • the fourth test transistor CT4 and the fifth test transistor CT5 of the second second test circuit 402 can be connected to the third data lead line 263-5, and the sixth test transistor CT6 can be connected to the third data lead line 263-6.
  • the fourth test transistor CT4 and the fifth test transistor CT5 of the third second test circuit 402 can be connected to the third data lead line 263-11, and the sixth test transistor CT6 can be connected to the third data lead line 263-12.
  • the test circuit can provide test data signals to sub-pixels of different rows of pixel units in the display area in different time periods.
  • the first group of test circuits can provide corresponding test data signals to multiple third data lead lines (e.g., including third data lead lines 263-1 to 263-12) in a cyclic order of RGBG, BGRG, RGBG during the first test period.
  • These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple groups of second adapter units to detect the display conditions of odd-numbered (or even-numbered) pixel units.
  • the first group of test circuits can provide corresponding test data signals to the multiple third data lead lines in a cyclic order of BGRG, RGBG, BGRG during the second test period. These test data signals are then provided to the second data lines and data connection lines of the display area after being reordered by multiple groups of second adapter units to detect the display conditions of even-numbered (or odd-numbered) pixel units.
  • test circuit please refer to the description of the aforementioned embodiment, so they will not be repeated here.
  • Figure 21 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure.
  • a set of second-side first adapter units 300b may include twelve first connection terminals 311, twelve second connection terminals 312, and twelve first adapter lines.
  • the twelve first connection terminals 311 may be arranged sequentially in the direction opposite to the second direction D2.
  • the first arrangement sequence of the twelve first connection terminals 311 arranged sequentially in the direction opposite to the second direction D2 may correspond to 1 to 12.
  • the twelve first connection terminals 311 may be connected to the twelve consecutively arranged third data lead lines in a one-to-one correspondence.
  • the third data lead-out lines connected to the first first connection terminal, the third first connection terminal, the fifth first connection terminal, the seventh first connection terminal, the ninth first connection terminal and the eleventh first connection terminal can be located in the first gate metal layer
  • the third data lead-out lines connected to the second first connection terminal, the fourth first connection terminal, the sixth first connection terminal, the eighth first connection terminal, the tenth first connection terminal and the twelfth first connection terminal can be located in the second gate metal layer.
  • the twelve second connection terminals 312 may be arranged sequentially in the direction opposite to the second direction D2.
  • the second arrangement sequence numbers of the twelve second connection terminals 312 arranged sequentially in the direction opposite to the second direction D2 may correspond to 1 to 12.
  • the twelve first adapter cables may include four first sequential adapter cables 314, four first plug-in sequence adapter cables 313a, and four second plug-in sequence adapter cables 313b.
  • FIG22 is an insertion sequence diagram of a data signal transmitted by the second connection end of a group of first adapter units on the second side shown in FIG21 Principle diagram.
  • the order that has not been adjusted by interpolation corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (for example, the red sub-pixel R) and the second sub-pixel (for example, the blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (for example, the green sub-pixel G) arranged in the same column is connected to the same data line.
  • the twelve data lines that have not been adjusted by interpolation can be arranged in the opposite direction of the second direction D2, and can be adjusted in sequence by inserting one data line every two data lines.
  • the minimum number of cycles of the data signal obtained by adjusting in a 2-in-1 manner is 12.
  • the sub-pixel arrangement order for example, the sub-pixel arrangement order of the odd-numbered row pixel unit
  • the sub-pixel cycles corresponding to the twelve data lines obtained in a 2-in-1 manner are: RGBG GRBG BGGR.
  • the sub-pixel cycle corresponding to the twelve data lines (nth to n+8th after the insertion order adjustment) obtained by the 2-in-1 method can be BGRG GBRG RGGB.
  • multiple data contact pads can provide data signals to sub-pixels in different rows of pixel units in the display area in different time periods.
  • the data signals provided by the multiple data contact pads may have a sub-pixel cycle corresponding to the data signals in the direction opposite to the second direction D2: RGBG GRBG BGGR.
  • the data signals transmitted by the multiple data contact pads are provided to the second connection terminals 312 of the multiple sets of second-side first adapter units 300b. For example, after passing through the multiple sets of second-side first adapter units 300b, the minimum number of cycles of the data signals output by the first connection terminals 311 of the multiple sets of second-side first adapter units 300b remains 12.
  • the sub-pixel cycles corresponding to the twelve data signals may have a cycle of GRGB GRGB GBGR.
  • the sub-pixel cycle corresponding to the data signals transmitted by the multiple data contact pads along the second direction D2 can be: BGRG GBRG RGGB.
  • the sub-pixel cycle corresponding to the data signals output by the multiple groups of second-side first adapter units 300b first connection terminals 311 can be: GBGR GBGR GRGB.
  • Figure 23 is a schematic plan view of a second set of test circuits according to at least one embodiment of the present disclosure.
  • the second set of test circuits can be connected to twelve third data lead lines 263 connected to a set of second-side first adapter units.
  • the second set of test circuits can include three first test circuits 401 and three second test circuits 402. Specifically, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, and one first test circuit 401 can be arranged sequentially in a direction opposite to the second direction D2.
  • the test data signals provided by the test circuit at different time periods may be different.
  • the test circuit may provide corresponding test data signals according to the rule of row-by-row scanning of the display area. For example, for odd-numbered rows of pixel units, the second group of test circuits may provide corresponding test data signals to multiple data lead lines in the reverse direction of the second direction D2 in the cyclic order of GRGB GRGB GBGR; for even-numbered rows of pixel units, the second group of test circuits may provide corresponding test data signals to multiple data lead lines in the reverse direction of the second direction D2 in the cyclic order of GBGR GBGR GRGB.
  • the remaining description of the test circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • Figure 24 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • Figure 25 is a schematic diagram of the principle of inserting and sequencing data signals transmitted by the second connection terminals of the set of first-side first adapter units shown in Figure 24.
  • m can be 16.
  • a set of first-side first transfer units 300a may include: sixteen first connection terminals 311, sixteen second connection terminals 312, and sixteen first transfer lines.
  • the sixteen first transfer lines may include: eight first-sequence transfer lines 314, four first-push-sequence transfer lines 313a, and four second-push-sequence transfer lines 313b.
  • the sixteen first transfer lines may include four first-order switching units, each of which may include: a first-push-sequence transfer line (e.g., including one first-push-sequence transfer line 313a) and a second-push-sequence transfer line (e.g., including one second-push-sequence transfer line 313b) that overlap in the orthographic projection of the substrate.
  • a first-push-sequence transfer line e.g., including one first-push-sequence transfer line 313a
  • second-push-sequence transfer line e.g., including one second-push-sequence transfer line 313b
  • the sixteen first connection terminals 311 may be connected to sixteen consecutively arranged third data lead lines in a one-to-one correspondence.
  • the sixteen third data lead lines may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the first first-patch adapter line 313a can connect the first first connection terminal and the second second connection terminal; the second first-patch adapter line 313a can connect the third first connection terminal and the fourth second connection terminal; the third first-patch adapter line 313a can connect the ninth first connection terminal and the tenth second connection terminal; the fourth first-patch adapter line 313a can connect the eleventh first connection terminal and the twelfth second connection terminal.
  • the first second-patch adapter line 313b can connect the second first connection terminal and the first second connection terminal; the second second-patch adapter line 313b can connect the fourth first connection terminal and the third second connection terminal; the third second-patch adapter line 313b can connect the tenth first connection terminal and the ninth second connection terminal; and the fourth second-patch adapter line 313b can connect the twelfth first connection terminal and the eleventh second connection terminal.
  • the first first-sequence patch cord 314 can connect the fifth first connection end and the fifth second connection end; the second first-sequence patch cord 314 can connect the sixth first connection end and the sixth second connection end; the third first-sequence patch cord 314 can connect the seventh first connection end and the seventh second connection end; the fourth first-sequence patch cord 314 can connect the eighth first connection end and the eighth second connection end; the fifth first-sequence patch cord 314 can connect the thirteenth first connection end and the thirteenth second connection end; the sixth first-sequence patch cord 314 can connect the fourteenth first connection end and the fourteenth second connection end; the seventh first-sequence patch cord 314 can connect the fifteenth first connection end and the fifteenth second connection end; and the eighth first-sequence patch cord 314 can connect the sixteenth first connection end and the sixteenth second connection end.
  • the sub-pixel arrangement of the display area is shown in FIG4 , and the sub-pixel arrangement order of the pixel units in the odd-numbered rows of the display area is RGBG.
  • sixteen data lines e.g., numbered n-3 to n+12 that have not undergone insertion sequence adjustment are used for illustration.
  • the sixteen data lines can be arranged along the second direction D2 , and a data line can be inserted every three data lines (i.e., a 3-in-1 method).
  • the data connection lines connected to the n-3 to n-1 data lines can be inserted between the n+1 to n+12 data lines.
  • the n-1 data line can be inserted between the n+3 and n+4 data lines
  • the n-2 data line can be inserted between the n+6 and n+7 data lines
  • the n-3 data line can be inserted between the n+9 and n+10 data lines.
  • the minimum number of cycles of the data signal obtained according to the 3-in-1 method is 16.
  • the sub-pixel cycle corresponding to the sixteen data lines obtained by the 3-in-1 method is: GRGB BGRG GBGR RGBG.
  • the sub-pixel cycle corresponding to the sixteen data lines obtained by the 3-in-1 method can be: GBGR RGBG GRGB BGRG.
  • multiple data contact pads can provide data signals to sub-pixels in different rows of pixel units in the display area in different time periods.
  • the data signals transmitted by the multiple data contact pads along the second direction D2 may correspond to a sub-pixel cycle of: GRGB BGRG GBGR RGBG.
  • the minimum number of data signal cycles remains 16.
  • the sub-pixel cycles corresponding to the sixteen data signals may be: RGBG BGRG BGRG RGBG.
  • the data signals transmitted by the multiple data contact pads along the second direction D2 may correspond to a sub-pixel cycle of: GBGR RGBG GRGB BGRG.
  • the sub-pixel cycles corresponding to the data signals output by the first connection terminals 311 of the multiple sets of first-side first adapter units 300a may be: BGRG RGBG RGBG RGBG BGRG.
  • FIG26 is a planar schematic diagram of a first group of test circuits corresponding to a group of first-side first adapter units shown in FIG24.
  • a first group of test circuits is connected to sixteen third data lead-out lines connected to a group of first-side first adapter units.
  • the first group of test circuits may include: four first test circuits 401 and four second test circuits 402. Among them, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, two first test circuits 401 and one second test circuit 402 may be Arranged in sequence along the second direction D2.
  • the test circuit can provide test data signals to sub-pixels of different rows of pixel units in the display area in different time periods.
  • the first group of test circuits can provide corresponding test data signals to multiple third data lead lines in a cyclic order of RGBG BGRG BGRG RGBG in the first test period.
  • These test data signals are provided to the second data lines and data connection lines of the display area after being reversed by multiple groups of second adapter units to detect the display conditions of odd-numbered (or even-numbered) pixel units.
  • the first group of test circuits can provide corresponding test data signals to multiple third data lead lines in a cyclic order of BGRG RGBG RGBG BGRG in the second test period.
  • test data signals are provided to the second data lines and data connection lines of the display area after being reversed by multiple groups of second adapter units to detect the display conditions of even-numbered (or odd-numbered) pixel units.
  • test circuit please refer to the description of the aforementioned embodiment, so they will not be repeated here.
  • Figure 27 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure.
  • a set of second-side first adapter units 300b may include sixteen first connection terminals 311, sixteen second connection terminals 312, and sixteen first adapter lines.
  • the sixteen first connection terminals 311 may be arranged sequentially in a direction opposite to the second direction D2.
  • the first arrangement sequence of the sixteen first connection terminals 311 arranged sequentially in a direction opposite to the second direction D2 may correspond to 1 to 16.
  • the sixteen first connection terminals 311 may be connected to sixteen consecutively arranged third data lead lines.
  • the third data lead-out lines connected to the first first connection terminal, the third first connection terminal, the fifth first connection terminal, the seventh first connection terminal, the ninth first connection terminal, the eleventh first connection terminal, the thirteenth first connection terminal and the fifteenth first connection terminal can be located in the first gate metal layer
  • the third data lead-out lines connected to the second first connection terminal, the fourth first connection terminal, the sixth first connection terminal, the eighth first connection terminal, the tenth first connection terminal, the twelfth first connection terminal, the fourteenth first connection terminal and the sixteenth first connection terminal can be located in the second gate metal layer.
  • the sixteen second connection terminals 312 may be arranged sequentially in the direction opposite to the second direction D2.
  • the second arrangement sequence numbers of the sixteen second connection terminals 312 arranged sequentially in the direction opposite to the second direction D2 may correspond to 1 to 16.
  • the sixteen first adapter cables may include eight first-sequential adapter cables 314, four first-plug-sequence adapter cables 313a, and four second-plug-sequence adapter cables 313b.
  • FIG28 is a schematic diagram of the principle of interleaving of data signals transmitted by the second connection end of a group of first adapter units on the second side shown in FIG27 .
  • the order that has not been adjusted for interleaving corresponds to the arrangement order of multiple data lines in the display area; the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) arranged in the same column are connected to the same data line, and the third sub-pixel (e.g., green sub-pixel G) arranged in the same column is connected to the same data line.
  • the first sub-pixel e.g., red sub-pixel R
  • the second sub-pixel e.g., blue sub-pixel B
  • the third sub-pixel e.g., green sub-pixel G
  • sixteen data lines (e.g., the n-3rd to the n+12th) that have not been adjusted for interleaving are arranged in the opposite direction of the second direction D2, and can be adjusted in sequence by inserting one data line every three data lines.
  • the minimum number of cycles of the data signal obtained by adjusting in a 3-in-1 manner is 16.
  • the sub-pixel cycle corresponding to the sixteen data lines (the nth to the n+12th after the insertion order is adjusted) obtained by the 3-in-1 method is: RGBG GRGB BGRG GBGR.
  • the sub-pixel cycle corresponding to the sixteen data lines (the nth to the n+12th after the insertion order is adjusted) obtained by the 3-in-1 method can be: BGRG GBGR RGBG GRGB.
  • multiple data contact pads can provide data signals to sub-pixels of different rows of pixel units in the display area in different time periods.
  • the sub-pixel cycle corresponding to the data signals provided by the multiple data contact pads along the reverse direction of the second direction D2 can be: RGBG GRGB BGRG GBGR.
  • the minimum number of data signal cycles after the multiple data signals pass through the multiple sets of second-side first adapter units 300b is still 16, and the sub-pixel cycle corresponding to the sixteen data signals along the reverse direction of the second direction D2 can be: GRGB GRGB GBGR GBGR.
  • the sub-pixel cycle corresponding to the data signals provided by the multiple data contact pads along the reverse direction of the second direction D2 can be: BGRG GBGR RGBG GRGB
  • the sub-pixel cycle corresponding to the data signal output by the multiple sets of second-side first adapter units 300b first connection terminals 311 can be: GBGR GBGR GRGB GRGB.
  • Figure 29 is a schematic plan view of a second set of test circuits according to at least one embodiment of the present disclosure.
  • the second set of test circuits can be connected to sixteen third data lead lines 263 connected to a set of second-side first adapter units.
  • the second set of test circuits can include four first test circuits 401 and four second test circuits 402. Specifically, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, and one first test circuit 401 can be arranged sequentially in a direction opposite to the second direction D2.
  • the test data signals provided by the test circuit at different time periods may be different.
  • the test circuit may provide corresponding test data signals according to the rule of row-by-row scanning of the display area. For example, for odd-numbered rows of pixel units, the second group of test circuits may provide corresponding test data signals to multiple data lead lines in a cyclic order of GRGB GRGB GBGR GBGR along the opposite direction of the second direction D2; for even-numbered rows of pixel units, the second group of test circuits may provide corresponding test data signals to multiple data lead lines in a cyclic order of GBGR GBGR GRGB GRGB along the opposite direction of the second direction D2.
  • the rest of the description of the test circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • Figure 30 is another schematic diagram of a set of first-side first adapter units according to at least one embodiment of the present disclosure.
  • Figure 31 is a schematic diagram of the principle of inserting and sequencing data signals transmitted by the second connection terminals of the set of first-side first adapter units shown in Figure 30.
  • m can be 20.
  • a set of first-side first transfer units 300a may include: twenty first connection terminals 311, twenty second connection terminals 312, and twenty first transfer lines.
  • the twenty first transfer lines may include: eight first-sequence transfer lines 314, six first-push-sequence transfer lines 313a, and six second-push-sequence transfer lines 313b.
  • the twenty first transfer lines may include six first-order switching units, each of which may include: a first-push-sequence transfer line (e.g., including one first-push-sequence transfer line 313a) and a second-push-sequence transfer line (e.g., including one second-push-sequence transfer line 313b) that overlap in the orthographic projection of the substrate.
  • a first-push-sequence transfer line e.g., including one first-push-sequence transfer line 313a
  • second-push-sequence transfer line e.g., including one second-push-sequence transfer line 313b
  • the twenty first connection terminals 311 may be connected to twenty consecutively arranged third data lead lines in a one-to-one correspondence.
  • the twenty third data lead lines may be alternately arranged in the first gate metal layer and the second gate metal layer.
  • the first first-push sequence adapter line 313a can connect the first first connection end and the second second connection end; the second first-push sequence adapter line 313a can connect the third first connection end and the fourth second connection end; the third first-push sequence adapter line 313a can connect the fifth first connection end and the sixth second connection end; the fourth first-push sequence adapter line 313a can connect the eleventh first connection end and the twelfth second connection end; the fifth first-push sequence adapter line 313a can connect the thirteenth first connection end and the fourteenth second connection end; and the sixth first-push sequence adapter line 313a can connect the fifteenth first connection end and the sixteenth second connection end.
  • the first second-push sequence adapter line 313b can connect the second first connection end and the first second connection end; the second second-push sequence adapter line 313b can connect the fourth first connection end and the third second connection end; the third second-push sequence adapter line 313b can connect the sixth first connection end and the fifth second connection end; the fourth second-push sequence adapter line 313b can connect the twelfth first connection end and the eleventh second connection end; the fifth second-push sequence adapter line 313b can connect the fourteenth first connection end and the thirteenth second connection end; and the sixth second-push sequence adapter line 313b can connect the sixteenth first connection end and the fifteenth second connection end.
  • the first first-sequence adapter line 314 can connect the seventh first connection end and the seventh second connection end; the second first-sequence adapter line 314 can connect the eighth first connection end and the eighth second connection end; the third first-sequence adapter line 314 can connect the ninth first connection end and the ninth second connection end; the fourth first-sequence adapter line 314 can connect the tenth first connection end and the tenth second connection end; the fifth first-sequence adapter line 314 can connect the seventeenth first connection end and the seventeenth second connection end; the sixth first-sequence adapter line 314 can connect the eighteenth first connection end and the eighteenth second connection end; the seventh first-sequence adapter line 314 can connect the nineteenth first connection end and the nineteenth second connection end; and the eighth first-sequence adapter line 314 can connect the twentieth first connection end and the twentieth second connection end.
  • the sub-pixel arrangement of the display area is shown in FIG4 , and the sub-pixel arrangement order of the odd-numbered rows of pixel units in the display area is RGBG.
  • the twenty data lines can be arranged along the second direction D1, and one data line can be inserted every four data lines (i.e., a 4-in-1 method).
  • the data connection lines connected to the n-3th to n-1th data lines can be inserted between the n+1th to n+16th data lines.
  • the n-1th data line can be inserted between the n+4th and n+5th data lines
  • the n-2th data line can be inserted between the n+8th and n+9th data lines
  • the n-3th data line can be inserted between the n+12th and n+13th data lines.
  • the minimum number of cycles of the data signal obtained by adjusting the 4-in-1 method is 20.
  • the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 method is: GRGB GBRG BGGR GBGR RGBG.
  • the sub-pixel cycle corresponding to the twenty data lines obtained by the 4-in-1 method can be: GBGR GRBG RGGB GRGB BGRG.
  • multiple data contact pads can provide data signals to sub-pixels in different rows of pixel units in the display area in different time periods.
  • the data signals transmitted by the multiple data contact pads along the second direction D2 may correspond to a sub-pixel cycle of: GRGB GBRG BGGR GBGR RGBG.
  • the minimum number of data signal cycles remains 20.
  • the sub-pixel cycles corresponding to the twenty data signals may be: RGBG BGRG BGRG BGRG RGBG.
  • the data signals transmitted by the multiple data contact pads along the second direction D2 may correspond to a sub-pixel cycle of: GBGR GRBG RGGB GRGB BGRG.
  • the sub-pixel cycles corresponding to the data signals output by the first connection terminals 311 of the multiple sets of first-side first adapter units 300a may be: BGRG RGBG RGBG RGBG RGBG BGRG.
  • Figure 32 is a plan view schematic diagram of a first group of test circuits corresponding to a set of first-side first adapter units shown in Figure 30 .
  • one first group of test circuits is connected to twenty third data lead-out lines connected to a set of first-side first adapter units.
  • the first group of test circuits may include five first test circuits 401 and five second test circuits 402. Specifically, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, one first test circuit 401, one second test circuit 402, or two first test circuits 401 and one second test circuit 402 may be arranged sequentially along the second direction D2.
  • the test data signals provided by the test circuit at different time periods may be different.
  • the test circuit may provide corresponding test data signals based on the row-by-row scanning pattern of the display area. For example, for odd-numbered rows of pixel units, the first group of test circuits may provide corresponding test data signals to the multiple data lead lines along the second direction D2 in a cyclic order of RGBG BGRG BGRG BGRG RGBG; for even-numbered rows of pixel units, the first group of test circuits may provide corresponding test data signals to the multiple data lead lines along the second direction D2 in a cyclic order of BGRG RGBG RGBG RGBG BGRG.
  • the test circuit please refer to the description of the aforementioned embodiment, and therefore will not be repeated here.
  • Figure 33 is a schematic diagram of a set of second-side first adapter units according to at least one embodiment of the present disclosure.
  • a set of second-side first adapter units 300b may include: twenty first connection terminals 311, twenty second connection terminals 312, and twenty first adapter lines.
  • the twenty first connection terminals 311 may be arranged sequentially in the direction opposite to the second direction D2.
  • the first arrangement sequence of the twenty first connection terminals 311 arranged sequentially in the direction opposite to the second direction D2 may correspond to 1 to 20.
  • the twenty first connection terminals 311 may be connected to twenty consecutively arranged third data lead lines.
  • the third data lead-out lines connected to the first first connection terminal, the third first connection terminal, the fifth first connection terminal, the seventh first connection terminal, the ninth first connection terminal, the eleventh first connection terminal, the thirteenth first connection terminal, the fifteenth first connection terminal, the seventeenth first connection terminal and the nineteenth first connection terminal can be located in the first gate metal layer
  • the third data lead-out lines connected to the second first connection terminal, the fourth first connection terminal, the sixth first connection terminal, the eighth first connection terminal, the tenth first connection terminal, the twelfth first connection terminal, the fourteenth first connection terminal, the sixteenth first connection terminal, the eighteenth first connection terminal and the twentieth first connection terminal can be located in the second gate metal layer.
  • the twenty second connection terminals 312 may be arranged sequentially in the direction opposite to the second direction D2.
  • the second arrangement sequence numbers of the twenty second connection terminals 312 arranged sequentially in the direction opposite to the second direction D2 may correspond to 1 to 20.
  • the twenty first adapter cables may include eight first-sequential adapter cables 314, six first-plug-sequence adapter cables 313a, and six second-plug-sequence adapter cables 313b.
  • Figure 34 is a schematic diagram illustrating the principle of interleaving data signals transmitted by the second connection terminals of the set of second-side first adapter units shown in Figure 33.
  • the sub-pixel cycle corresponding to the twenty data lines obtained using a 4-in-1 interleaving method is: RGBG RGGB GRBG BGRG GBGR.
  • the sub-pixel cycle corresponding to the twenty data lines obtained using a 4-in-1 interleaving method is: BGRG BGGR GBRG RGBG GRGB.
  • multiple data contact pads can provide data signals to sub-pixels in different rows of pixel units in the display area in different time periods.
  • the data signals provided by the multiple data contact pads along the reverse direction of the second direction D2 correspond to a sub-pixel cycle of: RGBG RGGB GRBG BGRG GBGR.
  • the minimum number of data signal cycles remains 20.
  • the sub-pixel cycles corresponding to the twenty data signals may be: GRGB GRGB GRGB GB GBGRGBGR GBGR GBGR GBGR.
  • the data signals transmitted by the multiple data contact pads along the reverse direction of the second direction D2 correspond to a sub-pixel cycle of: BGRG BGGR GBRG RGBG GRGB.
  • the sub-pixel cycles corresponding to the data signals output by the first connection terminals 311 of the multiple sets of second-side first adapter units 300b may be: GBGR GBGR GBGR GRGB GRGB.
  • Figure 35 is a plan view schematic diagram of a second group of test circuits according to at least one embodiment of the present disclosure.
  • the second group of test circuits can be connected to a group of twenty third data lead lines 263 connected to a second-side first adapter unit.
  • the second group of test circuits can include five first test circuits 401 and five second test circuits 402. Specifically, one first test circuit 401, one second test circuit 402, one first test circuit 401, one second test circuit 402, one first test circuit 401, two second test circuits 402, one first test circuit 401, one second test circuit 402, and one first test circuit 401 can be arranged sequentially in a direction opposite to the second direction D2.
  • the test data signals provided by the test circuit at different time periods may be different.
  • the test circuit may provide corresponding test data signals according to the rule of row-by-row scanning of the display area.
  • the second group of test circuits may provide corresponding test data signals to multiple data lead lines in a cyclic order of GRGB GRGB GRGB GBGR GBGR along the opposite direction of the second direction D2; for even-numbered rows of pixel units, the second group of test circuits may provide corresponding test data signals to multiple data lead lines in a cyclic order of GBGR GBGR GBGR GRGB GRGB along the opposite direction of the second direction D2.
  • the remaining description of the test circuit of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.
  • FIG36A to 36C are diagrams illustrating a connection method for a plurality of first adapter units according to at least one embodiment of the present disclosure.
  • FIG36A to 36C illustrate the sub-pixel arrangement of the display area as shown in FIG4 as an example.
  • the first plug-in sequence adapter line 313a can connect the first first connection end 311 and the fourth second connection end 312; the first second plug-in sequence adapter line 313b can connect the second first connection end 311 and the first second connection end 312; the second second plug-in sequence adapter line 313b can connect the third first connection end 311 and the second second connection end 312; and the third second plug-in sequence adapter line 313b can connect the fourth first connection end 311 and the third second connection end 312.
  • the orthographic projection of the first plug-in sequence adapter line 313a on the substrate overlaps with the orthographic projections of the three second plug-in sequence adapter lines 313b on the substrate.
  • the first plug-in sequence adapter line 313a can be located in the first source and drain metal layer, and the three second plug-in sequence adapter lines 313b can be located in the second source and drain metal layer.
  • this embodiment is not limited to this.
  • the first plug-in sequence transfer line may be located in the second source-drain metal layer, and the second plug-in sequence transfer line may be located in the first source-drain metal layer.
  • the data signal transmitted by the second connection terminal 312 when the data signal transmitted by the second connection terminal 312 is configured to correspond to GBGR in sequence, after passing through the four first adapter lines, the data signal transmitted by the first connection terminal 311 is configured to correspond to RGBG in sequence.
  • the data signals corresponding to the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) can be transmitted on the data lead line located in the second gate metal layer (or the first gate metal layer), and the data signal corresponding to the third sub-pixel (e.g., green sub-pixel G) can be transmitted on the data lead line located in the first gate metal layer (or the second gate metal layer), thereby ensuring uniformity of signal transmission.
  • the first sub-pixel e.g., red sub-pixel R
  • the second sub-pixel e.g., blue sub-pixel B
  • the third sub-pixel e.g., green sub-pixel G
  • the first plug-in sequence adapter 313a can connect the first first connection end 311 and the third second connection end 312; the second plug-in sequence adapter 313b can connect the third first connection end 311 and the first second connection end 312; the first first-sequence adapter 314 can connect the second first connection end and the second second connection end; and the second first-sequence adapter 314 can be connected between the fourth first connection end and the fourth second connection end.
  • the orthographic projection of the first first-sequence adapter 314 on the substrate overlaps with the orthographic projections of the first plug-in sequence adapter 313a and the second plug-in sequence adapter 313b on the substrate.
  • the orthographic projection of the second first-sequence adapter 314 on the substrate does not overlap with the orthographic projections of the first plug-in sequence adapter 313a and the second plug-in sequence adapter 313b on the substrate.
  • the first plug-in sequence adapter 313a can be located in the first source-drain metal layer
  • the second plug-in sequence adapter 313b can be located in the second source-drain metal layer.
  • the first first-sequence adapter 314 can be located in the first gate metal layer.
  • the first connection electrode of the first connection terminal 311 connected to the first first-sequence adapter 314 can be located in the first source-drain metal layer
  • the second connection electrode can be located in the first gate metal layer
  • the third connection electrode of the second connection terminal 312 connected to the first first-sequence adapter 314 can be located in the first source-drain metal layer
  • the fourth connection electrode can be located in the first gate metal layer.
  • the first first-sequence adapter 314, the second connection electrode of the first connection terminal 311 connected to it, and the fourth connection electrode of the second connection terminal 312 connected to it can be an integrated structure connected to each other.
  • the second first-sequence adapter 314 can be located in the second source-drain metal layer.
  • this embodiment is not limited to this.
  • the first plug-in sequence adapter can be located in the second source-drain metal layer, and the second plug-in sequence adapter can be located in the first source-drain metal layer.
  • the data signal transmitted by the second connection terminal 312 when the data signal transmitted by the second connection terminal 312 is configured to correspond to BGRG in sequence, after passing through the four first adapter lines, the data signal transmitted by the first connection terminal 311 is configured to correspond to RGBG in sequence.
  • the data signals corresponding to the first sub-pixel (e.g., red sub-pixel R) and the second sub-pixel (e.g., blue sub-pixel B) can be transmitted on the data lead line located in the second gate metal layer (or the first gate metal layer), and the data signal corresponding to the third sub-pixel (e.g., green sub-pixel G) can be transmitted on the data lead line located in the first gate metal layer (or the second gate metal layer), thereby ensuring uniform signal transmission.
  • the first sub-pixel e.g., red sub-pixel R
  • the second sub-pixel e.g., blue sub-pixel B
  • the third sub-pixel e.g., green sub-pixel G
  • the first plug-in sequence adapter line 313a can connect the first first connection end 311 and the fourth second connection end 312; the first second plug-in sequence adapter line 313b can connect the third first connection end 311 and the first second connection end 312; the second second plug-in sequence adapter line 313b can connect the fourth first connection end 311 and the third second connection end 312; the first second plug-in sequence adapter line 314 can connect the second second connection end 314.
  • the orthographic projection of the first sequential transfer line 314 on the substrate overlaps with the orthographic projections of the first plug-in sequence transfer line 313a and the first second plug-in sequence transfer line 313b on the substrate, and may not overlap with the orthographic projection of the second second plug-in sequence transfer line 313b on the substrate.
  • the orthographic projection of the first plug-in sequence transfer line 313a on the substrate may overlap with the orthographic projections of the two second plug-in sequence transfer lines 313b on the substrate.
  • the first plug-in sequence transfer line 313a may be located in the first source and drain metal layer
  • the two second plug-in sequence transfer lines 313b may be located in the second source and drain metal layer
  • the first sequential transfer line 314 may be located in the first gate metal layer.
  • this embodiment is not limited to this.
  • Figure 37 is another schematic diagram of the arrangement of sub-pixels in a display area according to at least one embodiment of the present disclosure.
  • each pixel unit in the display area may include: a first sub-pixel 15 emitting a first color light, a second sub-pixel 16 emitting a second color light, and a third sub-pixel 17 emitting a third color light.
  • the multiple sub-pixels may be arranged in an array along a first direction D1 and a second direction D2.
  • the multiple first sub-pixels 15 may be arranged in a row along the first direction D1
  • the multiple second sub-pixels 16 may be arranged in a row along the first direction D1
  • the multiple third sub-pixels 17 may be arranged in a row along the first direction D1.
  • the first sub-pixels 15, the third sub-pixels 17, and the second sub-pixels 16 may be periodically arranged along the second direction D2.
  • the first sub-pixel 15 may be a red sub-pixel (R)
  • the second sub-pixel 16 may be a blue sub-pixel (B)
  • the third sub-pixel 17 may be a green sub-pixel (G);
  • the multiple sub-pixels may be arranged in a Real RGB arrangement.
  • Figures 38A to 38F illustrate exemplary connection methods for multiple first adapter units according to at least one embodiment of the present disclosure.
  • Figures 38A to 38F illustrate the sub-pixel arrangement of the display area as shown in Figure 37 .
  • a group of first adapter units in the first border area can utilize a connection method using three first adapter units, as shown in at least one of Figures 38A to 38F.
  • the order in which data signals are transmitted from the data contact pads connected to the second connection terminals of the multiple groups of first adapter units in this example can be derived from the 1-in-1 or multiple-in-1 method described in the aforementioned embodiments.
  • the three first connection terminals 311 and the three second connection terminals 312 can be connected in a one-to-one correspondence via three first-sequence connection lines 314.
  • the data signals transmitted by the second connection terminals 312 are configured to correspond to RGB in sequence
  • the data signals transmitted by the first connection terminal 311 are configured to correspond to RGB in sequence after passing through the three first-sequence transfer lines 314.
  • the three first-sequence transfer lines 314 can all be located in the second source/drain metal layer.
  • the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence via a first sequential connection line 314, a first plug-in sequence connection line 313a, and a second plug-in sequence connection line 313b.
  • the first sequential connection line 314 can connect the first first connection terminal 311 and the first second connection terminal 312
  • the first plug-in sequence connection line 313a can connect the second first connection terminal 311 and the third second connection terminal 312
  • the second plug-in sequence connection line 313b can connect the third first connection terminal 311 and the second second connection terminal 312.
  • the orthographic projections of the first plug-in sequence connection line 313a and the second plug-in sequence connection line 313b on the substrate may overlap.
  • the first sequential connection line 314 and the second plug-in sequence connection line 313b can be located in the second source-drain metal layer, and the first plug-in sequence connection line 313a can be located in the first source-drain metal layer.
  • the data signals transmitted by the three second connection terminals 312 are configured to correspond to RBG in sequence
  • the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.
  • three first connection terminals 311 and three second connection terminals 312 can be connected in sequence through a first plug-in sequence connection line 313a, a second plug-in sequence connection line 313b, and a first sequence connection line 314.
  • the first plug-in sequence transfer line 313a can connect the first first connection terminal and the second second connection terminal
  • the second plug-in sequence transfer line 313b can connect the second first connection terminal and the first second connection terminal
  • the first sequence transfer line 314 can connect the third first connection terminal and the third second connection terminal.
  • the orthographic projections of the first plug-in sequence transfer line 313a and the second plug-in sequence transfer line 313b on the substrate may overlap.
  • the first sequence transfer line 314 and the second plug-in sequence transfer line 313b can be located in the second source-drain metal layer, and the first plug-in sequence transfer line 313a can be located in the first source
  • the data signals transmitted by the three second connection terminals 312 are configured to correspond to GRB in sequence
  • the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.
  • the three first connection terminals 311 and the three second connection terminals 312 can be connected sequentially via a first plug-in sequence adapter 313a and two second plug-in sequence adapters 313b.
  • the first plug-in sequence adapter 313a can connect the first first connection terminal and the three second connection terminals
  • the first second plug-in sequence adapter 313b can connect the second first connection terminal and the first second connection terminal
  • the second second plug-in sequence adapter 313b can connect the third first connection terminal and the second second connection terminal.
  • the orthographic projection of the first plug-in sequence adapter 313a on the substrate can overlap with the orthographic projections of the two second plug-in sequence adapters 313b on the substrate.
  • the first plug-in sequence adapter 313a can be located in the first source-drain metal layer
  • the two second plug-in sequence adapters 313b can be located in the second source-drain metal layer.
  • the data signals transmitted by the three second connection terminals 312 are configured to correspond sequentially to GBR
  • the data signals transmitted by the three first connection terminals 311 are configured to correspond sequentially to RGB.
  • the three first connection terminals 311 and the three second connection terminals 312 can be connected sequentially via two first plug-in sequence adapters 313a and one second plug-in sequence adapter 313b.
  • the first first plug-in sequence adapter 313a can connect the first first connection terminal and the second second connection terminal
  • the second first plug-in sequence adapter 313a can connect the second first connection terminal and the third second connection terminal
  • the second plug-in sequence adapter 313b can connect the third first connection terminal and the first second connection terminal.
  • the orthographic projection of the second plug-in sequence adapter 313b on the substrate overlaps with the orthographic projection of the two first plug-in sequence adapters 313a on the substrate.
  • the two first plug-in sequence adapters 313a can be located in the second source-drain metal layer
  • the second plug-in sequence adapter 313b can be located in the first source-drain metal layer.
  • the data signals transmitted by the three second connection terminals 312 are configured to correspond to BRG in sequence
  • the data signals transmitted by the three first connection terminals 311 are configured to correspond to RGB in sequence.
  • the three first connection terminals 311 and the three second connection terminals 312 can be connected in sequence through a first plug-in sequence adapter 313a, a first sequence adapter 314, and a second plug-in sequence adapter 313b.
  • the first plug-in sequence adapter 313a can connect the first first connection terminal and the third second connection terminal
  • the first sequence adapter 314 can connect the second first connection terminal and the second second connection terminal
  • the second plug-in sequence adapter 313b can connect the third first connection terminal and the first second connection terminal.
  • the orthographic projection of the first plug-in sequence adapter 313a on the substrate overlaps with the orthographic projections of the first sequence adapter 314 and the second plug-in sequence adapter 313b on the substrate.
  • the first plug-in sequence adapter 313a can be located in the second source and drain metal layer
  • the second plug-in sequence adapter 313b can be located in the first source and drain metal layer
  • the first sequence adapter 314 can be located in the first gate metal layer.
  • the display substrate provided in this embodiment by providing multiple groups of first adapter units to connect multiple data lead lines and multiple data contact pads, can use multiple groups of first adapter units to adjust the order of data signals transmitted by the data contact pads.
  • multiple groups of second adapter units by adjusting the order of data signals in conjunction with multiple groups of second adapter units, it is possible to avoid the jumper design in the second fan-out area, which is beneficial to reducing the defects caused by the jumper design, thereby improving the reliability of the display substrate.
  • This embodiment also provides a display substrate, including a substrate, a plurality of sub-pixels, a plurality of first data lines, a plurality of second data lines, a plurality of data connection lines, a plurality of data lead-out lines, and a plurality of groups of test circuits.
  • the substrate includes: a display area and a first frame area located on one side of the display area along a first direction, the first frame area including: a first signal access area and a wiring lead-out area located between the first signal access area and the display area.
  • a plurality of sub-pixels are arranged on one side of the substrate and located in the display area.
  • a plurality of first data lines, a plurality of second data lines, and a plurality of data connection lines are located in the display area; the plurality of first data lines and the plurality of second data lines are configured to provide data signals to the plurality of sub-pixels, and the plurality of first data lines are connected to the plurality of data connection lines.
  • a plurality of data lead-out lines are located in the wiring lead-out area, and the plurality of data lead-out lines are connected to the plurality of second data lines and the plurality of data connection lines.
  • a plurality of groups of test circuits are located in the wiring lead-out area and arranged in sequence along the second direction, and each group of test circuits Connected to m consecutively arranged data lead lines, the second direction intersects the first direction; m is an integer greater than 1.
  • Each group of test circuits includes: a first test circuit and b second test circuits, a and b are both integers greater than 0, and twice the sum of a and b is equal to m.
  • the first test circuit includes: a first test transistor, a second test transistor, and a third test transistor; the gate of the first test transistor is connected to the first test control line, the first electrode of the first test transistor is connected to the first test data line, the gate of the second test transistor is connected to the second test control line, the first electrode of the second test transistor is connected to the second test data line, and the second electrode of the first test transistor and the second electrode of the second test transistor are connected to the same data lead line; the gate of the third test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line.
  • the second test circuit includes: a fourth test transistor, a fifth test transistor, and a sixth test transistor; the gate of the fourth test transistor is connected to the second test control line, the first electrode of the fourth test transistor is connected to the first test data line, the gate of the fifth test transistor is connected to the first test control line, the first electrode of the fifth test transistor is connected to the second test data line, and the second electrode of the fourth test transistor and the second electrode of the fifth test transistor are connected to the same data lead line; the gate of the sixth test transistor is connected to the third test control line, and the first electrode of the third test transistor is connected to the third test data line; the second electrode of the first test transistor, the second electrode of the third test transistor, the second electrode of the fourth test transistor, and the second electrode of the sixth test transistor are connected to different data lead lines.
  • This embodiment adjusts the transmission order of the test data signals by providing multiple test circuits, thereby avoiding the jumper design in the second fan-out area, and is beneficial for reducing defects caused by the jumper design, thereby improving the reliability of the display substrate.
  • the first test transistor, the second test transistor, and the third test transistor of the first test circuit are arranged along the first direction; the fourth test transistor, the fifth test transistor, and the sixth test transistor of the second test circuit are arranged along the first direction.
  • the first test transistor and the fourth test transistor are aligned in the second direction, the second test transistor and the fifth test transistor are aligned in the second direction, and the third test transistor and the sixth test transistor are aligned in the second direction.
  • each group of test circuits includes: two first test circuits and two second test circuits; wherein one first test circuit, two second test circuits, and one first test circuit are arranged along the second direction.
  • each group of test circuits includes: three first test circuits and three second test circuits; wherein, one first test circuit, two second test circuits, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits and one first test circuit are arranged in a direction opposite to the second direction.
  • each group of test circuits includes: four first test circuits and four second test circuits; wherein, one first test circuit, two second test circuits, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged in a direction opposite to the second direction.
  • each group of test circuits includes: five first test circuits and five second test circuits; wherein, one first test circuit, two second test circuits, one first test circuit, one second test circuit, one first test circuit, one second test circuit, two first test circuits and one second test circuit are arranged along the second direction; or, one first test circuit, one second test circuit, one first test circuit, one second test circuit, one first test circuit, two second test circuits, one first test circuit, one second test circuit and one first test circuit are arranged in the opposite direction of the second direction.
  • FIG 39 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.
  • display substrate 910 may be an OLED display substrate.
  • Display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.
  • the reference terms "one embodiment”, “some embodiments”, “example” or “some examples” and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application.
  • the schematic representations of the above terms do not necessarily refer to the same embodiment or example.
  • the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
  • those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

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Abstract

一种显示基板，包括：衬底(10)、设置在衬底(10)一侧且位于显示区域(AA)的多个子像素(PX)、多条第一数据线(DLa)、多条第二数据线(DLb)和多条数据连接线(25)、位于走线引出区域的多条数据引出线、多组第一转接单元(300a、300b)和多组第二转接单元(32a、32b)、位于第一信号接入区域(B134)的多个数据接触垫(27)。多组第一转接单元(300a、300b)位于多组第二转接单元(32a、32b)远离显示区域(AA)的一侧。多条数据引出线通过多组第一转接单元(300a、300b)与多个数据接触垫(27)连接，通过多组第二转接单元(32a、32b)与多条第二数据线(DLb)和多条数据连接线(25)连接。

Description

显示基板及显示装置 技术领域
本文涉及但不限于显示技术领域，尤指一种显示基板及显示装置。
背景技术
有机发光二极管(OLED，Organic Light Emitting Diode)和量子点发光二极管(QLED，Quantum-dot Light Emitting Diode)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本实施例提供一种显示基板及显示装置。
一方面，本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一数据线、多条第二数据线、多条数据转接线、多条数据引出线、多个数据接触垫以及多组转接单元。衬底包括显示区域和沿第一方向位于显示区域一侧的第一边框区域，第一边框区域包括：第一信号接入区域以及位于第一信号接入区域和显示区域之间的走线引出区域。多个子像素设置在衬底的一侧且位于显示区域。多条第一数据线、多条第二数据线以及多条数据连接线位于显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接。多条数据引出线位于走线引出区域。多个数据接触垫位于第一信号接入区域。多组第一转接单元和多组第二转接单元位于所述走线引出区域，所述多组第一转接单元位于所述多组第二转接单元远离所述显示区域的一侧，所述多组第一转接单元沿第二方向排布，所述多组第二转接单元沿所述第二方向排布，所述第二方向与所述第一方向交叉。其中，所述多条数据引出线通过所述多组第一转接单元与所述多个数据接触垫连接，还通过所述多组第二转接单元与所述多条第二数据线和所述多条数据连接线连接，使得所述多个数据接触垫提供的数据信号的顺序与沿所述第二方向排布的所述多条第二数据线和所述多条数据连接线所需的数据信号的顺序匹配。
在一些示例性实施方式中，每组第一转接单元包括：m个第一连接端、m个第二连接端、以及m条第一转接线；每条第一转接线连接在一个第一连接端和一个第二连接端之间；每个第一连接端与一条数据引出线连接，每个第二连接端与一个数据接触垫连接；所述m个第一连接端沿所述第二方向排布且对应不同的第一排布序号，所述m个第二连接端沿所述第二方向排布且对应不同的第二排布序号。每组第一转接单元内的m条第一转接线包括：a条插序转接线，每条插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号不同；m和a均为大于1的整数，且m大于或等于a。其中，第二方向与第一方向交叉。
在一些示例性实施方式中，每组第一转接单元内的a条插序转接线包括：a1条第一插序转接线和a2条第二插序转接线，a1和a2均为大于0的整数，且a1与a2之和为a；所述第一插序转接线所连接的第一连接端对应的第一排布序号小于所连接的第二连接端对应的第二排布序号；所述第二插序转接线所连接的第一连接端对应的第一排布序号大于 所连接的第二连接端对应的第二排布序号。
在一些示例性实施方式中，所述第一插序转接线所连接的第二连接端对应的第二排布序号与所连接的第一连接端对应的第一排布序号之差，大于或等于所述第二插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号之差。
在一些示例性实施方式中，所述第一插序转接线在所述衬底的正投影与至少一条第二插序转接线在所述衬底的正投影存在交叠。
在一些示例性实施方式中，每组第一转接单元内的m条转接线还包括：b条第一顺序转接线，每条第一顺序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号相同；b为大于1的整数，且b小于或等于a。
在一些示例性实施方式中，所述b条第一顺序转接线与所述第一插序转接线为同层结构，或者，至少一条第一顺序转接线位于所述第一插序转接线和所述第二插序转接线靠近所述衬底的一侧。
在一些示例性实施方式中，m为8；每组第一转接单元包括：八个第一连接端、八个第二连接端、以及八条第一转接线；所述八个第一连接端沿所述第二方向依次排布，所述八个第二连接端沿所述第二方向依次排布且位于所述八个第一连接端靠近所述第一信号接入区域的一侧，所述八条第一转接线包括两条第一插序转接线、两条第二插序转接线以及四条第一顺序转接线；所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值包括：1、5。
在一些示例性实施方式中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数。在第一时段，每组第一转接单元内的所述八个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第二子像素、第三子像素、第三子像素、第二子像素、第一子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第三子像素、第二子像素、第二子像素、第三子像素、第三子像素和第一子像素。在所述第二时段，每组第一转接单元内的所述八个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第一子像素、第三子像素、第三子像素、第一子像素、第二子像素和第三子像素，或者配置为依次对应第二子像素、第三子像素、第三子像素、第一子像素、第一子像素、第三子像素、第三子像素和第二子像素。
在一些示例性实施方式中，m为12。每组第一转接单元包括：十二个第一连接端、十二个第二连接端、以及十二条第一转接线；所述十二个第一连接端沿所述第二方向依次排布，所述十二个第二连接端沿所述第二方向依次排布且位于所述十二个第一连接端靠近所述第一信号接入区域的一侧，所述十二条第一转接线包括四条第一插序转接线、四条第二插序转接线以及四条第一顺序转接线；所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值包括：1、3、7、9。
在一些示例性实施方式中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据 信号，其中，e为大于0的整数。在所述第一时段，每组第一转接单元内的所述十二个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第一子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第二子像素、第三子像素、第二子像素、第三子像素、第三子像素和第一子像素。在所述第二时段，每组第一转接单元内的所述十二个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第二子像素、第一子像素和第三子像素，或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第一子像素、第三子像素、第一子像素、第三子像素、第三子像素和第二子像素。
在一些示例性实施方式中，m为16。每组第一转接单元包括：十六个第一连接端、十六个第二连接端、以及十六条第一转接线；所述十六个第一连接端沿所述第二方向依次排布，所述十六个第二连接端沿所述第二方向依次排布且位于所述十六个第一连接端靠近所述第一信号接入区域的一侧，所述十六条第一转接线包括四条第一插序转接线、四条第二插序转接线和八条第一顺序转接线；所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值包括：1、3、9、11。
在一些示例性实施方式中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数。在所述第一时段，每组第一转接单元内的所述十六个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素和第一子像素。在所述第二时段，每组第一转接单元内的所述十六个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素和第三子像素，或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素和第二子像素。
在一些示例性实施方式中，m为20。每组第一转接单元包括：二十个第一连接端、二十个第二连接端、以及二十条第一转接线；所述二十个第一连接端沿所述第二方向依次排布，所述二十个第二连接端沿所述第二方向依次排布且位于所述二十个第一连接端靠近所述第一信号接入区域的一侧，所述二十条第一转接线包括六条第一插序转接线、六条第二插序转接线和八条第一顺序转接线；所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值包括：1、3、5、11、13、15。
在一些示例性实施方式中，位于所述显示区域的一个像素单元包括：一个出射第一颜 色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数。在所述第一时段，每组第一转接单元内的所述二十个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第二子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第二子像素、第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素和第一子像素。在所述第二时段，每组第一转接单元内的所述十六个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素和第三子像素，或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素和第二子像素。
在一些示例性实施方式中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。与所述多组第一转接单元的第一连接端连接的多条数据引出线包括：第一组数据引出线和第二组数据引出线，所述第一组数据引出线和第二组数据引出线位于不同导电层，且沿所述第二方向交替设置，所述第一组数据引出线配置为传输所述第三子像素所需的数据信号，所述第二组数据引出线配置为传输所述第一子像素和所述第二子像素所需的数据信号。
在一些示例性实施方式中，显示基板还包括：位于所述走线引出区域且沿第二方向依次排布的多组测试电路；所述多组测试电路在所述第一方向上位于所述多组第一转接单元远离所述第一信号接入区域的一侧；其中，一组测试电路与一组第一转接单元所连接的m条数据引出线连接；所述第二方向与所述第一方向交叉；每组测试电路包括：a个第一测试电路和b个第二测试电路；a与b之和的两倍等于m，a和b均为大于0的整数。所述第一测试电路包括：第一测试晶体管、第二测试晶体管和第三测试晶体管；所述第一测试晶体管的栅极与第一测试控制线连接，所述第一测试晶体管的第一极与第一测试数据线连接，所述第二测试晶体管的栅极与第二测试控制线连接，所述第二测试晶体管的第一极与第二测试数据线连接，所述第一测试晶体管的第二极和所述第二测试晶体管的第二极与同一条数据引出线连接；所述第三测试晶体管的栅极与第三测试控制线连接，所述第三测试晶体管的第一极与第三测试数据线连接。所述第二测试电路包括：第四测试晶体管、第五测试晶体管和第六测试晶体管；所述第四测试晶体管的栅极与所述第二测试控制线连接，所述第四测试晶体管的第一极与所述第一测试数据线连接，所述第五测试晶体管的栅极与所述第一测试控制线连接，所述第五测试晶体管的第一极与所述第二测试数据线连接，所述第四测试晶体管的第二极和所述第五测试晶体管的第二极与同一条数据引出线连接；所述第六测试晶体管的栅极与所述第三测试控制线连接，所述第三测试晶体管的第一极与所述第三测试数据线连接；所述第一测试晶体管的第二极、所述第三测试晶体管的第二极、所述第四测试晶体管的第二极和所述第六测试晶体管的第二极与不同的数据引出线连接。
在一些示例性实施方式中，所述第一测试电路的第一测试晶体管、第二测试晶体管和 第三测试晶体管沿所述第一方向排布；所述第二测试电路的第四测试晶体管、第五测试晶体管和第六测试晶体管沿所述第一方向排布。所述第一测试晶体管和所述第四测试晶体管在所述第二方向对齐设置，所述第二测试晶体管和所述第五测试晶体管在所述第二方向对齐设置，所述第三测试晶体管和所述第六测试晶体管在所述第二方向对齐设置。
在一些示例性实施方式中，m为8。每组测试电路包括：两个第一测试电路和两个第二测试电路；其中，一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向排布。
在一些示例性实施方式中，m为12。每组测试电路包括：三个第一测试电路和三个第二测试电路；其中，一个第一测试电路、两个第二测试电路、两个第一测试电路和一个第二测试电路沿着所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为16。每组测试电路包括：四个第一测试电路和四个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为20。每组测试电路包括：五个第一测试电路和五个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试机电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，所述显示区域的单个像素单元包括：c个子像素，m为c的k倍，k为大于1的整数。
另一方面，本实施例提供一种显示装置，包括如前所述的显示基板。
另一方面，本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一数据线、多条第二数据线、多条数据连接线、多条数据引出线、以及多组测试电路。衬底包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：第一信号接入区域以及位于所述第一信号接入区域和所述显示区域之间的走线引出区域。多个子像素设置在所述衬底的一侧且位于所述显示区域。多条第一数据线、多条第二数据线以及多条数据连接线，位于所述显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接。多条数据引出线位于所述走线引出区域，所述多条数据引出线与所述多条第二数据线和所述多条数据连接线连接。多组测试电路位于所述走线引出区域且沿第二方向依次排布，每组测试电路与m条连续排布的数据引出线连接，所述第二方向与所述第一方向交叉；m为大于1的整数。每组测试电路包括：a个第一测试电路和b个第二测试电路，a和b均为大于0的整数，且a与b之和的两倍等于m。所述第一测试电路包括：第一测试晶体管、第二测试晶体管和第三测试晶体管；所述第一测试晶体管的栅极与第一测试控制线连接，所述第一测试晶体管的第一极与第一测试数据线连接，所述第二测试晶体管的栅极与第二测试控制线连接，所述第二测试晶体管的第一极与第二测试数据线连接，所述第一测试晶体管的第二极和所述第二测试晶体管的第二极与同一条数据引出线连接；所述第三测试晶体管的栅极与第三测试控制线连接，所述第三测试晶体管的第一极与第三测试数据线连接。 所述第二测试电路包括：第四测试晶体管、第五测试晶体管和第六测试晶体管；所述第四测试晶体管的栅极与所述第二测试控制线连接，所述第四测试晶体管的第一极与所述第一测试数据线连接，所述第五测试晶体管的栅极与所述第一测试控制线连接，所述第五测试晶体管的第一极与所述第二测试数据线连接，所述第四测试晶体管的第二极和所述第五测试晶体管的第二极与同一条数据引出线连接；所述第六测试晶体管的栅极与所述第三测试控制线连接，所述第三测试晶体管的第一极与所述第三测试数据线连接；所述第一测试晶体管的第二极、所述第三测试晶体管的第二极、所述第四测试晶体管的第二极和所述第六测试晶体管的第二极与不同的数据引出线连接。
在一些示例性实施方式中，所述第一测试电路的第一测试晶体管、第二测试晶体管和第三测试晶体管沿所述第一方向排布；所述第二测试电路的第四测试晶体管、第五测试晶体管和第六测试晶体管沿所述第一方向排布。所述第一测试晶体管和所述第四测试晶体管在所述第二方向对齐设置，所述第二测试晶体管和所述第五测试晶体管在所述第二方向对齐设置，所述第三测试晶体管和所述第六测试晶体管在所述第二方向对齐设置。
在一些示例性实施方式中，m为8。每组测试电路包括：两个第一测试电路和两个第二测试电路；其中，一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向排布。
在一些示例性实施方式中，m为12。每组测试电路包括：三个第一测试电路和三个第二测试电路；其中，一个第一测试电路、两个第二测试电路、两个第一测试电路和一个第二测试电路沿着所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为16。每组测试电路包括：四个第一测试电路和四个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为20。每组测试电路包括：五个第一测试电路和五个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试机电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。
图1为本公开至少一实施例的显示基板的示意图；
图2为本公开至少一实施例的第一边框区域的示意图；
图3A为本公开至少一实施例的显示区域的局部剖面示意图；
图3B为本公开至少一实施例的显示区域的另一局部剖面示意图；
图4为本公开至少一实施例的显示区域的子像素的一种排布示意图；
图5为本公开至少一实施例的第一边框区域的局部走线示意图；
图6为本公开至少一实施例的多组第一侧第一转接单元的示意图；
图7A为图6中的第一栅金属层和第二栅金属层的示意图；
图7B为图6中的第一源漏金属层的示意图；
图7C为图6中的第二源漏金属层的示意图；
图8为图6中沿Q-Q’方向的局部剖面示意图；
图9A和图9B为图6所示的一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图10为本公开至少一实施例的多组第二侧第一转接单元的示意图；
图11为图10所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图12为本公开至少一实施例的一组第一侧第二转接单元的示意图；
图13为本公开至少一实施例的第一测试电路和第二测试电路的等效电路图；
图14A为本公开至少一实施例的第一组测试电路的平面示意图；
图14B为图14A中第一源漏金属层的示意图；
图14C为图14A中第一半导体层、第一栅金属层和第二栅金属层的示意图；
图15为本公开至少一实施例的第三测试电路的等效电路图；
图16为本公开至少一实施例的一组第一侧第一转接单元的另一示意图；
图17为图16中的第一栅金属层和第二栅金属层的示意图；
图18为图16所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图19为本公开至少一实施例的一组第一侧第二转接单元的示意图；
图20为本公开至少一实施例的第一组测试电路的平面示意图；
图21为本公开至少一实施例的一组第二侧第一转接单元的示意图；
图22为图21所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图23为本公开至少一实施例的第二组测试电路的平面示意图；
图24为本公开至少一实施例的一组第一侧第一转接单元的另一示意图；
图25为图24所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图26为图24所示的一组第一侧第一转接单元对应的第一组测试电路的平面示意图；
图27为本公开至少一实施例的一组第二侧第一转接单元的示意图；
图28为图27所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图29为本公开至少一实施例的第二组测试电路的平面示意图；
图30为本公开至少一实施例的一组第一侧第一转接单元的另一示意图；
图31为图30所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图32为图30所示的一组第一侧第一转接单元对应的第一组测试电路的平面示意图；
图33为本公开至少一实施例的一组第二侧第一转接单元的示意图；
图34为图33所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图；
图35为本公开至少一实施例的第二组测试电路的平面示意图；
图36A至图36C为本公开至少一实施例的多个第一转接单元的连接方式示例图；
图37为本公开至少一实施例的显示区域的子像素的另一排布示意图；
图38A至图38F为本公开至少一实施例的多个第一转接单元的连接方式示例图；
图39为本公开至少一实施例的显示装置的示意图。
详述
下面将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为其他形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了一个或多个构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中一个或多个部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。本公开中的“多个”表示两个及以上的数量。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述的构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。其中，“连接”可以包括“电连接”，“电连接”可以包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的传输，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有多种功能的元件等。
在本说明书中，晶体管是指至少包括栅极(栅电极)、漏极以及源极这三个端子的元 件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏极、沟道区域以及源极。在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。另外，栅极还可以称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源极”及“漏极”的功能有时互相调换。因此，在本说明书中，“源极”和“漏极”可以互相调换。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，圆形、椭圆形、三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似圆形、近似椭圆形、近似三角形、近似矩形、近似梯形、近似五边形或近似六边形等，可以存在公差导致的一些小变形，例如可以存在导角、弧边以及变形等。
本说明书中的“约”、“大致”，是指不严格限定界限，允许工艺和测量误差范围内的情况。在本公开中，“相同”包括数值相差10％以内的情况，比如数值相差5％以内的情况。
在本说明书中，A沿着B方向延伸是指，A可以包括主体部分和与主体部分连接的次要部分，主体部分是线、线段或条形状体，主体部分沿着B方向伸展，且主体部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。本说明书中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
本说明书中所说的“A和B为同层结构”是指，A和B通过同一次构图工艺同时形成。“相同层”不总是意味着层的厚度或层的高度在截面图中是相同的。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
图1为本公开至少一实施例的显示基板的示意图。在一些示例中，如图1所示，显示基板可以为包括线性边的闭合多边形。显示基板可以包括：显示区域AA和位于显示区域AA周围的边框区域BB。例如，显示区域AA可以包括：在第一方向D1上相对设置的第一显示边缘(下显示边缘)和第二显示边缘(上显示边缘)，以及在第二方向D2上相对设置的第三显示边缘(左显示边缘)和第四显示边缘(右显示边缘)。第一显示边缘和第二显示边缘可以为相互平行的线性边，第三显示边缘和第四显示边缘可以为相互平行的线性边。相邻线性边之间可以通过弯曲边缘(例如弧形边缘)连接。
在一些示例中，如图1所示，边框区域BB可以包括：沿第一方向D1位于显示区域AA两侧的第一边框区域B1和第四边框区域B4、沿第二方向D2位于显示区域AA两侧的第二边框区域B2和第三边框区域B3。第一边框区域B1可以连接第一显示边缘，第二边框区域B2可以连接第三显示边缘，第三边框区域B3可以连接第四显示边缘，第四边框区域B4可以连接第二显示边缘。第一边框区域B1可以与第二边框区域B2和第三边框区域B3连通，第三边框区域B4可以与第二边框区域B2和第三边框区域B3连通，第一边框区域B1、第二边框区域B2、第三边框区域B3和第四边框区域B4连通后可以围绕显示区域AA。例如，第一边框区域B1还可以称为显示基板的下边框区域，第二边框区域B2还可以称为显示基板的左边框区域，第三边框区域B3还可以称为显示基板的右边框区域，第四边框区域B4还可以称为显示基板的上边框区域。然而，本实施例对此并不限定。
图2为本公开至少一实施例的第一边框区域的示意图。在一些示例中，如图1和图2所示，第一边框区域B1可以包括：在第一方向D1上沿着远离显示区域AA的一侧依次 排布的第一子区域B11、弯折区域B12和第二子区域B13。第一子区域B11还可以称为第一扇出区域。第一子区域B11可以与第二边框区域B2和第三边框区域B3连通，并与显示区域AA连接。弯折区域B12可以连接在第一子区域B11和第二子区域B13之间。弯折区域B12可以配置为使第二子区域B13弯折到显示区域AA的背面。
在一些示例中，如图2所示，第一边框区域B1的第二子区域B13可以包括：在第一方向D1上沿着远离弯折区域B12的方向依次设置的第二扇出区域B131、电路设置区域B132、第三扇出区域B133、第一信号接入区域B134和第二信号接入区域B135。第一信号接入区域B134靠近显示区域AA一侧的区域还可以称为走线引出区域。本示例的走线引出区域可以包括：第一子区域B11、弯折区域B12、第二扇出区域B131、电路设置区域B132和第三扇出区域B133。然而，本实施例对此并不限定。
在一些示例中，电路设置区域B132可以设置有多个测试电路，多个测试电路可以配置为给显示区域AA的数据线提供测试数据信号。在另一些示例中，电路设置区域还可以设置多个静电释放电路，多个静电释放电路可以被配置为通过消除静电防止显示基板的静电损伤。本实施例对此并不限定。
在一些示例中，第一信号接入区域B134可以设置有多个第一接触垫，多个第一接触垫可以配置为连接集成电路(IC)。第二信号接入区域B135可以设置有多个第二接触垫，多个第二接触垫可以配置为与外部的柔性电路板(FPC)绑定连接。第一信号接入区域B134内的至少一个第一接触垫和第二信号接入区域B135内的至少一个第二接触垫可以通过走线连接。
在一些示例中，如图1所示，显示基板的显示区域AA可以至少包括：多个子像素PX、多条栅线GL和多条数据线(例如包括多条第一数据线DLa和多条第二数据线DLb)。多条栅线GL可以沿第二方向D2延伸，并沿第一方向D1排布；多条数据线可以沿第一方向D1延伸，并沿第二方向D2排布，例如，多条第一数据线DLa在第二方向D2上可以位于多条第二数据线DLb的外侧。多条数据线可以与多个子像素PX电连接，多条数据线可以被配置为向多个子像素PX提供数据信号。多条栅线GL可以与多个子像素PX电连接，多条栅线GL可以被配置为向多个子像素PX提供像素控制信号。例如，像素控制信号可以包括扫描信号，或者可以包括扫描信号和发光控制信号，或者可以包括扫描信号、复位控制信号和发光控制信号。
在一些示例中，第二方向D2可以是显示区域AA内栅线GL的延伸方向(例如，行方向)；第一方向D1可以是显示区域AA内数据线的延伸方向(例如，列方向)。第一方向D1与第二方向D2可以相互交叉，例如可以相互垂直。
在一些示例中，显示区域AA还可以设置有多条数据连接线25。第一数据线DLa可以通过数据连接线25与第一子区域B11的第一数据引出线连接。第二数据线DLb可以直接延伸至第一子区域B11，并与第一子区域B11的第一数据引出线连接。数据连接线25可以包括：沿第二方向D2延伸的第一数据连接段251和沿第一方向D1延伸的第二数据连接段252。第一数据连接段251可以连接在第一数据线DLa和第二数据连接段252之间，第二数据连接段252可以与第一子区域B11的第一数据引出线连接。第二数据连接段252可以位于所连接的第一数据线DLa远离显示基板的边缘的一侧。在一些示例中，第一数据连接段251和第二数据连接段252可以位于第一数据线DLa和第二数据线DLb远离衬底的一侧。然而，本实施例对此并不限定。通过在显示区域内设置数据连接线，使得第一子区域内的第一数据引出线通过数据连接线与第一数据线连接，可以有效减少第一子区域沿第一方向的长度，从而大大缩减下边框的尺寸。
在一些示例中，显示区域AA的一个像素单元可以包括三个子像素，三个子像素可以分别为出射第一颜色光(例如，红光)的第一子像素、出射第二颜色光(例如，蓝光)的第二子像素和出射第三颜色光(例如，绿光)的第三子像素。然而，本实施例对此并不限定。在一些示例中，一个像素单元可以包括四个子像素，四个子像素可以分别为出射红光的子像素、出射绿光的子像素、出射蓝光的子像素和出射白光的子像素。又如，一个像素单元可以包括四个子像素，四个子像素可以包括一个出射红光的子像素、一个出射蓝光的子像素、以及两个出射绿光的子像素。
在一些示例中，一个子像素可以包括：像素电路以及与像素电路电连接的发光元件。像素电路可以包括多个晶体管和至少一个电容。例如，像素电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。其中，上述电路结构中的T指的是薄膜晶体管，C指的是电容，T前面的数字代表电路中薄膜晶体管的数量，C前面的数字代表电路中电容的数量。在一些示例中，像素电路中的多个晶体管可以包括P型晶体管和N型晶体管。在另一些示例中，像素电路中的多个晶体管可以为P型晶体管或者可以为N型晶体管，像素电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板的工艺难度，提高产品的良率。
在一些示例中，子像素的发光元件的形状可以是矩形、菱形、五边形或六边形。一个像素单元包括三个子像素时，三个子像素的发光元件可以采用水平并列、竖直并列或品字方式排列；一个像素单元包括四个子像素时，四个子像素的发光元件可以采用水平并列、竖直并列或正方形方式排列。然而，本实施例对此并不限定。
在一些示例中，发光元件可以是发光二极管(LED，Light Emitting Diode)、有机发光二极管(OLED，Organic Light Emitting Diode)、量子点发光二极管(QLED，Quantum Dot Light Emitting Diode)、微LED(包括：mini-LED或micro-LED)等中的任一者。例如，发光元件可以为OLED，发光元件在其对应的像素电路的驱动下可以发出红光、绿光、蓝光、或者白光等。发光元件发光的颜色可根据需要而定。在一些示例中，发光元件可以包括：阳极、阴极以及位于阳极和阴极之间的有机发光层。发光元件的阳极可以与对应的像素电路电连接。然而，本实施例对此并不限定。
图3A为本公开至少一实施例的显示区域的局部剖面示意图。图3A中以显示区域的一个子像素的结构为例进行示意。在本示例中，以像素电路包括低温多晶硅薄膜晶体管和氧化物薄膜晶体管为例进行说明。
在一些示例中，如图3A所示，在垂直于显示基板的方向上，显示基板的显示区域可以至少包括：衬底10、以及依次设置在衬底10上的电路结构层12、发光结构层13以及封装结构层14。电路结构层12可以至少包括：多个子像素的像素电路，每个子像素的像素电路可以包括多个晶体管和至少一个电容。发光结构层13可以至少包括：多个子像素的发光元件。在另一些示例中，显示基板还可以包括位于封装结构层远离衬底一侧的触控结构层。
在一些示例中，图3A中以每个子像素包括的一个第一类型晶体管21、一个第二类型晶体管22和一个电容23为例进行示意。其中，第一类型晶体管21可以为低温多晶硅薄膜晶体管，第二类型晶体管22可以为氧化物薄膜晶体管。
在一些示例中，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第二半导体层、第三栅金属层、第一源漏金属层和第二源漏金属层。第一半导体层和第一栅金属层之间可以设置有第一绝缘层101，第一栅金属层和第二栅金属层之间可以设置有第二绝缘层102；第二栅金属层和第二半导体层之间 可以设置有第三绝缘层103；第二半导体层和第三栅金属层之间可以设置有第四绝缘层104；第三栅金属层和第一源漏金属层之间可以设置有第五绝缘层105；第一源漏金属层和第二源漏金属层之间可以设置有第六绝缘层106(还可以称为钝化层)和第七绝缘层107(还可以称为第一平坦层)，第七绝缘层107可以位于第六绝缘层106远离衬底10的一侧；第二源漏金属层远离衬底10的一侧可以设置有第八绝缘层108(还可以称为第二平坦层)。其中，第一绝缘层101、第二绝缘层102、第三绝缘层103、第四绝缘层104、第五绝缘层105以及第六绝缘层106可以为无机绝缘层，第七绝缘层107和第八绝缘层108可以为有机绝缘层。然而，本实施例对此并不限定。在另一些示例中，第一半导体层靠近衬底一侧还可以设置缓冲层，缓冲层可以防止衬底中的有害物质侵入显示基板的内部，还可以增加显示基板中的膜层在衬底上的附着力。在另一些示例中，在缓冲层靠近衬底一侧还可以设置底部遮光金属层(BSM，Bottom Shielding Metal)，底部遮光金属层可以被配置为至少部分覆盖像素电路的晶体管的有源层，以避免外部光线对晶体管的性能产生影响。另一些示例中，第一源漏金属层和第二源漏金属层之间可以省略第六绝缘层，第一源漏金属层和第二源漏金属层之间可以仅设置第七绝缘层。
在一些示例中，如图3A所示，显示区域的第一半导体层可以至少包括：第一类型晶体管21的第一有源层210。第一类型晶体管21的第一有源层210可以包括：第一区2101、第二区2102以及位于第一区2101和第二区2102之间的沟道区2100。第一栅金属层可以至少包括：第一类型晶体管21的第一栅极213、以及电容23的第一极板231。第一类型晶体管21的第一栅极213在衬底10的正投影可以覆盖第一有源层210的沟道区2100在衬底10的正投影。第二栅金属层可以至少包括：电容23的第二极板232、第二类型晶体管22的第三栅极224。电容23的第二极板232和第一极板231在衬底10的正投影可以至少部分交叠，例如，两者可以重合。第二半导体层可以至少包括：第二类型晶体管22的第二有源层220。第三栅金属层可以至少包括：第二类型晶体管22的第二栅极223。第二类型晶体管22的第二栅极223在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。第二类型晶体管22的第三栅极224在衬底10的正投影与第二有源层220在衬底10的正投影可以部分交叠。第三栅极224可以为第二类型晶体管22的底栅，第二栅极223可以为第二类型晶体管22的顶栅。
在一些示例中，如图3A所示，显示区域的第一源漏金属层可以至少包括：第一类型晶体管21的第一源极211和第一漏极212、第二类型晶体管22的第二源极221和第二漏极222。第五绝缘层105在显示区域可以开设有多个像素过孔(例如，包括第一像素过孔、第二像素过孔、第三像素过孔和第四像素过孔)，第一像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第一区2101的至少部分表面；第二像素过孔内的第五绝缘层105、第四绝缘层104、第三绝缘层103、第二绝缘层102和第一绝缘层101可以被去掉，暴露出第一有源层210的第二区2102的至少部分表面。第三像素过孔和第四像素过孔内的第五绝缘层105、第四绝缘层104和第三绝缘层103可以被去掉，暴露出第二有源层220的两端的至少部分表面。第一类型晶体管21的第一源极211可以通过第一像素过孔与第一有源层210的第一区2101电连接，第一漏极212可以通过第二像素过孔与第一有源层210的第二区2102电连接。第二类型晶体管22的第二源极221可以通过第三像素过孔与第二有源层220的一端电连接，第二类型晶体管22的第二漏极222可以通过第四像素过孔与第二有源层220的另一端电连接。第二源漏金属层可以至少包括：第一转接电极241。第一转接电极241可以通过第六绝缘层106和第七绝缘层107开设的第五像素过孔与像素电路的第一类型晶体管21的第一漏极212电连接。本示例可以通过第一转接电极241实现像素电路与发光元件之间的电连接。
在一些示例中，显示区域的栅线例如可以位于第一栅金属层和第三栅金属层，显示区域的数据线例如可以位于第二源漏金属层，显示区域的第一电源线例如可以位于第二源漏金属层，显示区域的数据连接线的第一数据连接段例如可以位于第一源漏金属层，第二数据连接段例如可以位于第二源漏金属层。本实施例对此并不限定。在另一些示例中，显示区域的电路结构层还可以包括：位于第二源漏金属层远离衬底一侧的第三源漏金属层，数据连接线可以位于第三源漏金属层。
在一些示例中，如图3A所示，发光结构层13可以包括：像素定义层134和多个发光元件。例如，每个发光元件可以包括：叠设的第一电极131、有机发光层132和第二电极133。发光元件的第一电极131可以为阳极，第一电极131可以设置在第八绝缘层108上，并通过第八绝缘层108开设的第六像素过孔，与第一转接电极241电连接。像素定义层134设置在第一电极131和第八绝缘层108上，像素定义层134可以开设有多个像素开口，一个像素开口可以暴露出对应的一个第一电极131的至少部分表面。有机发光层132的至少部分可以设置在一个像素开口内，并与对应的第一电极131连接。第二电极133可以设置在有机发光层132上，并与有机发光层132连接。有机发光层132在第一电极131和第二电极133的驱动下可以出射相应颜色的光线。
在一些示例中，发光元件的有机发光层132可以包括发光层(EML，Emitting Layer)，以及包括以下至少一个膜层：空穴注入层(HIL，Hole Injection Layer)、空穴传输层(HTL，Hole Transport Layer)、空穴阻挡层(HBL，Hole Block Layer)、电子阻挡层(EBL，Electron Block Layer)、电子注入层(EIL，Electron Injection Layer)、电子传输层(ETL，Electron Transport Layer)。在第一电极131和第二电极133的电压驱动下，可以利用有机材料的发光特性根据需要的灰度发光。
在一些示例中，不同颜色的发光元件的发光层可以不同。例如，红色发光元件包括红色发光层，绿色发光元件包括绿色发光层，蓝色发光元件包括蓝色发光层。为了降低工艺难度和提升良率，位于发光层一侧的空穴注入层和空穴传输层可以采用共通层，位于发光层另一侧的电子注入层和电子传输层可以采用共通层。在一些示例中，空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以通过一次工艺(一次蒸镀工艺或一次喷墨打印工艺)制作，并通过形成的膜层表面段差或者通过表面处理等手段实现隔离。例如，相邻子像素对应的空穴注入层、空穴传输层、电子注入层和电子传输层中的任意一层或多层可以是隔离的。在一些示例中，有机发光层可以通过采用精细金属掩模版(FMM，Fine Metal Mask)或者开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一些示例中，如图3A所示，封装结构层14可以包括叠设的第一封装层141、第二封装层142和第三封装层143。其中，第一封装层141和第三封装层143可以采用无机材料，例如氮化硅、氧化硅、氮氧化硅等，无机材料的致密性高，可以防止水、氧等的侵入。第二封装层142可以设置在第一封装层141和第三封装层143之间，以保证外界水汽无法进入发光元件。第二封装层142可以采用有机材料，例如，可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，或者可以为高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一封装层141和第三封装层143的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。然而，本实施例对此并不限定。例如，封装结构层可以采用无机/有机/无机/有机/无机的五层叠设结构。
图3B为本公开至少一实施例的显示区域的另一局部剖面示意图。在一些示例中，像素电路中的多个像素晶体管的晶体管类型可以相同，例如可以均为低温多晶硅薄膜晶体管。图3B中以每个子像素包括的一个第一类型晶体管21和一个电容23为例进行示意。
在一些示例中，如图3B所示，显示区域的电路结构层12可以包括：设置在衬底10上的第一半导体层、第一栅金属层、第二栅金属层、第一源漏金属层以及第二源漏金属层。第一半导体层和第一栅金属层之间可以设置第一绝缘层101，第一栅金属层和第二栅金属层之间可以设置第二绝缘层102，第二栅金属层和第一源漏金属层之间可以设置第三绝缘层103，第一源漏金属层和第二源漏金属层之间可以设置第六绝缘层106和第七绝缘层107，第二源漏金属层远离衬底10的一侧可以设置第八绝缘层108。第七绝缘层107和第八绝缘层108可以为有机绝缘层，第一绝缘层101、第二绝缘层102和第三绝缘层103可以为无机绝缘层。关于本示例的显示基板的显示区域的其余结构可以参照图3A所示实施例的描述，故于此不再赘述。
随着OLED显示技术的广泛应用，消费者对OLED显示产品提出了更高的要求，高分辨率(PPI)显示产品和窄边框显示产品等成为显示产品发展的新趋势。为了实现窄边框，通过在显示区域设置数据连接线，使得第一边框区域的数据引出线可以通过数据连接线与第一数据线连接，可以有效减小第一子区域的长度，从而大大缩减下边框的尺寸。然而，在通过数据连接线对第一数据线进行转接的过程中，第一边框区域内的数据引出线的顺序会被打乱，使得第一边框区域的数据引出线的顺序不同于显示区域的数据线的顺序。在一些实现方式中，为了兼容常规集成电路，需要在第一边框区域(例如第二扇出区域)进行跳线设计，使得第一信号接入区域的数据接触垫传输的数据信号与显示区域的数据线的顺序相同。然而，在第二扇出区域设置的跳线容易引发多种不良：比如，第二扇出区域的部分跳线会与其他数据引出线或电源线存在交叠，从而容易造成数据信号的负载突变、电阻补偿困难等问题；又如，由于第二扇出区域的空间限制，第二扇出区域的跳线的布线密集且间隙较小，容易存在金属材料刻蚀残留(Remain)，从而造成走线短路(Short)的情况。
本实施例提供一种显示基板，包括：衬底、多个子像素、多条第一数据线、多条第二数据线、多条数据转接线、多条数据引出线、多个数据接触垫、多组第一转接单元和多组第二转接单元。衬底包括显示区域和沿第一方向位于显示区域一侧的第一边框区域，第一边框区域包括：第一信号接入区域以及位于第一信号接入区域和显示区域之间的走线引出区域。多个子像素设置在衬底的一侧且位于显示区域。多条第一数据线、多条第二数据线以及多条数据连接线位于显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接。多条数据引出线位于走线引出区域。多个数据接触垫位于第一信号接入区域。多组第一转接单元和多组第二转接单元位于走线引出区域，多组第一转接单元位于多组第二转接单元远离显示区域的一侧，多组第一转接单元沿第二方向排布，多组第二转接单元沿第二方向排布。第二方向与第一方向交叉，例如，第二方向可以垂直于第一方向。多条数据引出线通过所述多组第一转接单元与所述多个数据接触垫连接，还通过所述多组第二转接单元与所述多条第二数据线和所述多条数据连接线连接，使得所述多个数据接触垫提供的数据信号的顺序与沿所述第二方向排布的所述多条第二数据线和所述多条数据连接线所需的数据信号的顺序匹配。
本实施例提供的显示基板，通过多组第一转接单元连接多条数据引出线和多个数据接触垫，通过多组第二转接单元连接多条数据引出线与多条第二数据线和多条数据连接线，可以使得多个数据接触垫所传输的数据信号的顺序与多条第二数据线和多条数据连接线所需的数据信号的顺序匹配，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
在一些示例中，多个数据接触垫提供的数据信号的顺序可以适应显示区域的第二数据 线和数据连接线的排布顺序。多个数据接触垫提供的数据信号具有第一顺序，经过多组第一转接单元之后数据信号的顺序发生变化，例如具有第二顺序，经过多组第二转接单元之后数据信号的顺序再次发生变化，例如变回第一顺序，使得显示区域的第二数据线和数据连接线可以接收所需的数据信号。
在一些示例性实施方式中，每组第一转接单元包括：m个第一连接端、m个第二连接端、以及m条第一转接线；每条第一转接线连接在一个第一连接端和一个第二连接端之间；每个第一连接端与一条数据引出线连接，每个第二连接端与一个数据接触垫连接；所述m个第一连接端沿所述第二方向排布且对应不同的第一排布序号，所述m个第二连接端沿所述第二方向排布且对应不同的第二排布序号。每组第一转接单元内的m条第一转接线包括：a条插序转接线，每条插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号不同；其中，m和a均为大于1的整数，且m大于或等于a。在一些示例中，一个第一转接单元可以包括：依次连接的一个第一连接端、一条第一转接线以及一个第二连接端，一个第一转接单元可以实现数据接触垫与数据引出线之间的一路数据信号的传输。在一些示例中，一个第二转接单元可以包括：一条第二转接线，一个第二转接单元可以实现数据引出线与第二数据线或数据连接线之间的一路数据信号的传输。本实施例提供的显示基板，通过设置多组第一转接单元连接多条数据引出线和多个数据接触垫，可以利用多组第一转接单元来调整数据接触垫所传输数据信号的顺序，同时搭配多组第二转接单元对数据信号的顺序调整，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
在一些示例性实施方式中，显示区域的单个像素单元可以包括：c个子像素，m为c的k倍，k为大于1的整数。例如，一个像素单元包括四个子像素，m可以为4的整数倍，比如可以为8、12、16或20；一个像素单元包括三个子像素，m可以为3的整数倍，比如可以为6、9、12或15。
在一些示例性实施方式中，每组第一转接单元内的a条插序转接线可以包括：a1条第一插序转接线和a2条第二插序转接线，a1和a2均为大于0的整数，且a1与a2之和为a。第一插序转接线所连接的第一连接端对应的第一排布序号小于所连接的第二连接端对应的第二排布序号；第二插序转接线所连接的第一连接端对应的第一排布序号大于所连接的第二连接端对应的第二排布序号。在一些示例中，第一插序转接线所连接的第二连接端对应的第二排布序号与所连接的第一连接端对应的第一排布序号之差，可以大于或等于第二插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号之差。本示例通过在每组第一转接单元内设置第一插序转接线和第二插序转接线来调整数据信号的传输顺序，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
在一些示例性实施方式中，每组第一转接单元内的m条第一转接线还可以包括：b条第一顺序转接线，每条第一顺序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号相同；b为大于1的整数，且b小于或等于a。在一些示例中，所述b条顺序转接线与第一插序转接线可以为同层结构，或者，至少一条第一顺序转接线可以位于第一插序转接线和第二插序转接线靠近衬底的一侧。本示例通过在每组第一转接单元内利用第一顺序转接线和插序转接线的配合，来调整数据信号的传输顺序，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
在一些示例性实施方式中，m可以为8，每组第一转接单元可以包括两条第一插序转接线、两条第二插序转接线以及四条第一顺序转接线。第一插序转接线可以配置为连接第 i个第一连接端与第i+1个第二连接端；第二插序转接线可以配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值可以包括1、5。
在一些示例性实施方式中，m可以为12，每组第一转接单元可以包括四条第一插序转接线、四条第二插序转接线以及四条第一顺序转接线。第一插序转接线可以配置为连接第i个第一连接端与第i+1个第二连接端；第二插序转接线可以配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值可以包括1、3、7、9。
在一些示例性实施方式中，m可以为16，每组第一转接单元可以包括四条第一插序转接线、四条第二插序转接线和八条第一顺序转接线。第一插序转接线可以配置为连接第i个第一连接端与第i+1个第二连接端；第二插序转接线可以配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值可以包括1、3、9、11。
在一些示例性实施方式中，m可以为20，每组第一转接单元可以包括六条第一插序转接线、六条第二插序转接线和八条第一顺序转接线。第一插序转接线可以配置为连接第i个第一连接端与第i+1个第二连接端；第二插序转接线可以配置为连接第i+1个第一连接端与第i个第二连接端；其中，i的取值可以包括1、3、5、11、13、15。
在一些示例性实施方式中，位于显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素。与所述多组第一转接单元的第一连接端连接的多条数据引出线可以包括：第一组数据引出线和第二组数据引出线，所述第一组数据引出线和第二组数据引出线位于不同导电层，且沿所述第二方向交替设置，所述第一组数据引出线配置为传输所述第三子像素所需的数据信号，所述第二组数据引出线配置为传输所述第一子像素和所述第二子像素所需的数据信号。例如，第三子像素(例如绿色子像素G)对应的数据信号可以由位于第一栅金属层的数据引出线传输，第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)对应的数据信号可以由位于第二栅金属层的数据引出线传输，可以保证信号传输走线的均一性排布，避免将传输第三子像素对应的数据信号的数据引出线排布在不同导电层而引起负载差异，影响显示效果。
在一些示例性实施方式中，显示基板还可以包括：位于走线引出区域且沿第二方向依次排布的多组测试电路。所述多组测试电路在第一方向上可以位于多组第一转接单元远离第一信号接入区域的一侧。其中，一组测试电路与一组第一转接单元所连接的m条数据引出线连接。每组测试电路可以包括：a个第一测试电路和b个第二测试电路；a与b之和的两倍等于m，a和b均为大于0的整数。第一测试电路可以包括：第一测试晶体管、第二测试晶体管和第三测试晶体管。第一测试晶体管的栅极与第一测试控制线连接，第一测试晶体管的第一极与第一测试数据线连接，第二测试晶体管的栅极与第二测试控制线连接，第二测试晶体管的第一极与第二测试数据线连接，第一测试晶体管的第二极和第二测试晶体管的第二极与同一条数据引出线连接；第三测试晶体管的栅极与第三测试控制线连接，第三测试晶体管的第一极与第三测试数据线连接。第二测试电路可以包括：第四测试晶体管、第五测试晶体管和第六测试晶体管。第四测试晶体管的栅极与第二测试控制线连接，第四测试晶体管的第一极与第一测试数据线连接，第五测试晶体管的栅极与第一测试控制线连接，第五测试晶体管的第一极与第二测试数据线连接，第四测试晶体管的第二极和第五测试晶体管的第二极与同一条数据引出线连接；第六测试晶体管的栅极与第三测试控制线连接，第三测试晶体管的第一极与第三测试数据线连接。第一测试晶体管的第二极、第三测试晶体管的第二极、第四测试晶体管的第二极和第六测试晶体管的第二极与不同的数据引出线连接。本示例通过设置多组测试电路，来调整测试数据信号的传输顺序，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的 可靠性。
下面通过一些示例对本实施例的方案进行举例说明。
图4为本公开至少一实施例的显示区域的子像素的一种排布示意图。在一些示例中，如图4所示，显示区域的每个像素单元可以包括：一个出射第一颜色光的第一子像素15、一个出射第二颜色光的第二子像素16、以及两个出射第三颜色光的第三子像素17a和17b。多个像素单元可以在显示区域AA内阵列排布。多个子像素的像素电路可以沿第一方向D1和第二方向D2阵列排布。在单个像素单元内，四个子像素的发光元件可以沿第二方向D2排布在不同列，第一子像素15和第二子像素16的发光元件可以设置在同一行，两个第三子像素17a和17b的发光元件可以设置在同一行。第一子像素15的发光元件和第三子像素17a的发光元件所在的行可以沿第一方向D1间隔设置。本示例中，第一子像素15可以为红色子像素(R)，第二子像素16可以为蓝色子像素(B)，第三子像素17a和17b可以为绿色子像素(G)，比如，第三子像素17a可以为第一绿色子像素(G1)，第三子像素17b可以为第二绿色子像素(G2)。
在一些示例中，如图4所示，沿第二方向D2排布的多个像素单元可以为一行像素单元，沿第一方向D1排布的多个像素单元可以为一列像素单元。多个像素单元可以包括多个第一像素单元和多个第二像素单元，第一像素单元和第二像素单元内的四个子像素的排布顺序可以不同。例如，第e行像素单元可以包括：沿第二方向D2依次排布的多个第一像素单元；第一像素单元的第一子像素15、第三子像素17a、第二子像素16和第三子像素17b沿第二方向D2依次排布。第e+1行像素单元可以包括：沿第二方向D2依次排布的多个第二像素单元，第二像素单元的第二子像素16、第三子像素17b、第一子像素15和第三子像素17a可以沿第二方向D2依次排布。一列像素单元可以包括：沿第一方向D1交替设置的第一像素单元和第二像素单元。其中，e可以为大于0的整数。比如，显示区域内奇数行像素单元的子像素可以采用RG1BG2的排布方式，偶数行像素单元的子像素可以采用BG2RG1的排布方式；或者，显示区域内奇数行像素单元的子像素可以采用BG2RG1的排布方式，偶数行像素单元的子像素可以采用RG1BG2的排布方式。
在一些示例中，沿第一方向D1排布的多个子像素可以为一列子像素。第j列子像素可以包括：沿第一方向D1交替设置的第一子像素15和第二子像素16；第j+1列子像素可以包括：沿第一方向D1交替设置的第三子像素17a和17b。j可以为大于1的整数。每列子像素的像素电路可以与同一条数据线连接。例如，第j列子像素可以与数据线DLj连接，第j+1列子像素可以与数据线DLj+1连接。
图5为本公开至少一实施例的第一边框区域的局部走线示意图。图5中主要示意了第一边框区域的数据引出线，省略示意了第一边框区域的其余走线。
在一些示例中，如图5所示，第一子区域B11可以设置有多条第一数据引出线261，多条第一数据引出线261可以配置为以扇出走线方式连接显示区域AA的多条第二数据线DLb和多条数据连接线25。多条第一数据引出线261与多条第二数据线DLb和多条数据连接线25可以一一对应电连接。例如，多条第一数据引出线261可以交替排布在第一栅金属层和第二栅金属层。
在一些示例中，弯折区域B12可以设置有多条数据弯折连接线264。多条数据弯折连接线264可以与多条第一数据引出线261一一对应电连接。例如，多条数据弯折连接线264可以位于第二源漏金属层。然而，本实施例对此并不限定。在另一些示例中，弯折区域的多条数据弯折连接线可以位于第一源漏金属层。
在一些示例中，第二扇出区域B131可以设置有多条第二数据引出线262。多条第二 数据引出线262与多条数据弯折连接线264可以一一对应电连接。例如，多条第二数据引出线262可以交替排布在第一栅金属层和第二栅金属层。
在一些示例中，第三扇出区域B133可以设置有多条第三数据引出线263。多条第三数据引出线263可以与多条第二数据引出线262连接，例如可以一一对应电连接。例如，多条第三数据引出线263可以交替排布在第一栅金属层和第二栅金属层。
在本示例中，走线引出区域可以包括：第一子区域B11、弯折区域B12、第二扇出区域B131、电路设置区域B132和第三扇出区域B133。位于走线引出区域的一条数据引出线可以包括：依次连接的第一数据引出线261、数据弯折连接线264、第二数据引出线262和第三数据引出线263。
在一些示例中，电路设置区域B132可以设置有多个测试电路，多条第三数据引出线263可以与多个测试电路电连接。在显示基板的测试阶段，可以利用多个测试电路通过多条数据引出线(例如每条数据引出线包括依次连接的第三数据引出线263、第二数据引出线262、数据弯折连接线264和第一数据引出线261)向显示区域AA的多条第二数据线DLb提供测试数据信号，还可以通过多条数据引出线和显示区域AA的多条数据连接线25给多条第一数据线DLa提供测试数据信号。
在一些示例中，第一信号接入区域B134可以设置有多个第一接触垫，多个第一接触垫可以包括多个数据接触垫27。多个数据接触垫27可以配置为提供数据信号。多个数据接触垫27可以沿第二方向D2排布为一行，多行(例如两行或三行)数据接触垫27可以沿第一方向D1排布。多个数据接触垫27可以与多条第三数据引出线263连接，例如可以一一对应电连接。在显示基板的正常显示阶段，多个数据接触垫27可以通过多条数据引出线(例如每条数据引出线包括依次连接的第三数据引出线263、第二数据引出线262、数据弯折连接线264和第一数据引出线261)向显示区域AA的多条第二数据线DLb提供数据信号，还可以通过多条数据引出线和显示区域AA的多条数据连接线25给多条第一数据线DLa提供数据信号。
在一些示例中，如图5所示，第一子区域B11可以设置多组第二转接单元，第三扇出区域B133可以设置多组第一转接单元。多组第二转接单元可以沿第二方向D2依次排布，并位于多条第一数据引出线261靠近显示区域AA的一侧。多条第一数据引出线261可以通过多组第二转接单元与显示区域AA的多条第二数据线DLb和多条数据连接线25连接。多组第一转接单元可以沿第二方向D2依次排布，并位于多条第三数据引出线263靠近第一信号接入区域B134的一侧。多条第三数据引出线263可以通过多组第一转接单元与第一信号接入区域B134内的多个数据接触垫27连接。
在一些示例中，如图5所示，多组第一转接单元可以包括：多组第一侧第一转接单元300a和多组第二侧第一转接单元300b。多组第一侧第一转接单元300a和多组第二侧第一转接单元300b可以位于第一边框区域B1的平行于第一方向D1的中线的两侧。例如，多组第一侧第一转接单元300a可以与显示区域AA的左半区域的数据线连接，多组第二侧第一转接单元300b可以与显示区域的右半区域的数据线连接。
在一些示例中，第一信号接入区域B134的多个数据接触垫27可以包括：第一组数据接触垫和第二组数据接触垫。第一组数据接触垫和第二组数据接触垫可以沿第二方向D2排布。第一组数据接触垫可以通过多组第一侧第一转接单元300a与多条第三数据引出线263连接，第二组数据接触垫可以通过多组第二侧第一转接单元300b与多条第三数据引出线263连接。
在一些示例中，如图5所示，多组第二转接单元可以包括：多组第一侧第二转接单元 32a和多组第二侧第二转接单元32b。多组第一侧第二转接单元32a和多组第二侧第二转接单元32b可以位于第一边框区域B1的平行于第一方向D1的中线的两侧。例如，多组第一侧第二转接单元32a可以与显示区域AA的左半区域的第二数据线和数据连接线连接，多组第二侧第二转接单元32b可以与显示区域的右半区域的第二数据线和数据连接线连接。在一些示例中，多组第一侧第二转接单元32a可以通过多条数据引出线与多组第一侧第一转接单元300a连接，多组第二侧第二转接单元32b可以通过多条数据引出线与多组第二侧第一转接单元300b连接。例如，第一侧第二转接单元的组数与第一侧第一转接单元的组数可以相同，第二侧第二转接单元的组数与第二侧第一转接单元的组数可以相同。
图6为本公开至少一实施例的多组第一侧第一转接单元的示意图。图6中以两组第一侧第一转接单元为例进行示意。图7A为图6中的第一栅金属层和第二栅金属层的示意图。图7B为图6中的第一源漏金属层的示意图。图7C为图6中的第二源漏金属层的示意图。图8为图6中沿Q-Q’方向的局部剖面示意图。本示例中，每组第一转接单元所包括的第一转接线的数目m可以为8。
在一些示例中，如图6至图8所示，一组第一侧第一转接单元300a可以包括：八个第一连接端311、八个第二连接端312、以及八条第一转接线。在一组第一侧第一转接单元300a内，八个第一连接端311可以沿第二方向D2依次排布，例如，沿第二方向D2依次排布的八个第一连接端311的第一排布序号可以对应为1至8。八个第一连接端311可以与八条连续排布的第三数据引出线(例如包括第三数据引出线263-1、263-2、263-3、263-4、263-5、263-6、263-7和263-8)一一对应连接。其中，第三数据引出线263-1、263-3、263-5和263-7可以位于第二栅金属层，第三数据引出线263-2、263-4、263-6和263-8可以位于第一栅金属层。例如，如图8中，位于第一栅金属层的第三数据引出线可以包括第三数据引出线263a。
在一些示例中，单个第一连接端311可以包括：位于不同导电层的第一连接电极311-1和第二连接电极311-2。第一连接电极311-1和第二连接电极311-2在衬底的正投影可以大致为沿第一方向D1延伸的条状。第一连接电极311-1沿第一方向D1的长度可以大于第二连接电极311-2沿第一方向D1的长度。例如，第一连接电极311-1可以位于第一源漏金属层，第二连接电极311-2可以位于第二源漏金属层。以图3B所示的显示基板的膜层结构为例，第一连接电极311-1可以通过第三绝缘层103和第二绝缘层102开设的多个过孔与位于第一栅金属层的第三数据引出线连接，或者，可以通过第三绝缘层103开设的多个过孔与位于第二栅金属层的第三数据引出线连接。第二连接电极311-2可以通过第七绝缘层107和第六绝缘层106开设的多个过孔与第一连接电极311-1连接。第二连接电极311-2在衬底的正投影与第三数据引出线在衬底的正投影可以没有交叠，或者，可以部分交叠。本实施例对此并不限定。
在一些示例中，在一组第一侧第一转接单元300a内，八个第二连接端312可以在第一方向D1上位于八个第一连接端311靠近第一信号接入区域B134的一侧。八个第二连接端312可以沿第二方向D2依次排布，例如，沿第二方向D2依次排布的八个第二连接端312的第二排布序号可以对应为1至8。八个第二连接端312和八个第一连接端311可以在第一方向D1上对齐排布。八个第二连接端312可以与八条连续排布的接触垫连接线265一一对应连接。其中，多条接触垫连接线265可以位于第一栅金属层。多条接触垫连接线265可以与第一信号接入区域B134内连续排布的多个数据接触垫27一一对应电连接。
在一些示例中，单个第二连接端312可以包括：位于不同导电层的第三连接电极312-1和第四连接电极312-2。第三连接电极312-1和第四连接电极312-2在衬底的正投影可以 大致为沿第一方向D1延伸的条状。第三连接电极312-1沿第一方向D1的长度可以大于第四连接电极312-2沿第一方向D1的长度。例如，第三连接电极312-1可以位于第一源漏金属层，第四连接电极312-2可以位于第二源漏金属层。以图3B所示的显示基板的膜层结构为例，第三连接电极312-1可以通过第三绝缘层103和第二绝缘层102开设的多个过孔与位于第一栅金属层的接触垫连接线265连接。第四连接电极312-2可以通过第七绝缘层107和第六绝缘层106开设的多个过孔与第三连接电极312-1连接。第四连接电极312-2在衬底的正投影与接触垫连接线265在衬底的正投影可以没有交叠，或者，可以部分交叠。本实施例对此并不限定。
在一些示例中，在一组第一侧第一转接单元300a内，八条第一转接线可以位于八个第一连接端311和八个第二连接端312之间。每条第一转接线可以连接在一个第一连接端311和一个第二连接端312之间。八条第一转接线可以包括：四条第一顺序转接线314、两条第一插序转接线313a和两条第二插序转接线313b。在本示例中，八条第一转接线可以包括两个第一换序单元，每个第一换序单元可以包括：在衬底的正投影存在交叠的至少一条第一插序转接线(例如包括一条第一插序转接线313a)和至少一条第二插序转接线(例如包括一条第二插序转接线313b)。在第二方向D2上，一个第一换序单元、两条第一顺序转接线314、一个第一换序单元和两条第一顺序转接线314可以依次排布。
在一些示例中，第一顺序转接线314在衬底的正投影可以大致为沿第一方向D1延伸的条状。第一插序转接线313a和第二插序转接线313b在衬底的正投影可以大致为沿第一方向D1延伸的折线状。一个第一换序单元在衬底的正投影可以大致为X字型。本实施例对此并不限定。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端；第一条第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端；第二条第一插序转接线313a可以连接第五个第一连接端和第六个第二连接端；第二条第二插序转接线313b可以连接第六个第一连接端和第五个第二连接端。第一条第一顺序转接线314可以连接第三个第一连接端和第三个第二连接端；第二条第一顺序转接线314可以连接第四个第一连接端和第四个第二连接端；第三条第一顺序转接线314可以连接第七个第一连接端和第七个第二连接端；第四条第一顺序转接线314可以连接第八个第一连接端和第八个第二连接端。
在一些示例中，多条第一顺序转接线314可以为同层结构，例如可以位于第二源漏金属层。比如，第一顺序转接线314与所连接的第一连接端311的第二连接电极311-2以及所连接的第二连接端312的第四连接电极312-2可以为相互连接的一体结构。
在一些示例中，第一插序转接线313a和第二插序转接线313b可以位于不同导电层。例如，第一插序转接线313a可以位于第一源漏金属层，第二插序转接线313b可以位于第二源漏金属层。第一插序转接线313a与所连接的第一连接端311的第一连接电极311-1和所连接的第二连接端312的第三连接电极312-1可以为相互连接的一体结构。第二插序转接线313b与所连接的第一连接端311的第二连接电极311-2和所连接的第二连接端312的第四连接电极312-2可以为相互连接的一体结构。
图9A和图9B为图6所示的一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。在一些示例中，如图9A和图9B所示，以显示区域的子像素排布方式如图4所示，一组第一侧第一转接单元的第二连接端传输的八路数据信号为例进行说明，每路数据信号可以被配置为提供给显示区域的一条数据线。本示例中，未经过插序调整的顺序对应显示区域的多条数据线的排布顺序；排布在同一列的第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)与同一条数据线连接，排布在同一列的第 三子像素(例如包括第一绿色子像素G1和第二绿色子像素G2)与同一条数据线连接。
在一些示例中，如图9A和图9B所示，以未经过插序调整的八条数据线(例如，第n-3条至第n+4条数据线)为例，八条数据线可以沿第二方向排布，按照隔一条数据线插入一条数据线的方式(即1插1方式)，可以将第n-3条至第n-1条数据线所连接的数据连接线插入到第n+1条数据线至第n+4条数据线之间。例如，第n-1条数据线所连接的数据连接线可以插入第n+1条数据线和第n+2条数据线之间，第n-2条数据线所连接的数据连接线可以插入第n+2条和第n+3条数据线之间，第n-3条数据线所连接的数据连接线可以插入第n+3条和第n+4条数据线之间。按照1插1方式调整得到的数据信号的最小循环数为8。
在一些示例中，如图9A所示，以显示区域内奇数行像素单元的子像素排布顺序为RG1BG2为例，按照1插1方式得到的八条数据线(插序调整后的第n条至第n+4条)对应的子像素循环为：G2RBG1 G1BRG2。如图9B所示，以显示区域内偶数行像素单元的子像素排布顺序为BG2RG1为例，按照1插1方式得到的八条数据线(插序调整后的第n条至第n+4条)对应的子像素循环为：G1BRG2 G2RBG1。
在一些示例中，显示区域内的第一数据线通过数据连接线与第一边框区域的数据引出线连接，因此，显示区域内多条数据线所需的数据信号的顺序与多条数据线的排布顺序不同。根据图9A和图9B所示的插序原理，多个数据接触垫可以提供满足多条第二数据线和多条数据连接线的顺序的数据信号。由于显示区域内奇数行和偶数行像素单元的子像素排布顺序不同，多个数据接触垫可以分时段给奇数行和偶数行像素单元的子像素提供对应的数据信号。例如，多个数据接触垫可以在第一时段沿第二方向D2按照子像素循环顺序为G2RBG1 G1BRG2提供对应的数据信号，以满足显示区域内奇数行像素单元所需的数据信号；多个数据接触垫可以在第二时段沿第二方向D2按照子像素循环顺序为G1BRG2 G2RBG1提供对应的数据信号，以满足显示区域内偶数行像素单元所需的数据信号。在一些示例中，多个数据接触垫可以按照第一时段和第二时段的循环顺序来依次给显示区域内的多行像素单元提供数据信号。比如，多个数据接触垫在第一个第一时段可以给显示区域的一行像素单元(例如第一行像素单元)的子像素提供数据信号，在第一个第二时段可以给显示区域的一行像素单元(例如第二行像素单元)的子像素提供数据信号；多个数据接触垫在第二个第一时段可以给显示区域的一行像素单元(例如第三行像素单元)的子像素提供数据信号，在第二个第二时段可以给显示区域的一行像素单元(例如第四行像素单元)的子像素提供数据信号，依此类推，可以分别给显示区域的多行像素单元的子像素提供所需的数据信号。
在另一些示例中，当显示区域内偶数行像素单元的子像素排布顺序为RG1BG2，且奇数行像素单元的子像素排布顺序为BG2RG1，则多个数据接触垫可以在第一时段沿第二方向D2按照子像素循环顺序为G2RBG1 G1BRG2提供对应的数据信号，以满足显示区域内偶数行像素单元所需的数据信号；多个数据接触垫可以在第二时段沿第二方向D2按照子像素循环顺序为G1BRG2 G2RBG1提供对应的数据信号，以满足显示区域内奇数行像素单元所需的数据信号。
在一些示例中，在第一时段，如图6所示，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：G2RBG1 G1BRG2，多个数据接触垫传输的数据信号被提供至多组第一侧第一转接单元300a的第二连接端312，例如，通过多组第一侧第一转接单元300a之后，由第一侧第一转接单元300a的第一连接端311输出的数据信号的最小循环数仍为8，且第一连接端311输出的数据信号对应的子像素循环可以为：RG2BG1 BG1RG2。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素 循环可以为：G1BRG2 G2RBG1，通过多组第一侧第一转接单元300a之后，由多组第一侧第一转接单元300a的第一连接端311输出的数据信号对应的子像素循环可以为：BG1RG2 RG2BG1。
在一些示例中，如图6所示，通过一组第一侧第一转接单元300a的转接之后，第三子像素(例如包括第一绿色子像素G1和第二绿色子像素G2)对应的数据信号可以由位于第一栅金属层的第三数据引出线传输，第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)对应的数据信号可以由位于第二栅金属层的第三数据引出线传输，可以保证信号传输走线的均一性排布，避免将传输第三子像素对应的数据信号的数据引出线排布在不同导电层而引起负载差异，影响显示效果。
图10为本公开至少一实施例的多组第二侧第一转接单元的示意图。图10中以两组第二侧第一转接单元为例进行示意。在一些示例中，如图10所示，一组第二侧第一转接单元300b可以包括：八个第一连接端311、八个第二连接端312、以及八条第一转接线。
在一些示例中，在一组第二侧第一转接单元300b内，八个第一连接端311可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的八个第一连接端311的第一排布序号可以对应为1至8。八个第一连接端311可以与八条连续排布的第三数据引出线一一对应连接。其中，第一个第一连接端、第三个第一连接端、第五个第一连接端和第七个第一连接端所连接的第三数据引出线可以位于第一栅金属层，第二个第一连接端、第四个第一连接端、第六个第一连接端和第八个第一连接端所连接的第三数据引出线可以位于第二栅金属层。
在一些示例中，在一组第二侧第一转接单元300b内，八个第二连接端312可以在第一方向D1上位于八个第一连接端311靠近第一信号接入区域的一侧。八个第二连接端312可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的八个第二连接端312的第二排布序号可以对应为1至8。八个第二连接端312和八个第一连接端311可以在第一方向D1上对齐排布。八个第二连接端312可以与八条连续排布的接触垫连接线265一一对应连接。其中，多条接触垫连接线265可以位于第一栅金属层。多条接触垫连接线265可以与第一信号接入区域B134内连续排布的多个数据接触垫27一一对应电连接。
在一些示例中，在一组第二侧第一转接单元300b内，八条第一转接线可以包括四条第一顺序转接线314、两条第一插序转接线313a和两条第二插序转接线313b。第一插序转接线313a所连接的第一连接端311的第一排布序号小于所连接的第二连接端312的第二排布序号；第二插序转接线313b所连接的第一连接端311的第一排布序号大于所连接的第二连接端312的第二排布序号。例如，第一插序转接线313a可以位于第二源漏金属层，第二插序转接线313b可以位于第一源漏金属层。
在一些示例中，八条第一转接线可以包括两个第一换序单元，每个第一换序单元可以包括：在衬底的正投影存在交叠的第一插序转接线(例如包括一条第一插序转接线313a)和第二插序转接线(例如包括一条第二插序转接线313b)。在第二方向D2的反方向上，一个第一换序单元、两条第一顺序转接线314、一个第一换序单元和两条第一顺序转接线314可以依次排布。
在一些示例中，多组第一侧第一转接单元300a的第二连接端所传输的数据信号的插序方式与多组第二侧第一转接单元300b的第二连接端所传输的数据信号的插序方式可以镜像设置，以匹配显示区域的数据线和数据连接线的设置方式。例如，显示区域的多条数据线和多条数据连接线可以关于显示区域平行于第一方向的中心线对称排布。
图11为图10所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。本示例中，未经过插序调整的顺序对应显示区域的多条数据线的排布顺序；排布在同一列的第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)与同一条数据线连接，排布在同一列的第三子像素(例如包括第一绿色子像素G1和第二绿色子像素G2)与同一条数据线连接。在一些示例中，如图11所示，未经过插序调整的八条数据线(例如，第n-3条至第n+4条数据线)沿第二方向D2的反方向排布，可以按照隔一条数据线插入一条数据线的方式进行顺序调整。按照1插1方式调整得到的数据信号的最小循环数为8。
在一些示例中，如图11所示，以显示区域内子像素排布顺序(例如奇数行像素单元的子像素排布顺序)为RG1BG2为例，沿第二方向D2的反方向按照1插1方式得到的八条数据线(插序调整后的第n条至第n+4调)对应的子像素循环为：RG2G1B BG1G2R。如图10所示，以多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环可以为：RG2G1B BG1G2R，多个数据接触垫传输的数据信号被提供至多组第二侧第一转接单元300b的第二连接端312，例如，通过多组第二侧第一转接单元300b之后，由多组第二侧第一转接单元300b的第一连接端311输出的数据信号的最小循环数仍为8，且第一连接端311输出的数据信号对应的子像素循环可以为：G2RG1B G1BG2R。
在一些示例中，以显示区域内子像素排布顺序(例如偶数行像素单元的子像素排布顺序)为BG2RG1为例，沿第二方向D2的反方向按照1插1方式得到的八条数据线(插序调整后的第n条至第n+4条)对应的子像素循环为：BG1G2R RG2G1B；多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环为：BG1G2R RG2G1B，则通过第二组第一转接单元300b之后，由第一连接端输出的数据信号对应的子像素循环可以为：G1BG2R G2RG1B。关于插序原理的其余说明可以参照前述实施例的说明，故于此不再赘述。
在一些示例中，如图10所示，通过一组第二侧第一转接单元300b的转接之后，第三子像素(例如包括第一绿色子像素G1和第二绿色子像素G2)对应的数据信号可以由位于第一栅金属层的第三数据引出线传输，第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)对应的数据信号可以由位于第二栅金属层的第三数据引出线传输，可以保证信号传输走线的均一性排布，避免将传输第三子像素对应的数据信号的数据引出线排布在不同导电层而引起负载差异，影响显示效果。
图12为本公开至少一实施例的一组第一侧第二转接单元的示意图。在一些示例中，每组第二转接单元可以包括m条第二转接线，本示例的m可以为8。如图12所示，一组第一侧第二转接单元32a可以包括八条第二转接线(例如包括：四条第二顺序转接线324、两条第三插序转接线323a和两条第四插序转接线323b)。本示例中，八条第二转接线可以包括两个第二换序单元，每个第二换序单元可以包括：在衬底的正投影存在交叠的至少一条第三插序转接线(例如包括一条第三插序转接线323a)和至少一条第四插序转接线(例如包括一条第四插序转接线323b)。在第二方向D2上，一个第二换序单元、两条第二顺序转接线324、一个第二换序单元和两条第二顺序转接线324可以依次排布。
在一些示例中，每条第二转接线的一端可以连接一条第二数据线DLb或一条数据连接线25，另一端可以连接一条第一数据引出线261。以给显示区域内子像素排布顺序为RG1BG2的至少一行像素单元提供数据信号为例，多条第一数据引出线261传输的数据信号沿第二方向D2对应的子像素循环可以为：RG2BG1 BG1RG2，经过第一侧第二转接单元32a转接输出后对应的子像素循环可以为G2RBG1 G1BRG2，使得多个数据接触垫传输的数据信号沿第二方向的顺序与显示区域内对应像素单元行所连接的第二数据线和数 据连接线沿第二方向D2所需的数据信号的顺序是匹配的。以给显示区域内子像素排布顺序为BG2RG1的至少一行像素单元提供数据信号为例，多条第一数据线261传输的数据信号沿第二方向D2对应的子像素循环可以为：BG1RG2 RG2BG1，经过第一侧第二转接单元32a转接输出后对应的子像素循环可以为G1BRG2 G2RBG1。本实施例对于第二转接单元的第二转接线的膜层并不限定，例如膜层设置类似第一转接线，故于此不再赘述。
在一些示例中，一组第二侧第二转接单元32b可以将一组第二侧第一转接单元300b的第一连接端输出的数据信号的顺序调整为与第二连接端输入的数据信号的顺序相同。本示例的第二侧第二转接单元32b的结构可以参照第一侧第二转接单元32a的结构，故于此不再赘述。
本示例通过设置多组第一转接单元以及对应的多组第二转接单元，可以使得多个数据接触垫传输的数据信号的顺序与显示区域内第二数据线和数据连接线所需的数据信号的顺序是匹配的，从而可以避免在第二扇出区的跳线设计，进而保证显示产品的可靠性。本示例的设置方式可以保证全高清(FHD，Full High Definition)分辨率且采用RGBG子像素排布的显示产品的显示效果。
在一些示例性实施方式中，电路设置区域可以设置沿第二方向依次排布的多组测试电路，多组测试电路在第一方向上可以位于多组第一转接单元远离第一信号接入区域的一侧。一组测试电路可以与一组第一转接单元所连接的多条(例如八条)数据引出线连接。每组测试电路可以包括：至少一个第一测试电路和至少一个第二测试电路，每组测试电路内的第一测试电路和第二测试电路的数目之和的两倍可以与每组第一转接单元所连接的数据引出线的数目相同。例如，每个第一测试电路可以与两条数据引出线连接，每个第二测试电路可以与两条数据引出线连接。
图13为本公开至少一实施例的第一测试电路和第二测试电路的等效电路图。在一些示例中，如图13所示，第一测试电路401可以包括：第一测试晶体管CT1、第二测试晶体管CT2和第三测试晶体管CT3。第一测试晶体管CT1的栅极可以与第一测试控制线SW1连接，第一测试晶体管CT1的第一极可以与第一测试数据线DR连接；第二测试晶体管CT2的栅极可以与第二测试控制线SW2连接，第二测试晶体管CT2的第一极可以与第二测试数据线DB连接；第三测试晶体管CT3的栅极可以与第三测试控制线SW3连接，第三测试晶体管CT3的第一极可以与第三测试数据线DG连接。第一测试晶体管CT1的第二极和第二测试晶体管CT2的第二极可以与同一条数据引出线(例如数据引出线DA-n)连接。第三测试晶体管CT3的第二极可以与另一条数据引出线(例如数据引出线DA-n+1)连接。
在一些示例中，第二测试电路402可以包括：第四测试晶体管CT4、第五测试晶体管CT5和第六测试晶体管CT6。第四测试晶体管CT4的栅极可以与第二测试控制线SW2连接，第四测试晶体管CT4的第一极可以与第一测试数据线DR连接。第五测试晶体管CT5的栅极可以与第一测试控制线SW1连接，第五测试晶体管CT5的第一极可以与第二测试数据线DB连接。第六测试晶体管CT6的栅极可以与第三测试控制线SW3连接，第六测试晶体管CT6的第一极可以与第三测试数据线DG连接。第四测试晶体管CT4的第二极和第五测试晶体管CT5的第二极可以与同一条数据引出线(例如数据引出线DA-n+2)连接。第六测试晶体管CT6的第二极可以与另一条数据引出线(例如数据引出线DA-n+3)连接。
在一些示例中，数据引出线DA-n所连接的子像素可以包括红色子像素(R)和蓝色子像素(B)，数据引出线DA-n+2所连接的子像素可以包括红色子像素(R)和蓝色子像素(B)，数据引出线DA-n+1和DA-n+3所连接的子像素可以包括第一绿色子像素(G1) 和第二绿色子像素(G2)。
在一些示例中，第一测试晶体管CT1的第二极、第三测试晶体管CT3的第二极、第四测试晶体管CT4的第二极以及第六测试晶体管CT6的第二极可以通过不同的数据引出线与不同的数据线连接。
在一些示例中，第一测试控制线SW1可以配置为控制第一测试电路401中的第一测试晶体管CT1和第二测试电路402中的第五测试晶体管CT5导通，第二测试控制线SW2可以配置控制第一测试电路401中的第二测试晶体管CT2和第二测试电路402中的第四测试晶体管CT4导通，使得第一测试数据线DR传输的第一测试数据信号和第二测试数据线DB传输的第二测试数据信号可以写入不同的数据线。
在一些示例中，在进行显示测试(例如彩色显示测试)时，可以通过控制装置向第一测试控制线SW1(或第二测试控制线SW2)以及第三测试控制线SW3提供导通信号，向多条测试数据线分别提供所需的测试数据信号，使显示区域中多条数据线获得测试数据信号，通过显示画面的颜色确定是否有发生不良的子像素，以及定位发生不良的子像素。
在一些示例性实施方式中，一组第一转接单元可以与一组测试电路对应。例如，多组测试电路可以包括：多个第一组测试电路和多个第二组测试电路；一组第一侧第一转接单元所连接的多条数据引出线可以与一个第一组测试电路连接，一组第二侧第一转接单元所连接的多条数据引出线可以与一个第二组测试电路连接。换言之，一组第一侧第一转接单元与一个第一组测试电路对应，一组第二侧第一转接单元与一个第二组测试电路对应。
图14A为本公开至少一实施例的第一组测试电路的平面示意图。图14B为图14A中第一源漏金属层的示意图。图14C为图14A中第一半导体层、第一栅金属层和第二栅金属层的示意图。
在一些示例中，如图14A至图14C所示，第一组测试电路可以包括：两个第一测试电路401和两个第二测试电路402。其中，一个第一测试电路401、两个第二测试电路402以及一个第一测试电路401可以沿着第二方向D2依次排布。每个第一测试电路401的第一测试晶体管CT1、第二测试晶体管CT2和第三测试晶体管CT3可以沿第一方向D1排布，每个第二测试电路402的第四测试晶体管CT4、第五测试晶体管CT5和第六测试晶体管CT6可以沿第一方向D1排布。
在一些示例中，第一测试晶体管CT1和第四测试晶体管CT4可以沿第二方向D2对齐排布，第二测试晶体管CT2和第五测试晶体管CT5可以沿第二方向D2对齐排布，第三测试晶体管CT3和第六测试晶体管CT6可以沿第二方向D2对齐排布。
在一些示例中，第一个第一测试电路401可以位于第三数据引出线263-1和263-2之间；第一个第二测试电路402可以位于第三数据引出线263-3和263-4之间；第二个第二测试电路402可以位于第三数据引出线263-5和263-6之间，第二个第一测试电路401可以位于第三数据引出线263-7和263-8之间。
在一些示例中，第一个第一测试电路401的第一测试晶体管CT1和第二测试晶体管CT2可以与第三数据引出线263-1连接，第三测试晶体管CT3可以与第三数据引出线263-2连接。第一个第二测试电路402的第四测试晶体管CT4和第五测试晶体管CT5可以与第三数据引出线263-3连接，第六测试晶体管CT6可以与第三数据引出线263-4连接。第二个第二测试电路402的第四测试晶体管CT4和第五测试晶体管CT5可以与第三数据引出线263-5连接，第六测试晶体管CT6可以与第三数据引出线263-6连接。第二个第一测试电路401的第一测试晶体管CT1和第二测试晶体管CT2可以与第三数据引出线263-7连接，第三测试晶体管CT3可以与第三数据引出线263-8连接。
在一些示例中，显示基板的第一边框区域的第一半导体层可以包括：第一测试电路401的第一测试晶体管CT1的有源层411和412、第二测试晶体管CT2的有源层421和422、第三测试晶体管CT3的有源层431、第二测试电路402的第四测试晶体管CT4的有源层441和442、第五测试晶体管CT5的有源层451和452、第六测试晶体管CT6的有源层461。第一测试晶体管CT1的有源层411和412、第二测试晶体管CT2的有源层421和422、第三测试晶体管CT3的有源层431可以沿第一方向D1排布；第四测试晶体管CT4的有源层441和442、第五测试晶体管CT5的有源层451和452、第六测试晶体管CT6的有源层461可以沿第一方向D1排布。
在一些示例中，显示基板的第一边框区域的第一栅金属层可以包括：第一测试晶体管CT1的栅极413a和413b、第二测试晶体管CT2的栅极423a和423b、第三测试晶体管CT3的栅极433、第四测试晶体管CT4的栅极443a和443b、第五测试晶体管CT5的栅极453a和453b、第六测试晶体管CT6的栅极463。第一测试晶体管CT1的栅极413a和413b可以为相互连接的一体结构，第二测试晶体管CT2的栅极423a和423b可以为相互连接的一体结构，第四测试晶体管CT4的栅极443a和443b可以为相互连接的一体结构，第五测试晶体管CT5的栅极453a和453b可以为相互连接的一体结构。
在一些示例中，显示基板的第一边框区域的第一栅金属层还可以包括：第三数据引出线263-2、263-4、263-6和263-8。显示基板的第二栅金属层可以包括：第三数据引出线263-1、263-3、263-5和263-7。
在一些示例中，显示基板的第一边框区域的第一源漏金属层可以包括：第一测试控制线SW1、第二测试控制线SW2、第三测试控制线SW3、第一测试数据线DR1和DR2、第二测试数据线DB1和DB2、第三测试数据线DG、第一测试晶体管CT1的第二极414、第二测试晶体管CT2的第二极424、第三测试晶体管CT3的第二极434和第一极435、第四测试晶体管CT4的第二极444、第五测试晶体管CT5的第二极454、第六测试晶体管CT6的第二极464和第一极465。
在一些示例中，第一测试控制线SW1、第二测试控制线SW2、第三测试控制线SW3、第一测试数据线DR1和DR2、第二测试数据线DB1和DB2、第三测试数据线DG可以至少沿第二方向D2延伸。第一测试晶体管CT1和第四测试晶体管CT4在第一方向D1上可以位于第一测试数据线DR1和DR2之间，第二测试晶体管CT2和第五测试晶体管CT5在第一方向D1上可以位于第二测试数据线DB1和DB2之间。第三测试晶体管CT3和第六测试晶体管CT6可以位于第三测试数据线DG在第一方向D1的一侧。第一测试控制线SW1和第二测试控制线SW2可以位于第一测试数据线DR2和第二测试数据线DB1之间，第三测试控制线SW3可以位于第二测试数据线DB2和第三测试数据线DG之间。
在一些示例中，第一个第一测试电路401的第一测试晶体管CT1的第二极414可以与第三数据引出线263-1、第一测试晶体管CT1的有源层411和412连接；第二测试晶体管CT2的第二极424可以与第三数据引出线263-1、第二测试晶体管CT2的有源层421和422连接；第三测试晶体管CT3的第二极434可以与第三数据引出线263-2、第三测试晶体管CT3的有源层431连接；第三测试晶体管CT3的第一极435可以与第三测试晶体管CT3的有源层431连接。
在一些示例中，第一个第二测试电路402的第四测试晶体管CT4的第二极444可以与第三数据引出线263-3、第四测试晶体管CT4的有源层441和442连接；第五测试晶体管CT5的第二极454可以与第三数据引出线263-3、第五测试晶体管CT5的有源层451和452连接；第六测试晶体管CT6的第二极464可以与第三数据引出线263-4、第六测试晶体管CT6的有源层461连接；第六测试晶体管CT6的第一极465可以与第六测试晶体 管CT6的有源层461连接。
在一些示例中，第一测试数据线DR1可以与第一测试晶体管CT1的有源层411和第四测试晶体管CT4的有源层441连接，第一测试数据线DR2可以与第一测试晶体管CT1的有源层412和第四测试晶体管CT4的有源层442连接。第二测试数据线DB1可以与第二测试晶体管CT2的有源层421和第五测试晶体管CT5的有源层451连接，第二测试数据线DB2可以与第二测试晶体管CT2的有源层422和第五测试晶体管CT5的有源层452连接。第三测试数据线DG与第三测试晶体管CT3的第一极435和第六测试晶体管CT6的第一极465可以为相互连接的一体结构。
在一些示例中，在测试阶段，测试电路可以分时段给显示区域内的不同行像素单元的子像素提供测试数据信号。第一组测试电路可以在第一测试时段按照RGBG BGRG的循环顺序向多条第三数据引出线(例如包括第三数据引出线263-1至263-8)提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测奇数行(或偶数行)像素单元的显示情况。第一组测试电路可以在第二测试时段按照BGRG RGBG的循环顺序向多条第三数据引出线提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测偶数行(或奇数行)像素单元的显示情况。其中，第一绿色子像素G1和第二绿色子像素G2对应的测试数据信号可以相同。第一组测试电路提供的数据信号的顺序与一组第一侧第一转接单元的第一输出端输出的数据信号的顺序可以相同。在一些示例中，第一组测试电路可以在第一个第一测试时段给第一行像素单元的子像素提供测试数据信号，在第一个第二测试时段给第二行像素单元的子像素提供测试数据信号；在第二个第一测试时段给第三行像素单元的子像素提供测试数据信号，在第二个第二测试时段给第四行像素单元的子像素提供测试数据信号，依此类推，给多行像素单元分别提供对应的测试数据信号。
本示例中，第一测试电路的第一测试晶体管和第二测试电路的第四测试晶体管连接不同的测试控制线，且连接相同的测试数据线，第一测试电路的第二测试晶体管和第二测试电路的第五测试晶体管连接不同的测试控制线，且连接相同的测试数据线，可以在测试阶段按照多组第一侧第一转接单元的第一输出端对应的数据信号顺序提供测试数据信号，以满足数据线对测试数据信号的需求。
在一些示例中，每组第二侧第一转接单元对应的第二组测试电路的结构与第一组测试电路的结构类似，故于此不再赘述。
本实施例通过设置多组测试电路，来调整测试数据信号的传输顺序，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
图15为本公开至少一实施例的第三测试电路的等效电路图。在一些示例中，如图15所示，第三测试电路可以包括：第七测试晶体管CT7、第八测试晶体管CT8、第九测试晶体管CT9和第十测试晶体管CT10。
在一些示例中，第七测试晶体管CT7、第八测试晶体管CT8、第九测试晶体管CT9和第十测试晶体管CT10的栅极均与第四测试控制线SW4连接，第七测试晶体管CT7的第一极和第八测试晶体管CT8的第一极与第四测试数据线DD1连接，第九测试晶体管CT9的第一极和第十测试晶体管CT10的第一极与第五测试数据线DD2连接。第七测试晶体管CT7、第八测试晶体管CT8、第九测试晶体管CT9和第十测试晶体管CT10的第二极可以通过不同的数据引出线与不同的数据线连接。例如，第七测试晶体管CT7的第二极可以与数据引出线DA-n连接，第八测试晶体管CT8的第二极可以与数据引出线 DA-n+1连接，第九测试晶体管CT9的第二极可以与数据引出线DA-n+2连接，第十测试晶体管CT10的第二极可以与数据引出线DA-n+3连接。
在一些示例中，第三测试电路在电路设置区域可以位于第一测试电路和第二测试电路靠近第一信号接入区域的一侧，或者可以位于靠近弯折区域的一侧。本实施例对此并不限定。
在一些示例中，第三测试电路可以配置为在黑白显示测试过程中给数据线提供测试数据信号，以进行黑白显示测试。
图16为本公开至少一实施例的一组第一侧第一转接单元的另一示意图。图17为图16中的第一栅金属层和第二栅金属层的示意图。图18为图16所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。本示例中，m可以为12。本示例及以下示例中，以第一绿色子像素G1和第二绿色子像素G2所需的数据信号相同，且所需的测试数据信号相同为例进行说明。
在一些示例中，如图16和图17所示，一组第一侧第一转接单元300a可以包括：十二个第一连接端311、十二个第二连接端312、以及十二条第一转接线。十二条第一转接线可以包括：四条第一顺序转接线314、四条第一插序转接线313a和四条第二插序转接线313b。十二条第一转接线可以包括四个第一换序单元，每个第一换序单元可以包括：在衬底的正投影存在交叠的第一插序转接线(例如包括一条第一插序转接线313a)和第二插序转接线(例如包括一条第二插序转接线313b)。在第二方向D2上，两个第一换序单元、两条第一顺序转接线314、两个第一换序单元和两条第一顺序转接线314可以依次排布。
在一些示例中，十二个第一连接端311可以与十二条连续排布的第三数据引出线263-1至263-12一一对应连接。其中，第三数据引出线263-1、263-3、263-5、263-7、263-9和263-11可以位于第二栅金属层，第三数据引出线263-2、263-4、263-6、263-8、263-10和263-12可以位于第一栅金属层。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端；第二条第一插序转接线313a可以连接第三个第一连接端和第四个第二连接端；第三条第一插序转接线313a可以连接第七个第一连接端和第八个第二连接端；第四条第一插序转接线313a可以连接第九个第一连接端和第十个第二连接端。第一条第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端；第二条第二插序转接线313b可以连接第四个第一连接端和第三个第二连接端；第三条第二插序转接线313b可以连接第八个第一连接端和第七个第二连接端；第四条第二插序转接线313b可以连接第十个第一连接端和第九个第二连接端。
在一些示例中，第一条第一顺序转接线314可以连接第五个第一连接端和第五个第二连接端；第二条第一顺序转接线314可以连接第六个第一连接端和第六个第二连接端；第三条第一顺序转接线314可以连接第十一个第一连接端和第十一个第二连接端；第四条第一顺序转接线314可以连接第十二个第一连接端和第十二个第二连接端。
在一些示例中，如图18所示，以显示区域的子像素排布方式如图4所示，以显示区域奇数行像素单元的子像素排布顺序为RGBG为例，以未经过插序调整的十二条数据线(例如序号为n-3至n+8)为例，十二条数据线可以沿第二方向D2排布，按照隔两条数据线插入一条数据线的方式(即2插1方式)，可以将第n-3条至第n-1条数据线所连接的数据连接线插入第n+1条数据线至第n+8条数据线之间。例如，第n-1条数据线所连接 的数据连接线可以插入第n+2条数据线和第n+3条数据线之间，第n-2条数据线可以插入第n+4条和第n+5条数据线之间，第n-3条数据线可以插入第n+6条和第n+7条数据线之间。按照2插1方式得到的数据信号的最小循环数为12，按照2插1方式得到的十二条数据线对应的子像素循环为：GRGB BGGR GRBG。在一些示例中，以显示区域偶数行像素单元的子像素排布顺序为BGRG为例，按照2插1方式得到的十二条数据线对应的子像素循环可以为：GBGR RGGB GBRG。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图16所示，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GRGB BGGR GRBG，多个数据接触垫传输的数据信号被提供至多组第一侧第一转接单元300a的第二连接端312，例如，通过多组第一侧第一转接单元300a之后，由第一连接端311输出的数据信号的最小循环数仍为12，且在第二方向D2上，第一连接端311输出的数据信号对应的子像素循环可以为：RGBG BGRG RGBG。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GBGR RGGB GBRG，通过多组第一侧第一转接单元300a之后，由多组第一侧第一转接单元300a的第一连接端311输出的数据信号对应的子像素循环可以为：BGRG RGBG BGRG。
图19为本公开至少一实施例的一组第一侧第二转接单元的示意图。在一些示例中，每组第二转接单元可以包括m条第二转接线，本示例的m可以为12。如图19所示，一组第一侧第二转接单元32a可以包括十二条第二转接线(例如包括：四条第二顺序转接线324、两条第三插序转接线323a和两条第四插序转接线323b)。本示例中，十二条第二转接线可以包括四个第二换序单元，每个第二换序单元可以包括：在衬底的正投影存在交叠的至少一条第三插序转接线(例如包括一条第三插序转接线323a)和至少一条第四插序转接线(例如包括一条第四插序转接线323b)。在第二方向D2上，两个第二换序单元、两条第二顺序转接线324、两个第二换序单元和两条第二顺序转接线324可以依次排布。
在一些示例中，每条第二转接线的一端可以连接一条第二数据线DLb或一条数据连接线25，另一端可以连接一条第一数据引出线261。在第一时段，多条第一数据引出线261传输的数据信号沿第二方向D2对应的子像素循环可以为：RGBG BGRG RGBG，经过多组第一侧第二转接单元32a转接输出后对应的子像素循环可以为GRGB BGGR GRBG；在第二时段，多条第一数据引出线261传输的数据信号沿第二方向D2对应的子像素循环可以为：BGRG RGBG BGRG，经过多组第一侧第二转接单元32a转接输出后对应的子像素循环可以为：GBGR RGGB GBRG，使得多个数据接触垫传输的数据信号沿第二方向D2的顺序与显示区域内第二数据线和数据连接线沿第二方向D2所需的数据信号的顺序是匹配的。例如，第一时段可以配置为给显示区域内的奇数行像素单元提供数据信号，第二时段可以配置为给显示区域内的偶数行像素单元提供数据信号。本实施例对于第二转接单元的第二转接线的膜层并不限定，例如膜层设置类似第一转接线，故于此不再赘述。
在一些示例中，第一信号接入区域内，沿第二方向排布的第一个数据接触垫可以传输第384路数据信号，并通过第一转接单元的第二连接端、一条第一转接线和第一连接端提供给位于第一栅金属层的第三数据引出线，并由第三数据引出线通过第二数据引出线和数据弯折连接线传输给第一数据引出线，由第一数据引出线通过第二转接单元的第二转接线传输给与绿色子像素连接的一条数据线(例如沿第二方向排布序号为384的数据线)。本示例通过结合数据接触垫所传输数据信号的顺序调整以及多组第一转接单元和多组第二转接单元的设置，可以在显示区域设置数据连接线的方案中避免在第二扇出区的跳线设计， 进而保证显示产品的可靠性。
图20为本公开至少一实施例的第一组测试电路的平面示意图。在一些示例中，如图20所示，第一组测试电路与一组第一侧第一转接单元所连接的十二条第三数据引出线(例如第三数据引出线263-1至263-12)连接。第一组测试电路可以包括：三个第一测试电路401和三个第二测试电路402。其中，一个第一测试电路401、两个第二测试电路402、两个第一测试电路401和一个第二测试电路402可以沿第二方向D2依次排布。
在一些示例中，第一个第一测试电路401的第一测试晶体管CT1和第二测试晶体管CT2可以与第三数据引出线263-1连接，第三测试晶体管CT3可以与第三数据引出线263-2连接。第二个第一测试电路401的第一测试晶体管CT1和第二测试晶体管CT2可以与第三数据引出线263-7连接，第三测试晶体管CT3可以与第三数据引出线263-8连接。第三个第一测试电路401的第一测试晶体管CT1和第二测试晶体管CT2可以与第三数据引出线263-9连接，第三测试晶体管CT3可以与第三数据引出线263-10连接。
在一些示例中，第一个第二测试电路402的第四测试晶体管CT4和第五测试晶体管CT5可以与第三数据引出线263-3连接，第六测试晶体管CT6可以与第三数据引出线263-4连接。第二个第二测试电路402的第四测试晶体管CT4和第五测试晶体管CT5可以与第三数据引出线263-5连接，第六测试晶体管CT6可以与第三数据引出线263-6连接。第三个第二测试电路402的第四测试晶体管CT4和第五测试晶体管CT5可以与第三数据引出线263-11连接，第六测试晶体管CT6可以与第三数据引出线263-12连接。
在一些示例中，测试电路可以分时段给显示区域内的不同行像素单元的子像素提供测试数据信号。在测试阶段，第一组测试电路可以在第一测试时段按照RGBG BGRG RGBG的循环顺序向多条第三数据引出线(例如包括第三数据引出线263-1至263-12)提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测奇数行(或偶数行)像素单元的显示情况。第一组测试电路可以在第二测试时段按照BGRG RGBG BGRG的循环顺序向多条第三数据引出线提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测偶数行(或奇数行)像素单元的显示情况。关于测试电路的其他说明可以参照前述实施例的描述，故于此不再赘述。
图21为本公开至少一实施例的一组第二侧第一转接单元的示意图。在一些示例中，如图21所示，一组第二侧第一转接单元300b可以包括：十二个第一连接端311、十二个第二连接端312以及十二条第一转接线。在一组第二侧第一转接单元300b内，十二个第一连接端311可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的十二个第一连接端311的第一排布序号可以对应为1至12。十二个第一连接端311可以与十二条连续排布的第三数据引出线一一对应连接。其中，第一个第一连接端、第三个第一连接端、第五个第一连接端、第七个第一连接端、第九个第一连接端和第十一个第一连接端所连接的第三数据引出线可以位于第一栅金属层，第二个第一连接端、第四个第一连接端、第六个第一连接端、第八个第一连接端、第十个第一连接端和第十二个第一连接端所连接的第三数据引出线可以位于第二栅金属层。
在一些示例中，在一组第二侧第一转接单元300b内，十二个第二连接端312可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的十二个第二连接端312的第二排布序号可以对应为1至12。十二条第一转接线可以包括四条第一顺序转接线314、四条第一插序转接线313a和四条第二插序转接线313b。
图22为图21所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序 原理示意图。本示例中，未经过插序调整的顺序对应显示区域的多条数据线的排布顺序；排布在同一列的第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)与同一条数据线连接，排布在同一列的第三子像素(例如绿色子像素G)与同一条数据线连接。在一些示例中，如图22所示，未经过插序调整的十二条数据线(例如，第n-3条至第n+8条数据线)可以沿第二方向D2的反方向排布，可以按照隔两条数据线插入一条数据线的方式进行顺序调整。按照2插1方式调整得到的数据信号的最小循环数为12。以子像素排布顺序(例如奇数行像素单元的子像素排布顺序)为RGBG为例，如图22所示，按照2插1方式得到的十二条数据线(插序调整后的第n条至第n+8条)对应的子像素循环为：RGBG GRBG BGGR。以子像素排布顺序(例如偶数行像素单元的子像素排布顺序)为BGRG为例，按照2插1方式得到的十二条数据线(插序调整后的第n条至第n+8条)对应的子像素循环可以为BGRG GBRG RGGB。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图21所示，多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环可以为：RGBG GRBG BGGR，多个数据接触垫传输的数据信号被提供至多组第二侧第一转接单元300b的第二连接端312，例如，通过多组第二侧第一转接单元300b之后，由多组第二侧第一转接单元300b的第一连接端311输出的数据信号的最小循环数仍为12，且沿第二方向D2的反方向，十二路数据信号对应的子像素循环可以为：GRGB GRGB GBGR。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：BGRG GBRG RGGB，通过多组第二侧第一转接单元300b之后，由多组第二侧第一转接单元300b的第一连接端311输出的数据信号对应的子像素循环可以为：GBGR GBGR GRGB。
图23为本公开至少一实施例的第二组测试电路的平面示意图。在一些示例中，如图23所示，第二组测试电路可以与一组第二侧第一转接单元所连接的十二条第三数据引出线263连接。第二组测试电路可以包括：三个第一测试电路401和三个第二测试电路402。其中，一个第一测试电路401、一个第二测试电路402、一个第一测试电路401、两个第二测试电路402和一个第一测试电路401可以沿第二方向D2的反方向依次排布。
在一些示例中，在测试阶段，测试电路在不同时段提供的测试数据信号可以不同。测试电路可以根据显示区域逐行扫描的规律来提供对应的测试数据信号。例如，针对奇数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GRGB GRGB GBGR的循环顺序向多条数据引出线提供对应的测试数据信号；针对偶数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GBGR GBGR GRGB的循环顺序向多条数据引出线提供对应的测试数据信号。关于本示例的测试电路的其余说明可以参照前述实施例的描述，故于此不再赘述。
图24为本公开至少一实施例的一组第一侧第一转接单元的另一示意图。图25为图24所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。本示例中，m可以为16。
在一些示例中，如图24所示，一组第一侧第一转接单元300a可以包括：十六个第一连接端311、十六个第二连接端312、以及十六条第一转接线。十六条第一转接线可以包括：八条第一顺序转接线314、四条第一插序转接线313a和四条第二插序转接线313b。十六条第一转接线可以包括四个第一换序单元，每个第一换序单元可以包括：在衬底的正投影存在交叠的第一插序转接线(例如包括一条第一插序转接线313a)和第二插序转接线(例如包括一条第二插序转接线313b)。在第二方向D2上，两个第一换序单元、四条第一顺序转接线314、两个第一换序单元和四条第一顺序转接线314可以依次排布。
在一些示例中，十六个第一连接端311可以与十六条连续排布的第三数据引出线一一对应连接。所述十六条第三数据引出线可以交替设置在第一栅金属层和第二栅金属层。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端；第二条第一插序转接线313a可以连接第三个第一连接端和第四个第二连接端；第三条第一插序转接线313a可以连接第九个第一连接端和第十个第二连接端；第四条第一插序转接线313a可以连接第十一个第一连接端和第十二个第二连接端。第一条第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端；第二条第二插序转接线313b可以连接第四个第一连接端和第三个第二连接端；第三条第二插序转接线313b可以连接第十个第一连接端和第九个第二连接端；第四条第二插序转接线313b可以连接第十二个第一连接端和第十一个第二连接端。
在一些示例中，第一条第一顺序转接线314可以连接第五个第一连接端和第五个第二连接端；第二条第一顺序转接线314可以连接第六个第一连接端和第六个第二连接端；第三条第一顺序转接线314可以连接第七个第一连接端和第七个第二连接端；第四条第一顺序转接线314可以连接第八个第一连接端和第八个第二连接端；第五条第一顺序转接线314可以连接第十三个第一连接端和第十三个第二连接端；第六条第一顺序转接线314可以连接第十四个第一连接端和第十四个第二连接端；第七条第一顺序转接线314可以连接第十五个第一连接端和第十五个第二连接端；第八条第一顺序转接线314可以连接第十六个第一连接端和第十六个第二连接端。
在一些示例中，如图25所示，以显示区域的子像素排布方式如图4所示，以显示区域奇数行像素单元的子像素排布顺序为RGBG为例，以未经过插序调整的十六条数据线(例如序号为n-3至n+12)为例进行说明，十六条数据线可以沿第二方向D2排布，按照隔三条数据线插入一条数据线的方式(即3插1方式)，可以将第n-3条至第n-1条数据线所连接的数据连接线插入第n+1条数据线至第n+12条数据线之间。例如，第n-1条数据线可以插入第n+3条数据线和第n+4条数据线之间，第n-2条数据线可以插入第n+6条和第n+7条数据线之间，第n-3条数据线可以插入第n+9条和第n+10条数据线之间。按照3插1方式得到的数据信号的最小循环数为16。以一行显示单元的子像素排布顺序为RGBG为例，按照3插1方式得到的十六条数据线对应的子像素循环为：GRGB BGRG GBGR RGBG。以一行显示单元的子像素排布顺序为BGRG为例，按照3插1方式得到的十六条数据线对应的子像素循环可以为：GBGR RGBG GRGB BGRG。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图24所示，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GRGB BGRG GBGR RGBG，多路数据信号通过多组第一侧第一转接单元300a之后，数据信号的最小循环数仍为16，且在第二方向D2上，十六路数据信号对应的子像素循环可以为：RGBG BGRG BGRG RGBG。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GBGR RGBG GRGB BGRG，通过多组第一侧第一转接单元300a之后，由多组第一侧第一转接单元300a的第一连接端311输出的数据信号对应的子像素循环可以为：BGRG RGBG RGBG BGRG。
图26为图24所示的一组第一侧第一转接单元对应的第一组测试电路的平面示意图。在一些示例中，如图26所示，一个第一组测试电路与一组第一侧第一转接单元所连接的十六条第三数据引出线连接。第一组测试电路可以包括：四个第一测试电路401和四个第二测试电路402。其中，一个第一测试电路401、两个第二测试电路402、一个第一测试电路401、一个第二测试电路402、两个第一测试电路401和一个第二测试电路402可以 沿第二方向D2依次排布。
在一些示例中，测试电路可以分时段给显示区域内的不同行像素单元的子像素提供测试数据信号。在测试阶段，第一组测试电路可以在第一测试时段按照RGBG BGRG BGRG RGBG的循环顺序向多条第三数据引出线提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测奇数行(或偶数行)像素单元的显示情况。第一组测试电路可以在第二测试时段按照BGRG RGBG RGBG BGRG的循环顺序向多条第三数据引出线提供对应的测试数据信号，这些测试数据信号通过多组第二转接单元的换序之后，被提供给显示区域的第二数据线和数据连接线，以检测偶数行(或奇数行)像素单元的显示情况。关于测试电路的其他说明可以参照前述实施例的描述，故于此不再赘述。
图27为本公开至少一实施例的一组第二侧第一转接单元的示意图。在一些示例中，如图27所示，一组第二侧第一转接单元300b可以包括：十六个第一连接端311、十六个第二连接端312以及十六条第一转接线。在一组第二转接单元300b内，十六个第一连接端311可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的十六个第一连接端311的第一排布序号可以对应为1至16。十六个第一连接端311可以与十六条连续排布的第三数据引出线连接。其中，第一个第一连接端、第三个第一连接端、第五个第一连接端、第七个第一连接端、第九个第一连接端、第十一个第一连接端、第十三个第一连接端和第十五个第一连接端所连接的第三数据引出线可以位于第一栅金属层，第二个第一连接端、第四个第一连接端、第六个第一连接端、第八个第一连接端、第十个第一连接端、第十二个第一连接端、第十四个第一连接端和第十六个第一连接端所连接的第三数据引出线可以位于第二栅金属层。
在一些示例中，在一组第二侧第一转接单元300b内，十六个第二连接端312可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的十六个第二连接端312的第二排布序号可以对应为1至16。十六条第一转接线可以包括八条第一顺序转接线314、四条第一插序转接线313a和四条第二插序转接线313b。
图28为图27所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。本示例中，未经过插序调整的顺序对应显示区域的多条数据线的排布顺序；排布在同一列的第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)与同一条数据线连接，排布在同一列的第三子像素(例如绿色子像素G)与同一条数据线连接。在一些示例中，如图28所示，未经过插序调整的十六条数据线(例如第n-3条至第n+12条)沿第二方向D2的反方向排布，可以按照隔三条数据线插入一条数据线的方式进行顺序调整。按照3插1的方式进行调整得到的数据信号的最小循环数为16。以一行像素单元的子像素排布顺序为RGBG为例，如图28所示，按照3插1方式得到的十六条数据线(插序调整后的第n条至第n+12条)对应的子像素循环为：RGBG GRGB BGRG GBGR。以一行像素单元的子像素排布顺序为BGRG为例，按照3插1方式得到的十六条数据线(插序调整后的第n条至第n+12条)对应的子像素循环可以为：BGRG GBGR RGBG GRGB。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图27所示，多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环可以为：RGBG GRGB BGRG GBGR，多路数据信号通过多组第二侧第一转接单元300b之后的数据信号的最小循环数仍为16，且沿第二方向D2的反方向，十六路数据信号对应的子像素循环可以为：GRGB GRGB GBGR GBGR。在第二时段，多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环可以为： BGRG GBGR RGBG GRGB，通过多组第二侧第一转接单元300b之后，沿第二方向D2的反方向，由多组第二侧第一转接单元300b的第一连接端311输出的数据信号对应的子像素循环可以为：GBGR GBGR GRGB GRGB。
图29为本公开至少一实施例的第二组测试电路的平面示意图。在一些示例中，如图29所示，第二组测试电路可以与一组第二侧第一转接单元所连接的十六条第三数据引出线263连接。第二组测试电路可以包括：四个第一测试电路401和四个第二测试电路402。其中，一个第一测试电路401、一个第二测试电路402、一个第一测试电路401、两个第二测试电路402、一个第一测试电路401、一个第二测试电路402和一个第一测试电路401可以沿第二方向D2的反方向依次排布。
在一些示例中，在测试阶段，测试电路在不同时段提供的测试数据信号可以不同。测试电路可以根据显示区域逐行扫描的规律来提供对应的测试数据信号。例如，针对奇数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GRGB GRGB GBGR GBGR的循环顺序向多条数据引出线提供对应的测试数据信号；针对偶数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GBGR GBGR GRGB GRGB的循环顺序向多条数据引出线提供对应的测试数据信号。关于本示例的测试电路的其余说明可以参照前述实施例的描述，故于此不再赘述。
图30为本公开至少一实施例的一组第一侧第一转接单元的另一示意图。图31为图30所示一组第一侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。本示例中，m可以为20。
在一些示例中，如图30所示，一组第一侧第一转接单元300a可以包括：二十个第一连接端311、二十个第二连接端312、以及二十条第一转接线。二十条第一转接线可以包括：八条第一顺序转接线314、六条第一插序转接线313a和六条第二插序转接线313b。二十条第一转接线可以包括六个第一换序单元，每个第一换序单元可以包括：在衬底的正投影存在交叠的第一插序转接线(例如包括一条第一插序转接线313a)和第二插序转接线(例如包括一条第二插序转接线313b)。在第二方向D2上，三个第一换序单元、四条第一顺序转接线314、三个第一换序单元和四条第一顺序转接线314可以依次排布。
在一些示例中，二十个第一连接端311可以与二十条连续排布的第三数据引出线一一对应连接。所述二十条第三数据引出线可以交替设置在第一栅金属层和第二栅金属层。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端；第二条第一插序转接线313a可以连接第三个第一连接端和第四个第二连接端；第三条第一插序转接线313a可以连接第五个第一连接端和第六个第二连接端；第四条第一插序转接线313a可以连接第十一个第一连接端和第十二个第二连接端；第五条第一插序转接线313a可以连接第十三个第一连接端和第十四个第二连接端；第六条第一插序转接线313a可以连接第十五个第一连接端和第十六个第二连接端。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端；第二条第二插序转接线313b可以连接第四个第一连接端和第三个第二连接端；第三条第二插序转接线313b可以连接第六个第一连接端和第五个第二连接端；第四条第二插序转接线313b可以连接第十二个第一连接端和第十一个第二连接端；第五条第二插序转接线313b可以连接第十四个第一连接端和第十三个第二连接端；第六条第二插序转接线313b可以连接第十六个第一连接端和第十五个第二连接端。
在一些示例中，在一组第一侧第一转接单元300a内，在第二方向D2上，第一条第一顺序转接线314可以连接第七个第一连接端和第七个第二连接端；第二条第一顺序转接线314可以连接第八个第一连接端和第八个第二连接端；第三条第一顺序转接线314可以连接第九个第一连接端和第九个第二连接端；第四条第一顺序转接线314可以连接第十个第一连接端和第十个第二连接端；第五条第一顺序转接线314可以连接第十七个第一连接端和第十七个第二连接端；第六条第一顺序转接线314可以连接第十八个第一连接端和第十八个第二连接端；第七条第一顺序转接线314可以连接第十九个第一连接端和第十九个第二连接端；第八条第一顺序转接线314可以连接第二十个第一连接端和第二十个第二连接端。
在一些示例中，如图31所示，以显示区域的子像素排布方式如图4所示，以显示区域奇数行像素单元的子像素排布顺序为RGBG为例，以未经过插序调整的二十条数据信号(例如序号为n-3至n+16)为例进行说明，二十条数据线可以沿第二方向D1排布，可以按照隔四条数据线插入一条数据线的方式(即4插1方式)，可以将第n-3条至第n-1条数据线所连接的数据连接线插入第n+1条数据线至第n+16条数据线之间。例如，第n-1条数据线可以插入第n+4条数据线和第n+5条数据线之间，第n-2条数据线可以插入第n+8条和第n+9条数据线之间，第n-3条数据线可以插入第n+12条和第n+13条数据线之间。按照4插1的方式进行调整得到的数据信号的最小循环数为20。以一行像素单元的子像素排布顺序为RGBG为例，按照4插1方式得到的二十条数据线对应的子像素循环为：GRGB GBRG BGGR GBGR RGBG。以一行像素单元的子像素排布顺序为BGRG，按照4插1方式得到的二十条数据线对应的子像素循环可以为：GBGR GRBG RGGB GRGB BGRG。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图30所示，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GRGB GBRG BGGR GBGR RGBG，多路数据信号通过多组第一侧第一转接单元300a之后，数据信号的最小循环数仍为20，且在第二方向D2上，二十路数据信号对应的子像素循环可以为：RGBG BGRG BGRG BGRG RGBG。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2上对应的子像素循环可以为：GBGR GRBG RGGB GRGB BGRG，通过多组第一侧第一转接单元300a之后，由多组第一侧第一转接单元300a的第一连接端311输出的数据信号对应的子像素循环可以为：BGRG RGBG RGBG RGBG BGRG。
图32为图30所示的一组第一侧第一转接单元对应的第一组测试电路的平面示意图。在一些示例中，如图32所示，一个第一组测试电路与一组第一侧第一转接单元所连接的二十条第三数据引出线连接。第一组测试电路可以包括：五个第一测试电路401和五个第二测试电路402。其中，一个第一测试电路401、两个第二测试电路402、一个第一测试电路401、一个第二测试电路402、一个第一测试电路401、一个第二测试电路402、两个第一测试电路401和一个第二测试电路402可以沿第二方向D2依次排布。
在一些示例中，在测试阶段，测试电路在不同时段提供的测试数据信号可以不同。测试电路可以根据显示区域逐行扫描的规律来提供对应的测试数据信号。例如，针对奇数行像素单元，第一组测试电路可以沿第二方向D2按照RGBG BGRG BGRG BGRG RGBG的循环顺序向多条数据引出线提供对应的测试数据信号；针对偶数行像素单元，第一组测试电路可以沿第二方向D2按照BGRG RGBG RGBG RGBG BGRG的循环顺序向多条数据引出线提供对应的测试数据信号。关于测试电路的其他说明可以参照前述实施例的描述，故于此不再赘述。
图33为本公开至少一实施例的一组第二侧第一转接单元的示意图。在一些示例中，如图33所示，一组第二侧第一转接单元300b可以包括：二十个第一连接端311、二十个第二连接端312以及二十条第一转接线。在一组第二侧第一转接单元300b内，二十个第一连接端311可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的二十个第一连接端311的第一排布序号可以对应为1至20。二十个第一连接端311可以与二十条连续排布的第三数据引出线连接。其中，第一个第一连接端、第三个第一连接端、第五个第一连接端、第七个第一连接端、第九个第一连接端、第十一个第一连接端、第十三个第一连接端、第十五个第一连接端、第十七个第一连接端和第十九个第一连接端所连接的第三数据引出线可以位于第一栅金属层，第二个第一连接端、第四个第一连接端、第六个第一连接端、第八个第一连接端、第十个第一连接端、第十二个第一连接端、第十四个第一连接端、第十六个第一连接端、第十八个第一连接端和第二十个第一连接端所连接的第三数据引出线可以位于第二栅金属层。
在一些示例中，在一组第二侧第一转接单元300b内，二十个第二连接端312可以沿第二方向D2的反方向依次排布，例如，沿第二方向D2的反方向依次排布的二十个第二连接端312的第二排布序号可以对应为1至20。二十条第一转接线可以包括八条第一顺序转接线314、六条第一插序转接线313a和六条第二插序转接线313b。
图34为图33所示的一组第二侧第一转接单元的第二连接端所传输的数据信号的插序原理示意图。在一些示例中，如图34所示，以一行像素单元的子像素排布顺序为RGBG为例，按照4插1方式得到的二十条数据线对应的子像素循环为：RGBG RGGB GRBG BGRG GBGR。以一行像素单元的子像素排布顺序为BGRG，按照4插1方式得到的二十条数据线对应的子像素循环为：BGRG BGGR GBRG RGBG GRGB。
在一些示例中，多个数据接触垫可以分时段给显示区域的不同行像素单元的子像素提供数据信号。在第一时段，如图33所示，多个数据接触垫提供的数据信号沿第二方向D2的反方向对应的子像素循环可以为：RGBG RGGB GRBG BGRG GBGR，多路数据信号通过多组第二侧第一转接单元300b之后的数据信号的最小循环数仍为20，且沿第二方向的反方向，二十路数据信号对应的子像素循环可以为：GRGB GRGB GRGB GBGR GBGR。在第二时段，多个数据接触垫传输的数据信号沿第二方向D2的反方向上对应的子像素循环可以为：BGRG BGGR GBRG RGBG GRGB，通过多组第二侧第一转接单元300b之后，由多组第二侧第一转接单元300b的第一连接端311输出的数据信号对应的子像素循环可以为：GBGR GBGR GBGR GRGB GRGB。
图35为本公开至少一实施例的第二组测试电路的平面示意图。在一些示例中，如图35所示，第二组测试电路可以与一组第二侧第一转接单元所连接的二十条第三数据引出线263连接。第二组测试电路可以包括：五个第一测试电路401和五个第二测试电路402。其中，一个第一测试电路401、一个第二测试电路402、一个第一测试电路401、一个第二测试电路402、一个第一测试电路401、两个第二测试电路402、一个第一测试电路401、一个第二测试电路402和一个第一测试电路401可以沿第二方向D2的反方向依次排布。
在一些示例中，在测试阶段，测试电路在不同时段提供的测试数据信号可以不同。测试电路可以根据显示区域逐行扫描的规律来提供对应的测试数据信号。例如，针对奇数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GRGB GRGB GRGB GBGR GBGR的循环顺序向多条数据引出线提供对应的测试数据信号；针对偶数行像素单元，第二组测试电路可以沿第二方向D2的反方向按照GBGR GBGR GBGR GRGB GRGB的循环顺序向多条数据引出线提供对应的测试数据信号。关于本示例的测试电路的其余说明可以参照前述实施例的描述，故于此不再赘述。
图36A至图36C为本公开至少一实施例的多个第一转接单元的连接方式示例图。图36A至图36C以显示区域的子像素排布方式如图4所示为例进行说明。
在一些示例中，如图36A所示，在第二方向D2上，第一插序转接线313a可以连接第一个第一连接端311和第四个第二连接端312；第一条第二插序转接线313b可以连接第二个第一连接端311和第一个第二连接端312；第二条第二插序转接线313b可以连接第三个第一连接端311和第二个第二连接端312；第三条第二插序转接线313b可以连接第四个第一连接端311和第三个第二连接端312。第一插序转接线313a在衬底的正投影与三条第二插序转接线313b在衬底的正投影均存在交叠。在一些示例中，第一插序转接线313a可以位于第一源漏金属层，三条第二插序转接线313b可以位于第二源漏金属层。然而，本实施例对此并不限定。在另一些示例中，第一插序转接线可以位于第二源漏金属层，第二插序转接线可以位于第一源漏金属层。
在一些示例中，如图36A所示，在第二连接端312传输的数据信号配置为依次对应GBGR时，通过四条第一转接线之后，第一连接端311传输的数据信号配置为依次对应RGBG。本示例通过设置第一转接单元可以使得第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)对应的数据信号可以在位于第二栅金属层(或第一栅金属层)的数据引出线传输，使得第三子像素(例如绿色子像素G)对应的数据信号可以在位于第一栅金属层(或第二栅金属层)的数据引出线传输，从而保证信号传输的均一性。
在一些示例中，如图36B所示，在第二方向D2上，第一插序转接线313a可以连接第一个第一连接端311和第三个第二连接端312；第二插序转接线313b可以连接第三个第一连接端311和第一个第二连接端312；第一条第一顺序转接线314可以连接第二个第一连接端和第二个第二连接端；第二条第一顺序转接线314可以连接在第四个第一连接端和第四个第二连接端之间。第一条第一顺序转接线314在衬底的正投影与第一插序转接线313a和第二插序转接线313b在衬底的正投影均存在交叠。第二条第一顺序转接线314在衬底的正投影与第一插序转接线313a和第二插序转接线313b在衬底的正投影没有交叠。
在一些示例中，如图36B所示，第一插序转接线313a可以位于第一源漏金属层，第二插序转接线313b可以位于第二源漏金属层。第一条第一顺序转接线314可以位于第一栅金属层，第一条第一顺序转接线314所连接的第一连接端311的第一连接电极可以位于第一源漏金属层，第二连接电极可以位于第一栅金属层，第一条第一顺序转接线314所连接的第二连接端312的第三连接电极可以位于第一源漏金属层，第四连接电极可以位于第一栅金属层。第一条第一顺序转接线314与所连接的第一连接端311的第二连接电极和所连接的第二连接端312的第四连接电极可以为相互连接的一体结构。第二条第一顺序转接线314可以位于第二源漏金属层。然而，本实施例对此并不限定。在另一些示例中，第一插序转接线可以位于第二源漏金属层，第二插序转接线可以位于第一源漏金属层。
在一些示例中，如图36B所示，在第二连接端312传输的数据信号配置为依次对应BGRG时，通过四条第一转接线之后，第一连接端311传输的数据信号配置为依次对应RGBG。本示例通过设置第一转接单元可以使得第一子像素(例如红色子像素R)和第二子像素(例如蓝色子像素B)对应的数据信号可以在位于第二栅金属层(或第一栅金属层)的数据引出线传输，使得第三子像素(例如绿色子像素G)对应的数据信号可以在位于第一栅金属层(或第二栅金属层)的数据引出线传输，从而保证信号传输的均一性。
在一些示例中，如图36C所示，在第二方向D2上，第一插序转接线313a可以连接第一个第一连接端311和第四个第二连接端312；第一条第二插序转接线313b可以连接第三个第一连接端311和第一个第二连接端312；第二条第二插序转接线313b可以连接第四个第一连接端311和第三个第二连接端312；第一顺序转接线314可以连接第二个第 一连接端和第二个第二连接端。
在一些示例中，如图36C所示，第一顺序转接线314在衬底的正投影与第一插序转接线313a和第一条第二插序转接线313b在衬底的正投影均存在交叠，并与第二条第二插序转接线313b在衬底的正投影可以没有交叠。第一插序转接线313a在衬底的正投影与两条第二插序转接线313b在衬底的正投影可以均存在交叠。在一些示例中，第一插序转接线313a可以位于第一源漏金属层，两条第二插序转接线313b可以位于第二源漏金属层，第一顺序转接线314可以位于第一栅金属层。然而，本实施例对此并不限定。
图37为本公开至少一实施例的显示区域的子像素的另一排布示意图。在一些示例中，如图37所示，显示区域的每个像素单元可以包括：一个出射第一颜色光的第一子像素15、一个出射第二颜色光的第二子像素16、以及一个出射第三颜色光的第三子像素17。多个子像素可以沿第一方向D1和第二方向D2阵列排布。多个第一子像素15可以沿第一方向D1排布为一列，多个第二子像素16可以沿第一方向D1排布为一列，多个第三子像素17可以沿第一方向D1排布为一列。第一子像素15、第三子像素17和第二子像素16可以沿第二方向D2周期性排布。本示例中，第一子像素15可以为红色子像素(R)，第二子像素16可以为蓝色子像素(B)，第三子像素17可以为绿色子像素(G)；多个子像素可以采用Real RGB的排布方式。
图38A至图38F为本公开至少一实施例的多个第一转接单元的连接方式示例图。图38A至图38F以显示区域的子像素排布方式如图37所示为例进行说明。在一些示例中，第一边框区域的一组第一转接单元可以采用如图38A至图38F中至少之一所示的三个第一转接单元的连接方式。本示例的多组第一转接单元的第二连接端连接的数据接触垫的数据信号的传输顺序可以参照前述实施例的1插1或多插1的方式来得到。
在一些示例中，如图38A所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以通过三条第一顺序连接线314一一对应连接。在第二连接端312传输的数据信号配置为依次对应RGB时，通过三条第一顺序转接线314之后，第一连接端311传输的数据信号配置为依次对应RGB。例如，三条第一顺序转接线314可以均位于第二源漏金属层。
在一些示例中，如图38B所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以依次通过一条第一顺序连接线314、一条第一插序连接线313a和一条第二插序连接线313b连接。其中，第一顺序转接线314可以连接第一个第一连接端311和第一个第二连接端312，第一插序转接线313a可以连接第二个第一连接端311和第三个第二连接端312，第二插序转接线313b可以连接第三个第一连接端311和第二个第二连接端312。第一插序转接线313a和第二插序转接线313b在衬底的正投影可以存在交叠。例如，第一顺序转接线314和第二插序转接线313b可以位于第二源漏金属层，第一插序转接线313a可以位于第一源漏金属层。在三个第二连接端312传输的数据信号配置为依次对应RBG时，通过三条转接线之后，三个第一连接端311传输的数据信号配置为依次对应RGB。
在一些示例中，如图38C所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以依次通过一条第一插序连接线313a、一条第二插序连接线313b和一条第一顺序连接线314连接。其中，第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端，第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端，第一顺序转接线314可以连接第三个第一连接端和第三个第二连接端。第一插序转接线313a和第二插序转接线313b在衬底的正投影可以存在交叠。例如，第一顺序转接线314和第二插序转接线313b可以位于第二源漏金属层，第一插序转接线313a可以位于第一源 漏金属层。在三个第二连接端312传输的数据信号配置为依次对应GRB时，通过三条第一转接线之后，三个第一连接端311传输的数据信号配置为依次对应RGB。
在一些示例中，如图38D所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以依次通过一条第一插序转接线313a和两条第二插序转接线313b连接。其中，第一插序转接线313a可以连接第一个第一连接端和三个第二连接端，第一条第二插序转接线313b可以连接第二个第一连接端和第一个第二连接端，第二条第二插序转接线313b可以连接第三个第一连接端和第二个第二连接端。第一插序转接线313a在衬底的正投影可以与两条第二插序转接线313b在衬底的正投影存在交叠。例如，第一插序转接线313a可以位于第一源漏金属层，两条第二插序转接线313b可以位于第二源漏金属层。在三个第二连接端312传输的数据信号配置为依次对应GBR时，通过三条第一转接线之后，三个第一连接端311传输的数据信号配置为依次对应RGB。
在一些示例中，如图38E所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以依次通过两条第一插序转接线313a和一条第二插序转接线313b连接。其中，第一条第一插序转接线313a可以连接第一个第一连接端和第二个第二连接端，第二条第一插序转接线313a可以连接第二个第一连接端和第三个第二连接端，第二插序转接线313b可以连接第三个第一连接端和第一个第二连接端。第二插序转接线313b在衬底的正投影与两条第一插序转接线313a在衬底的正投影存在交叠。例如，两条第一插序转接线313a可以位于第二源漏金属层，第二插序转接线313b可以位于第一源漏金属层。在三个第二连接端312传输的数据信号配置为依次对应BRG时，通过三条第一转接线之后，三个第一连接端311传输的数据信号配置为依次对应RGB。
在一些示例中，如图38F所示，在第二方向D2上，三个第一连接端311和三个第二连接端312可以依次通过一条第一插序转接线313a、一条第一顺序转接线314和一条第二插序转接线313b连接。其中，第一插序转接线313a可以连接第一个第一连接端和第三个第二连接端，第一顺序转接线314可以连接第二个第一连接端和第二个第二连接端，第二插序转接线313b可以连接第三个第一连接端和第一个第二连接端。第一插序转接线313a在衬底的正投影与第一顺序转接线314和第二插序转接线313b在衬底的正投影均存在交叠。例如，第一插序转接线313a可以位于第二源漏金属层，第二插序转接线313b可以位于第一源漏金属层，第一顺序转接线314可以位于第一栅金属层。在三个第二连接端312传输的数据信号配置为依次对应BGR时，通过三条第一转接线之后，三个第一连接端311传输的数据信号配置为依次对应RGB。
本实施例提供的显示基板，通过设置多组第一转接单元连接多条数据引出线和多个数据接触垫，可以利用多组第一转接单元来调整数据接触垫所传输数据信号的顺序，同时搭配多组第二转接单元对数据信号的顺序调整，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
本实施例还提供一种显示基板，包括衬底、多个子像素、多条第一数据线、多条第二数据线、多条数据连接线、多条数据引出线以及多组测试电路。衬底包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：第一信号接入区域以及位于所述第一信号接入区域和所述显示区域之间的走线引出区域。多个子像素设置在所述衬底的一侧且位于所述显示区域。多条第一数据线、多条第二数据线以及多条数据连接线位于所述显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接。多条数据引出线位于所述走线引出区域，所述多条数据引出线与所述多条第二数据线和所述多条数据连接线连接。多组测试电路，位于所述走线引出区域且沿第二方向依次排布，每组测试电路 与m条连续排布的数据引出线连接，所述第二方向与所述第一方向交叉；m为大于1的整数。每组测试电路包括：a个第一测试电路和b个第二测试电路，a和b均为大于0的整数，且a与b之和的两倍等于m。所述第一测试电路包括：第一测试晶体管、第二测试晶体管和第三测试晶体管；所述第一测试晶体管的栅极与第一测试控制线连接，所述第一测试晶体管的第一极与第一测试数据线连接，所述第二测试晶体管的栅极与第二测试控制线连接，所述第二测试晶体管的第一极与第二测试数据线连接，所述第一测试晶体管的第二极和所述第二测试晶体管的第二极与同一条数据引出线连接；所述第三测试晶体管的栅极与第三测试控制线连接，所述第三测试晶体管的第一极与第三测试数据线连接。所述第二测试电路包括：第四测试晶体管、第五测试晶体管和第六测试晶体管；所述第四测试晶体管的栅极与所述第二测试控制线连接，所述第四测试晶体管的第一极与所述第一测试数据线连接，所述第五测试晶体管的栅极与所述第一测试控制线连接，所述第五测试晶体管的第一极与所述第二测试数据线连接，所述第四测试晶体管的第二极和所述第五测试晶体管的第二极与同一条数据引出线连接；所述第六测试晶体管的栅极与所述第三测试控制线连接，所述第三测试晶体管的第一极与所述第三测试数据线连接；所述第一测试晶体管的第二极、所述第三测试晶体管的第二极、所述第四测试晶体管的第二极和所述第六测试晶体管的第二极与不同的条数据引出线连接。
本实施例通过设置多组测试电路，来调整测试数据信号的传输顺序，可以避免在第二扇出区域的跳线设计，有利于减少跳线设计带来的不良，从而提高显示基板的可靠性。
在一些示例性实施方式中，所述第一测试电路的第一测试晶体管、第二测试晶体管和第三测试晶体管沿所述第一方向排布；所述第二测试电路的第四测试晶体管、第五测试晶体管和第六测试晶体管沿所述第一方向排布。所述第一测试晶体管和所述第四测试晶体管在所述第二方向对齐设置，所述第二测试晶体管和所述第五测试晶体管在所述第二方向对齐设置，所述第三测试晶体管和所述第六测试晶体管在所述第二方向对齐设置。
在一些示例性实施方式中，m为8；每组测试电路包括：两个第一测试电路和两个第二测试电路；其中，一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向排布。
在一些示例性实施方式中，m为12；每组测试电路包括：三个第一测试电路和三个第二测试电路；其中，一个第一测试电路、两个第二测试电路、两个第一测试电路和一个第二测试电路沿着所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为16；每组测试电路包括：四个第一测试电路和四个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
在一些示例性实施方式中，m为20；每组测试电路包括：五个第一测试电路和五个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试机电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
关于本实施例的相关说明可以参照前述实施例的描述，故于此不再赘述。
图39为本公开至少一实施例的显示装置的示意图。在一些示例中，如图39所示，显示基板910可以为OLED显示基板。显示装置91可以为：OLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。然而，本实施例对此并不限定。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本申请的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本申请的限制，本领域的普通技术人员在本申请的范围内可以对上述实施例进行变化、修改、替换和变型。

Claims (30)

  1. 一种显示基板，包括：
    衬底，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：第一信号接入区域以及位于所述第一信号接入区域和所述显示区域之间的走线引出区域；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多条第一数据线、多条第二数据线以及多条数据连接线，位于所述显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接；
    多条数据引出线，位于所述走线引出区域；
    多个数据接触垫，位于所述第一信号接入区域；
    多组第一转接单元和多组第二转接单元，位于所述走线引出区域，所述多组第一转接单元位于所述多组第二转接单元远离所述显示区域的一侧，所述多组第一转接单元沿第二方向排布，所述多组第二转接单元沿所述第二方向排布，所述第二方向与所述第一方向交叉；
    其中，所述多条数据引出线通过所述多组第一转接单元与所述多个数据接触垫连接，还通过所述多组第二转接单元与所述多条第二数据线和所述多条数据连接线连接，使得所述多个数据接触垫提供的数据信号的顺序与沿所述第二方向排布的所述多条第二数据线和所述多条数据连接线所需的数据信号的顺序匹配。
  2. 根据权利要求1所述的显示基板，其中，每组第一转接单元包括：m个第一连接端、m个第二连接端、以及m条第一转接线；每条第一转接线连接在一个第一连接端和一个第二连接端之间；每个第一连接端与一条数据引出线连接，每个第二连接端与一个数据接触垫连接；所述m个第一连接端沿所述第二方向排布且对应不同的第一排布序号，所述m个第二连接端沿所述第二方向排布且对应不同的第二排布序号；
    每组第一转接单元内的m条第一转接线包括：a条插序转接线，每条插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号不同；其中，m和a均为大于1的整数，且m大于或等于a。
  3. 根据权利要求2所述的显示基板，其中，每组第一转接单元内的a条插序转接线包括：a1条第一插序转接线和a2条第二插序转接线，a1和a2均为大于0的整数，且a1与a2之和为a；
    所述第一插序转接线所连接的第一连接端对应的第一排布序号小于所连接的第二连接端对应的第二排布序号；
    所述第二插序转接线所连接的第一连接端对应的第一排布序号大于所连接的第二连接端对应的第二排布序号。
  4. 根据权利要求3所述的显示基板，其中，所述第一插序转接线所连接的第二连接端对应的第二排布序号与所连接的第一连接端对应的第一排布序号之差，大于或等于所述第二插序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号之差。
  5. 根据权利要求3所述的显示基板，其中，所述第一插序转接线在所述衬底的正投影与至少一条第二插序转接线在所述衬底的正投影存在交叠。
  6. 根据权利要求3至5中任一项所述的显示基板，其中，每组第一转接单元内的m条第一转接线还包括：b条第一顺序转接线，每条第一顺序转接线所连接的第一连接端对应的第一排布序号与所连接的第二连接端对应的第二排布序号相同；b为大于1的整数，且b小于或等于a。
  7. 根据权利要求6所述的显示基板，其中，所述b条第一顺序转接线与所述第一插序转接线为同层结构，或者，至少一条第一顺序转接线位于所述第一插序转接线和所述第二插序转接线靠近所述衬底的一侧。
  8. 根据权利要求6所述的显示基板，其中，m为8；
    每组第一转接单元包括：八个第一连接端、八个第二连接端、以及八条第一转接线；所述八个第一连接端沿所述第二方向依次排布，所述八个第二连接端沿所述第二方向依次排布且位于所述八个第一连接端靠近所述第一信号接入区域的一侧，所述八条第一转接线包括两条第一插序转接线、两条第二插序转接线以及四条第一顺序转接线；
    所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；
    所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；
    其中，i的取值包括：1、5。
  9. 根据权利要求8所述的显示基板，其中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素；
    所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数；
    在所述第一时段，每组第一转接单元内的所述八个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第二子像素、第三子像素、第三子像素、第二子像素、第一子像素和第三子像素，或者，配置为依次对应第一子像素、第三子像素、第三子像素、第二子像素、第二子像素、第三子像素、第三子像素和第一子像素；
    在所述第二时段，每组第一转接单元内的所述八个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第一子像素、第三子像素、第三子像素、第一子像素、第二子像素和第三子像素，或者配置为依次对应第二子像素、第三子像素、第三子像素、第一子像素、第一子像素、第三子像素、第三子像素和第二子像素。
  10. 根据权利要求6所述的显示基板，其中，m为12；
    每组第一转接单元包括：十二个第一连接端、十二个第二连接端、以及十二条第一转接线；所述十二个第一连接端沿所述第二方向依次排布，所述十二个第二连接端沿所述第二方向依次排布且位于所述十二个第一连接端靠近所述第一信号接入区域的一侧，所述十二条第一转接线包括四条第一插序转接线、四条第二插序转接线以及四条第一顺序转接线；
    所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；
    所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；
    其中，i的取值包括：1、3、7、9。
  11. 根据权利要求10所述的显示基板，其中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素；
    所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数；
    在所述第一时段，每组第一转接单元内的所述十二个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第一子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第二子像素、第三子像素、第二子像素、第三子像素、第三子像素和第一子像素；
    在所述第二时段，每组第一转接单元内的所述十二个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第二子像素、第一子像素和第三子像素，或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第一子像素、第三子像素、第一子像素、第三子像素、第三子像素和第二子像素。
  12. 根据权利要求6所述的显示基板，其中，m为16；
    每组第一转接单元包括：十六个第一连接端、十六个第二连接端、以及十六条第一转接线；所述十六个第一连接端沿所述第二方向依次排布，所述十六个第二连接端沿所述第二方向依次排布且位于所述十六个第一连接端靠近所述第一信号接入区域的一侧，所述十六条第一转接线包括四条第一插序转接线、四条第二插序转接线和八条第一顺序转接线；
    所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；
    所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；
    其中，i的取值包括：1、3、9、11。
  13. 根据权利要求12所述的显示基板，其中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素；
    所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数；
    在所述第一时段，每组第一转接单元内的所述十六个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素和第一子像素；
    在所述第二时段，每组第一转接单元内的所述十六个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素和第三子像素，或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子 像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素和第二子像素。
  14. 根据权利要求6所述的显示基板，其中，m为20；
    每组第一转接单元包括：二十个第一连接端、二十个第二连接端、以及二十条第一转接线；所述二十个第一连接端沿所述第二方向依次排布，所述二十个第二连接端沿所述第二方向依次排布且位于所述二十个第一连接端靠近所述第一信号接入区域的一侧，所述二十条第一转接线包括六条第一插序转接线、六条第二插序转接线和八条第一顺序转接线；
    所述第一插序转接线配置为连接第i个第一连接端与第i+1个第二连接端；
    所述第二插序转接线配置为连接第i+1个第一连接端与第i个第二连接端；
    其中，i的取值包括：1、3、5、11、13、15。
  15. 根据权利要求14所述的显示基板，其中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素；
    所述多个数据接触垫配置为在第一时段给所述显示区域内的第e行像素单元的子像素提供数据信号，在第二时段给所述显示区域内的第e+1行像素单元的子像素提供数据信号，其中，e为大于0的整数；
    在所述第一时段，每组第一转接单元内的所述二十个第二连接端所传输的数据信号配置为依次对应第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第二子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第一子像素、第一子像素、第三子像素、第二子像素和第三子像素；或者，配置为依次对应第一子像素、第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第二子像素、第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素和第一子像素；
    在所述第二时段，每组第一转接单元内的所述二十个第二连接端所传输的数据信号配置为依次对应第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第一子像素、第二子像素、第三子像素、第一子像素、第三子像素、第三子像素、第二子像素、第三子像素、第一子像素、第三子像素、第二子像素、第二子像素、第三子像素、第一子像素和第三子像素；或者，配置为依次对应第二子像素、第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素、第二子像素、第一子像素、第三子像素、第一子像素、第三子像素、第二子像素、第三子像素、第三子像素、第一子像素、第三子像素和第二子像素。
  16. 根据权利要求2所述的显示基板，其中，位于所述显示区域的一个像素单元包括：一个出射第一颜色光的第一子像素、一个出射第二颜色光的第二子像素、以及两个出射第三颜色光的第三子像素；
    与所述多组第一转接单元的第一连接端连接的多条数据引出线包括：第一组数据引出线和第二组数据引出线，所述第一组数据引出线和第二组数据引出线位于不同导电层，且沿所述第二方向交替设置，所述第一组数据引出线配置为传输所述第三子像素所需的数据信号，所述第二组数据引出线配置为传输所述第一子像素和所述第二子像素所需的数据信号。
  17. 根据权利要求1至16中任一项所述的显示基板，还包括：位于所述走线引出区 域且沿所述第二方向依次排布的多组测试电路；所述多组测试电路在所述第一方向上位于所述多组第一转接单元远离所述第一信号接入区域的一侧；其中，一组测试电路与一组第一转接单元所连接的m条数据引出线连接；所述第二方向与所述第一方向交叉；
    每组测试电路包括：a个第一测试电路和b个第二测试电路；a与b之和的两倍等于m，a和b均为大于0的整数；
    所述第一测试电路包括：第一测试晶体管、第二测试晶体管和第三测试晶体管；所述第一测试晶体管的栅极与第一测试控制线连接，所述第一测试晶体管的第一极与第一测试数据线连接，所述第二测试晶体管的栅极与第二测试控制线连接，所述第二测试晶体管的第一极与第二测试数据线连接，所述第一测试晶体管的第二极和所述第二测试晶体管的第二极与同一条数据引出线连接；所述第三测试晶体管的栅极与第三测试控制线连接，所述第三测试晶体管的第一极与第三测试数据线连接；
    所述第二测试电路包括：第四测试晶体管、第五测试晶体管和第六测试晶体管；所述第四测试晶体管的栅极与所述第二测试控制线连接，所述第四测试晶体管的第一极与所述第一测试数据线连接，所述第五测试晶体管的栅极与所述第一测试控制线连接，所述第五测试晶体管的第一极与所述第二测试数据线连接，所述第四测试晶体管的第二极和所述第五测试晶体管的第二极与同一条数据引出线连接；所述第六测试晶体管的栅极与所述第三测试控制线连接，所述第三测试晶体管的第一极与所述第三测试数据线连接；所述第一测试晶体管的第二极、所述第三测试晶体管的第二极、所述第四测试晶体管的第二极和所述第六测试晶体管的第二极与不同的数据引出线连接。
  18. 根据权利要求17所述的显示基板，其中，所述第一测试电路的第一测试晶体管、第二测试晶体管和第三测试晶体管沿所述第一方向排布；所述第二测试电路的第四测试晶体管、第五测试晶体管和第六测试晶体管沿所述第一方向排布；
    所述第一测试晶体管和所述第四测试晶体管在所述第二方向对齐设置，所述第二测试晶体管和所述第五测试晶体管在所述第二方向对齐设置，所述第三测试晶体管和所述第六测试晶体管在所述第二方向对齐设置。
  19. 根据权利要求17或18所述的显示基板，其中，m为8；
    每组测试电路包括：两个第一测试电路和两个第二测试电路；其中，一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向排布。
  20. 根据权利要求17或18所述的显示基板，其中，m为12；
    每组测试电路包括：三个第一测试电路和三个第二测试电路；其中，一个第一测试电路、两个第二测试电路、两个第一测试电路和一个第二测试电路沿着所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
  21. 根据权利要求17或18所述的显示基板，其中，m为16；
    每组测试电路包括：四个第一测试电路和四个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
  22. 根据权利要求17或18所述的显示基板，其中，m为20；
    每组测试电路包括：五个第一测试电路和五个第二测试电路；其中，一个第一测试电 路、两个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
  23. 根据权利要求1至22中任一项所述的显示基板，其中，所述显示区域的单个像素单元包括：c个子像素，m为c的k倍，k为大于1的整数。
  24. 一种显示装置，包括如权利要求1至23中任一项所述的显示基板。
  25. 一种显示基板，包括：
    衬底，包括：显示区域和沿第一方向位于所述显示区域一侧的第一边框区域，所述第一边框区域包括：第一信号接入区域以及位于所述第一信号接入区域和所述显示区域之间的走线引出区域；
    多个子像素，设置在所述衬底的一侧且位于所述显示区域；
    多条第一数据线、多条第二数据线以及多条数据连接线，位于所述显示区域；所述多条第一数据线和所述多条第二数据线配置为给所述多个子像素提供数据信号，所述多条第一数据线与所述多条数据连接线连接；
    多条数据引出线，位于所述走线引出区域，所述多条数据引出线与所述多条第二数据线和所述多条数据连接线连接；
    多组测试电路，位于所述走线引出区域且沿第二方向依次排布，每组测试电路与m条连续排布的数据引出线连接，所述第二方向与所述第一方向交叉；m为大于1的整数；
    每组测试电路包括：a个第一测试电路和b个第二测试电路，a和b均为大于0的整数，且a与b之和的两倍等于m；
    所述第一测试电路包括：第一测试晶体管、第二测试晶体管和第三测试晶体管；所述第一测试晶体管的栅极与第一测试控制线连接，所述第一测试晶体管的第一极与第一测试数据线连接，所述第二测试晶体管的栅极与第二测试控制线连接，所述第二测试晶体管的第一极与第二测试数据线连接，所述第一测试晶体管的第二极和所述第二测试晶体管的第二极与同一条数据引出线连接；所述第三测试晶体管的栅极与第三测试控制线连接，所述第三测试晶体管的第一极与第三测试数据线连接；
    所述第二测试电路包括：第四测试晶体管、第五测试晶体管和第六测试晶体管；所述第四测试晶体管的栅极与所述第二测试控制线连接，所述第四测试晶体管的第一极与所述第一测试数据线连接，所述第五测试晶体管的栅极与所述第一测试控制线连接，所述第五测试晶体管的第一极与所述第二测试数据线连接，所述第四测试晶体管的第二极和所述第五测试晶体管的第二极与同一条数据引出线连接；所述第六测试晶体管的栅极与所述第三测试控制线连接，所述第三测试晶体管的第一极与所述第三测试数据线连接；所述第一测试晶体管的第二极、所述第三测试晶体管的第二极、所述第四测试晶体管的第二极和所述第六测试晶体管的第二极与不同的数据引出线连接。
  26. 根据权利要求25所述的显示基板，其中，所述第一测试电路的第一测试晶体管、第二测试晶体管和第三测试晶体管沿所述第一方向排布；所述第二测试电路的第四测试晶体管、第五测试晶体管和第六测试晶体管沿所述第一方向排布；
    所述第一测试晶体管和所述第四测试晶体管在所述第二方向对齐设置，所述第二测试晶体管和所述第五测试晶体管在所述第二方向对齐设置，所述第三测试晶体管和所述第六 测试晶体管在所述第二方向对齐设置。
  27. 根据权利要求25所述的显示基板，其中，m为8；
    每组测试电路包括：两个第一测试电路和两个第二测试电路；其中，一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向排布。
  28. 根据权利要求25所述的显示基板，其中，m为12；
    每组测试电路包括：三个第一测试电路和三个第二测试电路；其中，一个第一测试电路、两个第二测试电路、两个第一测试电路和一个第二测试电路沿着所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
  29. 根据权利要求25所述的显示基板，其中，m为16；
    每组测试电路包括：四个第一测试电路和四个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
  30. 根据权利要求25所述的显示基板，其中，m为20；
    每组测试电路包括：五个第一测试电路和五个第二测试电路；其中，一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试电路、两个第一测试电路和一个第二测试电路沿所述第二方向排布；或者，一个第一测试电路、一个第二测试电路、一个第一测试电路、一个第二测试机电路、一个第一测试电路、两个第二测试电路、一个第一测试电路、一个第二测试电路和一个第一测试电路沿着所述第二方向的反方向排布。
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CN116322185A (zh) * 2023-03-21 2023-06-23 京东方科技集团股份有限公司 显示基板和显示装置
CN117337100A (zh) * 2023-09-27 2024-01-02 武汉天马微电子有限公司 显示面板及显示装置
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CN115188792A (zh) * 2022-07-15 2022-10-14 京东方科技集团股份有限公司 显示基板及显示装置
CN117479686A (zh) * 2023-03-17 2024-01-30 广州华星光电半导体显示技术有限公司 显示面板
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