WO2025212410A1

WO2025212410A1 - Light-emitting structures and methods of making and using thereof

Info

Publication number: WO2025212410A1
Application number: PCT/US2025/021973
Authority: WO
Inventors: Jung Han; Bingjun Li; Chenziyi MI; Jin-Ho Kang
Original assignee: Yale University
Current assignee: Yale University
Priority date: 2024-04-01
Filing date: 2025-03-28
Publication date: 2025-10-09
Anticipated expiration: 2026-10-01
Also published as: TW202608007A

Abstract

Various light-emitting structures, as well methods of making thereof, are described herein. Such structures, such as flip-chip vertical cavity surface emitting lasers (VCSELs), demonstrate improved thermal dissipation properties.

Description

LIGHT-EMITTING STRUCTURES AND METHODS OF MAKING AND USING

THEREOF

CROSS-REFERENCED TO RELATED APPLICATIONS

This application claims the benefit of and priority to U.S. Provisional Application No. 63/572,679, filed April 1, 2024, which is hereby incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

This invention is in the field of light-emitting structures, such as vertical cavity surface emitting lasers (VCSELs).

BACKGROUND OF THE INVENTION

Considerable research and development and commercialization effort were invested into long wavelength (LW) vertical cavity surface emitting lasers (VCSELs), LW-VCSELs, in the late 1990s and early 2000s, motivated by applications in high-bandwidth optical networks and fueled by the so called “telecom bubble”. Unfortunately, these efforts did not yield their expected results and, with the collapse of the overheated optical telecommunication market in 2001, further progress in this area stalled.

There have been different approaches to make NIR-MIR VCSELs, even with some small-scale commercialization, but none have reached the point of cost-effective mass production to-date.

The most mature VCSELs (700 nm - 1000 nm), including AlGaAs-based distributed Bragg reflector (DBR) mirrors and active regions on GaAs substrates, are prepared through well- established epitaxial growth. Moreover, AlGaAs has thermal conductivity allowing heat to dissipate through the mirrors. VCSELs, having an output power >10mW under continuous-wave (CW) operation with a power conversion efficiency above 40%, has been commercialized and been deployed in mobile application, datacom, and etc.

As the technology makes transition to short-wavelength infrared (SWIR, 1, 300-2, 400nm), the active region has to be prepared on InP substrates, which has been commercially ready for years. However, there have been no compatible epitaxial DBR mirrors for an InP substrate for more than 30 years.

It is noted that during the operation of an electrically-pumped VCSEL, a portion of electrical energy is converted into coherent light, while the rest of the electrical energy is turned into heat and is essentially wasted. Such devices can benefit from a good thermal management to address such heat dissipation issues. Thus, thermal management remains a concern. Therefore, there remains an essentially unaddressed need for VCSELs with improved thermal dissipation properties.

Therefore, it is an object of the invention to provide improved VCSEL architectures which address and overcome the thermal dissipation issues known to-date in current VCSELs.

It is yet another object of the invention to provide methods for preparing such VCSEL structures.

It is still a further object of the invention to provide methods of using such VCSEL structures.

SUMMARY OF THE INVENTION

Described herein are light-emitting structures, as well as methods of manufacturing and using thereof. In particular, such light-emitting structures have architectures which provide improved thermal dissipation properties.

In one non-limiting instance, such a light-emitting structure includes: a heat sink; a first metal contact on the heat sink; a distributed Bragg reflector mirror which is in contact with the first metal contact; an n-doped current spreading layer in contact with the distributed Bragg reflector mirror and the first metal contact; a multiple quantum well (MQW) structure; a current confinement structure which is in between the n-doped current spreading layer and the multiple quantum well (MQW) structure; wherein the current confinement structure includes an aperture region; a nanoporous distributed Bragg reflector mirror structure in contact with the multiple quantum well (MQW) structure; wherein the nanoporous distributed Bragg reflector mirror structure comprises: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10¹⁸ cm'³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer; wherein the highly n-doped semiconductor alternating layers are porous and comprise a plurality of pores; wherein the undoped or low-doped semiconductor alternating layers and the n-doped semiconductor layer are non-porous or substantially non- porous; wherein at least a region of the highly n-doped layers are non-porous or substantially non-porous; a second metal contact on the semiconductor layer, wherein the second metal contact comprises an opening over the current confinement structure; a passivation layer which contacts at least a sidewall of the nanoporous distributed Bragg reflector mirror structure and portion of the n-doped current spreading layer, the current confinement structure, and the multiple quantum well (MQW) structure; and an optional surface planarization material is in contact with the passivation layer, the first metal contact, and the heat sink.

The light-emitting structures described have an architecture which provides enhanced thermal dissipation properties. In certain instances, the light-emitting structure demonstrates a thermal resistance (R_th) of no greater than about 1.1, 1.2, 1.3, or 1.4 K/mW. In some instances, the light-emitting structure demonstrates a thermal resistance in a range of about 1.1 to 1.4 K/mW, as well as individual values or sub-ranges contained within the aforementioned range.

In some instances, the confinement structure of a non-limiting light-emitting structure contains a buried tunnel junction (BTI) and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly n-doped semiconductor has a smaller surface area than the surface area of the layer of p-doped semiconductor; wherein the n-doped current spreading layer encapsulates at least a portion of the layer of highly n-doped semiconductor; wherein the current spreading layer outside of the portion having the layer of highly n-doped semiconductor thereon contacts the highly p-doped semiconductor or the p-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect. In some other instances, the current confinement structure of a non-limiting light-emitting structure contains a laterally etched tunnel junction (TJ) and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly p-doped semiconductor and the layer of highly n- doped semiconductor both have a smaller surface area than the surface area of the layer of p-doped semiconductor and optionally have equal surface areas; wherein the n-doped current spreading layer contacts at least a surface portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

In still other instances, the confinement structure of a non-limiting light-emitting structure contains an ion implantation-based aperture region and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of p-doped semiconductor comprises an electrically conductive region surrounded by one or more electrically resistive regions and the electrically conductive region defines an aperture region within the layer of p-doped semiconductor; wherein the one or more electrically resistive regions are ion implanted regions; wherein the n-doped current spreading layer contacts at least a portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect. In one non-limiting instance, a method for making such light-emitting structure includes the steps of:

(a’) forming a bottom distributed Bragg reflector mirror structure comprising: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10¹⁸ cm'³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer;

(b’) forming a multiple quantum well (MQW) structure atop the n-doped first semiconductor layer;

(c’l forming a current confinement structure atop the multiple quantum well (MQW) structure; wherein the current confinement structure comprises an aperture region;

(d’) forming a n-doped current spreading layer atop the current confinement structure;

(e’) forming a mesa structure by etching a portion of the n-doped current spreading layer, the current confinement structure, and the MQW structure;

(f’) depositing a layer of silicon dioxide over the mesa structure, wherein at least a portion of the layer of n-doped first semiconductor is not covered by the layer of silicon dioxide;

(g’) etching the portion that is not covered by the layer of silicon dioxide to form a trench exposing a side-wall of the alternating layers of the bottom structure;

(h’) selectively porosifying the highly n-doped semiconductor layers in the alternating layers of the bottom distributed Bragg reflector mirror structure, wherein a plurality of pores are formed and wherein the undoped or low-doped semiconductor layers remain non-porous or substantially non-porous;

(i’) depositing a passivation layer to cover the trench, the side-wall, and side-walls of the mesa structure;

(j’) selectively removing the one or more materials to expose at least a portion of the mesa structure top, and optionally a portion of the n-doped first semiconductor, if covered by the one or more materials;

(k’) forming a distributed Bragg reflector mirror over the n-doped current spreading layer;

(1’) forming a first metal contact on the distributed Bragg reflector mirror; (m’) forming a second metal contact on the semiconductor layer of the bottom structure, where the second metal contact is a layer comprising an opening below the aperture region;

(n’) optionally surrounding at least a portion of the light-emitting structure with a surface planarization material;

(o’) by flip-chip bonding the light-emitting structure to a heat sink, wherein the first metal contact is contacted to the heat sink.

The various light-emitting structures, such as VCSELs, described herein can be used in various applications including electronic, photonic, and optoelectronic applications. The various light-emitting structures can be or form a part of an electronic device used for various of the aforementioned applications. Without limitation, exemplary applications can include: low-power on-chip laser sources for photonic-electronic integrated circuits; eye-safe optical sensing systems based on VCSELs and VCSEL arrays; low-cost optical links based on single-mode fiber for distances exceeding 1 km; free-space (last mile or indoor personal network) optical communication for 6G mobile and optical wireless networks; Internet of Things; low-cost light detection and ranging systems; 3D sensing; ranging; and biomedical sensing and diagnostic devices and systems.

In some instances, a plurality of the light-emitting structures described can form an array. By arranging a plurality of single-aperture, flip-chip nanoporous VCSELs, such as those described herein, into a 1 or 2-dimensional (ID or 2D) array, the output optical power can be boosted by several orders of magnitude to address the need for high-power coherent light source.

BRIEF DESCRIPTION OF THE DRAWINGS

Non- limiting embodiments are described by way of example with reference to the accompanying Figures, which are schematic and are not necessarily drawn to scale. In the Figures, each identical or nearly identical component illustrated is typically represented by a single numeral. For purposes of clarity, not every component is labeled in every figure, nor is every component shown where illustration is not necessary to allow those of ordinary skill in the art to understand the Figure(s).

Figure 1A shows a side-view illustration of a light-emitting VCSEL structure 100 including: a semiconductor layer 101 ; alternating layers of highly n-doped semiconductor, having non- porosified region(s) 102 and porosified region(s) 104 therein, and low-doped or undoped semiconductor layers 103, which are non-porous or substantially non-porous, which form a periodic stack forming a nanoporous distributed Bragg reflector mirror structure 105; an n-doped first semiconductor layer 106; a multi-quantum well (MQW) structure 107; a current confinement structure 108 which includes an aperture region 109 therein; an n-doped current spreading layer 110; a DBR mirror 111 ; a passivation layer 113 ; a sidewall trench 115 ; a top metal contact (anode) 112, which is connected to a heat sink (not shown); a second metal contact (cathode) 114.

Figure IB shows three heat flow pathways (116, 117, and 118) representing the heat dissipation flows for the VCSEL structure of Figure 1A.

Figure 2A shows a non-limiting side-view illustration of a light-emitting VCSEL structure 200, which is a flip-chip nanoporous (NP) VCSEL structure, including: a semiconductor layer 101 ; alternating layers of highly n-doped semiconductor, having non-porosified region(s) 102 and porosified region(s) 104 therein, and low-doped or undoped semiconductor layers 103, which are non-porous or substantially non-porous, which form a periodic stack forming a nanoporous distributed Bragg reflector mirror structure 105; an n-doped first semiconductor layer 106; a multiquantum well (MQW) structure 107; a current confinement structure 108 which includes an aperture region 109 therein; an n-doped current spreading layer 110; a DBR mirror 111 ; a passivation layer 113; a sidewall trench 115; a first metal contact (anode) 201 ; a second metal contact (cathode) 202 having an opening over the current confinement structure; an optional surface planarization material 203; and a heat sink 204.

Figure 2B shows four heat flow pathways (116, 117, 118, and 205) representing the heat dissipation flows for the flip-chip VCSEL structure of Figure 2A.

Figure 3 shows a non-limiting representation of a one-dimensional array containing four light-emitting VCSEL structures 200, where metal contacts 201 and 202 of all the structures are connected together, respectively.

Figure 4A shows a non-limiting side-view illustration of a current confinement structure including a buried tunnel junction (BTJ) which is between MQW structure 107 and current spreading layer 110. Layer 403 is a p-doped semiconductor, layer 402 is a highly p-doped semiconductor, layer 401 is a highly n-doped semiconductor, which has a reduced surface area. The current spreading layer 1 10 encapsulates layer 401 and includes an optional step feature 404.

Figure 4B shows a non-limiting side-view illustration of a current confinement structure including an aperture region formed by ion implantation which is between MQW structure 107 and current spreading layer 110. Layer 403 is a p-doped semiconductor, layer 402 is a highly p-doped semiconductor, and layer 401 is a highly n-doped semiconductor. Regions 405 are electrically resistive regions within layer 403 formed by ion implantation. The current spreading layer 110 includes an optional step feature 404.

Figure 4C shows a non-limiting side-view illustration of a current confinement structure including a laterally etched tunnel junction (TJ) which is between MQW structure 107 and current spreading layer 110. Layer 403 is a p-doped semiconductor, layer 402 is a highly p-doped semiconductor, and layer 401 is a highly n-doped semiconductor. Layers 401 and 402 both have reduced and equal surface areas. The current spreading layer 110 includes an optional step feature 404.

Figure 5 shows a non-limiting schematic process (a) - (h) of fabricating a light-emitting structure, such as a flip-chip VCSEL, 200.

DETAILED DESCRIPTION OF THE INVENTION

Light-emitting structures are described herein, as well as methods of manufacturing and using thereof. In particular, such light-emitting structures have architectures which provide improved thermal dissipation properties.

I. Definitions

“Porosity,” as used herein refers to the volumetric ratio of air present in a porosified medium, such as a InP, GaAs, or GaSb layer(s), which is expressed as a percentage.

“Electropolishing,” as used herein, refers to an n-doped indium phosphide or gallium arsenide being etched away completely or substantially etched away (where “substantially etched away” refers to etching greater than 95%, 96%, 97%, 98%, or 99%) leaving a void where n-doped material originally existed. The void represents the low-index medium (i.e., air). The air typically has a refractive index of about 1 .

“Refractive Index” or “Index of Refraction,” are used interchangeably and refer to the ratio of the velocity of light in a vacuum to its velocity in a specified medium, such as a layer of a InP, GaAs, or GaSb, according to the formula n = c/v, where c is the speed of light in vacuum and v is the phase velocity of light in the medium.

“Refractive Index Contrast,” as used herein refers to the relative difference in refractive index between two mediums having different indices of refraction and which are in contact and form an interface.

“Passivation Layer,” as used herein refers to a coating or film which can be applied to provide, for instance, (1) protection by acting as a barrier, protecting underlying semiconductor materials and components from various environmental factors such as moisture, humidity, chemicals, and mechanical damage; (2) electrical insulation by isolating different components or regions of the semiconductor device; and/or (3) surface smoothing of one or more surface(s) of a semiconductor device, such as for reducing surface defects.

“Surface planarization,” as used herein refers to achieving a flat and uniform surface on a semiconductor material or layer during a fabrication process. Numerical ranges include ranges of thicknesses, ranges of doping concentrations, ranges of integers, ranges of times, ranges of voltages, ranges of length, ranges of diameters, ranges of concentrations, etc. The ranges disclose individually each possible number that such a range could reasonably encompass, as well as any sub-ranges and combinations of sub-ranges encompassed therein. For example, a layer may have a thickness in the range of about 1 nm to 10 nm, where the range also discloses thicknesses that can be selected independently from about 2, 3, 4, 5, 6, 7, 8, and 9 nm, as well as any range between these numbers (for example, 3 nm to 8 nm), and any possible combination of ranges between these values.

Use of the term "about" is intended to describe values either above or below the stated value, which the term “about” modifies, in a range of approx. +/- 10%; in other instances the values may range in value either above or below the stated value in a range of approx. +/- 5%. When the term "about" is used before a range of numbers (i.e., about 1-5) or before a series of numbers (i.e., about 1, 2, 3, 4, etc.) it is intended to modify both ends of the range of numbers and/or each of the numbers recited in the entire series, unless specified otherwise.

II. Light-Emitting Structures

As noted, for light-emitting structures, such as VCSELs, a significant portion of electrical energy is wasted as heat. For example, Figure 1 A shows a side-view illustration of a light-emitting VCSEL structure 100 including: a semiconductor layer 101 ; alternating layers of highly n-doped semiconductor, having non-porosified region(s) 102 and porosified region(s) 104 therein, and low- doped or undoped semiconductor layers 103, which are non-porous or substantially non- porous, which form a periodic stack forming a nanoporous distributed Bragg reflector mirror structure 105; an n-doped first semiconductor layer 106; a multi-quantum well (MQW) structure 107; a current confinement structure 108 which includes an aperture region 109 therein; an n-doped current spreading layer 110; a DBR mirror 111; a passivation layer 113; a sidewall trench 115; a top metal contact (anode) 112, which is connected to a heat sink (not shown); a second metal contact (cathode) 1 14. For the VCSEL of Figure 1A, light emission occurs from the top surface of DBR mirror 111.

As shown in Figure IB, which is a heat flow schematic drawing of Figure 1 A, such a VCSEL structure has three heat flow pathways (labeled 116, 117, and 118) representing the heat dissipation for a VCSEL structure of Figure 1 A, where heat dissipation through the nanoporous distributed Bragg reflector mirror structure DBR (arrow 116) directly beneath the current confinement structure aperture region is significantly hindered due to poor thermal conductivity of porosified region(s) of the nanoporous distributed Bragg reflector mirror structure 105 (in Figure 1A). A minor portion of heat flows laterally first (arrow 117 in Figure IB), then flowing downward through the unporosified region(s) (102 and 103) before dissipating through region 101 and the second metal contact 114. Arrow 118 represents heat flow towards the top (first) metal contact 112. It is worth mentioning that in the VCSEL structure shown in Figure 1 A, the DBR mirror 111 is directly exposed to air for light extraction from DBR mirror 111. Air, however, is considered a good thermal insulator, and heat dissipation through DBR mirror 111 is expected to be negligible.

In order to address the thermal issues of such structures of Figure 1A, various light-emitting structures, such as flip-chip vertical cavity surface emitting lasers (VCSELs), are described herein which have architectures designed to provide improved thermal dissipation properties.

Figure 2A shows a non-limiting side-view representation of a light-emitting VCSEL structure 200, which is a flip-chip nanoporous (NP) VCSEL structure, including: a semiconductor layer 101; alternating layers of highly n-doped semiconductor, having non-porosified region(s) 102 and porosified region(s) 104 therein, and low-doped or undoped semiconductor layers 103, which are non-porous or substantially non-porous, which form a periodic stack forming a nanoporous distributed Bragg reflector mirror structure 105; an n-doped first semiconductor layer 106; a multiquantum well (MQW) structure 107; a current confinement structure 108 which includes an aperture region 109 within; an n-doped current spreading layer 110; a DBR mirror 111 ; a passivation layer 113; a sidewall trench 115; a first metal contact (anode) 201 ; a second metal contact (cathode) 202 having an opening over the current confinement structure; an optional surface planarization material 203; and a heat sink 204. For the VCSEL of Figure 2A, light emission occurs from the surface of semiconductor layer 101.

Figure 2B is a schematic drawing of the heat flow pathways for the structure shown in Figure 2A. For structures, such as shown in Figure 2A, three heat flow pathways (116, 117, 118, and 205) are expected, where heat dissipation through the nanoporous distributed Bragg reflector mirror structure 105 (arrow 116) directly over the current confinement structure aperture region occurs. A minor portion of heat flows laterally first (arrow 117 in Figure 2B), then flowing upward through the unporosified region(s) (103 and 102 in Figure 2A) before dissipating through region 101 and the metal contact 202. Arrow 1 18 represents heat flow towards the first metal contact 201 which also attaches to the sidewall and surface of DBR mirror 111 and allows heat dissipation through the mirror 111 into heat sink 204. Lastly, there is an additional pathway for heat dissipation directly through mirror 111, as represented by arrow 205, for these flip-chip VCSEL architectures. Accordingly, the light-emitting structures described herein demonstrate improved thermal dissipation properties.

For the light-emitting structures, the heat sink is made of or includes gold and/or copper. In some instances, the first (201) and the second (202) metal contacts are each independently made of or comprise a metal selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. In some instances, the first metal contacts can be chosen to strengthen the adhesion with the heatsink (204). In some instances, the thickness and pattern of the second metal contacts can be chosen to (1) enhance the thermal conductivity along pathway 118 in Figure 2B, and (2) to minimize stress incurred on top of the VCSEL aperture 109 and DBR 111. In some instances, the second metal contact is gold.

In some instances, the distributed Bragg reflector mirror includes alternating layers (i.e., pairs) of any one of a-Si/SiCE, TiCWSiCE, Ta2Os/SiO2, M^CE/SiCE, ZnSe/SiCE, a-Si/AECE, a- Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof. In some instances, the distributed Bragg reflector mirror has greater than two to less than four pairs of the any of the aforementioned alternating layers. In certain instances, there are 2.5 pairs of the alternating layers.

As noted, the light-emitting structures described have an architecture which provides enhanced thermal dissipation properties. In certain instances, the light-emitting structure demonstrates a thermal resistance (Rth) of no greater than about 1.1, 1.2, 1.3, or 1.4 K/mW. In some instances, the light-emitting structure demonstrates a thermal resistance in a range of about 1. 1 to 1.4 K/mW, as well as individual values or sub-ranges contained within the aforementioned range. Thermal resistance, expressed in units of Kelvin per milliwatt (K/mW), is a measure of the ability of the light-emitting structure, such as flip-chip VCSEL, to conduct heat away from a heat source per unit of power dissipated (in milliwatts). It quantifies how effectively the given structure can transfer heat and maintain a lower temperature for a given power input. Thermal resistance (Rth), in units of K/mW, can be defined as: AT (the temperature difference (in Kelvin) between a heat source and a heat sink) divided by P (the power dissipated (in milliwatts)). A lower thermal resistance indicates better heat conduction and dissipation properties, meaning that less temperature rise occurs for a given power input.

Details of the nanoporous DBR mirror structure, as well as methods of making thereof, are described in detail in Section IV below.

For the various layers, structures (MQW structure; DBR mirror, nanoporous DBR mirror structure, and other components (heat sink, metal contacts, materials) described above, these may have any suitable dimensions, shapes, and thicknesses suitable for their purpose and consistent with the above details. In some instances, the thicknesses are as provided in Table 1 below. Table 1. Non-limiting Thicknesses

* where the ranges also disclose sub-ranges and any particular thickness contained within the recited ranges above. a. Current Confinement Structure

The current confinement structure of the light-emitting structures described can have various designs, as discussed below. Typically, the current confinement structure defines an aperture region or zone 108.

1. Buried Tunnel Junction and Laterally Etched Tunnel Junction based Confinement Structures

In some instances, the confinement structure of a non-limiting light-emitting structure contains a buried tunnel junction (BTJ) and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly n-doped semiconductor has a smaller surface area than the surface area of the layer of p-doped semiconductor; wherein the n-doped current spreading layer encapsulates at least a portion of the layer of highly n-doped semiconductor; wherein the current spreading layer outside of the portion having the layer of highly n-doped semiconductor thereon contacts the highly p-doped semiconductor or the p-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

An exemplary non-limiting current confinement structure containing a BTJ is shown in Figure 4A. In the BTJ-based current confinement structure, a p-doped semiconductor layer 403 is in contact with the MQW structure 107; a highly p-doped semiconductor layer 402 and a highly n- doped semiconductor layer 401 are on top of layer 403, as shown. At least the layer of highly n- doped semiconductor 401 has a smaller surface area than the surface area of the layer of p-doped semiconductor 403. Optionally, the highly p-doped semiconductor layer 402 and the layer of highly n-doped second semiconductor 401 have equal areas or substantially equal areas on the layer of the p-doped semiconductor 403. The n-doped current spreading layer 110 encapsulates at least the layer of highly n-doped semiconductor. Layer 110 optionally encapsulates the layer of highly p-doped semiconductor 402 if the layer 402 has smaller surface area than p-doped semiconductor layer 403. Electrical current only flows within the reduced area of highly n-doped semiconductor layer 401. Optionally, a step feature 404 may be present/formed on the surface of current spreading layer 110 for optical confinement purposes.

As noted above, at least the layer of highly n-doped semiconductor has a smaller surface area than the surface area of the layer of highly p-doped semiconductor, where the layer of highly n-doped semiconductor occupies a smaller region or smaller surface area, as compared to the surface area of the layer of p-doped semiconductor. In some non-limiting instances, the surface area occupied by the layer of highly n-doped semiconductor may be about 1% to about 30%, as well as sub-ranges and individual values contained therein, of the total surface area of the layer of p-doped semiconductor. In some instances, the layer of highly p-doped semiconductor and the layer of highly n-doped semiconductor occupy equal areas or substantially equal areas on the layer of the p- doped semiconductor, as explained below. In still other instances, the layer of highly p-doped semiconductor and the layer of highly n-doped semiconductor occupy unequal areas on the layer of the p-doped semiconductor.

The current spreading layer, 110, encapsulates at least the layer of highly n-doped semiconductor, as shown in Figure 4A. In other instances, where the highly p-doped semiconductor layer 402 also has a reduced area, as compared to layer 403, the current spreading layer may optionally also encapsulate layer 402.

In some other instances, the current confinement structure of a non-limiting light-emitting structure contains a laterally etched tunnel junction (TJ) and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly p-doped semiconductor and the layer of highly n- doped semiconductor both have a smaller surface area than the surface area of the layer of p-doped semiconductor and optionally have equal surface areas; wherein the n-doped current spreading layer contacts at least a surface portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

An exemplary non-limiting confinement structure containing a laterally etched tunnel junction (TJ) is shown in Figures 4C. In the lateral etching of TJ structure a p-doped semiconductor layer 403 is in contact with the MQW structure 107. A highly p-doped semiconductor layer 402 and a highly n-doped semiconductor layer 401 are formed on top of layer 403. At least one of the layers

402 and 401 has a smaller surface area than the surface area of the layer of p-doped semiconductor

403 and optionally both have the same surface area, as shown. The current spreading layer 110 does not encapsulate these layers but is in contact with the surface of layer 401. As a result, injected current is confined within the reduced area of layers 401 and 402. Optionally, a step feature 404 may be present on the surface of n-doped current spreading layer 1 10 for optical confinement purposes.

For TJ-based current confinement structures, at least one of the layer of highly n-doped semiconductor or the layer of highly p-doped semiconductor, or both, has a smaller surface area than the surface area of the layer of p-doped semiconductor. In some non-limiting instances, the surface area occupied by the layer of highly n-doped or p-doped semiconductor may be about 1 % to about 30%, as well as sub-ranges and individual values contained therein, of the total surface area of the layer of p-doped semiconductor. In some instances, the layer of highly p-doped semiconductor and the layer of highly n-doped semiconductor occupy equal areas or substantially equal areas on the layer of the p-doped semiconductor, as shown in Figure 4C. In still other instances, the layer of highly p-doped semiconductor and the layer of highly n-doped semiconductor occupy unequal areas on the layer of the p-doped semiconductor.

For laterally etched TJ-based current confinement structures, the current spreading layer, 110, contacts at least a surface portion (and more typically all of the top surface) of the layer of highly n-doped semiconductor, as shown in Figure 4C. In such TJ-based structures, the current spreading layer typically does not encapsulate the highly p- or n-doped semiconductor layers. Injected current is confined within the reduced areas of the highly p- or n-doped semiconductor layers.

For the semiconductor materials forming part of the current confinement structures, such as the layers of highly p-doped and highly n-doped semiconductor, there are various doping concentrations possible. For the highly p- or n-doped layers, the p- or n- doping concentration levels may each independently have a high doping concentration level of at least about 1 x 10¹⁹ cm' ³ or higher; or in a range of between about 0.1 x 10¹⁹ cm'³ to 10 x IO²⁰ cm'³. In some cases, the high doping concentration level may be about 1 x 10¹⁹ cm'³, 2 x 10¹⁹ cm'³, 3 x 10¹⁹ cm'³, 4 x 10¹⁹ cm'³, 5 x 10¹⁹ cm'³, 6 x 10¹⁹ cm'³, 7 x 10¹⁹ cm'³, 8 x 10¹⁹ cm'³, 9 x 10¹⁹ cm'³, or 10 x 10¹⁹ cm'³. In some other instances, the highly p- or n- doped layers may each independently have a doping concentration level of greater than about 1 x 10¹⁸ cm'³ to less than 1 x 10²° cm'³, 2 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 3 x 10¹⁸ cm'³ to less than 1 x 10²° cm'³, 4 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, or 5 x 10¹⁸ cm'³ to less than 1 x 10²° cm'³. In some instances, the doped concentration level is in the range of 1 x 10¹⁹ cm'³ to less than 1 x IO²⁰ cm'³ or in the range of about 0.5 x 10¹⁹ cm'³ to 10 x 10¹⁹ cm'³. In some cases, the doping concentration level may be about 1 x 10¹⁸ cm'³, 2 x 10¹⁸ cm' ³, 3 x 10¹⁸ cm^-3, 4 x 10¹⁸ cm^-3, 5 x 10¹⁸ cm^-3, 6 x 10¹⁸ cm^-3, 7 x 10¹⁸ cm'³, 8 x 10¹⁸ cm'³, 9 x 10¹⁸ cm'³, or 10 x 10¹⁸ cm'³.

In some instances, the p- doped semiconductor layer in contact with the MQW structure can have a doping concentration level of less than about 20 x 10¹⁷ cm'³ or in the range of between about 0.5 x 10¹⁷ cm'³ to 10 x 10¹⁷ cm'³. In some cases, the low doping concentration level may be about 1 x 10¹⁷ cm'³, 2 x 10¹⁷ cm^-3, 3 x 10¹⁷ cm^-3, 4 x 10¹⁷ cm'³, 5 x 10¹⁷ cm'³, 6 x 10¹⁷ cm'³, 7 x 10¹⁷ cm'³, 8 x 10¹⁷ cm'³, 9 x 10¹⁷ cm'³, or 10 x 10¹⁷ cm'³.

For the layers of highly n-doped or highly p-doped semiconductor, these can have any suitable thickness throughout the same layer, and their reduced surface area, as described, is achieved due to the layer material being etched away completely in certain portions/regions of the respective layer.

In such instances, where the layer of highly n-doped semiconductor and the layer of highly p-doped semiconductor have equal areas or substantially equal areas, these are understood to lie on top of each other and form a bilayer stack present on the layer of the highly p-doped semiconductor. See Figure 4C. “Substantially equal,” as used herein refers to a comparison of the areas of two different layers wherein the respective areas differ by less than about 5%, 4%, 3%, 2%, 1%, or less. For current confinement structures, the p- doped and highly p- or n- doped semiconductor layers can be made of indium phosphide, gallium arsenide, or gallium antimonide and appropriately doped as described herein. In some instances, the p-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof. In some instances, the highly p-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof. In some instances, the highly n-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof.

2. Methods of Making BTJ and Lateral TJ-based Current Confinement Structures

A non-limiting method for making a current confinement structure having a buried tunnel junction (BTJ), can include the steps of:

(i) depositing a layer of a p-doped semiconductor atop the MQW structure;

(ii) depositing a layer of highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm’³, atop the layer of the p-doped semiconductor;

(iii) depositing a layer of highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm’³, a top the layer of highly p-doped semiconductor;

(iv) forming or patterning a masking material over a top surface portion of the layer of highly n-doped semiconductor;

(v) etching to remove at least the layer of highly n-doped semiconductor and optionally the highly p-doped semiconductor outside of the surface portion having the masking material thereon;

(vi) removing the masking material;

(vii) depositing an n-doped current spreading layer, which encapsulates at least a portion of the layer of highly n-doped semiconductor, and optionally a portion of the layer of highly p-doped semiconductor, and wherein the current spreading layer outside the surface portion contacts the highly p-doped semiconductor or the p- doped semiconductor layers; and

(viii) optionally forming a step feature in the n-doped current spreading layer.

In a non-limiting method for making a laterally etched tunnel junction (TJ), the method can include the steps of:

(i') depositing a layer of a p-doped semiconductor atop the MQW structure;

(ii’) depositing a layer of highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm’³, atop the layer of the p-doped semiconductor; (iii ’ ) depositing a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10^ls cm’³, a top the layer of highly p-doped semiconductor;

(iv’) forming or patterning a masking material over a top surface portion of the layer of highly n-doped semiconductor;

(v’) laterally etching to remove at least part of the layer of highly n-doped semiconductor and/or the highly p-doped semiconductor outside of the surface portion having the masking material thereon (such that at least one of the highly n- or p- doped semiconductor layers has a smaller surface area that the layer of p-doped semiconductor);

(v”) removing the masking material; and

(vi”) depositing an n-doped current spreading layer, which contacts at least a portion of the top surface of the layer of highly n-doped semiconductor, and wherein the current spreading layer does not encapsulate any of the- or p- doped semiconductor layers; and

(vii”) optionally forming a step feature in the n-doped current spreading layer.

For the layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at suitable thicknesses are known in the art.

In some instances, the masking material is, without limitation, selected from the group consisting of a dielectric (such as silicon dioxide, silicon nitride, aluminum oxide) and/or a photoresist. Such materials may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

For the methods described, patterning, etching, or removing of any materials, as needed, can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP-RIE). In some instances, in step (v’) laterally etching forms the TJ and can be achieved through wet etching by a mixture of citric acid and hydrogen peroxide. Conditions for wet etching are known, such as (Nakagawa, et al., IEEE J. Sei. Top. Quantum Electron. 7, 224-230 (2001); Asano, etal., IEEE Photonics Technology Letters, 15(10), 1333-1335 (2003). 3. Current Confinement Structure including an Aperture Region formed by Ion Implantation

In still other instances, the confinement structure of a non-limiting light-emitting structure contains an ion implantation-based aperture region and includes: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of p-doped semiconductor comprises an electrically conductive region surrounded by one or more electrically resistive regions and the electrically conductive region defines an aperture region within the layer of p-doped semiconductor; wherein the one or more electrically resistive regions are ion implanted regions; wherein the n-doped current spreading layer contacts at least a portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

An exemplary non-limiting confinement structure containing an aperture region formed by ion implantation is shown in Figure 4B. In such an ion implantation-based structure, an electrically conductive region formed of a p-doped semiconductor 403 is surrounded by a resistive region 105 formed of the ion implanted p-doped semiconductor, atop of the MQW structure 107. Region 405 is originally the p-doped semiconductor layer 403 that is converted to form the resistive region 105 through ion implantation, as detailed below. Electrical current only flows within the electrically conductive portion of layer 403. A highly p-doped semiconductor layer 402, highly n-doped second semiconductor layer 401, and the n-doped current spreading layer 110 are positioned above. Optionally, a step feature 404 can be present on the surface of layer 110 for optical confinement purposes.

For certain semiconductor materials forming part of the light emitting structure, the highly p- or n- doped semiconductor layers may each independently have a high doping concentration level of at least about 1 x 10¹⁹ cm'³ or higher; or in a range of between about 0.1 x 10¹⁹ cm'³ to 10 x IO²⁰ cm'³. In some cases, the high doping concentration level may be about 1 x 10¹⁹ cm'³, 2 x 10¹⁹ cm^-3, 3 x IO¹⁹ cm^-3, 4 x 10¹⁹ cm^-3, 5 x IO¹⁹ cm^-3, 6 x 10¹⁹ cm'³, 7 x IO¹⁹ cm'³, 8 x IO¹⁹ cm'³, 9 x 10¹⁹ cm'³, or 10 x 10¹⁹ cm'³. In some other instances, the highly p- or n- doped semiconductor layers may each independently have a doping concentration level of greater than about 1 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 2 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 3 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 4 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, or 5 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³. In some instances, the doped concentration level is in the range of 1 x 10¹⁹ cm'³ to less than 1 x IO²⁰ cm'³ or in the range of about 0.5 x 10¹⁹ cm'³ to 10 x 10¹⁹ cm'³. In some cases, the doping concentration level may be about 1 x 10¹⁸ cm'³, 2 x 10¹⁸ cm'³, 3 x 10¹⁸ cm'³, 4 x 10¹⁸ cm'³, 5 x 10¹⁸ cm'³, 6 x 10¹⁸ cm'³, 7 x 10¹⁸ cm'³, 8 x 10¹⁸ cm'³, 9 x 10¹⁸ cm'³, or 10 x 10¹⁸ cm'³.

In some instances, the p- doped semiconductor layer in contact with the MQW structure can have a doping concentration level of less than about 20 x 10¹⁷ cm'³ or in the range of between about 0.5 x 10¹⁷ cm'³ to 10 x 10¹⁷ cm'³. In some cases, the low doping concentration level may be about 1 x 10¹⁷ cm'³, 2 x 10¹⁷ cm'³, 3 x 10¹⁷ cm'³, 4 x 10¹⁷ cm'³, 5 x 10¹⁷ cm'³, 6 x 10¹⁷ cm'³, 7 x 10¹⁷ cm'³, 8 x 10¹⁷ cm'³, 9 x 10¹⁷ cm'³, or 10 x 10¹⁷ cm'³. Details of the ion implantation on portions of the p- doped semiconductor layer to render it electrically resistive are given below.

For current confinement structures, the p- doped and highly p- or n- doped semiconductor layers can be made of indium phosphide, gallium arsenide, or gallium antimonide and appropriately doped as described herein. In some instances, the p-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof. In some instances, the highly p-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof. In some instances, the highly n-doped semiconductor is formed of or includes a material selected from InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, or combinations thereof.

In some instances, the layer of ion implanted p-doped semiconductor outside the aperture region (defined by the electrically conductive region of 403) has an electrical conductivity which is about 1-4 orders of magnitude lower, as compared to within the aperture region (i.e., the electrically conductive p-doped semiconductor of 403). The choice of material which forms the layer of p- doped semiconductor should preferably be a material which when ion implanted experiences a reduction in conductivity (becomes more resistive), as compared to before ion implantation, and which does not recover or significantly recover electrical conductivity when annealed at high temperatures. “Significantly recover,” as used herein refers to a recovery of less than about 50%, less than about 40%, less than about 30%, less than about 20%, less than about 10%, less than about 5%, less than about 1% of the original electrical conductivity of the material prior to ion implantation. 4. Methods of Making Current Confinement Structures with an Ion Implantation-based Aperture Region

A non-limiting method for forming aperture region formed by ion implantation, can include the steps of:

(a) depositing a layer of a p-doped semiconductor atop the MQW structure;(b) optionally depositing a layer of highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of the p-doped semiconductor;

(c) optionally depositing a layer of a highly n-doped semiconductor, having a n- doping level greater than about 1 x 10¹⁸ cm'³, a top the layer of highly p-doped semiconductor;

(d) optionally depositing an n-doped current spreading layer, which contacts at least a portion of the top surface of the layer of highly n-doped semiconductor;

(e) forming or patterning a masking material over a region above the layer of p- doped semiconductor, or a layer(s) of (b)-(d), if present over the p-doped semiconductor layer;

(f) performing ion implantation to reduce the conductivity of at least the layer of p- doped semiconductor, which is not covered by the masking material; and

(g) removing the masking material.

In some instances, the ion implantation may reduce the electrical conductivity of other layers (such as the highly p- doped semiconductor layer, highly n- doped semiconductor layer, and/or current spreading layer) and not only of the layer of p-doped semiconductor not covered by the masking material. In such instances, it may be necessary to perform a step (h) of annealing these layer(s) to increase the electrical conductivity thereof following step (f).

For the layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at defined thicknesses are known in the art.

Regarding annealing of step (f), annealing may be performed at any suitable elevated temperature and period of time needed to increase the electrical conductivity of a layer, such as the current spreading layer, following ion implantation. In some instances, annealing restores at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or higher of the electrical conductivity of the ion implanted layer, as compared to the electrical conductivity of the layer before ion implantation. In some instances, annealing temperatures may be in a range of about 250 °C to about

450 °C, as well as sub-ranges or individual temperatures contained therein. Annealing may be applied for a time within a range of about 1 min to 1 hour or 1 min to 30 mins, as well as sub-ranges or individual times contained therein. In some instances, such as when an n-InP current spreading layer is used, the annealing temperature may be 350 °C and an annealing time of about 20 mins is applied to restore conductivity to the current spreading layer.

In some instances, the masking material of step (e) is, without limitation, selected from the group consisting of a dielectric (such as silicon dioxide, silicon nitride, aluminum oxide), a metal (such as nickel), and/or a photoresist. Such materials may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

For the methods described, patterning, etching, or removing of any materials, as needed, can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP-RIE).

5. Ion Implantation

Regarding the ion implantation of step (f), this can be performed based on the following details.

The masking material of step (e) can be formed from the materials specified above. More particularly, the masking material can be said to be an ion implant masking material which have any size, area, or shape to controllably select what area(s) of a surface are masked from the ion implant.

Such ion implant masks can be formed using several methods. Without limitation, some non-limiting examples include:

(1) Photoresist method: A layer of photoresist is spin coated onto a substrate. Then using photolithography, electron beam lithography or stamping techniques, the photoresist mask layer can be patterned into the desired shape. Based on the source of ions and ion energies used, the mask layer can vary from less than about 1 pm to greater than 10 pm, as needed.

(2) Hard mask, etching method: A hard mask layer of a material is deposited. This material can be dielectric (such as, for example, silicon dioxide or silicon nitride) or a metal, such as titanium, aluminum, etc. Based on the material, different deposition techniques can be used such as, for example, thermal evaporators, electron beam evaporators, sputters, spin coating, chemical vapor deposition, atomic layer depositions, etc. Then a layer of photoresist can be spin coated and patterned on top of the deposited hard mask layer of material. Then the hard mask layer of material can be etched away, either chemically or physically, in order to transfer the patterns from the photoresist to the underlying layer of the material. (3) Hard mask, liftoff method: Similar to the above technique (hard mask, etching method) but carried out in reverse order. First, a layer of photoresist is spin coated and then patterned. Then, a hard mask layer is deposited on top of the photoresist using one of the techniques previously described in (2). The photoresist is then etched away causing the lifting off of regions within the hard mask layer thus transferring the pattern to the hard mask layer.

In the ion implanting step, ion implants are made only in the exposed areas of layer(s) which are not masked. The ion implant ions can come from various ion sources. Many ion species and sources can be used, such as aluminum, gold, nitrogen, hydrogen, helium, carbon, oxygen, titanium, iron, to modify (i.e., damage/reduce) the electrical conductivity of the ion implanted areas or regions. In some instances, the ion may be chosen on the basis of higher atomic mass. For example, aluminum ions may be selected due to their greater atomic mass compared to hydrogen ions. The selected energy depends on the depth required of the ion implant. These energies can range from less than about 10 keV to greater than about 1 MeV to control implant at depths in a range from less than about 10 nm up to greater than about 1 pm, about 10 nm to about 750 nm, about 10 nm to about 500 nm, about 10 nm to about 250 nm, about 10 nm to about 100 nm, or any suitable subrange or individual depth value within those ranges disclosed here. The ion dosage can also be used to control the number of implanted ions and therefore the modification in the electrical conductivity. Typical ion implant dosages can range from, but not are limited to about 10¹² to 10¹⁶ cm’³, based on the ion species and desired depth. The energy of the ion implant source exposure can be used to control the depth of the ion implants made into a layer(s).

III. Methods of Making a Light-Emitting Structure

The light-emitting structures, such as flip-chip VCSELs, described above and shown in Figure 2A can be fabricated according to the methods described herein.

In one non- limiting instance, a method for making such light-emitting structure includes the steps of:

(a’) forming a bottom distributed Bragg reflector mirror structure comprising: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10¹⁸ cm’³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer;

(b’) forming a multiple quantum well (MQW) structure atop the n-doped first semiconductor layer; (c’) forming a current confinement structure atop the multiple quantum well (MQW) structure; wherein the current confinement structure comprises an aperture region;

(h’) selectively porosifying the highly n-doped semiconductor layers in the alternating layers of the bottom distributed Bragg reflector mirror structure, wherein a plurality of pores are formed and wherein the undoped or low-doped semiconductor layers remain non-porous or substantially non -porous;

(i’) depositing a passivation layer to cover the trench, the side-wall, and side-walls of the mesa structure; j’) selectively removing the one or more materials to expose at least a portion of the mesa structure top, and optionally a portion of the n-doped first semiconductor, if covered by the one or more materials;

(1’) forming a first metal contact on the distributed Bragg reflector mirror;

(m’) forming a second metal contact on the semiconductor layer of the bottom structure, where the second metal contact is a layer comprising an opening below the aperture region;

Methods for forming a bottom DBR mirror structure (and porosifying highly n-doped layers therein), forming a current confinement structure having a BTJ, laterally etched TJ, or ion implanted aperture are described in detail in Sections II and IV. Methods of forming a MQW structure are known in the art.

A non-limiting condensed example scheme for forming a light-emitting structure, according to the above method, is shown in Figure 5. First, (a) represents providing or forming a bottom DBR mirror structure (which can be porosified) having a mesa structure containing a current confinement structure, which is in between an n-doped current spreading layer and a MQW structure. The mesa structure can be formed through a wet etching or a dry etching process with a mask protecting the mesa top surface and the current spreading layer can include a step feature over the aperture region contained in the current confinement structure. The current confinement structure defines an aperture region which can be formed through i) BTJ, ii) lateral etching of a TJ, or iii) ion implantation. Next, (b) shows formation of a trench 115 through dry etching process to expose a sidewall of the bottom DBR structure at the highly n-doped semiconductor layers. Next (c) shows electrochemical etching which is performed to partially porosify the highly n-doped semiconductor layers and, consequently, turns the initial bottom DBR mirror structure into a nanoporous (NP) DBR mirror structure. Next (d) shows deposition and patterning of a passivation layer, where the passivation layer covers the sidewall of the trench and the sidewall of the mesa structure, while leaving a portion of mesa top surface uncovered. In some instances, the passivation layer 113 is made of SiO and is deposited through plasma-enhanced chemical vapor deposition (PECVD) and a photoresist is patterned on the SiCL, through a standard photolithography process, and is used as a mask for SiCL wet etching by Buffered Oxide Etch (BOE) to expose the top portion on the mesa structure. Next (e) shows formation of a (top) dielectric DBR mirror 111, as well as formation of a first metal contact layer (anode) 201. Next (f) shows a second metal contact layer (cathode) 202 was deposited and patterned on the bottom surface of the semiconductor layer of the NP DBR mirror, where the second metal contact layer (cathode) 202 includes an opening below the aperture region 109 in the current confinement structure. Next (g) shows the optional step of using a surface planarization material 203 on the structure, such that the surface is planarized, which facilitates the flip-chip bonding process which follows. Lastly (h) shows how the structure of (g) is flipped, and the first metal contact layer (anode) 201 is attached to a heat sink (i.e., Au and/or Cu) through a process of flip-chip bonding (John H. Lau, J. Electron. Package, 138(3), 030802 (2016)).

For the structures and layers formed or deposited in the methods described above, these can each be independently formed or deposited by art known deposition methods, including metal organic chemical vapor deposition (MOCVD). The selection of precursors, p- or n- dopants, and conditions for forming and doping such structures and layers at defined thicknesses are known in the art. For the methods described for preparing such light-emitting structures, patterning, etching, or removing can be performed, for example, by any suitable technique, such as wet chemical etching, plasma etching, inductively coupled plasma reactive-ion etching (ICP-RIE). In some instances of the methods, various types of photoresists are known in the art. For the methods described, the deposition of layers of silicon oxide and the one or more materials each may be formed by various methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable methods known in the art.

In some instances, the porosity formed in step (h’) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%. In some instances, step (h’) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage. In some instances, the electrolyte solution includes halide ions, hydrochloric acid (HC1), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄OH, NaCl, NaF, nitric acid (HNO₃), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

In some instances, the passivation layer includes one or more materials selected from silicon dioxide, aluminum oxide, and silicon nitride; and/or one or more materials selected from benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof.

In some instances, the surface planarization material is present and includes a material selected from benzocyclobutene (BCB), a polyimide, or combinations thereof.

In some instances, the heat sink is formed of or includes gold and/or copper. Other metals are possible. Heat sinks and suitable materials for heat sinks are known in the art.

In some instances, the flip-chip bonding in step (o’) includes forming an interconnection between the contacted first metal contact and the heat sink. In some instances, the interconnection is formed of or comprises an interconnecting or bonding material selected from the group consisting of Sn-Pb, Cu, Au, Ag, Ni, In, isotropic conductive adhesives, anisotropic conductive adhesives, and combinations thereof (see John H. Lau, J. Electron. Package, 138(3), 030802 (2016)). Isotropic conductive adhesives (TCAs) and Anisotropic conductive adhesives (ICAs) are materials used to facilitate formation of electrical connections between components. ICAs, for instance, do not require high- temperature processing and can be cured at relatively low temperatures. ICAs are typically formed of a polymer matrix filled with conductive particles (typically metal particles like silver or nickel) and the term "isotropic" refers to the fact that the adhesive can conduct electricity in all directions within the material. ACAs conduct electricity selectively in one direction but can also be formed of a polymer matrix filled with conductive particles which are aligned within the adhesive during the application process, either through pressure, heat, or a combination of both, creating a conductive pathway in a desired direction/pathway. In some instances of the methods, the first and second metal contacts formed during the above method are formed of or include one or more metals selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof. Methods for forming such metal contacts, which can be anodes or cathodes, are known to those of ordinary skill in the art.

IV. Nanoporous Distributed Bragg Reflector (DBR) Mirror Structure and Methods of Making and Porosifying Thereof

The nanoporous DBR mirror structure of the various light-emitting structures discussed above, are described in detail below.

The nanoporous DBR mirror structure includes alternating layers (i.e., pairs) of highly n- doped and undoped (or low n- doped) semiconductor layers on a semiconductor layer. A layer of an n-doped first semiconductor layer is typically present atop the alternating layers. In some instances, the semiconductor layer can be made, for example, of indium phosphide (InP), gallium arsenide (GaAs), or gallium antimonide (GaSb). Initially, these particular structures, the n-doped semiconductor layers have not yet been subjected to a selective porosifying treatment, such as by an electrochemical etching process, and remain intact.

In some instances, the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently include a binary semiconductor material selected from the group consisting of InP, GaAs, and GaSb; and wherein the alternating layers are lattice-matched to the semiconductor layer. In some other instances, the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently include a ternary semiconductor material selected from the group consisting of InAlAs and InGaAs; and wherein the alternating layers are lattice-matched to the semiconductor layer. In still other instances, the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure include a quaternary semiconductor material selected from the group consisting of InAlGaAs, TnGaAsP, and AlGaAsSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

In one instance, a non-limiting exemplary nanoporous DBR mirror structure contains a plurality of undoped or low doped semiconductor layers, which may be made of indium phosphide, gallium arsenide, or gallium antimonide layers, where at least one layer of a highly n-doped semiconductor is present between at least two layers of undoped or low doped semiconductor and can be porosified (or electropolished) due to electrochemical etching.

The nanoporous DBR structures include alternating layers of semiconductor layer on a semiconductor layer. In some instances, the semiconductor layer is chosen and a suitable semiconductor material, which is lattice-matched to the semiconductor layer, is chosen to form alternating n-doped and undoped (or low doped) semiconductor layers. For instance, the semiconductor layer of the DBR mirror structure may be made of any one of InP, GaAs, or GaSb. It is understood that the semiconductor substrate of the bottom structure and the alternating do not necessarily need to be made of the same material, but should preferably be made of lattice-matched materials, which the skilled person is able to select. The dimensions of semiconductor layer and other layer(s), whether doped or undoped (or low doped), thereon can be of any suitable dimensions, area, or shape for a specific application. In some instances, the highly n-doped semiconductor alternating layers each have identical thicknesses; and/or the undoped or low doped semiconductor alternating layers each have identical thicknesses.

Typically, the semiconductor layer and all layers thereon are of equal dimension, area, and shape. In some instances, the overall DBR mirror structure has dimensions (i.e., length and width) of or up to about 100 microns by 100 microns, as well as sub-ranges contained within.

In some instances, the alternating layers of the DBR mirror structure include or are made of a binary semiconductor material selected from, but not limited, to the group consisting of indium phosphide, gallium arsenide, and gallium antimonide, and are lattice-matched to the semiconductor substrate. In some other instances, the alternating layers of the DBR mirror structure include or are made of a ternary semiconductor material that is lattice-matched to the semiconductor substrate. In still other instances, the alternating layers of the DBR mirror structure include or are made of a quaternary semiconductor material that is lattice-matched to the semiconductor substrate.

In some instances, non-limiting examples of binary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InP, GaAs, GaSb, and AlAs. In some instances, non-limiting examples ternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlAs, InGaAs, AlGaAs, InAlP, InGaP, AlAsSb, and InAsSb. In some instances, quaternary semiconductor materials, which may be p- or n- doped, can be selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb. It is understood that the selection of any binary, ternary, or quaternary semiconductor material for use in the one or more layers, as named above, is preferably based on the semiconductor materials of the layers of a given structure being lattice-matched to the selected semiconductor substrate, which may be made of any one of InP, GaAs, or GaSb. The skilled person would be able to select the appropriate semiconductor material for each layer which is lattice-matched to the semiconductor substrate, as well as the desired doping type and doping concentration level, as detailed above.

In some instances, the semiconductor layer is formed of or includes a semiconductor material selected from the group consisting of InP, GaAs, GaSb, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof. In some instances, the n-doped first semiconductor layer is formed of or includes an n-doped semiconductor material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

In some instances, the DBR mirror structure includes at least 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, or more pairs of n-doped and undoped (or low doped) semiconductor layers which are in contact at least prior to electrochemical etching.

The person of ordinary skill in the art is familiar with methods for fabricating such a DBR mirror structure, such as by epitaxially or homoepitaxially art known methods, such as metal organic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), or liquid phase epitaxy (LPE), and using known reactants, dopants, and precursors to afford doped and undoped (or low doped) semiconductor layers.

The DBR mirror structure can be subjected to electrochemical (EC) etching conditions wherein the layers of n-doped semiconductor present are selectively porosified and a plurality of pores are formed within the n-doped semiconductor layers that are confined by and adjacent to undoped or low n-doped semiconductor layers which remain non-porous or substantially non- porous under EC conditions (where “substantially non-porous” refers to having a degree of porosity of less than 25%, 20%, 15%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low doped) layers). In some other instances, the plurality of pores are horizontally aligned (i.e., parallel) with a plane direction of the n-doped semiconductor layer.

In certain instances, the DBR mirror structure is made of a single type of doped and undoped (or low doped) semiconductor. For example, the bottom structure can made of all indium phosphide layers, all gallium arsenide layers, or all gallium antimonide layers, which alternate in doping as explained. However, mixtures of different types of materials are possible.

N-doped semiconductor layers, which are sufficiently doped, can be selectively electrochemically etched, as described below, to selectively porosify the doped semiconductor layer or to selectively electropolish (i.e., remove) the doped semiconductor layers or regions within. The undoped or low doped semiconductor layers are generally not electrochemically etched. The conditions that control the degree of porosification or that permit electropolishing are described in further detail below. Porosification and electropolishing need not remove the entirety of the n- doped semiconductor layer, where only a portion or region therein may be porosified or electropolished in a given EC process. Porosification or electropolishing forms structures which contain (air) pores or channels that can form in a horizontal direction due to selective lateral etching which proceeds from one or more side walls of the bottom structure, when EC etched. Electrochemical etching requires that n-doped semiconductor layers be doped with an n-type dopant. Accordingly, n-doped semiconductor layers, as present, are formed during deposition/formation. Exemplary dopants can include, but are not limited to, n-type Ge and Si dopants. Such dopant sources can include, for example, silane (SiFU), germane (GeH i), and isobutylgermane (IBGe). For n-type doped layers, the n-type doping concentration can be uniform across the entirety of the layer or the doping concentration may form a gradient (i.e., a layer having a graded dopant concentration across an axis of the layer, such width). The doping concentration is considered high at doping concentration levels of at least about 1 x 10¹⁹ cm'³ or higher; or is the range of between about 0.1 x 10¹⁹ cm'³ to 10 x IO²⁰ cm'³. In some cases, the high doping concentration level may be about 1 x 10¹⁹ cm'³, 2 x 10¹⁹ cm'³, 3 x 10¹⁹ cm'³, 4 x 10¹⁹ cm'³, 5 x 10¹⁹ cm'³, 6 x 10¹⁹ cm'³, 7 x 10¹⁹ cm'³, 8 x 10¹⁹ cm'³, 9 x 10¹⁹ cm'³, or 10 x 10¹⁹ cm'³. The doping concentration is considered to be moderate at doping concentration levels of greater than about 1 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 2 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 3 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, 4 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm'³, or 5 x 10¹⁸ cm'³ to less than 1 x IO²⁰ cm' ³. In some instances, the moderately doped concentration level is in the range of 1 x 10¹⁹ cm'³ to less than 1 x IO²⁰ cm'³ or in the range of about 0.5 x 10¹⁹ cm'³ to 10 x 10¹⁹ cm'³. In some cases, the moderate doping concentration level may be about 1 x 10¹⁸ cm'³, 2 x 10¹⁸ cm'³, 3 x 10¹⁸ cm'³, 4 x 10¹⁸ cm'³, 5 x 10¹⁸ cm'³, 6 x 10¹⁸ cm'³, 7 x 10¹⁸ cm'³, 8 x 10¹⁸ cm'³, 9 x 10¹⁸ cm'³, or 10 x 10¹⁸ cm'³. Moderate to high n-type doping is subject to the electrochemical etching process and results in controlled porosification and/or electropolishing of the doped layers, depending on the conditions used during the electrochemical etching process.

As noted above, the bottom structure contains layers of undoped semiconductor which are not affected (porosified or etched) when the bottom structure is electrochemically etched. In some instances, however, the bottom structure may contain layers of low doped or lowly doped semiconductor where the doping concentration is considered to be low at doping concentration levels of less than about 20 x 10¹⁷ cm'³ or in the range of between about 0.5 x 10¹⁷ cm'³ to 10 x 10¹⁷ cm'³. In some cases, the moderate doping concentration level may be about 1 x 10¹⁷ cm'³, 2 x 10¹⁷ cm'³, 3 x 10¹⁷ cm'³, 4 x 10¹⁷ cm'³, 5 x 10¹⁷ cm'³, 6 x 10¹⁷ cm'³, 7 x 10¹⁷ cm'³, 8 x 10¹⁷ cm'³, 9 x 10¹⁷ cm'³, or 10 x 10¹⁷ cm ³.

The thicknesses of any one of the n-doped or undoped (low doped) layers, prior to electrochemical etching, may each independently range in between about 50 to 500 nm (and subranges or individual thicknesses disclosed therein). In some instances, the total thickness of the bottom structure, before or after electrochemical etching, may range from between about 600 nm to about 8,000 nm or 600 nm to about 6,000 nm, and sub-ranges within. The dimensions and/or shape of the layers or semiconductor substrate may be of any suitable shape/dimension required for an application. In some instances, for the bottom structures, the n-doped semiconductor layers present within the alternating layers each have identical or substantially identical thicknesses to each other; and/or the undoped (or low doped) semiconductor layers present within the alternating layers each have identical or substantially identical thicknesses to each other. “Substantially identical,” as used herein refers to each of the particular layers, as described in the above instances, each having a thickness which differs by less than about 5%, 4%, 3%, 2%, 1%, or lower to the thickness of all the other similar layers present. It is possible for the n-doped and undoped (or low doped) semiconductor layers to have the same or different thicknesses.

Following electrochemical etching, in the DBR mirror structures the undoped or low doped semiconductor layers are typically unaffected (i.e., non-porosified or substantially non-porosified (where “substantially non-porosified” refers to having a degree of porosity of less than 25%, 20, 15%, 10%, 10%, 5%, 4%, 3%, 2%, or 1% in the undoped (or low doped) semiconductor layers). In some instances of the method, unintentional porosification of undoped (or lowly doped) semiconductor layers can occur, where even lowly n-doped semiconductor layers can be porosified during EC etching.

Following electrochemical etching, in the DBR mirror structures the n-doped semiconductor layers are porosified, as compared to prior to electrochemical etching. Porosification can be high where the layer contains at least one portion which has between about 10% and 90%, or greater porosity. In some instances, the porosity is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% or greater. Incorporation of a low index material, such as air, into layer (or portion thereof) by porosification has the effect of lowering the refractive index, as compared to the bulk semiconductor layer before porosification.

For the n-doped semiconductor layers, electrochemical etching can result in different degrees of porosities and pore morphologies by changing the type and concentration of electrolyte, n-doping concentration of the layers, and applied bias voltage, as discussed in detail below.

Electrochemical etching can be used to selectively create lateral or horizontal pores in the porosified n-doped semiconductor layers of the bottom structure. These selectively form from side surfaces of the multilayer structure. Without limitation, lateral or horizontal pores formed during the electrochemical etching process may be of any suitable length. Porosified semiconductor layers (or regions therein) contained within the multilayer structures are preferably nanoporous but may be further defined as being micro-, meso-, or macro-porous, or any combination thereof. The porosified layer or region therein may be further categorized as microporous (d < 2 nm), mesoporous (2 nm < d < 50 nm), or macroporous (d > 50 nm); where d is the average pore diameter. The morphology of the pores contained within the layer or region therein can also be classified as circular, semicircular, ellipsoidal, or a combination thereof. The pores may have an average size (i.e. , length) of between about 5 to 100 nm, 5 to 75 nm, 5 to 50 nm, or 5 to 25 nm. In some instances, the average pore size is about 5, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 nm or greater. In some instances, based on the original doping concentration, the etchant used, and the applied voltage during the electrochemical porosification process, the average size of the pores can range from between less than about 20 nm to greater than 50 nm. The spacing between any adjacent pores (which is also defines a measure of wall thickness of the pores) can range from between about 1 to 50 nm, 5 to 50 nm, 5 to 40 nm, 5 to 30 nm, 5 to 25 nm, 5 to 20 nm, 5 to 15 nm, or 5 to 10 nm.

In a given nanoporous DBR mirror structure, all or a portion of the doped semiconductor layer may be porosified during electrochemical etching. In some instances, electrochemical etching proceeds from a side wall and the extent of porosification of a layer is at least about 10, 20, 30, 40, 50, 60, 80, or 90% of the longest planar dimension of the doped layers. In some other instances, where electropolishing occurs, the extent of electropolishing of a layer is at least about 10, 20, 30, 40, 50, 60, 80, or 90% of the longest planar dimension of the doped layers. Porosification may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process. Electropolishing may occur uniformly or non-uniformly within each doped layer during the electrochemical etching process.

As noted above, in some instances the n-doped semiconductor layer is electropolished away (completely removed) which leaves little or no material between the undoped (or low doped) layers, where the doped semiconductor material used to be. The dimensions of the void space formed due to electropolishing depends on the dimensions of the doped semiconductor layer and the extent of material that was electropolished away. Electropolishing can, in some instances, create lateral or horizontal (air) pores or channels between the undoped layers where the doped material has been removed. a. Optical Properties of the Nanoporous DBR Mirror Structure

Selective incorporation of a low index material, such as air, into selected regions or layers of the DBR mirror structures by electrochemical etching has the effect of lowering the refractive index, as compared to the bulk semiconductor making up the structure. Thus, it is possible to tune the refractive index of the porosified regions within the bottom structure selectively.

For example, prior to electrochemical etching, in DBR mirror structures formed of, for example, InP each of the layers has an index of refraction of about 3.2. Electrochemical etching selectively porosifies or may completely electropolish n-doped InP layers which lowers the index of refraction below 3.2. In some instances, the index of refraction of porosified InP layers is about 1.5 to 2.7. When the InP layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (An) between the InP layers, after electrochemical etching, may be in the range of about 0. 1 to about 2. In some instances, the refractive index contrast (An) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (An) is at least about 1.5.

Prior to electrochemical etching, in DBR mirror structures formed of, for example, GaAs each of the layers has an index of refraction of about 3.95. Electrochemical etching, selectively porosifies or may completely electropolish doped InP layers which lower the index of refraction below 3.95. In some instances, the index of refraction of porosified GaAs layers is about 1.5 to 3.4. When the GaAs layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (An) between the GaAs layers, after electrochemical etching, may be in the range of about 0. 1 to about 2.5. In some instances, the refractive index contrast (An) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (An) is at least about 1.5.

Prior to electrochemical etching, in DBR mirror structures formed of GaSb each of the layers has an index of refraction of about 3.85. Electrochemical etching, selectively porosifies or may completely electropolish doped InP layers which lower the index of refraction below 3.85. In some instances, the index of refraction of porosified GaAs layers is about 1.2 to 3.4. When the GaAs layers are electropolished away the index of refraction is about 1. Consequently, the refractive index contrast (An) between the GaAs layers, after electrochemical etching, may be in the range of about 0.1 to about 2. In some instances, the refractive index contrast (An) is at least about 1.1, 1.2, 1.3, 1.4, or 1.5. In still other instances, the refractive index contrast ratio (An) is at least about 1.5.

The DBR mirror structures can act as a mirror and can demonstrate a reflectance of at least about 99%, 99.1%, 99.2%, 99.3%, 99.4%, 99.5%, 99.6%, 99.7%, 99.8%, or 99.9%. b. Methods of Electrochemically (EC) Etching the Nanoporous DBR Mirror Structures

As explained above, methods of forming the alternating layers of doped and undoped (or low doped) semiconductor layers are known in the art. Nevertheless, a non-limiting example of a method of forming a bottom structure, can include the steps of:

(a) forming a first layer of undoped or low doped semiconductor above a semiconductor layer;

(b) depositing a second layer of an n-doped semiconductor over the first layer;

(c) depositing a third layer of undoped or low doped semiconductor above the second layer; (d) optionally repeating steps (b) and (c) to form additional alternating layers of the n-doped and the undoped or low doped semiconductor.

The DBR structures, as formed, can be used in the fabrication of other structures, such the light-emitting structures described. In such processes, they can be subjected to electrochemical (EC) etching.

Electrochemical (EC) etching of n-doped semiconductor layers can be carried out in the presence of an electrolyte and under an applied bias voltage to selectively porosify or electropolish at least a portion of the n-doped semiconductor present;

Porosification and/or electropolishing which occurs during the electrochemical (EC) etching process can be controlled based on the concentration of electrolyte, doping concentration, and applied bias voltage (as discussed below). The applied bias voltage is typically a positive voltage in the range of about 0.1 to 10 V, 1.0 to 5V, or 1.0 to 2.5 V. In some instances, based on the original doping concentration and the type of etchant used, the applied bias ranges from less than about IV to at least about 10V, or greater. In some instances, porosity can be selectively minimized when lower relative doping concentrations ) are used, where in one non-limiting instance, a doping concentration of 5 x 10¹⁸ cm’³ in a sample produces a lower porosity as compared to a doping concentration of 2 x 10¹⁹ cm’³ when both are etched under the same conditions. This can be generally expected for all relative concentration differences, where the higher doping concentration will be subject to greater porosification when compared to a lower relative doping concentration, all other electrochemical etching parameters being constant. In some instances, depending on concentration of electrolyte, doping concentration, and selection of applied bias voltage applied voltage(s), electrochemical etching conditions may selectively and controllably result in only porosification (having between about 30% and 90%, or greater porosity introduced) or complete electropolishing (i.e., total or near total removal (i.e., greater than 95%, 96%, 97%, 98%, or 99% removal of doped material). The electric field direction during the EC etching process can be used to control the direction of the etching direction and thereby control the direction of the pores etched into the n-doped semiconductor layer. For example, the EC etching direction may be a function and determined by the electric field direction. The EC etching preferably produces a lateral etching direction. The rate of lateral etching can be about 0.1 pm/min, 0.2 pm/min, 0.3 pm/min, 0.4 pm/min, 0.5 pm/min, 0.6 pm/min, 0.7 pm/min, 0.8 pm/min, 0.9 pm/min, 1 pm/min, 2 pm/min, 3 pm/min, 4 pm/min, 5 pm/min, 6 pm/min, 7 pm/min, 8 pm/min, 9 pm/min, 10 pm/min, 20 pm/min, 30 pm/min, 40 pm/min, or 50 pm/min.

The EC etching can be carried out under an applied bias voltage from about 1 min to 24 hours, 1 min to 12 hours, 1 min to 6 hours, 1 min to 4 hours, 1 min to 2 hours, 1 min to 1 hour, or 1 min to 30 minutes. In some instances, the EC etching is carried out under an applied bias voltage for at least about 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, 2 hours, 3 hours, 4 hours, 5 hours, 6 hours, 10, hours, 15 hours, 20 hours, 24 hours, or greater. The EC etching can be carried out under an applied bias voltage at room temperature or at a temperature in the range of about 10 °C to about 50 °C. The EC etching can be carried out under an applied bias voltage under ambient conditions or optionally under an inert atmosphere (such as of nitrogen or argon).

The EC etching can be carried out in different types and concentrations of a high conductivity electrolyte (either salt or acid). Exemplary high conductivity electrolytes can include, but are not limited to halide ions (fluoride, chloride, bromide, iodide), hydrochloric acid (HC1), sulfuric acid (H₂SO₄), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)₂, Ca(OH)₂, Sr(OH)₂, NH₄0H, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof. The concentration of the electrolyte in the high conductivity electrolyte solutions, typically aqueous, can be in the range of between about 0.1 to 10M. In some other instances, concentration of the electrolyte in the high conductivity electrolyte solutions, typically aqueous, can be defined as a percentage (volume/volume) of the electrolyte to solvent(s), such as water, in which it is dissolved in and can be in the range of between about 0.1 to 30% by volume. In still other instances, concentration of the electrolyte in the high conductivity electrolyte solutions, typically aqueous, can be defined as a percentage (weight/volume) of the electrolyte to solvent(s), such as water, in which it is dissolved in and can be in the range of between about 0.1 to 30% by weight. The electrolytes listed above normally do not etch semiconductors, such as InP, GaAs, or GaSb, at room temperature, but can etch semiconductors, such as InP, GaAs, or GaSb, under the electrochemical anodic conditions applied.

It is believed that electrochemical etching, as described herein, proceeds from the edge of exposed sidewall(s), such as in a lateral direction to preferentially form horizontal pores. Lateral etching causes porosification producing pores, typically nanopores, to be formed horizontally or predominantly horizontally within a doped layer. The bottom structure has a vertical axis from the lowest to the top-most layer where planar layers of alternating doped and undoped (or lowly doped) semiconductor exist. When EC etching is induced, porosification of n-doped layers occurs perpendicularly or predominantly perpendicularly to the vertical axis. Predominantly perpendicular, as used herein, refers to pores that, on average, are oriented within about 20, 15, 10, or 5 degrees of the perpendicular/horizontal plane to the vertical axis. In other words, porosification occurs along or predominantly along a horizontal direction that is parallel or near parallel to the planar direction of doped layers. For the bottom structures, following electrochemical etching, there may be little, if any, pores that are vertically aligned with the vertical axis. Pores need not be aligned with the vertical axis of the bottom structure. In some instances, no vertically aligned pores are formed in the doped layers and only horizontal pores are formed during electrochemical etching. In some instances, substantially non-porosified undoped (or lowly doped) InP, GaAs, or GaSb also have nanopores formed along the [111] crystallographic direction, which are at an angle of 45 degree inclined from vertical [001] and horizontal directions. In some other instances, it may be the said that macroscopically nanopores formed in n-doped semiconductor laterally propagate during porosification, while microscopically nanopore generation can occur along a specific crystallographic directions (such as, +45°, -45° inclined from the doped layer surface).

Electrochemical etching generally consists of oxide formation and removal steps (Quill, N., et al. (2013). ECS transactions, 58(8), 25-38). It is believed that the presence of free holes at the semiconductor/electrolyte interface are important for oxidation, and oxides formed can be easily dissolved in the various electrolytes. The free holes are supplied by electric-field assisted tunneling and their amount mainly depends on anodic bias and doping concentration. In some instances, electrochemical (EC) etching conditions result in no EC etching at low anodic bias and/or low doping concentrations (low doping is described above), whereas electropolishing (i.e., complete etching) is observed at large bias and/or high n-doping concentrations. Porosification is observed at intermediate bias and/or doping concentrations.

V. Methods of Using the Light- Emitting Structures

In particular, the flip-chip nanoporous VCSELs described can provide long-wavelength emission (i.e., emitting at red, near red, or infrared wavelengths from 900 to 3000 nm, as well as subranges and individual wavelengths contained therein). In certain instances, the VCSELs described can emit at a particular wavelength or wavelength range, such as about 650 nm, about 850 nm to about 940 nm, about 1300 nm to about 1600 nm, or about 2000 nm to about 2400 nm. In some instances, the VCSELs can emit in the red wavelength range of the spectrum. VCSELs, in general, find important applications in various fields including information processing, microdisplay, pico-projection, laser headlamps, high-resolution printing, biophotonics, spectroscopic probing, and atomic clocks.

The various flip-chip VCSELs described can provide optical and electrical performance with advantages compared to more commonly used edge emitting laser diodes (EELDs), such as superior beam quality, compact form factor, low operating power, cost-effective wafer-level testing, higher yield and lower cost in manufacturing.

In some instances, the light-emitting structure is a vertical cavity surface emitting laser (VCSEL), which is flip-chip VCSEL. The VCSEL can operate at room temperature (about 25 °C) and in a continuous-wave mode.

In some other instances, the VCSEL operates at temperatures below about 0 °C, above about 25 °C, or above about 85 °C. In certain instances, the VCSEL operates in a pulse-mode. The VCSEL can emit in the infrared wavelength region, such as in the range of 1, 300-2, 400nm, as well as individual values or sub-ranges contained within the aforementioned range. In some instances, the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%. a. Arrays of Light-Emitting Structures

One single-aperture VCSEL normally may provide limited output power, on the order of milliwatts. However, applications, such as for 3D sensing and ranging, such as for mobile facial recognition and LiDARs for autonomous driving, can require a coherent light source with optical power in Watt-class and above. By arranging a plurality of single-aperture, flip-chip nanoporous VCSELs, such as those described herein, into a 1 or 2-dimensional (ID or 2D) array, the output optical power can be boosted by several orders of magnitude to address the need for high-power coherent light source. In the array, each VCSEL emitter can be controlled independently or as a whole, depending on the applications.

As shown in Figure 3, a plurality of flip-chip VCSEL structures can be combined as shown in a schematic drawing of a four-aperture array. The building block is flip-chip NP-InP VCSEL 200 and 200b, as labelled in Fig. 3. VCSEL 200 is the same as structure shown in Fig 2, while VCSEL 200R is the reverse or mirror image of VCSEL 200, having been flipped 180 degrees. When metal 202 (cathode) and metal 201 (anode) of all the devices are connected together, respectively. The four VCSELs operates simultaneously, and the total output power scales with the number of devices in the array. The number of flip-chip VCSEL structures in an array is not particularly limited. In some instances, an array (ID or 2D) may have at least two, three, four, five, six, seven, eight, nine, ten, or more VCSEL structures therein.

The disclosed structures and methods can be further understood through the following numbered paragraphs.

Paragraph 1. A light-emitting structure comprising: a heat sink; a first metal contact on the heat sink; a distributed Bragg reflector mirror which is in contact with the first metal contact; an n-doped current spreading layer in contact with the distributed Bragg reflector mirror and the first metal contact; a multiple quantum well (MQW) structure; a current confinement structure which is in between the n-doped current spreading layer and the multiple quantum well (MQW) structure; wherein the current confinement structure comprises an aperture region; a nanoporous distributed Bragg reflector mirror structure in contact with the multiple quantum well (MQW) structure; wherein the nanoporous distributed Bragg reflector mirror structure comprises: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10¹⁸ cm’³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer; wherein the highly n-doped semiconductor alternating layers are porous and comprise a plurality of pores; wherein the undoped or low-doped semiconductor alternating layers and the n-doped semiconductor layer are non-porous or substantially non- porous; wherein at least a region of the highly n-doped layers are non-porous or substantially non-porous; a second metal contact on the semiconductor layer, wherein the second metal contact comprises an opening over the current confinement structure; a passivation layer which contacts at least a sidewall of the nanoporous distributed Bragg reflector mirror structure and portion of the n-doped current spreading layer, the current confinement structure, and the multiple quantum well (MQW) structure; and an optional surface planarization material is in contact with the passivation layer, the first metal contact, and the heat sink.

Paragraph 2. The light-emitting structure of paragraph 1 , wherein the heat sink is made of or comprises gold and/or copper.

Paragraph 3. The light-emitting structure of any one of paragraphs 1-2, wherein the first and the second metal contacts are each independently made of or comprise a metal selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

Paragraph 4. The light-emitting structure of any one of paragraphs 1-3, wherein the distributed Bragg reflector mirror comprises alternating layers of any one of a-Si/SiCh. TiO SiCh, Ta Os/SiOz, M^Os/SiO , ZnSe/SiOz, a-Si/AhCh, a-Si/MgF, ZnS/MgF, a-Si/CaFz, or combinations thereof.

Paragraph 5. The light-emitting structure of any one of paragraphs 1-4, wherein the n- doped current spreading layer is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

Paragraph 6. The light-emitting structure of any one of paragraphs 1-5, wherein the semiconductor layer is formed of or comprises a semiconductor material selected from the group consisting of InP, GaAs, GaSb, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

Paragraph 7. The light-emitting structure of any one of paragraphs 1-6, wherein the n- doped first semiconductor layer is formed of or comprises an n-doped semiconductor material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

Paragraph 8. The light-emitting structure of any one of paragraphs 1-7, wherein the highly n-doped semiconductor alternating layers each have identical thicknesses; and/or the undoped or low doped semiconductor alternating layers each have identical thicknesses.

Paragraph 9. The light-emitting structure of any one of paragraphs 1-8, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently comprise a binary semiconductor material selected from the group consisting of InP, GaAs, and GaSb; and wherein the alternating layers are lattice-matched to the semiconductor layer. Paragraph 10. The light-emitting structure of any one of paragraphs 1-8, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently comprise a ternary semiconductor material selected from the group consisting of InAlAs and GaSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

Paragraph 11. The light-emitting structure of any one of paragraphs 1-8, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure comprise a quaternary semiconductor material selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

Paragraph 12. The light-emitting structure of any one of paragraphs 1-11, wherein the current confinement structure is formed of or comprises a buried tunnel junction (BTJ) comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly n-doped semiconductor has a smaller surface area than the surface area of the layer of p-doped semiconductor; wherein the n-doped current spreading layer encapsulates at least a portion of the layer of highly n-doped semiconductor; wherein the current spreading layer outside of the portion having the layer of highly n-doped semiconductor thereon contacts the highly p-doped semiconductor or the p-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

Paragraph 13. The light-emitting structure of any one of paragraphs 1-11, wherein the current confinement structure is formed of or comprises an ion implanted aperture comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of p-doped semiconductor comprises an electrically conductive region surrounded by one or more electrically resistive regions and the electrically conductive region defines an aperture region within the layer; wherein the one or more electrically resistive regions are ion implanted regions; wherein the n-doped current spreading layer contacts at least a portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

Paragraph 14. The light-emitting structure of any one of paragraphs 1-11, wherein the current confinement structure is formed of or comprises a lateral etched tunnel junction (TJ) comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly p-doped semiconductor and the layer of highly n- doped semiconductor both have a smaller surface area than the surface area of the layer of p-doped semiconductor and optionally have equal surface areas; wherein the n-doped current spreading layer contacts at least a surface portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

Paragraph 15. The light-emitting structure of any one of paragraphs 12-14, wherein the p- doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

Paragraph 16. The light-emitting structure of any one of paragraphs 12-15, wherein the highly p-doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof. Paragraph 17. The light-emitting structure of any one of paragraphs 12-16, wherein the highly n-doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

Paragraph 18. The light-emitting structure of any one of paragraphs 12-16, wherein the passivation layer is formed of or comprises a passivation material selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; and/or the passivation material comprises organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, a photoresist, and combinations thereof.

Paragraph 19. The light-emitting structure of any one of paragraphs 12-18, wherein the optional surface planarization material is present and is formed of or comprises an organic material selected from the group consisting of benzocyclobutene (BCB) and a polyimide.

Paragraph 20. The light-emitting structure of any one of paragraphs 1-19, wherein the porosity of the highly n-doped semiconductor alternating layers is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

Paragraph 21. The light-emitting structure of any one of paragraphs 1 -20, wherein a refractive index contrast (An) exists between the alternating layers which is in a range of about 0.1 to about 2 or about 0.1 to about 2.5.

Paragraph 22. The light-emitting structure of any one of paragraphs 1-21, wherein the distributed Bragg reflector mirror comprises alternating layers of any one of a-Si/SiCh, TiCh/SiCh, Ta2Os/SiO2, Nb2Os/SiO2, ZnSe/SiCb, a-Si/AhOs, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof; and there greater than two to less than four pairs of the alternating layers.

Paragraph 23. The light-emitting structure of paragraph 22, wherein there are 2.5 pairs of the alternating layers.

Paragraph 24. The light-emitting structure of any one of paragraphs 1-23, wherein the lightemitting structure demonstrates a thermal resistance of no greater than about 1.1, 1.2, 1.3, or 1.4 K/mW.

Paragraph 25. The light-emitting structure of any one of paragraphs 1-23, wherein the light- emitting structure demonstrates a thermal resistance in a range of about 1.1 to 1.4 K/mW.

Paragraph 26. The light-emitting structure of any one of paragraphs 1-25, wherein the lightemitting structure is a vertical cavity surface emitting laser (VCSEL).

Paragraph 27. The light-emitting structure of paragraph 26, wherein the vertical cavity surface emitting laser operates at room temperature (about 25 °C) and in a continuous-wave mode. Paragraph 28. The light-emitting structure of paragraph 26, wherein the vertical cavity surface emitting laser operates at temperatures below about 0 °C, above about 25 °C, or above about 85 °C.

Paragraph 29. The light-emitting structure of paragraph 26, wherein the vertical cavity surface emitting laser operates in a pulse-mode.

Paragraph 30. The light-emitting structure of paragraph 26, wherein the vertical cavity surface emitting laser emits in the infrared wavelength region.

Paragraph 31. The light-emitting structure of paragraph 26, wherein the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 7.5%, or 10%.

Paragraph 32. A method of forming a light-emitting structure comprising the steps of:

(i’) depositing a passivation layer to cover the trench, the side-wall, and side- walls of the mesa structure; j’) selectively removing the one or more materials to expose at least a portion of the mesa structure top, and optionally a portion of the n-doped first semiconductor, if covered by the one or more materials;

(1’) forming a first metal contact on the distributed Bragg reflector mirror;

(n’J optionally surrounding at least a portion of the light-emitting structure with a surface planarization material;

Paragraph 33. The method of paragraph 32, wherein the porosity formed in step (h’) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

Paragraph 34. The method of any one of paragraphs 32-33, wherein step (h’) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

Paragraph 35. The method of paragraph 34, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HC1), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

Paragraph 36. The method of any one of paragraphs 32-35, wherein the passivation layer comprises one or more materials selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; and/or one or more materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof.

Paragraph 37. The method of any one of paragraphs 32-36, wherein the surface planarization material is present and comprises a material selected from benzocyclobutene (BCB), a polyimide, or combinations thereof.

Paragraph 38. The method of any one of paragraphs 32-37, wherein the heat sink is formed of or comprises gold and/or copper. Paragraph 39. The method of any one of paragraphs 32-38, wherein the flip-chip bonding step comprises forming an interconnection between the contacted first metal contact and the heat sink.

Paragraph 40. The method of paragraph 39, wherein the interconnection is formed of or comprises an interconnecting or bonding material selected from the group consisting of Sn-Pb, Cu, Au, Ag, Ni, In, isotropic conductive adhesives, anisotropic conductive adhesives, and combinations thereof.

Paragraph 41. A light-emitting structure formed according to the method of any one of paragraphs 32-40.

Paragraph 42. An array comprising a plurality of light-emitting structures according to any one of paragraphs 1-31.

Paragraph 43. The array of paragraph 42, wherein the array is a one-dimensional array.

Paragraph 44. The array of paragraph 42, wherein the array is a two-dimensional array.

Paragraph 45. The array of any one of paragraphs 42-44, wherein each of the light-emitting structures of the array are independently controllable.

Paragraph 46. The array of any one of paragraphs 42-44, wherein the light-emitting structures of the array are controlled together.

Paragraph 47. The array of any one of paragraphs 42-46, wherein the plurality comprises at least two, three, four, five, six, seven, eight, nine, ten, or more of the light-emitting structures.

Paragraph 48. The array of any one of paragraphs 42-47, wherein the plurality of lightemitting structures of the array are all connected via the first and the second metal contacts thereon.

The present invention will be further understood by reference to the following non-limiting examples.

Example 1: Flip-Chip Vertical Cavity Surface Emitting Laser (VCSEL) Modeling

Using COMSOL Multiphysics, thermal characteristics of VCSEL structure, as shown in Figure 1 A, and flip-chip NP VCSEL structure, as shown in Figure 2A, both based on InP semiconductor materials, and gold metal contacts, were simulated and compared (each based on a 13pm aperture region). Here, it was assumed that all metal contacts are connected to a heat sink.

This study focused on examining the impact of the respective VCSEL architectures and the quantity of DBR mirror pairs on the thermal resistance. The outcomes of this analysis are presented in Table 2 below. Table 2: Simulation result of different architectures and DBR mirror design (with reflectivity >99.9%).

A typical VCSEL configuration, as shown in Figure 1 A, with a DBR mirror 111 consisting of 4~5 pairs of a-Si/SiCE, gave a thermal resistance around 1.6 K/mW, which is close to the experimentally measured value. Keeping the same design of DBR mirror 11 1, a flip-chip configuration, as shown in Figure 2A, provides an additional heat dissipation path, which lowers the thermal resistance (R_th) from 1.6 to 1.3 W/mK. Moreover, due to the high reflectivity of gold (Au), which forms the anode surrounding the DBR mirror 111, in the IR wavelength range, fewer number of pairs in DBR mirror 111 were required to achieve a > 99.9% reflectivity. By reducing to 2.5 pairs of a-Si/SiO in the DBR mirror, a thermal resistance of 1.1 K/mW was indicated by the simulation, which is close to the state-of-the-art for SWIR VCSELs which can be achieved through a wafer- fusion approach.

Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of skill in the art to which the disclosed invention belongs. Publications cited herein and the materials for which they are cited are specifically incorporated by reference.

Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention. Such equivalents are intended to be encompassed by the following claims.

Claims

We claim:

1. A light-emitting structure comprising: a heat sink; a first metal contact on the heat sink; a distributed Bragg reflector mirror which is in contact with the first metal contact; an n-doped current spreading layer in contact with the distributed Bragg reflector mirror and the first metal contact; a multiple quantum well (MQW) structure; a current confinement structure which is in between the n-doped current spreading layer and the multiple quantum well (MQW) structure; wherein the current confinement structure comprises an aperture region; a nanoporous distributed Bragg reflector mirror structure in contact with the multiple quantum well (MQW) structure; wherein the nanoporous distributed Bragg reflector mirror structure comprises: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10^ls cm’³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer; wherein the highly n-doped semiconductor alternating layers are porous and comprise a plurality of pores; wherein the undoped or low-doped semiconductor alternating layers and the n-doped semiconductor layer are non-porous or substantially non- porous; wherein at least a region of the highly n-doped layers are non-porous or substantially non-porous; a second metal contact on the semiconductor layer, wherein the second metal contact comprises an opening over the current confinement structure; a passivation layer which contacts at least a sidewall of the nanoporous distributed Bragg reflector mirror structure and portion of the n-doped current spreading layer, the current confinement structure, and the multiple quantum well (MQW) structure; and an optional surface planarization material is in contact with the passivation layer, the first metal contact, and the heat sink.

2. The light-emitting structure of claim 1 , wherein the heat sink is made of or comprises gold and/or copper.

3. The light-emitting structure of any one of claims 1-2, wherein the first and the second metal contacts are each independently made of or comprise a metal selected from the group consisting of Ti, Pt, Au, Ge, Ni, Pd, In, and combinations thereof.

4. The light-emitting structure of any one of claims 1-2, wherein the distributed Bragg reflector mirror comprises alternating layers of any one of a-Si/SiCT, TiCb/SiCh, TazOs/SiCh, NbzOs/SiCh, ZnSe/SiCh, a-Si/AbOi, a-Si/MgF, ZnS/MgF, a-Si/CaF2, or combinations thereof.

5. The light-emitting structure of any one of claims 1-2, wherein the n-doped current spreading layer is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

6. The light-emitting structure of any one of claims 1-2, wherein the semiconductor layer is formed of or comprises a semiconductor material selected from the group consisting of InP, GaAs, GaSb, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

7. The light-emitting structure of any one of claims 1-2, wherein the n-doped first semiconductor layer is formed of or comprises an n-doped semiconductor material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

8. The light-emitting structure of any one of claims 1-2, wherein the highly n-doped semiconductor alternating layers each have identical thicknesses; and/or the undoped or low doped semiconductor alternating layers each have identical thicknesses.

9. The light-emitting structure of any one of claims 1-2, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently comprise a binary semiconductor material selected from the group consisting of InP, GaAs, and GaSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

10. The light-emitting structure of any one of claims 1-2, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure each independently comprise a ternary semiconductor material selected from the group consisting of InAlAs and GaSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

11. The light-emitting structure of any one of claims 1-2, wherein the alternating layers of highly n-doped and undoped or low-doped semiconductor layers of the nanoporous distributed Bragg reflector mirror structure comprise a quaternary semiconductor material selected from the group consisting of InAlGaAs, InGaAsP, and AlGaAsSb; and wherein the alternating layers are lattice-matched to the semiconductor layer.

12. The light-emitting structure of any one of claims 1-2, wherein the current confinement structure is formed of or comprises a buried tunnel junction (BTJ) comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly n-doped semiconductor has a smaller surface area than the surface area of the layer of p-doped semiconductor; wherein the n-doped current spreading layer encapsulates at least a portion of the layer of highly n-doped semiconductor; wherein the current spreading layer outside of the portion having the layer of highly n-doped semiconductor thereon contacts the highly p-doped semiconductor or the p-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

13. The light-emitting structure of any one of claims 1-2, wherein the current confinement structure is formed of or comprises an ion implanted aperture comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of p-doped semiconductor comprises an electrically conductive region surrounded by one or more electrically resistive regions and the electrically conductive region defines an aperture region within the layer; wherein the one or more electrically resistive regions are ion implanted regions; wherein the n-doped current spreading layer contacts at least a portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

14. The light-emitting structure of any one of claims 1-2, wherein the current confinement structure is formed of or comprises a lateral etched tunnel junction (TJ) comprising: a layer of p-doped semiconductor which is in contact with the MQW structure; a layer of a highly p-doped semiconductor, having a p-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of p-doped semiconductor; a layer of a highly n-doped semiconductor, having a n-doping level greater than about 1 x 10¹⁸ cm'³, atop the layer of highly p-doped semiconductor; wherein the layer of highly p-doped semiconductor and the layer of highly n- doped semiconductor both have a smaller surface area than the surface area of the layer of p-doped semiconductor and optionally have equal surface areas; wherein the n-doped current spreading layer contacts at least a surface portion of the layer of highly n-doped semiconductor; and wherein the current spreading layer surface optionally comprises a region which is elevated and forms a step feature, which can provide an optical confinement effect.

15. The light-emitting structure of any one of claims 12-14, wherein the p-doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

16. The light-emitting structure of any one of claims 12-15, wherein the highly p-doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

17. The light-emitting structure of any one of claims 12-16, wherein the highly n-doped semiconductor is formed of or comprises a material selected from the group consisting of InP, InAlAs, InAlGaAs, InGaAsP, InGaAs, AlGaAsSb, and combinations thereof.

18. The light-emitting structure of any one of claims 12-16, wherein the passivation layer is formed of or comprises a passivation material selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; and/or the passivation material comprises organic materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, a photoresist, and combinations thereof.

19. The light-emitting structure of any one of claims 12-18, wherein the optional surface planarization material is present and is formed of or comprises an organic material selected from the group consisting of benzocyclobutene (BCB) and a polyimide.

20. The light-emitting structure of any one of claims 1-19, wherein the porosity of the highly n- doped semiconductor alternating layers is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

21. The light-emitting structure of any one of claims 1-20, wherein a refractive index contrast (An) exists between the alternating layers which is in a range of about 0.1 to about 2 or about 0.1 to about 2.5.

22. The light-emitting structure of any one of claims 1-21, wherein the distributed Bragg reflector mirror comprises alternating layers of any one of a-Si/SiOz, TiOz/SiOz, TazOs/SiOz, NbzOs/SiOz, ZnSe/SiOz, a-Si/AlzOz, a-Si/MgF, ZnS/MgF, a-Si/CaFz, or combinations thereof; and there greater than two to less than four pairs of the alternating layers.

23. The light-emitting structure of claim 22, wherein there are 2.5 pairs of the alternating layers.

24. The light-emitting structure of any one of claims 1-23, wherein the light-emitting structure demonstrates a thermal resistance of no greater than about 1.1, 1.2, 1.3, or 1.4 K/mW.

25. The light-emitting structure of any one of claims 1-23, wherein the light-emitting structure demonstrates a thermal resistance in a range of about 1.1 to 1.4 K/mW.

26. The light-emitting structure of any one of claims 1-25, wherein the light-emitting structure is a vertical cavity surface emitting laser (VCSEL).

27. The light-emitting structure of claim 26, wherein the vertical cavity surface emitting laser operates at room temperature (about 25 °C) and in a continuous-wave mode.

28. The light-emitting structure of claim 26, wherein the vertical cavity surface emitting laser operates at temperatures below about 0 °C, above about 25 °C, or above about 85 °C.

29. The light-emitting structure of claim 26, wherein the vertical cavity surface emitting laser operates in a pulse-mode.

30. The light-emitting structure of claim 26, wherein the vertical cavity surface emitting laser emits in the infrared wavelength region.

31. The light-emitting structure of claim 26, wherein the vertical cavity surface emitting laser has a power conversion efficiency of at least about 0%, 0.1 %, 0.5%, 1 %, 2%, 3%, 4%, 5%, 7.5%, or 10%.

32. A method of forming a light-emitting structure comprising the steps of:

(a’) forming a bottom distributed Bragg reflector mirror structure comprising: a semiconductor layer; an n-doped first semiconductor layer; alternating layers of highly n-doped, having a n-doping level greater than about 1 x 10^ls cm’³, and undoped or low-doped semiconductor layers in between the semiconductor layer and the n-doped semiconductor layer;

(c’) forming a current confinement structure atop the multiple quantum well (MQW) structure; wherein the current confinement structure comprises an aperture region;

(1’) forming a first metal contact on the distributed Bragg reflector mirror;

(n’) optionally surrounding at least a portion of the light-emitting structure with a surface planarization material; (o’) by flip-chip bonding the light-emitting structure to a heat sink, wherein the first metal contact is contacted to the heat sink.

33. The method of claim 32, wherein the porosity formed in step (h’) is at least about 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90%.

34. The method of any one of claims 32-33, wherein step (h’) is performed by electrochemical etching in an electrolyte solution and under an applied bias voltage.

35. The method of claim 34, wherein the electrolyte solution comprises halide ions, hydrochloric acid (HC1), sulfuric acid (H2SO4), hydrofluoric acid (HF), KOH, NaOH, Ba(OH)2, Ca(OH)2, Sr(OH)2, NH4OH, NaCl, NaF, nitric acid (HNO3), organic acids and their salts (such as oxalic acid and citric acid), and mixtures thereof.

36. The method of any one of claims 32-35, wherein the passivation layer comprises one or more materials selected from the group consisting of silicon dioxide, aluminum oxide, and silicon nitride; and/or one or more materials selected from the group consisting of benzocyclobutene (BCB), a polyimide, and a photoresist; and combinations thereof.

37. The method of any one of claims 32-36, wherein the surface planarization material is present and comprises a material selected from benzocyclobutene (BCB), a poly imide, or combinations thereof.

38. The method of any one of claims 32-37, wherein the heat sink is formed of or comprises gold and/or copper.

39. The method of any one of claims 32-38, wherein the flip-chip bonding step comprises forming an interconnection between the contacted first metal contact and the heat sink.

40. The method of claim 39, wherein the interconnection is formed of or comprises an interconnecting or bonding material selected from the group consisting of Sn-Pb, Cu, Au, Ag, Ni, In, isotropic conductive adhesives, anisotropic conductive adhesives, and combinations thereof.

41. A light-emitting structure formed according to the method of any one of claims 32-40.

42. An array comprising a plurality of light-emitting structures according to any one of claims 1-31.

43. The array of claim 42, wherein the array is a one-dimensional array.

44. The array of claim 42, wherein the array is a two-dimensional array.

45. The array of any one of claims 42-44, wherein each of the light-emitting structures of the array are independently controllable.

46. The array of any one of claims 42-44, wherein the light-emitting structures of the array are controlled together.

47. The array of any one of claims 42-46, wherein the plurality comprises at least two, three, four, five, six, seven, eight, nine, ten, or more of the light-emitting structures.

48. The array of any one of claims 42-47, wherein the plurality of light-emitting structures of the array are all connected via the first and the second metal contacts thereon.