WO2025201896A1

WO2025201896A1 - Digital-to-analog converter and corresponding method

Info

Publication number: WO2025201896A1
Application number: PCT/EP2025/056851
Authority: WO
Inventors: Sri Ram Gupta; Tarun Varma SAGIRAJU
Original assignee: Ams Osram AG
Current assignee: Ams Osram AG
Priority date: 2024-03-29
Filing date: 2025-03-13
Publication date: 2025-10-02
Anticipated expiration: 2026-09-29

Abstract

This invention relates generally to digital-to-analog converters (DACs) which convert digital input values in an analog output value. The segmented DAC comprises K DAC segments with a plurality of cells, a completely switching controller which generates K completely switching control signals and a binary switching controller. Thereby each DAC segment can be switched completely or binary, and the selection of a DAC segment that is to be switched binary depends on the input value. Advantageously, the mismatch can be reduced without increasing the required area. The invention also relates to a method to convert a digital signal to an analog signal and a driver for a light emitting diode.

Description

Digital-to-analog converter and corresponding method

DESCRIPTION

TECHNICAL FIELD

This invention relates generally to digital-to-analog converters ( DACs ) , which convert digital input values in an analog output value . It also relates to a method to convert a digital signal to an analog signal and a driver for a light emitting diode .

BACKGROUND

Digital-to-analog converters convert digital signals into analog signals . As it is known in the state of the art , there are a high number of applications , where digital-to-analog converters convert an X-bit digital word, which is also called an X-bit digital signal , into a corresponding analog signal . The number of required components , such as resistors , increases exponentially with the increase of X . Therefore , the number of elements to be fabricated on an integrated circuit chip as well as the required area is large for a high number of X .

To decrease the number of components and accordingly of the area, segmented converters are applied as a state of the art . A segmented digital-to-analog converter according to the state of the art is generally built in a way that it combines two di f ferent techniques . For the most signi ficant bits (MSB ) , the fast and high precision architecture of thermometer-coded digital-to-analog converters is applied . In the contrary, for the least signi ficant bits ( LSB ) , it uses a technique of a binary weighted DAC, where an individual electrical component is applied for each bit of the DAC and those individual components are connected to a summing point . Therefore , in a segmented DAC according to the state of the art , generally a two-stage technique is applied . In the first stage a group of higher order bits is converted . This is generally reali zed by a switching of whole segments , which include a plurality of active elements and where all active elements of a segment are switched together . In the second stage , the remaining, lower order bits are converted by applying an additional segment for the lower order bits . The technique of segmented DAC allows a signi ficant reduction of applied components and therefore also reduces the required area .

Due to the grouping of certain bits , small value changes lead to a required switching of a whole group of bits . Such a group of bits is generally arranged within one DAC segment . Due to both random and systematic mismatch of the switched bits , this may result in output variations that lead to errors of more than 1 LSB . Therefore , analog output changes may occur that are larger than 1 output unit leading to a lack of monotonicity .

An obj ective underlying the present invention is to provide a low cost and easy to manufacture DAC that provides a better performance and enhanced figures of merit , especially an enhanced monotonicity without increasing the required area of the implemented digital-to-analog converter on the integrated circuit signi ficantly .

SUMMARY

With respect to the Digital-to-analog converter ( DAC ) the obj ective is met by a segmented DAC according to claim 1 . The corresponding method is speci fied in claim 10 and the corresponding driver for a light emitting diode in claim 13 .

Accordingly, there is a segmented DAC for converting a digital input value in an analog output value indicative of the value of the digital signal . The segmented DAC comprises K DAC segments , wherein each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment . These cells are also called active elements . Thereby, each output of the DAC segments is combined into an output of the segmented DAC .

The segmented DAC further comprises a completely switching controller that is a thermometric controller, which generates K completely switching control signals and each of the completely switching control signals is coupled to one DAC segment in such a way that the DAC segments can be switched completely, i . e . they can be switched ON or OFF completely, by the completely switching controllers . The completely switching controller thus generates at least K output signals , which are the completely switching control signals . Here , K is at least two . K is the total number of DAC segments in an inventive DAC .

Here , each completely switching control signal is coupled to one of the DAC segments ; accordingly, each DAC segment can be switched completely by one completely switching control signal .

The segmented DAC additionally comprises a binary switching controller that is coupled to all DAC segments in such a way that depending on the input value one of the DAC segments is switched binary,

The completely switching controller, the binary switching controller as well as the DAC segments are thereby arranged and designed in such a way that each DAC segment can be switched completely or binary according to the input value .

That DAC segment n is to be switched binary that is to be switched ON completely for the next larger value that requires an additional DAC segment to be switched ON completely . According to the invention, the term switching can mean that a state is set , i . e . , the state can be changed or remain unchanged . Switching ON is here also understood to mean enabling a signal or switching ON a signal .

An additional cell which has been switched OFF before and that is switched ON means that the output value is increased by one , in particular by one LSB .

Switching OFF is generally also understood to mean disabling or switching OFF a signal resulting from a cell . However, an additional cell which was switched ON before that is switched OFF means that the output value is decreased by one , in particular by one LSB .

The term switching ON is also applied i f a cell is already enabled, but according to the invention switching ON is related to the final status to reali ze the corresponding output signal and it applies independent of the original status of the cell . The same applies for the term switching OFF, which is used independent of the original status of the cell as well . Switching OFF applies i f the corresponding cell or segment does not contribute to the analog output signal .

The term cell is also understood to mean active element that is used to contribute to the output signal , i f it is switched ON or enabled . In contrast a cell , which can also be called active element , that is switched OFF or disabled does not contribute to the output signal .

A DAO segment is switched completely, when all cells of this DAO segment are switched either ON or OFF, meaning all cells of the DAO segment are enabled or disabled . In contrast , a DAO segment can be switched partially, when depending on an input value a certain number of cells are switched ON, which can also be zero cells , and the residual cells are switched OFF . Here , a DAO segment that is switched partially is generally switched binary . That means the cells are divided into certain parts resembling a binary signal . The invention advantageously uses a segmentation of the cells, i.e., a grouping of the active elements is applied. As the completely switching controller and the corresponding completely switching control signals switch a DAC segment completely, the number of completely switching control signals is significantly smaller than if there was a controller required for any of the cells within the DAC segments. Accordingly, the required number of components as well as the area is smaller making this solution more efficient .

In addition, the mismatch is advantageously decreased in comparison to similar segmented DAC which use a separate binary weighted segment. For an inventive segmented DAC, the mismatch is decreased to a mismatch within one of the DAC segments, because the change of the size of one LSB results only in small changes within one of the DAC segments or in an addition of one LSB in a DAC segment. The resulting monotonicity is therefore increased. In addition, the Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) are enhanced.

The improvement of the figure of merit for these DACs is combined with only a small increase in required elements and can be applied without the requirement of large additional area .

Simulations showed the mismatch of an inventive DAC to be reduced; accordingly, the Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) that can be realized are a INL of up to 0,249 and a DNL of up to 0,052.

In comparison a segmented DAC of the state of the art with an additional binary switched DAC segment, i.e., which uses only one additional segment that can be switched binary, suffers from stronger mismatch as for certain value changes the whole binary switched DAC segment is to be switched OFF and a completely different DAC segment is to be switched ON in order to increase the value by only one LSB . Due to this disadvantage , the mismatch of a DAC with a separate binary switched DAC segment suf fers from bad INL and DNL . The simulations showed a disadvantageously high INL of 0 , 345 and an DNL of 0 , 072 .

In a preferred embodiment , there is a circuit arrangement which is coupled to the DAC segments and the thermometric controllers as well as to the binary controller, which can recombine the thermometric controllers and the binary switching controllers in such a way that a variation of the binary coded DAC segment can be reali zed . That means the DAC segment that is switched binary is varied between all DAC segments according to the input value . Accordingly, a rotation of the binary switched DAC segment is possible . That means the selection of the DAC segment that is switched binary changes from smaller to larger input values .

The terms "binary switched DAC segment" and "binary weighted DAC segment" designate certain aspects of the same DAC segment . Accordingly, a DAC segment that is binary weighted is the binary switched DAC segment according to this invention .

Preferably, every input signal is separated into M most signi ficant bits and L least signi ficant bits . The value of the most signi ficant bits (MSB ) determines the number of the DAC segments to be switched ON completely, whereby the DAC segments are preferably be switched ON thermometer-coded, i . e . they are switched ON completely consecutively from DAC segment 1 to DAC segment K starting by switching ON DAC segment 1 for an input value of 2^L up to switching all DAC segments ON for an input value 2 ^{(M+L )} -1 . Preferably, K is 2^M . The MSB signal also sets the DAC segment n that is to be switched binary . According to the invention that DAC segment n is to be switched binary that would have to be switched ON completely for the next larger value that requires an additional DAC segment to be switched ON completely . The DAC segment to be switched binary is switched according to the signal of the L least signi ficant bits ( LSB ) .

Therefore , each DAC segment can be set as switched binary and the DAC segment set as switched binary is chosen according to the input value . For each input value one DAC segment is switched binary due to the LSB signal and the residual DAC segments are thermometer coded according to the MSB signal . All DAC segments can be used as binary weighted depending on the value of the input signal .

Preferably, that DAC segment is set as switched binary which is the DAC segment to be switched ON completely at the next larger value that requires an additional DAC segment to be switched ON completely . Therefore , the error due to mismatch is reduced .

This can preferably be reali zed by an OR gate coupled to DAC segment n, which couples the thermometric signal resulting from the MSB signal of the n- 1 DAC segment and the binary weighted LSB signal . The binary weighted signal applies , i f the thermometric signal resulting from the MSB signal of DAC segment n is zero . In addition, there is a coupling of segment n to the signal of DAC segment n- 1 . The signal of segment n will only be binary switched, i f the thermometric signal resulting from the MSB signal of DAC segment n- 1 is one .

The segment n gets the information about a neighboring segment meaning about the segment n- 1 , preferably from the control of the neighboring segment meaning segment n- 1 .

Advantageously, the circuit applied ensures the DAC segments switched ON completely to be positioned next to each other and the DAC segment which is binary weighted, i . e . , that is switched binary, is positioned close to the last DAC segment that is switched ON completely . Accordingly, the mismatch is reduced drastically . In a preferred embodiment , the number of binary switching controllers as well as the number of DAC segments that are switched binary for each input value is exactly one . As an advantage , the mismatch is reduced, and the number of controllers is comparably small .

According to the invention, the binary switched DAC segment can also be switched partially but non-binary . Using the same number of controllers , the circuit has similar advantages .

Preferably, each DAC segment consists of 2^L cells , wherein L is at least two . Advantageously, there is only an L-bit mismatch . For an example where L=3 , the DAC segment consists of eight cells . Here , only seven cells are used to switch the DAC segment binary as it can be divided into parts of four cells , two cells and one cell and an additional cell will only be switched ON i f the corresponding DAC segment is switched ON completely . In general , for the binary switching of a DAC segment L²-l cells are required; as a result , for each DAC segment consisting of L² cells , only L²-l cells are applied for the binary switching, but an additional cell will only be switched ON, i f the completely switching controller and the corresponding completely switching control signal switches the whole segment ON, i . e . i f the DAC segment is switched ON completely .

Preferably, the selection of the DAC segment ( 1 ) that is switched binary is controlled by a recombination of the completely switching controller as well as the corresponding completely switching control signals and the binary switching controller .

As a result , this allows each of the DAC segments to be advantageously thermometrically switched which limits the number of completely switching controllers , which can also be referred to as thermometric controllers . Accordingly, also the completely switching control signals are limited to a number of K corresponding to the number of DAC segments . Due to the possibility to use any of the DAC segments as binary switched DAC segment , the mismatch can be reduced .

In a preferred embodiment , the recombination of the completely switching controller and the binary switching controller is reali zed by locali zed digital gates , i . e . digital gating is used meaning OR gates and AND gates are applied .

As an alternative , analog series elements can be used, i . e . analog gating is applied through series switches .

In a preferred embodiment , the completely switching controller and the binary switching controller are recombined by the application of OR gates . This is advantageously a simple and area saving way of recombination .

Preferably, one OR gate is applied for each DAC segment . Accordingly, there are K OR gates for K DAC segments . Preferably, each completely switching control signal is coupled to the binary switching controller by an OR gate . Therefore , only one OR gate per DAC segment is to be implemented .

The OR gates are preferably arranged or positioned under the DAC segment routing . As a result , the required additional area is advantageously small as the required area is not increased . The segment routing is the metal routing for segment controls from a controller to each segment and it carries thermometric controls from a controller to the segments .

The inventive segmented DAC can be reali zed as a current DAC or a voltage DAC . The invention can be applied to any kind of DAC as its principle is the switching scheme ; accordingly, di f ferent DAC cells or DAC elements can be applied .

In term of method, the invention relates to a method to convert a digital signal to an analog signal . This method applies a segmented DAC, wherein the segmented DAC comprises at least two DAC segments , wherein each DAC segment includes a plurality of cells for generating an analog output signal based on input data to each DAC segment . Preferably, the method applies a segmented DAC according to the invention . The method comprises the following steps :

• Receiving a digital input signal consisting of M Most signi ficant bit (MSB ) signal and L least signi ficant bit (LSB ) signal .

• The input signal is then split into the MSB signal and the LSB signal .

• The MSB signal ( 4 ) is afterwards modi fied to a thermometric signal ( 6 ) by a binary to thermal decoder ( 5 ) .

• The DAC segments ( 1 ) are switched completely according to the thermometric signal ( 6 ) orderly from the first DAC segment number 1 to the last DAC segment K . DAC segment number 1 is switched ON completely for a value of 2^M, while all DAC segments switched ON completely for the largest possible MSB .

• It is to be decided which DAC segment is the previous DAC segment n- 1 to the binary switched segment n . The previous segment n- 1 is thereby determined as the last of those DAC segments that are switched ON completely by the thermometric signal resulting from the MSB signal , i . e . DAC segment n- 1 is the DAC segment that is switched ON completely and has the largest number of those segments that are switched ON completely .

• The DAC segment n is binary switched according to the LSB signal . DAC segment n is preferably the DAC segment that would be switched ON completely for the next larger MSB value meaning the next larger value which would require an additional DAC segment to be switched ON completely .

• Afterwards , an analog signal is put out , for example an output voltage or an output current . The output signal is a combined output signal of all DAC segments .

The advantages of the method are a decreased mismatch . Applying this method to a segmented DAC reduces the mismatch and enhances certain figures of merit . In combination with a segmented DAC that has OR gates implemented, which are positioned under the DAC segment routing, the required area is not increased .

Preferably, an OR gate is applied to each DAC segment ( 1 ) to decide whether each DAC segment is switched ON completely or switched binary or switched OFF completely .

In term of a driver, the invention relates to a driver for a light emitting diode , which comprises a Digital-to-analog Converter according to the invention .

In summary, key elements of the invention are that the inventive segmented DAC consists of similar DAC segments . Those DAC segments are able to be switched in two di f ferent way : First , it is possible to switch these DAC segments completely, i . e . wherein the DAC segments are thermometer- coded for the most signi ficant bits . Second, each of the DAC segments can be switched binary . Using such a DAC, at least one DAC segment is switched binary and the residual segments are switched completely . The selection of the segment that is to be switched binary is dependent on the input value . To reduce the mismatch, that DAC segment is determined to be binary switched which would be the DAC segment that will be switched ON completely for the next larger input value which requires an additional DAC segment to be switched ON completely . BRIEF DESCRIPTION OF THE DRAWINGS

DETAILED DESCRIPTION

Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings.

FIG. 1 shows a working principle of a segmented DAC known in the state of the art.

FIG. 2 shows a scheme from changing the value from fifteen to sixteen for a segmented DAC known in the state of the art .

FIG. 3 shows a scheme of the inventive DAC for values from fourteen to eighteen. Here, a) shows a value of 14, b) shows a value of 15, c) shows a value of 16, d) shows a value of 17, and e) shows a value of 18.

FIG. 4 shows a scheme of the way of controlling the inventive DAC.

FIG. 5 shows a possible way of implementing a circuit to realize a DAC segment to work either binary or be switched completely.

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional, and material properties.

For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the circuits implementing a segmented DAC have not been detailed, the described embodiments being compatible with usual applications .

DETAILED DESCRIPTION

The principle of a conventional segmented DAC as it is shown in FIG . 1 is based on the segmentation of all elements into DAC segments 1 , each DAC segment 1 comprising several cells 2 . In this example three DAC segments 1 are applied as thermometric DAC segments 1A, which are completely switched DAC segments , and one DAC segment 1 is a binary weighted DAC segment IB, which can be switched partially .

The characteristic of such a segmented DAC from the state of the art is the principle to switch each of the thermometric DAC segments 1A at once . Accordingly, all cells within one of the thermometric DAC segments 1A, which are eight cells in this example , are grouped and switched together . According to the invention, the binary weighted DAC segment IB has seven cells and it is possible to switch only a few of these cells 2 ; accordingly, the binary switched DAC segment IB can be switched partially .

The input signal consisting of N bits can be separated into a number of L least Signi ficant Bits ( LSB ) and a number of M most signi ficant bits (MSB ) . The signal of the MSB is converted by a binary to thermal decoder and the resulting thermometric signal is used to switch the thermometric DAC segments 1A. In contrast the least Signi ficant Bits ( LSB ) are applied to the binary weighted DAC segment IB .

In this example , there are L=3 LSB and each thermometric DAC segment 1A consists of 2^L=8 cells 2 and therefore of eight sells 2 that can also be called active elements . The binary weighted DAC segment IB consists of seven cells 2 working as seven active elements . The binary weighted DAC segment IB is divided in three parts 3 . 1 , 3 . 2 , 3 . 3 which are always switched at once . The first part 3 . 1 is the largest and consists of four cells 2 that are always switched together . The second part 3 . 2 consists of two cells 2 that are always switched together and the third part 3 . 3 consists of only one cell 2 . The binary weighted DAC segment IB can therefore correspond to values from zero to seven cells 3 representing L=3 bits .

Due to the segmentation, there is a big disadvantage due to mismatch for the type of segmented DAC shown in FIG . 1 . The step from a value including the full seven cells 3 of the binary weighted DAC segment IB to be switched ON to the next larger value includes the switching OFF of the whole binary weighted DAC segment IB and the switching ON of a whole thermometric DAC segment 1A.

An example for the changing process from a value that includes the binary weighted DAC segment IB to be completely switched ON to the next larger value is shown in FIG . 2 . Here , the upper scheme shows a value of fi fteen and the lower scheme shows a value of sixteen in a conventional segmented DAC as known in the state of the art .

For the value of fi fteen in the upper scheme one of the thermometric DAC segments 1A is switched ON resulting in all eight cells 2 of this thermometric DAC segment 1A to be switched ON . In addition, the binary weighted DAC segment IB is switched ON completely as well , so all seven cells 2 of the binary weighted DAC segment IB are switched ON . To change the value in this scheme from fi fteen to sixteen, that is from the upper scheme to the lower scheme , the binary weighted DAC segment IB is to be switched OFF completely and an additional thermometric DAC segment 1A is to be switched ON completely . Due to mismatch, the error that occurs can be large .

The basic principle of the invention is illustrated in

FIG . 3 . The principle of the invention is to dispense with a separate binary weighted DAC segment, but to qualify each of the DAC segments 1 to be switched binary. Accordingly, certain DAC segments 1 are switched completely and preferably only one of the DAC segments is switched binary. The selection of the DAC segment 1 that is switched binary depends on the specific input value that is to be converted by the DAC .

The input value is separated in L least significant bits (LSB) and M most significant bits (MSB) . The MSB controls the number of DAC segments 1 to be switched ON completely. The process of switching a certain number of DAC segments 1 completely ON is thermometer coded. That means there is a sequence for switching ON the DAC segments 1 according to the value of the MSB.

In general, the DAC segment 1 is set to be switched binary that would be switched ON completely at the next larger input value that would require an additional DAC segment to be switched ON completely, i.e. at the next larger MSB value.

The scheme in FIG. 3 shows the process from a) the upper scheme to e) the lowest scheme from an input value of fourteen to a value of eighteen. Therefore, a) represents fourteen, b) represents fifteen, c) represents sixteen, d) represents seventeen and e) represents eighteen.

For the upper scheme the first DAC segment 1.1 is switched ON completely and the second DAC segment 1.2 is switched binary. As shown for a value of eighteen in e) of FIG. 3, the DAC segment 1 switched binary is separated in four parts 3.1, 3.2, 3.3, 3.4. This applies to every segment that is switched binary and therefore for every scheme from a) to e) . The first part 3.1 consists of four cells 2, the second part 3.2 consists of two cells 2 and the third part 3.3 consists of one cell 2. The fourth part 3.4 consisting of one cell 2 is not used for the binary switching, but is only switched ON if the DAC segment 1 is switched ON completely. In this case the adjacent DAC segment 1 is switched binary. To increase the value, the number of cells switched ON is increased. For the change from a) to b) , i.e. from fourteen to fifteen, as well as from b) to c) , i.e. from fifteen to sixteen, one additional cell 2 is switched ON in the second DAC segment 1.2. For c) , i.e. the value of sixteen, the first DAC segment 1.1 and the second DAC segment 1.2 are switched ON completely. The third DAC segment 1.3 is switched binary, but all cells 2 are switched Off for a value of zero for the LSB.

For the change from d) to e) , i.e. from the value of seventeen to the value of eighteen, the third part 3.3 of the third DAC segment 1.3 is switched OFF and the second part 3.2 of the third DAC segment 1.3 is switched ON. For the values of c) , d) and e) , i.e. the values of sixteen, seventeen and eighteen, which are shown in the three lowest schemes, the third DAC segment 1.3 is switched binary, while the first DAC segment 1.1 and the second DAC segment 1.2 are completely switched ON and the fourth DAC segment 1.4 is switched OFF completely .

The big advantage of the inventive DAC is the smaller error due to reduced mismatch. The number of cells 2 to be switched OFF for an increase of one LSB is limited to three cells 2 within the binary switched DAC segment 1.

In FIG. 4 it is shown how the principle illustrated in FIG. 3 in which all segments 1 can be controlled by both the MSB and the LSB can be implemented. All DAC segments 1 are controlled both using information of the MSB as well as of the LSB. The MSB signal 4 is converted by a binary to thermal decoder 5. Accordingly, the converted signal 6 is applied to code the thermometric switching of the DAC segments 1, i.e. the converted signal 6 selects the DAC segments 1 that are switched ON completely according to the information of the MSB. The converted signal is split into parts 6.1, 6.2, 6.3, 6.4 of the converted signal 6, so that each part 6.1, 6.2, 6.3, 6.4 controls one of the DAC segments 1. In contrast, the same binary weighted LSB signal 7 is coupled to each of the DAC segments 1. But only the DAC segment 1 that is to be switched binary, here the second segment l.n, applies the information to switch certain cells 2 according to the binary weighted LSB signal 7.

The converted signal 6 results from the MSB and controls certain segments, which are switched completely. The DAC segments 1 are switched ON in order from 1 to K, here K is four. The last DAC segment 1 to be switched ON completely by the converted signal 6 which results from the MSB is called n-1. According to the inventive principle, the adjacent DAC segment 1 is called n and is switched binary. All DAC segments 1 are coupled to the binary weighted LSB signal 7, but only the DAC segment 1 which is the one to be switched ON completely for the next larger MSB value, which is here n+1, is coded binary and is accordingly switched binary.

Advantageous, the number of controllers required for this type of switching is limited to the controllers implementing the MSB signal and which are able to switch all DAC segments 1 completely ON or OFF and an additional binary controller which applies the binary weighted LSB signal 7.

The process of selecting the binary weighted DAC segment 1, i.e., the DAC segment 1 that is to be switched binary, is visualized in FIG. 5.

The basic principle is that there are only three scenarios for each DAC segment 1. Each DAC segment 1 can either be switched ON completely, be switched OFF completely or it can be switched binary, i.e., it can be switched according to the binary weighted signal of the LSB, where a certain number of cells 2 are switched ON, i.e., they are enabled. A proposed DAC segment implementation to realize the inventive principle is shown in FIG. 5. A certain number, three in this example, of OR gates 8 are applied to each segment. In general, the number of OR gates 8 corresponds to the number L of the Least significant bits.

Advantageously, these gates can be added to the DAC segments 1 and they can be placed under the DAC segment routing; accordingly, they do not require additional area.

The implementation is explained in the following for DAC segment l.n, according to the three scenarios. For the first scenario, where the DAC segment l.n is switched ON completely, i.e. all cells are enabled, the converted signal 6.n resulting from the MSB is one. Accordingly, the resulting signal at the OR gate 8 is one independent of the binary weighted LSB signal 7. The output voltage Vx is set with the bias voltage V_o to earth 9. In addition, the converted signal 6.n-l of the previous DAC segment l.n-1, i.e., of the DAC segment number n-1 is applied. For the first scenario, this value is always one. For the first DAC segment 1.1, this value 6. n-1 is always replaced by a value of one. Each segment l.n gets the information about a neighboring segment meaning about the segment l.n-1, preferably from the control of the segment l.n-1.

For the second scenario, where the DAC segment l.n is switched OFF completely, the previous DAC segment l.n-1 was either switched OFF completely as well or it was switched binary. In both cases the converted signal 6. n-1 resulting of the MSB value of the previous DAC segment l.n-1 is zero. Accordingly, the output voltage Vx is zero independent of the result at the OR gate 8.

The third scenario describes the case of a binary switched DAC segment l.n. In this case, the converted signal 6.n resulting from the MSB is zero. Accordingly, the binary weighted signal 7 is relevant for switching the OR gate 8. In this case the converted signal 6. n-1 of the previous DAC segment l.n-1 is one. Accordingly, the output voltage Vx is affected by both the bias voltage V_o as well as the binary weighted signal 7. Accordingly, the implementation of OR gates 8 as shown in FIG . 5 quali fies each segment to be controlled either by the MSB or by the LSB according to the input value .

LIST OF REFERENCE SIGNS

DAC segment 1

Thermometric DAC segment 1A

Binary weighted DAC segment IB

First DAC segment 1.1

Second DAC segment 1.2

Third DAC segment 1.3

Fourth DAC segment 1.4

DAC segment number n l.n

Previous DAC segment l.n-1

Last DAC segment l.K

Cell 2

Part of a DAC segment 3

First part 3.1

Second part 3.2

Third part 3.3

Fourth part 3.4

Most significant bits (MSB) signal 4

Binary to thermal decoder 5

Converted signal 6

First Part of the converted signal 6.1

Second Part of the converted signal 6.2

Third Part of the converted signal 6.3

Fourth Part of the converted signal 6.4

Least significant bit (LSB) signal 7

OR gate 8

Ground 9

Bias voltage V_o

Claims

1. A segmented digital-to-analog converter, DAC, for converting a digital input value in an analog output value indicative of the value of the digital signal comprising:

• K DAC segments (1) , wherein each DAC segment includes a plurality of DAC cells (2) for generating an analog output signal based on input data to each DAC segment ( 1 ) ,

• a completely switching controller that is a thermometric controller, which generates K completely switching control signals, wherein each of the completely switching control signals is coupled to one DAC segment (1) in such a way that the DAC segments (1) can be switched completely by the completely switching control signals,

• a binary switching controller that is coupled to all DAC segments (1) in such a way that one of the DAC segments (1) is switched binary, wherein the completely switching controller, the binary switching controller as well as the DAC segments (1) are arranged and designed in such a way that each DAC segment (1) can be switched completely or binary and the selection of a DAC segment (1) that is to be switched binary depends on the input value, wherein that DAC segment (l.n) is set as switched binary which is the DAC segment (1) to be switched ON completely at the next larger value that requires an additional DAC segment (1) to be switched ON completely.

2. A segmented DAC according to claim 1, wherein the selection of the DAC segment (l.n) that is switched binary is controlled by a recombination of the completely switching controller and the binary switching controller.

3. A segmented DAC according to claim 1 or 2, wherein for every input value one of the DAC segments is switched binary according to L least significant bits and each of the residual DAC segments (1) is switched completely according to the M most significant bits.

4. A segmented DAC according to one of the claims 1 to 3, wherein each DAC segment (1) comprises 2^L cells (2) .

5. A segmented DAC according to one of the claims 1 to 4, wherein the number of binary switching controllers as well as the number of DAC segments (1) that are switched binary is exactly one.

6. A segmented DAC according to one of the claims 1 to 5, wherein the completely switching controller and the binary switching controller are recombined by the application of an OR gate ( 8 ) .

7. A segmented DAC according to claim 6, wherein one OR gate (8) is applied for each DAC segment (1) .

8. A segmented DAC according to claim 7, wherein the

OR gates (8) are arranged under the DAC segment routing.

9. A segmented DAC according to one of the claims 1 to 8, wherein the segmented DAC comprises a circuit arrangement, which is coupled to the DAC segments (1) and the completely switching controller as well as to the binary switching controller, and which can recombine the completely switching controller and the binary switching controller in such a way that a variation of the binary switched DAC segment (1) can be realized.

10. A Method to convert a digital signal to an analog signal, Applying a segmented DAC, wherein the segmented DAC comprises at least two DAC segments (1) , wherein each DAC segment (1) includes a plurality of cells (2) for generating an analog output signal based on input data to each DAC segment (1) , the method comprising: • Receiving a digital input signal consisting of M Most significant bit (MSB) signal and L least significant bit (LSB) signal,

• Splitting the digital input signal into the MSB signal and the LSB signal,

• Modifying the MSB signal (4) to a thermometric signal (6) by a binary to thermal decoder (5) ,

• Completely switching the DAC segments (1) orderly from the first DAC segment (1.1) to the last DAC segment (l.K) according to the thermometric signal ( 6 ) ,

• Deciding which DAC segment (1) is the previous DAC segment (l.n-1) to the binary switched segment (l.n) , wherein the previous segment (l.n-1) is the last of those DAC segments (1) that are switched ON completely by the thermometric signal ( 6 ) ,

• Binary Switching of the binary switched DAC segment (l.n) using the LSB signal,

• Output an analog signal which is a combined output of all DAC segments (1) .

11. Method according to claim 10, wherein that DAC segment number n (l.n) is set as switched binary, which is the DAC segment (1) to be switched ON completely at the next larger value that requires an additional DAC segment (1) to be switched ON completely.

12. Method according to claim 10 or 11, wherein an OR gate (8) is applied to each DAC segment (1) to decide whether each DAC segment (1) is switched ON completely or switched binary or switched OFF completely.

13. A driver for a light emitting diode comprising a Digital-to-analog Converter according to one of the claims 1 to 9.