WO2025201895A1

WO2025201895A1 - Pinned photodiode circuit and method for converting a light signal to a digital electronic signal

Info

Publication number: WO2025201895A1
Application number: PCT/EP2025/056850
Authority: WO
Inventors: Andrea Bonelli
Original assignee: Ams Osram AG
Current assignee: Ams Osram AG
Priority date: 2024-03-25
Filing date: 2025-03-13
Publication date: 2025-10-02
Anticipated expiration: 2026-09-25

Abstract

The invention concerns a Converter circuit (1) comprising: - A first photodiode (2) arranged in a first pixel subcircuit (10), the pixel subcircuit (10) being configured for receiving a light input signal to be converted into an output voltage signal (Vpix1) in a first operation stage and for receiving a reference signal (Vref) in to be fed through the first pixel subcircuit in a second operation stage, - A second photodiode (2') arranged in a second pixel subcircuit (10'), the pixel subcircuit (10') being configured for receiving a light input signal to be converted into an output voltage signal (Vpix2) in a first operation stage and for receiving a reference signal (Vref) in to be fed through the second pixel subcircuit in a second operation stage; - the first and the second pixel subcircuit (10, 10') being arranged side-by-side and exposed to the same light and the first and the second pixel subcircuit (10, 10') being identical in construction, and - A comparator module, connected to the first pixel subcircuit and the second pixel subcircuit to a respective output for generating an offset corrected output signal. The invention further concerns a method for such a converter.

Description

DESCRIPTION

PINNED PHOTODIODE CIRCUIT AND METHOD FOR CONVERTING A LIGHT SIGNAL TO A DIGITAL ELECTRONIC SIGNAL

TECHNICAL FIELD

The invention relates to a Pinned photodiode circuit and a method for converting a light signal into a digital electronic signal .

BACKGROUND

In the field of detection of light , photo diodes are known to the person skilled in the art for converting a light signal into an electrical signal . A photodiode is a semiconductor device . One type of photodiodes are so called Pinned photodiodes ( PPD) . Those Pinned photodiodes have a higher sensitivity for light compared to traditional n-well photodiodes or island photodiodes .

It is important to have on one hand side a good linearity of the photodiode itsel f over its full dynamic range from a very low illumination to a very high illumination and to have a low dark count , meaning electrical output signal i f there is no illumination . A low dark count reduces the noise in the signal .

Typically arrays of PPD' s are arranged in a sensor in order to compensate on one hand for a certain variation within the PPD fabrication process and on the other hand for reducing electrical noise ef fects .

Using a Pinned photodiode as a sensor for light , the Pinned photodiode ( PPD) is typically integrated into a so-called pixel subcircuit . This pixel subcircuit comprises the PPD, which is the device sensitive to light . The PPD is reset to an initial state to deplete from charges its collection region, in particular by applying a reset voltage . After the reset , the PPD is then left open/ floating to collect electron charges generated from photons of the received light . The collected charges of the PPD are then trans ferred to a Floating di f fusion ( FD) capacitance and converted in a voltage .

The design of such a Pixel subcircuit is typically optimi zed to make the FD capacitance very small to maximi ze the conversion gain in terms of voltage per electrons .

The voltage of the FD capacitance is then propagated to the next stage through a source follower ( SF) transistor . This output voltage of the pixel is thus fed into an Analog to Digital converters (ADC ) in order to convert the light input signal into a digital output signal .

One of the problems of such a pixel or such a circuit is that the SF transistors are inherently non-linear and traditional methods to compensate SF transistor nonlinearity compromises either the sensitivity or the dark count error .

In one design of a converter circuit according to the state of the art , the pixel is connected via a sampling and hold module and a buf fer to the ADC . In such a design, there is no compensation for the non-linearity of the SF transistor in the pixel . Furthermore , the buf fer induces further dark count and of fset .

The purpose of this invention is to create a circuit capable of ampli fying the signal of the Pixel to a level it can be read by the comparator of an ADC . Due to the large number of Pixels in the sensor array the ampli fier must be designed with small transistors having poor matching therefore the ampli fier has high input of fset voltage . The ampli fier should have an of fset compensation schema to get low dark counts error . It is also important that the circuit corrects for the non-linearity of the SF of the Pixel stage . As the circuit should preserve a high conversion gain of Pixel no circuitry can be added to the FD capacitance node of the Pixel .

It is an obj ect of the present invention to provide a method and a device for increasing the performance of the conversion . In particular, the method and device should be optimi zed for reducing non-linearity and/or dark count error .

SUMMARY

In accordance with an aspect of the invention a converter circuit comprises :

A first photodiode arranged in a first pixel subcircuit , the pixel subcircuit being configured for receiving a light input signal to be converted into an output voltage signal Vpixl in a first operation stage and for receiving a reference signal Vref_in to be feed through in a second operation stage ,

A second photodiode arranged in a second pixel subcircuit , the pixel subcircuit being configured for receiving a light input signal to be converted into an output voltage signal Vpix2 in a first operation stage and for receiving a reference signal Vref_in to be feed through in a second operation stage ;

The first and the second pixel subcircuit being arranged side-by-side and exposed to the same light and the first and the second pixel subcircuit being identical in construction, and

A comparation module , connected to the first pixel subcircuit and the second pixel subcircuit to a respective output for generating an of fset corrected output signal .

The combination or comparison of the pixels makes it possible to eliminate the of fset of the conversion circuit , which leads to an important reduction in the dark count error . Furthermore , the combination or comparison of the pixels makes it possible to eliminate the non-linearity of the pixel subcircuit . According to one embodiment , the first photodiode and the second photodiode are Pinned photo diodes ( PPD) . FDD' s have a high light sensitivity .

According to one embodiment , an output of the first pixel subcircuit Vpixl is ampli fied and/or converted by an analog- to-digital converter (ADC ) .

According to one embodiment , an output of the second pixel subcircuit Vpix2 is ampli fied and/or converted by an analog- to-digital converter (ADC )

According to one embodiment , the first and second pixel circuit each comprises : a capacitance , in particular a floating di f fusion capacitance a transmission gate transistor, an input switch for switching between a first and a second operation stage as well as a source follower ( SF) transistor .

The input switch is comparable with the reset switch in the state of the art . In particular, the input switch is a transistor, wherein the reset voltage or reference voltage is connected to drain . The SF transistor is in particular connected with its gate to the output or the photodiode and to the source of the input switch transistor . The SF transistor ampli fies the signal of the photodiode V_PPD and it decouples the floating di f fusion capacitor from the output of the pixel . An output of the SF transistor depends in a nonlinear manner on the signal of the photodiode V_PPD .

According to one embodiment , the circuit comprises an additional subcircuit having an output connected to the input switch, the additional subcircuit being configured for choosing a reset voltage signal as reference signal or a feed-back reference signal as input signal . In particular, the feed-back reference signal might be an output voltage of a DAC converter V_DAC - In particular, the additional switch might have a first and a second switch for selectively choosing one of the voltages .

According to one embodiment , the operation for correcting for the of fset of the converter circuit is averaging the conversion of the first pixel subcircuit with the conversion of the second pixel subcircuit .

According to one embodiment , the operation for correcting for the of fset of the converter circuit is accumulating the conversion of the first pixel subcircuit with the conversion of the second pixel subcircuit .

According to one embodiment , the comparation module comprises a comparator and optionally an ampli fier for each input signal .

According to one embodiment , the circuit further comprises a controller for conducting the following method , a first phase comprising : reset first pixel subcircuit , after resetting sampling of light and trans ferring charges to an output node of the subcircuit , initiali zation of the second pixel subcircuit , feeding an output signal of a DAC or a ramp generator of a ADC conversion signal as Vref_in into the second pixel subcircuit , such that a signal at the output node of the second subcircuit corresponds Vrefpix2 , wherein a comparator of the comparation module triggers , when the output Vrefpix2 and the output VPixl of the first pixel subcircuit are equal , wherein the trigger value is Vppdl + of fset , with Vppdl being the voltage at the gate of the SF transistor of the first pixel subcircuit , a second phase comprising : reset second pixel subcircuit , after resetting sampling of light and trans ferring charges to an output node of the subcircuit , initiali zation of the first pixel subcircuit , feeding an output signal of the DAC or a ramp generator of a ADC conversion into the first pixel subcircuit , such that a signal at the output node of the subcircuit corresponds to Vrefpixl , wherein a comparator of the comparation module triggers , when Vrefpixl and the output VPix2 of the second pixel subcircuit are equal , wherein the trigger value is Vppd2 - of fset , with Vppd2 being the voltage at the gate of the SF transistor of the second pixel subcircuit .

Thus , in the third phase the signals may be combined by accumulation

Accumulation = V (ppdl ) +of f set+V (ppd2 ) -of f set =

V (ppdl ) +V (ppd2 )

Or through averaging : Average = (V (ppdl ) +of f set+V (ppd2 ) -of f set ) /2 =

(V (ppdl ) +V (ppd2 ) ) /2

Via both operations the of fset is eliminated and the signal depends only on the output voltage of the two photodiodes .

The conversion circuit as set out above can be part of a sensor arrangement with a plurality of photodiodes , in particular with a plurality of pairs of pixel subcircuits .

In accordance with an aspect of the invention a method for converting a light signal into a digital signal , the method comprising : Converting the light signal received at a first photo diode into a first electrical signal through a first pixel subcircuit , Converting the light signal received at a second photo diode into a second electrical signal through a second pixel subcircuit , the conversion of both light signals being performed in the same manner, alternatingly reading out the first electrical signal with a second pixel reference signal and a second electrical signal with a first pixel reference signal , and combining the readout signals with each other in such a way that the offset of a conversion circuit is eliminated.

According to one embodiment, the method further comprising: Amplifying the first electrical signal, Amplifying the second electrical signal.

According to one embodiment, combining is averaging the first read-out signal to the second read-out signal.

According to one embodiment, combining is accumulating the first and second read-out signals.

According to one embodiment, combining the signals includes a transformation into a digital signal.

According to one embodiment, the method comprises: a first phase comprising: reset first pixel subcircuit, after resetting sampling of light and transferring charges to an output node of the subcircuit, initialization of the second pixel subcircuit, feeding an output signal of a DAC or a ramp generator of a ADC conversion signal as Vref_in into the second pixel subcircuit, such that a signal at the output node of the second subcircuit corresponds Vrefpix2, wherein a comparator of the comparation module triggers, when the output Vrefpix2 and the output VPixl of the first pixel subcircuit are equal, wherein the trigger value is Vppdl + offset, with Vppdl being the voltage at the gate of the SF transistor of the first pixel subcircuit, a second phase comprising: reset second pixel subcircuit, after resetting sampling of light and transferring charges to an output node of the subcircuit, initialization of the first pixel subcircuit, feeding an output signal of the DAC or a ramp generator of an ADC conversion into the first pixel subcircuit, such that a signal at the output node of the subcircuit corresponds to Vrefpixl , wherein a comparator of the comparation module triggers, when Vrefpixl and the output VPix2 of the second pixel subcircuit are equal, wherein the trigger value is Vppd2 - offset, with Vppd2 being the voltage at the gate of the SF transistor of the second pixel subcircuit.

The method according to the invention can be applied with the embodiments of the conversion circuits.

These and other features, embodiments, objectives, and advantages of the invention will become apparent from the subsequent description.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings.

FIG. 1 shows a wire diagram of a sensor circuit according to the state of the art.

FIG. 2 shows a wire diagram of a sensor circuit according to the invention.

FIG. 3 shows the wire diagram of FIG. 2 in a first phase.

FIG. 4 shows the wire diagram of FIG. 2 in a second phase.

FIG. 5 shows a block diagram of the according to the present invention .

FIG. 6 shows a block diagram of the method in the first phase .

FIG. 7 shows a block diagram of the method in the second phase . FIG . 8 shows a block diagram of the method in the third phase in a first alternative .

FIG . 9 shows a block diagram of the method in the third phase in a second alternative .

DETAILED DESCRIPTION

FIG . 1 shows a wire diagram of a sensor circuit 1 according to the state of the art . The wire diagram shows a pixel subcircuit 10 . This pixel subcircuit comprises the PPD 2 , which is the device sensitive to light . The PPD 2 is reset to an initial state , in particular by applying a reset voltage V_RST . After the reset , the PPD 2 is then left open/ floating to accumulate electron charges generated from photons of the received light . The accumulated charges of the PPD 2 are then trans ferred to a Floating di f fusion ( ED) capacitance 6 and converted in a voltage . This voltage is also called V_PPD . The design of the pixel subcircuit 10 is typically optimi zed to make the ED capacitance 6 very small to maximi ze the conversion gain in terms of voltage per electrons . The voltage of the ED capacitance 6 is then propagated to the next stage through a source follower ( SF) transistor 8 . This output voltage of the pixel 10 is thus fed through a sample and hold module 20 and a buf fer 30 into an Analog to Digital converter (ADC ) 30 in order to convert the light input signal into a digital output signal .

FIG . 2 shows a wire diagram of a sensor circuit according to the present invention . The circuit comprises a pixel 10 also called first pixel or left pixel and a second pixel 10 ' . Both pixels are subcircuits having an identical design .

This pixel subcircuit comprises a PPD 2 , which is the device sensitive to light . The PPD 2 is reset to an initial state , in particular by applying a reset voltage . For applying a reset voltage an input switch 3 is included in the pixel subcircuit , which can be switched in such a way to apply a reset or reference voltage to the pixel subcircuit . After the reset , the PPD 2 is then left open/ floating to accumulate electron charges generated from photons of the received light . The accumulated charges of the PPD 2 are then trans ferred to a Floating di f fusion ( FD) capacitance 6 and converted in a voltage .

The design of the pixel subcircuit 10 might be optimi zed to make the FD capacitance 6 very small to maximi ze the conversion gain in terms of voltage per electrons . The voltage of the FD capacitance 6 , which is Vppdl for the first pixel subcircuit and Vppd2 for the second pixel subcircuit is then propagated to the next stage through a source follower ( SF) transistor 8 .

At the input for supplying a reset voltage to each of the pixel subcircuits an additional subcircuit is connected . The additional subcircuit is configured to have a first switch 14 to feed the reset voltage V_RST through the additional subcircuit to the respective pixel subcircuit . On the other hand, the additional subcircuit has a second switch 16 to connect a reference voltage Vref_in, in particular the output of an DAC, V_DAC, to the input switch 3 of the pixel subcircuit . Thus , this subcircuit has in principle three switching stages , being no output voltage , reset voltage as output or V_DAC as output voltage . Thus , the combination of the pixel subcircuit and the additional subcircuits may be switched in such a way that an output (node ) of the pixel subcircuit is

Vp_ixl resp . Vpi_x2, if only Vppdl resp . Vppd2 is applied to the SF transistor 8 Vrefpixl resp . Vrefpix2 , i f Vref_in is applied to the pixel subcircuit , wherein Vref_in might be V_DAC .

Circuit 1 now comprises the first and the second pixel subcircuit 10 , 10 ' with their additional subcircuits 12 , 12 ' . The output of each of the pixels is connected via a respective feed switch 32 to an ADC comparator 30 . The circuit 1 might now be switched as follows :

1 ) Compare the output of the first pixel V _lxl to a reference voltage Vrefpix2 of the second pixel , which is in particular dependent on V_DAC voltage .

2 ) Compare the output of the second pixel V_Plx2 to a reference voltage Vrefpixl of the first pixel , which is in particular dependent on V_DAC voltage .

3 ) Compare the output of the first pixel V _lxl to the output of the second pixel V _lx2

4 ) Compare a reference voltage of the second pixel Vrefpix2 to a reference voltage of the first pixel Vrefpixl .

In accordance with the present invention, the first two options are the interesting ones .

Thus , the comparator 30 is integrated into the circuit to compare outputs of a first side with the output of the second side .

To facilitate the understanding, the schematic block diagram in FIG . 5 j ust shows the respective pixel subcircuits 10 , 10 ' . The first subcircuit 10 is connected with an input the additional subcircuit 12 . The first subcircuit 10 may feed either Vpixl or Vrefpixl into the comparator 30 . The additional subcircuit 12 may receive a Vref_in signal from the comparator 30 as a feed-back signal . On the other side of the comparator 30 , there is the second subcircuit 10 ' , which is connected with an input the additional subcircuit 12 ' . The second subcircuit 10 ' may feed either Vpix2 or Vrefpix2 into the comparator 30 . The additional subcircuit 12 ' may receive a Vref_in signal from the comparator 30 as a feed-back signal .

The switching possibilities are now set out in more detail with reference to FIG . 3 and 4 .

FIG . 3 and FIG . 6 show a first phase . In this switch, the signal of the first or left pixel is collected normally . The first phase comprises : reset first pixel subcircuit S101.

Therefore, the reset voltage V_RST is fed into the first pixel subcircuit 10 via switches 3 and 14. after resetting, sampling of light, and transferring charges to an output node of the subcircuit, S102.

Thus, Vppdl is applied to the gate of the SF transistor 8 and the output voltage of the first subcircuit is VPixl initialization of the second pixel subcircuit S103, and subsequent feeding of an output signal of the DAC or a ramp generator of an ADC conversion into the second pixel subcircuit S104, therefore V_DAC as Vref_in is fed via switch 16 into the second pixel subcircuit 10 to obtain Vrefpix2.

The comparator triggers S105, when VPixl is equal to Vrefpix2, which is the case when V_DAC and the voltage VPPD1 are equal, Thus the trigger value is Vppdl + offset.

FIG. 4 shows a second phase. In this switch, the signal of the second or right pixel is collected normally.

The second phase comprises: reset second pixel subcircuit S201, Therefore, the reset voltage V_RST is fed into the second pixel subcircuit 10 via switches 3 and 14. after resetting sampling of light and transferring charges to an output node of the subcircuit S202

Thus, Vppd2 is applied to the gate of the SF transistor 8 and the output voltage of the second subcircuit is VPix2. initialization of the first pixel subcircuit S203, feeding an output signal of the DAC or a ramp generator of an ADC conversion into the first pixel subcircuit S204 wherein the comparator triggers, when V_DAC and the output of the second pixel subcircuit are equal, wherein the trigger value is Vppd2 - offset, S205.

After the first and second phase there is a third phase which can be accorded in two different ways. FIG. 8 shows a first alternative where the average between the output of the first and the second pixel by applying Average = (V (ppdl ) +of f set+V (ppd2 ) -of f set ) /2 =

(V (ppdl ) +V (ppd2 ) ) /2

FIG . 9 shows the second alternative , where the accumulation of the conversion of the left pixel and the right pixel .

Accumulation = V (ppdl ) +of f set+V (ppd2 ) -of f set =

V (ppdl ) +V (ppd2 )

LIST OF REFERENCE SIGNS

Circuit 1

Photodiode 2 Input switch 3

Transmission Gate Transistor 4 reset switch 5

Floating Di f fusion Capacitance 6

Source Follower Transistor 8 Pixel subcircuit 10

Additional subcircuit 12

Switch 14

Switch 16

Sample and hold 20 Buf fer 22

Analog to Digital Converter 30

Feed Switch 32

Claims

1. Converter circuit (1) comprising:

A first photodiode (2) arranged in a first pixel subcircuit (10) , the pixel subcircuit (10) being configured for receiving a light input signal to be converted into an output voltage signal Vpixl in a first operation stage and for receiving a reference signal Vref_in to be feed through the first pixel subcircuit in a second operation stage;

A second photodiode (2) arranged in a second pixel subcircuit (10' ) , the pixel subcircuit (10' ) being configured for receiving a light input signal to be converted into an output voltage signal Vpix2 in a first operation stage and for receiving a reference signal Vref_in to be feed through the second pixel subcircuit in a second operation stage; the first and the second pixel subcircuit (10, 10' ) being arranged side-by-side and exposed to the same light and the first and the second pixel subcircuit (10, 10' ) being identical in construction; and

A comparation module, connected to the first pixel subcircuit and the second pixel subcircuit to a respective output for generating an offset corrected output signal.

2. Converter circuit (1) according to claim 1, wherein the first photodiode (2) and the second photodiode (2' ) are Pinned photo diodes.

3. Converter circuit (1) according to one of the previous claims :

Wherein an output of the first pixel subcircuit Vpixl is amplified and converted by an analog-to-digital converter (ADC) and

Wherein an output of the second pixel subcircuit Vpix2 is amplified and converted by an analog-to- digital converter (ADC)

4. Converter circuit (1) according to one of claim 1 to 3, wherein the first and second pixel subcircuit (10, 10' ) each comprises: a capacitance (6) a transmission gate transistor (4) , an input switch (3) for switching between a first and a second operation stage as well as a source follower (SF) transistor (8) .

5. Converter circuit (1) according claim 4, comprising an additional subcircuit (12) having an output connected to the input switch (3) of the pixel subcircuit (10, 10' ) , the additional subcircuit (12) being configured for choosing a reset voltage signal V_RST as reference signal or a feed-back reference signal as input signal.

6. Converter circuit (1) according to one of claims 1 to 4, wherein the operation for correcting for the offset of the converter circuit (1) is averaging the conversion of the first pixel subcircuit (10) with the conversion of the second pixel subcircuit (10' ) .

7. Converter circuit (1) according to one of claims 1 to 4, wherein the operation for correcting for the offset of the converter circuit is accumulating the conversion of the first pixel subcircuit (10) with the conversion of the second pixel subcircuit (10' ) .

8. Converter circuit (1) according to one of the previous claims, wherein the comparation module comprises a comparator (30) and optionally an amplifier for each input signal.

9. Converter circuit (1) according to one of the previous claims, further comprising a controller configured for conducting the following method: a first phase comprising: reset first pixel subcircuit (10) , after resetting sampling of light and transferring charges to an output node of the subcircuit, initialization of the second pixel subcircuit (10' ) , feeding an output signal of a DAC or a ramp generator of an ADC conversion signal as Vref_in into the second pixel subcircuit (10' ) , such that a signal at the output node of the second subcircuit (10' ) corresponds Vrefpix2, wherein a comparator (30) of the comparation module triggers, when the output Vrefpix2 and the output VPixl of the first pixel subcircuit are equal, wherein the trigger value is Vppdl + offset, with Vppdl being the voltage at the gate of the SF transistor (8) of the first pixel subcircuit (10) , a second phase comprising: reset second pixel subcircuit (10' ) , after resetting sampling of light and transferring charges to an output node of the subcircuit (10' ) , initialization of the first pixel subcircuit (10) , feeding an output signal of the DAC or a ramp generator of an ADC conversion as Vref_in into the first pixel subcircuit (10) , such that a signal at the output node of the first pixel subcircuit corresponds to Vrefpixl, wherein a comparator (30) of the comparation module triggers, when Vrefpixl and the output VPix2 of the second pixel subcircuit are equal, wherein the trigger value is Vppd2 - offset, with Vppd2 being the voltage at the gate of the SF transistor (8) of the second pixel subcircuit (10' ) .

10. Method for converting a light signal into a digital signal, the method comprising:

Converting the light signal received at a first photodiode (2) into a first electrical signal through a first pixel subcircuit (10) , Converting the light signal received at a second photo diode (2' ) into a second electrical signal through a second pixel subcircuit (10' ) , the conversion of both light signals being performed in the same manner, alternatingly reading out the first electrical signal with a second pixel reference signal and a second electrical signal with a first pixel reference signal, and combining the readout signals with each other in such a way that the offset of a conversion circuit (1) is eliminated .

11. Method according to claim 9, further comprising: Amplifying the first electrical signal, Amplifying the second electrical signal.

12. Method according to claim 9 or 10, wherein combining is averaging the first read-out signal to the second readout signal.

13. Method according to claim 9 or 10, wherein combining is accumulating the first and second read-out signals.

14. Method according to one of claims 9 to 12, wherein combining the signals includes a transformation into a digital signal.

15. Method according to one of claim 9 to 14 comprising: a first phase comprising: reset first pixel subcircuit (10) , after resetting sampling of light and transferring charges to an output node of the subcircuit, initialization of the second pixel subcircuit (10' ) , feeding an output signal of a DAC or a ramp generator of a ADC conversion signal as Vref_in into the second pixel subcircuit (10' ) , such that a signal at the output node of the second subcircuit (10' ) corresponds to Vrefpix2, wherein a comparator (30) of the comparation module triggers, when the output Vrefpix2 and the output VPixl of the first pixel subcircuit are equal, wherein the trigger value is Vppdl + offset, with Vppdl being the voltage at the gate of the SF transistor (8) of the first pixel subcircuit (10) , a second phase comprising: reset second pixel subcircuit (10' ) , after resetting sampling of light and transferring charges to an output node of the subcircuit (10' ) , initialization of the first pixel subcircuit (10) , feeding an output signal of the DAC or a ramp generator of an ADC conversion as Vref_in into the first pixel subcircuit (10) , such that a signal at the output node of the first pixel subcircuit corresponds to Vrefpixl, wherein a comparator (30) of the comparation module triggers, when Vrefpixl and the output VPix2 of the second pixel subcircuit are equal, wherein the trigger value is Vppd2 - offset, with Vppd2 being the voltage at the gate of the SF transistor (8) of the second pixel subcircuit (10' ) .

16. Method according to one of claims 10 to 15, the method using a converter circuit (1) of any of claims 1 to 9.

17. Sensor comprising a multitude of photodiode integrated into conversion circuits according to any of claims 1 to 9.