RU2688953C1 - Device for reading signals from a photodetector matrix of infrared radiation (versions) - Google Patents

Abstract

FIELD: data processing.SUBSTANCE: invention can be used for processing optical information. Essence of the invention consists in that the device for reading signals from the photodetector matrix of infrared radiation comprises an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of the operational amplifier with a storage capacitor connected in parallel to the negative feedback circuit, a column bus, column charge-sensitive amplifier with a second operational amplifier and connected in parallel to the negative feedback circuit by a capacitor, further comprises a second column bus, wherein one column bus is realized in the form of a signal column bus, and second column bus is implemented in the form of reference column bus, capacitive transimpedance amplifier is also made with input inclusion, in composition of input cell also made integrating transistor, reset transistor, first and second address transistors, integrating start transistor is connected by its source to inverting input of capacitance transimpedance amplifier, which is inverting input of operational amplifier, and the first capacitor capacitor cap, by its drain the integration start transistor is connected to the photodiode cathode, the gate of the integrating start transistor is connected to the input input of the capacitive trans-impedance amplifier, which is the input input of the operational amplifier, wherein said gate and input are configured to supply a control signal of the beginning of integration, the discharge transistor by its drain is connected to the source of the integrating transistor and the first capacitor capacitor plate, by the reset source, the reset transistor is connected to the output of the capacitive trans-impedance amplifier, which is the output of the operational amplifier, and a second capacitor capacitor plate, the resetting transistor gate is configured to supply an input cell reset signal thereto, first address transistor by its drain is connected to inverting input of capacitive transimpedance amplifier, which is inverting input of operational amplifier, first capacitor capacitor coating, source of transistor of integration beginning, drain of reset transistor, source of first address transistor is connected to signal column bus, gate of the first address transistor is connected to the gate of the second address transistor, wherein gates of the first and second address transistors are configured to supply a reading signal thereto, second address transistor by its drain is connected to output of capacitive trans-impedance amplifier, which is output of operational amplifier, with a second capacitor capacitor coating, with a resetting transistor source, and the second address transistor source source is connected to the reference column bus, non-inverting input of the capacitive trans-impedance amplifier, which is a non-inverting input of the operational amplifier, is configured to apply a reference voltage thereto, as a part of the charge-sensitive column amplifier, a second reset transistor is made, wherein the charge-sensitive column amplifier is provided with inverting and non-inverting inputs, respectively inverting and non-inverting inputs of the second operational amplifier, non-inverting input of the column charge-sensitive amplifier is connected to a reference column bus configured to supply a reference voltage thereto, inverting input of a column charge-sensitive amplifier is connected to a first electrode of a capacitor connected in parallel to a negative feedback circuit in the form of a linear capacitor with a discrete set of capacitance values, with a signal column bus, with a drain of the second reset transistor, source of the second reset transistor is connected to the second electrode of the capacitor connected in parallel to the negative feedback circuit in the form of a linear capacitor with a discrete set of capacitance values, with the output of the column charge-sensitive amplifier, which is the output of the second operational amplifier, and the gate of the second reset transistor is configured to supply a reset signal of the column charge-sensitive amplifier to it.EFFECT: possibility of reducing power consumption, improving homogeneity of the output signal.5 cl, 4 dwg

Description

The technical solution (variants) relates to the field of integrated microelectronics and can be used in optical information processing systems.

A device for reading signals from a photodetector array of infrared radiation is known (Very wide dynamic range of SWIR sensors, Canal, Randal J. Hansen, Adrienne N. Costello, William J. Parrish // Proc. SPIE 3698, Infrared Technology and Application XXV, July 1999), containing an input cell, a column bus, a current source, a column buffer amplifier. The input cell is made up of a capacitive transimpedance amplifier (TIU), which is formed by an inverting amplifier with a storage capacitor and a reset key connected in parallel in the negative feedback circuit, as well as a result capacitor limiting the TIU bandwidth, and a sampling / storage key integration, source follower for reloading parasitic capacitance of the column bus, address key. Input TIU made with the possibility of connection with the anode of the photodiode through an indium column. One end of the access / storage key and one plate of the capacitor limiting the bandwidth of the capacitor, the second plate of which is shorted to ground, are connected to the TIU output. The second end of the sample / storage key is connected to the input (gate) of the source follower and one plate of the integration / storage result capacitor capacitor, the second plate of which is shorted to ground. The output of the source follower is configured to switch to a column bus via an address key. A current source is connected to the column bus, which ensures the operation of the source follower, a column buffer amplifier.

The device is designed for HgCdTe and InGaAs photodetectors of the shortwave infrared (IR) range of 320 × 256 format with a step of 30 μm. The device is made on a semiconductor substrate in CMOS (complementary metal-oxide-semiconductor structure) technology with a design standard of 0.6 μm.

The input cell provides operation in the “Snapshot” mode in two options - “Integrate Then Read” (Integrate Then Read - ITR) and “Integrate While Read” (Integrate While Read - IWR).

Stabilization of the bias voltage (operating point) on the photodiode is achieved due to the Miller effect occurring in the capacitive TII, resulting in which the effective input capacitance increases in proportion to the capacitance of the storage capacitor installed in the feedback circuit of the inverting amplifier and the voltage gain.

The principle of operation of the device is as follows. At the beginning of the frame resets the capacitances of the input cell. As a result of the reset, a constant voltage is set at the input and output of the TII. After the reset, the process of integrating the photocurrent begins. TIU converts the accumulated during the integration of the photocell into voltage. The magnitude of the TIU output voltage is proportional to the intensity of the radiation flux incident on the photodiode, which, therefore, makes it possible to judge the radiation intensity. In the IWR mode, at the end of the integration act, the sample / storage key is opened, the TIU recharges the sampling / storage capacitor of the integration result, from which further information is read with the newly closed sampling / storage key. Simultaneously with reading information from the entire array of input cells in IWR mode, a new act of integration begins. When reading information from the input cell, the address key commutes the output of the source follower to the column bus. As a result, a voltage is set at the input of the column buffer amplifier approximately equal to the voltage across the sampling / storage capacitor of the integration result, taking into account the bias, by the threshold voltage of the source follower. The column buffer amplifier amplifies the input signal at the power (repeats the voltage) for further multiplexing.

The development of this device does not solve the technical problem of obtaining a device for reading signals from the photodetector array of infrared radiation, which reduces energy consumption and improves the quality of the photoelectric characteristics, since it does not eliminate a number of drawbacks.

The disadvantages of the considered technical solution are high power consumption, poor linearity of the transfer characteristic of the reader, low charge capacity of the input cell, non-uniformity of the output signal.

The reasons for these shortcomings are as follows.

For the column bus has a large parasitic capacitance. The need to recharge it provides significant power consumption during reading. It should also be noted that at the moment of a full-scale reset, a storage capacitor is recharged, limiting the bandwidth of the capacitor capacitor and capacitor and the reverse-biased pn-junction of the photodiode in the entire array of input cells of the reader, each of which is connected to an individual photosensitive element of the photodetector matrix. This recharge leads to a surge current in the power circuit.

Poor linearity of the transfer characteristic may be associated with the use of circuit design solutions in TIU, which are characterized by low voltage gain. In addition, the use of a source follower due to the effect of the influence of the substrate weakens the amplitude of the output signal and introduces nonlinear distortion.

In order to minimize the contribution of the technological variation of the characteristics of the source follower to the total geometric noise of the reader, there is a need to avoid using the minimum topological dimensions. This circumstance leads to an increase in the part of the input cell area occupied by the repeater, and, as a result, does not allow the use of the maximum area to accommodate the capacitive TIU electrical circuit with high voltage gain, also does not allow to increase the charge capacity.

The non-uniformity of the output voltages from all cells of the reader is provided by the technological spread of the electrical capacitance of the storage capacitor and the spread of the bias voltage of the inverting amplifiers as part of the TII. When implementing a capacitive TIU on the basis of an inverting amplifier without a differential input, there is no possibility of fine tuning the bias voltage on the photodiode. As a result of technological variation, the uniformity of displacement decreases. The bias voltage may vary depending on the temperature and operating current of the TII. In addition, the technological variation of the threshold voltage of the source followers, the parasitic resistance of column tires, the reference current of the source followers leads to an increase in the geometric noise of the reading device — an increase in the non-uniformity of the output voltages.

A device for reading signals from an infrared photodetector array of infrared radiation (An uncooled 1280 × 1024 InGaAs focal plane for small platform, shortwave infrared imaging) is known. , M. Lin, J. Passe, M. Stern, T. Sudol (Proc. SPIE 7298, Infrared Technology and Application XXXV, 729883C, 7 May 2009), containing an input cell, a column bus, pair-wise column amplifiers and sample capacitors / storage. The input cell is made up of a capacitive transimpedance amplifier (TIU), which is formed by an operational amplifier (OA) with a storage capacitor connected in parallel to the negative feedback circuit, as well as a transistor connected to the feedback circuit in parallel with the anti-blooming function, storage capacitor with keys activating it. In addition, as part of the input cell, a capacitor, an address switch, an offset compensation key during resetting, which restricts the bandwidth of the TII, is made. TIU is made with the possibility of connection with the anode of the photodiode by means of an indium column with an inverting input and with the possibility of applying a reference voltage to a non-inverting input. The TIU output is connected to one end of the address key and one lining of the capacitor limiting the bandwidth of the TII, the second lining of which is shorted to ground. The address key is configured to switch when reading the output TIU on the column bus. A pair of switchable column amplifiers and sampling / storage capacitors are connected to the column bus. TIU is implemented with the ability to control the current consumption (load capacity) by controlling the bias voltage of the software-hardware complex.

The device is designed for InGaAs based photodetectors for the shortwave infrared range of 1280 × 1024 format with a step of 15 μm. The device is made on a semiconductor substrate by CMOS technology with a design standard of 0.35 microns.

The principle of operation of the device is as follows. At the beginning of the frame resets the capacitances of the input cell. As a result of the reset, a constant voltage is set at the input and output of the TII, applied to the non-inverting input. The bias voltage on the photodiode in this case is determined by the difference between the reference voltage TII and the voltage on the common cathode of the photodiodes of the photodetector matrix. After the reset, the process of integrating the photocurrent begins. TIU converts the accumulated during the integration of the photocell into voltage. After the act of integration, the address key commutes the output of the TLI to the column bus. TIU recharges the parasitic capacitance of the column bus and the capacitor sampling / storage. While the first set of sample / hold capacitors produces signal information from input cells of a specific row, duplicate column amplifiers further output signal information for multiplexing from the second set of sample / storage capacitors, on which the signal information from the previous row is generated.

This approach allows to reduce the current consumption TIU during the reading and reduce the time of the output signal information. Also, to minimize power consumption, the TIU bias voltage in the rows of the matrix of input cells varies depending on the stage of the reading process, in which the line is located - reset, or integration, or reading. The minimum current in the cells of the row flows during integration, during reading and dumping the operating current is thrown.

The above analog does not solve the technical problem of developing a device for reading signals from the photodetector array of infrared radiation, which reduces energy consumption and improves the quality of photovoltaic characteristics, since it has drawbacks.

The disadvantages of the second analogue include high power consumption, unsatisfactory linearity of the transfer characteristics of the reader, the heterogeneity of the output signal.

The reasons for these shortcomings are as follows.

Energy minimization is not fully achieved. During reading and resetting, the operating current TIU is thrown up. In addition, the conveyor read mode implemented by the device causes the image to be blurred when exposed to a rapidly changing scene, and throughout the frame in the entire array of input cells of the TII, they remain active and dissipate additional power.

The use of circuit solutions with a low voltage gain in the TIU composition ensures a deterioration of the linearity of the transfer characteristic. The non-uniformity of the output signal causes a technological variation of the electrical capacitance of the storage capacitor and the voltages of the OU displacements as part of the TII.

As the closest analogue, a device for reading signals from an infrared infrared photodetector array was selected , International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Application, 73833L, 5 August 2009). The device is implemented for reading information from matrices of IR microcantilevers with an input circuit based on capacitive TII. The device contains an input cell, a column bus, a charge-sensitive amplifier (ICF).

The input cell is made up of a capacitive transimpedance amplifier (TIU), which is formed by an operational amplifier (OA) with a storage capacitor and reset key, sampling / storage key, sampling / storage integration result capacitor, address key connected in parallel to the negative feedback circuit. Capacitive TII is made with inverting and non-inverting inputs. The inverting input is designed to connect to the cantilever, and the non-inverting input to supply the reference voltage. The output of the TIU is connected to one end of the sample / storage key, the other end of which is connected to one end of the address key and one plate of the integration / storage capacitor of the integration result, the second plate of which is shorted to ground. The second end of the address key is connected to the column bus. The PCU is formed by a second op-amp with a capacitor and a reset key, connected in parallel in the negative feedback circuit of the second op-amp. FCA is made with inverting and non-inverting inputs. The column bus is connected to an inverting PSU, and the non-inverting input is designed to supply a reference voltage.

The input cell provides operation in the “Snapshot” mode in the “integration, then reading” mode - ITR.

The device was developed for photo-receivers based on IR microcantilevers of the format 160 × 120 in 50 μm increments, made on a semiconductor substrate using CMOS technology with a design standard of 0.35 μm.

The principle of operation of the device is as follows. At the beginning of the frame resets the capacitances of the input cell. As a result of the reset, the reference voltage is set at the input and output of the TIU applied to the non-inverting input. After the reset, the process of integrating the photocurrent begins. TIU converts a photocharge accumulated during the integration time into voltage. During integration, the sampling / storage key is open, and the sampling / storage capacitor of the integration result also performs the function of limiting the bandwidth of the TII. After the end of the act of integration, the sample / storage key is closed, locking the information signal charge on the sample / storage capacitor of the integration result. The output signal of the input cell is charged. When reading information from the input cell, the address key (transistor) switches the output signal, due to the charge stored on the capacitor sampling / storage of the integration result, to the column bus. Installed on the column bus, the SCF performs conversion to voltage. In large-format readers, the use of an SFC on a column avoids the need to install a source follower at the output of the cell, which is used to recharge the parasitic capacitance of the column bus. With a high gain of the OS, which forms the ASD, the influence of the parasitic capacitance of the column bus is negligible. SCF “keeps” the constant voltage on the bus in the process of reading, thereby preventing the processes of redistribution and transfer of charge. To minimize power consumption during the readout stage of the signal information of the TII, the entire array of input cells is in the off state.

The closest analogue does not solve the technical problem of developing a device for reading signals from the photodetector array of infrared radiation, which reduces power consumption and improves the quality of photovoltaic characteristics, since it has drawbacks.

The disadvantages of the closest analogue are high power consumption, unsatisfactory linearity of the transfer characteristic of the reader, low charge capacity of the input cell, non-uniformity of the output signal.

The reasons for these shortcomings are as follows.

Energy minimization is not fully achieved. At the moment of a full-length reset, the storage capacitor and the sensor capacitance are recharged in the entire array of cells of the photoreceiver, which causes a current inrush to the power circuit.

The use of circuit solutions with low voltage gain in the composition of the TIU causes the deterioration of the linearity of the transfer characteristic.

The sampling / storage capacitor of the integration result occupies a significant part of the input cell area, preventing the use of the maximum possible area for the arrangement of the capacitive TIU electrical circuit with high voltage gain, as well as increasing the charge capacity.

The high non-uniformity of the output signal (output voltages from all cells) is associated with the technological variation of the values of the electrical capacitance of the storage capacitor and the bias voltages of the shelter in the TLI.

The development of the proposed device is aimed at solving the technical problem of obtaining a device for reading signals from the photodetector array of infrared radiation, which ensures a reduction in energy consumption and an increase in the quality of photoelectric characteristics.

The technical result of the solution is:

- reduction of energy consumption;

- improving the linearity of the transfer characteristics of the reader;

- increase the charge capacity of the input cell;

- improving the homogeneity of the output signal.

The technical result is achieved in a device for reading signals from a photodetector array of infrared radiation, containing an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of an operational amplifier with a storage capacitor connected in parallel in the negative feedback circuit, a column-type charge-sensitive amplifier with a second an operational amplifier and a capacitor connected in parallel to the negative feedback circuit, The device contains a second column bus, while one column bus is implemented as a signal column bus, and the second column bus is implemented as a reference column bus, a capacitive transimpedance amplifier is also provided with an enable input, the integration start transistor and the transistor are also included in the input cell. reset, the first and second address transistors, the integration start transistor is connected by its source to the inverting input of a capacitive transimpedance amplifier, which is an inverti The first input of the operational amplifier and the first plate of the storage capacitor, with its drain, start the integration transistor connected to the cathode of the photodiode, the gate of the integration start transistor is connected to the enable input of the capacitive transimpedance amplifier, which turns on the operating amplifier; of the control signal of the start of integration, the reset transistor with its drain is connected to the source of the transistor of the start of integration and the first the storage capacitor plate, the source of the reset transistor is connected to the output of a capacitive transimpedance amplifier, which is the output of the operational amplifier, and the second plate of the storage capacitor, the gate of the reset transistor is configured to supply the reset cell input signal to it, the first address transistor is connected to the inverting input of the capacitive transistor by means of a drain amplifier, which is the inverting input of the operational amplifier, the first plate of the storage capacitor, ohm of the start of integration transistor, the drain of the reset transistor, the source of the first address transistor is connected to the signal column bus, the gate of the first address transistor is connected to the gate of the second address transistor, and the gates of the first and second address transistors are configured to supply a read signal to them, the second address transistor is its the drain is connected to the output of a capacitive transimpedance amplifier, which is the output of an operational amplifier, with a second capacitor capacitor plate a, with the source of the reset transistor, and the source of the second address transistor is connected to the supporting column bus, the non-inverting input of a capacitive transimpedance amplifier, which is a non-inverting input of the operational amplifier, with the possibility of applying a reference voltage to it, as part of a column-sensitive amplifier, a second reset transistor is made, This column charge-sensitive amplifier is made with inverting and non-inverting inputs, which are respectively inverting and non-inverting The secondary inputs of the second operational amplifier, the non-inverting input of the column-type charge-sensitive amplifier, are connected to the reference column bus, which can be supplied with a reference voltage, and the inverting input of the column-type sensitive amplifier, is connected to the first plate connected in parallel to the negative feedback circuit of the capacitor, made in the form of a linear capacitor discrete set of capacitance values, with a signal column bus, with a drain of the second reset transistor, The second reset transistor is connected to the second plate connected in parallel to the negative feedback circuit of a capacitor, made as a linear capacitor with a discrete set of capacitance values, with an output of a column-type sensitive amplifier, which is the output of the second operational amplifier, and the gate of the second reset transistor is configured to feed to it the reset signal of the charge-sensitive column amplifier.

The reader additionally contains a capacitor in the input cell to limit the bandwidth of a capacitive transimpedance amplifier that is connected by one plate to the output of a capacitive transimpedance amplifier, which is an output of the operational amplifier, and the second plate is shorted to ground.

In the reader in the capacitive transimpedance amplifier, the power supply input and the common input shorted to ground are also made, respectively, the power supply input and the common input shorted to ground, of the operational amplifier, are also made in the charge-sensitive amplifier column input supply voltage and common input, shorted to ground, which are, respectively, the input power supply voltage and common input, shorted to ground, the second operational amplifier .

The technical result is achieved in a device for reading signals from a photodetector array of infrared radiation containing an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of an operational amplifier with a storage capacitor connected in parallel in the negative feedback circuit, a column-type charge-sensitive amplifier, the device contains a second column bus, with one column bus implemented in the form of inverse st the front bus, and the second column bus is implemented as a straight column bus, the capacitive transimpedance amplifier is also made with the enable input, the input cell also has an integration start transistor, a reset transistor, the first and second address transistors, the integration start transistor is connected to an inverting source by its source the input capacitive transimpedance amplifier, which is the inverting input of the operational amplifier, and the first plate of the storage capacitor, its drain transistor The integration start is connected to the cathode of the photodiode, the gate of the start of integration transistor is connected to the turn on input of a capacitive transimpedance amplifier, which is the turn on input of the operational amplifier, the gate and the input are supplied with the possibility of supplying a control signal of the start of integration to them, the drain transistor is connected to the source of the transistor on them the beginning of the integration and the first plate of the storage capacitor, the source of the reset transistor is connected to the output capacitive transimpedno amplifier, which is the output of the operational amplifier, and the second plate of the storage capacitor, the gate of the reset transistor is configured to supply the input cell reset signal to it, the first address transistor is connected to the inverting input of the capacitive transimpedance amplifier, which is the inverting input of the operational amplifier, with the first storage switch the capacitor, the source of the transistor start integration, the drain of the reset transistor, the source of the first address transistor is connected to inverse column bus, the gate of the first address transistor is connected to the gate of the second address transistor, and the gates of the first and second address transistors are configured to supply a read signal to them, the second address transistor is connected to the output of the second capacitive transimpedance amplifier, which is an output of the operational amplifier, from the second the lining of the storage capacitor, with the source of the reset transistor, and the source of the second address transistor is connected to the straight column bus, noninver A capacitive transimpedance amplifier input, which is a non-inverting input of an operational amplifier, is designed to supply a reference voltage to it, a column-type charge-sensitive amplifier is completely differential in a capacitor made as a linear capacitor with a discrete set of capacitance values, and a second capacitor made as a linear capacitor with discrete set of capacitance values, second and third reset transistors and fully differential op istration amplifier inverting input being the inverting input of the column charge sensitive amplifier connected to the inverse of column bus, the non-inverting input being the non-inverting input of the column charge sensitive amplifier coupled to direct the column bus, with an inverted and direct outputs, which are respectively inverted and direct outputs column charge-sensitive amplifier, with an inverting input of a fully differential operational amplifier connecting The first capacitor plate, made as a linear capacitor with a discrete set of capacitance values, and the drain of the second reset transistor, the second plate of a capacitor, made as a linear capacitor with a discrete set of capacitance value, and the source of the second reset transistor are connected to the direct output of a fully differential operational amplifier which is a direct output of a column-type charge-sensitive amplifier, with a non-inverting input of a fully differential op amp connecting The first plate of the second capacitor, made in the form of a linear capacitor with a discrete set of capacitance values, and the drain of the third reset transistor, the second plate of the second capacitor, made in the form of a linear capacitor with a discrete set of capacitance values, and the source of the third reset transistor are connected to the inverse output of the fully differential an operational amplifier, which is the inverse output of a column-type charge-sensitive amplifier, the gates of the second and third reset transistors are made with united with each other and with the possibility of supplying them with a control signal for resetting the column-type charge-sensitive amplifier.

In the reader in the capacitive transimpedance amplifier, there is also a power supply input and a common input shorted to ground, which are, respectively, a power supply input and common input shorted to ground, of an operational amplifier, in a fully differential column-sensitive amplifier A power supply input and a common input, shorted to ground, which are, respectively, a power supply input and common input, shorted to ground, is also made spine differential op amp.

The essence of the technical solution is explained in the following description and the attached figures.

FIG. 1 shows an electrical circuit diagram of a device for reading signals from an infrared (IR) photoreceiver array in the first embodiment with an input cell, a signal column bus, a reference bus and a charge-sensitive amplifier, where: DA1 is an operational amplifier (OA); DA2 -operational amplifier (OU); C1 - storage capacitor; C2 - limiting the bandwidth of the transimpedance amplifier (TIU) capacitor; C3 - linear capacitor with a discrete set of capacitance values; VD1 - photodiode; VT1 - the start of the integration transistor; VT2 - reset transistor; VT3 - the first address transistor; VT4 - the second address transistor; VT5 - the second transistor reset; VDD - supply voltage; GND - the general line ("land"); RSTM - input cell reset signal; PHDC is the voltage at the cathode of the photodiode; RSTC is a reset signal of a charge-sensitive column amplifier (PSU); VREF - reference voltage; READ - read signal; INT_EN is the start signal of integration; V_OMX is the voltage at the output of a charge-sensitive amplifier (PSU).

FIG. 2 shows an electrical circuit diagram of a device for reading signals from a photodetector array of infrared (IR) radiation in the second embodiment with an input cell, differential signal column tires and a fully differential charge-sensitive amplifier, where: DA1 is an operational amplifier (OA); DA3 - fully differential operational amplifier (OU); C1 - storage capacitor; C3 - linear capacitor with a discrete set of capacitance values; C4 - linear capacitor with a discrete set of capacitance values; VD1 - photodiode; VT1 - the start of the integration transistor; VT2 - reset transistor; VT3 - the first address transistor; VT4 - the second address transistor; VT5 - the second transistor reset; VT6 - the third transistor reset; VDD - supply voltage; GND - the general line ("land"); PHDC is the voltage at the cathode of the photodiode; RSTM - input cell reset signal; RSTC is a reset signal of a charge-sensitive column amplifier (PSU); VREF - reference voltage; READ - read signal; INT_EN - integration signal; V_OMXD is the voltage at the direct output of the fully differential column charge-sensitive amplifier (SCF); V_OMXD_B is the voltage at the inverse of the output of a fully differential column charge-sensitive amplifier (PSU).

FIG. 3 shows a timing diagram reflecting the operation of a device for reading signals from an infrared (IR) radiation photoreceiver in the first embodiment with an input cell, a signal column bus, a reference bus and a charge sensitive amplifier, where: T _FRAME is the frame time; T _INT - integration time; RSTM - input cell reset signal; INT_EN - integration signal; READ - read signal; RSTC is a reset signal of a charge-sensitive column amplifier (PSU); PHDC is the voltage at the cathode of the photodiode; V_INT is the voltage at the output of the transimpedance amplifier (TII); V_TIN is the voltage at the input of the transimpedance amplifier (TII); V_OMX is the voltage at the output of the charge-sensitive amplifier (PSU); VREF - reference voltage; VDD - supply voltage; Q _C1 - the charge accumulated on the storage capacitor C1 during the integration time.

FIG. 4 shows a timing diagram reflecting the operation of a device for reading signals from an infrared (IR) photoreception array in the second embodiment with an input cell, differential signal column buses and a fully differential charge-sensitive amplifier, where: T _FRAME is the frame time; T _INT - integration time; RSTM - input cell reset signal; INT_EN - integration signal; READ - read signal; RSTC is a reset signal of a charge-sensitive column amplifier (PSU); PHDC is the voltage at the cathode of the photodiode; V_INT is the voltage at the output of the transimpedance amplifier (TII); V_OMXD is the voltage at the direct output of the fully differential column charge-sensitive amplifier (SCF); V_OMXD_B is the voltage at the inverse output of a fully differential column charge-sensitive amplifier (PSU); VREF - reference voltage; VDD- supply voltage; Q _C1 - the charge accumulated on the storage capacitor C1 during the integration time.

The main function of the reader is to register photocharges, which are information signals resulting from the accumulation of photocurrents for a given integration time, from all elements of the photodetector matrix and the subsequent subsequent output of the generated information signals. The main nodes of the analog readout device that provide the required quality of photovoltaic characteristics include an input cell, a column amplifier. The function of the input cell includes the accumulation of the photocurrent for a given integration time and the implementation of the stabilization of the operating point in relation to the photosensitive element of the photodetector - the photodiode. The electrical signal generated by the input cell during the integration time is transmitted via the data bus - the column bus to the column amplifier, then multiplexed to the output amplifier.

The need to register weak infrared fluxes when operating, in particular, in the short-wavelength spectral range requires the integration of capacitive TII by directly into the input cell of the reader. As a rule, the implementation of capacitive TIU is based on the OS with a storage capacitor included in the negative feedback circuit. Traditionally, as for example, in the above analogues, the characteristics of the used opamp in a capacitive TII determine the power consumption, linearity of the transfer characteristic of the reader and the variation of the output voltage level (uniformity).

Reducing the step of the input cells narrows the number of suitable OU circuit solutions in order to integrate the capacitive TIU into the input cell. In addition, the reduction of cell area often prevents the implementation of the necessary requirements for increasing the charge capacity, determined by the electrical capacitance of the storage capacitor and the magnitude of the output voltage of the capacitive TII. To preserve the linearity of converting capacitive TIU into a negative feedback circuit, it is necessary to install capacitors whose capacitance does not depend on the applied voltage, which prevents the use of capacitors based on MOS structures with a higher specific capacitance.

The tendency to increase the number of photosensitive elements (format) of the matrix imposes increased requirements on the level of energy consumption of input cells based on capacitive TII. In addition, an increase in the linear dimensions of the crystal leads to an increase in the influence of the parasitic components of the data transmission buses.

Taking into account the above, in the proposed options for the reader (see Figs. 1 and 2), the achievement of the above technical result is provided by a design that allows reading the charge directly from the storage capacitor C1 installed in the feedback circuit of the TII that is in the off state.

The design, as in the above analogues, is made on the basis of a capacitive transimpedance amplifier and a column amplifier, which, as in the nearest analogue, is charge-sensitive. The capacitive TII of the input cell performs the functions of stabilizing the voltage on the photodiode, integrating the photocurrent, and converting the accumulated photo charge to output voltage. In the first and third (closest) analogues, the capacitive TIU recharges the sampling / storage capacitor of the integration result, from which the signal information is subsequently output. In the second analogue, the output of the signal information from the input cell (as voltage) is carried out directly from the output of the TII. In the proposed variants of the technical solution, the charge is read out directly from the storage capacitor C1 (see Figs. 1 and 2) installed in the negative feedback circuit of the TII. During the reading period TIU is disabled. With this approach, the TII is used to stabilize the voltage on the photodiode and integrate the photocurrent. The conversion of a photo charge to voltage occurs on a columnar voltage converter. Due to the new distribution of functions, the achievement of the technical result is ensured.

Regarding the linearity of the transfer characteristic, the indicated distribution of functions leads to the fact that the linearity of the transfer characteristic of the reader is not dominantly determined by the capacitive TIU DU, as noted above, but by the characteristics of the columnar VCU.

The achievement of improvement in the linearity of the transfer characteristics of the variants of the proposed device is achieved by reducing the influence of the gain of the OS in the TIU composition on the linearity of the conversion. In relation to the proposed variants of the reading device, linearity is mainly determined by the gain of the OS that forms the column-wise PSU. The implementation of topological placement of high gain op amps, as well as with a linear capacitor in negative feedback, is much simpler in the area under the column than in the input cell. As a rule, a region with a width equal to two steps of cells is allocated for the placement of a columnar superimposed voltage exclusion system, and the length of the specified area is not limited. Thus, the PSUs are placed on opposite sides of the matrix of input cells, or one above the other.

It should be noted that the amplitude characteristic of a real op-amp contains non-linear portions that reduce the working range of the TIU output voltage. Accordingly, a significant deviation from a straight line dependence begins near these areas. In the proposed versions of the device, the charge is read directly from the storage capacitor made in the negative feedback circuit of the TII. Therefore, the input range of values can be increased up to the transition of the photodiode to the voltaic mode (under the condition of high dynamic resistance of the photodiode).

Regarding the achievement of the technical result in terms of reducing energy consumption, we note the following. In the proposed versions of the device, in contrast to the above first and second analogs, there is no process of reloading the parasitic capacitance of the column bus at the time of reading. In addition, unlike the above first and third analogs, in which at the time of a full-length reset, the storage capacitor is recharged and the capacitor limits the TIU capacitor in the entire array of input cells, leading to a current surge in the power supply circuit, the band-limiting capacitor TIU, if the latter is provided for in the circuit, is carried out at the moment of reading the input cell, thereby reducing the requirements for the line AI and power source.

The achievement of the technical result in terms of increasing the charge capacity of the input cell is due to the possibility of using in the negative feedback circuit of the capacitive TIU of nonlinear capacitors, as a rule, having a large specific capacity.

The technical result in terms of improving the homogeneity of the output signal is achieved by leveling (smoothing) the effect of the technological variation of the size of the storage capacitor installed in the negative feedback circuit of a capacitive TII. Traditionally, as for example, in the above known technical solutions, the change in voltage at the output of the TII is an output signal, inversely proportional to the value of the storage capacitor. In the proposed variants of the reader in the approximation of high gain, the accumulated and subsequently readable signal charge is determined by the product of the photocurrent values and the integration time and does not depend on the value of the storage capacitor. In this regard, the variation in the value of the storage capacitor does not lead to a variation in the slope of the transfer characteristic, although it will still contribute to the variation in the value of the charge capacity. The scatter of voltages of an op-amp bias as part of a capacitive TII is also not affected by the proposed device variants, since the charge discharged to zero regardless of the op amp bias voltage is read from the input cell.

The proposed reading device is designed for n-on-p HgCdTe photodetectors of the shortwave and mediumwave IR ranges and is made on a semiconductor substrate by CMOS technology. The reader has N × M input cells (N, M≥1) - N rows of the matrix, M column charge-sensitive amplifiers (M≥1) - M columns of the matrix, M (M≥1) pairs of column buses - signal and reference column buses in the case of the device in the implementation of the first option, inverse and straight bus tires in the case of the device in the implementation of the second option (see Fig. 1 and 2). N input cells fall on one column - one column PSU. Input cells belonging to the same column are switched in turn to the same pair of column buses.

FIG. 1 is an electrical schematic diagram of the proposed reader in accordance with the first embodiment of its implementation.

The device for reading signals from the infrared photodetector array contains an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, which is formed by an operational amplifier DA1 with a storage capacitor C1 connected in parallel in the negative feedback circuit, a column bus, a column-sensitive amplifier with a second operational amplifier DA2 connected in parallel to the negative feedback capacitor circuit.

The proposed reader in accordance with the first embodiment of its implementation, in contrast to the closest analogue, has the following features.

In addition to the above column bus, the device comprises a second column bus. In this case, one column bus is implemented as a signal column bus, and the second column bus is implemented as a support column bus (see Fig. 1).

The input cell with a capacitive transimpedance amplifier formed by an operational amplifier DA1 with a storage capacitor C1 connected in parallel to the negative feedback circuit also contains the integration start transistor VT1, the reset transistor VT2, the first and second address transistors, respectively, VT3 and VT4 (see. FIG. one). The transistor of the beginning of integration VT1 ensures the start of the process of integrating the photocurrent and the accumulation of charge on the storage capacitor C1. VT2 reset transistor provides input cell reset before integration. The first and second address transistors, respectively, VT3 and VT4 are necessary for organizing the reading of the accumulated charge from the storage capacitor C1 with a column-type sensing amplifier; through the first address transistor VT3, the reading is performed;

Capacitive transimpedance amplifier is made with inverting and non-inverting inputs, with the enable input "EN", which are, respectively, inverting and non-inverting inputs, the enable input of the operational amplifier DA1. The non-inverting input of a capacitive transimpedance amplifier, which is a non-inverting input of an operational amplifier DA1, is configured to provide a reference voltage “VREF” to it. In addition, in the capacitive transimpedance amplifier, as in the well-known analogs, the power supply input “VDD” and the common input “VSS”, shorted to ground, are made, respectively, the power supply input and the common input, shorted to ground, DA1 op amp.

The integration start transistor VT1 is connected by its source to the inverting input of a capacitive transimpedance amplifier, which is the inverting input of the operational amplifier DA1, the first plate of the storage capacitor C1, the drain of the transistor VT2, the drain of the first address transistor VT3. The drain transistor of the beginning of integration VT1 is connected to the cathode of the photodiode VD1. The gate of the transistor of the beginning of integration VT1 is connected to the “EN” switch-on input of a capacitive transimpedance amplifier, which is the switch-on input of the operational amplifier DA1. In this case, the gate of the transistor of the beginning of integration VT1 and the enable input of "EN" are made with the possibility of supplying them with a control signal of the beginning of integration - "INT_EN". The reset transistor VT2 drain is connected to the source of the transistor start integrating VT1 and the first plate of the storage capacitor C1. The source of the reset transistor VT2 is connected to the output of a capacitive transimpedance amplifier, which is the output of the operational amplifier DA1, and the second plate of the storage capacitor C1. The gate of the reset transistor VT2 is configured to supply it with a reset signal of the input cell - “RSTM”. The first address transistor VT3 is connected to the inverting input of a capacitive transimpedance amplifier, which is the inverting input of the operational amplifier DA1, the first plate of the storage capacitor C1, the source of the transistor of the beginning of integration VT1, the drain of the transistor VT2. The source of the first address transistor VT3 is connected to the signal column bus. The gate of the first address transistor VT3 is connected to the gate of the second address transistor VT4. Moreover, the gates of the first and second address transistors, respectively, VT3 and VT4 made with the possibility of applying to them the read signal "READ". The second address transistor VT4 is connected to the output of a capacitive transimpedance amplifier, which is an output of the operational amplifier DA1, with the second plate of the storage capacitor C1, with the source of the reset transistor VT2. The source of the second address transistor VT4 is connected to the reference column bus.

A capacitor C2 can be made in the input cell to limit the bandwidth of a capacitive transimpedance amplifier. The capacitor C2 is connected by one plate to the output of a capacitive transimpedance amplifier, which is the output of an operational amplifier DA1. The second plate of the capacitor C2 is shorted to ground. The purpose of this additional capacitor C2 is to reduce the noise level when the reader is in operation. This capacitor prevents a noticeable increase in the contribution of thermal noise of the capacitive TIU to the total noise of the reader when the operating temperature rises, in particular more than 150 K. This increases the signal-to-noise ratio of the photoreceiver.

The column charge-sensitive amplifier with the second operational amplifier DA2 and the capacitor C3 connected in parallel in the negative feedback circuit further comprises a second reset transistor VT5 (see. Fig. 1).

The column charge-sensing amplifier is made with inverting and non-inverting inputs, which are respectively inverting and non-inverting inputs of the second operational amplifier DA2. In addition, in the column charge-sensitive amplifier, as in the well-known analogs, the power supply input “VDD” and the common input “VSS”, shorted to ground, are made, respectively, the input power supply voltage and the common input, shorted to ground, the second operational amplifier DA2. The non-inverting input of a charge-sensitive column amplifier is connected to a support column bus, configured to supply the reference voltage “VREF” to it. The inverting input of the column-type charge-sensitive amplifier is connected to the first plate of the capacitor C3 connected in parallel in the negative feedback circuit, to the signal column bus, to the drain of the second transistor VT5.

The second reset transistor VT5 provides a reset of the column-controlled voltage supply field before reading the charge from the storage capacitor C1. The source of the second transistor VT5 is connected to the second plate connected in parallel in the negative feedback circuit of the capacitor C3, with the output of the column-type charge-sensitive amplifier, which is the output of the second operational amplifier DA2. The gate of the second transistor VT5 reset is configured to supply him with a reset signal "RSTC" column charge-sensitive amplifier.

Capacitor C3 is designed as a linear capacitor with a discrete set of capacitance values. The purpose of this capacitor C3 is to provide the possibility of maximizing the output voltage of a columnar SCU at any filling level of the storage capacitor C1, based on its discrete set of capacitance values.

The transistor began to integrate VT1, the reset transistor VT2, the first address transistor VT3, the second address transistor VT4, the second reset transistor VT5 - field-effect transistors made n-MOSFET transistors. The substrates of these transistors are shorted to ground.

The operation of the reader, implemented by the first variant of its implementation, with the achievement of the specified technical result is explained using time diagrams (see. Fig. 3), illustrating the qualitative change in the control and the resulting potentials on the elements of the reader (see.

The frame time “T _FRAME ” is made up of the integration time “T _INT ” and the time taken to read the signal information from the array of input cells. At the beginning of the frame, the RSTM signal applied to the gate of the reset transistor VT2 resets each of the input cells in the array, which, as indicated above, contains N × M (N≥1, M≥1). During the “RSTM” pulse, with a lag relative to the moment of the last feed, start the “INT_EN” pulse, which is used to turn on the capacitive transimpedance amplifier and open the transistor of the start of integration VT1. As a result of resetting the input cell, the photodiode capacitance is recharged and the voltage is balanced at the inverting input and output of the capacitive transimpedance amplifier near the reference voltage level “VREF” as a result of the influence of the DA1 bias voltage. The process of integrating the photocurrent I _PD begins with the cessation of the impulse “RSTM” and lasts until the end of the impulse “INT_EN”.

The change in voltage at the inverting input of a capacitive transimpedance amplifier during integration is determined by the expression

where: I _PD is the photodiode current VD1;

T _INT - integration time;

And ₁ - gain OU DA1 voltage;

C ₁ - the capacity of the storage capacitor C1;

C _PD is the capacitance of the photodiode VD1.

Accordingly, the change in voltage at the output of a capacitive transimpedance amplifier during the integration time is equal to

where: A ₁ - the voltage gain of the amplifier DA1;

ΔV _INT - voltage change at the inverse of the input capacitive TII;

I _PD is the photodiode current VD1;

T _INT - integration time;

C ₁ - the capacity of the storage capacitor C1;

C _PD is the capacitance of the photodiode VD1.

The charge accumulated by the capacitor C1 during the integration time is given by

where: A ₁ - the voltage gain of the amplifier DA1;

C ₁ - the capacity of the storage capacitor C1;

ΔV _INT - voltage change at the inverse of the input capacitive TII;

I _PD is the photodiode current VD1;

T _INT - integration time;

C _PD is the capacitance of the photodiode VD1.

Expressions (1) - (3) are valid under the assumption of high dynamic resistance of the photodiode R _PD , at which the decrease in the efficiency of injection of the photocurrent during the integration process can be neglected (Wei Zhang, SongLei Huang, ZhangCheng Huang, Jiaxpong Fang, Analysis and design of low-noise) ROIC for hybrid InGaAs infrared FPA // Proc. SPIE 8193, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, 81933Q, September 8, 2011). In this approximation, the dynamic resistance of the photodiode R _PD should satisfy the condition

where: T _INT is the integration time;

A ₁ - the voltage gain of the amplifier DA1;

C ₁ - the capacity of the storage capacitor C1;

C _PD is the capacitance of the photodiode VD1.

Even with a small gain OU DA1 voltage A ₁ = 25 and values of integration time T _INT = 30 ms, capacitance C1 C1 ₁ = 150 fF, photodiode capacitance VD1 C _PD = 30 fF from the expression (4) the necessary condition R _PD >> 10 ¹⁰ Ohms, which is easily realized in photodiodes based on a solid solution of cadmium telluride and mercury for the shortwave and mediumwave IR ranges.

The PHDC operating point is stabilized by the Miller effect arising in a capacitive transimpedance amplifier, which results in an increase in the effective input capacitance proportional to the value of the storage capacitor C1 and the gain of the opamp DA1 in voltage.

The first and second address transistors, VT3 and VT4, respectively, are opened with the readout pulse READ. Operational amplifier DA1 at the time of the read signal "READ" is already in the off state. The second plate of the storage capacitor C1 (as well as the capacitor plate C2 to limit the bandwidth of a capacitive transimpedance amplifier if the reader is equipped with it) is short-circuited to the reference column bus through the second address transistor VT4 recharge C2 to the reference voltage "VREF"). Column charge-sensitive amplifier through the first address transistor VT3 reads the accumulated signal charge from the storage capacitor C1. The change in voltage at the output of the charge-sensitive column amplifier is determined by the expression

where: A ₂ - the voltage gain of the amplifier DA2;

Q _C1 is the charge of the storage capacitor C1 during the integration time;

C ₃ is the capacity of a linear capacitor with a discrete set of capacitance values.

When А ₂ >> 1, the potential difference between the plates of the storage capacitor C1 after reading can be neglected. Thus, at the time of resetting the input cell by the “RSTM” signal, the recharge of the storage capacitor C1 (as well as the capacitor C2 to limit the bandwidth of the capacitive transimpedance amplifier if the reader is equipped with it) is absent. Also, at high values of the gain of the OU DA2 over the voltage A2, there are no processes of redistribution and charge transfer along the signal column bus.

Полагая, что выходное напряжение ОУ DA1 достигает напряжения питания «VDD» и напряжение смещение ОУ DA1 равно нулю, средняя величина электрической емкости накопительного конденсатора С1 в рабочем диапазоне определяетсяSince it is taken into account that the storage capacitor C1, in particular, can be non-linear, we determine the average value of its electrical capacitance in the operating range

Assuming that the output voltage OU DA1 reaches the supply voltage "VDD" and the voltage offset OU DA1 is zero, the average value of the electrical capacitance of the storage capacitor C1 in the operating range is determined

where: V _VDD - the value of the supply voltage;

And ₁ - gain OU DA1 voltage;

V _VREF - the value of the reference voltage;

C ₁ - the capacity of the storage capacitor C1.

а

причем в промежутке указанных значений емкость конденсатора С3 принимает значения с дискретностью

(шестнадцать значений емкости). Подбирая величину емкости линейного конденсатора с дискретным набором значений емкости С3 из заданного дискретного набора значений, можно добиться максимального размаха выходного напряжения столбцового зарядочувствительного усилителя ΔV_OMX даже при малом коэффициенте заполнения накопительного конденсатора С1, в данном случае величина емкости линейного конденсатора с дискретным набором значений

В предлагаемом устройстве считывания линейность передаточной характеристики в значительной степени определяется характеристиками операционного усилителя DA2. При использовании в качестве его операционного усилителя с полнодиапазонным размахом выходного сигнала и высоким коэффициентом усиления (А₂>1000) отсутствуют заметные искажения сигнала даже вблизи линий питания. В этом случае величина емкости линейного конденсатора с дискретным набором значений емкости С3 равна величине

емкости накопительного конденсатора С1.The capacitor C3 is implemented, for example, in such a way that its electrical capacity

but

moreover, in the interval of these values, the capacitance of the capacitor C3 takes values with discreteness

(sixteen capacity values). By selecting the capacitance value of a linear capacitor with a discrete set of capacitance C3 values from a given discrete set of values, you can maximize the output voltage of the columnar charge-sensitive amplifier ΔV _OMX even with a small fill factor of the storage capacitor C1, in this case, the capacitance value of the linear capacitor with a discrete set of values

In the proposed reader, the linearity of the transfer characteristic is largely determined by the characteristics of the operational amplifier DA2. When used as its operational amplifier with a full-range swing of the output signal and a high gain factor (А ₂ > 1000), there are no noticeable distortions of the signal even near the power lines. In this case, the capacitance value of a linear capacitor with a discrete set of capacitance values C3 is equal to

storage capacitor capacitance C1.

Reset column charge-sensitive amplifier carry out the signal "RSTC" to the gate of the second transistor reset VT5. The start of the “RSTC” pulse can be during the “READ” pulse. However, this condition is optional.

Regarding the achievement of the technical result in terms of the linearity of the transfer characteristic, we note the following.

In the known readers with an input cell based on a capacitive transimpedance amplifier — given analogs — the voltage described by equation (2) is taken as the basis for further reading of information. So, in the device specified as the first analogue (Roberts F. Cannata, Randal J. Hansen, Adrienne N. Costello, William J. Parrish), Proc. SPIE 3698, Infrared Technology and Application XXV, July 1999), this voltage, being additionally distorted, is derived using a source follower. In the device, indicated as the closest analogue (Design of the readout circuit for microcantilever infrared focal plane array with snapshot integration), Zhongjian Chen, Junmin Cao, Yaciong Zhang, Wengao Lu, Lijiu Ji // Proc. SPIE 7383, International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Application, 73833L, 5 August 2009), this voltage is stored on the sampling / storage capacitor of the integration result, then read as a charge. In the proposed device, the conversion of the photocharge charged to the storage capacitor C1 to the voltage takes place in a column-type charge-sensitive amplifier.

The amplitude characteristic of a real op amp deviates from a straight line, near the saturation region a significant decrease in the gain is observed. Non-linear distortions of an op-amp as part of a capacitive TIU lead to a decrease in the linear dynamic range of the reader. From the analysis of equations (2) and (3) it is clearly seen that in the proposed device the reduction in the gain factor introduces significantly less non-linear distortions in the transfer characteristic of the reading device.

Under the condition A ₁ >> C _PD / C _1, equations (2) and (3) are simplified, respectively, to

where: C ₁ is the capacitance of the storage capacitor C1;

T _INT - integration time;

I _PD is the photodiode current VD1.

Thus, if the electrical capacitance of the storage capacitor C1 depends on the applied voltage, the voltage at the output of the capacitive transimpedance amplifier in the process of integration will also deviate from a straight line dependence. Assuming no effect of small changes in the bias voltage on the photodiode VD1 on the photocurrent value, it is possible to conclude from the expression (8) that for A ₁ >> C _PD / C1, a linear accumulation of charge takes place during integration regardless of the linearity of the capacitance of the storage capacitor C1.

Regarding the achievement of superiority in terms of the homogeneity of the output signal with the technological variation of the electrical capacitance of the storage capacitor C1, similar reasoning is valid.

In the known reading devices given in the description of the prior art, the variation of the capacitance of the storage capacitor C1 will lead to the variation of the slope of the transfer characteristic according to equation (7). In the proposed reader, the variation in the capacitance of the storage capacitor C1 in accordance with equation (8) has no effect on the slope of the transfer characteristic, although it introduces a variation in the charge capacitance of the input cell and, accordingly, in the maximum integration time. This scatter will appear only in the saturation region of the input cells.

It is also known that the variation of the output signal level is caused by the variation of the bias voltage of an operational amplifier of a capacitive TIU (Dong Yang, Hang-yu Zhou, Jian Wang) // Proc. SPIE 8193, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, 81932H, September 8, 2011; Wei Zhang, SongLei Huang, ZhangCheng Huang, Jiaxpong Fang, Analysis and InGaAs infrared FPA // Proc. SPIE 8193, International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Infrared Imaging and Applications, 81933Q, September 8, 2011). In the proposed technical solution, the output signal of the input cell is the charge, reset to zero before the act of integration, regardless of the bias voltage of the operational amplifier DA1. The voltage at the output of the reader, corresponding to the "zero" illumination of the photodetector, will vary only from column to column, there will be no interline variation. The spread will be determined by the characteristics of the DA2 operational amplifier of a column-type charge-sensitive amplifier.

FIG. 2 shows an electrical schematic diagram of the proposed reader in accordance with the second embodiment of its implementation.

The device for reading signals from the photoreceiver array of infrared radiation contains an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, which is formed by operating amplifier DA1 with a storage capacitor C1 connected in parallel in the negative feedback circuit, a column bus, a column-sensitive amplifier.

The proposed reader in accordance with the second variant of its implementation in contrast to the closest analogue has the following features.

The device contains, in addition to the column bus, a second column bus. In this case, one column bus is implemented as an inverse column bus, and the second column bus is implemented as a straight column bus (see. Fig. 2).

The input cell with a capacitive transimpedance amplifier formed by an operational amplifier DA1 with a storage capacitor C1 connected in parallel to the negative feedback circuit also contains the integration start transistor VT1, the reset transistor VT2, the first and second address transistors, respectively, VT3 and VT4 (see. FIG. 2). Similarly, the first variant of the proposed device, these elements perform the following functions.

The transistor of the beginning of integration VT1 ensures the start of the process of integrating the photocurrent and the accumulation of charge on the storage capacitor C1. VT2 reset transistor provides input cell reset before integration. The first and second address transistors, respectively, VT3 and VT4 are required for organizing the reading of the accumulated charge from the storage capacitor C1 with a column-type sensitive amplifier; the input of SCh, through the second address transistor VT4 is the shorting of the second plate of the storage capacitor C1 on column straight bus.

Capacitive transimpedance amplifier is made with inverting and non-inverting inputs, with the enable input "EN", which are, respectively, inverting and non-inverting inputs, the enable input of the operational amplifier DA1. The non-inverting input of a capacitive transimpedance amplifier, which is a non-inverting input of an operational amplifier DA1, is configured to provide a reference voltage “VREF” to it. In the capacitive transimpedance amplifier, as in the well-known analogs, the input supply voltage "VDD" and the common input "VSS" shorted to ground are made, respectively, the input supply voltage and common input shorted to ground ", operational amplifier DA1.

The integration start transistor VT1 is connected by its source to the inverting input of a capacitive transimpedance amplifier, which is the inverting input of the operational amplifier DA1, the first plate of the storage capacitor C1, the drain of the transistor VT2, the drain of the first address transistor VT3. The drain transistor of the beginning of integration VT1 is connected to the cathode of the photodiode VD1. The gate of the transistor of the beginning of integration VT1 is connected to the “EN” switch-on input of a capacitive transimpedance amplifier, which is the switch-on input of the operational amplifier DA1. In this case, the gate of the transistor of the beginning of integration VT1 and the enable input of "EN" are made with the possibility of supplying them with a control signal of the beginning of integration - "INT_EN". The reset transistor VT2 drain is connected to the source of the transistor start integrating VT1 and the first plate of the storage capacitor C1. The source of the reset transistor VT2 is connected to the output of a capacitive transimpedance amplifier, which is the output of the operational amplifier DA1, and the second plate of the storage capacitor C1. The gate of the reset transistor VT2 is configured to supply it with a reset signal of the input cell - “RSTM”. The first address transistor VT3 is connected to the inverting input of a capacitive transimpedance amplifier, which is the inverting input of the operational amplifier DA1, the first plate of the storage capacitor C1, the source of the transistor of the beginning of integration VT1, the drain of the transistor VT2. The source of the first address transistor VT3 is connected to the inverse column bus. The gate of the first address transistor VT3 is connected to the gate of the second address transistor VT4. Moreover, the gates of the first and second address transistors, respectively, VT3 and VT4 made with the possibility of applying to them the read signal "READ". The second address transistor VT4 is connected to the output of a capacitive transimpedance amplifier, which is an output of the operational amplifier DA1, with the second plate of the storage capacitor C1, with the source of the reset transistor VT2. The source of the second address transistor VT4 is connected to a straight column bus (see Fig. 2).

The column charge-sensitive amplifier is completely differential (see Fig. 2). It consists of a capacitor C3 and a second capacitor C4, which are made in the form of linear capacitors with a discrete set of capacitance values.

Also, the composition of the column charge-sensitive amplifier includes the second and third reset transistors, respectively, VT5 and VT6, fully differential operational amplifier DA3.

Fully differential operational amplifier DA3 is made with an inverting input, which is an inverting input of a columnar charge-sensitive amplifier, connected to an inverse column bus, with a non-inverting input, which is a non-inverting input of a columnar charge-sensitive amplifier, connected to a straight column bus, and an inverse and direct output of the signs, a pull-sensitive amplifier, connected to a straight column bus, inverse and direct outputs, the signs, a Jacosen-sensitive amplifier, connected to a straight column bus, inverse and direct outputs, the Icys, a sensitively-sensing amplifier, connected to a straight column bus, inverse and direct outputs, the signs, a pull-sensitive amplifier, connected to a straight column bus, inverse and direct outputs, the Icys, a sensitively-sensing amplifier, connected to a straight column bus, inverse and direct outputs, the Icys, a sensitive antenna, connected to a direct output column. inverse and direct outputs of a charge-sensitive column amplifier. In the fully differential column charge-sensitive amplifier, the input of the supply voltage “VDD” and the common input “VSS” shorted to ground are also made, respectively, the input of the supply voltage and common input shorted to ground, of a fully differential operational amplifier DA3, whose presence for the OS is well known.

A first plate of a C3 capacitor, made in the form of a linear capacitor with a discrete set of capacitance values, and the drain of the second reset transistor VT5 are connected to the inverting input of the fully differential operational amplifier DA3. The second plate of the capacitor C3, made in the form of a linear capacitor with a discrete set of capacitance values, and the source of the second reset transistor VT5 are connected to the direct output of the fully differential operational amplifier DA3, which is the direct output of the column-type charge-sensitive amplifier. A first plate of the second capacitor C4, made in the form of a linear capacitor with a discrete set of capacitance values, and the drain of the third reset transistor VT6 are connected to the non-inverting input of the fully differential operational amplifier DA3. The second plate of the second capacitor C4, made in the form of a linear capacitor with a discrete set of capacitance values, and the source of the third reset transistor VT6 are connected to the inverse output of the fully differential operational amplifier DA3, which is the inverse output of the column-sensitive amplifier. The gates of the second and third transistors reset, respectively, VT5 and VT6 are connected to each other and with the ability to supply them with a control signal reset column charge-sensitive amplifier "RSTC".

The purpose of the capacitors C3 and C4 is to provide the possibility of maximizing the output voltage of the column PSU with any filling level of the storage capacitor C1, based on their discrete sets of values. The purpose of the second and third reset transistors, respectively, VT5 and VT6 to ensure the reset of a fully differential column-type charge-sensitive amplifier.

VT1 integration start transistor, VT2 reset transistor, VT3 first address transistor, VT4 second address transistor, VT5 second reset transistor, VT6 third reset transistor - field effect transistors made by n-MOS transistors The substrates of these transistors are shorted to ground.

The functioning of the reader, implemented by the second variant of its implementation, with the achievement of the specified technical result is explained with the help of timing diagrams (see Fig. 4), illustrating the qualitative change of control and resulting potentials on the elements of the reader (see Fig. 2).

Just as with the operation of the device in the first embodiment, the frame time “T _FRAME ” is made up of the integration time “T _INT ” and the time taken to read the signal information from the array of input cells. At the beginning of the frame on the signal "RSTM", applied to the gate of the reset transistor VT2, reset the array of input cells. After the supply, during the “RSTM” pulse, the “INT_EN” pulse starts to be delivered, which enables the capacitive transimpedance amplifier to be switched on and the transistor of integration start VT1 is opened. As a result of resetting the input cell, the capacitance of the photodiode is recharged and the voltage is balanced at the inverted input and output of the capacitive transimpedance amplifier near the reference voltage level “VREF” as a result of the influence of the DA1 bias voltage. The process of integrating the photocurrent I _PD begins with the cessation of the impulse “RSTM” and lasts until the end of the impulse “INT_EN”.

The change in voltage at the inverse of the input of a capacitive transimpedance amplifier during integration is also determined by expression (1), as in the operation of the device in the first embodiment.

Also, respectively, the change in voltage at the output of a capacitive transimpedance amplifier during integration time during operation of the device during its implementation according to the second variant is determined by expression (2).

The charge accumulated by the storage capacitor C1 during the integration time is given by the above expression (3).

The read signal "READ" fully differential column charge-sensitive amplifier through the opening first and second address transistors, respectively, VT3 and VT4 reads the signal charge accumulated by the storage capacitor C1 during the integration time given by the above expression (3), using differential column tires - inverse and straight column tires. When reading the operational amplifier DA1, as in the operation of the device in the first embodiment, is in the off state. The change in voltage at the differential outputs of the operational amplifier DA3 - direct and inverse outputs, respectively, "V_OMXD" and "V_OMXD_B" (see Fig. 2) are determined by the expressions

where: A ₃ is the voltage gain of the power amplifier DA3;

Q _C1 is the charge of the storage capacitor C1 during the integration time;

C ₃ is the capacity of a linear capacitor with a discrete set of capacitance values;

C ₄ is the capacity of the second linear capacitor with a discrete set of capacitance values.

The output signal of the reader, implemented by the second variant, is the differential voltage ΔV _OMXD + ΔV _OMXDB , proportional to the intensity of the radiation incident on the photodiode during the integration time T _INT .

The voltage on the differential column tires - inverse and straight column tires - is kept near the value equal to half the value of the supply voltage "VDD". During the reset pulse of the RSTM input cells, the first and second address transistors, respectively, VT3 and VT4 will be closed. Therefore, until the operational amplifier DA1 is turned on, the state on the plates of the storage capacitor C1 corresponds to a high-impedance state. When the operational amplifier DA1 is turned on, the signal "INT_EN" on the plates of the storage capacitor C1 will set the voltage to a value close to the reference voltage "VREF". When A ₃ >> 1 after reading the charge, the potential difference between the plates of the storage capacitor C1 can be considered equal to zero. In connection with which the process of recharging the storage capacitor C1 at the time of resetting the input cell is absent.

The capacitances of the capacitor C3 and the second capacitor C4, which are made in the form of linear capacitors with a discrete set of capacitance values, must be equal. The value of their capacity is selected from a given discrete set of values of capacity.

При слабых потоках ИК-излучения (малом коэффициенте заполнения накопительного конденсатора С1) величина емкости конденсаторов С3 и С4 с дискретным набором значений емкости

Тогда конденсаторы С3 и С4 можно реализовать, например, таким образом, что

а

В промежутке указанных значений емкости конденсаторов С3 и С4 принимают шестнадцать значений, меняясь с дискретностью

In the proposed reader in the second embodiment, the linearity of the transfer characteristic is largely determined by the characteristics of the operational amplifier DA3. When used as its operational amplifier with a full-range output signal sweep (from 0 to VDD) and high gain (A ₃ > 1000), there are no noticeable distortions of the signal, even near power lines. The output voltage DA1 varies in the range from "VREF" to "VDD", selecting the capacitance values of linear capacitors with a discrete set of C3 and C4 values from a given discrete set of capacitance values, you can achieve the maximum swing of the output voltage of a column-sensitive amplifier with C ₃ and C values ₄ corresponding linear capacitors C3 and C4 approximately equal

With weak infrared fluxes (low fill factor of the storage capacitor C1), the capacitance value of the capacitors C3 and C4 with a discrete set of capacitance values

Then the capacitors C3 and C4 can be implemented, for example, in such a way that

but

In the interval of the indicated values of the capacitance of capacitors C3 and C4 take sixteen values, varying with discreteness

The above considerations regarding the linearity of the transfer characteristic and the homogeneity of the output signal when explaining the essence of the proposed reader in the first embodiment are valid with respect to the proposed reader in the second embodiment.

Differential charge reading and further signal transmission in differential form, implemented in the second version of the proposed reader, provide the following advantages.

Firstly, a fully differential column-controlled VChU provides greater sensitivity when registering signals from the photodetector array as compared to single-phase ASD in the first embodiment of the device, provides a higher signal-to-noise ratio (the output voltage reaches the supply voltage in the second embodiment)

Secondly, a fully differential column-based PSU provides common-mode noise suppression, the possibility of which occurs when implementing the proposed device in the first embodiment.

Thirdly, the use of a differential signal, which is typical for the proposed device according to the second embodiment, provides the best noise immunity and resistance to pickups in the power supply circuits.

Claims (5)

1. A device for reading signals from the photodetector array of infrared radiation, containing an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of an operational amplifier with an accumulative capacitor connected in parallel in the negative feedback circuit, a column bus, a column-sensitive amplifier with a second operational amplifier and a capacitor connected in parallel in the negative feedback circuit, characterized in that it contains a second column bus, while one column bus is implemented as a signal column bus, and the second column bus is implemented as a reference column bus, a capacitive transimpedance amplifier is also provided with an enable input, the integration start transistor, the reset transistor, the first and the second address transistors, the integration start transistor is connected by its source with the inverting input of a capacitive transimpedance amplifier, which is the inverting input of an operational amplifier and the first plate of the storage capacitor, with its drain, the integration start transistor is connected to the photodiode cathode, the integration start gate of the integration transistor is connected to the enable input of a capacitive transimpedance amplifier, which is the enable input of the operational amplifier, with the specified gate and input configured to supply a control signal to them start of integration, the reset transistor is connected to the source of the transistor at the start of integration and the first plate of the storage terminal by its drain the source, the reset transistor is connected to the output of a capacitive transimpedance amplifier, which is the output of the operational amplifier, and the second plate of the storage capacitor, the gate of the reset transistor is configured to supply a reset cell input signal to it, the first address transistor is connected to the inverting input of the capacitive transimpedance amplifier, which is the inverting input of the operational amplifier, the first plate of the storage capacitor, the source of the transistor began to integrate the drain transistor, the source of the first address transistor is connected to the signal column bus, the gate of the first address transistor is connected to the gate of the second address transistor, and the gates of the first and second address transistors are configured to supply a read signal to them, the second address transistor is connected to the drain by output capacitive transimpedance amplifier, which is the output of the operational amplifier, with the second plate of the storage capacitor, with the source of the reset transistor, and the source of the second address transistor is connected to a reference column bus, a non-inverting input of a capacitive transimpedance amplifier, which is a non-inverting input of an operational amplifier, configured to supply a reference voltage to it, and a second reset transistor is made of a column-sensitive amplifier, while a column-sensitive amplifier is made of a charger. and non-inverting inputs, which are respectively the inverting and non-inverting inputs of the second operation. A non-inverting input of a column-type sensitive amplifier is connected to a reference column bus configured to supply a reference voltage to it, the inverting input of a column-sensitive sensitive amplifier is connected to a first plate connected in parallel to a negative feedback circuit of a capacitor made as a linear capacitor with a discrete set of values capacitance, with a signal column bus, with the drain of the second transistor reset, the source of the second transistor reset connect indented with a second plate connected in parallel to the negative feedback circuit of a capacitor made as a linear capacitor with a discrete set of capacitance values, with an output of a column-type sensitive amplifier, which is the output of the second operational amplifier, and the gate of the second reset transistor is configured to supply a reset signal to it charge sensitive amplifier. 2. The reader under item 1, characterized in that it further comprises a capacitor in the input cell to limit the bandwidth of a capacitive transimpedance amplifier, which is connected by one plate to the output of a capacitive transimpedance amplifier, which is the output of the operational amplifier, and the second plate is shorted to ground . 3. The reader according to Claim. 1, characterized in that the capacitive transimpedance amplifier also has a power supply input and a common input shorted to ground, which are respectively a power supply input and common input shorted to ground, operating amplifier, in the charge-sensitive column amplifier there is also a power supply input and a common input shorted to ground, respectively, the input of the supply voltage and a common input shorted to ground, second o opamp. 4. A device for reading signals from the photodetector array of infrared radiation, containing an input cell with a capacitive transimpedance amplifier with inverting and non-inverting inputs, made on the basis of an operational amplifier with a storage capacitor connected in parallel in the negative feedback circuit, a column bus, a column-sensitive amplifier, different in that contains the second column bus, with one column bus implemented in the form of an inverse column bus, and the second column I bus is implemented as a straight column bus, a capacitive transimpedance amplifier is also made with an enable input, the input cell also includes an integration start transistor, a reset transistor, the first and second address transistors, the integration start transistor is connected to an inverting input of a capacitive transimpedance amplifier by its source, which is the inverting input of the operational amplifier, and the first plate of the storage capacitor, with its drain, the integration start transistor is connected the cathode of the photodiode, the gate of the transistor of the beginning of integration is connected to the enable input of a capacitive transimpedance amplifier, which is the enable input of the operational amplifier, with the specified gate and input configured to supply them with a control signal of the start of integration, the reset transistor is connected to the source of the beginning of integration and the first transistor the capacitor capacitor plate, the source of the reset transistor is connected to the output of a capacitive transimpedance amplifier, which is the output the operational amplifier and the second plate of the storage capacitor, the gate of the reset transistor is configured to supply a reset cell input signal to it, the first address transistor is connected to the inverting input of the capacitive transimpedance amplifier that is the inverting input of the operational amplifier by the source of the storage capacitor integration, drain drain transistor, the source of the first address transistor is connected to the inverse column bus, then the thief of the first address transistor is connected to the gate of the second address transistor, and the gates of the first and second address transistors are configured to supply a read signal to them, the second address transistor is connected to the output of a capacitive transimpedance amplifier, which is an output of an operational amplifier, with the second plate of the storage capacitor, with the source of the reset transistor, and the source of the second address transistor is connected to a straight column bus, a non-inverting input capacitive transi a pedal amplifier, which is a non-inverting input of an operational amplifier, is configured to supply a reference voltage to it, a column-type sensing amplifier is completely differential consisting of a capacitor made as a linear capacitor with a discrete set of capacitance values, and a second capacitor made as a linear capacitor with a discrete set capacitance values, second and third reset transistors and a fully differential op amp with inverti A separate input, which is an inverting input of a column-sensitive amplifier connected to an inverse column bus, with a non-inverting input, which is a non-inverting input of a column-type charge-sensitive amplifier, connected to a direct column bus, with inverse and direct outputs, which are corresponding to inverse and direct outputs of a column, and an inverse and direct output; the first capacitor plate is connected to the inverting input of the fully differential opamp; , made in the form of a linear capacitor with a discrete set of capacitance values, and a drain of the second reset transistor, the second capacitor plate, made in the form of a linear capacitor with a discrete set of capacitance values, and the source of the second reset transistor are connected to a direct output of a fully differential operational amplifier, which is a direct output a columnar charge-sensitive amplifier, with a non-inverting input of a fully differential operational amplifier, the first lining of the second cond is connected A capacitor made in the form of a linear capacitor with a discrete set of capacitance values, and a drain of the third reset transistor, the second plate of the second capacitor made in the form of a linear capacitor with a discrete set of capacitance values, and the source of the third reset transistor are connected to the inverse output of the fully differential operational amplifier, which is the inverse output of the column charge-sensitive amplifier, the gates of the second and third reset transistors are made connected with each other and with the possibility zhnosti feed them the control reset signal of column charge sensitive amplifier. 5. The reader according to claim 4, characterized in that the capacitive transimpedance amplifier also has a power supply input and a common input shorted to ground, which are respectively a power supply input and common input shorted to ground, operating the amplifier, in the fully differential charge-sensitive column amplifier, the power supply input and the common input shorted to ground are also made, respectively, the power supply input and the common input, zak on the ground, a fully differential opamp.

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