WO2025190031A1 - 像素电路和显示装置 - Google Patents

像素电路和显示装置

Info

Publication number
WO2025190031A1
WO2025190031A1 PCT/CN2025/077304 CN2025077304W WO2025190031A1 WO 2025190031 A1 WO2025190031 A1 WO 2025190031A1 CN 2025077304 W CN2025077304 W CN 2025077304W WO 2025190031 A1 WO2025190031 A1 WO 2025190031A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
node
terminal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/077304
Other languages
English (en)
French (fr)
Inventor
宋江
郭永林
闫卓然
李正坤
陈渡
王本莲
于子阳
郑海
胡明
邱海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025190031A1 publication Critical patent/WO2025190031A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a display device.
  • the compensation transistor is directly connected to the gate of the driving transistor and the drain of the driving transistor.
  • GOA gate drive circuit provided on the array substrate
  • the initialization voltage will be written to the gate of the driving transistor and the second pole of the driving transistor at the same time, which will affect the stress of the driving transistor.
  • the main purpose of the present disclosure is to provide a pixel circuit and a display device to solve the problem in the prior art that the compensation transistor is directly connected to the gate of the driving transistor and the drain of the driving transistor, so that when the transistor used to initialize the gate potential of the driving transistor and the compensation transistor used for compensation control are turned on at the same time, the initialization voltage will be written to the gate of the driving transistor and the second electrode of the driving transistor at the same time, which will affect the stress of the driving transistor.
  • an embodiment of the present disclosure provides a pixel circuit, comprising a light-emitting element and a driving transistor; a first electrode of the driving transistor is electrically connected to a first voltage terminal;
  • the pixel circuit further includes at least two transistors disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor; the second electrode of the driving transistor is electrically connected to the light-emitting element, and the driving transistor is used to generate a driving current to drive the light-emitting element;
  • control signals connected to the gates of at least two transistors of the at least two transistors are different from each other.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;
  • the first electrode of the driving transistor is electrically connected to the first voltage terminal through the first light emitting control circuit
  • the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit
  • the second electrode of the light emitting element is electrically connected to the second voltage terminal
  • the first light emitting control circuit is electrically connected to the first light emitting control terminal, and is used to control the connection between the first electrode of the driving transistor and the first voltage terminal under the control of a control signal provided by the first light emitting control terminal;
  • the second light emitting control circuit is electrically connected to the second light emitting control terminal, and is used to control the connection between the second electrode of the driving transistor and the first electrode of the light emitting element under the control of a control signal provided by the second light emitting control terminal.
  • the first light-emitting control terminal is different from the second light-emitting control terminal, and the control signal provided by the first light-emitting control terminal is different from the control signal provided by the second light-emitting control terminal.
  • the pixel circuit includes a compensation control circuit, an on/off control circuit, and a tank circuit; the gate of the driving transistor is electrically connected to the first node; the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node respectively, and is used to control the communication between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal;
  • the on-off control circuit is electrically connected to the on-off control terminal, the third node, and the fourth node, respectively, and is configured to control the connection between the third node and the fourth node under the control of the on-off control signal provided by the on-off control terminal;
  • the energy storage circuit is electrically connected to the first node and is used to store electrical energy.
  • the pixel circuit includes a compensation control circuit, an on/off control circuit, and a tank circuit; the gate of the driving transistor is electrically connected to the first node; the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the compensation control circuit is electrically connected to the compensation control terminal, the fourth node and the third node respectively, and is used to control the communication between the fourth node and the third node under the control of the compensation control signal provided by the compensation control terminal;
  • the on-off control circuit is electrically connected to the on-off control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the on-off control signal provided by the on-off control terminal;
  • the energy storage circuit is electrically connected to the fourth node and is used for storing electrical energy.
  • the pixel circuit includes a first initialization circuit
  • the first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first initial control signal provided by the first initial control terminal.
  • the compensation control terminal is the n-th level first scanning terminal, and the on-off control terminal is the n-th level second scanning terminal; or,
  • the compensation control terminal is the first scanning terminal of the nth level; the transistor included in the on-off control circuit is a p-type transistor, and the on-off control terminal is a low-level terminal; or,
  • the compensation control terminal is the third scanning terminal of the nth level;
  • the transistor included in the on-off control circuit is an n-type transistor, and the on-off control terminal is a high level terminal;
  • n is a positive integer.
  • the first light control terminal and the second light control terminal are connected to the nth level first light control signal
  • the compensation control terminal is connected to the nth level second light control signal
  • the first initial control terminal is connected to the n-ath level second light control signal
  • n and a are positive integers
  • the first light-emitting control terminal is the n-th level light-emitting control terminal
  • the second light-emitting control terminal is the n+1-th level light-emitting control terminal
  • the compensation control terminal is the n-th level first scanning terminal
  • the on-off control terminal is the n-1-th level first scanning terminal
  • n is a positive integer
  • the first light-emitting control terminal is connected to the first light-emitting control signal of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal of the nth level
  • the compensation control terminal is connected to the third light-emitting control signal of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal of the n-bth level
  • n and b are positive integers.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second initial control signal provided by the second initial control terminal.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a third initialization circuit;
  • the data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;
  • the third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.
  • the compensation control circuit includes a first transistor, the on-off control circuit includes a second transistor; and the energy storage circuit includes a storage capacitor.
  • the gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;
  • the gate of the second transistor is electrically connected to the on/off control terminal, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the first plate of the storage capacitor is electrically connected to the first node, and the second plate of the storage capacitor is electrically connected to the DC voltage terminal.
  • the compensation control circuit includes a first transistor, the on-off control circuit includes a second transistor; and the energy storage circuit includes a storage capacitor.
  • the gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node;
  • the gate of the second transistor is electrically connected to the on/off control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the first plate of the storage capacitor is electrically connected to the fourth node, and the second plate of the storage capacitor is electrically connected to the DC voltage terminal.
  • the first light emitting control circuit includes a third transistor
  • the second light emitting control circuit includes a fourth transistor
  • the first initialization circuit includes a fifth transistor
  • the gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;
  • the gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element;
  • a gate of the fifth transistor is electrically connected to the first initial control terminal, a first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node.
  • the second initialization circuit includes a sixth transistor
  • a gate of the sixth transistor is electrically connected to the second initial control terminal, a first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the data writing circuit includes a seventh transistor, and the third initialization circuit includes an eighth transistor;
  • the gate of the seventh transistor is electrically connected to the write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the second node;
  • the gate of the eighth transistor is electrically connected to the third initial control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.
  • an embodiment of the present disclosure provides a display device, characterized in that it includes the above-mentioned pixel circuit.
  • the pixel circuit and display device described in at least one embodiment of the present disclosure use at least two transistors arranged between the gate of the driving transistor and the second electrode of the driving transistor.
  • the control signals connected to the gates of at least two of the at least two transistors are different from each other and are controlled by different control signals to reduce the impact of stress on the driving transistor during the initialization stage.
  • FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG10A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG10B is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG11A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG10A ;
  • FIG11B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG10B ;
  • FIG12 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG13 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG12 ;
  • FIG14 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG14 ;
  • FIG16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG17 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG16 ;
  • FIG18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG19 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG18 ;
  • FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG21 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG20 ;
  • FIG22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG23 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG22 ;
  • FIG24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG25 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG24 ;
  • FIG26 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG27 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG26 ;
  • FIG28 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG29 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG28 ;
  • FIG30 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG31 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG30 ;
  • FIG32 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG33 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG32 ;
  • FIG34 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 35 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 34 .
  • the transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the pixel circuit according to the embodiment of the present disclosure includes a light-emitting element and a driving transistor; a first electrode of the driving transistor is electrically connected to a first voltage terminal;
  • the pixel circuit further includes at least two transistors disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor; the second electrode of the driving transistor is electrically connected to the light-emitting element, and the driving transistor is used to generate a driving current to drive the light-emitting element;
  • control signals connected to the gates of at least two transistors of the at least two transistors are different from each other.
  • the pixel circuit may include a light-emitting element and a driving transistor, and at least two transistors may be arranged between the gate of the driving transistor and the second electrode of the driving transistor, and the control signals connected to the gates of at least two of the at least two transistors are different from each other and are controlled by different control signals.
  • the transistor used to initialize the gate potential of the driving transistor and the compensation transistor used for compensation control may be turned on at the same time. If there is no other transistor with a different gate connected to a different control signal between the gate of the driving transistor and the second pole of the driving transistor, when the transistor used to initialize the gate potential of the driving transistor and the compensation transistor used for compensation control are turned on at the same time, the initialization voltage will be written to the gate of the driving transistor and the second pole of the driving transistor at the same time, which will affect the stress of the driving transistor.
  • the pixel circuit described in at least one embodiment of the present disclosure adopts at least two transistors arranged between the gate of the driving transistor and the second pole of the driving transistor, and the control signals connected to the gates of at least two of the at least two transistors are different from each other and are controlled by different control signals to reduce the impact of stress on the driving transistor during the initialization stage.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;
  • the first electrode of the driving transistor is electrically connected to the first voltage terminal through the first light emitting control circuit
  • the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit
  • the second electrode of the light emitting element is electrically connected to the second voltage terminal
  • the first light emitting control circuit is electrically connected to the first light emitting control terminal, and is used to control the connection between the first electrode of the driving transistor and the first voltage terminal under the control of a control signal provided by the first light emitting control terminal;
  • the second light emitting control circuit is electrically connected to the second light emitting control terminal, and is used to control the connection between the second electrode of the driving transistor and the first electrode of the light emitting element under the control of a control signal provided by the second light emitting control terminal.
  • the first voltage terminal may be a power supply voltage terminal
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the pixel circuit may further include a first light-emitting control circuit and a second light-emitting control circuit.
  • the first light-emitting control circuit may be arranged between the first pole of the driving transistor and the first voltage terminal, and the second light-emitting control circuit may be arranged between the second pole of the driving transistor and the light-emitting element.
  • the first light-emitting control circuit and the second light-emitting control circuit may perform light-emitting control.
  • the first light-emitting control terminal is different from the second light-emitting control terminal, and the control signal provided by the first light-emitting control terminal is different from the control signal provided by the second light-emitting control terminal.
  • the first light-emitting control terminal may be different from the second light-emitting control terminal, and the control signal provided by the first light-emitting control terminal may be different from the control signal provided by the second light-emitting control terminal, but the present invention is not limited thereto.
  • the first light-emitting control end may also be the same as the second light-emitting control end.
  • the pixel circuit includes a light-emitting element E1 and a driving transistor DT;
  • the pixel circuit further includes a first light emitting control circuit 11 and a second light emitting control circuit 12;
  • the gate of the driving transistor DT is electrically connected to the first node N1;
  • the source of the driving transistor DT is electrically connected to the first voltage terminal V1 through the first light emitting control circuit 11, and the drain of the driving transistor DT is electrically connected to the first electrode of the light emitting element E1 through the second light emitting control circuit 12; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2;
  • the first light emitting control circuit 11 is electrically connected to the first light emitting control terminal EMT1, and is used to control the connection between the source of the driving transistor DT and the first voltage terminal V1 under the control of a control signal provided by the first light emitting control terminal EMT1;
  • the second light emitting control circuit 12 is electrically connected to the second light emitting control terminal EMT2 and is configured to control the connection between the drain of the driving transistor DT and the first electrode of the light emitting element E1 under the control of a control signal provided by the second light emitting control terminal EMT2.
  • the pixel circuit includes a compensation control circuit, an on/off control circuit, and an energy storage circuit; the gate of the driving transistor is electrically connected to the first node; the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the compensation control circuit is electrically connected to the compensation control terminal, the first node, and the fourth node respectively, and is used to control the communication between the first node and the fourth node under the control of the compensation control signal provided by the compensation control terminal;
  • the on-off control circuit is electrically connected to the on-off control terminal, the third node, and the fourth node, respectively, and is configured to control the connection between the third node and the fourth node under the control of the on-off control signal provided by the on-off control terminal;
  • the energy storage circuit is electrically connected to the first node and is used to store electrical energy.
  • the pixel circuit may include a compensation control circuit, an on-off control circuit and an energy storage circuit.
  • the compensation control circuit and the on-off control circuit are arranged between the gate of the driving transistor and the second electrode of the driving transistor.
  • the gate of the transistor included in the compensation control circuit is electrically connected to the compensation control end, and operates under the control of the compensation control signal provided by the compensation control end;
  • the gate of the transistor included in the on-off control circuit is electrically connected to the on-off control end, and operates under the control of the on-off control signal provided by the on-off control end;
  • the compensation control circuit can be arranged between the first node and the fourth node, and the on-off control circuit can be arranged between the third node and the fourth node.
  • the pixel circuit includes a compensation control circuit 21, an on/off control circuit 22, and a tank circuit 20; the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit 21 is electrically connected to the compensation control terminal SC, the first node N1, and the fourth node N4, respectively, and is configured to control the connection between the first node N1 and the fourth node N4 under the control of the compensation control signal provided by the compensation control terminal SC;
  • the on-off control circuit 22 is electrically connected to the on-off control terminal ST, the third node N3, and the fourth node N4, respectively, and is configured to control the connection between the third node N3 and the fourth node N4 under the control of the on-off control signal provided by the on-off control terminal ST;
  • the energy storage circuit 20 is electrically connected to the first node N1 and is configured to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure includes a compensation control circuit, an on-off control circuit, and an energy storage circuit; the gate of the driving transistor is electrically connected to the first node; the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the compensation control circuit is electrically connected to the compensation control terminal, the fourth node and the third node respectively, and is used to control the communication between the fourth node and the third node under the control of the compensation control signal provided by the compensation control terminal;
  • the on-off control circuit is electrically connected to the on-off control terminal, the first node, and the fourth node, respectively, and is used to control the connection between the first node and the fourth node under the control of the on-off control signal provided by the on-off control terminal;
  • the energy storage circuit is electrically connected to the fourth node and is used for storing electrical energy.
  • the pixel circuit may include a compensation control circuit, an on-off control circuit and an energy storage circuit.
  • the compensation control circuit, the on-off control circuit and the energy storage circuit may be arranged between the gate of the driving transistor and the second electrode of the driving transistor.
  • the gate of the transistor included in the compensation control circuit is electrically connected to the compensation control end, and operates under the control of the compensation control signal provided by the compensation control end;
  • the gate of the transistor included in the on-off control circuit is electrically connected to the on-off control end, and operates under the control of the on-off control signal provided by the on-off control end;
  • the compensation control circuit may be arranged between the first node and the third node, and the on-off control circuit may be arranged between the first node and the fourth node.
  • the pixel circuit includes a compensation control circuit 21 , an on/off control circuit 22 , and a tank circuit 20 ;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit 21 is electrically connected to the compensation control terminal SC, the fourth node N4, and the third node N3, respectively, and is configured to control the fourth node N4 to be connected to the third node N3 under the control of a compensation control signal provided by the compensation control terminal SC;
  • the on-off control circuit 22 is electrically connected to the on-off control terminal ST, the first node N1, and the fourth node N4, respectively, and is used to control the connection between the first node N1 and the fourth node N4 under the control of the on-off control signal provided by the on-off control terminal ST;
  • the energy storage circuit 20 is electrically connected to the fourth node N4 and is configured to store electrical energy.
  • the pixel circuit includes a first initialization circuit
  • the first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first initial control signal provided by the first initial control terminal.
  • the pixel circuit may include a first initialization circuit, which may write a first initial voltage to a first node under the control of a first initial control signal during an initialization phase, so that the driving transistor can be turned on at the beginning of a compensation phase.
  • the pixel circuit according to at least one embodiment of the present disclosure includes a first initialization circuit 41 ;
  • the first initialization circuit 41 is electrically connected to the first initial control terminal SI1, the first initial voltage terminal I1 and the first node N1, respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal SI1.
  • the pixel circuit according to at least one embodiment of the present disclosure includes a first initialization circuit 41 ;
  • the first initialization circuit 41 is electrically connected to the first initial control terminal SI1, the first initial voltage terminal I1 and the first node N1, respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first initial control signal provided by the first initial control terminal SI1.
  • the compensation control terminal is the n-th level first scanning terminal, and the on-off control terminal is the n-th level second scanning terminal; or,
  • the compensation control terminal is the first scanning terminal of the nth level; the transistor included in the on-off control circuit is a p-type transistor, and the on-off control terminal is a low-level terminal; or,
  • the compensation control terminal is the third scanning terminal of the nth level;
  • the transistor included in the on-off control circuit is an n-type transistor, and the on-off control terminal is a high-level terminal; for example, the high-level terminal can be a power supply voltage terminal;
  • n is a positive integer.
  • the first light-emitting control terminal and the second light-emitting control terminal are connected to the nth level first light-emitting control signal
  • the compensation control terminal is connected to the nth level second light-emitting control signal
  • the first initial control terminal is connected to the n-ath level second light-emitting control signal
  • n and a are positive integers
  • the first light-emitting control terminal is the n-th level light-emitting control terminal
  • the second light-emitting control terminal is the n+1-th level light-emitting control terminal
  • the compensation control terminal is the n-th level first scanning terminal
  • the on-off control terminal is the n-1-th level first scanning terminal
  • n is a positive integer
  • the first light-emitting control terminal is connected to the first light-emitting control signal of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal of the nth level
  • the compensation control terminal is connected to the third light-emitting control signal of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal of the n-bth level
  • n and b are positive integers.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit
  • the second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the second node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the second node under the control of the second initial control signal provided by the second initial control terminal.
  • the pixel circuit may further include a second initialization circuit. Under the control of a second initial control signal, the second initialization circuit writes a second initial voltage into the second node to improve the hysteresis phenomenon.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a third initialization circuit;
  • the data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;
  • the third initialization circuit is electrically connected to the third initial control terminal, the third initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light-emitting element under the control of the third initial control signal provided by the third initial control terminal.
  • the pixel circuit may further include a data writing circuit and a third initialization circuit
  • the data write circuit writes the data voltage into the second node to write the data voltage.
  • the third initialization circuit writes the third initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.
  • the write control terminal may be the n-th level first scan terminal
  • the third initial control terminal may be the n-th level first scan terminal
  • the second initial control terminal may be the reset control terminal
  • the write control terminal may be the first scanning terminal of the nth level, the third initial control terminal may be the reset control terminal, and the second initial control terminal may be the reset control terminal;
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a third initialization circuit 62 ;
  • the data writing circuit 61 is electrically connected to the write control terminal GW, the data line DL and the second node N2, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the write control signal provided by the write control terminal GW;
  • the third initialization circuit 62 is electrically connected to the third initial control terminal SI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal SI3.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit 61 and a third initialization circuit 62 ;
  • the data writing circuit 61 is electrically connected to the write control terminal GW, the data line DL and the second node N2, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the write control signal provided by the write control terminal GW;
  • the third initialization circuit 62 is electrically connected to the third initial control terminal SI3, the third initial voltage terminal I3 and the first electrode of the light-emitting element, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E1 under the control of the third initial control signal provided by the third initial control terminal SI3.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 80 ;
  • the second initialization circuit 80 is electrically connected to the second initial control terminal SI2, the second initial voltage terminal I2 and the second node N2, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second initial control signal provided by the second initial control terminal SI2, so as to improve hysteresis.
  • the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 80 ;
  • the second initialization circuit 80 is electrically connected to the second initial control terminal SI2, the second initial voltage terminal I2 and the second node N2, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the second node N2 under the control of the second initial control signal provided by the second initial control terminal SI2, so as to improve hysteresis.
  • the compensation control circuit includes a first transistor, the on-off control circuit includes a second transistor; and the energy storage circuit includes a storage capacitor.
  • the gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the fourth node;
  • the gate of the second transistor is electrically connected to the on/off control terminal, the first electrode of the second transistor is electrically connected to the third node, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the first plate of the storage capacitor is electrically connected to the first node, and the second plate of the storage capacitor is electrically connected to the DC voltage terminal.
  • the compensation control circuit includes a first transistor, the on-off control circuit includes a second transistor; and the energy storage circuit includes a storage capacitor.
  • the gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the fourth node, and the second electrode of the first transistor is electrically connected to the third node;
  • the gate of the second transistor is electrically connected to the on/off control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the fourth node;
  • the first plate of the storage capacitor is electrically connected to the fourth node, and the second plate of the storage capacitor is electrically connected to the DC voltage terminal.
  • the first light emitting control circuit includes a third transistor
  • the second light emitting control circuit includes a fourth transistor
  • the first initialization circuit includes a fifth transistor
  • the gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;
  • the gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element;
  • a gate of the fifth transistor is electrically connected to the first initial control terminal, a first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first node.
  • the second initialization circuit includes a sixth transistor
  • a gate of the sixth transistor is electrically connected to the second initial control terminal, a first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the data writing circuit includes a seventh transistor, and the third initialization circuit includes an eighth transistor;
  • the gate of the seventh transistor is electrically connected to the write control terminal, the first electrode of the seventh transistor is electrically connected to the data line, and the second electrode of the seventh transistor is electrically connected to the second node;
  • the gate of the eighth transistor is electrically connected to the third initial control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the n-th stage second scanning terminal GT2(n), the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level first light emitting control signal EM1(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the first scanning terminal GT(n-1) of the n-1th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the third scanning terminal GT3(n) of the nth stage, the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the first scanning terminal GT(n) of the nth level
  • the on-off control terminal is the second scanning terminal GT2(n) of the nth level
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the first initial control terminal is the first scanning terminal GT(n-1) of the n-1th level
  • the write control terminal is the third scanning terminal GT3(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • FIG. 11A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 10A .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT2(n) provides a high voltage signal
  • GT3(n) provides a high voltage signal
  • T5 is turned on
  • T8 is turned on
  • I1 provides a first initial voltage Vinit1
  • I3 provides a third initial voltage Vinit3
  • Vinit1 is written to the first node N1, so that DT can be turned on when the write phase S2 begins
  • Vinit3 is written to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • GT2(n) provides a low voltage signal
  • GT3(n) provides a low voltage signal
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides the data voltage Vdata to N2 for data voltage writing
  • EM(n) is a low voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • GT2(n) provides a low voltage signal
  • GT3(n) provides a high voltage signal
  • T3 and T4 are turned on
  • T2 is turned on
  • the first scan signal of the n-1th level provided by GT(n-1) and the first scan signal of the nth level provided by GT(n) have overlapping effective time periods.
  • T1 and T5 are turned on at the same time.
  • Vinit1 is written to the gate of DT and the drain of DT at the same time, which affects the stress of DT.
  • the time for the power supply voltage provided by the power supply voltage terminal VDD to reach the anode of O1 can be controlled by T2.
  • the time the power supply voltage stays at the source of DT is beneficial to improving the hysteresis of DT and improving the display afterimage phenomenon.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the n-th stage second scanning terminal GT2(n), the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level first light emitting control signal EM1(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the first scanning terminal GT(n-1) of the n-1th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the n-th first scanning terminal GT(n)
  • the on-off control terminal is the n-th second scanning terminal GT2(n)
  • the first light-emitting control terminal is connected to the n-th first light-emitting control signal EM1(n)
  • the second light-emitting control terminal is connected to the n-th first light-emitting control signal EM1(n)
  • the first initial control terminal is the n-1-th first scanning terminal GT(n-1)
  • the write control terminal is the n-th first scanning terminal GT(n)
  • the third initial control terminal is the n-th first scanning terminal GT(n).
  • FIG. 11B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 10B .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • GT2(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • GT2(n) provides a low voltage signal
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides a data voltage Vdata to the second node N2, and N1 and N3 are connected
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a low voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • GT2(n) provides a low voltage signal
  • T3, T4 and T2 are turned on, and DT drives O1 to emit light.
  • the difference between at least one embodiment of the pixel circuit shown in Figure 12 of the present disclosure and at least one embodiment of the pixel circuit shown in Figure 10 of the present disclosure is that the gate of T2 is electrically connected to the low-level end VGL, so as to reduce the number of control signals used by the pixel circuit, so as to reduce the number of GOA (gate drive circuit arranged on the array substrate) circuits used to generate control signals.
  • GOA gate drive circuit arranged on the array substrate
  • FIG. 13 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12 .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides a data voltage Vdata to the second node N2, and N1 and N3 are connected
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a low voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • T3, T4 and T2 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is connected to the n-th stage second light emitting control signal EM2(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level first light emitting control signal EM1(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-7th level second light emitting control signal EM2(n-7), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the on-off control terminal is a low-level terminal
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the first initial control terminal is connected to the second light-emitting control signal EM2(n-7) of the n-7th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • FIG. 15 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure.
  • the gate of T2 may be replaced by being electrically connected to the second scanning terminal of the nth stage.
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • EM2(n-7) is a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM2(n-7) is a high voltage signal
  • EM2(n) is a low voltage signal
  • GT(n) provides a low voltage signal
  • DL provides a data voltage Vdata to the second node N2
  • T1 is turned on
  • T2 is turned on
  • N1 and N3 are connected
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • DT is turned on, and Vdata is Cst to change the potential of N1 until the potential of N1 becomes Vdata+Vth.
  • DT is then turned off and charging stops to compensate for the threshold voltage; Vth is the threshold voltage of DT.
  • EM1(n) is a low voltage signal
  • EM2(n) is a high voltage signal
  • EM2(n-7) is a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on
  • T2 is turned on
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n+1th level first light emitting control signal EM1(n+1), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the first scanning terminal GT(n-1) of the n-1th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the first scanning terminal GT(n) of the nth level
  • the on-off control terminal is the low-level terminal
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n+1) of the n+1th level
  • the first initial control terminal is the first scanning terminal GT(n-1) of the n-1th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 may be replaced by being electrically connected to the second scanning terminal of the nth stage.
  • FIG. 17 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 16 of the present disclosure.
  • a display cycle includes an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 that are sequentially arranged;
  • EM1(n) is a high voltage signal
  • EM1(n+1) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM1(n+1) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides a data voltage Vdata to the second node N2;
  • DT is turned on and charges Cst through Vdata to change the potential of the first node N1 until the potential of N1 becomes Vdata+Vth.
  • DT is then turned off and stops charging to perform threshold voltage compensation; Vth is the threshold voltage of DT.
  • EM1(n) is a low voltage signal
  • EM1(n+1) is a low voltage signal
  • T3 and T4 are turned on
  • T2 is turned on
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is connected to the n-th stage third light emitting control signal EM3(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-5th level third light emitting control signal EM3(n-5), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the third light-emitting control signal of the nth level
  • the on-off control terminal is a low-level terminal
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal EM3(n-5) of the n-5th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 may be replaced by being electrically connected to the second scanning terminal of the nth stage.
  • FIG. 19 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure.
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a low voltage signal
  • GT(n) provides a low voltage signal
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1
  • DL provides the data voltage Vdata
  • T7 is turned on
  • T1 and T2 are turned on;
  • DT is turned on and charges Cst through Vdata, changing the potential of the first node N1 until the potential of the first node N1 becomes Vdata+Vth. DT is then turned off and stops charging to perform threshold voltage compensation.
  • EM1(n) is a low voltage signal
  • EM2(n) is a low voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on
  • T2 is turned on
  • EM1 ( n ) and EM2 ( n ) may also be adjacent-stage light emission control signals generated by the same EOA circuit (the EOA circuit may be a driving circuit that generates a control signal).
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is connected to the n-th stage third light emitting control signal EM3(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-5th level third light emitting control signal EM3(n-5), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the second initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the drain of the sixth transistor T6 is electrically connected to the second node N2;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • a gate of the eighth transistor T8 is electrically connected to the reset control terminal RST, a source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and a drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the third light-emitting control signal of the nth level
  • the on-off control terminal is a low-level terminal
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal EM3(n-5) of the n-5th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the reset control terminal RST
  • the second initial control terminal is the reset control terminal RST.
  • the gate of T2 may be replaced by being electrically connected to the second scanning terminal of the nth stage.
  • FIG. 21 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 20 of the present disclosure.
  • a display cycle may include a first initialization phase S11 , a writing phase S2 , a second initialization phase S12 , and a light emitting phase S3 , which are sequentially arranged;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a low voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T5, T6 and T8 are turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1 so that DT can be turned on when the write phase S2 begins
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve hysteresis
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a low voltage signal
  • GT(n) provides a low voltage signal
  • RST provides a high voltage signal
  • T7 is turned on
  • T2 is turned on
  • T1 is turned on
  • DL provides the data voltage Vdata to the second node N2, and charges Cst through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth
  • DT is turned off to stop charging and perform threshold voltage compensation
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve hysteresis
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a low voltage signal
  • EM2(n) is a low voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a high voltage signal
  • T3 and T4 are turned on
  • T2 is turned on
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level first light emitting control signal EM1(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the first scanning terminal GT(n-1) of the n-1th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the first scanning terminal GT(n) of the nth level
  • the on-off control terminal is the low level terminal VGL
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the first initial control terminal is the first scanning terminal GT(n-1) of the n-1th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 can be replaced by being electrically connected to a control terminal that provides a control signal, which provides a low voltage signal during the initialization stage, the writing stage and the light-emitting stage to enable the pixel circuit to operate.
  • FIG. 23 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 22 .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1
  • T7 is turned on
  • DL provides the data voltage Vdata to the second node N2
  • T1 and T2 are turned on;
  • DT is turned on and Cst is charged through Vdata, changing the potential of the first node N1 until the potential of N1 becomes Vdata+Vth.
  • DT is then turned off and charging stops, performing threshold voltage compensation; Vth is the threshold voltage of DT.
  • EM1(n) is a low voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is connected to the n-th stage second light emitting control signal EM2(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level first light emitting control signal EM1(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-7th level second light emitting control signal EM2(n-7), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the on-off control terminal is the low level terminal VGL
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the first initial control terminal is connected to the second light-emitting control signal EM2(n-7) of the n-7th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 can be replaced by being electrically connected to a control terminal that provides a control signal, which provides a low voltage signal during the initialization stage, the writing stage, and the light-emitting stage to enable the pixel circuit to operate.
  • FIG. 25 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 24 .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • EM2(n-7) is a low voltage signal
  • GT(n) provides a high voltage signal
  • T2 is turned on
  • T5 is turned on
  • T2 is turned on
  • I3 provides a third initial voltage Vinit3 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM2(n-7) is a high voltage signal
  • EM2(n) provides a low voltage signal
  • GT(n) provides a low voltage signal
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1, clearing the residual charge on the anode of O1
  • T7 is turned on
  • T1 and T2 are turned on
  • DL provides a data voltage Vdata to the second node N2, and charges Cst through Vdata, changing the potential of the first node N1 until the potential of the first node N1 becomes Vdata+Vth
  • DT is turned off to perform threshold voltage compensation
  • EM1(n) is a low voltage signal
  • EM2(n-7) is a high voltage signal
  • EM2(n) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n+1th level first light emitting control signal EM1(n+1), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the first scanning terminal GT(n-1) of the n-1th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the first scanning terminal GT(n) of the nth level
  • the on-off control terminal is the low level terminal VGL
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the first light-emitting control signal EM1(n+1) of the n+1th level
  • the first initial control terminal is the first scanning terminal GT(n-1) of the n-1th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 can be replaced by being electrically connected to a control terminal that provides a control signal, which provides a low voltage signal during the initialization stage, the writing stage and the light-emitting stage to enable the pixel circuit to operate.
  • FIG. 27 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 26 .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • EM1(n+1) is a high voltage signal
  • GT(n-1) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • T2 is turned on
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM1(n+1) is a high voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1, clearing the residual charge on the anode of O1
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides a data voltage Vdata to the second node N2, and charges Cst through Vdata, changing the potential of the first node N1 until DT is turned off, and the potential of N1 is Vdata+Vth for threshold voltage compensation
  • Vth is the threshold voltage of the DTFT
  • EM1(n) is a low voltage signal
  • EM1(n+1) is a low voltage signal
  • GT(n-1) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is connected to the n-th stage third light emitting control signal EM3(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-5th level third light emitting control signal EM3(n-5), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the third light-emitting control signal EM3(n) of the nth level
  • the on-off control terminal is the low-level terminal VGL
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal EM3(n-5) of the n-5th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 can be replaced by being electrically connected to a control terminal that provides a control signal, which provides a low voltage signal during the initialization stage, the writing stage, and the light-emitting stage to enable the pixel circuit to operate.
  • FIG. 29 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 28 .
  • a display cycle may include an initialization phase S1 , a writing phase S2 , and a light emitting phase S3 , which are arranged in sequence;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a low voltage signal
  • GT(n) provides a high voltage signal
  • T5 is turned on
  • T2 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1, so that DT can be turned on when the write phase S2 begins;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a low voltage signal
  • GT(n) provides a low voltage signal
  • T8 is turned on
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1
  • T1 and T2 are turned on
  • T7 is turned on
  • DL provides a data voltage Vdata to the second node N2;
  • DT is turned on, charging Cst through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, and DT is turned off to perform threshold voltage compensation, where Vth is the threshold voltage of DT.
  • EM1(n) is a low voltage signal
  • EM2(n) is a low voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is connected to the n-th stage third light emitting control signal EM3(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the low level terminal VGL, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage first light emitting control signal EM1(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is connected to the n-5th level third light emitting control signal EM3(n-5), the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the second initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the drain of the sixth transistor T6 is electrically connected to the second node N2;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • all transistors are p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is connected to the third light-emitting control signal EM3(n) of the nth level
  • the on-off control terminal is the low level terminal VGL
  • the first light-emitting control terminal is connected to the first light-emitting control signal EM1(n) of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the first initial control terminal is connected to the third light-emitting control signal EM3(n-5) of the n-5th level
  • the second initial control terminal is the reset control terminal RST
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the first scanning terminal GT(n) of the nth level.
  • the gate of T2 can be replaced by being electrically connected to a control terminal that provides a control signal, and the control terminal provides a low voltage signal in the first initialization stage, the writing stage and the light-emitting stage to enable the pixel circuit to operate.
  • FIG. 31 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 30 .
  • a display cycle may include a first initialization phase S11 , a writing phase S2 , a second initialization phase S12 , and a light emitting phase S3 , which are sequentially arranged;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a low voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T5 is turned on
  • T2 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1 to enable DT to be turned on at the beginning of the write phase S2
  • T6 and T8 are turned on, and I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a low voltage signal
  • GT(n) provides a low voltage signal
  • RST provides a high voltage signal
  • T1 and T2 are turned on; T7 is turned on, and DL provides the data voltage Vdata to the second node N2;
  • Vth is the threshold voltage of DT.
  • EM1(n) is a high voltage signal
  • EM2(n) is a high voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM1(n) is a low voltage signal
  • EM2(n) is a low voltage signal
  • EM3(n-5) is a high voltage signal
  • EM3(n) is a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the gate of the first transistor T1 is electrically connected to the n-th stage third scanning terminal NG(n), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the fourth node N4;
  • the gate of the second transistor T2 is electrically connected to the power supply voltage terminal VDD, the source of the second transistor T2 is electrically connected to the third node N3, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage second light emitting control signal EM2(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the third scanning terminal NG(n-5) of the n-5th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the second initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the drain of the sixth transistor T6 is electrically connected to the second node N2;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8 (;
  • the gate of the seventh transistor T7 is electrically connected to the n-th stage first scanning terminal GT(n), the source of the seventh transistor T7 is electrically connected to the data line DL, and the drain of the seventh transistor T7 is electrically connected to the second node N2;
  • a gate of the eighth transistor T8 is electrically connected to the reset control terminal RST, a source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and a drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • T1 , T2 , and T5 are all n-type transistors, and the other transistors are all p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the third scanning terminal NG(n) of the nth level
  • the on-off control terminal is the power supply voltage terminal
  • the first light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the second light-emitting control terminal is connected to the second light-emitting control signal EM2(n) of the nth level
  • the first initial control terminal is the third scanning terminal NG(n-5) of the n-5th level
  • the write control terminal is the first scanning terminal GT(n) of the nth level
  • the third initial control terminal is the reset control terminal RST
  • the second initial control terminal is the reset control terminal RST.
  • FIG33 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG32 of the present disclosure.
  • a display cycle may include a first initialization phase S11 , a writing phase S2 , a second initialization phase S12 , and a light emitting phase S3 , which are sequentially arranged;
  • EM2(n) is a high voltage signal
  • NG(n-5) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T5 is turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1 to enable DT to be turned on at the beginning of the write phase S2
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM2(n) is a high voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • RST provides a high voltage signal
  • T1 and T2 are turned on
  • T7 is turned on
  • DL passes the data voltage Vdata to the second node N2;
  • DT is turned on, charging Cst through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, and DT is turned off to perform threshold voltage compensation;
  • Vth is the threshold voltage of DT;
  • EM2(n) provides a high voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM2(n) is a low voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the light emitting element is an organic light emitting diode O1;
  • the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3;
  • the compensation control circuit includes a first transistor T1, the on-off control circuit includes a second transistor T2; the energy storage circuit includes a storage capacitor Cst;
  • the gate of the first transistor T1 is electrically connected to the n-th stage third scanning terminal NG(n), the source of the first transistor T1 is electrically connected to the fourth node N4, and the drain of the first transistor T1 is electrically connected to the third node N3;
  • the gate of the second transistor T2 is electrically connected to the power supply voltage terminal VDD, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the fourth node N4;
  • the first plate of the storage capacitor Cst is electrically connected to the fourth node N4, and the second plate of the storage capacitor Cst is electrically connected to the power supply voltage terminal VDD;
  • the first light emitting control circuit includes a third transistor T3, the second light emitting control circuit includes a fourth transistor T4, and the first initialization circuit includes a fifth transistor T5;
  • the gate of the third transistor T3 is connected to the n-th stage second light emitting control signal EM2(n), the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;
  • the gate of the fourth transistor T4 is connected to the n-th level second light emitting control signal EM2(n), the source of the fourth transistor T4 is electrically connected to the third node N3, the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1; and the cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal.
  • the gate of the fifth transistor T5 is electrically connected to the third scanning terminal NG(n-5) of the n-5th stage, the source of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the drain of the fifth transistor T5 is electrically connected to the first node N1;
  • the second initialization circuit includes a sixth transistor T6;
  • the gate of the sixth transistor T6 is electrically connected to the reset control terminal RST, the source of the sixth transistor T6 is electrically connected to the second initial voltage terminal I2, and the drain of the sixth transistor T6 is electrically connected to the second node N2;
  • the data writing circuit includes a seventh transistor T7, and the third initialization circuit includes an eighth transistor T8;
  • the gate of the eighth transistor T8 is electrically connected to the nth stage first scanning terminal GT(n), the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the anode of the organic light emitting diode O1.
  • T1 and T2 are both n-type transistors, and the other transistors are all p-type transistors, but the present invention is not limited thereto.
  • the compensation control terminal is the n-th level third scanning terminal NG(n)
  • the on-off control terminal is the low level terminal VGL
  • the first light-emitting control terminal is connected to the n-th level second light-emitting control signal EM2(n)
  • the second light-emitting control terminal is connected to the n-th level second light-emitting control signal EM2(n)
  • the first initial control terminal is the n-5th level third scanning terminal NG(n-5)
  • the second initial control terminal is the reset control terminal RST
  • the write control terminal is the n-th level first scanning terminal GT(n)
  • the third initial control terminal is the n-th level first scanning terminal GT(n).
  • FIG. 35 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 34 .
  • At least one embodiment of the pixel circuit shown in FIG34 of the present disclosure is in operation.
  • the display cycle may include a first initialization phase S11, a writing phase S2, a second initialization phase S12 and a light emitting phase S3 which are arranged in sequence;
  • EM2(n) is a high voltage signal
  • NG(n-5) provides a high voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T5 and T2 are turned on
  • I1 provides a first initial voltage Vinit1 to the first node N1 to enable DT to be turned on at the beginning of the write phase S2
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM2(n) is a high voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a high voltage signal
  • GT(n) provides a low voltage signal
  • RST provides a high voltage signal
  • T1 and T2 are turned on
  • T7 is turned on
  • DL passes the data voltage Vdata to the second node N2;
  • DT is turned on, charging Cst through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, and DT is turned off to perform threshold voltage compensation;
  • Vth is the threshold voltage of DT;
  • EM2(n) provides a high voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a low voltage signal
  • T6 and T8 are turned on
  • I2 provides a second initial voltage Vinit2 to the second node N2 to improve the hysteresis of DT
  • I3 provides a third initial voltage Vinit3 to the anode of O1 to clear the residual charge on the anode of O1;
  • EM2(n) is a low voltage signal
  • NG(n-5) provides a low voltage signal
  • NG(n) provides a low voltage signal
  • GT(n) provides a high voltage signal
  • RST provides a high voltage signal
  • T3 and T4 are turned on, and DT drives O1 to emit light.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

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Abstract

一种像素电路和显示装置，像素电路包括发光元件（E1）和驱动晶体管（DT），驱动晶体管（DT）的第一极与第一电压端（V1）电连接，像素电路还包括设置于驱动晶体管（DT）的栅极与驱动晶体管（DT）的第二极之间的至少两个晶体管，驱动晶体管（DT）的第二极与发光元件（E1）电连接，驱动晶体管（DT）用于产生驱动发光元件（E1）的驱动电流，至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同。像素电路采用设置于驱动晶体管（DT）的栅极与驱动晶体管（DT）的第二极之间的至少两个晶体管，至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同，被不同的控制信号控制，以减少在初始化阶段，对驱动晶体管（DT）的应力的影响。

Description

像素电路和显示装置
相关申请的交叉引用
本申请主张在2024年3月13日在中国提交的中国专利申请号No.202410288313.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路和显示装置。
背景技术
随着OLED(有机发光而二极管)行业的不断更新迭代，也随之提出了很对适用于各种新功能的像素电路。针对目前常规使用的LTPS(低温多晶硅)或LTPO(低温多晶氧化物)像素电路，都存在一个专利问题：补偿晶体管直接连接驱动晶体管的栅极和驱动晶体管的漏极。在相关技术中，为了减少采用的GOA(设置于阵列基板上的栅极驱动电路)电路的个数，用于为驱动晶体管的栅极电位进行初始化的晶体管和用于进行补偿控制的补偿晶体管可能同时打开，而如若所述驱动晶体管的栅极与所述驱动晶体管的第二极之间不存在另一个栅极接入不同控制信号的晶体管时，在所述用于为驱动晶体管的栅极电位进行初始化的晶体管和用于进行补偿控制的补偿晶体管同时打开时，初始化电压会同时写入驱动晶体管的栅极和所述驱动晶体管的第二极，这样会影响驱动晶体管的stress(应力)。
发明内容
本公开的主要目的在于提供一种像素电路和显示装置，解决现有技术中补偿晶体管直接连接驱动晶体管的栅极和驱动晶体管的漏极，而使得用于为驱动晶体管的栅极电位进行初始化的晶体管和用于进行补偿控制的补偿晶体管同时打开时，初始化电压会同时写入驱动晶体管的栅极和所述驱动晶体管的第二极，这样会影响驱动晶体管的stress(应力)的问题。
在一个方面中，本公开实施例提供一种像素电路，包括发光元件和驱动晶体管；所述驱动晶体管的第一极与第一电压端电连接；
所述像素电路还包括设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间的至少两个晶体管；所述驱动晶体管的第二极与发光元件电连接，所述驱动晶体管用于产生驱动所述发光元件的驱动电流；
所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同。
可选的，本公开至少一实施例所述的像素电路还包括第一发光控制电路和第二发光控制电路；
所述驱动晶体管的第一极通过所述第一发光控制电路与所述第一电压端电连接，所述驱动晶体管的第二极通过所述第二发光控制电路与所述发光元件的第一极电连接；所述发光元件的第二极与第二电压端电连接；
所述第一发光控制电路与第一发光控制端电连接，用于在所述第一发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第一极与所述第一电压端之间连通；
所述第二发光控制电路与第二发光控制端电连接，用于在所述第二发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第二极与所述发光元件的第一极之间连通。
可选的，所述第一发光控制端与所述第二发光控制端不同，所述第一发光控制端提供的控制信号与所述第二发光控制端提供的控制信号不同。
可选的，本公开至少一实施例所述的像素电路包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
所述补偿控制电路分别与补偿控制端、所述第一节点和第四节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
所述通断控制电路分别与通断控制端、所述第三节点和所述第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第三节点与所述第四节点之间连通；
所述储能电路与所述第一节点电连接，用于储存电能。
可选的，本公开至少一实施例所述的像素电路包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
所述补偿控制电路分别与补偿控制端、第四节点和第三节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第四节点与所述第三节点之间连通；
所述通断控制电路分别与通断控制端、所述第一节点和第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
所述储能电路与所述第四节点电连接，用于储存电能。
可选的，本公开至少一实施例所述的像素电路包括第一初始化电路；
所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第一节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第一节点。
可选的，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n级第二扫描端；或者，
所述补偿控制端为第n级第一扫描端；所述通断控制电路包括的晶体管为p型晶体管，所述通断控制端为低电平端；或者，
所述补偿控制端为第n级第三扫描端；所述通断控制电路包括的晶体管为n型晶体管，所述通断控制端为高电平端；
n为正整数。
可选的，所述第一发光控制端和所述第二发光控制端接入第n级第一发光控制信号，所述补偿控制端接入第n级第二发光控制信号，所述第一初始控制端接入第n-a级第二发光控制信号；n和a为正整数；或者，
所述第一发光控制端为第n级发光控制端，所述第二发光控制端为第n+1级发光控制端，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n-1级第一扫描端；n为正整数；或者，
所述第一发光控制端接入第n级第一发光控制信号，所述第二发光控制端接入第n级第二发光控制信号，所述补偿控制端接入第n级第三发光控制信号，所述第一初始控制端接入第n-b级第三发光控制信号；n和b为正整数。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第二节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路和第三初始化电路；
所述数据写入电路分别与写入控制端、数据线和所述第二节点电连接，用于在所述写入控制端提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第三初始化电路分别与第三初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第三初始控制端提供的第三初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
可选的，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第四节点电连接；
所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第三节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述存储电容的第一极板与所述第一节点电连接，所述存储电容的第二极板与直流电压端电连接。
可选的，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第四节点电连接，所述第一晶体管的第二极与所述第三节点电连接；
所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述存储电容的第一极板与所述第四节点电连接，所述存储电容的第二极板与直流电压端电连接。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述第一初始化电路包括第五晶体管；
所述第三晶体管的栅极与所述第一发光控制端电连接，所述第三晶体管的第一极与第一电压端电连接，所述第三晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第四晶体管的栅极与所述第二发光控制端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接；
所述第五晶体管的栅极与所述第一初始控制端电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述第一节点电连接。
可选的，所述第二初始化电路包括第六晶体管；
所述第六晶体管的栅极与所述第二初始控制端电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，所述数据写入电路包括第七晶体管，所述第三初始化电路包括第八晶体管；
所述第七晶体管的栅极与所述写入控制端电连接，所述第七晶体管的第一极与所述数据线电连接，所述第七晶体管的第二极与所述第二节点电连接；
所述第八晶体管的栅极与所述第三初始控制端电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与所述发光元件的第一极电连接。
在第二个方面中，本公开实施例提供一种显示装置，其特征在于，包括上述的像素电路。
本公开至少一实施例所述像素电路和显示装置采用设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间的至少两个晶体管，所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同，被不同的控制信号控制，以减少在初始化阶段，对驱动晶体管的应力的影响。
附图说明
图1是本公开至少一实施例所述的像素电路的结构图；
图2是本公开至少一实施例所述的像素电路的结构图；
图3是本公开至少一实施例所述的像素电路的结构图；
图4是本公开至少一实施例所述的像素电路的结构图；
图5是本公开至少一实施例所述的像素电路的结构图；
图6是本公开至少一实施例所述的像素电路的结构图；
图7是本公开至少一实施例所述的像素电路的结构图；
图8是本公开至少一实施例所述的像素电路的结构图；
图9是本公开至少一实施例所述的像素电路的结构图；
图10A是本公开至少一实施例所述的像素电路的电路图；
图10B是本公开至少一实施例所述的像素电路的电路图；
图11A是图10A所示的像素电路的至少一实施例的工作时序图；
图11B是图10B所示的像素电路的至少一实施例的工作时序图；
图12是本公开至少一实施例所述的像素电路的电路图；
图13是图12所示的像素电路的至少一实施例的工作时序图；
图14是本公开至少一实施例所述的像素电路的电路图；
图15是图14所示的像素电路的至少一实施例的工作时序图；
图16是本公开至少一实施例所述的像素电路的电路图；
图17是图16所示的像素电路的至少一实施例的工作时序图；
图18是本公开至少一实施例所述的像素电路的电路图；
图19是图18所示的像素电路的至少一实施例的工作时序图；
图20是本公开至少一实施例所述的像素电路的电路图；
图21是图20所示的像素电路的至少一实施例的工作时序图；
图22是本公开至少一实施例所述的像素电路的电路图；
图23是图22所示的像素电路的至少一实施例的工作时序图；
图24是本公开至少一实施例所述的像素电路的电路图；
图25是图24所示的像素电路的至少一实施例的工作时序图；
图26是本公开至少一实施例所述的像素电路的电路图；
图27是图26所示的像素电路的至少一实施例的工作时序图；
图28是本公开至少一实施例所述的像素电路的电路图；
图29是图28所示的像素电路的至少一实施例的工作时序图；
图30是本公开至少一实施例所述的像素电路的电路图；
图31是图30所示的像素电路的至少一实施例的工作时序图；
图32是本公开至少一实施例所述的像素电路的电路图；
图33是图32所示的像素电路的至少一实施例的工作时序图；
图34是本公开至少一实施例所述的像素电路的电路图；
图35是图34所示的像素电路的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的像素电路包括发光元件和驱动晶体管；所述驱动晶体管的第一极与第一电压端电连接；
所述像素电路还包括设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间的至少两个晶体管；所述驱动晶体管的第二极与发光元件电连接，所述驱动晶体管用于产生驱动所述发光元件的驱动电流；
所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同。
在具体实施时，所述像素电路可以包括发光元件和驱动晶体管，在所述驱动晶体管的栅极与所述驱动晶体管的第二极之间可以设置有至少两个晶体管，并且，所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同，被不同的控制信号控制。
在相关的像素电路中，为了减少采用的GOA(设置于阵列基板上的栅极驱动电路)电路的个数，用于为驱动晶体管的栅极电位进行初始化的晶体管和用于进行补偿控制的补偿晶体管可能同时打开，而如若所述驱动晶体管的栅极与所述驱动晶体管的第二极之间不存在另一个栅极接入不同控制信号的晶体管时，在所述用于为驱动晶体管的栅极电位进行初始化的晶体管和用于进行补偿控制的补偿晶体管同时打开时，初始化电压会同时写入驱动晶体管的栅极和所述驱动晶体管的第二极，这样会影响驱动晶体管的stress(应力)。基于如上问题，本公开至少一实施例所述像素电路采用设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间的至少两个晶体管，所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同，被不同的控制信号控制，以减少在初始化阶段，对驱动晶体管的应力的影响。
本公开至少一实施例所述的所述的像素电路还包括第一发光控制电路和第二发光控制电路；
所述驱动晶体管的第一极通过所述第一发光控制电路与所述第一电压端电连接，所述驱动晶体管的第二极通过所述第二发光控制电路与所述发光元件的第一极电连接；所述发光元件的第二极与第二电压端电连接；
所述第一发光控制电路与第一发光控制端电连接，用于在所述第一发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第一极与所述第一电压端之间连通；
所述第二发光控制电路与第二发光控制端电连接，用于在所述第二发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第二极与所述发光元件的第一极之间连通。
可选的，所述第一电压端可以为电源电压端，所述第二电压端可以为低电压端，但不以此为限。
在具体实施时，所述像素电路还可以包括第一发光控制电路和第二发光控制电路，所述第一发光控制电路可以设置于驱动晶体管的第一极与第一电压端之间，所述第二发光控制电路可以设置于驱动晶体管的第二极与所述发光元件之间，第一发光控制电路和第二发光控制电路可以进行发光控制。
在本公开至少一实施例中，所述第一发光控制端与所述第二发光控制端不同，所述第一发光控制端提供的控制信号与所述第二发光控制端提供的控制信号不同。
在具体实施时，所述第一发光控制端可以与所述第二发光控制端不同，所述第一发光控制端提供的控制信号与所述第二发光控制端提供的控制信号可以不同，但不以此为限。
可选的，所述第一发光控制端也可以与所述第二发光控制端相同。
如图1所示，本公开至少一实施例所述的像素电路包括发光元件E1和驱动晶体管DT；
本公开至少一实施例所述的像素电路还包括第一发光控制电路11和第二发光控制电路12；
所述驱动晶体管DT的栅极与第一节点N1电连接；
所述驱动晶体管DT的源极通过所述第一发光控制电路11与第一电压端V1电连接，所述驱动晶体管DT的漏极通过所述第二发光控制电路12与所述发光元件E1的第一极电连接；所述发光元件E1的第二极与第二电压端V2电连接；
所述第一发光控制电路11与第一发光控制端EMT1电连接，用于在所述第一发光控制端EMT1提供的控制信号的控制下，控制所述驱动晶体管DT的源极与所述第一电压端V1之间连通；
所述第二发光控制电路12与第二发光控制端EMT2电连接，用于在所述第二发光控制端EMT2提供的控制信号的控制下，控制所述驱动晶体管DT的漏极与所述发光元件E1的第一极之间连通。
本公开至少一实施例所述的像素电路包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
所述补偿控制电路分别与补偿控制端、所述第一节点和第四节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
所述通断控制电路分别与通断控制端、所述第三节点和所述第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第三节点与所述第四节点之间连通；
所述储能电路与所述第一节点电连接，用于储存电能。
在具体实施时，所述像素电路可以包括补偿控制电路、通断控制电路和储能电路，所述补偿控制电路和所述通断控制电路设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间，所述补偿控制电路包括的晶体管的栅极与补偿控制端电连接，在所述补偿控制端提供的补偿控制信号的控制下工作；所述通断控制电路包括的晶体管的栅极与通断控制端电连接，在所述通断控制端提供的通断控制信号的控制下工作；所述补偿控制电路可以设置于第一节点与第四节点之间，所述通断控制电路可以设置于第三节点和第四节点之间。
如图2所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路包括补偿控制电路21、通断控制电路22和储能电路20；所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路21分别与补偿控制端SC、所述第一节点N1和第四节点N4电连接，用于在所述补偿控制端SC提供的补偿控制信号的控制下，控制所述第一节点N1与所述第四节点N4之间连通；
所述通断控制电路22分别与通断控制端ST、所述第三节点N3和所述第四节点N4电连接，用于在所述通断控制端ST提供的通断控制信号的控制下，控制所述第三节点N3与所述第四节点N4之间连通；
所述储能电路20与所述第一节点N1电连接，用于储存电能。
本公开至少一实施例所述的所述的像素电路包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
所述补偿控制电路分别与补偿控制端、第四节点和第三节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第四节点与所述第三节点之间连通；
所述通断控制电路分别与通断控制端、所述第一节点和第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
所述储能电路与所述第四节点电连接，用于储存电能。
在具体实施时，所述像素电路可以包括补偿控制电路、通断控制电路和储能电路，所述补偿控制电路、所述通断控制电路和所述储能电路可以设置于驱动晶体管的栅极与所述驱动晶体管的第二极之间，所述补偿控制电路包括的晶体管的栅极与补偿控制端电连接，在所述补偿控制端提供的补偿控制信号的控制下工作；所述通断控制电路包括的晶体管的栅极与通断控制端电连接，在所述通断控制端提供的通断控制信号的控制下工作；所述补偿控制电路可以设置于第一节点与第三节点之间，所述通断控制电路可以设置于第一节点与第四节点之间。
如图3所示，在图1所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路包括补偿控制电路21、通断控制电路22和储能电路20；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路21分别与补偿控制端SC、第四节点N4和第三节点N3电连接，用于在所述补偿控制端SC提供的补偿控制信号的控制下，控制所述第四节点N4与所述第三节点N3之间连通；
所述通断控制电路22分别与通断控制端ST、所述第一节点N1和第四节点N4电连接，用于在所述通断控制端ST提供的通断控制信号的控制下，控制所述第一节点N1与所述第四节点N4之间连通；
所述储能电路20与所述第四节点N4电连接，用于储存电能。
本公开至少一实施例所述的像素电路包括第一初始化电路；
所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第一节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第一节点。
在具体实施时，所述像素电路可以包括第一初始化电路，所述第一初始化电路可以在初始化阶段，在第一初始控制信号的控制下，将第一初始电压写入第一节点，以使得在补偿阶段开始时，所述驱动晶体管能够导通。
如图4所示，在图2所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路包括第一初始化电路41；
所述第一初始化电路41分别与第一初始控制端SI1、第一初始电压端I1和所述第一节点N1电连接，用于在所述第一初始控制端SI1提供的第一初始控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第一节点N1。
如图5所示，在图3所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路包括第一初始化电路41；
所述第一初始化电路41分别与第一初始控制端SI1、第一初始电压端I1和所述第一节点N1电连接，用于在所述第一初始控制端SI1提供的第一初始控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第一节点N1。
在本公开至少一实施例中，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n级第二扫描端；或者，
所述补偿控制端为第n级第一扫描端；所述通断控制电路包括的晶体管为p型晶体管，所述通断控制端为低电平端；或者，
所述补偿控制端为第n级第三扫描端；所述通断控制电路包括的晶体管为n型晶体管，所述通断控制端为高电平端；例如，所述高电平端可以为电源电压端；
n为正整数。
在本公开至少一实施例中，所述第一发光控制端和所述第二发光控制端接入第n级第一发光控制信号，所述补偿控制端接入第n级第二发光控制信号，所述第一初始控制端接入第n-a级第二发光控制信号；n和a为正整数；或者，
所述第一发光控制端为第n级发光控制端，所述第二发光控制端为第n+1级发光控制端，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n-1级第一扫描端；n为正整数；或者，
所述第一发光控制端接入第n级第一发光控制信号，所述第二发光控制端接入第n级第二发光控制信号，所述补偿控制端接入第n级第三发光控制信号，所述第一初始控制端接入第n-b级第三发光控制信号；n和b为正整数。
本公开至少一实施例所述的像素电路还包括第二初始化电路；
所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第二节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第二节点。
在具体实施时，所述像素电路还可以包括第二初始化电路，第二初始化电路在第二初始控制信号的控制下，将第二初始电压写入第二节点，以改善迟滞现象。
本公开至少一实施例所述的像素电路还包括数据写入电路和第三初始化电路；
所述数据写入电路分别与写入控制端、数据线和所述第二节点电连接，用于在所述写入控制端提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第三初始化电路分别与第三初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第三初始控制端提供的第三初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
在具体实施时，所述像素电路还可以包括数据写入电路和第三初始化电路；
所述数据写入电路在写入控制信号的控制下，将数据电压写入第二节点，以进行数据电压写入，第三初始化电路在第三初始控制信号的控制下，将第三初始电压写入发光元件的第一极，以清除所述发光元件的第一极残留的电荷。
可选的，所述写入控制端可以为第n级第一扫描端，所述第三初始控制端可以为第n级第一扫描端，所述第二初始控制端可以为复位控制端；或者，
所述写入控制端可以为第n级第一扫描端，所述第三初始控制端可以为复位控制端，所述第二初始控制端可以为复位控制端；
但不以此为限。
如图6所示，在图4所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路61和第三初始化电路62；
所述数据写入电路61分别与写入控制端GW、数据线DL和所述第二节点N2电连接，用于在所述写入控制端GW提供的写入控制信号的控制下，将所述数据线DL提供的数据电压Vdata写入所述第二节点N2；
所述第三初始化电路62分别与第三初始控制端SI3、第三初始电压端I3和所述发光元件的第一极电连接，用于在所述第三初始控制端SI3提供的第三初始控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压Vinit3写入所述发光元件E1的第一极。
如图7所示，在图5所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括数据写入电路61和第三初始化电路62；
所述数据写入电路61分别与写入控制端GW、数据线DL和所述第二节点N2电连接，用于在所述写入控制端GW提供的写入控制信号的控制下，将所述数据线DL提供的数据电压Vdata写入所述第二节点N2；
所述第三初始化电路62分别与第三初始控制端SI3、第三初始电压端I3和所述发光元件的第一极电连接，用于在所述第三初始控制端SI3提供的第三初始控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压Vinit3写入所述发光元件E1的第一极。
如图8所示，在图6所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二初始化电路80；
所述第二初始化电路80分别与第二初始控制端SI2、第二初始电压端I2和所述第二节点N2电连接，用于在所述第二初始控制端SI2提供的第二初始控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第二节点N2，以能够改善迟滞。
如图9所示，在图7所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还包括第二初始化电路80；
所述第二初始化电路80分别与第二初始控制端SI2、第二初始电压端I2和所述第二节点N2电连接，用于在所述第二初始控制端SI2提供的第二初始控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第二节点N2，以能够改善迟滞。
可选的，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第四节点电连接；
所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第三节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述存储电容的第一极板与所述第一节点电连接，所述存储电容的第二极板与直流电压端电连接。
可选的，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第四节点电连接，所述第一晶体管的第二极与所述第三节点电连接；
所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
所述存储电容的第一极板与所述第四节点电连接，所述存储电容的第二极板与直流电压端电连接。
可选的，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述第一初始化电路包括第五晶体管；
所述第三晶体管的栅极与所述第一发光控制端电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第四晶体管的栅极与所述第二发光控制端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接；
所述第五晶体管的栅极与所述第一初始控制端电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述第一节点电连接。
可选的，所述第二初始化电路包括第六晶体管；
所述第六晶体管的栅极与所述第二初始控制端电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述第二节点电连接。
可选的，所述数据写入电路包括第七晶体管，所述第三初始化电路包括第八晶体管；
所述第七晶体管的栅极与所述写入控制端电连接，所述第七晶体管的第一极与所述数据线电连接，所述第七晶体管的第二极与所述第二节点电连接；
所述第八晶体管的栅极与所述第三初始控制端电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与所述发光元件的第一极电连接。
如图10A所示，在图6所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极与第n级第一扫描端GT(n)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与第n级第二扫描端GT2(n)电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第一发光控制信号EM1(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-1级第一扫描端GT(n-1)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第三扫描端GT3(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图10A所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图10A所示的像素电路的至少一实施例中，补偿控制端为第n级第一扫描端GT(n)，通断控制端为第n级第二扫描端GT2(n)，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第一发光控制信号EM1(n)，第一初始控制端为第n-1级第一扫描端GT(n-1)，写入控制端为第n级第三扫描端GT3(n)，第三初始控制端为第n级第一扫描端GT(n)。
图11A是图10A所示的像素电路的至少一实施例的工作时序图。
如图11A所示，本公开图10A所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，GT(n-1)提供低电压信号，GT2(n)提供高电压信号，GT3(n)提供高电压信号，T5打开，T8打开，I1提供第一初始电压Vinit1，I3提供第三初始电压Vinit3，将Vinit1写入第一节点N1，使得在写入阶段S2开始时，DT能够导通；将Vinit3写入O1的阳极，清除O1的阳极残留的电荷；
在写入阶段S2，EM1(n)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，GT2(n)提供低电压信号，GT3(n)提供低电压信号，T1和T2打开，T7打开，DL提供数据电压Vdata至N2，以进行数据电压写入；
在写入阶段S2开始时，DT打开，通过Vdata为Cst充电，直至N1的电位变为Vdata+Vth，DT关断，以进行阈值电压补偿；Vth为DT的阈值电压；
在发光阶段S3，EM(n)为低电压信号，GT(n-1)提供高电压信号，GT(n)提供高电压信号，GT2(n)提供低电压信号，GT3(n)提供高电压信号，T3和T4打开，T2打开，DT驱动O1发光。
如图11A所示，本公开图10A所示的像素电路的至少一实施例在工作时，GT(n-1)提供的第n-1级第一扫描信号和GT(n)提供的第n级第一扫描信号存在交叠的有效时间段，此时T1和T5同时打开，此时如果DT的栅极与DT的漏极之间仅存在T1，则Vinit1同时写入DT的栅极和DT的漏极，会影响DT的stress；
在发光阶段S3，可以通过T2控制电源电压端VDD提供的电源电压到达O1的阳极的时间，电源电压在DT的源极停留的时间有利于改善DT的迟滞，改善显示残像现象。
如图10B所示，在图6所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极与第n级第一扫描端GT(n)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与第n级第二扫描端GT2(n)电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第一发光控制信号EM1(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-1级第一扫描端GT(n-1)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图10B所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图10B所示的像素电路的至少一实施例中，补偿控制端为第n级第一扫描端GT(n)，通断控制端为第n级第二扫描端GT2(n)，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第一发光控制信号EM1(n)，第一初始控制端为第n-1级第一扫描端GT(n-1)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
图11B是图10B所示的像素电路的至少一实施例的工作时序图。
如图11B所示，本公开图10B所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，GT(n-1)提供低电压信号，GT(n)提供高电压信号，GT2(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，GT2(n)提供低电压信号，T1和T2打开，T7打开，DL提供数据电压Vdata至第二节点N2，N1与N3之间连通；T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在发光阶段S3，EM1(n)为低电压信号，GT(n-1)提供高电压信号，GT(n)提供高电压信号，GT2(n)提供低电压信号，T3、T4和T2打开，DT驱动O1发光。
本公开图12所示的像素电路的至少一实施例与本公开图10所示的像素电路的至少一实施例的区别在于：T2的栅极与低电平端VGL电连接，以能减少像素电路采用的控制信号的个数，以减少采用的生成控制信号的GOA(设置于阵列基板上的栅极驱动电路)电路的个数。
图13是图12所示的像素电路的至少一实施例的工作时序图。
如图13所示，本公开图12所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，GT(n-1)提供低电压信号，GT(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，T1和T2打开，T7打开，DL提供数据电压Vdata至第二节点N2，N1与N3之间连通；T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在发光阶段S3，EM1(n)为低电压信号，GT(n-1)提供高电压信号，GT(n)提供高电压信号，T3、T4和T2打开，DT驱动O1发光。
如图14所示，在图6所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极接入第n级第二发光控制信号EM2(n)，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第一发光控制信号EM1(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-7级第二发光控制信号EM2(n-7)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图14所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图14所示的像素电路的至少一实施例中，补偿控制端接入第n级第二发光控制信号EM2(n)，通断控制端为低电平端，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第一发光控制信号EM1(n)，第一初始控制端接入第n-7级第二发光控制信号EM2(n-7)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
图15是本公开图14所示的像素电路的至少一实施例的工作时序图。
在图14所示的像素电路的至少一实施例中，T2的栅极可以被替换为与第n级第二扫描端电连接。
如图15所示，本公开图14所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM2(n-7)为低电压信号，GT(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，EM2(n-7)为高电压信号，EM2(n)为低电压信号，GT(n)提供低电压信号，DL提供数据电压Vdata至第二节点N2，T1导通，T2导通，N1与N3之间连通；T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在写入阶段S2开始时，DT导通，通过Vdata为Cst，以改变N1的电位，直至N1的电位变为Vdata+Vth，DT关断，停止充电，以进行阈值电压补偿；Vth为DT的阈值电压；
在发光阶段S3，EM1(n)为低电压信号，EM2(n)为高电压信号，EM2(n-7)为高电压信号，GT(n)提供高电压信号，T3和T4打开，T2打开，DT驱动O1发光。
如图16所示，在图6所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极与第n级第一扫描端GT(n)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n+1级第一发光控制信号EM1(n+1)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-1级第一扫描端GT(n-1)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图16所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图16所示的像素电路的至少一实施例中，补偿控制端为第n级第一扫描端GT(n)，通断控制端为低电平端，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n+1级第一发光控制信号EM1(n+1)，第一初始控制端为第n-1级第一扫描端GT(n-1)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图16所示的像素电路的至少一实施例中，T2的栅极可以被替换为与第n级第二扫描端电连接。
图17是本公开图16所示的像素电路的至少一实施例的工作时序图。
如图17所示，本公开图16所示的像素电路的至少一实施例在工作时，显示周期包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM1(n+1)为高电压信号，GT(n-1)提供低电压信号，GT(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，EM1(n+1)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；T1和T2打开，T7打开，DL提供数据电压Vdata至第二节点N2；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，以改变第一节点N1的电位，直至N1的电位变为Vdata+Vth，DT关断，停止充电，以进行阈值电压补偿；Vth为DT的阈值电压；
在发光阶段S3，EM1(n)为低电压信号，EM1(n+1)为低电压信号，T3和T4打开，T2打开，DT驱动O1发光。
如图18所示，在图6所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极接入第n级第三发光控制信号EM3(n)，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-5级第三发光控制信号EM3(n-5)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图18所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图18所示的像素电路的至少一实施例中，补偿控制端接入第n级第三发光控制信号，通断控制端为低电平端，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端接入第n-5级第三发光控制信号EM3(n-5)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图18所示的像素电路的至少一实施例中，T2的栅极可以被替换为与第n级第二扫描端电连接。
图19是本公开图18所示的像素电路的至少一实施例的工作时序图。
如图19所示，本公开图18所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为低电压信号，GT(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够打开；
在写入阶段S2，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为低电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；DL提供数据电压Vdata，T7打开，T1和T2打开；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，改变第一节点N1的电位，直至第一节点N1的电位变为Vdata+Vth，DT关断，停止充电，以进行阈值电压补偿；
在发光阶段S3，EM1(n)为低电压信号，EM2(n)为低电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，T3和T4打开，T2打开，DT驱动O1发光。
在图18所示的至少一中，EM1(n)和EM2(n)也可以为同一EOA电路(EOA电路可以为生成控制信号的驱动电路)生成的相邻级发光控制信号。
如图20所示，在图8所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极接入第n级第三发光控制信号EM3(n)，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-5级第三发光控制信号EM3(n-5)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述第二初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与复位控制端RST电连接，所述第六晶体管T6的源极与所述第二初始电压端I2电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述复位控制端RST电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图20所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图20所示的像素电路的至少一实施例中，补偿控制端接入第n级第三发光控制信号，通断控制端为低电平端，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端接入第n-5级第三发光控制信号EM3(n-5)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为复位控制端RST，第二初始控制端为复位控制端RST。
在图20所示的像素电路的至少一实施例中，T2的栅极可以被替换为与第n级第二扫描端电连接。
图21是本公开图20所示的像素电路的至少一实施例的工作时序图。
如图21所示，本公开图20所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一初始化阶段S11、写入阶段S2、第二初始化阶段S12和发光阶段S3；
在第一初始化阶段S11，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为低电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，RST提供低电压信号，T5、T6和T8打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能导通；I2提供第二初始电压Vinit2至第二节点N2，以改善迟滞；I3提供第三初始电压Vinit3至O1的阳极，以清除O1的阳极残留的电荷；
在写入阶段S2，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为低电压信号，GT(n)提供低电压信号，RST提供高电压信号，T7打开，T2打开，T1打开，DL提供数据电压Vdata至第二节点N2，通过Vdata为Cst充电，改变N1的电位，直至N1的电位变为Vdata+Vth，DT关断，以停止充电，进行阈值电压补偿；
在第二初始化阶段S12，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，RST提供低电压信号，T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，以改善迟滞；I3提供第三初始电压Vinit3至O1的阳极，以清除O1的阳极残留的电荷；
在发光阶段S3，EM1(n)为低电压信号，EM2(n)为低电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，RST提供高电压信号，T3和T4打开，T2打开，DT驱动O1发光。
如图22所示，在图7所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极与第n级第一扫描端GT(n)电连接，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第一发光控制信号EM1(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-1级第一扫描端GT(n-1)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图22所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图22所示的像素电路的至少一实施例中，补偿控制端为第n级第一扫描端GT(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第一发光控制信号EM1(n)，第一初始控制端为第n-1级第一扫描端GT(n-1)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图22所示的像素电路的至少一实施例中，T2的栅极可以替换为与提供控制信号的控制端电连接，该控制端在初始化阶段、写入阶段和发光阶段提供低电压信号，以使得像素电路可以工作。
图23是图22所示的像素电路的至少一实施例的工作时序图。
如图23所示，本公开图22所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，GT(n-1)提供低电压信号，GT(n)提供高电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；T7打开，DL提供数据电压Vdata至第二节点N2；T1和T2打开；
在写入阶段S2开始时，DT打开，通过Vdata为Cst充电，改变第一节点N1的电位，直至N1的电位变为Vdata+Vth，DT关断，停止充电，进行阈值电压补偿；Vth为DT的阈值电压；
在发光阶段S3，EM1(n)为低电压信号，GT(n-1)提供高电压信号，GT(n)提供高电压信号，T3和T4打开，DT驱动O1发光。
如图24所示，在图7所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极接入第n级第二发光控制信号EM2(n)，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第一发光控制信号EM1(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-7级第二发光控制信号EM2(n-7)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图24所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图24所示的像素电路的至少一实施例中，补偿控制端接入第n级第二发光控制信号EM2(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第一发光控制信号EM1(n)，第一初始控制端接入第n-7级第二发光控制信号EM2(n-7)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图24所示的像素电路的至少一实施例中，T2的栅极可以替换为与提供控制信号的控制端电连接，该控制端在初始化阶段、写入阶段和发光阶段提供低电压信号，以使得像素电路可以工作。
图25是图24所示的像素电路的至少一实施例的工作时序图。
如图25所示，本公开图24所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM2(n-7)为低电压信号，GT(n)提供高电压信号，T2打开，T5打开，T2打开，I3提供第三初始电压Vinit3至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，EM2(n-7)为高电压信号，EM2(n)提供低电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；T7打开，T1和T2打开，DL提供数据电压Vdata至第二节点N2，通过Vdata为Cst充电，改变第一节点N1的电位，直至第一节点N1的电位变为Vdata+Vth，DT关断，进行阈值电压补偿；
在发光阶段S3，EM1(n)为低电压信号，EM2(n-7)为高电压信号，EM2(n)提供高电压信号，GT(n)提供高电压信号，T3和T4打开，DT驱动O1发光。
如图26所示，在图7所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极与第n级第一扫描端GT(n)电连接，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n+1级第一发光控制信号EM1(n+1)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-1级第一扫描端GT(n-1)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图26所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图26所示的像素电路的至少一实施例中，补偿控制端为第n级第一扫描端GT(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n+1级第一发光控制信号EM1(n+1)，第一初始控制端为第n-1级第一扫描端GT(n-1)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图26所示的像素电路的至少一实施例中，T2的栅极可以替换为与提供控制信号的控制端电连接，该控制端在初始化阶段、写入阶段和发光阶段提供低电压信号，以使得像素电路可以工作。
图27是图26所示的像素电路的至少一实施例的工作时序图。
如图27所示，本公开图26所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM1(n+1)为高电压信号，GT(n-1)提供低电压信号，GT(n)提供高电压信号，T2打开，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，EM1(n+1)为高电压信号，GT(n-1)提供高电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；T1和T2打开，T7打开，DL提供数据电压Vdata至第二节点N2，通过Vdata为Cst充电，改变第一节点N1的电位，直至DT关断，N1的电位为Vdata+Vth，以进行阈值电压补偿；Vth为DTFT的阈值电压；
在发光阶段S3，EM1(n)为低电压信号，EM1(n+1)为低电压信号，GT(n-1)提供高电压信号，GT(n)提供高电压信号，T3和T4打开，DT驱动O1发光。
如图28所示，在图7所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极接入第n级第三发光控制信号EM3(n)，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-5级第三发光控制信号EM3(n-5)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图28所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图28所示的像素电路的至少一实施例中，补偿控制端接入第n级第三发光控制信号EM3(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端接入第n-5级第三发光控制信号EM3(n-5)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图28所示的像素电路的至少一实施例中，T2的栅极可以替换为与提供控制信号的控制端电连接，该控制端在初始化阶段、写入阶段和发光阶段提供低电压信号，以使得像素电路可以工作。
图29是图28所示的像素电路的至少一实施例的工作时序图。
如图29所示，本公开图28所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的初始化阶段S1、写入阶段S2和发光阶段S3；
在初始化阶段S1，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为低电压信号，GT(n)提供高电压信号，T5打开，T2打开，I1提供第一初始电压Vinit1至第一节点N1，以使得写入阶段S2开始时，DT能够导通；
在写入阶段S2，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为低电压信号，GT(n)提供低电压信号，T8打开，I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；T1和T2打开，T7打开，DL提供数据电压Vdata至第二节点N2；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，改变N1的电位，直至N1的电位变为Vdata+Vth，DT关断，进行阈值电压补偿，Vth为DT的阈值电压；
在发光阶段S3，EM1(n)为低电压信号，EM2(n)为低电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，T3和T4打开，DT驱动O1发光。
如图30所示，在图9所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极接入第n级第三发光控制信号EM3(n)，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与低电平端VGL电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第一发光控制信号EM1(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极接入第n-5级第三发光控制信号EM3(n-5)，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述第二初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与复位控制端RST电连接，所述第六晶体管T6的源极与所述第二初始电压端I2电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图30所示的像素电路的至少一实施例中，所有晶体管都为p型晶体管，但不以此为限。
在图30所示的像素电路的至少一实施例中，补偿控制端接入第n级第三发光控制信号EM3(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第一发光控制信号EM1(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端接入第n-5级第三发光控制信号EM3(n-5)，第二初始控制端为复位控制端RST，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
在图30所示的像素电路的至少一实施例中，T2的栅极可以替换为与提供控制信号的控制端电连接，该控制端在第一初始化阶段、写入阶段和发光阶段提供低电压信号，以使得像素电路可以工作。
图31是图30所示的像素电路的至少一实施例的工作时序图。
如图31所示，本公开图30所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一初始化阶段S11、写入阶段S2、第二初始化阶段S12和发光阶段S3；
在第一初始化阶段S11，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为低电压信号，GT(n)提供高电压信号，RST提供低电压信号，T5打开，T2打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，以改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在写入阶段S2，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为低电压信号，GT(n)提供低电压信号，RST提供高电压信号，T1和T2打开；T7打开，DL提供数据电压Vdata至第二节点N2；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，改变N1的电位，直至DT关断，N1的电位变为Vdata+Vth，进行阈值电压补偿，Vth为DT的阈值电压；
在第二初始化阶段S12，EM1(n)为高电压信号，EM2(n)为高电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，RST提供低电压信号，T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，以改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在发光阶段S3，EM1(n)为低电压信号，EM2(n)为低电压信号，EM3(n-5)为高电压信号，EM3(n)为高电压信号，GT(n)提供高电压信号，RST提供高电压信号，T3和T4打开，DT驱动O1发光。
如图32所示，在图8所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述第一晶体管T1的栅极与第n级第三扫描端NG(n)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第四节点N4电连接；
所述第二晶体管T2的栅极与电源电压端VDD电连接，所述第二晶体管T2的源极与所述第三节点N3电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第一节点N1电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第二发光控制信号EM2(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-5级第三扫描端NG(n-5)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述第二初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与复位控制端RST电连接，所述第六晶体管T6的源极与所述第二初始电压端I2电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8(；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述复位控制端RST电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图32所示的像素电路的至少一实施例中，T1、T2和T5都为n型晶体管，其他晶体管都为p型晶体管，但不以此为限。
在图32所示的像素电路的至少一实施例中，补偿控制端为第n级第三扫描端NG(n)，通断控制端为电源电压端，第一发光控制端接入第n级第二发光控制信号EM2(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端为第n-5级第三扫描端NG(n-5)，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为复位控制端RST，第二初始控制端为复位控制端RST。
图33是本公开图32所示的像素电路的至少一实施例的工作时序图。
如图33所示，本公开图32所示的像素电路的至少一实施例在工作时，显示周期可以包括先后设置的第一初始化阶段S11、写入阶段S2、第二初始化阶段S12和发光阶段S3；
在第一初始化阶段S11，EM2(n)为高电压信号，NG(n-5)提供高电压信号，GT(n)提供高电压信号，RST提供低电压信号，T5打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在写入阶段S2，EM2(n)为高电压信号，NG(n-5)提供低电压信号，NG(n)提供高电压信号，GT(n)提供低电压信号，RST提供高电压信号，T1和T2打开，T7打开，DL通过数据电压Vdata至第二节点N2；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，改变N1的电位，直至N1的电位变为Vdata+Vth，DT关断，进行阈值电压补偿；Vth为DT的阈值电压；
在第二初始化阶段S12，EM2(n)为高电压信号，NG(n-5)提供低电压信号，NG(n)提供低电压信号，GT(n)提供高电压信号，RST提供低电压信号，T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在发光阶段S3，EM2(n)为低电压信号，NG(n-5)提供低电压信号，NG(n)提供低电压信号，GT(n)提供高电压信号，RST提供高电压信号，T3和T4导通，DT驱动O1发光。
如图34所示，在图9所示的像素电路的至少一实施例的基础上，发光元件为有机发光二极管O1；
所述驱动晶体管DT的源极与第二节点N2电连接，所述驱动晶体管DT的漏极与第三节点N3电连接；
所述补偿控制电路包括第一晶体管T1，所述通断控制电路包括第二晶体管T2；所述储能电路包括存储电容Cst；
所述第一晶体管T1的栅极与第n级第三扫描端NG(n)电连接，所述第一晶体管T1的源极与所述第四节点N4电连接，所述第一晶体管T1的漏极与第三节点N3电连接；
所述第二晶体管T2的栅极与电源电压端VDD电连接，所述第二晶体管T2的源极与所述第一节点N1电连接，所述第二晶体管T2的漏极与所述第四节点N4电连接；
所述存储电容Cst的第一极板与所述第四节点N4电连接，所述存储电容Cst的第二极板与电源电压端VDD电连接；
所述第一发光控制电路包括第三晶体管T3，所述第二发光控制电路包括第四晶体管T4，所述第一初始化电路包括第五晶体管T5；
所述第三晶体管T3的栅极接入第n级第二发光控制信号EM2(n)，所述第三晶体管T3的源极与电源电压端VDD电连接，所述第三晶体管T3的漏极与所述第二节点N2电连接；
所述第四晶体管T4的栅极接入第n级第二发光控制信号EM2(n)，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述有机发光二极管O1的阳极电连接；所述有机发光二极管O1的阴极与低电压端电连接；
所述第五晶体管T5的栅极与第n-5级第三扫描端NG(n-5)电连接，所述第五晶体管T5的源极与所述第一初始电压端I1电连接，所述第五晶体管T5的漏极与所述第一节点N1电连接；
所述第二初始化电路包括第六晶体管T6；
所述第六晶体管T6的栅极与复位控制端RST电连接，所述第六晶体管T6的源极与所述第二初始电压端I2电连接，所述第六晶体管T6的漏极与所述第二节点N2电连接；
所述数据写入电路包括第七晶体管T7，所述第三初始化电路包括第八晶体管T8；
所述第七晶体管T7的栅极与第n级第一扫描端GT(n)电连接，所述第七晶体管T7的源极与所述数据线DL电连接，所述第七晶体管T7的漏极与所述第二节点N2电连接；
所述第八晶体管T8的栅极与所述第n级第一扫描端GT(n)电连接，所述第八晶体管T8的源极与所述第三初始电压端I3电连接，所述第八晶体管T8的漏极与所述有机发光二极管O1的阳极电连接。
在图34所示的像素电路的至少一实施例中，T1和T2都为n型晶体管，其他晶体管都为p型晶体管，但不以此为限。在图34所示的像素电路的至少一实施例中，补偿控制端为第n级第三扫描端NG(n)，通断控制端为低电平端VGL，第一发光控制端接入第n级第二发光控制信号EM2(n)，第二发光控制端接入第n级第二发光控制信号EM2(n)，第一初始控制端为第n-5级第三扫描端NG(n-5)，第二初始控制端为复位控制端RST，写入控制端为第n级第一扫描端GT(n)，第三初始控制端为第n级第一扫描端GT(n)。
图35是图34所示的像素电路的至少一实施例的工作时序图。
如图35所示，本公开图34所示的像素电路的至少一实施例在工作时，
显示周期可以包括先后设置的第一初始化阶段S11、写入阶段S2、第二初始化阶段S12和发光阶段S3；
在第一初始化阶段S11，EM2(n)为高电压信号，NG(n-5)提供高电压信号，GT(n)提供高电压信号，RST提供低电压信号，T5和T2打开，I1提供第一初始电压Vinit1至第一节点N1，以使得在写入阶段S2开始时，DT能够导通；T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在写入阶段S2，EM2(n)为高电压信号，NG(n-5)提供低电压信号，NG(n)提供高电压信号，GT(n)提供低电压信号，RST提供高电压信号，T1和T2打开，T7打开，DL通过数据电压Vdata至第二节点N2；
在写入阶段S2开始时，DT导通，通过Vdata为Cst充电，改变N1的电位，直至N1的电位变为Vdata+Vth，DT关断，进行阈值电压补偿；Vth为DT的阈值电压；
在第二初始化阶段S12，EM2(n)为高电压信号，NG(n-5)提供低电压信号，NG(n)提供低电压信号，GT(n)提供高电压信号，RST提供低电压信号，T6和T8打开，I2提供第二初始电压Vinit2至第二节点N2，改善DT的迟滞现象；I3提供第三初始电压Vinit3至O1的阳极，清除O1的阳极残留的电荷；
在发光阶段S3，EM2(n)为低电压信号，NG(n-5)提供低电压信号，NG(n)提供低电压信号，GT(n)提供高电压信号，RST提供高电压信号，T3和T4导通，DT驱动O1发光。
本公开实施例所述的显示装置包括上述的像素电路。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (16)

  1. 一种像素电路，包括发光元件和驱动晶体管；所述驱动晶体管的第一极与第一电压端电连接；
    所述像素电路还包括设置于所述驱动晶体管的栅极与所述驱动晶体管的第二极之间的至少两个晶体管；所述驱动晶体管的第二极与发光元件电连接，所述驱动晶体管用于产生驱动所述发光元件的驱动电流；
    所述至少两个晶体管中的至少两个晶体管的栅极接入的控制信号互不相同。
  2. 如权利要求1所述的像素电路，其中，还包括第一发光控制电路和第二发光控制电路；
    所述驱动晶体管的第一极通过所述第一发光控制电路与所述第一电压端电连接，所述驱动晶体管的第二极通过所述第二发光控制电路与所述发光元件的第一极电连接；所述发光元件的第二极与第二电压端电连接；
    所述第一发光控制电路与第一发光控制端电连接，用于在所述第一发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第一极与所述第一电压端之间连通；
    所述第二发光控制电路与第二发光控制端电连接，用于在所述第二发光控制端提供的控制信号的控制下，控制所述驱动晶体管的第二极与所述发光元件的第一极之间连通。
  3. 如权利要求2所述的像素电路，其中，所述第一发光控制端与所述第二发光控制端不同，所述第一发光控制端提供的控制信号与所述第二发光控制端提供的控制信号不同。
  4. 如权利要求2所述的像素电路，其中，包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
    所述补偿控制电路分别与补偿控制端、所述第一节点和第四节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
    所述通断控制电路分别与通断控制端、所述第三节点和所述第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第三节点与所述第四节点之间连通；
    所述储能电路与所述第一节点电连接，用于储存电能。
  5. 如权利要求2所述的像素电路，其中，包括补偿控制电路、通断控制电路和储能电路；所述驱动晶体管的栅极与第一节点电连接；所述驱动晶体管的第一极与第二节点电连接，所述驱动晶体管的第二极与第三节点电连接；
    所述补偿控制电路分别与补偿控制端、第四节点和第三节点电连接，用于在所述补偿控制端提供的补偿控制信号的控制下，控制所述第四节点与所述第三节点之间连通；
    所述通断控制电路分别与通断控制端、所述第一节点和第四节点电连接，用于在所述通断控制端提供的通断控制信号的控制下，控制所述第一节点与所述第四节点之间连通；
    所述储能电路与所述第四节点电连接，用于储存电能。
  6. 如权利要求4或5所述的像素电路，其中，包括第一初始化电路；
    所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第一节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第一节点。
  7. 如权利要求4或5所述的像素电路，其中，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n级第二扫描端；或者，
    所述补偿控制端为第n级第一扫描端；所述通断控制电路包括的晶体管为p型晶体管，所述通断控制端为低电平端；或者，
    所述补偿控制端为第n级第三扫描端；所述通断控制电路包括的晶体管为n型晶体管，所述通断控制端为高电平端；
    n为正整数。
  8. 如权利要求6所述的像素电路，其中，所述第一发光控制端和所述第二发光控制端接入第n级第一发光控制信号，所述补偿控制端接入第n级第二发光控制信号，所述第一初始控制端接入第n-a级第二发光控制信号；n和a为正整数；或者，
    所述第一发光控制端为第n级发光控制端，所述第二发光控制端为第n+1级发光控制端，所述补偿控制端为第n级第一扫描端，所述通断控制端为第n-1级第一扫描端；n为正整数；或者，
    所述第一发光控制端接入第n级第一发光控制信号，所述第二发光控制端接入第n级第二发光控制信号，所述补偿控制端接入第n级第三发光控制信号，所述第一初始控制端接入第n-b级第三发光控制信号；n和b为正整数。
  9. 如权利要求6所述的像素电路，其中，还包括第二初始化电路；
    所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第二节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第二节点。
  10. 如权利要求6所述的像素电路，其中，还包括数据写入电路和第三初始化电路；
    所述数据写入电路分别与写入控制端、数据线和所述第二节点电连接，用于在所述写入控制端提供的写入控制信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
    所述第三初始化电路分别与第三初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第三初始控制端提供的第三初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
  11. 如权利要求4所述的像素电路，其中，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
    所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第四节点电连接；
    所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第三节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
    所述存储电容的第一极板与所述第一节点电连接，所述存储电容的第二极板与直流电压端电连接。
  12. 如权利要求5所述的像素电路，其中，所述补偿控制电路包括第一晶体管，所述通断控制电路包括第二晶体管；所述储能电路包括存储电容；
    所述第一晶体管的栅极与所述补偿控制端电连接，所述第一晶体管的第一极与所述第四节点电连接，所述第一晶体管的第二极与所述第三节点电连接；
    所述第二晶体管的栅极与所述通断控制端电连接，所述第二晶体管的第一极与所述第一节点电连接，所述第二晶体管的第二极与所述第四节点电连接；
    所述存储电容的第一极板与所述第四节点电连接，所述存储电容的第二极板与直流电压端电连接。
  13. 如权利要求6所述的像素电路，其中，所述第一发光控制电路包括第三晶体管，所述第二发光控制电路包括第四晶体管，所述第一初始化电路包括第五晶体管；
    所述第三晶体管的栅极与所述第一发光控制端电连接，所述第三晶体管的第一极与第一电压端电连接，所述第三晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第四晶体管的栅极与所述第二发光控制端电连接，所述第四晶体管的第一极与所述驱动晶体管的第二极电连接，所述第四晶体管的第二极与所述发光元件的第一极电连接；
    所述第五晶体管的栅极与所述第一初始控制端电连接，所述第五晶体管的第一极与所述第一初始电压端电连接，所述第五晶体管的第二极与所述第一节点电连接。
  14. 如权利要求9所述的像素电路，其中，所述第二初始化电路包括第六晶体管；
    所述第六晶体管的栅极与所述第二初始控制端电连接，所述第六晶体管的第一极与所述第二初始电压端电连接，所述第六晶体管的第二极与所述第二节点电连接。
  15. 如权利要求10所述的像素电路，其中，所述数据写入电路包括第七晶体管，所述第三初始化电路包括第八晶体管；
    所述第七晶体管的栅极与所述写入控制端电连接，所述第七晶体管的第一极与所述数据线电连接，所述第七晶体管的第二极与所述第二节点电连接；
    所述第八晶体管的栅极与所述第三初始控制端电连接，所述第八晶体管的第一极与所述第三初始电压端电连接，所述第八晶体管的第二极与所述发光元件的第一极电连接。
  16. 一种显示装置，包括如权利要求1至15中任一权利要求所述的像素电路。
PCT/CN2025/077304 2024-03-13 2025-02-14 像素电路和显示装置 Pending WO2025190031A1 (zh)

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