WO2025162015A1 - 跨导增强的低噪声放大器及射频芯片 - Google Patents

跨导增强的低噪声放大器及射频芯片

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Publication number
WO2025162015A1
WO2025162015A1 PCT/CN2025/073167 CN2025073167W WO2025162015A1 WO 2025162015 A1 WO2025162015 A1 WO 2025162015A1 CN 2025073167 W CN2025073167 W CN 2025073167W WO 2025162015 A1 WO2025162015 A1 WO 2025162015A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
inductor
mos transistor
transconductance
resistor
Prior art date
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Application number
PCT/CN2025/073167
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English (en)
French (fr)
Inventor
童凌云
郭嘉帅
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Lansus Technologies Inc
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Lansus Technologies Inc
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Publication of WO2025162015A1 publication Critical patent/WO2025162015A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present invention is applicable to the field of wireless communication technology, and in particular relates to a low-noise amplifier with enhanced transconductance and a radio frequency chip.
  • a low-noise amplifier is an amplifier with a very low noise factor.
  • the noise of the amplifier itself may interfere with the signal more seriously than the interference of the signal itself.
  • the low-noise amplifier reduces its own noise through a certain structure to improve the signal-to-noise ratio of the signal output, thereby achieving better signal amplification effect.
  • the cascode low-noise amplifier (LNA) structure is the most commonly used in various circuits. Currently, to achieve power gain, the cascode LNA requires an additional amplifier stage. This design increases the circuit size and is not conducive to the implementation of microcircuits.
  • the present invention provides a low-noise amplifier with enhanced transconductance and a radio frequency chip, aiming to solve the problem that the power gain of the existing low-noise amplifier increases the circuit size.
  • the present invention provides a low-noise amplifier with enhanced transconductance, comprising a signal input terminal, an input matching circuit, an amplifying circuit, a transconductance enhancement circuit, an output matching circuit, and a signal output terminal, wherein:
  • the input matching circuit includes a first capacitor and a first inductor, wherein a first end of the first capacitor is connected to the signal input end, a second end of the first capacitor is connected to a first end of the first inductor, and a second end of the first inductor is grounded;
  • the output matching circuit includes a second capacitor and a second inductor, wherein a first end of the second capacitor is connected to the signal output end, a second end of the second capacitor is connected to a first end of the second inductor, and a second end of the second inductor is connected to a first power supply voltage;
  • the amplifier circuit includes a first MOS transistor and a first resistor, wherein the source of the first MOS transistor is connected to the second end of the first capacitor, the drain of the first MOS transistor is connected to the second end of the second capacitor, the gate of the first MOS transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to a first bias voltage;
  • the transconductance enhancement circuit is used to feed back the signal input to the source of the first MOS transistor to the gate of the first MOS transistor.
  • the transconductance enhancement circuit includes a second MOS transistor and a second resistor, the gate of the second MOS transistor is connected to the source of the first MOS transistor as the input end of the transconductance enhancement circuit, the drain of the second MOS transistor is connected to the gate of the first MOS transistor as the output end of the transconductance enhancement circuit, and the source of the second MOS transistor is grounded; the first end of the second resistor is connected to the gate of the second MOS transistor, and the second end of the second resistor is connected to the second bias voltage.
  • the transconductance enhancement circuit also includes a third capacitor, a first end of the third capacitor is connected to the source of the first MOS transistor, and a second end of the third capacitor is respectively connected to the gate of the second MOS transistor and the first end of the second resistor.
  • the transconductance enhancement circuit also includes a fourth capacitor and a third inductor, a first end of the fourth capacitor is connected to the drain of the second MOS transistor, a second end of the fourth capacitor is connected to the gate of the first MOS transistor, a first end of the third inductor is connected to the first end of the fourth capacitor, and a second end of the third inductor is connected to the second power supply voltage.
  • the first inductor is coupled to the third inductor.
  • the transconductance enhancement circuit includes a fifth inductor and a sixth capacitor, a first end of the fifth inductor is connected to the first end of the sixth capacitor, a second end of the fifth inductor is grounded, a second end of the sixth capacitor is connected to the gate of the first MOS transistor, and the first inductor is coupled to the fifth inductor.
  • the input matching circuit further includes a first input inductor, a second input inductor, a third resistor, a third MOS transistor, a fourth inductor, and a fifth capacitor.
  • the first end of the first input inductor is connected to the signal input terminal
  • the second end of the first input inductor is connected to the first end of the first capacitor
  • the second end of the first capacitor is connected to the gate of the third MOS transistor
  • the first end of the third resistor is connected to the second end of the first capacitor
  • the second end of the third resistor is connected to a third bias voltage
  • the first end of the second input inductor is connected to the source of the third MOS transistor
  • the second end of the second input inductor is grounded
  • the drain of the third MOS transistor is connected to the first end of the fifth capacitor
  • the second end of the fifth capacitor is connected to the source of the first MOS transistor
  • the first end of the fourth inductor is connected to the first end of the fifth capacitor
  • the present invention further provides a radio frequency chip, comprising the transconductance enhanced low noise amplifier as described above.
  • the beneficial effect achieved by the present invention lies in proposing a new low-noise amplifier and radio frequency chip that can achieve transconductance enhancement. Without adding an additional amplifier stage, the low-noise amplifier increases the gate voltage swing by inverting the input signal and feeding it into the MOS tube gate of the common-gate amplifier circuit, thereby effectively enhancing the transconductance of the low-noise amplifier and improving the power gain while maintaining the receiving sensitivity.
  • FIG1 is a schematic diagram of a circuit structure of a low-noise amplifier with enhanced transconductance provided by an embodiment of the present invention
  • FIG2 is a schematic diagram of a circuit structure of a low-noise amplifier with transconductance enhancement implemented in an active manner according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of an optimized circuit structure of a low-noise amplifier with transconductance enhancement implemented in an active manner according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of the circuit structure of a low-noise amplifier with enhanced transconductance implemented in a passive manner according to an embodiment of the present invention
  • FIG5 is a schematic diagram of an optimized circuit structure of a low-noise amplifier with enhanced transconductance implemented in a passive manner according to an embodiment of the present invention.
  • FIG1 is a schematic diagram of a circuit structure of a low-noise amplifier 100 with enhanced transconductance provided by an embodiment of the present invention.
  • the low-noise amplifier 100 with enhanced transconductance includes a signal input terminal RF in , an input matching circuit, an amplification circuit, a transconductance enhancement circuit, an output matching circuit, and a signal output terminal RF out , wherein:
  • the input matching circuit includes a first capacitor C1 and a first inductor L1, wherein a first end of the first capacitor C1 is connected to the signal input terminal RF in , a second end of the first capacitor C1 is connected to a first end of the first inductor L1 , and a second end of the first inductor L1 is grounded;
  • the output matching circuit includes a second capacitor C2 and a second inductor L2, wherein a first end of the second capacitor C2 is connected to the signal output terminal RF out , a second end of the second capacitor C2 is connected to a first end of the second inductor L2, and a second end of the second inductor L2 is connected to a first power supply voltage VDD1;
  • the amplifier circuit includes a first MOS transistor M1 and a first resistor R1.
  • the source of the first MOS transistor M1 is connected to the second end of the first capacitor C1
  • the drain of the first MOS transistor M1 is connected to the second end of the second capacitor C2
  • the gate of the first MOS transistor M1 is connected to the first end of the first resistor R1
  • the second end of the first resistor R1 is connected to a first bias voltage V bias1 .
  • the transconductance enhancement circuit is used to feed back the signal input to the source of the first MOS transistor to the gate of the first MOS transistor.
  • the transconductance-enhanced low-noise amplifier 100 in the embodiment of the present invention forms a transconductance enhancement circuit by adding a path at the source end of the MOS tube.
  • the effect of this circuit on the transconductance of the amplifier circuit is represented by a coefficient A.
  • the transconductance enhancement circuit can increase the transconductance Gm by (1+A) while reducing the NF of the device itself by (1+A) while keeping the output impedance of the amplifier unchanged.
  • the transconductance enhancement circuit in the transconductance-enhanced low-noise amplifier 100 in the embodiment of the present invention can be implemented based on active, passive, or a combination of active and passive methods.
  • the embodiment of the present invention also has the following implementation methods:
  • the transconductance enhancement circuit includes a second MOS transistor M2 and a second resistor R2.
  • the gate of the second MOS transistor M2 serves as the input of the transconductance enhancement circuit and is connected to the source of the first MOS transistor M1.
  • the drain of the second MOS transistor M2 serves as the output of the transconductance enhancement circuit and is connected to the gate of the first MOS transistor M1.
  • the source of the second MOS transistor M2 is grounded.
  • a first end of the second resistor R2 is connected to the gate of the second MOS transistor M2, and a second end of the second resistor R2 is connected to a second bias voltage V bias2 .
  • the transconductance enhancement circuit further includes a third capacitor C3.
  • a first end of the third capacitor C3 is connected to the source of the first MOS transistor M1, and a second end of the third capacitor C3 is connected to the gate of the second MOS transistor M2 and the first end of the second resistor R2, respectively.
  • the transconductance enhancement circuit further includes a fourth capacitor C4 and a third inductor L3.
  • a first end of the fourth capacitor C4 is connected to the drain of the second MOS transistor M2, and a second end of the fourth capacitor C4 is connected to the gate of the first MOS transistor M1.
  • a first end of the third inductor L3 is connected to the first end of the fourth capacitor C4, and a second end of the third inductor L3 is connected to the second power supply voltage VDD2. In this manner, two separate power supply voltages are provided in the circuit to ensure DC supply.
  • the second MOS transistor M2, the second capacitor C2, and the third capacitor C3 together constitute the transconductance enhancement circuit of the transconductance enhanced low noise amplifier 100.
  • the coefficient A is determined by the second MOS transistor M2.
  • the circuit structure of FIG. 2 can be optimized. As shown in FIG. 3 , based on FIG. 2 , a first input inductor Lg, a second input inductor Ls, a third resistor R3, a third MOS transistor M3, a fourth inductor L4, and a fifth capacitor C5 are added to the input matching circuit.
  • the first end of the first input inductor Lg is connected to the signal input terminal RF in , the second end of the first input inductor Lg is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the gate of the third MOS transistor M3, the first end of the third resistor R3 is connected to the second end of the first capacitor C1, and the second end of the third resistor R3 is connected to the third bias voltage V bias3
  • the first end of the second input inductor Ls is connected to the source of the third MOS transistor M3, the second end of the second input inductor Ls is grounded, the drain of the third MOS transistor M3 is connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is connected to the source of the first MOS transistor M1, the first end of the fourth inductor L4 is connected to the first end of the fifth capacitor C5, and the second end of the fourth inductor L4 is connected to the third power supply voltage VDD3.
  • the transconductance enhancement circuit includes a fifth inductor L5 and a sixth capacitor C6.
  • a first end of the fifth inductor L5 is connected to a first end of the sixth capacitor C6, a second end of the fifth inductor L5 is grounded, a second end of the sixth capacitor C6 is connected to the gate of the first MOS transistor M1, and the first inductor L1 is coupled to the fifth inductor L5.
  • the coupling coefficient between the first inductor L1 and the fifth inductor L5 is k.
  • the coefficient A is determined by the coupling coefficient k.
  • the circuit structure of FIG. 4 can be optimized. As shown in FIG. 5 , based on FIG. 4 , a first input inductor Lg, a second input inductor Ls, a third resistor R3, a third MOS transistor M3, a fourth inductor L4, and a fifth capacitor C5 are added to the input matching circuit.
  • a first end of the first input inductor Lg is connected to the signal input terminal RF in , a second end of the first input inductor Lg is connected to a first end of the first capacitor C1, a second end of the first capacitor C1 is connected to the gate of the third MOS transistor M3, a first end of the third resistor R3 is connected to a second end of the first capacitor C1, and a second end of the third resistor R3 is connected to a third bias voltage V bias3
  • the first end of the second input inductor Ls is connected to the source of the third MOS transistor M3, the second end of the second input inductor Ls is grounded, the drain of the third MOS transistor M3 is connected to the first end of the fifth capacitor C5, the second end of the fifth capacitor C5 is connected to the source of the first MOS transistor M1, the first end of the fourth inductor L4 is connected to the first end of the fifth capacitor C5, and the second end of the fourth inductor L4 is connected to the third power supply voltage VDD3.
  • the circuit structure of the transconductance enhanced low noise amplifier 100 implemented based on the active-passive combination is the same as that of the second embodiment, as shown in FIG2 .
  • the specific implementation of the active-passive combination is to couple the first inductor L1 with the third inductor L3 based on the second embodiment.
  • the coupling coefficient between the first inductor L1 and the third inductor L3 is k.
  • the coefficient A is determined by the second MOS transistor M2 and the coupling coefficient k.
  • the embodiment of the present invention provides a larger output voltage swing while keeping the output impedance of the amplifier circuit unchanged, thereby improving the gain.
  • the beneficial effect achieved by the present invention lies in proposing a new low-noise amplifier and radio frequency chip that can achieve transconductance enhancement. Without adding an additional amplifier stage, the low-noise amplifier increases the gate voltage swing by inverting the input signal and feeding it into the MOS tube gate of the common-gate amplifier circuit, thereby effectively enhancing the transconductance of the low-noise amplifier and improving the power gain while maintaining the receiving sensitivity.
  • An embodiment of the present invention further provides a radio frequency chip including a low-noise amplifier with enhanced transconductance as described in the above embodiment.
  • the radio frequency chip using the low-noise amplifier with enhanced transconductance can effectively enhance the transconductance of the low-noise amplifier without adding an additional amplifier stage, thereby improving power gain while maintaining receiver sensitivity.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

本发明适用于无线通信技术领域，尤其涉及一种跨导增强的低噪声放大器及射频芯片，包括：输入匹配电路，包括第一电容和第一电感，第一电容的第一端接信号输入端，第二端接第一电感的第一端，第一电感的第二端接地；输出匹配电路，第二电容和第二电感，第二电容的第一端接信号输出端，第二端接第二电感的第一端，第二电感的第二端接第一电源电压；放大电路，包括第一MOS管和第一电阻，第一MOS管源极接第一电容的第二端，漏极接第二电容的第二端，栅极接至第一电阻的第一端，第一电阻的第二端接偏置电压；跨导增强电路，用于将输入第一MOS管的源极的信号馈入第一MOS管的栅极。本发明在不额外增加一级放大器的前提下提升了功率增益。

Description

跨导增强的低噪声放大器及射频芯片 技术领域
本发明适用于无线通信技术领域，尤其涉及一种跨导增强的低噪声放大器及射频芯片。
背景技术
低噪声放大器是一种噪声系数很低的放大器，在利用放大器放大微弱信号的场合，放大器自身的噪声对信号的干扰可能会比信号本身带有的干扰更为严重，而低噪声放大器则是通过一定的结构来减小自身噪声，以提高信号输出的信噪比，从而达到更好的信号放大效果。
共源共栅结构的低噪声放大器是各种电路中最常使用到的结构。目前，共源共栅低噪声放大器为了实现功率增益，需要在电路结构中额外增加一级放大器，这样的设计增加了电路的大小，不利于微电路的实现。
发明内容
本发明提供一种跨导增强的低噪声放大器及射频芯片，旨在解决现有的低噪声放大器实现功率增益会使得电路大小增加的问题。
为解决上述技术问题，第一方面，本发明提供一种跨导增强的低噪声放大器，包括信号输入端、输入匹配电路、放大电路、跨导增强电路、输出匹配电路和信号输出端，其中：
所述输入匹配电路包括第一电容和第一电感，所述第一电容的第一端连接所述信号输入端，所述第一电容的第二端连接所述第一电感的第一端，所述第一电感的第二端接地；
所述输出匹配电路包括第二电容和第二电感，所述第二电容的第一端连接所述信号输出端，所述第二电容的第二端连接所述第二电感的第一端，所述第二电感的第二端用于连接第一电源电压；
所述放大电路包括第一MOS管和第一电阻，所述第一MOS管的源极连接所述第一电容的第二端，所述第一MOS管的漏极连接所述第二电容的第二端，所述第一MOS管的栅极连接至所述第一电阻的第一端，所述第一电阻的第二端接第一偏置电压；
所述跨导增强电路用于将输入至所述第一MOS管的源极的信号反馈至所述第一MOS管的栅极。
更进一步地，所述跨导增强电路包括第二MOS管和第二电阻，所述第二MOS管的栅极作为所述跨导增强电路的输入端连接至所述第一MOS管的源极，所述第二MOS管的漏极作为所述跨导增强电路的输出端连接至所述第一MOS管的栅极，所述第二MOS管的源极接地；所述第二电阻的第一端连接至所述第二MOS管的栅极，所述第二电阻的第二端连接第二偏置电压。
更进一步地，所述跨导增强电路还包括第三电容，所述第三电容的第一端连接所述第一MOS管的源极，所述第三电容的第二端分别与所述第二MOS管的栅极及所述第二电阻的第一端连接。
更进一步地，所述跨导增强电路还包括第四电容和第三电感，所述第四电容的第一端连接所述第二MOS管的漏极，所述第四电容的第二端与所述第一MOS管的栅极连接，所述第三电感的第一端连接至所述第四电容的第一端，所述第三电感的第二端连接第二电源电压。
更进一步地，所述第一电感与所述第三电感耦合。
更进一步地，所述跨导增强电路包括第五电感和第六电容，所述第五电感的第一端与所述第六电容的第一端连接，所述第五电感的第二端接地，所述第六电容的第二端与所述第一MOS管的栅极连接，所述第一电感与所述第五电感耦合。
更进一步地，所述输入匹配电路还包括第一输入电感、第二输入电感、第三电阻、第三MOS管、第四电感以及第五电容，所述第一输入电感的第一端连接所述信号输入端，所述第一输入电感的第二端连接所述第一电容的第一端，所述第一电容的第二端连接所述第三MOS管的栅极，所述第三电阻的第一端连接所述第一电容的第二端，所述第三电阻的第二端连接第三偏置电压，所述第二输入电感的第一端连接所述第三MOS管的源极，所述第二输入电感的第二端接地，所述第三MOS管的漏极连接所述第五电容的第一端，所述第五电容的第二端连接所述第一MOS管的源极，所述第四电感的第一端连接所述第五电容的第一端，所述第四电感的第二端连接第三电源电压。
第二方面，本发明还提供一种射频芯片，所述射频芯片包括如上所述的跨导增强的低噪声放大器。
本发明所达到的有益效果，在于提出了一种可以实现跨导增强的新型低噪声放大器及射频芯片，该低噪声放大器在不额外增加一级放大器的前提下，通过将输入信号反转后馈入共栅放大电路的MOS管栅极的方式，增加了栅极电压的摆幅，从而有效增强低噪声放大器的跨导，进而在保持接收灵敏度的同时提升功率增益。
附图说明
图1是本发明实施例提供的跨导增强的低噪声放大器的电路结构示意图；
图2是本发明实施例提供的基于有源方式实现的跨导增强的低噪声放大器的电路结构示意图；
图3是本发明实施例提供的基于有源方式实现的跨导增强的低噪声放大器的优化电路结构示意图；
图4是本发明实施例提供的基于无源方式实现的跨导增强的低噪声放大器的电路结构示意图；
图5是本发明实施例提供的基于无源方式实现的跨导增强的低噪声放大器的优化电路结构示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一
请参照图1，图1是本发明实施例提供的跨导增强的低噪声放大器100的电路结构示意图，所述跨导增强的低噪声放大器100包括信号输入端RFin、输入匹配电路、放大电路、跨导增强电路、输出匹配电路和信号输出端RFout，其中：
所述输入匹配电路包括第一电容C1和第一电感L1，所述第一电容C1的第一端连接所述信号输入端RFin，所述第一电容C1的第二端连接所述第一电感L1的第一端，所述第一电感L1的第二端接地；
所述输出匹配电路包括第二电容C2和第二电感L2，所述第二电容C2的第一端连接所述信号输出端RFout，所述第二电容C2的第二端连接所述第二电感L2的第一端，所述第二电感L2的第二端用于连接第一电源电压VDD1；
所述放大电路包括第一MOS管M1和第一电阻R1，所述第一MOS管M1的源极连接所述第一电容C1的第二端，所述第一MOS管M1的漏极连接所述第二电容C2的第二端，所述第一MOS管M1的栅极连接至所述第一电阻R1的第一端，所述第一电阻R1的第二端接第一偏置电压Vbias1；
所述跨导增强电路用于将输入至所述第一MOS管的源极的信号反馈至所述第一MOS管的栅极。
本发明实施例中，本发明实施例中的所述跨导增强的低噪声放大器100通过在MOS管的源端增加一段通路形成跨导增强电路，该电路对放大电路的跨导影响用系数A表示，跨导增强电路可以使得放大器输出阻抗不变的情况下，使得跨导Gm增大(1+A)，同时器件本身NF缩小(1+A)。具体的，本发明实施例中的所述跨导增强的低噪声放大器100中的跨导增强电路可以基于有源、无源或有源无源结合的方式实现，对应不同的实现方式，本发明实施例还具有以下实施方式：
实施例二
基于有源方式实现的跨导增强的低噪声放大器100如图2所示，所述跨导增强电路包括第二MOS管M2和第二电阻R2，所述第二MOS管M2的栅极作为所述跨导增强电路的输入端连接至所述第一MOS管M1的源极，所述第二MOS管M2的漏极作为所述跨导增强电路的输出端连接至所述第一MOS管M1的栅极，所述第二MOS管M2的源极接地；所述第二电阻R2的第一端连接至所述第二MOS管M2的栅极，所述第二电阻R2的第二端接第二偏置电压Vbias2。
在有源方式中，由于不同MOS管的同时堆叠，需要更高的DC供给水平，本发明实施例中，为了提高DC供给水平，所述跨导增强电路还包括第三电容C3，所述第三电容C3的第一端连接所述第一MOS管M1的源极，所述第三电容C3的第二端分别与所述第二MOS管M2的栅极及所述第二电阻R2的第一端连接。
所述跨导增强电路还包括第四电容C4和第三电感L3，所述第四电容C4的第一端连接所述第二MOS管M2的漏极，所述第四电容C4的第二端与所述第一MOS管M1的栅极连接，所述第三电感L3的第一端，连接至所述第四电容C4的第一端，所述第三电感L3的第二端连接第二电源电压VDD2，通过这样的方式，在电路中提供了两段分离的电源电压，以保证DC供给。
在这种实施方式下，所述第二MOS管M2、所述第二电容C2、所述第三电容C3共同构成所述跨导增强的低噪声放大器100的跨导增强电路。而系数A由所述第二MOS管M2决定。
示例性的，为了提高所述跨导增强的低噪声放大器100的性能表现，在一种较优的实施方式中，可以基于图2的电路结构进行优化，如图3所示，在图2的基础上，输入匹配电路中增加了第一输入电感Lg、第二输入电感Ls、第三电阻R3、第三MOS管M3、第四电感L4以及第五电容C5，所述第一输入电感Lg的第一端连接所述信号输入端RFin，所述第一输入电感Lg的第二端连接所述第一电容C1的第一端，所述第一电容C1的第二端连接所述第三MOS管M3的栅极，所述第三电阻R3的第一端连接所述第一电容C1的第二端，所述第三电阻R3的第二端接第三偏置电压Vbias3，所述第二输入电感Ls的第一端连接所述第三MOS管M3的源极，所述第二输入电感Ls的第二端接地，所述第三MOS管M3的漏极连接所述第五电容C5的第一端，所述第五电容C5的第二端连接所述第一MOS管M1的源极，所述第四电感L4的第一端连接所述第五电容C5的第一端，所述第四电感L4的第二端连接第三电源电压VDD3。在这样的优化结构下，所述第一MOS管M1、所述第二MOS管M2和所述第三MOS管M3共同构成所述跨导增强的低噪声放大器100的放大支路。
实施例三
基于无源方式实现的跨导增强的低噪声放大器100如图4所示，所述跨导增强电路包括第五电感L5和第六电容C6，所述第五电感L5的第一端与所述第六电容C6的第一端连接，所述第五电感L5的第二端接地，所述第六电容C6的第二端与所述第一MOS管M1的栅极连接，所述第一电感L1与所述第五电感L5耦合。
其中，所述第一电感L1与所述第五电感L5之间的耦合系数为k。在这种实施方式下，系数A由所述耦合系数k决定。
同样的，为了提高所述跨导增强的低噪声放大器100的性能表现，在一种较优的实施方式中，可以基于图4的电路结构进行优化，如图5所示，在图4的基础上，输入匹配电路中增加了第一输入电感Lg、第二输入电感Ls、第三电阻R3、第三MOS管M3、第四电感L4以及第五电容C5，所述第一输入电感Lg的第一端连接所述信号输入端RFin，所述第一输入电感Lg的第二端连接所述第一电容C1的第一端，所述第一电容C1的第二端连接所述第三MOS管M3的栅极，所述第三电阻R3的第一端连接所述第一电容C1的第二端，所述第三电阻R3的第二端接第三偏置电压Vbias3，所述第二输入电感Ls的第一端连接所述第三MOS管M3的源极，所述第二输入电感Ls的第二端接地，所述第三MOS管M3的漏极连接所述第五电容C5的第一端，所述第五电容C5的第二端连接所述第一MOS管M1的源极，所述第四电感L4的第一端连接所述第五电容C5的第一端，所述第四电感L4的第二端接第三电源电压VDD3。在这样的优化结构下，所述第一MOS管M1、所述第二MOS管M2和所述第三MOS管M3共同构成所述跨导增强的低噪声放大器100的放大支路。
在图5所示的电路结构下，由于设置了多个电感，实施过程中可以根据需要对不同级间匹配与输出匹配进行灵活配置，从而实现多阶匹配。
实施例四
基于有源无源结合的方式实现的跨导增强的低噪声放大器100的电路结构与实施例二的结构相同，如图2所示，有源无源结合的具体实现是在实施例二的基础上，将所述第一电感L1与所述第三电感L3耦合。
其中，所述第一电感L1与所述第三电感L3之间的耦合系数为k。
在这种实施方式下，系数A由所述第二MOS管M2和所述耦合系数k共同决定。
通过上述实施方式，本发明实施例在放大电路输出阻抗不变的情况下，提供了更大的输出电压摆幅，进而提升了增益。
本发明所达到的有益效果，在于提出了一种可以实现跨导增强的新型低噪声放大器及射频芯片，该低噪声放大器在不额外增加一级放大器的前提下，通过将输入信号反转后馈入共栅放大电路的MOS管栅极的方式，增加了栅极电压的摆幅，从而有效增强低噪声放大器的跨导，进而在保持接收灵敏度的同时提升功率增益。
实施例五
本发明实施例还提供一种射频芯片，所述射频芯片包括如上实施例所述的跨导增强的低噪声放大器。应用所述跨导增强的低噪声放大器的所述射频芯片能够在不额外增加一级放大器的前提下有效增强低噪声放大器的跨导，进而在保持接收灵敏度的同时提升功率增益。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本发明各个实施例所述的方法。
上面结合附图对本发明的实施例进行了描述，所揭露的仅为本发明较佳实施例而已，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式用等同变化，均属于本发明的保护之内。

Claims (8)

  1. 一种跨导增强的低噪声放大器，其特征在于，包括信号输入端、输入匹配电路、放大电路、跨导增强电路、输出匹配电路和信号输出端，其中：
    所述输入匹配电路包括第一电容和第一电感，所述第一电容的第一端连接所述信号输入端，所述第一电容的第二端连接所述第一电感的第一端，所述第一电感的第二端接地；
    所述输出匹配电路包括第二电容和第二电感，所述第二电容的第一端连接所述信号输出端，所述第二电容的第二端连接所述第二电感的第一端，所述第二电感的第二端用于连接第一电源电压；
    所述放大电路包括第一MOS管和第一电阻，所述第一MOS管的源极连接所述第一电容的第二端，所述第一MOS管的漏极连接所述第二电容的第二端，所述第一MOS管的栅极连接至所述第一电阻的第一端，所述第一电阻的第二端用于连接第一偏置电压；
    所述跨导增强电路用于将输入至所述第一MOS管的源极的信号反馈至所述第一MOS管的栅极。
  2. 如权利要求1所述的跨导增强的低噪声放大器，其特征在于，所述跨导增强电路包括第二MOS管和第二电阻，所述第二MOS管的栅极作为所述跨导增强电路的输入端连接至所述第一MOS管的源极，所述第二MOS管的漏极作为所述跨导增强电路的输出端连接至所述第一MOS管的栅极，所述第二MOS管的源极接地；所述第二电阻的第一端连接至所述第二MOS管的栅极，所述第二电阻的第二端连接第二偏置电压。
  3. 如权利要求2所述的跨导增强的低噪声放大器，其特征在于，所述跨导增强电路还包括第三电容，所述第三电容的第一端连接所述第一MOS管的源极，所述第三电容的第二端分别与所述第二MOS管的栅极及所述第二电阻的第一端连接。
  4. 如权利要求2所述的跨导增强的低噪声放大器，其特征在于，所述跨导增强电路还包括第四电容和第三电感，所述第四电容的第一端连接所述第二MOS管的漏极，所述第四电容的第二端与所述第一MOS管的栅极连接，所述第三电感的第一端连接至所述第四电容的第一端，所述第三电感的第二端连接第二电源电压。
  5. 如权利要求4所述的跨导增强的低噪声放大器，其特征在于，所述第一电感与所述第三电感耦合。
  6. 如权利要求1所述的跨导增强的低噪声放大器，其特征在于，所述跨导增强电路包括第五电感和第六电容，所述第五电感的第一端与所述第六电容的第一端连接，所述第五电感的第二端接地，所述第六电容的第二端与所述第一MOS管的栅极连接，所述第一电感与所述第五电感耦合。
  7. 如权利要求1所述的跨导增强的低噪声放大器，其特征在于，所述输入匹配电路还包括第一输入电感、第二输入电感、第三电阻、第三MOS管、第四电感以及第五电容，所述第一输入电感的第一端连接所述信号输入端，所述第一输入电感的第二端连接所述第一电容的第一端，所述第一电容的第二端连接所述第三MOS管的栅极，所述第三电阻的第一端连接所述第一电容的第二端，所述第三电阻的第二端连接第三偏置电压，所述第二输入电感的第一端连接所述第三MOS管的源极，所述第二输入电感的第二端接地，所述第三MOS管的漏极连接所述第五电容的第一端，所述第五电容的第二端连接所述第一MOS管的源极，所述第四电感的第一端连接所述第五电容的第一端，所述第四电感的第二端连接第三电源电压。
  8. 一种射频芯片，其特征在于，所述射频芯片包括如权利要求1-7任一项所述的跨导增强的低噪声放大器。
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CN117713704B (zh) * 2024-02-02 2024-05-28 深圳飞骧科技股份有限公司 跨导增强的低噪声放大器及射频芯片
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060046681A1 (en) * 2004-08-30 2006-03-02 Wilinx, Inc. High frequency wireless receiver circuits and methods
US20090115516A1 (en) * 2006-12-05 2009-05-07 Electronics And Telecommunications Research Institute Nauta operational transconductance amplifier
CN111740705A (zh) * 2020-07-10 2020-10-02 西安电子科技大学 一种消除非线性的低噪声放大器
CN117176085A (zh) * 2023-09-15 2023-12-05 西安中森电子科技有限公司 一种基于跨导增强技术的单端转差分低噪声放大器
CN117713704A (zh) * 2024-02-02 2024-03-15 深圳飞骧科技股份有限公司 跨导增强的低噪声放大器及射频芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102497167B (zh) * 2011-12-09 2014-10-15 电子科技大学 一种基于电感补偿的射频超宽带低噪声放大器
CN102983817B (zh) * 2012-11-22 2015-07-08 东南大学 一种高增益的宽带低噪声放大器
CN104660179B (zh) * 2014-12-30 2018-02-16 上海华虹宏力半导体制造有限公司 低噪声放大器
CN105680802B (zh) * 2015-11-30 2018-10-16 中国电子科技集团公司第五十五研究所 一种低功耗单片集成宽带低噪声放大器
CN107508563B (zh) * 2017-08-09 2020-11-13 上海华虹宏力半导体制造有限公司 一种自适应线性度增强低噪声放大器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060046681A1 (en) * 2004-08-30 2006-03-02 Wilinx, Inc. High frequency wireless receiver circuits and methods
US20090115516A1 (en) * 2006-12-05 2009-05-07 Electronics And Telecommunications Research Institute Nauta operational transconductance amplifier
CN111740705A (zh) * 2020-07-10 2020-10-02 西安电子科技大学 一种消除非线性的低噪声放大器
CN117176085A (zh) * 2023-09-15 2023-12-05 西安中森电子科技有限公司 一种基于跨导增强技术的单端转差分低噪声放大器
CN117713704A (zh) * 2024-02-02 2024-03-15 深圳飞骧科技股份有限公司 跨导增强的低噪声放大器及射频芯片

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