WO2025112982A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2025112982A1
WO2025112982A1 PCT/CN2024/126205 CN2024126205W WO2025112982A1 WO 2025112982 A1 WO2025112982 A1 WO 2025112982A1 CN 2024126205 W CN2024126205 W CN 2024126205W WO 2025112982 A1 WO2025112982 A1 WO 2025112982A1
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WIPO (PCT)
Prior art keywords
initialization signal
signal bus
display substrate
initialization
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/126205
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English (en)
French (fr)
Inventor
胡明
刘庭良
董向丹
黄耀
青海刚
张毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025112982A1 publication Critical patent/WO2025112982A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • OLED organic light-emitting diode
  • a display substrate in one aspect, includes a display area and a peripheral area surrounding the display area.
  • the peripheral area includes a first frame area, a second frame area, a third frame area, and a fourth frame area, the first frame area and the second frame area are arranged on both sides of the display area along a first direction, the third frame area and the fourth frame area are arranged on both sides of the display area along a second direction, and the first direction and the second direction intersect.
  • the display substrate further includes at least one first binding electrode group, a first initialization signal bus, a second initialization signal bus, a third initialization signal bus and a plurality of initialization signal lines.
  • the first binding electrode group is located in the third frame area, and each of the first binding electrode groups is used to connect a driver chip; the first initialization signal bus is arranged in the first frame area; the second initialization signal bus is arranged in the second frame area; the third initialization signal bus is arranged in the third frame area; the third initialization signal bus is connected to the first initialization signal bus and the second initialization signal bus, and is connected to the first binding electrode group; a plurality of initialization signal lines are arranged at least in the display area, and are connected to the first initialization signal bus, the second initialization signal bus and the third initialization signal bus.
  • the display substrate further includes a data writing transistor, a second reset transistor, a second scanning signal line, and a second reset control signal line.
  • the gate of the data writing transistor is electrically connected to the second scanning signal line
  • the gate of the second reset transistor is electrically connected to the second reset control signal line.
  • the second scan signal line has a first refresh frequency
  • the second reset control signal line has a second refresh frequency
  • the second refresh frequency is greater than the first refresh frequency
  • the display substrate further includes at least one initialization signal first connection line group.
  • Each of the initialization signal first connection line groups includes a plurality of initialization signal first connection lines, and the plurality of initialization signal first connection lines are located in the third border area and between the first binding electrode group and the third initialization signal bus, and are used to connect the first binding electrode group and the third initialization signal bus.
  • the display substrate further includes a first source-drain metal layer and a second source-drain metal layer which are stacked.
  • the third initialization signal bus and the first connection line group of the initialization signal are located in the first source-drain metal layer or the second source-drain metal layer; or, one of the third initialization signal bus and the first connection line group of the initialization signal is located in the first source-drain metal layer, and the other is located in the second source-drain metal layer.
  • the initialization signal lines include a plurality of first initialization signal lines extending along the second direction and a plurality of second initialization signal lines extending along the first direction.
  • the plurality of first initialization signal lines extend to the third border area and are connected to the third initialization signal bus
  • the plurality of second initialization signal lines extend to the first border area and the second border area and are respectively connected to the first initialization signal bus and the second initialization signal bus; the plurality of first initialization signal lines are connected to the plurality of second initialization signal lines.
  • the display substrate further comprises two stacked source-drain metal layers.
  • the third initialization signal bus and the plurality of first initialization signal lines are located in different source-drain metal layers; the plurality of first initialization signal lines and the plurality of second initialization signal lines are located in different source-drain metal layers.
  • the display substrate further includes a plurality of light-emitting devices, a first voltage signal bus, and a plurality of first voltage signal lines extending along the second direction.
  • the first voltage signal bus is disposed in the third frame area; located on one side of the third initialization signal bus in the second direction; the first voltage signal bus is connected to the cathode of the light-emitting device; the first voltage signal line is at least disposed in the display area and extends to the third frame area, and the plurality of first voltage signal lines are connected to the first voltage signal bus; in the third frame area, the plurality of first initialization signal lines and the plurality of first voltage signal lines are alternately disposed along the first direction.
  • the display substrate further comprises two stacked source-drain metal layers.
  • the first voltage signal bus and the third initialization signal bus are located in the same source-drain metal layer; the first voltage signal bus and the plurality of first voltage signal lines are located in different source-drain metal layers.
  • the display substrate further includes a plurality of pixel circuits, a reference voltage signal bus, and a plurality of reference voltage signal lines extending along the second direction.
  • the pixel circuit includes a driving transistor, a writing transistor, and a first reset transistor, wherein the driving transistor, the writing transistor, and the first reset transistor are electrically connected to a first node, and the first reset transistor is configured to transmit a reference voltage signal to the first node;
  • the reference voltage signal bus is disposed in the third frame area and is located on one side of the third initialization signal bus along the second direction;
  • the reference voltage signal bus is configured to transmit a reference voltage signal;
  • a plurality of reference voltage signal lines are at least disposed in the display area and extend to the third frame area, and the plurality of reference voltage signal lines are connected to the reference voltage signal bus; in the third frame area, a plurality of the first initialization signal lines and a plurality of the reference voltage signal lines are alternately disposed along the first direction.
  • the display substrate further comprises two stacked source-drain metal layers.
  • the reference voltage signal bus and the third initialization signal bus are located in the same source-drain metal layer; the reference voltage signal bus and the plurality of reference voltage signal lines are located in different source-drain metal layers.
  • the display substrate further comprises at least one second binding electrode group and a fourth initialization signal bus.
  • the second binding electrode group is located in the fourth border area, and the second binding electrode group is used to connect to the driving chip;
  • the fourth initialization signal bus is located in the fourth border area, connected to the first initialization signal bus, the second initialization signal bus, and the second binding electrode group; the plurality of initialization signal lines are also connected to the fourth initialization signal bus.
  • the display substrate further includes an initialization signal second connection line group.
  • the initialization signal second connection line group includes a plurality of initialization signal second connection lines, which are located in the fourth frame area and between the second binding electrode group and the fourth initialization signal bus, and are used to connect the second binding electrode group and the fourth initialization signal bus.
  • a display device comprising: a display substrate as described in any one of the above embodiments.
  • FIG1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG2A is an equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure.
  • FIG2B is a timing signal control diagram of a pixel driving circuit provided by some embodiments of the present disclosure.
  • FIG3 is a structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG4 is a schematic diagram of the display substrate in FIG3 generating horizontal stripes
  • FIG5 is another structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG6 is another structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG7 is a partial structural diagram of area B in FIG5 ;
  • FIG8 is another structural diagram of a display substrate according to some embodiments of the present disclosure.
  • FIG. 9 is another structural diagram of a display substrate according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and the area of regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the drawings shown herein.
  • the shapes of the regions are not limited to the shapes of the devices, but include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the example embodiments.
  • a display device 1000 which can be any product or component with a display function, such as a television, a monitor, a laptop, a tablet computer, a mobile phone, a navigator, etc.
  • the display device 1000 is illustrated as a mobile phone.
  • the display device 1000 described above may be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
  • PDAs personal data assistants
  • GPS receivers/navigators cameras
  • the display device 1000 may be an electroluminescent display device or a photoluminescent display device.
  • the electroluminescent display device may be an organic light emitting diode (OLED) or a quantum dot electroluminescent display device (QLED).
  • the display device is a photoluminescent display device
  • the photoluminescent display device may be a quantum dot photoluminescent display device.
  • the display device 1000 may be a low temperature polycrystalline oxide (LTPO) display device, wherein the LTPO display device can support a variety of refresh rates, for example, from 120 Hz to 1 Hz.
  • LTPO low temperature polycrystalline oxide
  • the display device 1000 includes a display substrate 100 .
  • the structure of the display substrate 100 is described in detail below.
  • Figure 3 is a structural diagram of a display substrate 100' provided in some embodiments
  • Figure 5 is a structural diagram of a display substrate 100 provided in some embodiments of the present disclosure.
  • the display substrate 100 includes a display area AA and a peripheral area AN surrounding the display area AA.
  • the peripheral area AN includes a first frame area 11, a second frame area 12, a third frame area 13 and a fourth frame area 14.
  • the first frame area 11 and the second frame area 12 are arranged on both sides of the display area AA along the first direction X
  • the third frame area 13 and the fourth frame area 14 are arranged on both sides of the display area AA along the second direction Y.
  • the first direction X and the second direction Y intersect, and illustratively, the first direction X and the second direction Y are perpendicular.
  • the display area AA of the display substrate 100 is used to display images.
  • a display device is disposed in the display area AA.
  • the embodiments of the present disclosure include but are not limited to these, and any other display substrates may also be considered as long as the same technical concept is applied.
  • a plurality of pixel units are disposed in the display area AA, and each pixel unit includes at least three sub-pixels P.
  • the sub-pixel P is the smallest light-emitting unit in the display area AA.
  • the plurality of pixel units are arranged in a plurality of rows and columns.
  • the plurality of sub-pixels P emit light of the same color
  • the display area AA may further include a color filter layer disposed on the light emitting side of the plurality of sub-pixels P.
  • multiple sub-pixels P emit white light, red light, green light, blue light or other color light.
  • the color light emitted by the sub-pixel P remains the same color light after passing through the color filter layer, or is converted into other color light for emission. Therefore, when multiple sub-pixels P emit the same color light, the display area AA can achieve multi-color light emission.
  • multiple sub-pixels P emit light of different colors.
  • multiple sub-pixels P include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light, thereby realizing multi-color light emission in the display area AA.
  • each pixel unit includes at least three sub-pixels P, that is, each pixel unit may include three, four or more sub-pixels P, and the multiple sub-pixels P included in each pixel unit may be a row, a column or a group of sub-pixels, and a group of sub-pixels P may be a plurality of sub-pixels P adjacent to each other, and the adjacent plurality of sub-pixels P are arranged in a row, a column, an L shape, a rectangle or a diamond shape, etc.
  • the light emitting areas of the multiple sub-pixels P included in each pixel unit may be the same or different.
  • the above is only an exemplary description and is not intended to limit the present disclosure.
  • the specific adaptive design can be carried out according to actual needs.
  • the sub-pixel includes a pixel driving circuit, as shown in FIG2A , which is a schematic diagram of an equivalent circuit of a pixel driving circuit provided in some embodiments of the present disclosure.
  • FIG2A takes the pixel driving circuit as an 8T1C structure as an example for illustration, but the structure of the pixel driving circuit in the present disclosure is not limited thereto, for example, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure.
  • T represents a transistor
  • the number in front of T represents the number of transistors
  • C represents a capacitor
  • the number in front of C represents the number of capacitors.
  • the pixel driving circuit may include eight transistors (transistor T1 to transistor T8 ) and one storage capacitor C. As shown in FIG.
  • the pixel driving circuit may further include a first node N1, a second node N2, a third node N3 and a fourth node N4.
  • the nodes do not represent actual components, but represent the junction points of related electrical connections in the equivalent circuit schematic diagram of the pixel driving circuit, that is, these nodes are nodes formed by the junction points of related electrical connections in the equivalent circuit schematic diagram of the pixel driving circuit.
  • the first node N1 is connected to the gate of the driving transistor T3, the first plate of the storage capacitor C and the source of the threshold compensation transistor T2, respectively;
  • the second node N2 is connected to the source of the driving transistor T3, the first light emitting control transistor C and the second light emitting control transistor T3, respectively.
  • the drain of the data writing transistor T5, the drain of the data writing transistor T4 and the drain of the third reset transistor T8 are connected, the third node N3 is respectively connected to the drain of the first reset transistor T1, the source of the threshold compensation transistor T2, the source of the second light emitting control transistor T6 and the drain of the driving transistor T3, and the fourth node N4 is respectively connected to the drain of the second light emitting control transistor T6, the drain of the second reset transistor T7 and the light emitting device D.
  • the second plate of the storage capacitor C is electrically connected to the first power voltage line VDD, and the first plate of the storage capacitor C is connected to the first node N1, that is, the first plate of the storage capacitor C is connected to the gate of the driving transistor T3.
  • the source of the first reset transistor T1 is configured to be electrically connected to the initialization signal line Vinit to receive the initialization signal
  • the drain of the first reset transistor T1 is electrically connected to the drain of the driving transistor T3
  • the gate of the first reset transistor T1 is configured to be electrically connected to the first reset control signal line Preset1 to receive the reset control signal.
  • the source of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 , the drain of the threshold compensation transistor T2 is electrically connected to the drain of the driving transistor T3 , and the gate of the threshold compensation transistor T2 is configured to be electrically connected to the first scanning signal line Ngate to receive the compensation control signal.
  • the gate of the driving transistor T3 is connected to the first plate of the storage capacitor C, the source of the driving transistor T3 is connected to the second node N2, and the drain of the driving transistor T3 is connected to the third node N3.
  • the driving transistor T3 determines the magnitude of the driving current flowing between the second voltage signal line VDD and the first voltage signal line VSS according to the potential difference between the gate and the source thereof.
  • the drain of the data writing transistor T4 is electrically connected to the source of the driving transistor T3, the source of the data writing transistor T4 is configured to be electrically connected to the data signal line Data to receive the data signal, and the gate of the data writing transistor T4 is configured to be electrically connected to the second scanning signal line Pgate to receive the scanning signal.
  • the source of the first light emitting control transistor T5 is electrically connected to the second voltage signal line (VDD) 91, the drain of the first light emitting control transistor T5 is electrically connected to the source of the driving transistor T3, and the gate of the first light emitting control transistor T5 is configured to be electrically connected to the light emitting control signal line EM to receive a light emitting control signal.
  • the source of the second light emitting control transistor T6 is electrically connected to the drain of the driving transistor T3, the drain of the second light emitting control transistor T6 is electrically connected to the first electrode of the light emitting device D, and the gate of the second light emitting control transistor T6 is configured to be electrically connected to the light emitting control signal line EM to receive a light emitting control signal.
  • the source of the second reset transistor T7 is configured to be electrically connected to the initialization signal line Vinit to receive the initialization signal
  • the drain of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device D
  • the gate of the second reset transistor T7 is configured to be electrically connected to the second reset control signal line Preset2 to receive the reset control signal.
  • the source of the third reset transistor T8 is configured to be electrically connected to the reference voltage signal line Vref to receive the reference voltage signal
  • the drain of the third reset transistor T8 is electrically connected to the source of the driving transistor T3
  • the gate of the third reset transistor T8 is configured to be connected to the second reset control signal line Preset2 to receive the reset control signal.
  • the second electrode of the light emitting device D is electrically connected to the first voltage signal line (VSS) 62 .
  • the first scanning signal line Ngate is used to transmit the first scanning signal
  • the second scanning signal line Pgate is used to transmit the first scanning signal.
  • the first reset control signal line Preset1 is used to transmit the first reset control signal
  • the second reset control signal line is used to transmit the second reset control signal
  • the second voltage signal line VDD is used to transmit the second voltage signal, for example, a high-voltage DC signal
  • the initialization signal line Vinit is used to transmit the initialization signal
  • the data signal line Data is used to transmit the data signal
  • the light-emitting control signal line EM is used to transmit the light-emitting control signal
  • the first voltage signal line VSS is used to transmit the first voltage signal, for example, a low-voltage DC signal.
  • transistors T1 to T8 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate 100, and improve the yield of the product.
  • transistors T1 to T8 may include P-type transistors and N-type transistors, wherein transistor T2 is an N-type transistor, and the remaining transistors are P-type transistors.
  • transistors T1 to T8 may be low-temperature polysilicon thin film transistors, or may be oxide thin film transistors, or may be low-temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low-temperature polysilicon thin film transistor uses low-temperature polysilicon (Low Temperature Poly-Silicon, referred to as LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide).
  • LTPS Low Temperature Poly-Silicon
  • oxide semiconductor Oxide
  • Low-temperature polysilicon thin film transistors and oxide thin film transistors are integrated on a display substrate 100 to form a low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide, referred to as LTPO) display substrate.
  • LTPO Low Temperature Polycrystalline Oxide
  • the display substrate 100 switches the refresh frequency
  • One of the adjustment methods is to reduce the refresh frequency on the basis of the basic refresh frequency (i.e., base frequency), and the refresh frequency can generally be reduced by an integer multiple.
  • the refresh frequency is reduced by an integer multiple, it can be called interpolation frequency modulation.
  • the display frame of the basic refresh frequency includes a write frame.
  • the display frame after the refresh frequency is reduced on the basis of the basic refresh frequency includes a write frame and a hold frame, and the duration of the write frame and the hold frame is the same.
  • the refresh frequency of the display substrate 100 is reduced by inserting a hold frame between adjacent write frames, and the reduction multiple of the refresh frequency is changed by changing the number of hold frames inserted between adjacent write frames.
  • the basic refresh frequency is 120HZ
  • the refresh frequency is reduced to 60HZ after inserting a hold frame
  • the refresh frequency is reduced to 40HZ after inserting two hold frames, and so on.
  • the switching of two different refresh frequencies can be a switching between a basic refresh frequency and a refresh frequency after the basic refresh frequency is reduced, or it can be a switching between two refresh frequencies after the same basic refresh frequency is reduced.
  • the data writing of all rows of pixels is completed between every two refreshes (1s/120), and the time between starting the data writing of the pixel driving circuit of the first row in the display area AA and completing the data writing of the pixel driving circuit of the last row corresponds to the length of one display frame. Therefore, in this case 1s includes 120 display frames.
  • each pixel driving circuit still controls the light-emitting element D to emit light according to the voltage on its storage capacitor C and the light-emitting control signal EM.
  • Figure 2B is a timing signal control diagram of a pixel driving circuit provided by some embodiments of the present disclosure.
  • the second scanning signal line Pgate has a first refresh frequency; the second reset control signal line Preset2 has a second refresh frequency.
  • the second refresh frequency is greater than the first refresh frequency.
  • the first refresh frequency may be 120 Hz, and the second refresh frequency may be 360 Hz.
  • the refresh frequency of the display substrate 100 is consistent with the frequency of writing the data signal, that is, the refresh frequency of the display substrate 100 is the first refresh frequency of the second scanning signal line Pgate. Every time the second scanning signal line Pgate is refreshed and a data signal is written, the second reset control signal line Preset2 also needs to be refreshed, and the initialization signal is written to reset the first electrode of the light-emitting device D to avoid the influence of the data signal written in the previous frame on the data signal written in the current frame, resulting in poor uniformity of light emission of the display substrate 100.
  • the refresh frequency of the display substrate 100 is to be switched (for example, the refresh frequency is reduced)
  • the first refresh frequency of the second scan signal line Pgate and the second refresh frequency of the second reset control signal line Preset2 need to be changed simultaneously, that is, the basic refresh frequency needs to be reduced by integer multiples by increasing the holding frame (that is, the above-mentioned interpolation frequency modulation).
  • the first refresh frequency can be 120Hz
  • the refresh frequency switching of 30Hz, 40Hz or 60Hz can be realized to ensure that each time the second scan signal line Pgate is refreshed, the second reset control signal line Preset2 is also refreshed. In this way, the signal waveform of the signal line is greatly changed.
  • the refresh frequency of the display substrate 100 is reduced, and both the first refresh frequency and the second refresh frequency are reduced, the screen flickers, affecting the display effect.
  • the second refresh frequency of the second reset control signal line Preset2 is set to be greater than the first refresh frequency of the second scan signal line Pgate, for example, it is set to three times the original frequency, which is 360Hz, so that more refresh frequency switching can be supported and the screen flickering phenomenon can be improved.
  • the second refresh frequency of the second reset control signal line Preset2 is relatively large, that is, in each frame stage, the signal transmitted by the second reset control signal line has a working level, which can reset the first electrode of the light-emitting device D.
  • the refresh frequency of the display substrate 100 is to be switched (for example, the refresh frequency is reduced)
  • only the first refresh frequency of the second scan signal line Pgate needs to be changed, and the second refresh frequency of the second reset control signal line Preset2 does not need to be changed. It can also ensure that the second reset control signal line Preset2 is also refreshed every time the second scan signal line Pgate is refreshed, thereby simplifying the modification of the timing signal of the signal line.
  • the screen refresh effect is visually achieved, thereby improving the screen flickering problem caused by the reduction of the refresh rate of the display substrate 100.
  • the first scan signal line Ngate has a first refresh frequency; the first reset control signal line Preset1 has a second refresh frequency. Since the first scan signal line Ngate also needs to be refreshed when the second scan signal line Pgate refreshes the write data signal, the threshold compensation transistor T2 is turned on for threshold compensation. When the first scan signal line Preset2 is reset to reset the fourth node N4, the first reset control signal line Preset1 is also refreshed to reset the third node N3. Therefore, the setting principle of the refresh frequency of the first scan signal line Ngate and the first reset control signal line Preset1 is consistent with the setting principle of the second scan signal line Pgate and the second reset control signal line Preset2, which will not be repeated here.
  • each three adjacent frame stages form a group
  • the first frame stage in a group is a writing frame stage, which is responsible for writing the display signal and emitting light
  • the second frame stage and the third frame stage are both holding frame stages, which are responsible for emitting light based on the display signal written in the writing frame stage.
  • the driving process of the above pixel driving circuit is divided into a writing frame stage and a holding frame stage:
  • a writing frame phase includes a first reset phase t1, a data refresh and compensation phase t2, a second reset phase t3 and a first light emitting phase t4.
  • the threshold compensation transistor T2 is turned on under the control of the first scanning signal
  • the first reset transistor T1 is turned on under the control of the first reset control signal, so that the initialization signal is written to the first node N1, thereby resetting the first node N1.
  • the driving transistor T3 is turned on, the writing transistor T4, the first light emission control transistor T5 and the second light emission control transistor T6 are all in the off state, and the light emitting device OLED does not emit light.
  • the first reset transistor T1 is turned off under the control of the first reset control signal, the threshold compensation transistor T2 remains turned on, the write transistor T4 is turned on under the control of the second scan signal, and the drive transistor T3 maintains the turned-on state of the first reset stage t1, so the data signal can be transmitted to the first node N1 through the write transistor T4, the drive transistor T3 and the threshold compensation transistor T2 in sequence, so that the voltage of the first node N1 changes until the voltage of the first node N1 reaches the sum of the threshold voltage of the drive transistor T3 and the voltage of the data signal Data, so that the drive transistor T3 is turned off.
  • the threshold voltage of the drive transistor T3 can be written to the first node N1 to compensate for the threshold voltage drift of the drive transistor T3, avoid the change of the drive signal generated by the drive transistor, and avoid the influence on the light intensity of the light-emitting device D.
  • the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are in a disconnected state under the control of the light-emitting control signal.
  • the compensation transistor T2 is disconnected under the control of the first scan signal
  • the write transistor T4 is disconnected under the control of the second scan signal
  • the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal, so that the initialization signal is written into the second node N2 and the anode of the light-emitting device D, thereby resetting the second node N2 and the anode of the light-emitting device D (the fourth node N4).
  • the second reset transistor T7 and the third reset transistor T8 are turned off under the control of the second reset control signal, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, so that the first voltage signal is written into the first electrode region of the driving transistor T3, and the anode voltage of the light-emitting device D is The voltage may be written into the second electrode region of the driving transistor T3, thereby turning on the driving transistor T3, thereby forming a path between the first power supply voltage line VDD and the light emitting device D, so that the light emitting device D emits light.
  • each holding frame stage includes a third reset stage t5, a fourth reset stage t6 and a light emitting stage t7.
  • the threshold compensation transistor T2 is turned on under the control of the first scanning signal
  • the first reset transistor T1 is turned on under the control of the first reset control signal, so that the initialization signal is written to the first node N1, thereby resetting the first node N1.
  • the second reset transistor T7 and the third reset transistor T8 are turned on under the control of the second reset control signal, so that the initialization signal is written into the second node N2 and the anode of D, thereby resetting the second node N2 and the anode of the light emitting device D (the fourth node N4).
  • the second reset transistor T7 and the third reset transistor T8 are disconnected under the control of the second reset control signal, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal, so that the first voltage signal is written into the first electrode region of the driving transistor T3, and the anode voltage of the light-emitting device D can be written into the second electrode region of the driving transistor T3, so that the driving transistor T3 is turned on, thereby forming a path between the first power supply voltage line VDD and the light-emitting device D, so that the light-emitting device D emits light.
  • the initialization signal transmitted by the initialization signal line (Vinit) 40 resets the first node N1, the second node N2, the third node N3 or the fourth node N4 to change the potential of the above nodes, thereby raising or lowering the potential of the corresponding nodes of each pixel driving circuit to a uniform potential, avoiding interference from interference sources in the display substrate to the potential of the nodes of each pixel driving circuit, resulting in uneven display brightness. Therefore, the wiring of the initialization signal line is very important for the accuracy and uniformity of the transmitted initialization signal.
  • the wiring method of the initialization signal line (Vinit) 40 in the display substrate 100 is described in detail below.
  • the display substrate 100 ′ includes a first binding electrode group 21, a first initialization signal bus 31, a second initialization signal bus 32, and an initialization signal line 40.
  • the first binding electrode group 21 is located in the third frame area 13, and the first binding electrode group 21 is used to connect the driver chip 10; the first initialization signal bus 31 is arranged in the first frame area 11; the second initialization signal bus 32 is arranged in the second frame area 12; and a plurality of initialization signal lines 40 are arranged at least in the display area AA, and are connected to the first initialization signal bus 31 and the second initialization signal bus 32.
  • initialization signal lines 40 introduce initialization signals from both sides of the display area AA through the first initialization signal bus 31 and the second initialization signal bus 32. Due to the existence of resistance on the initialization signal line, a voltage drop will be generated during the transmission of the initialization signal, and there is a difference between the voltage drop of the initialization signal line close to the first border area 11 or the second border area 12 and the voltage drop far away from the first border area 11 or the second border area 12.
  • the second refresh frequency of the second reset control signal line Preset2 is relatively large, for example, 360 Hz.
  • the reset time of the N4 node will be reduced.
  • the N4 node will be reset.
  • the node reset time is 1/360s, which will result in insufficient reset of the N4 node when the display substrate 100 displays low grayscale, causing defects such as horizontal stripes, that is, as shown in FIG. 4 , multiple (three) stripes appear in the display area AA of the display substrate 100 .
  • the display area AA of the display substrate 100 is more likely to have multiple (three) stripes as shown in FIG. 4 .
  • the display substrate 100 includes at least one first binding electrode group 21, a first initialization signal bus 31, a second initialization signal bus 32, a third initialization signal bus 33, and a plurality of initialization signal lines 40.
  • At least one first binding electrode group 21 is located in the third frame area 13, and each first binding electrode group 21 is used to connect a driving chip 10; the first initialization signal bus 31 is arranged in the first frame area 11; the second initialization signal bus 32 is arranged in the second frame area 12; the third initialization signal bus 33 is arranged in the third frame area 13; the third initialization signal bus 33 is connected to the first initialization signal bus 31 and the second initialization signal bus 32, and is connected to the first binding electrode group 21; the plurality of initialization signal lines 40 are arranged at least in the display area AA, and are connected to the first initialization signal bus 31, the second initialization signal bus 32, and the third initialization signal bus 33.
  • the third initialization signal bus 33 is connected to the first initialization signal bus 31 and the second initialization signal bus 32, and is connected to the binding electrode group 21.
  • the plurality of initialization signal lines 40 are also connected to the third initialization signal bus 33.
  • the initialization signal can be transmitted to the initialization signal line 40 through the first initialization signal bus 31, the second initialization signal bus 32 and the third initialization signal bus 33 at the same time, and the portion of the initialization signal line 40 away from the first initialization signal bus 31 and the second initialization signal bus 32 can receive the initialization signal through the third initialization signal bus 33, which can reduce the voltage drop (IR Drop) difference between the plurality of initialization signal lines 40 at the middle position and the edge position of the display area AA, so that the initialization signals received by the plurality of sub-pixels tend to be consistent, and the display substrate 100 can avoid display defects such as horizontal stripes.
  • IR Drop voltage drop
  • the driver chip 10 may be packaged by Chip On Film (COF), Chip On Glass (COG), or Chip On Pi (COP), and bound to the third frame area 13.
  • COF Chip On Film
  • the driver chip 10 may be packaged by Chip On Film (COF)
  • the display substrate 100 includes a COF assembly
  • the COF assembly includes a Flexible Printed Circuit (FPC) and the driver chip 10 bound to the FPC.
  • FPC Flexible Printed Circuit
  • the display substrate 100 may include one, two, three, four or more first binding electrode groups 21.
  • FIG6 is another structural diagram of the display substrate 100 provided in some embodiments of the present disclosure.
  • the display substrate 100 may include four first binding electrode groups 21, each first binding electrode group 21 is connected to a corresponding driving chip 10, that is, four driving chips 10 are also provided accordingly, and the four first binding electrode groups 21 can be provided in the third border area 13, and are respectively connected to the third initialization signal bus 33 and transmit the initialization signal, which is conducive to further reducing the voltage drop (IR Drop) of the initialization signal line and improving the display effect of the display substrate 100.
  • IR Drop voltage drop
  • the third frame region 13 of the display substrate 100 includes a non-bending region and a bending region.
  • the non-bending area is far away from the display area AA
  • the third initialization signal bus 33 is located in the non-bending area
  • multiple first binding electrode groups 21 are located in the bending area.
  • the bending area can be bent toward the non-display side of the display substrate 100, that is, bent to the back of the display substrate 100 to reduce the frame of the display substrate 100.
  • the driving chip 10 is arranged on the back of the display substrate 100, and the driving chip 10 is connected to the first binding electrode group 21 through a flexible circuit board.
  • the display substrate 100 may further include at least one second binding electrode group 22 and a fourth initialization signal bus 34.
  • the second binding electrode group 22 is located in the fourth frame area 14 and is used to connect the driver chip 10; the fourth initialization signal bus 34 is also located in the fourth frame area 14, and the fourth initialization signal bus 34 is respectively connected to the first initialization signal bus 31 and the second initialization signal bus 32, and is connected to the second binding electrode group 22; a plurality of initialization signal lines 40 are also connected to the fourth initialization signal bus 34.
  • the second binding electrode group 22 is connected to the driver chip 10 in the third frame area 13 and transmits the initialization signal.
  • the fourth initialization signal bus 34 is connected to the first initialization signal bus 31 and the second initialization signal bus 32, that is, the first initialization signal bus 31, the second initialization signal bus 32, the third initialization signal bus 33 and the fourth initialization signal bus 34 are connected to each other to form a ring structure, and the fourth initialization signal bus 34 is also connected to the second binding electrode group 22 for transmitting the initialization signal, and the plurality of initialization signal lines 40 are connected to the fourth initialization signal bus 34 in addition to being connected to the first initialization signal bus 31, the second initialization signal bus 32 and the third initialization signal bus 33.
  • the initialization signal can be transmitted to the initialization signal line 40 through the first initialization signal bus 31, the second initialization signal bus 32, the third initialization signal bus 33 and the fourth initialization signal bus 34 at the same time, which can further reduce the voltage drop (IR Drop) difference between the initialization signal line 40 at the middle position and the edge position of the display area AA, avoid the display substrate 100 from having poor display such as horizontal stripes, and improve the display uniformity of the display substrate 100.
  • IR Drop voltage drop
  • the display substrate 100 may include one, two, three, four or more second binding electrode groups 22.
  • the display substrate 100 may include two second binding electrode groups 22, each second binding electrode group 22 is connected to a corresponding driving chip 10, and the two second binding electrode groups 22 may be arranged in the fourth border area 14, and respectively connected to the fourth initialization signal bus 34 and transmit the initialization signal, which is beneficial to further reduce the voltage drop (IR Drop) of the initialization signal line and improve the display effect of the display substrate 100.
  • IR Drop voltage drop
  • the fourth frame area 14 of the display substrate 100 includes a non-bending area and a bending area, the bending area is relatively far away from the display area AA relative to the non-bending area, the fourth initialization signal bus 34 is located in the non-bending area, and the plurality of second binding electrode groups 22 are located in the bending area, and the bending area can be bent toward the non-display side of the display substrate 100, that is, bent to the back of the display substrate 100, so as to reduce the frame of the display substrate 100.
  • the driving chip 10 is disposed on the back of the display substrate 100, and the driving chip 10 is connected to the second binding electrode group 22 through a flexible circuit board disposed on the back of the display substrate 100.
  • the first binding electrode group 21 and the second binding electrode group 22 can be connected to the same driver chip 10.
  • the second binding electrode group 22 is connected to the driver chip 10 connected to the first binding electrode group 21 through a flexible circuit board.
  • the resistance of the wiring in the display substrate 100 is smaller than that of the wiring in the display substrate 100. Therefore, a second binding electrode group 22 is set in the fourth border area 14 of the display substrate 100 and bent to the back of the display substrate 100.
  • the third border area 13 and the fourth border area 14 of the display substrate 100 are connected through a flexible circuit board. This can reduce the signal voltage drop and further improve the uniformity of the initialization signal in the display area AA, thereby improving the uniformity of the display.
  • the display substrate 100 also includes at least one initialization signal first connection line group 51; each initialization signal first connection line group 51 includes a plurality of initialization signal first connection lines 511, and the plurality of initialization signal first connection lines 511 are located in the third border area 13, and are located between the first binding electrode group 21 and the third initialization signal bus 33, and are used to connect the first binding electrode group 21 and the third initialization signal bus 33, and transmit the initialization signal.
  • the voltage drop (IR Drop) of the initialization signal on the third initialization signal bus 33 can be reduced, which is beneficial to improving the display effect of the display substrate 100.
  • one of the multiple initialization signal first connection lines 511 is also connected to an end of the first initialization signal bus near the third border area, and another of the multiple initialization signal first connection lines 511 is also connected to an end of the second initialization signal bus near the third border area.
  • the initialization signal is transmitted from the first binding electrode group 21 to the first initialization signal bus and the second initialization signal bus through the initialization signal first connection line 511, and is also transmitted to the third initialization signal bus, thereby realizing signal transmission between the first binding electrode group and the initialization signal bus.
  • the number of initialization signal first connection lines 511 in each initialization signal first connection line group 51 can be set to two, three, four, five, seven, eight or nine, as long as sufficient wiring space is ensured and the initialization signal first connection lines 511 do not have the risk of short circuit with other metal wirings in the display substrate 100, or multiple initialization signal first connection lines 511 do not overlap or affect each other, and no specific limitation is made herein.
  • the display substrate 100 also includes at least one initialization signal second connection line group 52; each initialization signal second connection line group 52 includes a plurality of initialization signal second connection lines 512, and the plurality of initialization signal second connection lines 512 are located in the fourth border area 14, and are located between the second binding electrode group 22 and the fourth initialization signal bus 34, and are used to connect the second binding electrode group 22 and the fourth initialization signal bus 34, and transmit the initialization signal.
  • the voltage drop (IR Drop) of the initialization signal on the fourth initialization signal bus 34 can be reduced, which is beneficial to improving the display effect of the display substrate 100 .
  • the number of the initialization signal second connection lines 512 in each initialization signal second connection line group 52 can be set to two, three, four, five, seven, eight or nine, as long as sufficient wiring space is ensured and the initialization signal second connection lines 512 are not short-circuited with other metal wirings in the display substrate 100, or It is sufficient that the plurality of initialization signal second connection lines 512 do not overlap with each other and do not affect each other, and no specific limitation is made herein.
  • the initialization signal line 40 includes a plurality of first initialization signal lines 401 and a plurality of second initialization signal lines 402.
  • Each first initialization signal line 401 extends along the second direction Y to the third frame area 13, and is connected to the third initialization signal bus 33, and the plurality of first initialization signal lines 401 are arranged in sequence along the first direction X;
  • each second initialization signal line 402 extends along the first direction X to the first frame area 11 and the second frame area 12, and is respectively connected to the first initialization signal bus 31 and the second initialization signal bus 32, and the plurality of second initialization signal lines 402 are arranged in sequence along the second direction Y; the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 are connected so that the initialization signal line 40 forms a mesh structure.
  • the initialization signals provided by the first initialization signal bus 31, the second initialization signal bus 32 and the third initialization signal bus 33 are dispersedly transmitted through the initialization signal line 40 of the mesh structure, which can further reduce the voltage drop of the initialization signal on the transmission path and improve the uniformity of the initialization signal, thereby further improving the display uniformity and avoiding display defects such as horizontal stripes on the display substrate.
  • the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 may be arranged in the same layer or in different layers.
  • the two may be arranged as one; when the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 are arranged in different layers, the two may be electrically connected by punching, or transferred through other conductive parts, without any specific limitation here.
  • Figure 7 is a partial structural diagram of area B in Figure 5.
  • the display substrate 100 also includes a first voltage signal bus 61 and a plurality of first voltage signal lines 62.
  • the first voltage signal bus 61 is arranged in the third frame area 13 and is located on one side of the third initialization signal bus 33 in the second direction Y; the first voltage signal bus 61 is connected to the cathode of the light-emitting device and is used to transmit a voltage signal to the light-emitting device.
  • the plurality of first voltage signal lines 62 extend along the second direction Y, are at least arranged in the display area AA, and extend to the third frame area 13, and the plurality of first voltage signal lines 62 are connected to the first voltage signal bus 61.
  • the plurality of first initialization signal lines 401 and the plurality of first voltage signal lines 62 are alternately arranged along the first direction X.
  • each first initialization signal line 401 and each first voltage signal line 62 are alternately arranged along the first direction X” includes that each first initialization signal line 401 and each first voltage signal line 62 are regularly alternately arranged along the first direction X.
  • each initialization signal line 401 is electrically connected to a column of sub-pixels P
  • each first voltage signal line 62 is electrically connected to a column of sub-pixels P.
  • the display substrate 100 further includes a reference voltage signal bus 71 and a plurality of reference voltage signal lines 72.
  • the reference voltage signal bus 71 is disposed in the third frame area 13 and is located on one side of the third initialization signal bus 33 along the second direction Y.
  • the reference voltage signal bus 71 is configured to transmit a reference voltage signal; the plurality of reference voltage signal lines 72 are connected to the reference voltage signal bus 71.
  • the reference voltage signal line 72 extends along the second direction Y, is at least arranged in the display area AA, and extends to the third frame area 13, and multiple reference voltage signal lines 72 are connected to the reference voltage signal bus 71; in the third frame area 13, multiple first initialization signal lines 401 and multiple reference voltage signal lines 72 are alternately arranged along the first direction X.
  • multiple first initialization signal lines 401 and multiple reference voltage signal lines 72 are alternately arranged along the first direction X may mean that multiple first initialization signal lines 401 and multiple reference voltage signal lines 72 are regularly alternately arranged along the first direction X.
  • each initialization signal line 401 is electrically connected to a column of sub-pixels P
  • each reference voltage signal line 72 is electrically connected to a column of sub-pixels P.
  • a plurality of first initialization signal lines 401 , a plurality of first voltage signal lines 62 , and a plurality of reference voltage signal lines 72 are alternately arranged along the first direction X.
  • multiple first initialization signal lines 401, multiple first voltage signal lines 62 and multiple reference voltage signal lines 72 are alternately arranged along the first direction X may mean that multiple first initialization signal lines 401, multiple first voltage signal lines 62 and multiple reference voltage signal lines 72 are regularly alternately arranged along the first direction X.
  • a first initialization signal line 401, a first voltage signal line 62 and a reference voltage signal line 72 are a group regularly alternately arranged along the first direction X, which is conducive to maintaining good wiring repeatability.
  • a plurality of first initialization signal lines 401, a plurality of first voltage signal lines 62, and a plurality of reference voltage signal lines 72 may be arranged alternately and irregularly along the first direction X.
  • the signal line wiring method corresponding to one pixel unit may be one first initialization signal line 401, one first voltage signal line 62, and one first initialization signal line 401
  • the signal line wiring method corresponding to another pixel unit adjacent to the above pixel unit may be one first initialization signal line 401 and two reference voltage signal lines 72.
  • the display substrate further includes a plurality of data signal lines 81 and a plurality of second voltage signal lines 91 extending along the second direction Y.
  • the plurality of data signal lines 81 and the plurality of second voltage signal lines 91 are arranged in the display area AA and extend to the third frame area 13. As shown in FIG. 7 , the plurality of data signal lines 81 and the plurality of second voltage signal lines 91 are arranged alternately in the first direction X, each data signal line 81 is electrically connected to a column of sub-pixels P, and each second voltage signal line 91 is electrically connected to a column of sub-pixels P.
  • multiple first initialization signal lines 401 and multiple data signal lines 81 are alternately arranged along the first direction X, which can avoid the multiple first initialization signal lines 401 and the multiple data signal lines 81 overlapping in the third border area 13 to cause a short circuit, and can reduce the difficulty of wiring in the third border area 13 .
  • the plurality of first initialization signal lines 401 and the plurality of second voltage signal lines 91 are alternately arranged along the first direction X, so that the plurality of first initialization signal lines 401 and the plurality of second voltage signal lines 91 can be prevented from overlapping in the third frame area 13 to cause a short circuit, and the wiring in the third frame area 13 can be reduced. Difficulty.
  • the display substrate 100 may include multiple metal layers stacked together, and the third initialization signal bus 33, the initialization signal first connection line group 51, multiple first initialization signal lines 401, the first voltage signal bus 61, multiple first voltage signal lines 62, the reference voltage signal bus 71 and the multiple reference voltage signal lines 72 are arranged in the above-mentioned multiple metal layers.
  • the display substrate 100 may be a low temperature polycrystalline oxide (LTPO) substrate.
  • LTPO low temperature polycrystalline oxide
  • FIG9 is a structural diagram of a display substrate 100 provided in some embodiments of the present disclosure.
  • the display substrate 100 includes a first active layer (Poly), a first gate metal layer (Gate1), a second gate metal layer (Gate2), a second active layer (not shown in the figure), a third gate metal layer (Gate3), a first source-drain metal layer (SD1), a first planar layer (PLN1), a second source-drain metal layer (SD2), and a second planar layer (PLN2) which are sequentially arranged and insulated from each other on a base substrate 101.
  • the substrate 101 may be a flexible substrate, such as a plastic substrate having excellent heat resistance and durability, such as polyvinyl ether phthalate, polyarylate, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), cycloolefin polymer (COP), cellulose acetate propionate (CAP), polyether sulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyphenylene sulfide (PPS), polyallyl ester, cellulose triacetate (TAC), etc.; it may also be a rigid substrate, such as a glass substrate, without any specific limitation herein.
  • a plastic substrate having excellent heat resistance and durability
  • PI polyvinyl ether phthalate
  • PET polyethylene terephthalate
  • PC polycarbonate
  • COP cycloolefin polymer
  • CAP cellulose acetate propionate
  • PAR polyether sulfone
  • PAR
  • the materials of the first flat layer (PLN1) and the second flat layer (PLN2) can be organic insulating materials such as polyacrylic resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, etc., without any specific limitation.
  • the materials of the metal film layers such as the first gate metal layer (Gate1), the second gate metal layer (Gate2), the third gate metal layer (Gate3), the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2) can be molybdenum (Mo), aluminum (Al), titanium (Ti) and other materials suitable for dry etching.
  • the above metal film layers can be single-layer metals or laminated metals.
  • the first gate metal layer (Gate1), the second gate metal layer (Gate2) and the third gate metal layer (Gate3) are single-layer molybdenum metals
  • the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2) are triple-layers consisting of titanium metal layer/aluminum metal layer/titanium metal layer.
  • the third initialization signal bus 33 and the initialization signal first connection line group 51 are located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the initialization signal first connection line group 51 are arranged in the same layer, and can be arranged at the first source-drain metal layer (SD1) or at the second source-drain metal layer (SD2) at the same time.
  • one of the third initialization signal bus 33 and the initialization signal first connection line group 51 is located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the initialization signal first connection line group 51 are arranged in different layers.
  • the third initialization signal bus 33 is arranged in the first source-drain metal layer (SD1)
  • the initialization signal first connection line group 51 is arranged in the second source-drain metal layer (SD2)
  • the initialization signal first connection line group 51 is arranged in the first source-drain metal layer (SD1).
  • the third initialization signal bus 33 and one of the multiple first initialization signal lines 401 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the first initialization signal line 401 are arranged in different layers.
  • the third initialization signal bus 33 is arranged in the first source-drain metal layer (SD1)
  • the first initialization signal line 401 is arranged in the second source-drain metal layer (SD2)
  • the third initialization signal bus 33 is arranged in the second source-drain metal layer (SD2)
  • the first initialization signal line 401 is arranged in the first source-drain metal layer (SD1).
  • one of the plurality of first initialization signal lines 401 and the plurality of second initialization signal lines 402 is located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the first initialization signal line 401 and the second initialization signal line 402 can be arranged in different layers.
  • the first initialization signal line 401 is arranged in the first source-drain metal layer (SD1)
  • the second initialization signal line 402 is arranged in the second source-drain metal layer (SD2)
  • the first initialization signal line 401 is arranged in the second source-drain metal layer (SD2)
  • the second initialization signal line 402 is arranged in the first source-drain metal layer (SD1).
  • the capacitance at the overlapping position with the signal line arranged on the lower metal layer (for example, the first gate metal layer, the second gate metal layer or the third gate metal layer) can be reduced, which is conducive to further reducing the voltage drop of the first initialization signal line 401 or the second initialization signal line 402, and further improving the display uniformity.
  • the third initialization signal bus 33 and the first voltage signal bus 61 can be located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the first voltage signal bus 61 are set in the same layer, and can be set at the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2) at the same time.
  • the first voltage signal bus 61 and one of the multiple first voltage signal lines 62 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the first voltage signal bus 61 and the first voltage signal line 62 can be set in different layers.
  • SD1 first source-drain metal layer
  • SD2 second source-drain metal layer
  • the first voltage signal line 62 is set in the first source-drain metal layer (SD1).
  • the third initialization signal bus 33 and the reference voltage signal bus 71 can be located in the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2), that is, the third initialization signal bus 33 and the reference voltage signal bus 71 are set in the same layer, and can be set at the first source-drain metal layer (SD1) or the second source-drain metal layer (SD2) at the same time.
  • the reference voltage signal bus 71 and one of the multiple reference voltage signal lines 72 are located in the first source-drain metal layer (SD1), and the other is located in the second source-drain metal layer (SD2), that is, the reference voltage signal bus 71 and the reference voltage signal line 72 can be set in different layers, when the reference voltage signal bus 71 is set in the first source-drain metal layer (SD1), the reference voltage signal line 72 is set in the second source-drain metal layer (SD2); when the reference voltage signal bus 71 is set in the second source-drain metal layer (SD2), the reference voltage signal line 72 is set in the first source-drain metal layer (SD1).

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Abstract

显示基板和显示装置，所述显示基板包括显示区以及围绕所述显示区的周边区。所述周边区包括第一边框区、第二边框区、第三边框区和第四边框区。所述显示基板还包括至少一个第一绑定电极组、第一初始化信号总线、第二初始化信号总线、第三初始化信号总线和多条初始化信号线。第一绑定电极组位于所述第三边框区；第一初始化信号总线设置于所述第一边框区；第二初始化信号总线设置于所述第二边框区；第三初始化信号总线设置于所述第三边框区；所述第三初始化信号总线和所述第一初始化信号总线、所述第二初始化信号总线连接，且与所述绑定电极组连接；多条初始化信号线至少设置于所述显示区。所述显示基板用于显示图像。

Description

显示基板及显示装置
本申请要求于2023年11月27日提交的、申请号为202311599718.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
随着显示技术的不断发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light-Emitting Diode，简称：OLED)显示面板由于具有自发光、低功耗、宽视角、响应速度快、高对比度等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。高刷新频率是目前显示装置的一个重要发展方向。
发明内容
一方面，提供一种显示基板。所述显示基板包括显示区以及围绕所述显示区的周边区。所述周边区包括第一边框区、第二边框区、第三边框区和第四边框区，所述第一边框区和所述第二边框区设置于所述显示区的沿第一方向的两侧，所述第三边框区和所述第四边框区设置于所述显示区沿第二方向的两侧，所述第一方向和所述第二方向交叉。
所述显示基板还包括至少一个第一绑定电极组、第一初始化信号总线、第二初始化信号总线、第三初始化信号总线和多条初始化信号线。第一绑定电极组位于所述第三边框区，每个所述第一绑定电极组用于连接一个驱动芯片；第一初始化信号总线设置于所述第一边框区；第二初始化信号总线设置于所述第二边框区；第三初始化信号总线设置于所述第三边框区；所述第三初始化信号总线和所述第一初始化信号总线、所述第二初始化信号总线连接，且与所述第一绑定电极组连接；多条初始化信号线至少设置于所述显示区，且与所述第一初始化信号总线、所述第二初始化信号总线和所述第三初始化信号总线连接。
在一些实施例中，所述显示基板还包括数据写入晶体管、第二复位晶体管、第二扫描信号线和第二复位控制信号线。所述数据写入晶体管的栅极和所述第二扫描信号线电连接，所述第二复位晶体管的栅极和所述第二复位控制信号线电连接。
其中，所述第二扫描信号线具有第一刷新频率，所述第二复位控制信号线具有第二刷新频率，所述第二刷新频率大于所述第一刷新频率。
在一些实施例中，所述显示基板还包括至少一个初始化信号第一连接线组。每个所述初始化信号第一连接线组包括多条初始化信号第一连接线，多条所述初始化信号第一连接线位于第三边框区，且位于所述第一绑定电极组和所述第三初始化信号总线之间，用于连接所述第一绑定电极组和所述第三初始化信号总线。
在一些实施例中，所述显示基板还包括层叠设置的第一源漏金属层和第二源漏金属层。 所述第三初始化信号总线和所述初始化信号第一连接线组位于第一源漏金属层或第二源漏金属层；或者，所述第三初始化信号总线和所述初始化信号第一连接线组中的一者位于第一源漏金属层，另一者位于第二源漏金属层。
在一些实施例中，所述初始化信号线包括沿所述第二方向延伸的多条第一初始化信号线和沿所述第一方向延伸的多条第二初始化信号线。所述多条第一初始化信号线延伸至第三边框区，且和所述第三初始化信号总线连接，所述多条第二初始化信号线延伸至所述第一边框区和所述第二边框区，且分别与所述第一初始化信号总线和所述第二初始化信号总线连接；多条所述第一初始化信号线和多条所述第二初始化信号线连接。
在一些实施例中，所述显示基板还包括层叠设置的两层源漏金属层。所述第三初始化信号总线与多条第一初始化信号线位于不同的源漏金属层；所述多条第一初始化信号线和多条第二初始化信号线位于不同的源漏金属层。
在一些实施例中，所述显示基板还包括多个发光器件、第一电压信号总线和沿所述第二方向延伸的多条第一电压信号线。第一电压信号总线设置于所述第三边框区；位于所述第三初始化信号总线在第二方向上的一侧；所述第一电压信号总线与所述发光器件的阴极连接；第一电压信号线至少设置于所述显示区，且延伸至所述第三边框区，所述多条第一电压信号线和所述第一电压信号总线连接；在所述第三边框区，所述多条第一初始化信号线和多条第一电压信号线沿第一方向交替设置。
在一些实施例中，所述显示基板还包括层叠设置的两层源漏金属层。所述第一电压信号总线和所述第三初始化信号总线位于同一所述源漏金属层；所述第一电压信号总线和多条所述第一电压信号线位于不同所述源漏金属层。
在一些实施例中，显示基板还包括多个像素电路、参考电压信号总线和沿所述第二方向延伸的多条参考电压信号线。所述像素电路包括驱动晶体管、写入晶体管和第一复位晶体管，所述驱动晶体管和所述写入晶体管、第一复位晶体管电连接于第一节点，第一复位晶体管被配置为将参考电压信号传输至第一节点；参考电压信号总线设置于第三边框区，且位于第三初始化信号总线沿第二方向的一侧；所述参考电压信号总线被配置为传输参考电压信号；多条参考电压信号线至少设置于所述显示区，且延伸至所述第三边框区，所述多条参考电压信号线和所述参考电压信号总线连接；在所述第三边框区，多条所述第一初始化信号线和多条所述参考电压信号线沿所述第一方向交替设置。
在一些实施例中，所述显示基板还包括层叠设置的两层源漏金属层。所述参考电压信号总线和所述第三初始化信号总线位于同一所述源漏金属层；所述参考电压信号总线和多条所述参考电压信号线位于不同所述源漏金属层。
在一些实施例中，所述显示基板还包括至少一个第二绑定电极组和第四初始化信号总线。所述第二绑定电极组位于所述第四边框区，所述第二绑定电极组用于连接驱动芯片； 所述第四初始化信号总线位于所述第四边框区，所述第四初始化信号总线和所述第一初始化信号总线、所述第二初始化信号总线连接，且与所述第二绑定电极组连接；所述多条初始化信号线还与第四初始化信号总线连接。
在一些实施例中，所述显示基板还包括初始化信号第二连接线组。所述初始化信号第二连接线组包括多条初始化信号第二连接线，位于所述第四边框区，且位于所述第二绑定电极组和所述第四初始化信号总线之间，用于连接所述第二绑定电极组和所述第四初始化信号总线。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开的一些实施例的显示装置的结构图；
图2A为本公开的一些实施例所提供的像素驱动电路的等效电路图；
图2B为本公开的一些实施例所提供的像素驱动电路的时序信号控制图；
图3为根据本公开的一些实施例的显示基板的一种结构图；
图4为图3中的显示基板产生横纹的示意图；
图5为根据本公开的一些实施例的显示基板的另一种结构图；
图6为根据本公开的一些实施例的显示基板的又一种结构图；
图7为图5中区域B的局部结构图；
图8为根据本公开的一些实施例的显示基板的又一种结构图；
图9为根据本公开的一些实施例的显示基板的又一种结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示 例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的 区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
如图1所示，本公开的一些实施例提供了一种显示装置1000，显示装置1000可以为电视机、显示器、笔记本电脑、平板电脑、手机、导航仪等任何具有显示功能的产品或者部件。图1中以显示装置1000为手机为例进行示意。
示例性地，上述显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
示例性地，上述显示装置1000可以为电致发光显示装置或光致发光显示装置。在该显示装置为电致发光显示装置的情况下，电致发光显示装置可以为有机电致发光显示装置(Organic LightEmitting Diode，简称OLED)或量子点电致发光显示装置(Quantum Dot Light Emitting Diodes，简称QLED)。在该显示装置为光致发光显示装置的情况下，光致发光显示装置可以为量子点光致发光显示装置。
在一些实施例中，上述显示装置1000可以为低温多晶氧化物(low temperature polycrystalline oxide，LTPO)显示装置。其中，LTPO显示装置能够支持多种刷新率，例如从120赫兹(Hz)到1赫兹(Hz)。
在一些实施例中，上述显示装置1000包括显示基板100。
以下对上述显示基板100的结构进行详细说明。
如图3和图5所示，图3为一些实施例提供的显示基板100’的一种结构图，图5为本公开的一些实施例提供的显示基板100的一种结构图。显示基板100包括显示区AA以及围绕显示区AA的周边区AN。周边区AN包括第一边框区11、第二边框区12、第三边框区13和第四边框区14。第一边框区11和第二边框区12设置于显示区AA的沿第一方向X的两侧，第三边框区13和第四边框区14设置于显示区AA沿第二方向Y的两侧，第一方向X和第二方向Y交叉，示例性地，第一方向X和第二方向Y垂直。
需要说明的是，显示基板100的显示区AA用于显示图像。为了实现显示基板100的画面显示功能，在显示区AA设置有显示器件。
以下以显示基板100为OLED显示基板为例，对本公开的一些实施例进行示意性说 明，但是本公开的实施方式包括但不限于此，也可以考虑任何其它显示基板，只要应用相同的技术思想即可。
在一些实施例中，显示区AA内设置多个像素单元，每个像素单元包括至少三个子像素P。子像素P为显示区AA内的最小发光单元。
示例性地，多个像素单元排列成多行多列。
在一些示例中，多个子像素P发射相同颜色的光线，显示区AA还可以包括设置于多个子像素P的出光侧的彩膜层。
例如，多个子像素P均发射白光、红光、绿光或蓝光等颜色光，在这种情况下，子像素P发出的颜色光经过彩膜层后保持同色光射出，或转化为其他颜色光射出，从而在多个子像素P发射同色光时，显示区AA可以实现多色出光。
在另一些示例中，多个子像素P发射不同颜色的光线，比如，多个子像素P包括发射红色光线的红光子像素、发射绿色光线的绿光子像素和发射蓝色光线的蓝光子像素，从而实现显示区AA的多色出光。
需要说明的是，每个像素单元包括至少三个子像素P，即每个像素单元可以包括三个、四个或更多个子像素P，且每个像素单元包括的多个子像素P可以是一行，一列或一组子像素，一组子像素P可以是彼此相邻的多个子像素P，相邻的多个子像素P排成一行、排成一列、排成L型、排成矩形或排成菱形等。
同时，每个像素单元包括的多个子像素P的发光面积可以相同或不完全相同。以上仅作为示例性说明，不作为对本公开的限定，具体可以根据实际需要进行适应性设计。
在一些实施例中，子像素中包括像素驱动电路，如图2A所示，图2A为本公开的一些实施例提供的一种像素驱动电路的等效电路示意图。需要说明的是，图2A中以像素驱动电路为8T1C结构为例进行说明，但是本公开中像素驱动电路的结构并不局限于此，例如像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C或7T1C等结构。其中，T代表晶体管，位于T前面的数字表示为晶体管的个数，C代表电容器，位于C前面的数字表示为电容器的个数。
请继续参照图2A，像素驱动电路可以包括8个晶体管(晶体管T1～晶体管T8)和1个存储电容C。
像素驱动电路还可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。需要说明的是，在本公开实施例提供的像素驱动电路中，节点并非表示实际存在的部件，而是表示像素驱动电路的等效电路示意图中相关电连接的汇合点，也就是说，这些节点是由像素驱动电路的等效电路示意图中相关电连接的汇合点等效而成的节点。
其中，第一节点N1分别与驱动晶体管T3的栅极、存储电容C的第一极板和阈值补偿晶体管T2的源极连接，第二节点N2分别与驱动晶体管T3的源极、第一发光控制晶体 管T5的漏极、数据写入晶体管T4的漏极和第三复位晶体管T8的漏极连接，第三节点N3分别与第一复位晶体管T1的漏极、阈值补偿晶体管T2的源极、第二发光控制晶体管T6的源极和驱动晶体管T3的漏极连接，第四节点N4分别与第二发光控制晶体管T6的漏极、第二复位晶体管T7的漏极和发光器件D连接。
存储电容C的第二极板与第一电源电压线VDD电连接，存储电容C的第一极板与第一节点N1连接，即存储电容C的第一极板与驱动晶体管T3的栅极连接。
第一复位晶体管T1的源极被配置为与初始化信号线Vinit电连接以接收初始化信号，第一复位晶体管T1的漏极与驱动晶体管T3的漏极电连接，第一复位晶体管T1的栅极被配置为与第一复位控制信号线Preset1电连接以接收复位控制信号。
阈值补偿晶体管T2的源极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的漏极与驱动晶体管T3的漏极电连接，阈值补偿晶体管T2的栅极被配置为与第一扫描信号线Ngate电连接以接收补偿控制信号。
驱动晶体管T3的栅极与存储电容C的第一极板连接，驱动晶体管T3的源极与第二节点N2连接，动晶体管T3的漏极与第三节点N3连接。驱动晶体管T3根据其栅极与源极之间的电位差来确定在第二电压信号线VDD与第一电压信号线VSS之间流动的驱动电流的大小。
数据写入晶体管T4的漏极与驱动晶体管T3的源极电连接，数据写入晶体管T4的源极被配置为与数据信号线Data电连接以接收数据信号，数据写入晶体管T4的栅极被配置为与第二扫描信号线Pgate电连接以接收扫描信号。
第一发光控制晶体管T5的源极与第二电压信号线(VDD)91电连接，第一发光控制晶体管T5的漏极与驱动晶体管T3的源极电连接，第一发光控制晶体管T5的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号。
第二发光控制晶体管T6的源极与驱动晶体管T3的漏极电连接，第二发光控制晶体管T6的漏极与发光器件D的第一电极电连接，第二发光控制晶体管T6的栅极被配置为与发光控制信号线EM电连接以接收发光控制信号。
第二复位晶体管T7的源极被配置为与初始化信号线Vinit电连接以接收初始化信号，第二复位晶体管T7的漏极与发光器件D的第一电极电连接，第二复位晶体管T7的栅极被配置为与第二复位控制信号线Preset2电连接以接收复位控制信号。
第三复位晶体管T8的源极被配置为与参考电压信号线Vref电连接以接收参考电压信号，第三复位晶体管T8的漏极与驱动晶体管T3的源极电连接，第三复位晶体管T8的栅极被配置为与第二复位控制信号线Preset2连接以接收复位控制信号。
发光器件D的第二电极与第一电压信号线(VSS)62电连接。
其中，第一扫描信号线Ngate用于传输第一扫描信号，第二扫描信号线Pgate用于传 输第二扫描信号，第一复位控制信号线Preset1用于传输第一复位控制信号，第二复位控制信号线用于传输第二复位控制信号，第二电压信号线VDD用于传输第二电压信号，例如为高压直流信号，初始化信号线Vinit用于传输初始化信号，数据信号线Data用于传输数据信号，发光控制信号线EM用于传输发光控制信号，第一电压信号线VSS用于传输第一电压信号，例如为低压直流信号。
示例性地，晶体管T1～晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示基板100的工艺难度，提高产品的良率。例如，晶体管T1到晶体管T8可以包括P型晶体管和N型晶体管，其中晶体管T2为N型晶体管，其余晶体管为P型晶体管。
示例性地，晶体管T1到晶体管T8可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板100上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，利用两者的优势，可以对显示基板100的刷新频率进行切换，以实现低频驱动，有利于降低功耗，提高显示品质。
当显示基板100进行刷新频率切换时，通常存在多种调节方式。其中一种调节方式为，在基础刷新频率(即基频)的基础上，将刷新频率进行降低，一般可以将刷新频率进行整数倍降低。将刷新频率进行整数倍降低时，可以称为插帧法调频。在插帧法中，基础刷新频率的显示帧包括写入帧。在基础刷新频率基础上降低刷新频率后的显示帧包括写入帧和保持帧，写入帧和保持帧的时长相同。也就是说，通过在相邻写入帧之间插入保持帧，来降低显示基板100的刷新频率，通过改变相邻写入帧之间插入保持帧的数量，改变刷新频率的降低倍数。例如，基础刷新频率为120HZ，插入一个保持帧后刷新频率降低为60HZ，插入两个保持帧后刷新频率降低为40HZ，以此类推。两种不同刷新频率的切换，可以为基础刷新频率和由该基础刷新频率降频后的刷新频率之间的切换，也可以为基于同一个基础刷新频率降频后的两种刷新频率之间的切换。
例如，当显示基板100上的待显示内容(诸如视频)需要较高的刷新频率，例如120Hz的频率，即一秒钟刷新120次，每两次刷新之间(1s/120)完成所有行的像素的数据写入，将开始显示区AA内第一行的像素驱动电路的数据写入和完成最后一行像素驱动电路的数据写入之间的时长与一个显示帧的时长对应，因此在这种情况下1s包括120个显示帧。
又例如，当显示基板100上的待显示内容(诸如静止图像)不需要较高的刷新频率，只需要1Hz的刷新频率即可，即一秒钟仅更新1次显示数据。显示帧的时长相对于不同的 数据刷新频率是不变的，这样，在显示周期(例如1s)的第一个显示帧(称为写入帧)内完成了所有行的像素驱动电路的数据写入，在后续的显示帧(称为保持帧)中每个像素驱动电路仍根据其存储电容C上的电压，并根据发光控制信号EM而控制发光元件D进行发光。
再例如，如图2A和2B所示，图2B为本公开的一些实施例所提供的像素驱动电路的时序信号控制图。第二扫描信号线Pgate具有第一刷新频率；第二复位控制信号线Preset2具有第二刷新频率。
其中，第二刷新频率大于第一刷新频率。第一刷新频率可以为120Hz，第二刷新频率可以为360Hz。
可以理解的是，显示基板100的刷新频率与数据信号写入的频率一致，即显示基板100的刷新频率为第二扫描信号线Pgate的第一刷新频率。在每次第二扫描信号线Pgate刷新，有数据信号写入时，第二复位控制信号线Preset2也需要刷新，将初始化信号写入，对与发光器件D的第一电极进行复位，以避免上帧写入的数据信号对本帧写入的数据信号的影响，造成显示基板100发光均一性差。当第二扫描信号线Pgate的第一刷新频率和第二复位控制信号线Preset2的第二刷新频率相同时，若要切换显示基板100的刷新频率(例如降低刷新频率)，需要同时改变第二扫描信号线Pgate的第一刷新频率和第二复位控制信号线Preset2的第二刷新频率，即需要通过增加保持帧(即上述插帧法调频)，将基础刷新频率整数倍降低，例如当第一刷新频率可以为120Hz时，可以实现30Hz、40Hz或60Hz的刷新频率切换，以保证每次第二扫描信号线Pgate刷新，第二复位控制信号线Preset2也刷新。这样，造成对信号线的信号波形改动较大，同时，由于显示基板100的刷新频率降低，且第一刷新频率和第二刷新频率均降低，会出现屏幕闪烁的现象，影响显示效果。
将第二复位控制信号线Preset2的第二刷新频率设置为大于第二扫描信号线Pgate的第一刷新频率，例如设置为原来的三倍，为360Hz，可以支持更多的刷新频率切换且改善屏幕闪烁的现象。如图2B所示，第二复位控制信号线Preset2的第二刷新频率较大，即每个帧阶段，第二复位控制信号线传输的信号均具有工作电平，能够对发光器件D的第一电极进行复位，若要切换显示基板100的刷新频率(例如降低刷新频率)，只需改变第二扫描信号线Pgate的第一刷新频率，无需改变第二复位控制信号线Preset2的第二刷新频率，也能保证在每次第二扫描信号线Pgate刷新时，第二复位控制信号线Preset2也刷新，这样就简化了对信号线的时序信号的改动，同时，由于在每个帧阶段都会对发光器件D的第一电极进行复位，视觉上具有屏幕刷新的效果，这样就改善了由于显示基板100的刷新率降低带来的屏幕闪烁的问题。
在一些实施例中，第一扫描信号线Ngate具有第一刷新频率；第一复位控制信号线Preset1具有第二刷新频率。由于在第二扫描信号线Pgate刷新写入数据信号时，第一扫描信号线Ngate也需要刷新，将阈值补偿晶体管T2导通进行阈值补偿，在第二复位控制信 号线Preset2复位对第四节点N4复位时，第一复位控制信号线Preset1也进行刷新，对第三节点N3复位，因此第一扫描信号线Ngate和第一复位控制信号线Preset1的刷新频率的设置原理与第二扫描信号线Pgate和第二复位控制信号线Preset2的设置原理一致，此处不再赘述。以下结合图2A和图2B，对显示基板100进行刷新频率切换时像素驱动电路的工作原理进行说明。需要说明的是，图2B中的时序图针对的是不需要高刷新频率的情况(也称为低频显示)，而在需要高刷新频率的情况下，每个显示帧(例如，1s内120个显示帧)的驱动时序都与图2B所描述的写入帧的时序相同，在此不进行赘述。
在显示装置低频显示的场景下，以每相邻三个帧阶段为一组，一组中的第一帧阶段为写入帧阶段，负责显示信号写入并发光，第二帧阶段和第三帧阶段均为保持帧阶段，负责基于写入帧阶段所写入的显示信号进行发光，上述像素驱动电路的驱动过程分为写入帧阶段和保持帧阶段：
在写入帧阶段，一个写入帧阶段包括第一复位阶段t1、数据刷新及补偿阶段t2、第二复位阶段t3和第一发光阶段t4。其中，在第一复位阶段t1，阈值补偿晶体管T2在第一扫描信号的控制下导通，第一复位晶体管T1在第一复位控制信号的控制下导通，使得初始化信号写入到第一节点N1，进而对第一节点N1进行复位。
此时，驱动晶体管T3导通，写入晶体管T4、第一发光控制晶体管T5以及第二发光控制晶体管T6均处于断开的状态，且发光器件OLED不发光。
在数据刷新及补偿阶段t2，第一复位晶体管T1在第一复位控制信号的控制下断开，阈值补偿晶体管T2保持导通状态，写入晶体管T4在第二扫描信号的控制下导通，驱动晶体管T3维持第一复位阶段t1的导通状态，因此数据信号可以依次通过写入晶体管T4、驱动晶体管T3和阈值补偿晶体管T2传输至第一节点N1，使得第一节点N1的电压改变，直至第一节点N1的电压达到驱动晶体管T3的阈值电压与数据信号Data的电压之和，使得驱动晶体管T3断开。在数据刷新及补偿阶段t2，可以将驱动晶体管T3的阈值电压写入到第一节点N1，以此补偿驱动晶体管T3的阈值电压漂移，避免驱动晶体管产生的驱动信号发生变化，避免对发光器件D的发光强度所产生的影响。在该阶段，第一发光控制晶体管T5和第二发光控制晶体管T6在发光控制信号的控制下处于断开的状态。
在第二复位阶段t3，补偿晶体管T2在第一扫描信号的控制下断开，写入晶体管T4在第二扫描信号的控制下断开，第二复位晶体管T7和第三复位晶体管T8在第二复位控制信号的控制下导通，进而使得初始化信号写入第二节点N2和发光器件D的阳极，进而对第二节点N2和发光器件D(第四节点N4)的阳极进行复位。
在第一发光阶段t4，第二复位晶体管T7和第三复位晶体管T8在第二复位控制信号的控制下断开，第一发光控制晶体管T5和第二发光控制晶体管T6在发光控制信号的控制下导通，进而使得第一电压信号写入到驱动晶体管T3的第一极区，发光器件D的阳极电压 可以写入到驱动晶体管T3的第二极区，进而使得驱动晶体管T3导通，以此在第一电源电压线VDD与发光器件D之间形成通路，使得发光器件D发光。
在保持帧阶段，每个保持帧阶段包括第三复位阶段t5、第四复位阶段t6和发光阶段t7。在第三复位阶段t5，阈值补偿晶体管T2在第一扫描信号的控制下导通，第一复位晶体管T1在第一复位控制信号的控制下导通，使得初始化信号写入到第一节点N1，进而对第一节点N1进行复位。
在第四复位阶段t6，第二复位晶体管T7和第三复位晶体管T8在第二复位控制信号的控制下导通，进而使得初始化信号写入第二节点N2和D的阳极，进而对第二节点N2和发光器件D的阳极(第四节点N4)进行复位。
在第二发光阶段t7，第二复位晶体管T7和第三复位晶体管T8在第二复位控制信号的控制下断开，第一发光控制晶体管T5和第二发光控制晶体管T6在发光控制信号的控制下导通，进而使得第一电压信号写入到驱动晶体管T3的第一极区，发光器件D的阳极电压可以写入到驱动晶体管T3的第二极区，进而使得驱动晶体管T3导通，以此在第一电源电压线VDD与发光器件D之间形成通路，使得发光器件D发光。
由上述像素驱动电路的驱动过程可知，在各复位阶段，均由初始化信号线(Vinit)40传输的初始化信号对第一节点N1、第二节点N2、第三节点N3或第四节点N4进行复位，以改变上述节点的电位，从而将各像素驱动电路的相对应节点的电位拉高或拉低至统一电位，避免显示基板中的干扰源对各像素驱动电路的节点的电位的干扰，造成显示亮度不均一的情况。因此，初始化信号线的布线对所传输的初始化信号的准确性和均一性非常重要。
以下对上述初始化信号线(Vinit)40在显示基板100内的布线方式进行详细说明。
如图3所示，显示基板100’包括第一绑定电极组21、第一初始化信号总线31、第二初始化信号总线32和初始化信号线40。第一绑定电极组21位于第三边框区13，第一绑定电极组21用于连接驱动芯片10；第一初始化信号总线31设置于第一边框区11；第二初始化信号总线32设置于第二边框区12；多条初始化信号线40至少设置于显示区AA，且与第一初始化信号总线31和第二初始化信号总线32连接。
多条初始化信号线40通过第一初始化信号总线31和第二初始化信号总线32，从显示区AA的两侧引入初始化信号，由于初始化信号线上存在电阻，初始化信号传输过程中会产生压降，且初始化信号线的靠近第一边框区11或第二边框区12的位置的压降和远离第一边框区11或第二边框区12的位置的压降存在差异，这样会导致初始化信号线的不同位置传输的初始化信号不均一，提供给各子像素中像素驱动电路的初始化信号不一致，造成在第四节点N4复位时，该节点的电位偏低，从而对应子像素偏暗，影响显示效果。
尤其是当第二复位控制信号线Preset2的第二刷新频率较大时，例如360Hz。在显示基板100低灰阶显示时，N4节点的复位时间将减少，例如当第二刷新频率为360Hz时，N4 节点的复位时间为1/360s，这将导致显示基板100低灰阶显示时N4节点复位不充分，引起横纹等不良，即如图4所示，显示基板100的显示区AA出现多条(三条)带状横纹。
且在中等或较大尺寸的显示基板100中，由于显示基板100面积较大，显示基板100的显示区AA更加容易出现如图4所示的多条(三条)带状横纹。
基于此，如图5所示，本申请的一些实施例提供一种显示基板100。显示基板100包括至少一个第一绑定电极组21、第一初始化信号总线31、第二初始化信号总线32、第三初始化信号总线33和多条初始化信号线40。至少一个第一绑定电极组21位于第三边框区13，每个第一绑定电极组21用于连接一个驱动芯片10；第一初始化信号总线31设置于第一边框区11；第二初始化信号总线32设置于第二边框区12；第三初始化信号总线33设置于第三边框区13；第三初始化信号总线33与第一初始化信号总线31和第二初始化信号总线32连接，且与第一绑定电极组21连接；多条初始化信号线40至少设置于显示区AA，且与第一初始化信号总线31、第二初始化信号总线32和第三初始化信号总线33连接。
通过在第三边框区13设置第三初始化信号总线33，第三初始化信号总线33与第一初始化信号总线31和第二初始化信号总线32连接，且与绑定电极组21连接，多条初始化信号线40除了与第一初始化信号总线31和第二初始化信号总线32连接之外，还与第三初始化信号总线33连接。可以通过第一初始化信号总线31、第二初始化信号总线32和第三初始化信号总线33同时向初始化信号线40传输初始化信号，且初始化信号线40内远离第一初始化信号总线31和第二初始化信号总线32的部分可以通过第三初始化信号总线33接收初始化信号，可以减小多条初始化信号线40在显示区AA的中间位置和边缘位置的压降(IR Drop)差异，使得多个子像素所接收到的初始化信号趋于一致，避免显示基板100出现横纹等显示不良。
示例性地，驱动芯片10可以通过覆晶薄膜(Chip On Film，缩写COF)、覆晶玻璃(Chip On Glass，缩写COG)和覆晶柔性材料(Chip On Pi，缩写COP)等方式封装，并与第三边框区13绑定。例如，驱动芯片10可以通过覆晶薄膜(Chip On Film，缩写COF)封装，该显示基板100包括覆晶薄膜组件，该覆晶薄膜组件包括柔性线路板(Flexible Printed Circuit，缩写FPC)和绑定于该柔性线路板的驱动芯片10。
示例性地，显示基板100可以包括一个、两个、三个、四个或更多个第一绑定电极组21。例如，如图6所示，图6为本公开的一些实施例提供的显示基板100的另一种结构图。显示基板100可以包括四个第一绑定电极组21,每个第一绑定电极组21对应连接有一个驱动芯片10，即驱动芯片10也相应设置四个，四个第一绑定电极组21均可以设置在第三边框区13，且分别和第三初始化信号总线33连接并传输初始化信号，有利于进一步降低初始化信号线的压降(IR Drop)，提高显示基板100的显示效果。
在一些实施例中，显示基板100的第三边框区13包括非弯折区和弯折区，弯折区相 对非弯折区远离显示区AA，第三初始化信号总线33位于非弯折区，多个第一绑定电极组21位于弯折区，弯折区可以朝向显示基板100的非显示侧弯折，即弯折到显示基板100的背面，以减小显示基板100的边框，驱动芯片10设置于显示基板100的背面，驱动芯片10通过柔性线路板与第一绑定电极组21连接。
在一些实施例中，请继续参照图6，显示基板100还可以包括至少一个第二绑定电极组22和第四初始化信号总线34。第二绑定电极组22位于第四边框区14，用于连接驱动芯片10；第四初始化信号总线34也位于第四边框区14，第四初始化信号总线34分别与第一初始化信号总线31和第二初始化信号总线32连接，且与第二绑定电极组22连接；多条初始化信号线40还与第四初始化信号总线34连接。在显示基板100的非显示侧，第二绑定电极组22与第三边框区13内的驱动芯片10连接并传输初始化信号。
通过在第四边框区14设置第四初始化信号总线34，第四初始化信号总线34与第一初始化信号总线31和第二初始化信号总线32连接，即，第一初始化信号总线31、第二初始化信号总线32、第三初始化信号总线33和第四初始化信号总线34相互连接形成环状结构，且第四初始化信号总线34还与第二绑定电极组22连接用于传输初始化信号，多条初始化信号线40除了与第一初始化信号总线31、第二初始化信号总线32和第三初始化信号总线33连接之外，还与第四初始化信号总线34连接。可以通过第一初始化信号总线31、第二初始化信号总线32、第三初始化信号总线33和第四初始化信号总线34同时向初始化信号线40传输初始化信号，可以进一步减小初始化信号线40在显示区AA的中间位置和边缘位置的压降(IR Drop)差异，避免显示基板100出现横纹等显示不良，提高显示基板100的显示均一性。
示例性地，显示基板100可以包括一个、两个、三个、四个或更多个第二绑定电极组22。例如，请继续参照图6，显示基板100可以包括两个第二绑定电极组22,每个第二绑定电极组22对应连接有一个驱动芯片10，两个第二绑定电极组22均可以设置在第四边框区14，且分别和第四初始化信号总线34连接并传输初始化信号，有利于更进一步降低初始化信号线的压降(IR Drop)，提高显示基板100的显示效果。
在一些实施例中，显示基板100的第四边框区14包括非弯折区和弯折区，弯折区相对非弯折区远离显示区AA，第四初始化信号总线34位于非弯折区，多个第二绑定电极组22位于弯折区，弯折区可以朝向显示基板100的非显示侧弯折，即弯折到显示基板100的背面，以减小显示基板100的边框。驱动芯片10设置于显示基板100的背面，驱动芯片10通过设置在显示基板100的背面的柔性线路板与第二绑定电极组22连接。
示例性地，第一绑定电极组21和第二绑定电极组22可以连接同一个驱动芯片10。例如，在显示基板100的背面(即显示基板100的非显示侧)，第二绑定电极组22通过柔性线路板连接至与第一绑定电极组21连接的驱动芯片10。由于柔性线路板中的走线电阻远 小于显示基板100中的走线的电阻，因此，在显示基板100的第四边框区14设置第二绑定电极组22，并弯折到显示基板100的背面，将显示基板100的第三边框区13和第四边框区14通过柔性线路板连接，可以降低信号压降，进一步提升初始化信号在显示区AA的均一性，进而提升显示的均一性。
在一些实施例中，请继续参照图5和图6，显示基板100还包括至少一个初始化信号第一连接线组51；每个初始化信号第一连接线组51包括多条初始化信号第一连接线511，多条初始化信号第一连接线511位于第三边框区13，且位于第一绑定电极组21和第三初始化信号总线33之间，用于连接第一绑定电极组21和第三初始化信号总线33，并传输初始化信号。
通过设置多条初始化信号第一连接线511向第三初始化信号总线33输入初始化信号，可以减小初始化信号在第三初始化信号总线33上的压降(IR Drop)，有利于提高显示基板100的显示效果。
在一些示例中，如图5所示，多条初始化信号第一连接线511中的一条还与第一初始化信号总线的靠近第三边框区的一端连接，多条初始化信号第一连接线511中的另一条还与第二初始化信号总线靠近第三边框区的一端连接，初始化信号由第一绑定电极组21通过初始化信号第一连接线511传输至第一初始化信号总线和第二初始化信号总线，同时传输至第三初始化信号总线，实现第一绑定电极组和初始化信号总线之间的信号传输。
示例性地，每个初始化信号第一连接线组51内的初始化信号第一连接线511的数量可以设置为两条、三条、四条、五条、七条、八条或九条，只要保证足够的布线空间，及能够使得初始化信号第一连接线511不与显示基板100内其他金属走线发生短路风险，或者，多条初始化信号第一连接线511之间互相不交叠、互不影响即可，在此不作任何具体限定。
在一些实施例中，请继续参照图6，显示基板100还包括至少一个初始化信号第二连接线组52；每个初始化信号第二连接线组52包括多条初始化信号第二连接线512，多条初始化信号第二连接线512位于第四边框区14，且位于第二绑定电极组22和第四初始化信号总线34之间，用于连接第二绑定电极组22和第四初始化信号总线34，并传输初始化信号。
通过设置多条初始化信号第二连接线512向第四初始化信号总线34输入初始化信号，可以减小初始化信号在第四初始化信号总线34上的压降(IR Drop)，有利于提高显示基板100的显示效果。
示例性地，每个初始化信号第二连接线组52内的初始化信号第二连接线512的数量可以设置为两条、三条、四条、五条、七条、八条或九条，只要保证足够的布线空间，及能够使得初始化信号第二连接线512不与显示基板100内其他金属走线发生短路风险，或 者，多条初始化信号第二连接线512之间互相不交叠、互不影响即可，在此不作任何具体限定。
在一些实施例中，请继续参照图5和图6，初始化信号线40包括多条第一初始化信号线401和多条第二初始化信号线402。每条第一初始化信号线401沿第二方向Y延伸至第三边框区13，并与第三初始化信号总线33连接，多条第一初始化信号线401沿第一方向X依次排布；每条第二初始化信号线402沿所述第一方向X延伸至第一边框区11和第二边框区12，并分别与第一初始化信号总线31和第二初始化信号总线32连接，多条第二初始化信号线402沿第二方向Y依次排布；多条第一初始化信号线401和多条第二初始化信号线402连接使初始化信号线40形成网状结构。
通过将初始化信号线40设置为网状结构，第一初始化信号总线31、第二初始化信号总线32和第三初始化信号总线33提供的初始化信号经网状结构的初始化信号线40分散传输，可进一步降低初始化信号在传输路径上的压降、提升初始化信号的均一性，从而进一步提升显示均一性，避免显示基板产生横纹等显示不良。
示例性地，多条第一初始化信号线401和多条第二初始化信号线402可以同层或者异层设置。当多条第一初始化信号线401和多条第二初始化信号线402同层设置时，二者可以一体设置；当多条第一初始化信号线401和多条第二初始化信号线402异层设置时，二者可以通过打孔的方式电连接，或通过其他导电部转接，在此不作任何具体限定。
在一些实施例中，如图7和图8所示，图7为图5中区域B的局部结构图。显示基板100还包括第一电压信号总线61和多条第一电压信号线62。第一电压信号总线61设置于第三边框区13，且位于第三初始化信号总线33在第二方向Y上的一侧；第一电压信号总线61与发光器件的阴极连接，用于向发光器件传输电压信号。多条第一电压信号线62沿第二方向Y延伸，至少设置于显示区AA，且延伸至第三边框区13，多条第一电压信号线62和第一电压信号总线61连接。在第三边框区13，多条第一初始化信号线401和多条第一电压信号线62沿第一方向X交替设置。
上述“多条第一初始化信号线401和多条第一电压信号线62沿第一方向X交替设置”，包括每一条第一初始化信号线401和每一条第一电压信号线62沿第一方向X有规律地交替设置，在这种情况下，每条初始化信号线401和一列子像素P电连接，每条第一电压信号线62和一列子像素P电连接。
通过上述设置，可以避免多条第一初始化信号线401和多条第一电压信号线62在第三边框区13内交叠导致短路，且可以降低第三边框区13内布线难度。
在一些实施例中，请继续参照图7，显示基板100还包括参考电压信号总线71和多条参考电压信号线72。参考电压信号总线71设置于第三边框区13，且位于第三初始化信号总线33沿第二方向Y的一侧，参考电压信号总线71被配置为传输参考电压信号；多条参 考电压信号线72沿第二方向Y延伸，至少设置于显示区AA，且延伸至第三边框区13，多条参考电压信号线72和参考电压信号总线71连接；在第三边框区13，多条第一初始化信号线401和多条参考电压信号线72沿第一方向X交替设置。
上述“多条第一初始化信号线401和多条参考电压信号线72沿第一方向X交替设置”，可以是多条第一初始化信号线401和多条参考电压信号线72沿第一方向X有规律地交替设置，在这种情况下，每条初始化信号线401和一列子像素P电连接，每条参考电压信号线72和一列子像素P电连接。
通过上述设置，可以避免多条第一初始化信号线401和多条参考电压信号线72在第三边框区13内交叠导致短路，且可以降低第三边框区13内布线难度。
在一些实施例中，请继续参照图7，在第三边框区13，多条第一初始化信号线401、多条第一电压信号线62和多条参考电压信号线72沿第一方向X交替设置。通过上述设置，可以避免多条第一初始化信号线401、多条第一电压信号线62和多条参考电压信号线72在第三边框区13内交叠导致短路，且可以降低第三边框区13内布线难度。
上述“多条第一初始化信号线401、多条第一电压信号线62和多条参考电压信号线72沿第一方向X交替设置”，可以是多条第一初始化信号线401、多条第一电压信号线62和多条参考电压信号线72沿第一方向X有规律地交替设置，例如，一条第一初始化信号线401、一条第一电压信号线62和一条参考电压信号线72为一组沿第一方向X有规律地交替设置，有利于保持较好的布线重复性。
也可以是多条第一初始化信号线401、多条第一电压信号线62和多条参考电压信号线72沿第一方向X无规律地交替设置，例如，一个像素单元对应的信号线布线方式可以为一条第一初始化信号线401、一条第一电压信号线62和一条第一初始化信号线401，与上述像素单元相邻的另一个像素单元对应的信号线布线方式可以为一条第一初始化信号线401和两条参考电压信号线72。在一些实施例中，显示基板还包括沿第二方向Y延伸的多条数据信号线81和多条第二电压信号线91，多条数据信号线81和多条第二电压信号线91设置于显示区AA，且延伸至第三边框区13，如图7所示，多条数据信号线81和多条第二电压信号线91在第一方向X上交替设置，每条数据信号线81和一列子像素P电连接，每条第二电压信号线91和一列子像素P电连接。
在一些实施例中，如图7所示，在第三边框区13，多条第一初始化信号线401和多条数据信号线81沿第一方向X交替设置，可以避免多条第一初始化信号线401和多条数据信号线81在第三边框区13内交叠导致短路，且可以降低第三边框区13内布线难度。
在一些实施例中，如图7所示，在第三边框区13，多条第一初始化信号线401和多条第二电压信号线91沿第一方向X交替设置，可以避免多条第一初始化信号线401和多条第二电压信号线91在第三边框区13内交叠导致短路，且可以降低第三边框区13内布线 难度。
在一些实施例中，显示基板100可以包括层叠设置的多个金属层，上述第三初始化信号总线33、初始化信号第一连接线组51、多条第一初始化信号线401、第一电压信号总线61、多条第一电压信号线62、参考电压信号总线71与多条参考电压信号线72设置于上述多个金属层内。
示例性地，多个金属层可以与像素驱动电路中晶体管的的金属层同层制作。需要说明的是，“多个金属层与TFT中的金属层同层制作”是指，多个金属层与TFT中的金属层通过同一次构图工艺同时形成，“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。
示例性地，显示基板100可以为低温多晶氧化物(LTPO)基板。如图9所示，图9为本公开的一些实施例提供的显示基板100的一种结构图。显示基板100包括在衬底基板101上依次设置且相互绝缘的第一有源层(Poly)、第一栅金属层(Gate1)、第二栅金属层(Gate2)、第二有源层(图中未示出)、第三栅金属层(Gate3)、第一源漏金属层(SD1)、第一平坦层(PLN1)、第二源漏金属层(SD2)和第二平坦层(PLN2)。
示例性地，衬底基板101可以是柔性衬底基板，例如由聚乙烯醚邻苯二甲酸酯、多芳基化合物、聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚碳酸酯(PC)、环烯烃聚合物(COP)、醋酸丙酸纤维素(CAP)、聚醚砜(PES)、聚丙烯酸酯(PAR)、聚醚酰亚胺(PEI)、聚萘二甲酸乙二醇酯(PEN)、聚苯硫醚(PPS)、聚烯丙酯、三乙酸纤维素(TAC)等具有优良的耐热性和耐久性的塑料基板；也可以是刚性衬底基板，例如玻璃基板，在此不作任何具体限定。
示例性地，第一平坦层(PLN1)和第二平坦层(PLN2)的材料可以为聚丙烯酸树脂、聚环氧丙烯酸树脂、感光性聚酰亚胺树脂、聚酯丙烯酸酯、聚氨酯丙烯酸酯树脂、酚醛环氧压克力树脂等有机绝缘材料，在此不作任何具体限定。
示例性地，第一栅金属层(Gate1)、第二栅金属层(Gate2)、第三栅金属层(Gate3)、第一源漏金属层(SD1)和第二源漏金属层(SD2)等金属膜层的材料可以采用钼(Mo)、铝(Al)、钛(Ti)等适于干刻的材料。可选地，上述金属膜层可以为单层金属或叠层金属。例如，第一栅金属层(Gate1)、第二栅金属层(Gate2)和第三栅金属层(Gate3)为单层钼金属，第一源漏金属层(SD1)和第二源漏金属层(SD2)为钛金属层/铝金属层/钛金属层构成的三叠层。
在一些实施例中，请参照图6和图9，第三初始化信号总线33和初始化信号第一连接线组51位于第一源漏金属层(SD1)或第二源漏金属层(SD2)，即第三初始化信号总线33和初始化信号第一连接线组51同层设置，既可以同时设置在第一源漏金属层(SD1)，也可以同时设置在第二源漏金属层(SD2)。
在另一些实施例中，第三初始化信号总线33和初始化信号第一连接线组51中的一者位于第一源漏金属层(SD1)，另一者位于第二源漏金属层(SD2)，即第三初始化信号总线33和初始化信号第一连接线组51异层设置，当第三初始化信号总线33设置在第一源漏金属层(SD1)时，初始化信号第一连接线组51设置于第二源漏金属层(SD2)；当第三初始化信号总线33设置在第二源漏金属层(SD2)时，初始化信号第一连接线组51设置于第一源漏金属层(SD1)。
在一些实施例中，第三初始化信号总线33与多条第一初始化信号线401中的一者位于第一源漏金属层(SD1)，另一者位于第二源漏金属层(SD2)，即第三初始化信号总线33和第一初始化信号线401异层设置，当第三初始化信号总线33设置在第一源漏金属层(SD1)时，第一初始化信号线401设置于第二源漏金属层(SD2)；当第三初始化信号总线33设置在第二源漏金属层(SD2)时，第一初始化信号线401设置于第一源漏金属层(SD1)。
在一些实施例中，多条第一初始化信号线401与多条第二初始化信号线402中的一者位于第一源漏金属层(SD1)，另一者位于第二源漏金属层(SD2)，即第一初始化信号线401和第二初始化信号线402可以异层设置，当第一初始化信号线401设置在第一源漏金属层(SD1)时，第二初始化信号线402设置于第二源漏金属层(SD2)；当第一初始化信号线401设置在第二源漏金属层(SD2)时，第二初始化信号线402设置于第一源漏金属层(SD1)。当第一初始化信号线401或第二初始化信号线402设置在第二源漏金属层(SD2)时，可以减小与下层金属层(例如第一栅金属层、第二栅金属层或第三栅金属层)上设置的信号线在交叠位置的电容，有利于进一步减小第一初始化信号线401或第二初始化信号线402的压降，并进一步提高显示均一性。
在一些实施例中，请继续参照图7，第三初始化信号总线33和第一电压信号总线61可以位于第一源漏金属层(SD1)或第二源漏金属层(SD2)，即第三初始化信号总线33和第一电压信号总线61同层设置，既可以同时设置在第一源漏金属层(SD1)，也可以同时设置在第二源漏金属层(SD2)。
在一些实施例中，请继续参照图7，第一电压信号总线61与多条第一电压信号线62中的一者位于第一源漏金属层(SD1)，另一者位于第二源漏金属层(SD2)，即第一电压信号总线61和第一电压信号线62可以异层设置，当第一电压信号总线61设置在第一源漏金属层(SD1)时，第一电压信号线62设置于第二源漏金属层(SD2)；当第一电压信号总线61设置在第二源漏金属层(SD2)时，第一电压信号线62设置于第一源漏金属层(SD1)。
在一些实施例中，请继续参照图7，第三初始化信号总线33和参考电压信号总线71可以位于第一源漏金属层(SD1)或第二源漏金属层(SD2)，即第三初始化信号总线33和参考电压信号总线71同层设置，既可以同时设置在第一源漏金属层(SD1)，也可以同时设置在第二源漏金属层(SD2)。
在一些实施例中，请继续参照图7，参考电压信号总线71与多条参考电压信号线72中的一者位于第一源漏金属层(SD1)，另一者位于第二源漏金属层(SD2)，即参考电压信号总线71和参考电压信号线72可以异层设置，当参考电压信号总线71设置在第一源漏金属层(SD1)时，参考电压信号线72设置于第二源漏金属层(SD2)；当参考电压信号总线71设置在第二源漏金属层(SD2)时，参考电压信号线72设置于第一源漏金属层(SD1)。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种显示基板，包括：显示区以及围绕所述显示区的周边区；
    所述周边区包括第一边框区、第二边框区、第三边框区和第四边框区，所述第一边框区和所述第二边框区设置于所述显示区的沿第一方向的两侧，所述第三边框区和所述第四边框区设置于所述显示区沿第二方向的两侧，所述第一方向和所述第二方向交叉；
    所述显示基板还包括：
    至少一个第一绑定电极组，位于所述第三边框区，每个所述第一绑定电极组用于连接一个驱动芯片；
    第一初始化信号总线，设置于所述第一边框区；
    第二初始化信号总线，设置于所述第二边框区；
    第三初始化信号总线，设置于所述第三边框区；所述第三初始化信号总线和所述第一初始化信号总线、所述第二初始化信号总线连接，且与所述第一绑定电极组连接；
    多条初始化信号线，至少设置于所述显示区，且与所述第一初始化信号总线、所述第二初始化信号总线和所述第三初始化信号总线连接。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括数据写入晶体管、第二复位晶体管、第二扫描信号线和第二复位控制信号线；
    所述数据写入晶体管的栅极和所述第二扫描信号线电连接；
    所述第二复位晶体管的栅极和所述第二复位控制信号线电连接；
    其中，所述第二扫描信号线具有第一刷新频率，所述第二复位控制信号线具有第二刷新频率，所述第二刷新频率大于所述第一刷新频率。
  3. 根据权利要求1或2所述的显示基板，其中，所述显示基板还包括至少一个初始化信号第一连接线组；
    每个所述初始化信号第一连接线组包括多条初始化信号第一连接线，多条所述初始化信号第一连接线位于第三边框区，且位于所述第一绑定电极组和所述第三初始化信号总线之间，用于连接所述第一绑定电极组和所述第三初始化信号总线。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板还包括层叠设置的第一源漏金属层和第二源漏金属层；
    所述第三初始化信号总线和所述初始化信号第一连接线组位于第一源漏金属层或第二源漏金属层；
    或者，所述第三初始化信号总线和所述初始化信号第一连接线组中的一者位于第一源漏金属层，另一者位于第二源漏金属层。
  5. 根据权利要求1～4中任一项所述的显示基板，其中，所述多条初始化信号线包括：
    沿所述第二方向延伸的多条第一初始化信号线，所述多条第一初始化信号线延伸至第三边框区，且和所述第三初始化信号总线连接，
    沿所述第一方向延伸的多条第二初始化信号线，所述多条第二初始化信号线延伸至所述第一边框区和所述第二边框区，且分别与所述第一初始化信号总线和所述第二初始化信号总线连接；
    多条所述第一初始化信号线和多条所述第二初始化信号线连接。
  6. 根据权利要求5所述的显示基板，其中，所述显示基板还包括层叠设置的两层源漏金属层；
    所述第三初始化信号总线与多条第一初始化信号线位于不同的源漏金属层；
    所述多条第一初始化信号线和多条第二初始化信号线位于不同的源漏金属层。
  7. 根据权利要求5～6中任一项所述的显示基板，其中，所述显示基板还包括：
    多个发光器件：
    第一电压信号总线，设置于所述第三边框区；位于所述第三初始化信号总线在第二方向上的一侧；所述第一电压信号总线与所述发光器件的阴极连接；
    沿所述第二方向延伸的多条第一电压信号线，至少设置于所述显示区，且延伸至所述第三边框区，所述多条第一电压信号线和所述第一电压信号总线连接；
    在所述第三边框区，所述多条第一初始化信号线和多条第一电压信号线沿第一方向交替设置。
  8. 根据权利要求7所述的显示基板，其中，所述显示基板还包括层叠设置的两层源漏金属层；
    所述第一电压信号总线和所述第三初始化信号总线位于同一所述源漏金属层；
    所述第一电压信号总线和多条所述第一电压信号线位于不同所述源漏金属层。
  9. 根据权利要求5～6中任一项所述的显示基板，其中，显示基板还包括：
    多个像素电路，所述像素电路包括驱动晶体管、写入晶体管和第一复位晶体管，所述驱动晶体管和所述写入晶体管、第一复位晶体管电连接于第一节点，第一复位晶体管被配 置为将参考电压信号传输至第一节点；
    参考电压信号总线，设置于第三边框区，且位于第三初始化信号总线沿第二方向的一侧；所述参考电压信号总线被配置为传输参考电压信号；
    沿所述第二方向延伸的多条参考电压信号线，至少设置于所述显示区，且延伸至所述第三边框区，所述多条参考电压信号线和所述参考电压信号总线连接；
    在所述第三边框区，多条所述第一初始化信号线和多条所述参考电压信号线沿所述第一方向交替设置。
  10. 根据权利要求9所述的显示基板，其中，所述显示基板还包括层叠设置的两层源漏金属层；
    所述参考电压信号总线和所述第三初始化信号总线位于同一所述源漏金属层；
    所述参考电压信号总线和多条所述参考电压信号线位于不同所述源漏金属层。
  11. 根据权利要求1～10中任一项所述的显示基板，其中，所述显示基板还包括：
    至少一个第二绑定电极组，位于所述第四边框区，所述第二绑定电极组用于连接所述驱动芯片；
    第四初始化信号总线，位于所述第四边框区，所述第四初始化信号总线和所述第一初始化信号总线、所述第二初始化信号总线连接，且与所述第二绑定电极组连接；
    所述多条初始化信号线还与第四初始化信号总线连接。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板还包括初始化信号第二连接线组；
    所述初始化信号第二连接线组包括多条初始化信号第二连接线，位于所述第四边框区，且位于所述第二绑定电极组和所述第四初始化信号总线之间，用于连接所述第二绑定电极组和所述第四初始化信号总线。
  13. 一种显示装置，包括：
    上述权利要求1～12中任一项所述的显示基板；
    至少一个驱动芯片，与所述至少一个第一绑定电极组分别连接。
PCT/CN2024/126205 2023-11-27 2024-10-21 显示基板及显示装置 Pending WO2025112982A1 (zh)

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