WO2025112976A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2025112976A1
WO2025112976A1 PCT/CN2024/126135 CN2024126135W WO2025112976A1 WO 2025112976 A1 WO2025112976 A1 WO 2025112976A1 CN 2024126135 W CN2024126135 W CN 2024126135W WO 2025112976 A1 WO2025112976 A1 WO 2025112976A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
isolation
display panel
area
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/126135
Other languages
English (en)
French (fr)
Inventor
程羽雕
嵇凤丽
秦成杰
张顺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025112976A1 publication Critical patent/WO2025112976A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device.
  • Display devices are widely used in people's daily life, such as mobile phones, monitors, tablet computers, etc. Display panels are an important part of display devices.
  • the display panel includes a base substrate and a plurality of isolation columns.
  • the base substrate has an opening area, an isolation area and a display area, the display area surrounds the opening area, and the isolation area is located between the opening area and the display area.
  • a plurality of isolation columns are located in the isolation area and on the first surface of the base substrate, and the plurality of isolation columns are annular and surround the opening area.
  • the isolation columns are used to divide the film layer (e.g., the light-emitting layer) located on the side of the isolation columns away from the first surface, thereby preventing external water and oxygen from extending from the edge of the opening area along the light-emitting material to the display area.
  • the isolation column usually adopts a metal structure and is in a floating state without power supply for a long time.
  • the metal structure is easy to react with external water and oxygen under electrochemical action, and the metal structure loses electrons and is oxidized, resulting in electrochemical corrosion. Electrochemical corrosion can cause defects such as perforation and local damage in the metal structure, resulting in packaging failure and affecting the reliability of the display panel.
  • the embodiments of the present disclosure provide a display panel and a manufacturing method thereof, and a display device, which can reduce the electrochemical corrosion of the isolation column of the metal structure.
  • the technical solution is as follows:
  • a display panel comprising a substrate, a light-emitting functional layer and a plurality of isolation columns; the substrate has a display area, an isolation area and an opening area, the display area surrounds the opening area, and the isolation area is located between the display area and the opening area; the light-emitting functional layer is located on the substrate
  • the first surface of the device, the light-emitting functional layer includes a plurality of light-emitting units, the plurality of light-emitting units are arrayed in the display area, and the light-emitting unit includes a first electrode; the plurality of isolation columns are located in the isolation area and on the first surface, the isolation columns are annular and surround the opening area, the isolation columns are metal structures, the isolation columns are insulated from the first electrode, and at least one of the isolation columns is electrically connected to a negative voltage signal source.
  • the display panel also includes a driving circuit layer and a first connecting line, the driving circuit layer is located between the light-emitting functional layer and the base substrate, the first connecting line is electrically connected to the negative voltage signal source and the isolation column respectively, and the first connecting line is in the same layer as at least one conductive layer in the driving circuit layer.
  • the driving circuit layer includes a bottom shading layer, a first gate layer and a second gate layer located sequentially on the first surface in a direction away from the first surface; the at least one conductive layer includes at least one of the bottom shading layer, the first gate layer and the second gate layer.
  • the multiple isolation columns include at least one first isolation column and at least one second isolation column, the first isolation column surrounds the second isolation column, the first isolation column is electrically connected to the first connection line, or the second isolation column is electrically connected to the first connection line; the second isolation column is electrically connected to the first isolation column through the second connection line.
  • the second connecting line is in the same layer as the first electrode.
  • the second connecting line is in the same layer as at least one of the bottom light shielding layer, the first gate layer and the second gate layer.
  • the display panel also includes a first metal ring, which is located between the base substrate and the first isolation column, the orthographic projection of the first isolation column on the base substrate is located within the orthographic projection of the first metal ring on the base substrate, the first metal ring is on the same layer as and connected to the second connecting line, the first isolation column is connected to the first metal ring through a via, and the first connecting line is connected to the first metal ring.
  • a first metal ring which is located between the base substrate and the first isolation column
  • the orthographic projection of the first isolation column on the base substrate is located within the orthographic projection of the first metal ring on the base substrate
  • the first metal ring is on the same layer as and connected to the second connecting line
  • the first isolation column is connected to the first metal ring through a via
  • the first connecting line is connected to the first metal ring.
  • the display panel further comprises a second metal ring and a third metal ring which are sequentially located on the first surface in a direction away from the first surface, the second metal ring is located between the base substrate and the second isolation column, the third metal ring is located between the second metal ring and the second isolation column, the orthographic projection of the second isolation column on the base substrate is located within the orthographic projection of the third metal ring on the base substrate, and the orthographic projection of the third metal ring on the base substrate is located at the orthographic projection of the second metal ring on the base substrate; the side wall of the second isolation column has an extension portion, the extension portion The second isolation column is connected to the second metal ring through a via, and the second metal ring is in the same layer and connected to the second connecting line; or the second isolation column is connected to the third metal ring through a via, and the third metal ring is in the same layer and connected to the second connecting line.
  • the negative voltage signal source is used to provide an initialization signal or a light emitting control signal for the driving circuit layer.
  • the isolation column includes a first sublayer, a second sublayer and a third sublayer stacked in sequence along a direction away from the first surface, and the side wall of the second sublayer away from the opening area is recessed toward the opening area; and/or the side wall of the second sublayer close to the opening area is recessed toward the direction away from the opening area.
  • the isolation column closest to the display area also includes an insulating part, which is located in a groove structure formed by the side wall of the second sub-layer away from the opening area and recessed toward the opening area, and the insulating part is respectively connected to the first sub-layer, the second sub-layer and the third sub-layer.
  • the display panel further includes an encapsulation layer, and the encapsulation layer is located on a side of the light-emitting functional layer away from the first surface.
  • the display panel further includes an isolation dam, the isolation dam is located in the isolation area, the isolation dam is located on the first surface, and the height of the isolation dam is greater than the height of the isolation column.
  • a method for manufacturing a display panel comprising: providing a base substrate, the base substrate having a display area, an isolation area and an opening area, the display area surrounding the opening area, and the isolation area being located between the display area and the opening area; forming a light-emitting functional layer on the first surface of the base substrate, the light-emitting functional layer comprising a plurality of light-emitting units, the plurality of light-emitting units being arranged in an array in the display area, the light-emitting units comprising a first electrode; forming a plurality of isolation columns in the isolation area and on the first surface, the isolation columns being annular and surrounding the opening area, the isolation columns being a metal structure, the isolation columns being insulated from the first electrode and at least one of the isolation columns being electrically connected to a negative voltage signal source.
  • a display device comprising a power supply circuit and any one of the above-mentioned display panels, wherein the power supply circuit supplies power to the display panel.
  • the isolation column is a metal structure.
  • the isolation column By isolating the isolation column from the first electrode and electrically connecting it to the negative voltage signal source, the electrical signal on the first electrode will not be generated by the negative voltage electrical signal provided by the negative voltage signal source. Interference or conflict occurs, and the potential of the isolation column is negative.
  • the isolation column contacts with external water and oxygen, it is difficult for the isolation column to lose electrons and be oxidized, which can reduce the electrochemical corrosion degree of the isolation column of the metal structure and reduce the probability of packaging failure, thereby improving the reliability of the display panel.
  • FIG1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure
  • FIG2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure
  • FIG4 is a schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a cross-sectional structure of another display panel provided in an embodiment of the present disclosure.
  • FIG7 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure.
  • FIG8 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure.
  • Isolation column 31 First isolation column 32. Second isolation column 33. Isolation dam 34. Groove 35. Extension 40. First connection line 41. Second connection line 50. First metal ring 51. Second metal ring 52. Third metal ring 60. Encapsulation layer 61. First inorganic encapsulation layer 62. Organic encapsulation layer 63. Second Inorganic Encapsulation Layer
  • Words such as "connect” or “connected” and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
  • "Up”, “down”, “left”, “right”, “top”, “bottom” and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
  • “A and/or B” means that there are three situations: A, B and A and B.
  • Fig. 1 is a schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure. As shown in Fig. 1 , the display panel has a display area 1, an isolation area 2 and an opening area 3, wherein the display area 1 surrounds the opening area 3 and the isolation area 2 is located between the display area 1 and the opening area 3.
  • the opening area 3 is used to place electronic devices, which may be camera modules, fingerprint modules or other modules that need to receive external light.
  • the display panel may further include a peripheral area (not shown), which surrounds the display area 1.
  • the peripheral area is used to arrange peripheral wiring, etc.
  • the peripheral wiring is used to control the display area 1 to display images.
  • the display panel may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc., which is not limited in the present disclosure.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the following description will take the display panel as an OLED display panel as an example.
  • FIG2 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present disclosure.
  • FIG2 may be a cross-sectional view of the display panel shown in FIG1 at line BB'.
  • the display panel includes a base substrate 101, a light-emitting functional layer 20, and a plurality of isolation columns 30.
  • the base substrate 101 has a display area 1, an isolation area 2, and an opening area 3 that are the same as those of the display panel in FIG1.
  • the light-emitting functional layer 20 is located on the first surface of the base substrate 101, and the light-emitting functional layer 20 includes a plurality of light-emitting units, and the plurality of light-emitting units are arranged in an array in the display area 1, and the light-emitting unit includes a first electrode 21.
  • a plurality of isolation columns 30 are located in the isolation area 2 and on the first surface, and the isolation columns 30 are annular and surround the opening area 3.
  • the isolation columns 30 are metal structures, and the isolation columns 30 are insulated from the first electrode 21, and at least one isolation column 30 is electrically connected to the negative voltage signal source.
  • the negative pressure signal source is used to provide a negative pressure electrical signal
  • the negative pressure electrical signal refers to an electrical signal less than 0 V.
  • the voltage range of the negative pressure electrical signal may be -11 V to -3 V.
  • the negative pressure electrical signal may be -7 V or -3 V.
  • the isolation column 30 is a metal structure. By insulating the isolation column 30 from the first electrode 21 and electrically connecting it to the negative voltage signal source, the electrical signal on the first electrode 21 will not interfere with or conflict with the negative voltage electrical signal provided by the negative voltage signal source, and the potential of the isolation column 30 is a negative potential.
  • the isolation column 30 comes into contact with external water and oxygen, it is difficult for the isolation column 30 to lose electrons and be oxidized, which can reduce the degree of electrochemical corrosion of the metal structure isolation column 30 and reduce the probability of packaging failure, thereby improving the reliability of the display panel.
  • the display panel further includes a driving circuit layer 10, which is located between the light-emitting functional layer 20 and the base substrate 101.
  • the driving circuit layer 10 includes a plurality of pixel driving circuits, each of which is connected to a light-emitting unit to control the light-emitting unit to emit light.
  • the negative voltage signal source is used to provide a negative voltage electrical signal to the pixel driving circuit corresponding to each light-emitting unit during the operation of the display panel.
  • the negative voltage signal source is used to provide an initialization signal or a light-emitting control signal to the driving circuit layer 10.
  • the initialization signal (Vinit) and the light control (EM) signal are in a negative voltage state most of the time.
  • the electrical connection between the negative voltage signal source and the isolation column 30 can effectively reduce the electrochemical corrosion of the isolation column 30 and reduce the probability of packaging failure, thereby improving the reliability of the display panel.
  • the voltage of the initialization signal may be -3V, and the voltage of the light emitting control signal may be at -7V for a long time.
  • the display panel further includes a first connection line 40, which is electrically connected to the negative voltage signal source and the isolation column 30 respectively, and the first connection line 40 is in the same layer as at least one conductive layer in the driving circuit layer 10.
  • the first connection line 40 can be used as an introduction end of the negative voltage signal source, thereby electrically connecting the isolation column 30 to the negative voltage signal source.
  • the first connection line 40 is in the same layer as at least one conductive layer in the driving circuit layer 10, so the first connection line 40 can be manufactured synchronously with other conductive layers in the driving circuit layer 10, which can simplify the process flow.
  • the driving circuit layer 10 includes a bottom light shielding layer 102, a first gate layer 106, and a second gate layer 108, which are sequentially located on the first surface in a direction away from the first surface.
  • the at least one conductive layer includes at least one of the bottom light shielding layer 102, the first gate layer 106, and the second gate layer 108.
  • the bottom light shielding layer 102 may also be referred to as a bottom shielding metal (BSM) layer.
  • the first connecting line 40 is in the same layer as at least one of these conductive layers, which facilitates the electrical connection of the negative voltage signal source to the isolation column 30 below the isolation column 30 .
  • the first connection line 40 is in the same layer as the bottom light shielding layer 102, the first gate layer 106 or the second gate layer 108.
  • the first connection line 40 is in the same layer as the second gate layer 108.
  • the first connection line 40 includes multiple parts, wherein a part of the first connection line 40 is in the same layer as the bottom light shielding layer 102, and another part of the first connection line 40 is in the same layer as the first gate layer 106.
  • the multiple parts of the first connection line 40 may also adopt other combinations of the same layers, and the present disclosure is not limited to this.
  • the plurality of isolation columns 30 include at least one first isolation column 31 and at least one second isolation column 32, and the first isolation column 31 surrounds the second isolation column 32.
  • the first isolation column 31 is also called an inner isolation column
  • the second isolation column 32 is also called an outer isolation column.
  • some of the plurality of isolation columns 30 are electrically connected to the negative pressure signal source. In other embodiments, all isolation columns 30 are connected to the negative pressure signal source.
  • FIG. 2 takes all isolation columns 30 as an example of being electrically connected to the negative pressure signal source, and the potential of all isolation columns 30 is set to The negative potential is beneficial to reducing the electrochemical corrosion degree of the isolation column 30 and improving the reliability of the display panel.
  • the first isolation column 31 is electrically connected to the first connection line 40 ; and the second isolation column 32 is electrically connected to the first isolation column 31 through the second connection line 41 .
  • the first connection line 40 can be electrically connected to the first isolation column 31 first, so that the negative pressure signal source is electrically connected to the first isolation column 31, and then the second isolation column 32 is electrically connected to the first isolation column 31 through the second connection line 41, so that the first isolation column 31 and the second isolation column 32 are both electrically connected to the negative pressure signal source.
  • the first isolation column 31 is far away from the hole area 3
  • the first isolation column 31, as the starting point for introducing the negative pressure signal in the plurality of isolation columns 30, can make the first connection line 40 farther away from the hole area 3, reducing the probability of the first connection line 40 being corroded by external water and oxygen.
  • the second isolation column 32 is electrically connected to the first connection line 40 ; the second isolation column 32 is electrically connected to the first isolation column 31 through the second connection line 41 .
  • the first connecting line 40 can be electrically connected to the second isolation column 32 first, so that the negative pressure signal source is electrically connected to the second isolation column 32, and then the second isolation column 32 is electrically connected to the first isolation column 31 through the second connecting line 41, so that the first isolation column 31 and the second isolation column 32 are both electrically connected to the negative pressure signal source.
  • the multiple first isolation columns 31 and multiple second isolation columns 32 are electrically connected through the second connection line 41
  • the multiple second isolation columns 32 are electrically connected through the second connection line 41 .
  • the second connection line 41 is in the same layer as the first electrode 21.
  • the first electrode 21 and the second connection line 41 can be manufactured simultaneously, thereby saving process costs.
  • the second connection line 41 is in the same layer as at least one of the bottom light shielding layer 102 , the first gate layer 106 and the second gate layer 108 . This facilitates the electrical connection of the second isolation column 32 with the first isolation column 31 through the second connection line 41 below the isolation column 30 .
  • the second connection line 41 is in the same layer as the first electrode 21, the bottom light shielding layer 102, the first gate layer 106 or the second gate layer 108.
  • the second connection line 41 may be in the same layer only as the first electrode 21. Since the first electrode 21 is generally manufactured by making a whole layer to cover the driving circuit layer 10 and the surface of the light-emitting functional layer 20 away from the first surface, the first electrode 21 and the second connection line 41 can be manufactured simultaneously without modifying the pattern formed after photolithography in the process of manufacturing the first electrode 21, thereby realizing electrical connection between all isolation columns 30 of the metal structure through the second connection line 41 in a whole layer above the isolation column 30.
  • the second connecting line 41 includes multiple parts, one of which is The second connection line 41 is in the same layer as the first electrode 21, another part of the second connection line 41 is in the same layer as the first gate layer 106, and another part of the second connection line 41 is in the same layer as the second gate layer 108.
  • multiple parts of the second connection line 41 can also adopt other combinations of the same layers, and the present disclosure does not limit this.
  • the second connection line includes two parts, one part of the second connection line 41 is in the same layer as the first electrode 21, and the other part of the second connection line 41 is in the same layer as the second gate layer 108.
  • the two parts of the second connection line are electrically connected to all the isolation pillars 30 respectively.
  • the display panel further includes a first metal ring 50, the first metal ring 50 is located between the base substrate 101 and the first isolation column 31, and the orthographic projection of the first isolation column 31 on the base substrate 101 is located within the orthographic projection of the first metal ring 50 on the base substrate 101.
  • the first metal ring 50 can increase the height of the first isolation column 31, which is beneficial for the first isolation column 31 to divide the luminescent material, thereby better blocking external water and oxygen from extending from the edge of the opening area 3 along the luminescent material to the display area 1.
  • the first metal ring 50 and the second connection line 41 are in the same layer and connected, the first isolation column 31 is connected to the first metal ring 50 through a via, and the first connection line 40 is connected to the first metal ring 50. This can save process costs and enable the first isolation column 31 to be electrically connected to the first metal ring 50 through the via.
  • the first metal ring 50 is not disposed under the first isolation column 31 , and the first isolation column 31 is directly connected to the first connection line 40 through a via.
  • the display panel also includes a second metal ring 51 and a third metal ring 52 which are sequentially located on the first surface in a direction away from the first surface, the second metal ring 51 is located between the base substrate 101 and the second isolation column 32, the third metal ring 52 is located between the second metal ring 51 and the second isolation column 32, the orthographic projection of the second isolation column 32 on the base substrate 101 is located within the orthographic projection of the third metal ring 52 on the base substrate 101, and the orthographic projection of the third metal ring 52 on the base substrate 101 is located within the orthographic projection of the second metal ring 51 on the base substrate 101.
  • the height of the second isolation column 32 near the opening area 3 can be made higher than the height of the first isolation column 31, so that the luminescent material can be better divided, thereby better preventing external water and oxygen from extending from the edge of the opening area 3 along the luminescent material to the display area 1.
  • the widths of the second metal ring 51, the third metal ring 52, and the second isolation column 32 decrease in sequence. After the encapsulation layer is subsequently covered on the second isolation column 32, the encapsulation layer can be deposited more smoothly, which is conducive to releasing external stress, reducing the probability of cracks in the encapsulation layer due to external stress, and further preventing water and oxygen from invading.
  • the second isolation column 32 is connected to the third metal ring 52 through a via hole, and the third metal ring 52 is in the same layer and connected to the second connection line 41.
  • the second connecting line 41 , the first metal ring 50 and the third metal ring 52 are all in the same layer as the second gate layer 108 , and the second metal ring 51 is in the same layer as the first gate layer 106 .
  • the isolation column 30 includes a first sublayer 301, a second sublayer 302 and a third sublayer 303 stacked in sequence along a direction away from the first surface, and the side wall of the second sublayer 302 away from the hole area 3 is recessed in the direction close to the opening area 3, and the side wall of the second sublayer 302 close to the opening area is recessed in the direction away from the hole area.
  • a spacer column 30 similar to an I-shaped structure can be formed, which is beneficial for naturally isolating the film layer above the spacer column 30 and simplifying the manufacturing process of the display panel.
  • only the side wall of the second sub-layer 302 away from the hole area 3 may be recessed toward the direction close to the hole area 3, or only the side wall of the second sub-layer 302 close to the hole area 3 may be recessed toward the direction away from the hole area 3.
  • Such a groove structure formed by the one-side inward recess can also isolate the film layer above the isolation column 30.
  • the isolation column 30 closest to the display area 1 also includes an insulating part 304, which is located in a groove structure formed by the side wall of the second sub-layer 302 away from the opening area 3 being recessed toward the opening area 3, and the insulating part 304 is respectively connected to the first sub-layer 301, the second sub-layer 302 and the third sub-layer 303.
  • the insulating portion 304 can cut off the electrical connection between the first electrode 21 of the display area 1 and the isolation column 30 , thereby preventing the electrical signal on the first electrode 30 from interfering with or conflicting with the negative voltage electrical signal provided by the negative voltage signal source.
  • the insulating portion 304 may be made of an organic insulating material or an inorganic insulating material, such as acrylic organic glue.
  • the groove structure may be a groove structure with a trapezoidal cross section or a groove structure with an arc-shaped interface.
  • the embodiment of the present disclosure does not limit the shape of the groove structure, as long as it can isolate the film layer above the isolation column 30.
  • the hierarchical structure of the display panel is exemplarily described below.
  • the substrate 101 and the driving circuit layer 10 form a driving backplane
  • the driving backplane can be a low-temperature polycrystalline silicon oxide (LTPO) backplane or a low-temperature polycrystalline silicon (LTPS) backplane.
  • LTPO low-temperature polycrystalline silicon oxide
  • LTPS low-temperature polycrystalline silicon
  • the driving circuit layer 10 includes a plurality of thin film transistors (TFT).
  • TFT thin film transistors
  • the multiple TFTs include low-temperature polysilicon TFTs and metal oxide TFTs.
  • the driving circuit layer also includes a buffer layer 103, a first active layer 104, a first gate insulating layer 105, a first insulating layer 107, a second gate insulating layer 109, a second active layer 110, a third gate insulating layer 111, a third gate layer 112, an interlayer dielectric layer 113, a first source and drain layer 114, a passivation layer 115, a first planarization layer 116, a second source and drain layer 117 and a second planarization layer 118.
  • the bottom light shielding layer 102, the buffer layer 103, the first active layer 104, the first gate insulating layer 105, the first gate layer 106, the first insulating layer 107, the second gate layer 108, the second gate insulating layer 109, the second active layer 110, the third gate insulating layer 111, the third gate layer 112, the interlayer dielectric layer 113, the first source and drain layer 114, the passivation layer 115, the first planarization layer 116, the second source and drain layer 117 and the second planarization layer 118 are stacked in sequence along the direction away from the first surface.
  • the driving circuit layer may further include an extraction electrode 119, which is in the same layer as the first source-drain electrode layer 114 and is connected to the bottom light shielding layer 102 through a via.
  • the extraction electrode 119 may be used to provide a negative voltage electrical signal with a constant voltage of -7V to the bottom light shielding layer 102, and the electrical signal is used to prevent leakage caused by TFT characteristic drift.
  • the light-emitting functional layer 20 may include a second electrode (not shown), a pixel definition layer 23, a light-emitting layer 22 and a first electrode 21 which are sequentially stacked in a direction away from the first surface.
  • the pixel definition layer 23 is a halftone pixel definition layer (HPDL)
  • the first electrode 21 is a cathode layer
  • the second electrode is an anode layer.
  • the base substrate 101 can be any transparent substrate, such as a glass substrate, a quartz substrate, a plastic substrate, other transparent hard substrates or other transparent flexible substrates, which can be a single layer or a multilayer structure.
  • the base substrate 101 includes a first PI (polyimide) layer, a first protective layer, a second PI layer, and a second protective layer stacked from bottom to top.
  • the two protective layers are used to protect the PI layer to prevent subsequent processes from damaging the PI layer.
  • the second protective layer is also covered with a buffer layer 103, which can block water oxygen and block alkaline ions.
  • the bottom light shielding layer 102 may be made of a metal material, including but not limited to molybdenum, aluminum, titanium, copper and the like.
  • the bottom light shielding layer 102 can reduce the light exposure to the TFT and can also conduct electricity.
  • the first active layer 104 is made of low-temperature polysilicon material
  • the second active layer 110 is made of metal oxide semiconductor materials such as indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the first gate insulating layer 105, the first insulating layer 107, the second gate insulating layer 109, The third gate insulating layer 111 and the interlayer dielectric layer 113 may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like.
  • the first gate layer 106 and the second gate layer 108 are made of metal materials, such as one or more of molybdenum, copper, and aluminum.
  • the third gate layer 112 includes a first sub-gate layer and a second sub-gate layer stacked.
  • the first sub-gate layer is made of a transparent conductive material, such as indium tin oxide (ITO).
  • the second sub-gate layer is made of a metal material, which can be a single metal layer or a plurality of metal layers stacked in sequence.
  • the metal material used in the metal layer in the second sub-gate layer can be titanium, aluminum, titanium, etc.
  • the passivation layer 115 may be made of a silicon oxide layer or a silicon nitride layer.
  • the first planarization layer 116 and the second planarization layer 118 are made of an organic insulating material, such as resin.
  • the material of the pixel definition layer 23 includes one or more of polyimide, polyphthalimide, polyphthalamide, silicon oxide, silicon nitride and the like.
  • the second electrode may be made of a metal material, such as gold, or the second electrode may be made of a transparent conductive material, such as ITO.
  • the light-emitting layer 22 may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), an electron blocking layer (EBL) and a light-emitting material layer.
  • HTL hole transport layer
  • HIL hole injection layer
  • ETL electron transport layer
  • EIL electron injection layer
  • HBL hole blocking layer
  • EBL electron blocking layer
  • EBL light-emitting material layer
  • the first electrode 21 is made of a metal material such as magnesium-silver alloy; or made of a transparent conductive material such as ITO.
  • the first source-drain electrode layer 114 may include a plurality of metal films including a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.
  • the second source-drain electrode layer 117 may include a plurality of metal films including a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.
  • the isolation column 30 may be in the same layer as the first source-drain electrode layer 114 or the second source-drain electrode layer 117. Accordingly, the first sublayer 301 and the third sublayer 303 may be titanium layers, and the second sublayer 302 may be an aluminum layer.
  • the display panel further includes an encapsulation layer 60, which is located on a side of the light-emitting functional layer 20 away from the first surface.
  • the encapsulation layer 60 can protect the light-emitting functional layer 20 below, block water and oxygen intrusion, and ensure the reliability of the display panel.
  • the encapsulation layer 60 may include a first inorganic encapsulation layer 61, an organic encapsulation layer 62, and a second inorganic encapsulation layer 63 stacked in sequence in a direction away from the first surface.
  • the encapsulation layer 60 may also include other more or fewer film layers, which is not limited in the present disclosure.
  • the first inorganic encapsulation layer 61 is made of silicon nitride, silicon oxide or silicon oxynitride.
  • the second inorganic encapsulation layer 63 is made of silicon nitride, silicon oxide or silicon oxynitride.
  • the organic encapsulation layer 62 is made of an organic insulating material, and here, the organic insulating material includes polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), phenolic resin and other materials.
  • the display panel further includes an isolation dam 33, the isolation dam 33 is located in the isolation area 2, and the isolation dam 33 is located on the first surface, and the height of the isolation dam 33 is greater than the height of the isolation column 30.
  • the isolation dam 33 can further prevent water and oxygen from entering the display area 1 and causing poor display, and can prevent the organic encapsulation layer 62 from overflowing into the opening area 3, thereby improving the reliability of the display panel.
  • the orthographic projection of the isolation dam 33 on the base substrate 101 is located between the orthographic projection of the first isolation column 31 on the base substrate 101 and the orthographic projection of the second isolation column 32 on the base substrate 101 .
  • the isolation dam 33 may be formed in the same layer as the pixel definition layer 23 .
  • the same layer means being formed by the same patterning process, or being in contact with the same surface of the same film layer, or being located on the same side of the same film layer, etc.
  • a groove 34 is formed in the interlayer dielectric layer 113 located in the isolation region 2 and on a side of the plurality of isolation pillars 30 close to the first surface.
  • FIG3 is a schematic diagram of a partial planar structure of a display panel provided by an embodiment of the present disclosure.
  • FIG3 may be a schematic diagram of a partial planar structure of the display panel shown in FIG1 at the dotted box C.
  • the orthographic projection of the groove 34 on the substrate substrate 101 is located between the orthographic projection of the isolation dam 33 on the substrate substrate 101 and the orthographic projection of the first isolation column 31 on the substrate substrate 101.
  • the groove 34 can make the height fluctuation between the isolation dam 34 and the first isolation column 31 larger.
  • first isolation columns 31 , adjacent first isolation columns 31 and second isolation columns 32 , and multiple second isolation columns 32 are electrically connected via second connecting lines 41 , so that the potential of all isolation columns 30 is negative, which is beneficial to improving the reliability of the display panel.
  • FIG4 is a schematic diagram of the cross-sectional structure of another display panel provided by an embodiment of the present disclosure.
  • the difference between the display panel shown in FIG4 and the display panel shown in FIG2 is that the connection method of the first connecting line 40 and the first metal ring 50 is different.
  • the first connecting line 40 is in the same layer as the bottom light shielding layer 102.
  • the first metal ring 50 is connected to the first connecting line 40 through a via. In this way, the potential of the isolation column 30 can be negatively connected to the negative voltage signal source through the lead-out electrode 119 on the bottom light shielding layer 102.
  • FIG5 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present disclosure.
  • the difference between the display panel shown in FIG5 and the display panel shown in FIG2 is that the first connecting line 40, the second connecting line 41 under the isolation column 30, the first metal ring 50 and the second metal ring 51 in FIG5 are all in the same layer as the first gate layer 106.
  • the side wall of the second isolation column 32 has an extension portion 35 , the extension portion 35 is connected to the second metal ring 51 through a via, and the second metal ring 51 is connected to the second connection line 41 .
  • the orthographic projection of the second isolation column 32 on the base substrate 101 is located within the orthographic projection of the third metal ring 52 on the base substrate 101
  • the orthographic projection of the third metal ring 52 on the base substrate 101 is located within the orthographic projection of the second metal ring 51 on the base substrate 101.
  • the second isolation column 32 can be connected to the second metal ring 51, and then the first isolation column 31 and the second isolation column 32 are electrically connected through the second connecting line 41.
  • FIG6 is a schematic diagram of a cross-sectional structure of another display panel provided by an embodiment of the present disclosure.
  • the difference between the display panel shown in FIG6 and the display panel shown in FIG5 is that the connection method of the first connecting line 40 and the first metal ring 50 is different.
  • the first connecting line 40 is in the same layer as the bottom light shielding layer 102.
  • the first metal ring 50 is connected to the first connecting line 40 through a via. In this way, a negative voltage signal source can be connected through the bottom light shielding layer 102 to make the potential of the isolation column 30 a negative potential.
  • FIG7 is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure. As shown in FIG7 , the manufacturing method includes:
  • step S701 a base substrate is provided.
  • the base substrate comprises a display area, an isolation area and an opening area, wherein the display area surrounds the opening area, and the isolation area is located between the display area and the opening area.
  • step S702 a light-emitting functional layer is formed on a first surface of the base substrate.
  • the light-emitting functional layer includes a plurality of light-emitting units, and the plurality of light-emitting units are arranged in an array in the display area.
  • the element includes a first electrode.
  • step S703 a plurality of isolation pillars are formed in the isolation region and on the first surface.
  • the isolation column is annular and surrounds the opening area.
  • the isolation column is a metal structure.
  • the isolation column is insulated from the first electrode and at least one isolation column is electrically connected to the negative pressure signal source.
  • the isolation column is a metal structure. By insulating the isolation column from the first electrode and electrically connecting it to the negative voltage signal source, the electrical signal on the first electrode will not interfere with or conflict with the negative voltage electrical signal provided by the negative voltage signal source, and the potential of the isolation column is a negative potential.
  • the isolation column comes into contact with external water and oxygen, it is difficult for the isolation column to lose electrons and be oxidized, which can reduce the degree of electrochemical corrosion of the isolation column of the metal structure and reduce the probability of packaging failure, thereby improving the reliability of the display panel.
  • FIG8 is a flow chart of another method for manufacturing a display panel provided in an embodiment of the present disclosure.
  • the manufacturing method is used to manufacture the display panel shown in FIG2 , as shown in FIG8 , and the manufacturing method includes:
  • step S801 a base substrate is provided.
  • step S802 a driving circuit layer is formed on a first surface of the base substrate.
  • step S802 may include:
  • a light-shielding metal layer is deposited on the substrate, and then a photoresist structure is obtained through processes such as photoresist coating, exposure, and development, and the light-shielding metal layer is etched using the photoresist structure as a mask to obtain a bottom light-shielding layer.
  • the second step is to form a buffer layer on the bottom light shielding layer, for example, by deposition.
  • a first active layer is formed on the buffer layer, for example, an initial first active layer can be deposited on the buffer layer, a photoresist structure is obtained by photoresist coating, exposure, development and other processes, and the initial first active layer is etched using the photoresist structure as a mask to form the first active layer.
  • an initial first gate insulating layer and an initial first gate layer are sequentially formed on the first active layer by, for example, deposition.
  • the initial first gate insulating layer covers the first active layer.
  • a photoresist structure is obtained on the initial first gate layer by processes such as photoresist coating, exposure, and development, and the initial first gate layer is etched using the photoresist structure as a mask to form a first gate pattern layer.
  • the first gate pattern layer includes a first gate layer located in the display area and a second metal ring located in the isolation area.
  • the portion of the first active layer not covered by the first gate layer is conductorized to ensure good ohmic contact between the first active layer and the first source and drain layer formed subsequently.
  • an initial first insulating layer and an initial second gate layer are sequentially formed on the first gate pattern layer by, for example, deposition.
  • the initial second gate layer is coated with photoresist, exposed, developed, and the like.
  • a photoresist structure is obtained, and the initial second gate layer is etched using the photoresist structure as a mask to form a second gate pattern layer.
  • the second gate pattern layer includes a second gate layer, a first connecting line, a second connecting line, a first metal ring and a third metal ring.
  • the fifth step is to form an initial second gate insulating layer and an initial second active layer on the second gate layer in sequence by, for example, deposition, and then obtain a photoresist structure through processes such as photoresist coating, exposure, and development, and etch the initial second active layer using the photoresist structure as a mask to obtain a second active layer.
  • an initial third gate insulating layer and an initial third gate layer are sequentially formed on the second active layer by, for example, deposition.
  • the initial third gate insulating layer covers the second active layer.
  • a photoresist structure is obtained on the initial third gate layer by processes such as photoresist coating, exposure, and development, and the initial third gate layer is etched using the photoresist structure as a mask to form a third gate layer.
  • the portion of the second active layer not covered by the third gate layer is conductorized to ensure good ohmic contact between the second active layer and the second source and drain layer formed subsequently.
  • an initial interlayer dielectric layer is formed on the third gate layer by, for example, deposition.
  • a series of processes such as photoresist coating, exposure, etching, and stripping, multiple vias are formed to expose the light shielding layer, and the first gate insulating layer is obtained from the initial first gate insulating layer; and then through a series of processes such as photoresist coating, exposure, etching, and stripping, multiple vias are formed to expose the first active layer, and the first insulating layer is obtained from the initial first insulating layer, and the second gate insulating layer is obtained from the initial second gate insulating layer.
  • an interlayer dielectric layer is obtained.
  • a first source-drain pattern layer is formed by a series of processes such as deposition, photoresist coating, exposure, etching, and stripping, wherein the first source-drain pattern layer includes a first source-drain layer and a lead-out electrode located in the display area, and a plurality of isolation columns located in the isolation area.
  • the isolation column includes a first sub-layer, a second sub-layer, and a third sub-layer stacked in sequence in a direction away from the first surface, and a side wall of the second sub-layer away from the opening area is recessed in a direction close to the opening area, and a side wall of the second sub-layer close to the opening area is recessed in a direction away from the opening area.
  • an initial passivation layer and an initial first planarization layer are formed on the first source and drain pattern layer by, for example, deposition.
  • a plurality of vias exposing the second active layer are formed by a series of processes such as photoresist coating, exposure, etching, and stripping, and at the same time, a third gate insulation layer is obtained from the initial third gate insulation layer, a passivation layer is obtained from the initial passivation layer, and a first planarization layer is obtained from the initial first planarization layer.
  • a second source and drain layer is formed in the via hole obtained by etching in the ninth step to expose the second active layer by adopting a series of processes such as deposition, photoresist coating, exposure, etching, and stripping.
  • a second planarization layer is formed on the second source and drain electrode layer by, for example, deposition.
  • step S803 an insulating portion is formed in the groove structure on a side of the isolation column closest to the display area and close to the display area.
  • step S804 a light-emitting functional layer is formed on a side of the driving circuit layer away from the first surface.
  • the light-emitting functional layer may include a plurality of light-emitting units, the plurality of light-emitting units are arrayed in the display area, and the first electrodes of the plurality of light-emitting units are connected.
  • the light-emitting functional layer includes a second electrode, a pixel definition layer, a light-emitting layer and a first electrode which are sequentially stacked in a direction away from the first surface.
  • the pixel definition layer is HPDL
  • the first electrode layer is a cathode layer
  • the second electrode layer is an anode layer.
  • step S805 an encapsulation layer is formed on a side of the light-emitting functional layer away from the first surface.
  • each layer and the positional relationship of the orthographic projection of each layer on the substrate may refer to the relevant embodiment of FIG. 2 , and detailed description is omitted here.
  • the difference between the manufacturing method for manufacturing the display panel shown in FIGS. 4 to 6 and the manufacturing method in the embodiment of FIG. 8 is mainly that the first connecting line and the second connecting line are manufactured in different layers, that is, the patterns formed after photolithography in the steps of forming the bottom light shielding layer, forming the first gate layer or forming the second gate layer are different, and detailed description is omitted here.
  • Fig. 9 is a schematic diagram of the structure of a display device provided by an embodiment of the present disclosure. As shown in Fig. 9, the display device includes a power supply circuit 1001 and the aforementioned display panel 1000, and the power supply circuit 1001 supplies power to the display panel 1000.
  • the display device can be any product or component with a display function, such as a laptop computer, a mobile phone, a tablet computer, a television, a monitor, a wearable device, a digital photo frame, a navigator, etc.
  • a display function such as a laptop computer, a mobile phone, a tablet computer, a television, a monitor, a wearable device, a digital photo frame, a navigator, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本公开实施例提供了一种显示面板及其制作方法、显示装置，属于显示技术领域。该显示面板包括衬底基板、发光功能层和多个隔离柱；衬底基板具有显示区、隔离区和开孔区，显示区围绕开孔区，隔离区位于显示区和开孔区之间；发光功能层位于衬底基板的第一表面，发光功能层包括多个发光单元，多个发光单元阵列布置在显示区中，发光单元包括第一电极；多个隔离柱位于隔离区且位于第一表面，隔离柱呈环形且围绕开孔区，隔离柱为金属结构，隔离柱与第一电极绝缘且至少一个隔离柱与负压信号源电连接。本公开实施例能减轻金属结构的隔离柱的电化学腐蚀程度。

Description

显示面板及其制作方法、显示装置
本申请要求于2023年11月29日提交的申请号为202311612832.4、发明名称为“显示面板及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示面板及其制作方法、显示装置。
背景技术
显示装置广泛应用于人们的日常生活中，例如手机、显示器或者平板电脑等设备中。显示面板为显示装置的重要组成部分。
相关技术中，显示面板包括衬底基板和多个隔离柱。衬底基板具有开孔区、隔离区和显示区，显示区围绕开孔区，隔离区位于开孔区和显示区之间。多个隔离柱位于隔离区且位于衬底基板的第一表面，多个隔离柱均呈环形且围绕开孔区。隔离柱用于将位于隔离柱的远离第一表面的一侧的膜层(例如发光层)进行分割，从而阻挡外界水氧从开孔区边缘沿发光材料延伸至显示区。
然而，隔离柱通常采用金属结构，且长期处于未加载电源的浮空(Floating)状态，金属结构在电化学作用下容易与外界水氧反应，金属结构失去电子而被氧化，产生电化学腐蚀。电化学腐蚀会使金属结构产生穿孔和局部损坏等缺陷，从而导致封装失效，影响显示面板的可靠性。
发明内容
本公开实施例提供了一种显示面板及其制作方法、显示装置，能减轻金属结构的隔离柱的电化学腐蚀程度。所述技术方案如下：
一方面，提供了一种显示面板，包括衬底基板、发光功能层和多个隔离柱；所述衬底基板具有显示区、隔离区和开孔区，所述显示区围绕所述开孔区，所述隔离区位于所述显示区和所述开孔区之间；所述发光功能层位于所述衬底基板 的第一表面，所述发光功能层包括多个发光单元，所述多个发光单元阵列布置在所述显示区中，所述发光单元包括第一电极；所述多个隔离柱位于所述隔离区且位于所述第一表面，所述隔离柱呈环形且围绕所述开孔区，所述隔离柱为金属结构，所述隔离柱与所述第一电极绝缘且至少一个所述隔离柱与负压信号源电连接。
可选地，所述显示面板还包括驱动电路层和第一连接线，所述驱动电路层位于所述发光功能层和所述衬底基板之间，所述第一连接线分别与所述负压信号源和所述隔离柱电连接，且所述第一连接线与所述驱动电路层中的至少一层导电层同层。
可选地，所述驱动电路层包括沿远离所述第一表面的方向依次位于所述第一表面的底部遮光层、第一栅极层和第二栅极层；所述至少一层导电层包括所述底部遮光层、所述第一栅极层和所述第二栅极层中的至少一层。
可选地，所述多个隔离柱包括至少一个第一隔离柱和至少一个第二隔离柱，所述第一隔离柱环绕所述第二隔离柱，所述第一隔离柱与所述第一连接线电连接，或者所述第二隔离柱与所述第一连接线电连接；所述第二隔离柱通过第二连接线与所述第一隔离柱电连接。
可选地，所述第二连接线与所述第一电极同层。
可选地，所述第二连接线与所述底部遮光层、所述第一栅极层和所述第二栅极层中的至少一层同层。
可选地，所述显示面板还包括第一金属环，所述第一金属环位于所述衬底基板和所述第一隔离柱之间，所述第一隔离柱在所述衬底基板上的正投影位于所述第一金属环在所述衬底基板上的正投影内，所述第一金属环与所述第二连接线同层且连接，所述第一隔离柱通过过孔与所述第一金属环连接，所述第一连接线与所述第一金属环连接。
可选地，所述显示面板还包括沿远离所述第一表面的方向依次位于所述第一表面的第二金属环和第三金属环，所述第二金属环位于所述衬底基板和所述第二隔离柱之间，所述第三金属环位于所述第二金属环与所述第二隔离柱之间，所述第二隔离柱在所述衬底基板上的正投影位于所述第三金属环在所述衬底基板上的正投影内，所述第三金属环在所述衬底基板上的正投影位于所述第二金属环在所述衬底基板上的正投影；所述第二隔离柱的侧壁具有延伸部，所述延伸 部通过过孔与所述第二金属环连接，所述第二金属环与所述第二连接线同层且连接；或者，所述第二隔离柱通过过孔与所述第三金属环连接，所述第三金属环与所述第二连接线同层且连接。
可选地，所述负压信号源用于为所述驱动电路层提供初始化信号或者发光控制信号。
可选地，所述隔离柱包括沿远离所述第一表面的方向依次层叠的第一子层、第二子层和第三子层，所述第二子层的远离所述开孔区的侧壁向靠近所述开孔区的方向凹陷；和/或，所述第二子层的靠近所述开孔区的侧壁向远离所述开孔区的方向凹陷。
可选地，与所述显示区的距离最近的所述隔离柱还包括绝缘部，所述绝缘部位于所述第二子层的远离所述开孔区的侧壁向靠近所述开孔区的方向凹陷形成的凹槽结构中，且所述绝缘部分别与所述第一子层、所述第二子层和所述第三子层连接。
可选地，所述显示面板还包括封装层，所述封装层位于所述发光功能层的远离所述第一表面的一侧。
可选地，所述显示面板还包括隔离坝，所述隔离坝位于隔离区，且所述隔离坝位于所述第一表面，所述隔离坝的高度大于所述隔离柱的高度。
另一方面，提供了一种显示面板的制作方法，包括：提供一衬底基板，所述衬底基板具有显示区、隔离区和开孔区，所述显示区围绕所述开孔区，所述隔离区位于所述显示区和所述开孔区之间；在所述衬底基板的第一表面形成发光功能层，所述发光功能层包括多个发光单元，所述多个发光单元阵列布置在所述显示区中，所述发光单元包括第一电极；在所述隔离区且在所述第一表面形成多个隔离柱，所述隔离柱呈环形且围绕所述开孔区，所述隔离柱为金属结构，所述隔离柱与所述第一电极绝缘且至少一个所述隔离柱与负压信号源电连接。
又一方面，提供了一种显示装置，包括供电电路和前述任一种显示面板，所述供电电路为所述显示面板供电。
本公开实施例提供的技术方案带来的有益效果是：
本公开实施例中，隔离柱为金属结构，通过将隔离柱与第一电极绝缘且与负压信号源电连接，第一电极上的电信号不会与负压信号源提供的负压电信号产 生干扰或者冲突，且隔离柱的电位为负电位，当隔离柱与外界水氧接触时，隔离柱难以失去电子而被氧化，可以减轻金属结构的隔离柱的电化学腐蚀程度，减小封装失效的几率，从而提高显示面板的可靠性。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种显示面板的平面结构示意图；
图2是本公开实施例提供的一种显示面板的截面结构示意图；
图3是本公开实施例提供的一种显示面板的局部平面结构示意图；
图4是本公开实施例提供的另一种显示面板的截面结构示意图；
图5是本公开实施例提供的又一种显示面板的截面结构示意图；
图6是本公开实施例提供的又一种显示面板的截面结构示意图；
图7是本公开实施例提供的一种显示面板的制作方法流程图；
图8是本公开实施例提供的另一种显示面板的制作方法流程图；
图9是本公开实施例提供的一种显示装置的结构示意图。
图例说明：
1、显示区 2、隔离区 3、开孔区
10、驱动背板 101、衬底基板 102、底部遮光层 103、缓冲层
104、第一有源层 105、第一栅极绝缘层 106、第一栅极层
107、第一绝缘层 108、第二栅极层 109、第二栅极绝缘层
110、第二有源层 111、第三栅极绝缘层 112、第三栅极层
113、层间介电层 114、第一源漏极层 115、钝化层
116、第一平坦化层 117、第二源漏极层 118、第二平坦化层
119、引出电极
1000、显示面板 1001、供电电路
20、发光功能层 21、第一电极 22、发光层 23、像素定义层
30、隔离柱 31、第一隔离柱 32、第二隔离柱 33、隔离坝
34、凹槽 35、延伸部
40、第一连接线 41、第二连接线
50、第一金属环 51、第二金属环 52、第三金属环
60、封装层 61、第一无机封装层 62、有机封装层
63、第二无机封装层
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”、“顶”、“底”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。此外，“A和/或B”表示存在三种情况：A、B以及A和B。
图1是本公开实施例提供的一种显示面板的平面结构示意图。如图1所示，显示面板具有显示区1、隔离区2和开孔区3，显示区1围绕开孔区3，隔离区2位于显示区1和开孔区3之间。
开孔区3用于放置电子器件。电子器件可以是摄像模组、指纹模组或者其他需要接收外界光线的模组。
可选地，显示面板还可以包括周边区(图未示)，该周边区围绕显示区1。周边区用于布置外围走线等，外围走线用于控制显示区1显示画面。
可选地，显示面板可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等，本公开对此不做限制。下文中将以显示面板为OLED显示面板为例进行说明。
图2是本公开实施例提供的一种显示面板的截面结构示意图。图2可以是图1所示的显示面板在BB’线处的截面图。如图2所示，该显示面板包括衬底基板101、发光功能层20和多个隔离柱30。衬底基板101具有与图1中显示面板相同的显示区1、隔离区2和开孔区3。
其中，发光功能层20位于衬底基板101的第一表面，发光功能层20包括多个发光单元，多个发光单元阵列布置在显示区1中，发光单元包括第一电极21。多个隔离柱30位于隔离区2且位于第一表面，隔离柱30呈环形且围绕开孔区3，隔离柱30为金属结构，隔离柱30与第一电极21绝缘且至少一个隔离柱30与负压信号源电连接。
在本公开实施例中，负压信号源用于提供负压电信号，负压电信号是指小于0V的电信号。可选地，负压电信号的电压范围可以为-11V至-3V。示例性地，负压电信号可以为-7V或-3V。
本公开实施例中，隔离柱30为金属结构，通过将隔离柱30与第一电极21绝缘且与负压信号源电连接，第一电极21上的电信号不会与负压信号源提供的负压电信号产生干扰或者冲突，且隔离柱30的电位为负电位，当隔离柱30与外界水氧接触时，隔离柱30难以失去电子而被氧化，可以减轻金属结构的隔离柱30的电化学腐蚀程度，减小封装失效的几率，从而提高显示面板的可靠性。
如图2所示，显示面板还包括驱动电路层10，驱动电路层10位于发光功能层20和衬底基板101之间。驱动电路层10包括多个像素驱动电路，每个像素驱动电路与一个发光单元连接，用于控制所连接的发光单元发光。
在一种可能的实施方式中，负压信号源用于在显示面板的工作过程中为每个发光单元对应的像素驱动电路提供负压电信号。可选地，负压信号源用于为驱动电路层10提供初始化信号或者发光控制信号。
在显示面板的工作过程中，初始化信号(Vinit)和发光控制(EM)信号大部分时间处于负压状态，这样负压信号源与隔离柱30电连接可以有效减轻隔离柱30的电化学腐蚀程度，减小封装失效的几率，从而提高显示面板的可靠性。
示例性地，初始化信号的电压可以是-3V，发光控制信号的电压可以长时间处于-7V。
在另一种可能的实施方式中，负压信号源也可以是单独的信号源，仅用于为隔离柱30提供负压电信号。
为了将隔离柱30与负压信号源电连接，显示面板还包括第一连接线40，第一连接线40分别与负压信号源和隔离柱30电连接，且第一连接线40与驱动电路层10中的至少一层导电层同层。第一连接线40可以作为负压信号源的引入端，进而使得隔离柱30与负压信号源电连接。第一连接线40与驱动电路层10中的至少一层导电层同层，因此，第一连接线40可以与驱动电路层10中的其他导电层同步制作，可以简化工艺流程。
可选地，驱动电路层10包括沿远离第一表面的方向依次位于第一表面的底部遮光层102、第一栅极层106和第二栅极层108。至少一层导电层包括底部遮光层102、第一栅极层106和第二栅极层108中的至少一层。其中，底部遮光层102也可以称为底部遮挡金属(Bottom Shield Metal，BSM)层。
由于驱动电路层10中，底部遮光层102、第一栅极层106和第二栅极层108一般采用导电材料制作，因此第一连接线40与这些导电层中的至少一层同层，便于在隔离柱30下方将负压信号源与隔离柱30电连接。
在一种可能的实施方式中，第一连接线40与底部遮光层102、第一栅极层106或第二栅极层108同层。例如，如图2所示，第一连接线40与第二栅极层108同层。
在另一种可能的实施方式中，第一连接线40包括多个部分，其中一部分的第一连接线40与底部遮光层102同层，另一部分的第一连接线40与第一栅极层106同层。当然，第一连接线40的多个部分的也可以采用其他的同层组合，本公开对此不做限制。
可选地，多个隔离柱30包括至少一个第一隔离柱31和至少一个第二隔离柱32，第一隔离柱31环绕第二隔离柱32。第一隔离柱31又称内隔离柱，第二隔离柱32又称外隔离柱。
在一些实施例中，多个隔离柱30中的部分隔离柱30与负压信号源电连接。在另一些实施例中，所有隔离柱30均与负压信号源连接。图2以所有的隔离柱30均与负压信号源电连接作为示例，通过负压信号源使所有隔离柱30的电位为 负电位，有利于减轻隔离柱30的电化学腐蚀程度，提高显示面板的可靠性。
如图2所示，第一隔离柱31与第一连接线40电连接；第二隔离柱32通过第二连接线41与第一隔离柱31电连接。
也即是，第一连接线40可以先与第一隔离柱31电连接，以使负压信号源与第一隔离柱31电连接，然后第二隔离柱32通过第二连接线41与第一隔离柱31电连接，从而使第一隔离柱31和第二隔离柱32均与负压信号源电连接。这样，由于第一隔离柱31远离开孔区3，第一隔离柱31作为多个隔离柱30中负压信号的引入起点可以使第一连接线40离开孔区3的距离更远，减小了第一连接线40被外界水氧腐蚀的几率。
在其他实施例中，第二隔离柱32与第一连接线40电连接；第二隔离柱32通过第二连接线41与第一隔离柱31电连接。
也即是，第一连接线40可以先与第二隔离柱32电连接，以使负压信号源与第二隔离柱32电连接，然后第二隔离柱32通过第二连接线41与第一隔离柱31电连接，从而使第一隔离柱31和第二隔离柱32均与负压信号源电连接。
需要说明的是，当存在多个第一隔离柱31以及多个第二隔离柱32时，多个第一隔离柱31之间通过第二连接线41电连接，多个第二隔离柱32之间通过第二连接线41电连接。
可选地，第二连接线41与第一电极21同层。这样，可以同步制作第一电极21与第二连接线41从而节省工艺成本。
可选地，第二连接线41与底部遮光层102、第一栅极层106和第二栅极层108中的至少一层同层。这样便于在隔离柱30下方通过第二连接线41使第二隔离柱32与第一隔离柱31电连接。
在一种可能的实施方式中，第二连接线41与第一电极21、底部遮光层102、第一栅极层106或第二栅极层108同层。例如，第二连接线41可以仅与第一电极21同层，由于制作第一电极21时一般是做一整层来覆盖驱动电路层10以及发光功能层20的远离第一表面一侧的表面，这样无需修改制作第一电极21过程中光刻后形成的图案，即可同步制作出第一电极21和第二连接线41，从而通过在隔离柱30上方一整层的第二连接线41实现所有的金属结构的隔离柱30之间的电连接。
在另一种可能的实施方式中，第二连接线41包括多个部分，其中一部分的 第二连接线41与第一电极21同层，另一部分的第二连接线41与第一栅极层106同层，又一部分的第二连接线41与第二栅极层108同层。当然，第二连接线41的多个部分也可以采用其他的同层组合，本公开对此不做限制。
如图2所示，第二连接线包括两个部分，其中一部分的第二连接线41与第一电极21同层，另一部分的第二连接线41与第二栅极层108同层。第二连接线的两部分分别与所有隔离柱30电连接。
可选地，显示面板还包括第一金属环50，第一金属环50位于衬底基板101和第一隔离柱31之间，第一隔离柱31在衬底基板101上的正投影位于第一金属环50在衬底基板101上的正投影内。第一金属环50可以增加第一隔离柱31的高度，有利于第一隔离柱31对发光材料进行分割，从而更好地阻挡外界水氧从开孔区3边缘沿发光材料延伸至显示区1。
可选地，第一金属环50与第二连接线41同层且连接，第一隔离柱31通过过孔与第一金属环50连接，第一连接线40与第一金属环50连接。这样可以节省工艺成本且能通过过孔使第一隔离柱31与第一金属环50电连接。
在一些实施例中，第一隔离柱31下方没有布置第一金属环50，且第一隔离柱31直接通过过孔与第一连接线40连接。
可选地，显示面板还包括沿远离第一表面的方向依次位于第一表面的第二金属环51和第三金属环52，第二金属环51位于衬底基板101和第二隔离柱32之间，第三金属环52位于第二金属环51和第二隔离柱32之间，第二隔离柱32在衬底基板101上的正投影位于第三金属环52在衬底基板101上的正投影内，第三金属环52在衬底基板101上的正投影位于第二金属环51在衬底基板101上的正投影内。
这样，可以使靠近开孔区3的第二隔离柱32的高度高于第一隔离柱31的高度，可以更好地对发光材料进行分割，从而更好地阻挡外界水氧从开孔区3边缘沿发光材料延伸至显示区1。由下至上第二金属环51、第三金属环52和第二隔离柱32的宽度依次减小，后续在第二隔离柱32上覆盖封装层后可以使封装层沉积得更平滑，有利于释放外界应力，减小封装层受外界应力产生裂纹(Crack)的几率，进一步阻挡水氧侵入。
如图2所示，第二隔离柱32通过过孔与第三金属环52连接，第三金属环52与第二连接线41同层且连接。也即是，图2中第一连接线40、隔离柱30下 方的第二连接线41、第一金属环50和第三金属环52均与第二栅极层108同层，第二金属环51与第一栅极层106同层。
如图2所示，隔离柱30包括沿远离第一表面的方向依次层叠的第一子层301、第二子层302和第三子层303，第二子层302的远离开孔区3的侧壁向靠近开孔区3的方向凹陷，且第二子层302的靠近开孔区的侧壁向远离开孔区的方向凹陷。
这样，可以形成类似于工字型结构的隔离柱30，有利于自然隔断隔离柱30上方的膜层，简化显示面板的制作工艺。
在其他实施例中，也可以仅第二子层302的远离开孔区3的侧壁向靠近开孔区3的方向凹陷，或者是仅第二子层302的靠近开孔区3的侧壁向远离开孔区3的方向凹陷。这种单侧向内凹陷形成的凹槽结构也能够隔断隔离柱30上方的膜层。
如图2所示，与显示区1的距离最近的隔离柱30还包括绝缘部304，绝缘部304位于第二子层302的远离开孔区3的侧壁向靠近开孔区3的方向凹陷形成的凹槽结构中，且绝缘部304分别与第一子层301、第二子层302和第三子层303连接。
绝缘部304可以隔断显示区1的第一电极21与隔离柱30的电连接，防止第一电极30上的电信号与负压信号源提供的负压电信号产生干扰或者冲突。
示例性地，绝缘部304的制作材料可以为有机绝缘材料，也可以为无机绝缘材料。例如，绝缘部304的制作材料可以为亚克力有机胶等。
示例性地，形成凹槽结构可以是截面为梯形的凹槽结构或者界面为弧形的凹槽结构。本公开实施例对凹槽结构的形状不做限制，只要能够隔断隔离柱30上方的膜层即可。
下面对显示面板的层级结构进行示例性说明。
可选地，衬底基板101与驱动电路层10组成驱动背板，驱动背板可以是低温多晶硅氧化物(Low-Temperature Polycrystalline Oxide，LTPO)背板或低温多晶硅(Low-Temperature Poly-Silicon，LTPS)背板。
可选地，驱动电路层10包括多个薄膜晶体管(Thin Film Transistor，TFT)。
如图2所示，以LTPO背板为例，多个TFT包括低温多晶硅TFT和金属氧化物TFT。
可选地，驱动电路层还包括缓冲层103、第一有源层104、第一栅极绝缘层105、第一绝缘层107、第二栅极绝缘层109、第二有源层110、第三栅极绝缘层111、第三栅极层112、层间介电层113、第一源漏极层114、钝化层115、第一平坦化层116、第二源漏极层117和第二平坦化层118。图2中，底部遮光层102、缓冲层103、第一有源层104、第一栅极绝缘层105、第一栅极层106、第一绝缘层107、第二栅极层108、第二栅极绝缘层109、第二有源层110、第三栅极绝缘层111、第三栅极层112、层间介电层113、第一源漏极层114、钝化层115、第一平坦化层116、第二源漏极层117和第二平坦化层118沿远离第一表面的方向依次层叠。
示例性地，驱动电路层还可以包括引出电极119，引出电极119与第一源漏极层114同层，且通过过孔与底部遮光层102连接。引出电极119可以用于为底部遮光层102提供一个电压恒定为-7V的负压电信号，该电信号用于防止TFT特性漂移导致的漏电。
示例性地，发光功能层20可以包括沿远离第一表面的方向依次层叠的第二电极(图未示)、像素定义层23、发光层22和第一电极21。
示例性地，像素定义层23为半色调像素定义层(Halftone Pixel Define Layer，HPDL)，第一电极21为阴极层，第二电极为阳极层。
示例性地，衬底基板101可以为任意呈透明的基板，例如玻璃基板、石英基板、塑胶基板、其他透明的硬质基板或者其他透明的可挠式基板，其可以是单层或多层结构。以多层结构为例，衬底基板101包括由下至上依次层叠设置的第一PI(聚酰亚胺)层、第一保护层、第二PI层、第二保护层，两个保护层用于保护PI层，防止后续工艺对PI层的破坏。第二保护层上还覆盖有缓冲层103，可以阻挡水氧和阻隔碱性离子。
示例性地，底部遮光层102的制作材料可以为金属材料，包括但不限于钼、铝、钛、铜等材料，底部遮光层102可以减少TFT受到的光照，同时还能够导电。
示例性地，第一有源层104采用低温多晶硅材料制成，第二有源层110采用铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)等金属氧化物半导体材料制成。
示例性地，第一栅极绝缘层105、第一绝缘层107、第二栅极绝缘层109、 第三栅极绝缘层111和层间介电层113的制作材料可以是硅氧化物或硅氮化物，硅氮氧化物等。
示例性地，第一栅极层106和第二栅极层108的制作材料为金属材料，例如钼、铜、铝中的一种或者多种。
示例性地，第三栅极层112包括层叠的第一子栅极层和第二子栅极层。第一子栅极层采用透明导电材料制成，例如氧化铟锡(Indium tin oxide，ITO)。第二子栅极层采用金属材料制成，可以为单层金属层或者包括依次层叠的多层金属层。第二子栅极层中的金属层采用的金属材料可以为钛、铝、钛等。
示例性地，钝化层115的制作材料可以为氧化硅层或者氮化硅层。
示例性地，第一平坦化层116和第二平坦化层118采用有机绝缘材料制成，如树脂等。
示例性地，像素定义层23的制作材料包括聚酰亚胺、聚酞亚胺、聚酞胺、氧化硅、氮化硅等中的一种或多种。
示例性地，第二电极可以采用金属材料制成，例如金等，或者，第二电极可以采用透明导电材料制成，例如ITO等。
示例性地，发光层22可以包括空穴传输层(Hole Transport Layer，HTL)、空穴注入层(Hole Injection Layer，HIL)、电子传输层(Electron Transport Layer，ETL)、电子注入层(Electron Injection Layer，EIL)、空穴阻挡层(Hole Block Layer，HBL)、电子阻挡层(Electron Blocking Layer，EBL)和发光材料层。
示例性地，第一电极21采用镁银合金等金属材料制成；或者采用透明导电材料制成，例如ITO等。
示例性地，第一源漏极层114可以包括依次层叠的钛层、铝层和钛层等多层金属薄膜。第二源漏极层117可以包括依次层叠的钛层、铝层和钛层等多层金属薄膜。
在本公开实施例中，隔离柱30可以与第一源漏极层114或第二源漏极层117同层。相应的，第一子层301和第三子层303可以为钛层，第二子层302可以为铝层。
可选地，显示面板还包括封装层60，封装层60位于发光功能层20的远离第一表面的一侧。封装层60可以保护下方发光功能层20，阻挡水氧入侵，保证显示面板的可靠性。
示例性地，封装层60可以包括沿远离第一表面的方向依次层叠的第一无机封装层61、有机封装层62和第二无机封装层63。当然，封装层60也可以包括别的更多或更少的膜层，本公开对此不做限制。
示例性地，第一无机封装层61的制作材料为氮化硅、氧化硅或氮氧化硅材料。第二无机封装层63的制作材料为氮化硅、氧化硅或氮氧化硅材料。有机封装层62采用有机绝缘材料制成，这里，有机绝缘材料包括聚酰亚胺、聚酰胺、丙烯酸树脂、苯并环丁烯、六甲基二硅氧烷(HMDSO)、酚醛树脂等材料。
可选地，显示面板还包括隔离坝33，隔离坝33位于隔离区2，且隔离坝33位于第一表面，隔离坝33的高度大于隔离柱30的高度。隔离坝33可进一步防止水氧进入显示区1而造成显示不良，且能防止有机封装层62溢出至开孔区3，提高显示面板的可靠性。
示例性地，隔离坝33在衬底基板101上的正投影位于第一隔离柱31在衬底基板101上的正投影与第二隔离柱32在衬底基板101上的正投影之间。
示例性地，隔离坝33可以与像素定义层23同层。
在本公开实施例中，同层是指通过同一构图工艺形成，或者，与同一膜层的同一表面接触，或者，位于同一膜层的同一侧等。
如图2所示，位于隔离区2且位于多个隔离柱30的靠近第一表面的一侧的层间介电层113中具有凹槽34。
图3是本公开实施例提供的一种显示面板的局部平面结构示意图。图3可以是图1所示的显示面板在虚线框C处的局部平面结构示意图。如图3所示，凹槽34在衬底基板101上的正投影位于隔离坝33在衬底基板101上的正投影与第一隔离柱31在衬底基板101上的正投影之间。凹槽34可以使隔离坝34与第一隔离柱31之间的高度起伏更大，形成开孔区3的过程中产生的裂纹传播至该起伏处时如果裂纹要继续传播需要改变方向，改变方向传播需要消耗较大的能量，并且该起伏高度较大增加了裂纹的传播路径，因此可以阻碍裂纹传播，减小形成开孔区3的过程中产生的裂纹传播至显示区1的几率，保证显示面板的可靠性。
如图3所示，多个第一隔离柱31之间、相邻的第一隔离柱31和第二隔离柱32之间以及多个第二隔离柱32之间均通过第二连接线41实现电连接，从而使所有的隔离柱30的电位为负电位，有利于提高显示面板的可靠性。
图4是本公开实施例提供的另一种显示面板的截面结构示意图。图4所示的显示面板与图2所示的显示面板的区别在于第一连接线40和第一金属环50的连接方式不同。图4中第一连接线40与底部遮光层102同层。第一金属环50通过过孔与第一连接线40连接。这样可以通过底部遮光层102上的引出电极119连接负压信号源使隔离柱30的电位为负电位。
图5是本公开实施例提供的又一种显示面板的截面结构示意图。图5所示的显示面板与图2所示的显示面板的区别在于，图5中第一连接线40、隔离柱30下方的第二连接线41、第一金属环50和第二金属环51均与第一栅极层106同层。
如图5所示，第二隔离柱32的侧壁具有延伸部35，延伸部35通过过孔与第二金属环51连接，第二金属环51与第二连接线41连接。
由于第二隔离柱32在衬底基板101上的正投影位于第三金属环52在衬底基板101上的正投影内，第三金属环52在衬底基板101上的正投影位于第二金属环51在衬底基板101上的正投影内。这样，通过在第二隔离柱32的侧壁设置延伸部35，可以使第二隔离柱32与第二金属环51连接，进而通过第二连接线41使第一隔离柱31与第二隔离柱32电连接。
图6是本公开实施例提供的又一种显示面板的截面结构示意图。图6所示的显示面板与图5所示的显示面板的区别在于第一连接线40和第一金属环50的连接方式不同。图6中第一连接线40与底部遮光层102同层。第一金属环50通过过孔与第一连接线40连接。这样可以通过底部遮光层102连接负压信号源使隔离柱30的电位为负电位。
图4至图6所示实施例中，其余各层的结构、材料以及各层在衬底基板101上的正投影的位置关系等参见图2相关实施例，在此省略详细描述。
图7是本公开实施例提供的一种显示面板的制作方法流程图。如图7所示，该制作方法包括：
在步骤S701中，提供一衬底基板。
衬底基板具有显示区、隔离区和开孔区，显示区围绕开孔区，隔离区位于显示区和开孔区之间。
在步骤S702中，在衬底基板的第一表面形成发光功能层。
发光功能层包括多个发光单元，多个发光单元阵列布置在显示区中，发光单 元包括第一电极。
在步骤S703中，在隔离区且在第一表面形成多个隔离柱。
隔离柱呈环形且围绕开孔区，隔离柱为金属结构，隔离柱与第一电极绝缘且至少一个隔离柱与负压信号源电连接。
本公开实施例中，隔离柱为金属结构，通过将隔离柱与第一电极绝缘且与负压信号源电连接，第一电极上的电信号不会与负压信号源提供的负压电信号产生干扰或者冲突，且隔离柱的电位为负电位，当隔离柱与外界水氧接触时，隔离柱难以失去电子而被氧化，可以减轻金属结构的隔离柱的电化学腐蚀程度，减小封装失效的几率，从而提高显示面板的可靠性。
图8是本公开实施例提供的另一种显示面板的制作方法流程图。该制作方法用于制作图2所示的显示面板，如图8所示，该制作方法包括：
在步骤S801中，提供一衬底基板。
在步骤S802中，在衬底基板的第一表面形成驱动电路层。
示例性地，该步骤S802可以包括：
第一步，在衬底基板上沉积遮光金属层，然后通过光刻胶涂覆、曝光、显影等工艺得到光刻胶结构，并以该光刻胶结构为掩膜对遮光金属层进行刻蚀，得到底部遮光层。
第二步，在底部遮光层上形成缓冲层，例如，通过沉积的方式在底部遮光层上形成缓冲层。然后，在缓冲层上形成第一有源层，例如，可以先在在缓冲层上沉积形成初始第一有源层，通过光刻胶涂覆、曝光、显影等工艺得到光刻胶结构，并以该光刻胶结构为掩膜对初始第一有源层进行刻蚀，以形成第一有源层。
第三步，在第一有源层上依次通过例如沉积的方式形成初始第一栅极绝缘层和初始第一栅极层。初始第一栅极绝缘层覆盖第一有源层。在初始第一栅极层上通过光刻胶涂覆、曝光、显影等工艺得到光刻胶结构，并以该光刻胶结构为掩膜对初始第一栅极层进行刻蚀，形成第一栅极图案层。第一栅极图案层包括位于显示区的第一栅极层和位于隔离区的第二金属环。可选地，对于未被第一栅极层覆盖的部分第一有源层进行导体化，以保证第一有源层与后续形成的第一源漏极层之间具有良好的欧姆接触。
第四步，在第一栅极图案层上依次通过例如沉积的方式形成初始第一绝缘层和初始第二栅极层。在初始第二栅极层上通过光刻胶涂覆、曝光、显影等工艺 得到光刻胶结构，并以该光刻胶结构为掩膜对初始第二栅极层进行刻蚀，形成第二栅极图案层。第二栅极图案层包括第二栅极层、第一连接线、第二连接线、第一金属环和第三金属环。
第五步，在第二栅极层上依次通过例如沉积的方式形成初始第二栅极绝缘层和初始第二有源层，然后通过光刻胶涂覆、曝光、显影等工艺得到光刻胶结构，并以该光刻胶结构为掩膜对初始第二有源层进行刻蚀，得到第二有源层。
第六步，在第二有源层上依次通过例如沉积的方式形成初始第三栅极绝缘层和初始第三栅极层。初始第三栅极绝缘层覆盖第二有源层。在初始第三栅极层上通过光刻胶涂覆、曝光、显影等工艺得到光刻胶结构，并以该光刻胶结构为掩膜对初始第三栅极层进行刻蚀，形成第三栅极层。可选地，对于未被第三栅极层覆盖的部分第二有源层进行导体化，以保证第二有源层与后续形成的第二源漏极层之间具有良好的欧姆接触。
第七步，在第三栅极层上通过例如沉积的方式形成初始层间介电层。通过光刻胶涂覆、曝光、刻蚀、剥离等一系列工序，形成多个暴露出遮光层的过孔，同时由初始第一栅极绝缘层得到第一栅极绝缘层；再通过光刻胶涂覆、曝光、刻蚀、剥离等一系列工序，形成多个暴露出第一有源层的过孔，同时由初始第一绝缘层得到第一绝缘层、由初始第二栅极绝缘层得到第二栅极绝缘层。同时得到层间介电层。
第八步，在第七步刻蚀得到的暴露遮光层和第一有源层的过孔后，通过采用例如沉积、光刻胶涂覆、曝光、刻蚀、剥离等一系列工序形成第一源漏极图案层，第一源漏极图案层包括位于显示区的第一源漏极层和引出电极，以及位于隔离区多个隔离柱。可选地，隔离柱包括沿远离第一表面的方向依次层叠的第一子层、第二子层和第三子层，第二子层的远离开孔区的侧壁向靠近开孔区的方向凹陷，且第二子层的靠近开孔区的侧壁向远离开孔区的方向凹陷。
第九步，在第一源漏极图案层上通过例如沉积的方式因此形成初始钝化层和初始第一平坦化层。通过光刻胶涂覆、曝光、刻蚀、剥离等一系列工序，形成多个暴露出第二有源层的过孔，同时由初始第三栅极绝缘层得到第三栅极绝缘层，由初始钝化层得到钝化层，由初始第一平坦化层得到第一平坦化层。
第十步，在第九步刻蚀得到的暴露第二有源层的过孔内，通过采用例如沉积、光刻胶涂覆、曝光、刻蚀、剥离等一系列工序形成第二源漏极层。
第十一步，在第二源漏极层上通过例如沉积的方式形成第二平坦化层。
在步骤S803中，在与显示区的距离最近的隔离柱的靠近显示区的一侧的凹槽结构中形成绝缘部。
在步骤S804中，在驱动电路层的远离第一表面的一侧形成发光功能层。
可选地，发光功能层可以包括多个发光单元，多个发光单元阵列布置在显示区中，且多个发光单元的第一电极相连。
可选地，发光功能层包括沿远离第一表面的方向依次层叠的第二电极、像素定义层、发光层和第一电极。
示例性地，像素定义层为HPDL，第一电极层为阴极层，第二电极层为阳极层。
在步骤S805中，在发光功能层的远离第一表面的一侧形成封装层。
可选地，各层的结构、材料以及各层在衬底基板上的正投影的位置关系等参见图2相关实施例，在此省略详细描述。
用于制作图4至图6所示的显示面板的制作方法的与图8实施例中的制作方法的区别主要在于第一连接线和第二连接线的同层制作情况不同。也即是在形成底部遮光层、形成第一栅极层或形成第二栅极层的步骤中光刻后形成的图案不同，在此省略详细描述。
图9是本公开实施例提供的一种显示装置的结构示意图。如图9所示，该显示装置包括供电电路1001和前述的显示面板1000，供电电路1001为显示面板1000供电。
可选地，该显示装置可以为笔记本电脑、手机、平板电脑、电视机、显示器、可穿戴设备、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，并非对本公开作任何形式上的限制，虽然本公开已通过实施例揭露如上，然而并非用以限定本公开，任何熟悉本专业的技术人员，在不脱离本公开技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本公开技术方案的内容，依据本公开的技术实质对以上实施例所作的任何简单修改、等同变化与修饰，均仍属于本公开技术方案的范围内。

Claims (15)

  1. 一种显示面板，其特征在于，包括衬底基板、发光功能层和多个隔离柱；
    所述衬底基板具有显示区、隔离区和开孔区，所述显示区围绕所述开孔区，所述隔离区位于所述显示区和所述开孔区之间；
    所述发光功能层位于所述衬底基板的第一表面，所述发光功能层包括多个发光单元，所述多个发光单元阵列布置在所述显示区中，所述发光单元包括第一电极；
    所述多个隔离柱位于所述隔离区且位于所述第一表面，所述隔离柱呈环形且围绕所述开孔区，所述隔离柱为金属结构，所述隔离柱与所述第一电极绝缘且至少一个所述隔离柱与负压信号源电连接。
  2. 根据权利要求1所述的显示面板，其特征在于，所述显示面板还包括驱动电路层和第一连接线，所述驱动电路层位于所述发光功能层和所述衬底基板之间，所述第一连接线分别与所述负压信号源和所述隔离柱电连接，且所述第一连接线与所述驱动电路层中的至少一层导电层同层。
  3. 根据权利要求2所述的显示面板，其特征在于，所述驱动电路层包括沿远离所述第一表面的方向依次位于所述第一表面的底部遮光层、第一栅极层和第二栅极层；
    所述至少一层导电层包括所述底部遮光层、所述第一栅极层和所述第二栅极层中的至少一层。
  4. 根据权利要求3所述的显示面板，其特征在于，所述多个隔离柱包括至少一个第一隔离柱和至少一个第二隔离柱，所述第一隔离柱环绕所述第二隔离柱，所述第一隔离柱与所述第一连接线电连接，或者所述第二隔离柱与所述第一连接线电连接；
    所述第二隔离柱通过第二连接线与所述第一隔离柱电连接。
  5. 根据权利要求4所述的显示面板，其特征在于，所述第二连接线与所述第 一电极同层。
  6. 根据权利要求4所述的显示面板，其特征在于，所述第二连接线与所述底部遮光层、所述第一栅极层和所述第二栅极层中的至少一层同层。
  7. 根据权利要求6所述的显示面板，其特征在于，所述显示面板还包括第一金属环，所述第一金属环位于所述衬底基板和所述第一隔离柱之间，所述第一隔离柱在所述衬底基板上的正投影位于所述第一金属环在所述衬底基板上的正投影内，所述第一金属环与所述第二连接线同层且连接，所述第一隔离柱通过过孔与所述第一金属环连接，所述第一连接线与所述第一金属环连接。
  8. 根据权利要求6所述的显示面板，其特征在于，所述显示面板还包括沿远离所述第一表面的方向依次位于所述第一表面的第二金属环和第三金属环，所述第二金属环位于所述衬底基板和所述第二隔离柱之间，所述第三金属环位于所述第二金属环与所述第二隔离柱之间，所述第二隔离柱在所述衬底基板上的正投影位于所述第三金属环在所述衬底基板上的正投影内，所述第三金属环在所述衬底基板上的正投影位于所述第二金属环在所述衬底基板上的正投影；
    所述第二隔离柱的侧壁具有延伸部，所述延伸部通过过孔与所述第二金属环连接，所述第二金属环与所述第二连接线同层且连接；或者，
    所述第二隔离柱通过过孔与所述第三金属环连接，所述第三金属环与所述第二连接线同层且连接。
  9. 根据权利要求2至8任一项所述的显示面板，其特征在于，所述负压信号源用于为所述驱动电路层提供初始化信号或者发光控制信号。
  10. 根据权利要求9所述的显示面板，其特征在于，所述隔离柱包括沿远离所述第一表面的方向依次层叠的第一子层、第二子层和第三子层，所述第二子层的远离所述开孔区的侧壁向靠近所述开孔区的方向凹陷；
    和/或，所述第二子层的靠近所述开孔区的侧壁向远离所述开孔区的方向凹陷。
  11. 根据权利要求10所述的显示面板，其特征在于，与所述显示区的距离最近的所述隔离柱还包括绝缘部，所述绝缘部位于所述第二子层的远离所述开孔区的侧壁向靠近所述开孔区的方向凹陷形成的凹槽结构中，且所述绝缘部分别与所述第一子层、所述第二子层和所述第三子层连接。
  12. 根据权利要求1至8和权利要求10至11任一项所述的显示面板，其特征在于，所述显示面板还包括封装层，所述封装层位于所述发光功能层的远离所述第一表面的一侧。
  13. 根据权利要求1至8和权利要求10至11任一项所述的显示面板，其特征在于，所述显示面板还包括隔离坝，所述隔离坝位于隔离区，且所述隔离坝位于所述第一表面，所述隔离坝的高度大于所述隔离柱的高度。
  14. 一种显示面板的制作方法，其特征在于，包括：
    提供一衬底基板，所述衬底基板具有显示区、隔离区和开孔区，所述显示区围绕所述开孔区，所述隔离区位于所述显示区和所述开孔区之间；
    在所述衬底基板的第一表面形成发光功能层，所述发光功能层包括多个发光单元，所述多个发光单元阵列布置在所述显示区中，所述发光单元包括第一电极；
    在所述隔离区且在所述第一表面形成多个隔离柱，所述隔离柱呈环形且围绕所述开孔区，所述隔离柱为金属结构，所述隔离柱与所述第一电极绝缘且至少一个所述隔离柱与负压信号源电连接。
  15. 一种显示装置，其特征在于，包括供电电路和如权利要求1至13任一项所述的显示面板，所述供电电路为所述显示面板供电。
PCT/CN2024/126135 2023-11-29 2024-10-21 显示面板及其制作方法、显示装置 Pending WO2025112976A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202311612832.4A CN117500336A (zh) 2023-11-29 2023-11-29 显示面板及其制作方法、显示装置
CN202311612832.4 2023-11-29

Publications (1)

Publication Number Publication Date
WO2025112976A1 true WO2025112976A1 (zh) 2025-06-05

Family

ID=89680069

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/126135 Pending WO2025112976A1 (zh) 2023-11-29 2024-10-21 显示面板及其制作方法、显示装置

Country Status (2)

Country Link
CN (1) CN117500336A (zh)
WO (1) WO2025112976A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117500336A (zh) * 2023-11-29 2024-02-02 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN121038522A (zh) * 2024-05-28 2025-11-28 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置
CN119907405B (zh) * 2024-07-24 2026-05-01 合肥维信诺科技有限公司 显示面板及显示装置
WO2026055941A1 (zh) * 2024-09-13 2026-03-19 京东方科技集团股份有限公司 显示面板及其制备方法、显示装置
CN118900589B (zh) * 2024-09-27 2024-12-20 京东方科技集团股份有限公司 显示面板和显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230157101A1 (en) * 2020-10-22 2023-05-18 Boe Technology Group Co., Ltd. Display substrate and manufacturing method therefor, and display apparatus
WO2023088096A1 (zh) * 2021-11-17 2023-05-25 华为技术有限公司 显示面板及其制作方法、电子设备
CN117082917A (zh) * 2023-09-28 2023-11-17 京东方科技集团股份有限公司 显示面板和显示装置
CN117500336A (zh) * 2023-11-29 2024-02-02 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230157101A1 (en) * 2020-10-22 2023-05-18 Boe Technology Group Co., Ltd. Display substrate and manufacturing method therefor, and display apparatus
WO2023088096A1 (zh) * 2021-11-17 2023-05-25 华为技术有限公司 显示面板及其制作方法、电子设备
CN117082917A (zh) * 2023-09-28 2023-11-17 京东方科技集团股份有限公司 显示面板和显示装置
CN117500336A (zh) * 2023-11-29 2024-02-02 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN117500336A (zh) 2024-02-02

Similar Documents

Publication Publication Date Title
US11678528B2 (en) Display substrate, method of manufacturing display substrate, and display device including display substrate
US12453243B2 (en) Organic light emitting diode display device
US11189679B2 (en) Array substrate and manufacturing method therefor, and display device
US12557485B2 (en) Display substrate and manufacturing method therefor, and display device
US11723257B2 (en) Organic light emitting diode display substrate, manufacturing method therefor, and organic light emitting diode display device
US11257957B2 (en) Thin film transistor, method of fabricating the same, array substrate and display device
US11961850B2 (en) Display substrate, manufacturing method thereof, and display device
CN111627973B (zh) 一种显示基板及其制备方法、显示装置
CN111415995B (zh) 一种显示面板、其制作方法及显示装置
CN113707725B (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
US12230695B2 (en) Display substrate and manufacturing method thereof, display device
WO2025025859A1 (zh) 显示面板及其制作方法和显示装置
US12133433B2 (en) Display panel and method for manufacturing same
CN117500336A (zh) 显示面板及其制作方法、显示装置
CN114664912A (zh) 有机发光二极管显示面板及其制造方法
CN113471257B (zh) 显示面板及移动终端
US20250287813A1 (en) Display panel, method for manufacturing display panel, and display device
CN115000089B (zh) 阵列基板及其制造方法、显示装置
US12628508B2 (en) Display substrate, method for manufacturing same and display device
US11282867B2 (en) Manufacturing method of display substrate motherboard, and display device
CN114823725B (zh) 显示面板及显示面板的制作方法
WO2023226080A1 (zh) 显示面板及制作方法、电子设备
WO2025054831A1 (zh) 显示面板及其制作方法、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24896069

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE