WO2025018112A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025018112A1
WO2025018112A1 PCT/JP2024/023093 JP2024023093W WO2025018112A1 WO 2025018112 A1 WO2025018112 A1 WO 2025018112A1 JP 2024023093 W JP2024023093 W JP 2024023093W WO 2025018112 A1 WO2025018112 A1 WO 2025018112A1
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Prior art keywords
layer
semiconductor device
lead
semiconductor
bonding
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PCT/JP2024/023093
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English (en)
French (fr)
Japanese (ja)
Inventor
達也 藤井
健裕 三角
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2025533935A priority Critical patent/JPWO2025018112A1/ja
Publication of WO2025018112A1 publication Critical patent/WO2025018112A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses an example of a conventional semiconductor device.
  • the semiconductor device disclosed in this document includes a die pad and a semiconductor element.
  • the semiconductor element is mounted on the die pad.
  • the die pad has a pad main surface.
  • the semiconductor element is mounted on the pad main surface by die bonding using a conductive bonding layer.
  • the die pad is made of Cu (copper) or a copper alloy.
  • the pad main surface is plated with Ag (silver) in consideration of bonding properties, etc.
  • Ag plating is formed on the pad main surface in this way leads to increased manufacturing costs.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional semiconductor devices.
  • an object of the present disclosure is to provide a semiconductor device that is suitable for improving the bondability to the leads of a semiconductor element while suppressing an increase in manufacturing cost.
  • a semiconductor device provided by one aspect of the present disclosure includes a first lead, a semiconductor element having a semiconductor layer mounted on one side of the first lead in the thickness direction, and a bonding layer interposed between the first lead and the semiconductor layer and bonding the first lead and the semiconductor element.
  • the bonding layer contains Sn and Cu.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 3 is a perspective view of a main part showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 4 is a perspective view of a main part showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 5 is a plan view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 6 is a bottom view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 7 is a front view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 8 is a side view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a perspective view showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 9 is a plan view showing a main part of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 10 is a bottom view of a main portion showing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view taken along line XI-XI of FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG.
  • FIG. 14 is a partially enlarged cross-sectional view of FIG.
  • FIG. 15 is a partially enlarged cross-sectional view showing a process in the manufacture of the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 16 is a partially enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 17 is a partially enlarged cross-sectional view showing a process in the manufacture of a semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 18 is a partially enlarged cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 19 is a partial enlarged cross-sectional view showing a process in the manufacture of a semiconductor device according to the third embodiment of the present disclosure.
  • an object A is formed on an object B" and “an object A is formed on an object B” include “an object A is formed directly on an object B” and “an object A is formed on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A is disposed on an object B” and “an object A is disposed on an object B” include “an object A is disposed directly on an object B” and “an object A is disposed on an object B with another object interposed between the object A and the object B" unless otherwise specified.
  • an object A is located on an object B includes “an object A is located on an object B in contact with an object B” and “an object A is located on an object B with another object interposed between the object A and the object B” unless otherwise specified.
  • an object A overlaps an object B when viewed in a certain direction includes “an object A overlaps the entire object B” and “an object A overlaps a part of an object B.”
  • a surface A faces in direction B is not limited to the case where the angle of surface A with respect to direction B is 90 degrees, but also includes the case where surface A is tilted with respect to direction B.
  • First embodiment: 1 to 14 show a semiconductor device according to a first embodiment of the present disclosure.
  • the semiconductor device A1 of this embodiment includes a semiconductor element 1, a first lead 2, a second lead 3, a third lead 4, a first bonding wire 5, a second bonding wire 6, a bonding layer 7, and a sealing resin 8.
  • the application of the semiconductor device A1 is not limited in any way, and it is used in electronic devices equipped with a power conversion circuit, such as a DC-DC converter.
  • FIGS. 3 and 4 are perspective views showing the semiconductor device A1.
  • FIGS. 3 and 4 are perspective views of the main part of the semiconductor device A1.
  • the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line).
  • FIG. 5 is a plan view showing the semiconductor device A1.
  • FIG. 6 is a bottom view showing the semiconductor device A1.
  • FIG. 7 is a front view showing the semiconductor device A1.
  • FIG. 8 is a side view showing the semiconductor device A1.
  • FIG. 9 is a plan view of the main part of the semiconductor device A1.
  • FIG. 10 is a bottom view of the main part of the semiconductor device A1.
  • the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line).
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 10.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. 10.
  • FIG. 14 is a partially enlarged cross-sectional view of FIG. 11.
  • an example of the thickness direction of the present disclosure is the "thickness direction z".
  • An example of a direction perpendicular to the thickness direction z is called the "first direction x”.
  • An example of a direction perpendicular to the thickness direction z and the first direction is called the "second direction y”.
  • one side of the thickness direction z is an example of the "one side of the thickness direction” of the present disclosure and is called the “z1 side of the thickness direction z”
  • the other side of the thickness direction z is an example of the "other side of the thickness direction” of the present disclosure and is called the "z2 side of the thickness direction z”.
  • One side of the first direction x is an example of the "one side of the first direction” of the present disclosure and is called the “x1 side of the first direction x”
  • the other side of the first direction x is an example of the "other side of the first direction” of the present disclosure and is called the "x2 side of the first direction x”.
  • An example of one side of the second direction y is called the “y1 side of the second direction y”
  • an example of the other side of the second direction y is called the "y2 side of the second direction y".
  • the semiconductor element 1 is an element that exerts the electrical function of the semiconductor device A1.
  • the semiconductor element 1 is a three-terminal element having three electrodes, for example a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).
  • the semiconductor element 1 may be a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a diode.
  • the semiconductor element 1 is an n-channel type MOSFET with a vertical structure.
  • the semiconductor element 1 is rectangular when viewed in the thickness direction z. As shown in Figures 4 and 10 to 14, the semiconductor element 1 has a semiconductor layer 10, a first electrode 11, a second electrode 12, and a third electrode 13.
  • the semiconductor layer 10 is a layer that contains a semiconductor.
  • the composition of the semiconductor contains, for example, Si (silicon), SiC (silicon carbide), etc.
  • the semiconductor layer 10 contains, for example, GaN (gallium nitride).
  • the first electrode 11 is disposed on the z2 side of the semiconductor layer 10 in the thickness direction z.
  • a current corresponding to the power before being converted by the semiconductor element 1 flows through the first electrode 11.
  • the first electrode 11 corresponds to the drain electrode of the semiconductor element 1.
  • the second electrode 12 is disposed on the z1 side of the semiconductor layer 10 in the thickness direction z. A current corresponding to the power converted by the semiconductor element 1 flows through the second electrode 12. In other words, the second electrode 12 corresponds to the source electrode of the semiconductor element 1.
  • the third electrode 13 is disposed on the z1 side of the semiconductor layer 10 in the thickness direction z.
  • a gate voltage for driving the semiconductor element 1 is applied to the third electrode 13.
  • the third electrode 13 corresponds to the gate electrode of the semiconductor element 1.
  • the area of the third electrode 13 is smaller than the area of the second electrode 12.
  • the first electrode 11 includes a first intermediate metal layer 111 and a second metal layer 112.
  • the first intermediate metal layer 111 is interposed between the semiconductor layer 10 and the second metal layer 112, and is in contact with the semiconductor layer 10.
  • the first intermediate metal layer 111 contains, for example, Ti (titanium), Ni (nickel), etc.
  • the first intermediate metal layer 111 may be a single layer, or may be a laminate of multiple layers.
  • the thickness (dimension in the thickness direction z) of the first intermediate metal layer 111 is, for example, 0.05 ⁇ m or more and 2.0 ⁇ m or less.
  • the first intermediate metal layer 111 is a layer for preventing the semiconductor layer 10 from being damaged when the second metal layer 112 is formed.
  • the second metal layer 112 contacts the first intermediate metal layer 111.
  • the second metal layer 112 contains, for example, Ag (silver) or Cu (copper).
  • the second metal layer 112 is mainly composed of Ag (silver).
  • Specific examples of the second metal layer 112 mainly composed of Ag (silver) include an Ag (silver) plating layer and an Ag (silver) layer formed by a film formation technique such as sputtering.
  • the thickness of the second metal layer 112 is, for example, 0.50 ⁇ m or more and 5.0 ⁇ m or less. In the illustrated example, the second metal layer 112 forms the surface layer of the first electrode 11.
  • the first lead 2, the second lead 3, and the third lead 4 are formed, for example, by punching or bending a metal plate (lead frame).
  • the first lead 2, the second lead 3, and the third lead 4 contain, for example, Cu (copper) or Ni (nickel).
  • the constituent material of each of the first lead 2, the second lead 3, and the third lead 4 contains Fe (iron) and Ni (nickel), and is, for example, 42 alloy.
  • the first lead 2 includes a portion that is disposed on the z1 side of the semiconductor element 1 in the thickness direction z. As shown in Figures 2 to 13, the first lead 2 includes a first pad portion 21 and a first terminal portion 22.
  • the first pad portion 21 is the portion on which the semiconductor element 1 is mounted.
  • the first pad portion 21 has a first main surface 201 and a second main surface 202.
  • the first main surface 201 is a surface facing the z1 side in the thickness direction z.
  • the second main surface 202 is a surface facing the z2 side in the thickness direction z.
  • the semiconductor element 1 is bonded to the first main surface 201 of the first pad portion 21 via a bonding layer 7.
  • the bonding layer 7 is made of a conductive material.
  • the first electrode 11 of the semiconductor element 1 faces the first main surface 201.
  • the first electrode 11 and the first main surface 201 are conductively bonded via the bonding layer 7.
  • the semiconductor element 1 is mounted on the first main surface 201 of the first pad portion 21 by die bonding.
  • the first pad portion 21 (first lead 2) has a base material 20A and a first plating layer 20B.
  • the base material 20A contains Fe (iron) and Ni (nickel) and is, for example, a 42 alloy.
  • the first plating layer 20B covers a portion of the base material 20A.
  • the first plating layer 20B covers at least the portion of the first pad portion 21 on which the semiconductor element 1 is mounted.
  • the constituent material of the first plating layer 20B contains Cu (copper).
  • the surface of the first plating layer 20B facing the z1 side in the thickness direction z constitutes at least a portion of the first main surface 201.
  • the bonding layer 7 includes a first intermetallic compound layer 71, a first metal layer 72, and a second intermetallic compound layer 73.
  • the first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2). More specifically, the first intermetallic compound layer 71 is in contact with the first plating layer 20B of the first pad portion 21.
  • the first plating layer 20B in contact with the first intermetallic compound layer 71 in the first pad portion 21 contains Cu (copper) as described above.
  • the first metal layer 72 is interposed between the first intermetallic compound layer 71 and the semiconductor layer 10, and is in contact with the first intermetallic compound layer 71.
  • the first metal layer 72 contains Sn (tin).
  • the second intermetallic compound layer 73 is interposed between the first intermetallic compound layer 71 and the semiconductor layer 10.
  • the second intermetallic compound layer 73 is interposed between the first metal layer 72 and the second metal layer 112, and is in contact with the first metal layer 72 and the second metal layer 112.
  • the first intermetallic compound layer 71 contains Sn (tin) and Cu (copper).
  • the first intermetallic compound layer 71 is formed by combining Sn (tin) constituting the first metal layer 72 with Cu (copper) constituting the first plating layer 20B.
  • the thickness t1 of the first intermetallic compound layer 71 is greater than the thickness t2 of the first metal layer 72.
  • the thickness t1 of the first intermetallic compound layer 71 is, for example, 0.50 ⁇ m or more and 5.0 ⁇ m or less.
  • the thickness t2 of the first metal layer 72 is, for example, 0 ⁇ m or more and 3.0 ⁇ m or less.
  • the boundary surfaces between the first intermetallic compound layer 71 and other layers adjacent to both sides in the thickness direction z are shown as flat, but the boundary surfaces may include uneven shapes.
  • the second intermetallic compound layer 73 contains Sn (tin) and Ag (silver).
  • the second intermetallic compound layer 73 is formed by combining Sn (tin) constituting the first metal layer 72 with Ag (silver) constituting the second metal layer 112.
  • the thickness of the second intermetallic compound layer 73 is, for example, 0.05 ⁇ m or more and 3.0 ⁇ m or less. Note that in the attached drawings, the boundary surfaces between the second intermetallic compound layer 73 and other adjacent layers on both sides in the thickness direction z are depicted as flat, but the boundary surfaces may include uneven shapes.
  • the first terminal portion 22 is connected to the first pad portion 21 on the y1 side in the second direction y.
  • the first terminal portion 22 extends in the second direction y when viewed in the thickness direction z.
  • the first terminal portion 22 is exposed from the sealing resin 8 and has a portion that protrudes from the sealing resin 8 to the y1 side in the second direction y, a portion that is folded back to the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z.
  • the first terminal portion 22 is used as a terminal when mounting the semiconductor device A1.
  • the first terminal portion 22 is electrically connected to the first electrode 11 of the semiconductor element 1.
  • the first terminal portion 22 is the drain terminal of the semiconductor device A1.
  • a plating layer made of an alloy mainly composed of Sn (tin), for example, may be formed on the portion of the first lead 2 exposed from the sealing resin 8 (first terminal portion 22).
  • a plating layer 203 is formed on the first terminal portion 22.
  • the second lead 3 is disposed on the x1 side of the first lead 2 in the first direction x. As shown in Figures 1 to 12, the second lead 3 includes a second pad portion 31 and a second terminal portion 32.
  • the second pad portion 31 is located on the x1 side in the first direction x with respect to the first pad portion 21. Although detailed illustration is omitted, a plating layer is formed on the surface of the second pad portion 31 facing the z1 side in the thickness direction z. Like the first pad portion 21, the second pad portion 31 has a base material made of 42 alloy and a plating layer covering the surface of the base material on the z1 side in the thickness direction z.
  • the constituent material of the plating layer includes Cu (copper).
  • a first bonding wire 5 is connected to the surface of the second pad portion 31 facing the z1 side in the thickness direction z.
  • the second terminal portion 32 is connected to the y2 side of the second direction y with respect to the second pad portion 31.
  • the second terminal portion 32 extends in the second direction y when viewed in the thickness direction z.
  • the second terminal portion 32 is exposed from the sealing resin 8, and has a portion that protrudes from the sealing resin 8 to the y2 side in the second direction y, a portion that is folded back to the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z.
  • the second terminal portion 32 is used as a terminal when mounting the semiconductor device A1.
  • a plating layer made of an alloy mainly composed of Sn (tin), for example, may be formed on the portion (second terminal portion 32) of the second lead 3 exposed from the sealing resin 8. Although detailed illustration is omitted, a plating layer is formed on the second terminal portion 32 in the same manner as the first terminal portion 22 described above.
  • the third lead 4 is disposed on the x2 side of the first lead 2 in the first direction x. As shown in Figures 1 to 7 and 9 to 13, the third lead 4 includes a third pad portion 41 and a third terminal portion 42.
  • the third pad portion 41 is located on the x2 side in the first direction x with respect to the first pad portion 21. Although detailed illustration is omitted, a plating layer is formed on the surface of the third pad portion 41 facing the z1 side in the thickness direction z. Like the first pad portion 21, the third pad portion 41 has a base material made of 42 alloy and a plating layer covering the surface of the base material on the z1 side in the thickness direction z.
  • the constituent material of the plating layer includes Cu (copper).
  • a second bonding wire 6 is connected to the surface of the third pad portion 41 facing the z1 side in the thickness direction z.
  • the third terminal portion 42 is connected to the third pad portion 41 on the y2 side in the second direction y.
  • the third terminal portion 42 extends in the second direction y when viewed in the thickness direction z.
  • the third terminal portion 42 is exposed from the sealing resin 8 and has a portion that protrudes from the sealing resin 8 to the y2 side in the second direction y, a portion that is folded back to the z1 side in the thickness direction z, and a portion that is located on the z1 side in the thickness direction z.
  • the third terminal portion 42 When viewed in the first direction x, has a shape and size that generally overlaps with the second terminal portion 32.
  • the third terminal portion 42 is used as a terminal when mounting the semiconductor device A1.
  • a plating layer made of an alloy mainly composed of Sn (tin), for example, may be formed on the portion of the third lead 4 exposed from the sealing resin 8 (third terminal portion 42). Although detailed illustration is omitted, a plating layer is formed on the third terminal portion 42 in the same manner as the first terminal portion 22 described above.
  • the first bonding wire 5 is bonded to the second electrode 12 of the semiconductor element 1 and the second pad portion 31 of the second lead 3.
  • the constituent material of the first bonding wire 5 is not limited in any way and may include metals such as Al (aluminum), Cu (copper), and Au (gold).
  • the number of first bonding wires 5 is also not limited in any way and multiple first bonding wires 5 may be provided.
  • the first bonding wire 5 includes Au (gold).
  • the second terminal portion 32 of the second lead 3 is electrically connected to the second electrode 12 of the semiconductor element 1 via the first bonding wire 5.
  • the second terminal portion 32 is the source terminal of the semiconductor device A1.
  • the second bonding wire 6 is bonded to the third electrode 13 of the semiconductor element 1 and the third pad portion 41 of the third lead 4.
  • the constituent material of the first bonding wire 5 is not limited in any way and includes metals such as Al (aluminum), Cu (copper), and Au (gold). In the illustrated example, the first bonding wire 5 includes Au (gold).
  • the third terminal portion 42 of the third lead 4 is electrically connected to the third electrode 13 of the semiconductor element 1 via the second bonding wire 6.
  • the third terminal portion 42 is the gate terminal of the semiconductor device A1.
  • the sealing resin 8 covers the semiconductor element 1, the first bonding wire 5, the second bonding wire 6, and a portion of each of the first lead 2, the second lead 3, and the third lead 4. More specifically, the sealing resin 8 covers the first pad portion 21, the second pad portion 31, and the third pad portion 41 of the first lead 2, the second lead 3, and the third lead 4.
  • the sealing resin 8 has electrical insulation properties.
  • the sealing resin 8 is made of a material that contains, for example, black epoxy resin.
  • the shape of the sealing resin 8 is not limited in any way.
  • the sealing resin 8 of this embodiment has a first resin surface 81, a second resin surface 82, a third resin surface 83, a fourth resin surface 84, a fifth resin surface 85, and a sixth resin surface 86.
  • the first resin surface 81 is a surface facing the z1 side in the thickness direction z.
  • the second resin surface 82 is a surface facing the z2 side in the thickness direction z.
  • the first resin surface 81 and the second resin surface 82 are flat surfaces, but are not limited to this and may be curved or bent surfaces, for example.
  • the third resin surface 83 is a surface facing the x1 side in the first direction x.
  • the fourth resin surface 84 is a surface facing the x2 side in the first direction x.
  • the third resin surface 83 and the fourth resin surface 84 are slightly curved surfaces, but are not limited to this and may be, for example, curved surfaces or flat surfaces.
  • the fifth resin surface 85 is a surface facing the y1 side in the second direction y.
  • the sixth resin surface 86 is a surface facing the y2 side in the second direction y.
  • the fifth resin surface 85 and the sixth resin surface 86 are slightly curved surfaces, but are not limited to this and may be, for example, curved surfaces or flat surfaces.
  • the first terminal portion 22 protrudes from the fifth resin surface 85, and the second terminal portion 32 and the third terminal portion 42 protrude from the sixth resin surface 86.
  • FIG. 15 is a partially enlarged view showing one step in the manufacture of the semiconductor device A1.
  • FIG. 15 shows a cross section similar to FIG. 14.
  • a bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z.
  • the bonding material portion 70 contains Sn (tin).
  • the bonding material portion 70 is pressed against the first plating layer 20B of the first pad portion 21 with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere.
  • the ambient temperature here is set to, for example, the melting point of Sn (tin) (approximately 232°C) or higher.
  • Cu copper
  • Ag silver
  • a first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the second intermetallic compound layer 73.
  • the bonding layer 7 contains Sn (tin) and Cu (copper). Specifically, the bonding layer 7 contains a first intermetallic compound layer 71, which contains Sn (tin) and Cu (copper).
  • This configuration improves the bonding to the first pad portion 21 of the semiconductor element 1 without forming Ag (silver) plating on the first pad portion 21 (first lead 2).
  • Ag (silver) plating since it is not necessary to form Ag (silver) plating, an increase in manufacturing costs can be suppressed.
  • the first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2).
  • the first plating layer 20B which is the portion of the first pad portion 21 (first lead 2) that is in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, it is possible to easily form the first intermetallic compound layer 71.
  • FIGS. 16 to 19 show other embodiments of the present disclosure.
  • elements that are the same as or similar to those in the above embodiment are given the same reference numerals as in the above embodiment, and duplicated explanations will be omitted.
  • the configurations of the various parts in each embodiment can be combined with each other as appropriate to the extent that no technical contradictions arise.
  • Second embodiment: 16 shows a semiconductor device according to a second embodiment of the present disclosure, which is a partially enlarged cross-sectional view showing a semiconductor device A2 according to the present embodiment, and shows a cross section similar to that shown in FIG.
  • the configuration of the first electrode 11 and the bonding layer 7 differs from that of the semiconductor device A1 described above.
  • the first electrode 11 does not include the second metal layer 112.
  • the bonding layer 7 does not include the second intermetallic compound layer 73.
  • the first metal layer 72 is interposed between the first intermetallic compound layer 71 and the first intermediate metal layer 111, and is in contact with the first intermetallic compound layer 71 and the first intermediate metal layer 111.
  • FIG. 17 is a partially enlarged view showing a step in the manufacture of the semiconductor device A2.
  • FIG. 17 shows a cross section similar to FIG. 16.
  • a bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z.
  • the bonding material portion 70 contains Sn (tin).
  • the bonding material portion 70 is pressed against the first plating layer 20B of the first pad portion 21 with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere.
  • the ambient temperature here is set to, for example, the melting point (about 232°C) of Sn (tin) or higher.
  • Cu (copper) which is a constituent material of the first plating layer 20B, diffuses into the bonding material portion 70. This forms a first intermetallic compound layer 71.
  • a first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the first intermediate metal layer 111.
  • the bonding layer 7 contains Sn (tin) and Cu (copper). Specifically, the bonding layer 7 contains a first intermetallic compound layer 71, which contains Sn (tin) and Cu (copper). With this configuration, it is possible to improve the bonding to the first pad portion 21 of the semiconductor element 1 without forming Ag (silver) plating on the first pad portion 21 (first lead 2). In the semiconductor device A2, since it is not necessary to form Ag (silver) plating, it is possible to suppress an increase in manufacturing costs.
  • the first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2).
  • the first plating layer 20B which is the portion of the first pad portion 21 (first lead 2) that is in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, it is possible to easily form the first intermetallic compound layer 71.
  • Third embodiment shows a semiconductor device according to a third embodiment of the present disclosure, which is a partially enlarged cross-sectional view showing a semiconductor device A3 according to the present embodiment, and shows a cross section similar to that shown in FIG.
  • the configuration of the first pad portion 21 is different from that of semiconductor device A1 described above.
  • the first pad portion 21 is configured to include a base material 20A and a first plating layer 20B, but in this embodiment, the first pad portion 21 is configured from a base material 20C.
  • the constituent material of base material 20C includes Cu (copper).
  • the first intermetallic compound layer 71 of the bonding layer 7 is in contact with the base material 20C of the first pad portion 21 (first lead 2).
  • the base material 20C in contact with the first intermetallic compound layer 71 in the first pad portion 21 contains Cu (copper).
  • FIG. 19 is a partially enlarged view showing one step in the manufacture of the semiconductor device A3.
  • FIG. 19 shows a cross section similar to FIG. 18.
  • a bonding material portion 70 is formed on the z1 side of the first electrode 11 of the semiconductor element 1 in the thickness direction z.
  • the bonding material portion 70 contains Sn (tin).
  • the bonding material portion 70 is pressed against the first pad portion 21 (base material 20C) with a predetermined load at a predetermined temperature and in a predetermined gas atmosphere.
  • the ambient temperature here is set to, for example, the melting point (about 232°C) of Sn (tin) or higher.
  • Cu (copper) which is a constituent material of the base material 20C, diffuses into the bonding material portion 70.
  • first intermetallic compound layer 71 This forms a first intermetallic compound layer 71.
  • Ag silver
  • second metal layer 112 diffuses into the bonding material portion 70 by the die bonding process.
  • a first metal layer 72 containing Sn (tin) is formed between the first intermetallic compound layer 71 and the second intermetallic compound layer 73.
  • the bonding layer 7 includes Sn (tin) and Cu (copper).
  • the bonding layer 7 includes a first intermetallic compound layer 71, which includes Sn (tin) and Cu (copper).
  • This configuration can improve the bonding to the first pad portion 21 of the semiconductor element 1 without forming Ag (silver) plating on the first pad portion 21 (first lead 2).
  • Ag (silver) plating since it is not necessary to form Ag (silver) plating, an increase in manufacturing costs can be suppressed.
  • the first intermetallic compound layer 71 is in contact with the first pad portion 21 (first lead 2).
  • the base material 20C which is the portion of the first pad portion 21 (first lead 2) that is in contact with the first intermetallic compound layer 71, contains Cu (copper). With this configuration, it is possible to easily form the first intermetallic compound layer 71.
  • the semiconductor device according to the present disclosure is not limited to the above-mentioned embodiment.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be freely designed in various ways.
  • the present disclosure includes configurations related to the following notes.
  • Appendix 1 The first lead; a semiconductor element having a semiconductor layer and mounted on one side of the first lead in a thickness direction; a bonding layer interposed between the first lead and the semiconductor layer and bonding the first lead and the semiconductor element, The semiconductor device, wherein the bonding layer contains Sn and Cu.
  • Appendix 2. The semiconductor device of claim 1, wherein the bonding layer includes a first intermetallic compound layer containing Sn and Cu.
  • Appendix 3. the first intermetallic compound layer is in contact with the first lead; 3.
  • the bonding layer includes a second intermetallic compound layer interposed between the first intermetallic compound layer and the semiconductor layer. Appendix 5. 5. The semiconductor device of claim 4, wherein the second intermetallic compound layer contains Sn and Ag. Appendix 6. the bonding layer includes a first metal layer interposed between the first intermetallic compound layer and the semiconductor layer and in contact with the first intermetallic compound layer; 6. The semiconductor device according to claim 2, wherein the first metal layer contains Sn. Appendix 7. 7. The semiconductor device of claim 6, wherein the first intermetallic compound layer has a thickness greater than a thickness of the first metal layer. Appendix 8. 8. 8.
  • Appendix 9. The semiconductor device of claim 8, further comprising a second metal layer interposed between the bonding layer and the first intermediate metal layer and in contact with the first intermediate metal layer.
  • Appendix 10. 10. The semiconductor device of claim 9, wherein the second metal layer contains Ag.
  • Appendix 11. the first lead has a base material and a first plating layer formed on one side of the base material in the thickness direction and in contact with the first intermetallic compound layer; 8. The semiconductor device according to claim 2, wherein the first plating layer contains Cu.
  • Appendix 12. 12 The semiconductor device of claim 11, wherein the substrate contains Fe and Ni. Appendix 13.
  • the semiconductor element has a first electrode disposed on the other side in the thickness direction of the semiconductor layer, the first lead includes a first pad portion on which the semiconductor element is mounted, The semiconductor device according to claim 9 or 10, wherein the first electrode is configured to include the second metal layer and the first intermediate metal layer.
  • Appendix 14 a second lead arranged at a distance from the first lead, and a first bonding wire; the second lead includes a second pad portion located on one side of the first pad portion in a first direction perpendicular to the thickness direction, the semiconductor element has a second electrode disposed on one side in the thickness direction of the semiconductor layer, 14.
  • the third lead includes a third pad portion located on the other side in the first direction with respect to the first pad portion, the semiconductor element has a third electrode disposed on one side in the thickness direction of the semiconductor layer, 15.
  • the second bonding wire is conductively connected to the third electrode and the third pad portion. Appendix 16. 16.

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013099243A1 (ja) * 2011-12-27 2013-07-04 パナソニック株式会社 接合構造体
JP2017103434A (ja) * 2015-12-04 2017-06-08 トヨタ自動車株式会社 半導体装置
JP2018187670A (ja) * 2017-05-11 2018-11-29 パナソニックＩｐマネジメント株式会社 はんだ合金およびそれを用いた接合構造体

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013099243A1 (ja) * 2011-12-27 2013-07-04 パナソニック株式会社 接合構造体
JP2017103434A (ja) * 2015-12-04 2017-06-08 トヨタ自動車株式会社 半導体装置
JP2018187670A (ja) * 2017-05-11 2018-11-29 パナソニックＩｐマネジメント株式会社 はんだ合金およびそれを用いた接合構造体

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