WO2025018065A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2025018065A1
WO2025018065A1 PCT/JP2024/021289 JP2024021289W WO2025018065A1 WO 2025018065 A1 WO2025018065 A1 WO 2025018065A1 JP 2024021289 W JP2024021289 W JP 2024021289W WO 2025018065 A1 WO2025018065 A1 WO 2025018065A1
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Prior art keywords
trench
region
semiconductor device
contact
main surface
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2025533909A priority Critical patent/JPWO2025018065A1/ja
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  • This disclosure relates to a semiconductor device.
  • Patent document 1 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling injection.
  • An embodiment of the present disclosure provides a semiconductor device capable of preventing local current concentration and improving breakdown resistance.
  • a semiconductor device includes a chip having a first main surface and a second main surface on the opposite side thereof, a first impurity region of a first conductivity type formed in a surface layer of the first main surface, a second impurity region of a second conductivity type formed in a surface layer of the first impurity region, a third impurity region of a first conductivity type formed in a surface layer of the second impurity region, a trench extending from the first main surface through the third impurity region and the second impurity region to the first impurity region, a field relaxation structure of a second conductivity type formed at the bottom of the trench, a first contact region formed along one side of the trench from the first main surface toward the second main surface and electrically connected to the second impurity region and the field relaxation structure, and a second contact region formed along the other side of the trench from the first main surface toward the second main surface and electrically connected to the second impurity region and the field relaxation structure, and a plurality of the first impurity region of a
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of a chip layout.
  • FIG. 4 is a perspective view showing an example of a chip layout.
  • FIG. 5 is a plan view showing the active area and trench structure.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is a cross-sectional perspective view corresponding to FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG.
  • FIG. 9 is a cross-sectional perspective view corresponding to FIG. FIG.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG.
  • FIG. 11 is a perspective view showing the configuration of the outer circumferential area.
  • FIG. 12 is a cross-sectional view showing a main part of the outer circumferential region.
  • FIG. 13 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices.
  • FIG. 14 is a flowchart showing an example of a method for manufacturing a semiconductor device.
  • FIG. 15A is a diagram showing an example of a method for manufacturing a semiconductor device.
  • FIG. 15B is a diagram showing a step subsequent to that of FIG. 15A.
  • FIG. 15C is a diagram showing a step subsequent to FIG. 15B.
  • FIG. 15D is a diagram showing a step subsequent to FIG. 15C.
  • FIG. 15A is a diagram showing an example of a method for manufacturing a semiconductor device.
  • FIG. 15B is a diagram showing a step subsequent to that of FIG. 15A.
  • FIG. 15E is a diagram showing a step subsequent to FIG. 15D.
  • FIG. 15F is a diagram showing a step subsequent to FIG. 15E.
  • FIG. 15G is a diagram showing a step subsequent to FIG. 15F.
  • FIG. 16 is a diagram showing a first modification of the semiconductor device.
  • FIG. 17 is a diagram showing a second modification of the semiconductor device.
  • 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 17.
  • FIG. FIG. 19 is a diagram showing a third modification of the semiconductor device.
  • FIG. 20 is a diagram showing a fourth modification of the semiconductor device.
  • FIG. 21 is a diagram showing a fifth modification of the semiconductor device.
  • FIG. 22 is a diagram showing a sixth modification of the semiconductor device.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the “first conductivity type” and “p-type” as the “second conductivity type”.
  • p-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of a chip 2.
  • FIG. 4 is a perspective view showing an example layout of a chip 2.
  • FIG. 5 is a plan view showing a trench structure 16 together with an active region 9.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is a cross-sectional perspective view corresponding to FIG. 6.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is a cross-sectional perspective view corresponding to FIG. 8.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG. 5.
  • semiconductor device 1 includes chip 2 including SiC single crystal.
  • Chip 2 may be referred to as a "SiC chip” or a “semiconductor chip".
  • chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape.
  • Hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the second side 5B is connected to the first side 5A
  • the third side 5C is connected to the second side 5B
  • the fourth side 5D is connected to the first side 5A and the third side 5C.
  • the first side 5A and the third side 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X.
  • the second side 5B and the fourth side 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z.
  • the axis extending along the vertical direction Z may be referred to as the "vertical axis.”
  • the first direction X and the second direction Y may be referred to as the "horizontal direction.”
  • the horizontal direction is also the direction extending along the first main surface 3.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle ⁇ o that is inclined at a predetermined angle in a predetermined off direction Do with respect to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle ⁇ o from the vertical axis toward the off direction Do.
  • the c-plane of the SiC single crystal is inclined by the off angle ⁇ o with respect to the horizontal plane.
  • the off-direction Do is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle ⁇ o may be greater than 0° and less than or equal to 10°.
  • the off-angle ⁇ o may have a value that falls within any one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle ⁇ o is preferably 5° or less. It is particularly preferable that the off angle ⁇ o is 2° or more and 4.5° or less.
  • the off angle ⁇ o is typically set in the range of 4° ⁇ 0.1°. Of course, this specification does not exclude a configuration in which the off angle ⁇ o is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the chip 2 includes an n-type base layer 6 made of SiC single crystal.
  • the base layer 6 may also be referred to as a "drain region,” a “base SiC layer,” a “base region,” etc.
  • the base layer 6 extends in a layered manner in the horizontal direction and forms part of the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the base layer 6 is made of a substrate made of SiC single crystal (i.e., a SiC substrate).
  • the base layer 6 has the off-direction Do and off-angle ⁇ o described above.
  • the base layer 6 may have a peak n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the base layer 6 preferably has an almost constant n-type impurity concentration in the thickness direction.
  • the n-type impurity concentration of the base layer 6 is preferably adjusted by a single type of pentavalent element. It is particularly preferable that the n-type impurity concentration of the base layer 6 is adjusted by a pentavalent element other than phosphorus. In this embodiment, the n-type impurity concentration of the base layer 6 is adjusted by nitrogen.
  • the base layer 6 has a first thickness T1.
  • the first thickness T1 may be 5 ⁇ m or more and 300 ⁇ m or less.
  • the first thickness T1 may have a value belonging to any one of the following ranges: 5 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, and 250 ⁇ m or more and 300 ⁇ m or less.
  • the first thickness T1 is preferably 50 ⁇ m or more and 250 ⁇ m or less.
  • the chip 2 includes a semiconductor layer 7 made of single crystal SiC stacked on the base layer 6.
  • the semiconductor layer 7, which is an example of a first impurity region, may be referred to as a "drift region,” "SiC layer,” “semiconductor region,” etc.
  • the semiconductor layer 7 extends in a layered manner in the horizontal direction and forms part of the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the semiconductor layer 7 has a lower end and an upper end.
  • the lower end of the semiconductor layer 7 is the starting point of crystal growth, and the upper end of the semiconductor layer 7 is the end point of crystal growth.
  • the lower end of the semiconductor layer 7 is also the bottom of the semiconductor layer 7. Since the semiconductor layer 7 is grown continuously from the base layer 6, the lower end of the semiconductor layer 7 coincides with the upper end of the base layer 6.
  • the semiconductor layer 7 includes an n-type drift region 8.
  • the drift region 8 is formed by a portion (n-type portion) of the semiconductor layer 7. More specifically, the drift region 8 is formed by a portion of the semiconductor layer 7 on the second main surface 4 side relative to the body region 15 (described later) and the electric field relaxation structure 21 (described later) in the vertical direction Z.
  • the boundary between the base layer 6 and the semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and/or determined from other configurations and elements.
  • the semiconductor layer 7 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and off-angle ⁇ o of the base layer 6.
  • the n-type impurity concentration of the semiconductor layer 7 (drift region 8) is preferably lower than the n-type impurity concentration of the base layer 6.
  • the semiconductor layer 7 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the semiconductor layer 7 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the semiconductor layer 7 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the n-type impurity concentration of the semiconductor layer 7 is adjusted by nitrogen.
  • the semiconductor layer 7 may have an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the semiconductor layer 7 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the semiconductor layer 7 contains a pentavalent element other than phosphorus.
  • the semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1.
  • the second thickness T2 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 may have a value that belongs to any one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, and 8 ⁇ m or more and 10 ⁇ m or less.
  • the second thickness T2 is preferably 2 ⁇ m or more and 8 ⁇ m or less.
  • the semiconductor device 1 includes an active region 9 set in the chip 2.
  • the active region 9 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 9 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 9 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1 includes a peripheral region 10 that is set outside the active region 9 in the chip 2.
  • the peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a planar view.
  • the peripheral region 10 extends in a band shape along the active region 9 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.
  • the semiconductor device 1 includes an active surface 11 formed on the first main surface 3, an outer surface 12, and first to fourth connecting surfaces 13A to 13D.
  • the active surface 11, outer surface 12, and first to fourth connecting surfaces 13A to 13D define an active plateau 14 on the first main surface 3.
  • the active surface 11 may be referred to as the "first surface portion,” the outer peripheral surface 12 as the “second surface portion,” the first to fourth connection surfaces 13A to 13D as the “connection surface portion,” and the active plateau 14 as the “active mesa portion.”
  • the active surface 11, the outer peripheral surface 12, and the first to fourth connection surfaces 13A to 13D may be considered to be components of the chip 2 (first main surface 3).
  • the active surface 11 is formed in the active region 9. That is, the active surface 11 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 11 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 11 is formed by a c-plane (Si-plane).
  • the active surface 11 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 12 is formed in the outer peripheral region 10. That is, the outer peripheral surface 12 is formed outside the active surface 11.
  • the outer peripheral surface 12 is recessed in the thickness direction of the chip 2 (towards the second main surface 4) relative to the active surface 11. Specifically, in this embodiment, the outer peripheral surface 12 is recessed to a depth less than the thickness of the semiconductor layer 7 so as to expose the semiconductor layer 7. That is, the outer peripheral surface 12 faces the base layer 6 with a portion of the semiconductor layer 7 in between, exposing the semiconductor layer 7.
  • the outer peripheral surface 12 extends in a band shape along the active surface 11 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 11.
  • the outer peripheral surface 12 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 11.
  • the outer peripheral surface 12 is formed by a c-plane (Si-plane).
  • the outer peripheral surface 12 is connected to the first to fourth side surfaces 5A to 5D.
  • the outer peripheral surface 12 has an outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the first to fourth connection surfaces 13A to 13D extend in the vertical direction Z and connect the active surface 11 and the outer peripheral surface 12.
  • the first connection surface 13A is located on the first side surface 5A side
  • the second connection surface 13B is located on the second side surface 5B side
  • the third connection surface 13C is located on the third side surface 5C side
  • the fourth connection surface 13D is located on the fourth side surface 5D side.
  • the first connection surface 13A and the third connection surface 13C extend in the first direction X and face the second direction Y.
  • the second connection surface 13B and the fourth connection surface 13D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 13A to 13D may extend approximately vertically between the active surface 11 and the outer peripheral surface 12 so as to define a quadrangular prism-shaped active plateau 14.
  • the first to fourth connection surfaces 13A to 13D may be inclined obliquely downward from the active surface 11 toward the outer peripheral surface 12 so as to define a quadrangular pyramid-shaped active plateau 14.
  • the active plateau 14 is defined in a protruding shape on the semiconductor layer 7 at the first main surface 3.
  • the active plateau 14 is formed only on the semiconductor layer 7, and is not formed on the base layer 6.
  • the semiconductor device 1 includes a p-type body region 15 formed in a surface layer portion of the first main surface 3 (active surface 11).
  • the body region 15, which is an example of a second impurity region, is formed in a layer extending along the active surface 11.
  • the body region 15 may be formed over the entire active surface 11 and exposed from the first to fourth connection surfaces 13A to 13D.
  • the body region 15 is formed at a distance from the lower end of the semiconductor layer 7 toward the active surface 11. It is preferable that the body region 15 is formed at a distance from the depth position of the outer peripheral surface 12 toward the active surface 11 and exposed from the active surface 11.
  • the body region 15 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the body region 15 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the body region 15 may be at least one of boron, aluminum, gallium, and indium.
  • the semiconductor device 1 includes a plurality of trench electrode type trench structures 16 formed on the first main surface 3 (active surface 11) in the active region 9.
  • the trench structures 16 may be referred to as "gate structures", “trench gate structures”, etc.
  • a gate potential is applied to the plurality of trench structures 16 as a control potential.
  • the plurality of trench structures 16 control the inversion and non-inversion of the channel (current path) in the body region 15 in response to the gate potential.
  • the multiple trench structures 16 are arranged at intervals inward from the periphery (first to fourth connection surfaces 13A to 13D) of the active surface 11 in the active region 9.
  • the multiple trench structures 16 are arranged at intervals in the first direction X, and are each formed in a strip shape extending in the second direction Y.
  • the multiple trench structures 16 are arranged at intervals in the m-axis direction and each extends in the a-axis direction.
  • the multiple trench structures 16 are arranged in stripes extending in the a-axis direction (second direction Y).
  • the extension direction of the multiple trench structures 16 coincides with the off-direction Do of the semiconductor layer 7.
  • the multiple trench structures 16 are formed at intervals from the lower end (base layer 6) of the semiconductor layer 7 toward the first main surface 3 (active surface 11), and face the base layer 6 with a portion of the semiconductor layer 7 in between.
  • the multiple trench structures 16 define a lower region 7a in the region between the bottom walls of the multiple trench structures 16 and the lower end (base layer 6) of the semiconductor layer 7.
  • Each trench structure 16 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z.
  • the trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the trench width WT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench width WT may have a value falling within any one of the following ranges: 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the trench depth DT is preferably less than the second thickness T2 of the semiconductor layer 7. It is particularly preferable that the trench depth DT is approximately equal to the aforementioned outer periphery depth DO. Of course, the trench depth DT may be greater than or less than the outer periphery depth DO.
  • each of the trench structures 16 preferably has an aspect ratio DT/WT that extends in a vertically elongated columnar shape.
  • the aspect ratio DT/WT is the ratio of the trench width WT to the trench depth DT.
  • the aspect ratio DT/WT may be, for example, 1 to 5, and is preferably 1 to 3.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, and 4 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less, and more preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple trench structures 16 are arranged in the first direction X at intervals of the trench pitch PT.
  • the trench pitch PT is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the trench pitch PT is preferably less than the trench depth DT.
  • the trench pitch PT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench pitch PT may have a value in any one of the ranges of 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the trench pitch PT is preferably 0.5 ⁇ m to 3 ⁇ m, and more preferably 0.5 ⁇ m to 1.5 ⁇ m.
  • Each trench structure 16 includes a trench 17, an insulating film 18, and a buried electrode 19.
  • the trench 17 is formed in the active surface 11 and defines the walls (side walls and bottom wall) of the trench structure 16.
  • the bottom wall of the trench 17 preferably has a flat portion.
  • a mesa portion 20 formed by a part of the semiconductor layer 7 is formed between adjacent trenches 17.
  • the mesa portion 20 may be referred to as an "element mesa portion.”
  • the multiple trenches 17 and multiple mesa portions 20 are in the form of stripes extending along the second direction Y, and are arranged alternately in the first direction X.
  • the multiple trenches 17 and multiple mesa portions 20 are arranged in a stripe pattern as a whole.
  • the flat portion of the bottom wall of trench 17 extends approximately parallel to first main surface 3.
  • the bottom wall of trench 17 has an off angle ⁇ o that is inclined at a predetermined angle in a predetermined off direction Do relative to the c-plane.
  • the bottom wall of trench 17 has a flat portion that extends in the off direction Do.
  • the bottom wall of trench 17 may be curved in an arc shape toward the lower end side of semiconductor layer 7.
  • the insulating film 18 covers the wall surface of the trench 17.
  • the insulating film 18 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 18 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 18 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 19 is buried in the trench 17 and faces the channel across the insulating film 18. In this embodiment, the buried electrode 19 faces the body region 15 across the insulating film 18.
  • the buried electrode 19 may include p-type or n-type conductive polysilicon.
  • the semiconductor device 1 includes a plurality of p-type electric field relaxation structures 21 formed at intervals in the horizontal direction in the semiconductor layer 7. Specifically, the plurality of electric field relaxation structures 21 are formed in the lower region 7a in the semiconductor layer 7. The plurality of electric field relaxation structures 21 are formed in the thickness range between the lower end of the semiconductor layer 7 and the bottom walls of the plurality of trench structures 16.
  • the electric field relaxation structures 21 are arranged at intervals in the first direction X in the lower region 7a, and are each formed in a strip shape extending in the second direction Y. In other words, the electric field relaxation structures 21 are arranged at intervals in the m-axis direction and extend in the a-axis direction of the SiC single crystal. The electric field relaxation structures 21 are formed in stripes extending in the a-axis direction (second direction Y), and the extension direction of the electric field relaxation structures 21 coincides with the off-direction Do of the semiconductor layer 7.
  • the multiple electric field relaxation structures 21 overlap the multiple trench structures 16 in the stacking direction. Specifically, the multiple electric field relaxation structures 21 overlap the multiple trench structures 16 in a one-to-one correspondence in the stacking direction.
  • the multiple electric field relaxation structures 21 are formed in the active region 9 at intervals inward from the periphery of the active surface 11 (first to fourth connection surfaces 13A to 13D).
  • each electric field relaxation structure 21 is each connected to the bottom wall of the corresponding trench structure 16. As a result, the upper end of the electric field relaxation structure 21 is exposed at the bottom wall of the trench structure 16 (trench 17). Specifically, each electric field relaxation structure 21 has a side surface 22 that is flush with both side surfaces of the trench 17 in the depth direction of the trench structure 16. The side surface 22 of the electric field relaxation structure 21 extends in the depth direction of the trench structure 16 and forms a boundary surface with the semiconductor layer 7 (lower region 7a). Therefore, the electric field relaxation structure 21 is physically separated from the body region 15 in the depth direction of the trench structure 16, and forms the entire bottom wall of the trench structure 16.
  • both ends of the multiple electric field relaxation structures 21 may be located on the peripheral side of the active region 9 with respect to both ends of the multiple trench structures 16, as shown in FIG. 12. Both ends of the multiple electric field relaxation structures 21 may be located on the inner side of the active region 9 with respect to both ends of the multiple trench structures 16.
  • the electric field relaxation structures 21 are arranged at intervals of the relaxation pitch PR in the first direction X.
  • the relaxation pitch PR may be the same as the trench pitch PT.
  • the relaxation pitch PR may have a value belonging to any one of the following ranges: 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the relaxation pitch PR is preferably 0.5 ⁇ m to 3.0 ⁇ m.
  • the p-type impurity concentration of the electric field relaxation structure 21 is preferably higher than the p-type impurity concentration of the body region 15.
  • the electric field relaxation structure 21 may have a peak p-type impurity concentration of 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less.
  • the p-type impurity concentration of the electric field relaxation structure 21 may be approximately constant in the thickness direction.
  • the p-type impurity concentration of the electric field relaxation structure 21 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the electric field relaxation structure 21 has a relaxation depth DR in the vertical direction Z that is greater than that of the trench 17. More preferably, the relaxation depth DR of the electric field relaxation structure 21 is at least twice the trench depth DT. Of course, the relaxation depth DR may be less than twice the trench depth DT.
  • the relaxation depth DR may have a value in any one of the following ranges: greater than 0.25 ⁇ m and equal to or less than 0.5 ⁇ m, equal to or greater than 0.5 ⁇ m and equal to or less than 1 ⁇ m, equal to or greater than 1.5 ⁇ m, equal to or greater than 1.5 ⁇ m and equal to or less than 2 ⁇ m, equal to or greater than 2 ⁇ m and equal to or less than 3 ⁇ m, equal to or greater than 3 ⁇ m and equal to or less than 4 ⁇ m, and equal to or greater than 4 ⁇ m and equal to or less than 5 ⁇ m.
  • the relaxation depth DR is preferably equal to or greater than 2 ⁇ m and equal to or less than 3 ⁇ m, in which case the trench depth DT is preferably equal to or greater than 0.5 ⁇ m and equal to or less than 1.5 ⁇ m.
  • the electric field relaxation structures 21 each have a relaxation width WR in the arrangement direction.
  • the relaxation width WR may be 0.25 ⁇ m or more and 5 ⁇ m or less.
  • the relaxation width WR may have a value that falls within any one of the following ranges: 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor device 1 includes a plurality of contact regions 34A, 34B formed in the surface portion of the first main surface 3 (active surface 11) in the region between the plurality of trench structures 16.
  • the plurality of contact regions 34A, 34B are regions physically separated from each other, and both are formed in the surface portion of the body region 15.
  • the plurality of contact regions 34A, 34B have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the body region 15.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of electric field relaxation structures 21.
  • the plurality of contact regions 34A, 34B may have a p-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the plurality of contact regions 34 includes a plurality of first contact regions 34A and a plurality of second contact regions 34B.
  • the first contact regions 34A are selectively formed on one of the two side surfaces of each trench 17 and are arranged at intervals in the second direction Y.
  • Each first contact region 34A extends along one sidewall of each trench 17 in the depth direction of each trench 17 from the first main surface 3 to the second main surface 4, and is electrically connected to the body region 15 and the electric field relaxation structure 21.
  • each first contact region 34A integrally comprises a first portion 23, a second portion 24, and a third portion 25, each of which extends in a different direction.
  • the first portion 23 is a portion that extends in the depth direction of the trench 17 (i.e., the vertical direction Z)
  • the second portion 24 is a portion that extends in a horizontal direction (in this embodiment, the first direction X) perpendicular to the vertical direction
  • the third portion 25 is a portion that extends in the horizontal direction (in this embodiment, the first direction X) and on the opposite side to the second portion 24.
  • the first portion 23 of the first contact region 34A extends along one side of the trench 17 from the first major surface 3 toward the second major surface 4.
  • the first portion 23 is formed throughout the entire depth direction of the trench 17 from the top to the bottom of the trench 17.
  • the first portion 23 has a lower end near the bottom of the trench 17 and an upper end near the top of the trench 17.
  • the first portion 23 penetrates the body region 15 and spans between the body region 15 and the electric field relaxation structure 21, which are separated from each other.
  • the second portion 24, and the third portion 25 at least the first portion 23 forms a boundary with the body region 15 and is connected to the body region 15.
  • the first portion 23 is also connected to the semiconductor layer 7 (drift region 8) below the body region 15.
  • a pn junction is formed between the first contact region 34A and the drift region 8 between the body region 15 and the electric field relaxation structure 21.
  • the first portion 23 is exposed from the side of the trench 17 and contacts the insulating film 18 at the side of the trench 17. The lower end of the first portion 23 may contact the side 22 of the electric field relaxation structure 21.
  • the second portion 24 of the first contact region 34A extends from one side of the trench 17 toward the inside of the trench 17 in the width direction along the bottom surface of the trench 17.
  • the second portion 24 penetrates the side surface 22 of the electric field relaxation structure 21 from the lower end of the first portion 23 and is formed on the bottom wall of the trench 17 halfway in the width direction of the trench 17.
  • the second portion 24 has an end portion in the horizontal direction, approximately at the center of the width direction of the trench 17.
  • the second portion 24 forms a boundary with the electric field relaxation structure 21 and is connected to the electric field relaxation structure 21.
  • the second portion 24 is exposed from the bottom surface of the trench 17 and contacts the insulating film 18 at the bottom surface of the trench 17. Therefore, on the side and bottom surface of the trench 17, the first contact region 34A, which is L-shaped in cross section and formed by integrating the first portion 23 and the second portion 24, partially covers the buried electrode 19 via the insulating film 18.
  • the third portion 25 of the first contact region 34A extends along the first main surface 3 from one side of the trench 17 toward the outer side of the trench 17 in the width direction (the side opposite to the extension direction of the second portion 24).
  • the third portion 25 is formed on the top wall of the mesa portion 20 from the upper end of the first portion 23 to the middle of the mesa portion 20 in the width direction.
  • the third portion 25 has an end in the horizontal direction, approximately at the center of the width direction of the mesa portion 20.
  • the third portion 25 is exposed from the first main surface 3.
  • the first contact region 34A which is approximately Z-shaped in cross section and is formed by integrating the first portion 23, the second portion 24 and the third portion 25, partially covers the buried electrode 19 via the insulating film 18 and is exposed from the first main surface 3 for contact.
  • the first portion 23 has a first thickness T1A.
  • the first thickness T1A may be the thickness of the first portion 23 in the horizontal direction from the side of the trench 17.
  • the first thickness T1A may be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less.
  • the second portion 24 has a second thickness T2A.
  • the second thickness T2A may be the thickness of the second portion 24 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the second thickness T2A is greater than the first thickness T1A.
  • the second thickness T2A may be, for example, 100 nm or more and 700 nm or less, preferably 200 nm or more and 500 nm or less.
  • the third portion 25 has a third thickness T3A.
  • the third thickness T3A may be the thickness of the third portion 25 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the third thickness T3A is greater than the first thickness T1A.
  • the third thickness T3A may be approximately the same as the second thickness T2A.
  • the third thickness T3A may be, for example, 100 nm or more and 700 nm or less, preferably 200 nm or more and 500 nm or less.
  • the first portion 23, the second portion 24, and the third portion 25 of the first contact region 34A have the same width WA in the longitudinal direction of the trench 17.
  • the first contact region 34A is formed in a quadrangular shape (in this embodiment, a rectangular shape) in a plan view.
  • the second contact regions 34B are selectively formed on the other of the two side surfaces of each trench 17 and are arranged at intervals in the second direction Y.
  • Each second contact region 34B extends along the other sidewall of each trench 17 in the depth direction of each trench 17 from the first main surface 3 toward the second main surface 4, and is electrically connected to the body region 15 and the electric field relaxation structure 21.
  • each second contact region 34B integrally comprises a first portion 26, a second portion 27, and a third portion 28, each of which extends in a different direction.
  • the first portion 26 is a portion that extends in the depth direction of the trench 17 (i.e., the vertical direction Z)
  • the second portion 27 is a portion that extends in a horizontal direction (first direction X in this embodiment) perpendicular to the vertical direction
  • the third portion 28 is a portion that extends in the horizontal direction (first direction X in this embodiment) and on the opposite side to the second portion 27.
  • the first portion 26 of the second contact region 34B extends along the other side of the trench 17 from the first major surface 3 toward the second major surface 4.
  • the first portion 26 is formed throughout the entire depth direction of the trench 17 from the top to the bottom of the trench 17.
  • the first portion 26 has a lower end near the bottom of the trench 17 and an upper end near the top of the trench 17.
  • the first portion 26 penetrates the body region 15 and spans between the body region 15 and the electric field relaxation structure 21, which are separated from each other.
  • the second portion 27, and the third portion 28 at least the first portion 26 forms a boundary with the body region 15 and is connected to the body region 15.
  • the first portion 26 is also connected to the semiconductor layer 7 (drift region 8) below the body region 15.
  • drift region 8 below the body region 15.
  • a pn junction is formed between the second contact region 34B and the drift region 8 between the body region 15 and the electric field relaxation structure 21.
  • the first portion 26 is exposed from the side of the trench 17 and contacts the insulating film 18 at the side of the trench 17.
  • the lower end of the first portion 26 may contact the side 22 of the electric field relaxation structure 21.
  • the third portion 28 of the second contact region 34B extends along the first main surface 3 from the other side of the trench 17 toward the outer side of the trench 17 in the width direction (the side opposite to the extension direction of the second portion 27).
  • the third portion 28 is formed on the top wall of the mesa portion 20 from the upper end of the first portion 26 to the middle of the mesa portion 20 in the width direction.
  • the third portion 28 has an end in the horizontal direction, approximately at the center of the width direction of the mesa portion 20. The third portion 28 is exposed from the first main surface 3.
  • the second contact region 34B which is approximately Z-shaped in cross section and is formed by integrating the first portion 26, the second portion 27 and the third portion 28, partially covers the buried electrode 19 via the insulating film 18 and is exposed from the first main surface 3 for contact.
  • the first portion 26 has a first thickness T1B.
  • the first thickness T1B may be the thickness of the first portion 26 in the horizontal direction from the side of the trench 17.
  • the first thickness T1B may be, for example, 10 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less.
  • the second portion 27 has a second thickness T2B.
  • the second thickness T2B may be the thickness of the second portion 27 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the second thickness T2B is greater than the first thickness T1B.
  • the second thickness T2B may be, for example, 100 nm or more and 700 nm or less, preferably 200 nm or more and 500 nm or less.
  • the third portion 28 has a third thickness T3B.
  • the third thickness T3B may be the thickness of the third portion 28 in the vertical direction Z from the bottom surface of the trench 17. In this embodiment, the third thickness T3B is greater than the first thickness T1B.
  • the third thickness T3B may be approximately the same as the second thickness T2B.
  • the third thickness T3B may be, for example, 100 nm or more and 700 nm or less, preferably 200 nm or more and 500 nm or less.
  • the first portion 26, the second portion 27, and the third portion 28 of the second contact region 34B have the same width WB in the longitudinal direction of the trench 17.
  • the second contact region 34B is formed in a quadrangular shape (in this embodiment, a rectangular shape) in a plan view.
  • the first contact regions 34A and the second contact regions 34B are arranged at intervals in the longitudinal direction of the trenches 17.
  • the first contact regions 34A are uniformly arranged on one side of the width of each of the trenches 17 throughout the trenches 17.
  • the second contact regions 34B are uniformly arranged on the other side of the length of each of the trenches 17 throughout the trenches 17.
  • the first contact regions 34A are formed on one side of the width of all of the trenches 17, and the second contact regions 34B are formed on the other side.
  • the first contact regions 34A and the second contact regions 34B are arranged alternately at intervals in each mesa portion 20.
  • the second contact region 34B of one of the pair of trenches 17A, 17B among the plurality of trenches 17 is arranged at a position adjacent to the first direction X (width direction of the trench 17) to the region 29 between the first contact regions 34A of one of the pair of trenches 17A, 17B of the other trench 17.
  • the first contact region 34A of one of the trenches 17B is arranged at a position adjacent to the first direction X (width direction of the trench 17) to the region 30 between the second contact regions 34B of the other trench 17B.
  • the first contact regions 34A and the second contact regions 34B are arranged in a staggered pattern in a plan view as a whole.
  • the body region 15 includes a channel portion 31 and a non-channel portion 32.
  • the channel portion 31 is a region in the body region 15 where the multiple contact regions 34A, 34B are not formed.
  • the regions 29 and 30 are the channel portion 31.
  • a channel is formed along the wall surface of the trench 17 adjacent to the channel portion 31.
  • the non-channel portion 32 the wall surface of the adjacent trench 17 is covered with the contact regions 34A, 34B from the top to the bottom of the trench 17.
  • the semiconductor device 1 includes a source region 33 formed in a region between the multiple trench structures 16 in the surface layer portion of the first main surface 3 (active surface 11).
  • the source region 33 which is an example of a third impurity region, is formed in the surface layer portion of the body region 15.
  • the source region 33 is formed in a region in the mesa portion 20 where the multiple contact regions 34A, 34B are not formed.
  • the first contact regions 34A and the second contact regions 34B are arranged alternately at intervals from one another in the length direction of the trench 17.
  • the region in the body region 15 where the source region 33 is formed is the aforementioned channel portion 31.
  • the source region 33 passes between the multiple first contact regions 34A and the multiple second contact regions 34B arranged alternately from one another in the left to right, and is formed in a zigzag shape in the second direction Y.
  • a plurality of first channel sections 35 and a plurality of second channel sections 36 are alternately arranged in the second direction Y (the length direction of the trench 17).
  • the first channel section 35 is a channel portion 31 corresponding to the region 29
  • the second channel section 36 is a channel portion 31 corresponding to the region 30.
  • the first channel section 35 and the second channel section 36 may have an overlapping channel section 49 that overlaps in the first direction X.
  • a channel is formed on both wall surfaces of the trench 17 on both sides of the mesa portion 20 in the first direction X.
  • the source region 33 has a higher n-type impurity concentration (peak value) than the semiconductor layer 7.
  • the source region 33 may have an n-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the source regions 33 are formed at intervals from the bottom of the body region 15 toward the active surface 11, and face the drift region 8 directly below, sandwiching a part of the body region 15 in the vertical direction Z.
  • Figure 11 is a perspective view showing the configuration of the outer peripheral region 10.
  • Figure 12 is a cross-sectional view showing a main part of the outer peripheral region 10.
  • the well region 37 is pulled out from the surface portion of the outer peripheral surface 12 toward the first to fourth connection surfaces 13A to 13D and extends along the surface portions of the first to fourth connection surfaces 13A to 13D.
  • the well region 37 is electrically connected to the body region 15 at the surface portion of the active surface 11.
  • the well region 37 is formed at a distance from the lower end of the semiconductor layer 7 towards the outer circumferential surface 12, and faces the base layer 6 across a part of the semiconductor layer 7.
  • the well region 37 forms a pn junction with the semiconductor layer 7.
  • the well region 37 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the well region 37 has a p-type impurity concentration lower than the p-type impurity concentrations of the multiple contact regions 34A, 34B.
  • the p-type impurity concentration of the well region 37 may be higher than the p-type impurity concentration of the body region 15. Of course, the p-type impurity concentration of the well region 37 may be lower than the body region 15. It is preferable that the p-type impurity concentration of the well region 37 is adjusted by at least one kind of trivalent element.
  • the trivalent element of the well region 37 may be the same kind as the trivalent element of the electric field relaxation structure 21, or may be a different kind from the trivalent element of the electric field relaxation structure 21.
  • the trivalent element of the well region 37 may be at least one kind of boron, aluminum, gallium, and indium.
  • the semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 12 (first main surface 3) in the outer peripheral region 10.
  • the number of the multiple field regions 38 is typically 4 to 8.
  • the multiple field regions 38 are formed in an electrically floating state, and relieve the electric field within the chip 2 at the periphery of the first main surface 3.
  • the number, width, depth, p-type impurity concentration, etc. of the field regions 38 are arbitrary and can take various values depending on the electric field to be relieved.
  • the multiple field regions 38 are formed in a band shape extending along the active region 9 in a planar view.
  • the multiple field regions 38 each have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 38 are formed in a ring shape (specifically, a square ring shape) surrounding the active region 9 (i.e., the multiple electric field relaxation structures 21) in a planar view.
  • the multiple field regions 38 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer circumferential surface 12, and form a pn junction with the semiconductor layer 7. It is preferable that the multiple field regions 38 have a bottom portion located on the outer circumferential surface 12 side relative to the intermediate portion of the thickness range of the semiconductor layer 7.
  • the multiple field regions 38 are formed at intervals from the electric field relaxation structure 21 toward the peripheral edge of the chip 2. Therefore, the multiple field regions 38 do not face the electric field relaxation structure 21 in the vertical direction Z.
  • the multiple field regions 38 are located closer to the second main surface 4 of the semiconductor layer 7 than the bottom wall of the trench structure 16.
  • the bottoms of the multiple field regions 38 may be located closer to the first main surface 3 of the semiconductor layer 7 than the depth position of the bottom of the electric field relaxation structure 21.
  • the bottoms of the multiple field regions 38 may be located closer to the second main surface 4 of the semiconductor layer 7 than the depth position of the bottom of the electric field relaxation structure 21.
  • the plurality of field regions 38 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 15.
  • the p-type impurity concentration of the plurality of field regions 38 may be higher than the p-type impurity concentration of the body region 15.
  • the p-type impurity concentration of the plurality of field regions 38 may be lower than the p-type impurity concentration of the body region 15.
  • the p-type impurity concentration of the multiple field regions 38 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the field region 38 may be the same type as the trivalent element of the electric field relaxation structure 21, or may be a different type from the trivalent element of the electric field relaxation structure 21.
  • the trivalent element of the field region 38 may be at least one type of boron, aluminum, gallium, and indium.
  • the multiple field regions 38 preferably have a width different from the relaxation width WR of the electric field relaxation structure 21.
  • the electric field relaxation effect of the field region 38 is preferably adjusted separately from the multiple electric field relaxation structures 21. It is particularly preferable that the width of the multiple field regions 38 is smaller than the relaxation width WR.
  • the width of the multiple field regions 38 may be larger than the relaxation width WR.
  • the width of the multiple field regions 38 may be approximately equal to the relaxation width WR.
  • the multiple field regions 38 are preferably formed at a pitch different from the relaxation pitch PR of the electric field relaxation structure 21. It is particularly preferable that the pitch of the multiple field regions 38 is smaller than the relaxation pitch PR. The pitch of the multiple field regions 38 may be larger than the relaxation pitch PR. The pitch of the multiple field regions 38 may be approximately equal to the relaxation pitch PR.
  • the semiconductor device 1 includes an interlayer insulating film 39 covering the first main surface 3.
  • the interlayer insulating film 39 may be referred to as an "insulating film,” an "interlayer film,” an “intermediate insulating film,” or the like.
  • the interlayer insulating film 39 has a layered structure including a first insulating film 40 and a second insulating film 41.
  • the first insulating film 40 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 40 includes a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).
  • the first insulating film 40 selectively covers the first main surface 3 in the active region 9 and the peripheral region 10. Specifically, the first insulating film 40 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connection surfaces 13A to 13D. The first insulating film 40 is connected to the insulating film 18 in the active surface 11, exposing the buried electrode 19.
  • the first insulating film 40 covers the well region 37 and the multiple field regions 38 on the outer peripheral surface 12.
  • the first insulating film 40 is continuous with the first to fourth side surfaces 5A to 5D.
  • the first insulating film 40 may be formed at a distance inward from the periphery of the outer peripheral surface 12, exposing the semiconductor layer 7 from the periphery of the outer peripheral surface 12.
  • the first insulating film 40 covers the body region 15 and well region 37 on the first to fourth connection surfaces 13A to 13D.
  • the second insulating film 41 is laminated on the first insulating film 40.
  • the second insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 39 preferably includes a silicon oxide film.
  • the second insulating film 41 covers the first main surface 3 in the active region 9 and the peripheral region 10, sandwiching the first insulating film 40 between them. Specifically, the second insulating film 41 selectively covers the active surface 11, the peripheral surface 12, and the first to fourth connection surfaces 13A to 13D, sandwiching the first insulating film 40 between them.
  • the second insulating film 41 covers the multiple trench structures 16 (buried electrodes 19) in the active region 9.
  • the second insulating film 41 covers the well region 37 and multiple field regions 38 in the peripheral region 10, sandwiching the first insulating film 40 between them.
  • the second insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D.
  • the second insulating film 41 may be formed at a distance inward from the periphery of the peripheral surface 12, exposing the periphery of the first main surface 3 together with the first insulating film 40.
  • the semiconductor device 1 includes a plurality of contact openings 42 formed in the interlayer insulating film 39.
  • the plurality of contact openings 42 include a plurality of contact openings 42 (not shown) that expose a plurality of trench structures 16 (buried electrodes 19), and a plurality of contact openings 42 that expose a plurality of source regions 33.
  • the plurality of contact openings 42 for the source regions 33 are formed in the regions between the plurality of adjacent trench structures 16, and expose the plurality of source regions 33 and the plurality of contact regions 34.
  • the semiconductor device 1 includes a sidewall structure 43 disposed in the interlayer insulating film 39 so as to cover at least one of the first to fourth connection surfaces 13A to 13D.
  • the sidewall structure 43 is disposed on the first insulating film 40 and is covered by the second insulating film 41.
  • the sidewall structure 43 reduces the step formed between the active surface 11 and the outer peripheral surface 12.
  • the sidewall structure 43 is formed in a band shape extending along at least one of the first to fourth connection surfaces 13A to 13D.
  • the sidewall structure 43 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 13A to 13D so as to surround the active surface 11 in a plan view.
  • the sidewall structure 43 may have a portion that extends in a film shape along the outer peripheral surface 12, and a portion that extends in a film shape along the first to fourth connection surfaces 13A to 13D.
  • the sidewall structure 43 is formed at a distance from the innermost field region 38 toward the active surface 11, and faces the well region 37 in the horizontal and vertical directions Z, sandwiching the first insulating film 40 therebetween.
  • the sidewall structure 43 may face the body region 15, sandwiching the first insulating film 40 therebetween.
  • the semiconductor device 1 includes a gate pad 44 disposed on the interlayer insulating film 39.
  • the gate pad 44 is an electrode to which a gate potential is applied from the outside.
  • the gate pad 44 may be referred to as a "gate pad electrode", a "first pad electrode”, etc.
  • the gate pad 44 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.
  • the gate pad 44 is disposed on a portion of the interlayer insulating film 39 that covers the active region 9. Specifically, the gate pad 44 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view. The gate pad 44 is disposed in a region close to the center of one side of the active surface 11 (the second connection surface 13B in this embodiment) in a plan view.
  • the gate pad 44 may be disposed in a region along any of the central portions of the first to fourth connection surfaces 13A to 13D.
  • the gate pad 44 may be disposed at any corner of the active surface 11 in a planar view.
  • the gate pad 44 may also be disposed at the central portion of the active surface 11 in a planar view.
  • the gate pad 44 is formed in a quadrangular shape in a planar view.
  • the semiconductor device 1 includes at least one gate wiring 45 (multiple in this embodiment) that is drawn from the gate pad 44 onto the interlayer insulating film 39.
  • the gate wiring 45 may also be referred to as a "wiring", a “wiring electrode”, etc.
  • the multiple gate wirings 45 are arranged on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view.
  • the multiple gate wirings 45 may have a laminated structure including a Ti-based metal film and an Al-based metal film laminated in this order from the interlayer insulating film 39 side.
  • the multiple gate wirings 45 include a first gate wiring 45A and a second gate wiring 45B.
  • the first gate wiring 45A is pulled out from the gate pad 44 toward the first connection surface 13A and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicularly) with a portion (specifically, one end) of the multiple trench structures 16.
  • the first gate wiring 45A penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to one end of the multiple trench structures 16.
  • the second gate wiring 45B is pulled out from the gate pad 44 toward the third connection surface 13C and extends in a line along the periphery of the active surface 11 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple trench structures 16.
  • the second gate wiring 45B penetrates the interlayer insulating film 39 via the multiple contact openings 42 and is electrically connected to the other end of the multiple trench structures 16.
  • the semiconductor device 1 includes a source pad 46 disposed on the interlayer insulating film 39 at a distance from the gate pad 44 and the gate wiring 45.
  • the source pad 46 is an electrode to which a source potential is applied from the outside.
  • the source pad 46 may be referred to as a "source pad electrode", a "second pad electrode”, etc.
  • the source pad 46 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 39 side.
  • the source pad 46 is disposed on the active surface 11 at a distance from the outer peripheral surface 12 in a plan view.
  • the source pad 46 is formed in a polygonal shape having a recess along the gate pad 44 in a plan view.
  • the source pad 46 may also be formed in a square shape in a plan view.
  • the source pad 46 penetrates the interlayer insulating film 39 through a plurality of contact openings 42, and is electrically connected to the body region 15, the plurality of source regions 33, and the plurality of contact regions 34A, 34B. In other words, the source pad 46 is electrically connected to the plurality of electric field relaxation structures 21 through the body region 15 and the plurality of contact regions 34A, 34B.
  • the semiconductor device 1 includes a drain pad 47 covering the second main surface 4.
  • the drain pad 47 is an electrode to which a drain potential is applied from the outside.
  • the drain pad 47 may be referred to as a "drain pad electrode”, a “third pad electrode”, etc.
  • the drain pad 47 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.
  • the drain pad 47 is electrically connected to the multiple drift regions 8 via the base layer 6.
  • the drain pad 47 may cover the entire second main surface 4 so as to be continuous with the periphery of the chip 2 (first to fourth side surfaces 5A to 5D).
  • the drain pad 47 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.
  • the breakdown voltage that can be applied between the source pad 46 and the drain pad 47 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 13 is a schematic diagram showing a wafer 50 used in the manufacture of the semiconductor device 1.
  • the wafer 50 is a substrate for the base layer 6 and contains SiC single crystal.
  • the wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.
  • the first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6.
  • the first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal.
  • the wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Do and off-angle ⁇ o described above.
  • the wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal.
  • the mark 54 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 51 in a plan view.
  • the mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • FIG. 12 an orientation flat extending in the m-axis direction (first direction X) in a plan view is shown.
  • a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like.
  • Each device region 55 is an area corresponding to a semiconductor device 1.
  • Each of the plurality of device regions 55 is set to have a rectangular shape in a plan view.
  • the multiple device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 55 are each set at intervals inward from the periphery of the first wafer main surface 51 in a plan view.
  • the multiple cutting lines 56 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 55.
  • FIG. 14 is a flowchart showing an example of a method for manufacturing the semiconductor device 1.
  • FIG. 15A to FIG. 15G are cross-sectional views showing an example of a method for manufacturing the semiconductor device 1.
  • FIG. 15A to FIG. 15G are cross-sectional views corresponding to FIG. 6.
  • the aforementioned wafer 50 preparation process is carried out (step S1 in FIG. 14).
  • the semiconductor layer 7 formation process is carried out (step S2 in FIG. 14).
  • the semiconductor layer 7 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth.
  • step S3 in FIG. 14 the process of forming the body region 15 is carried out.
  • p-type impurities are introduced into the entire semiconductor layer 7.
  • the body region 15 is formed over the entire surface portion of the semiconductor layer 7.
  • a process for forming the source region 33 is carried out (step S4 in FIG. 14).
  • n-type impurities are selectively introduced into the semiconductor layer 7 (the surface portion of the body region 15).
  • the source region 33 is formed in the surface portion of the body region 15.
  • a process for forming a plurality of trenches 17 is performed.
  • a first mask 60 having a predetermined pattern is formed (step S5 in FIG. 14).
  • the first mask 60 is preferably an inorganic mask (hard mask).
  • the first mask 60 has a plurality of first openings 61 that expose the areas in which the plurality of trenches 17 are to be formed.
  • unnecessary portions of the semiconductor layer 7 are removed by an etching method via the first mask 60.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the etching method is preferably an RIE (Reactive Ion Etching) method.
  • a plurality of trenches 17 are formed at the upper end of the semiconductor layer 7 (step S6 in FIG. 14).
  • an active surface 11, an outer peripheral surface 12, and first to fourth connection surfaces 12A to 12D are formed at the upper end of the semiconductor layer 7.
  • a process for forming a plurality of electric field relaxation structures 21 is carried out while leaving the first mask 60 on the semiconductor layer 7 (step S7 in FIG. 14).
  • p-type impurities are selectively introduced into the semiconductor layer 7 through the first mask 60. This forms an electric field relaxation structure 21 at the bottom of each trench 17.
  • the electric field relaxation structure 21 may be formed by a channeling ion implantation method.
  • the channeling implantation process is performed based on data (information) of the off angle ⁇ o. If it is a channeling implantation process, the electric field relaxation structure 21 can be selectively and easily formed at a deep position in the semiconductor layer 7. If the electric field relaxation structure 21 is formed by a channeling ion implantation method, the electric field relaxation structure 21 may be formed before the body region 15. Then, the first mask 60 is removed.
  • a process for forming the multiple contact regions 34A, 34B is performed.
  • a second mask 62 having a predetermined pattern is formed (step S8 in FIG. 14).
  • the second mask 62 is preferably an inorganic mask (hard mask).
  • the second mask 62 has multiple second openings 63 that expose the regions in which the multiple contact regions 34A, 34B are to be formed.
  • p-type impurities are introduced into the surface layer of the semiconductor layer 7 by ion implantation through the second mask 62, thereby forming a plurality of contact regions 34A, 34B.
  • an oblique implantation is performed at a predetermined angle with respect to the first wafer main surface 51. This allows ions to be implanted into the side of the trench 17 in addition to the first wafer main surface 51 and the bottom of the trench 17.
  • the trench structure 16 has an aspect ratio DT/WT (for example, 1 to 5) that extends in a vertically elongated columnar shape, and the trench depth DT is much larger than the trench width WT.
  • the ion implantation depth from the side of the trench 17 becomes shallow, and in the obtained plurality of contact regions 34A, 34B, the second thickness T2A ⁇ the first thickness T1A, the third thickness T3A, and the second thickness T2B ⁇ the first thickness T1B, the third thickness T3B.
  • a process for forming the buried electrode 19 is performed (step S11 in FIG. 14).
  • This process includes a process for forming a base electrode film on the insulating film 18.
  • the base electrode film includes conductive polysilicon.
  • the base electrode film backfills the multiple trenches 17 and covers the upper end of the semiconductor layer 7.
  • the base electrode film may be formed by a CVD method.
  • unnecessary portions of the buried electrode 19 are removed by an etching method.
  • the unnecessary portions of the buried electrode 19 are removed until the insulating film 18 is exposed.
  • the etching method may be either one or both of a wet etching method and a dry etching method. As a result, multiple buried electrodes 19 are buried in the multiple trenches 17, respectively, and multiple trench structures 16 are formed.
  • the interlayer insulating film 39 may be formed by a CVD method.
  • a plurality of contact openings 42 having a predetermined layout are formed in the interlayer insulating film 39 by an etching method using a mask (not shown) having a predetermined layout.
  • the gate pad 44, gate wiring 45, and source pad 46 are formed by depositing a metal film on the interlayer insulating film 39 by sputtering, and then shaping it into a predetermined layout by etching using a mask (not shown) having a predetermined layout.
  • drain pad 47 is formed by depositing a metal film on the second wafer main surface 52 by a sputtering method.
  • the wafer 50 is then cut along a number of intended cutting lines 56 (step S15 in FIG. 14).
  • the electric field relaxation structure 21 is formed on the bottom wall of the trench 17, it is possible to relax the electric field concentration on the bottom wall of the trench 17 in the trench gate structure related to the MISFET (Metal Insulator Semiconductor Field Effect Transistor).
  • the electric field relaxation structure 21 is connected to the multiple contact regions 34A, 34B, it is possible to fix the electric field relaxation structure 21 to a predetermined potential (in this embodiment, the source potential) via the multiple contact regions 34A, 34B.
  • a predetermined potential in this embodiment, the source potential
  • the source potential for example, by setting the source potential to a ground potential, it is possible to stably relax the electric field concentration on the bottom wall of the trench 17.
  • the channel current is biased toward the other side of each trench 17 in the width direction.
  • the current concentrates on the other side of each trench 17 in the width direction, increasing the number of cases in which breakdown occurs during a short circuit.
  • the channel can be formed evenly and in a balanced manner along the length of the trench 17, preventing current concentration and improving breakdown resistance.
  • FIGS. 16 to 22 are diagrams showing first to sixth modified examples of the semiconductor device 1. Next, the modified examples of the semiconductor device 1 will be described with reference to FIG. 16 to FIG. 22.
  • each electric field relaxation structure 21 may be located at the center in the width direction of the trench 17. More specifically, each electric field relaxation structure 21 is formed integrally with the body region 15 and is formed on one side of the trench 17 in the first direction X. In this embodiment, each electric field relaxation structure 21 extends from a part of the body region 15 between two adjacent trenches 17 downwardly beyond the bottom wall of the trench 17 in the vertical direction Z, and spreads along the horizontal direction along the first main surface 3, overlapping the bottom wall of the trench 17. As a result, each electric field relaxation structure 21 has a substantially L-shaped exposed surface exposed in each trench 17 as the lower part of the side wall of the trench 17 and the bottom wall of the trench 17 that is continuous with the lower part of the side wall.
  • the electric field relaxation structure 21 may integrally have a base portion 57 on the second main surface 4 side of the bottom wall of the trench 17, and a protrusion portion 58 sandwiched between two adjacent trenches 17.
  • the base portion 57 overlaps each trench 17 and crosses the sidewall of each trench 17 in the first direction X.
  • the base portion 57 has an end that protrudes horizontally outward from the region directly below the mesa portion 20.
  • the protrusion portion 58 extends from the base portion 57 along the sidewall of each trench 17 to the inside of the mesa portion 20 and is connected to the bottom of the body region 15.
  • the protrusion portion 58 is formed from the bottom wall of the trench 17 in the vertical direction Z to the body region 15.
  • the multiple first contact regions 34A and the multiple second contact regions 34B penetrate the body region 15 and the protrusion 58 in the vertical direction Z, and are further connected to the base portion 57.
  • multiple electric field relaxation structures 21 may be arranged at intervals in the second direction Y.
  • the electric field relaxation structure 21 corresponding to the second contact region 34B may be formed on the other side of the trench 17 in the first direction X (i.e., the opposite side of the trench 17 from the electric field relaxation structure 21 in FIG. 16). This allows the second contact region 34B to be connected to the protrusion 58 and base 57 of the electric field relaxation structure 21.
  • multiple contact regions 34A, 34B for contacting the electric field relaxation structure 21 are arranged separately on one side and the other side of each trench 17 in the width direction (only the first contact region 34 is shown in FIG. 16). This allows channels to be formed evenly in the length direction of the trench 17, making it possible to evenly balance the current during a short circuit. As a result, partial current concentration in the mesa portion 20 can be prevented, and the breakdown resistance can be improved.
  • a first contact region 34A formed along the side of one of a pair of trenches 17A, 17B among the multiple trenches 17 and a second contact region 34B formed along the side of the other trench 17B may be integrated to form one contact region 59 spanning one trench 17A and the other trench 17B.
  • Figures 17 and 18 show one each of reference symbols "17A" and "17B" as an example, the pair of trenches 17A, 17B may be selected from any pair of trenches 17.
  • the contact regions 59 are arranged in a staggered pattern in plan view.
  • a pair of the multiple mesas 20 in the first direction X is defined as a first mesa 20A and a second mesa 20B.
  • first contact regions are arranged at intervals in the extension direction of the trench structure 16.
  • second contact regions are arranged at intervals in the extension direction of the trench structure 16.
  • the multiple contact regions 59A and multiple contact regions 59B are arranged so as not to overlap each other in the first direction X.
  • the multiple contact regions 59A and multiple contact regions 59B are arranged in a staggered pattern as a whole.
  • the region where the multiple contact regions 59 are not formed is a channel section 64.
  • the channel section 64 is a region that has a constant width in the second direction Y.
  • the region where the multiple contact regions 59 are formed is a non-channel section 65.
  • the non-channel section 65 is a region that has a constant width in the second direction Y.
  • the channel sections 64 and non-channel sections 65 are arranged alternately in the extension direction of the trench structure 16.
  • channel sections 64 and non-channel sections 65 are arranged alternately on both sides of each trench 17. This allows channels to be formed evenly in the longitudinal direction of the trench 17, making it possible to equalize the current balance during a short circuit. As a result, partial current concentration in the mesa portion 20 can be prevented, and breakdown resistance can be improved.
  • each electric field relaxation structure 21 does not need to be a flat surface in the vertical direction Z from the side surface of the trench 17, and may have a bulge portion 66 that bulges in the horizontal direction (at least one of the first direction X and the second direction Y).
  • the element structure of the semiconductor device 1 may be an IGBT (Insulated Gate Bipolar Transistor) structure, unlike the MISFET structure of FIGS. 6 to 10.
  • a p-type collector region 71 may be formed instead of the base layer 6.
  • a p-type base region 72 may be formed by the body region 15, and an n-type emitter region 73 may be formed by the source region 33.
  • multiple contact regions 34A, 34B for contacting the electric field relaxation structure 21 are arranged separately on one side and the other side of each trench 17 in the width direction (only the first contact region 34 is shown in FIG. 20). This allows channels to be formed evenly in the length direction of the trench 17, making it possible to equalize the current balance when the IGBT is short-circuited. As a result, partial current concentration in the mesa portion 20 can be prevented, and the breakdown resistance can be improved.
  • the first contact regions 34A and the second contact regions 34B do not have to be arranged one by one in the second direction Y, alternating left and right with spaces between them.
  • they may be arranged multiple by multiple (two by two in FIG. 21) in alternating left and right with spaces between them, or they may be arranged alternately without spaces between them in the second direction Y, as shown in FIG. 22.
  • the base layer 6 and the semiconductor layer 7 each contain a SiC single crystal.
  • at least one or all of the base layer 6 and the semiconductor layer 7 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6 and the semiconductor layer 7 may be made of the same type of single crystal, or may be made of different types of single crystal. At least one or all of the base layer 6 and the semiconductor layer 7 may be made of silicon (Si).
  • semiconductor device in the following items may be replaced with "SiC semiconductor device,” “wide band gap semiconductor device,” “semiconductor switching device,” “semiconductor rectifier device,” “MISFET device,” “IGBT device,” “diode device,” etc., as necessary.
  • the electric field relaxation structure (21) is formed at the bottom of the trench (17), so that the electric field concentration at the bottom of the trench (17) can be relaxed.
  • the electric field relaxation structure (21) is connected to a plurality of first contact regions (34A) and second contact regions (34B), the electric field relaxation structure (21) can be fixed to a predetermined potential via the plurality of first contact regions (34A) and second contact regions (34B).
  • first contact regions (34A) and second contact regions (34B) for contacting the electric field relaxation structure (21) are arranged separately on one side and the other side of the width direction of the trench (17). This allows channels to be formed evenly in the length direction of the trench (17), making it possible to evenly balance the current during a short circuit. This makes it possible to prevent partial current concentration and improve the breakdown resistance.
  • the channel current is biased toward the other side of the trench (17) in the width direction. This increases the likelihood of current concentrating on the other side of the trench (17) in the width direction, leading to breakdown in the event of a short circuit.
  • the channel can be formed evenly and in a balanced manner along the length of the trench (17), preventing current concentration and improving breakdown resistance.
  • first contact region (34A) and the second contact region (34B) each integrally include a first portion (23, 26) extending along a side surface of the trench (17) in the depth direction of the trench (17) and having a first thickness (T1A, T1B) from the side surface of the trench (17), and a second portion (24, 27) extending from the first portion (23, 26) along a bottom surface of the trench (17) and having a second thickness (T2A, T2B) from the bottom surface of the trench (17) that is greater than the first thickness (T1A, T1B).
  • Appendix 1-6 The semiconductor device (1) according to any one of Appendices 1-1 to 1-5, wherein a plurality of the first contact regions (34A) and a plurality of the second contact regions (34B) are alternately arranged at intervals along the longitudinal direction of the trench (17).
  • a plurality of trenches (17) are arranged at intervals in a first direction (X);
  • the first contact regions (34A) are uniformly arranged on one side of each of the trenches (17) in the first direction (X) throughout the trenches (17),
  • the semiconductor device (1) described in Appendix 1-6, wherein the plurality of second contact regions (34B) are uniformly arranged on the other side of the first direction (X) of each of the trenches (17) throughout the entirety of the plurality of trenches (17).
  • a plurality of the trenches (17) are arranged at intervals, The semiconductor device (1) according to any one of Appendices 1-1 to 1-4, 1-10, and 1-11, wherein the first contact region (34A) formed along a side surface of one of a pair of trenches (17A) of the plurality of trenches (17) and the second contact region (34B) formed along a side surface of the other trench (17B) are integrated to form a single contact region (59) spanning the one trench (17A) and the other trench (17B).
  • Appendix 1-13 a drain region (6) of a first conductivity type formed on the second main surface (4) side of the first impurity region (7); a body region (15) formed by the second impurity region (15); a source region (33) formed by the third impurity region (33);
  • the semiconductor device (1) according to any one of Appendices 1-1 to 1-12, comprising a trench gate structure (16) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).
  • Appendix 1-14 a collector region (71) of a second conductivity type formed on the second main surface (4) side of the first impurity region (7); a base region (72) formed by the second impurity region (15); an emitter region (73) formed by the third impurity region (33);
  • the semiconductor device (1) according to any one of Appendices 1-1 to 1-12, comprising a trench gate structure (16) formed by the trench (17), an insulating film (18) covering a wall surface of the trench (17), and a buried electrode (19) buried in the trench (17).

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018225600A1 (ja) * 2017-06-06 2018-12-13 三菱電機株式会社 半導体装置および電力変換装置
JP2019096711A (ja) * 2017-11-22 2019-06-20 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
JP2020017641A (ja) * 2018-07-26 2020-01-30 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2023136822A (ja) * 2022-03-17 2023-09-29 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018225600A1 (ja) * 2017-06-06 2018-12-13 三菱電機株式会社 半導体装置および電力変換装置
JP2019096711A (ja) * 2017-11-22 2019-06-20 株式会社東芝 半導体装置、半導体装置の製造方法、インバータ回路、駆動装置、車両、及び、昇降機
JP2020017641A (ja) * 2018-07-26 2020-01-30 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2023136822A (ja) * 2022-03-17 2023-09-29 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機

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