WO2025011663A1 - 场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管 - Google Patents

场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管 Download PDF

Info

Publication number
WO2025011663A1
WO2025011663A1 PCT/CN2024/105467 CN2024105467W WO2025011663A1 WO 2025011663 A1 WO2025011663 A1 WO 2025011663A1 CN 2024105467 W CN2024105467 W CN 2024105467W WO 2025011663 A1 WO2025011663 A1 WO 2025011663A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
semiconductor layer
gate
type semiconductor
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/105467
Other languages
English (en)
French (fr)
Inventor
刘伟
尹向阳
薛勇
邓云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Huarui Shengyang Investment Co Ltd
Original Assignee
Guangzhou Huarui Shengyang Investment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Huarui Shengyang Investment Co Ltd filed Critical Guangzhou Huarui Shengyang Investment Co Ltd
Publication of WO2025011663A1 publication Critical patent/WO2025011663A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 

Definitions

  • the present invention belongs to the field of semiconductor technology, and in particular, relates to a field effect transistor, a trench MOS diode and an insulated gate bipolar transistor.
  • the Schottky source-drain MOSFET structure was proposed in the 1960s. It uses metal source-drain to replace the semiconductor-doped source-drain of the traditional pn junction MOSFET, and a Schottky contact barrier is formed between the metal source-drain and the semiconductor.
  • a Schottky contact barrier is formed between the metal source-drain and the semiconductor.
  • the Schottky source-drain MOSFET is a normally-off device; the conduction of the Schottky source-drain MOSFET is achieved by forming a conductive channel under the action of a positive gate bias, and the carriers at the source end directly tunnel through the barrier into the channel.
  • the on-state current of conventional pn junction MOSFET can reach tens of amperes to hundreds of amperes, while the on-state current of Schottky source-drain MOSFET under the same conditions can only reach milliamperes or even lower; second, the off-state leakage is large, and the leakage current includes the thermal electron emission current from the source junction transmitted through the substrate and the tunneling current from the source junction.
  • the applicant adjusts the pure Schottky source in the Schottky source-drain MOSFET to a combination of an ohmic source and a Schottky source, wherein the ohmic source is between the gate insulating film and the Schottky source.
  • the normally-off function can be realized by utilizing the local depletion effect of the Schottky junction formed by the Schottky source and the n-type semiconductor layer on the electron carriers.
  • the normally-off effect is achieved only by relying on the unilateral depletion effect of the electron carriers in the n-type semiconductor layer between the Schottky source and the gate insulating film layer on the Schottky junction formed by the Schottky source and the n-type semiconductor layer.
  • the width of the ohmic source needs to be ⁇ 100nm to ensure a good normally-off effect. This places extremely high demands on the wafer manufacturing process, especially the photolithography & etching technology and equipment.
  • the process window is narrow and the fault tolerance is small, which easily causes the width size to exceed the limit and leads to large off-state leakage of the device.
  • the present invention introduces a metal material or a p-type gate electrode material that can form a Schottky barrier with the semiconductor layer into the gate electrode, so that the gate electrode has a depletion effect on the electron carriers in the semiconductor layer, thereby achieving a double-sided pinch-off effect.
  • This can relax the precision control of the key width dimension, reduce the requirements for lithography & etching technology and equipment, and solve the problem of large off-state leakage of the device due to the narrow process window, which easily causes the width dimension to exceed the limit.
  • the present invention provides a field effect transistor having:
  • Electrodes including a drain electrode, a source electrode and a gate electrode
  • the gate electrode at least includes a metal material having a Schottky barrier with the semiconductor layer of the first conductivity type, and the metal material is in contact with a gate insulating film; or the gate electrode at least includes an electrode material of a second conductivity type, and the electrode material of the second conductivity type is in contact with a gate insulating film, wherein the conductivity types of the second conductivity type and the first conductivity type are different.
  • the work function of the metal material is greater than the work function of a corresponding material of the first conductive type semiconductor layer.
  • the metal material is Pt, Ni, Co, or Au.
  • the drain electrode is formed on the first main surface of the first conductivity type semiconductor layer, and the source electrode is located on the second main surface side of the first conductivity type semiconductor layer.
  • the field effect transistor is a vertical MOSFET.
  • the vertical MOSFET is a planar gate MOSFET, a trench gate MOSFET, a shielded gate MOSFET, or a super junction MOSFET.
  • the material of the semiconductor layer is silicon, silicon carbide, gallium nitride, gallium oxide, or tin oxide.
  • a first semiconductor layer including an n-type semiconductor region
  • a second semiconductor layer including an n-type semiconductor region and a high-resistance semiconductor region
  • Electrodes including a drain electrode, a source electrode and a gate electrode
  • a gate insulating film which is interposed between the gate electrode and the semiconductor layer
  • the drain electrode is formed on a surface of the first semiconductor layer opposite to the second semiconductor layer;
  • the source electrode is formed on a surface of the second semiconductor layer opposite to the first semiconductor layer, a Schottky barrier exists between a portion of the source electrode and the n-type semiconductor region of the second semiconductor layer, a first portion of the source electrode is not in contact with the gate insulating film, and a second portion of the source electrode is in contact with the n-type semiconductor region of the second semiconductor layer to form an ohmic contact;
  • the high-resistance semiconductor region of the second semiconductor layer is disposed in a region close to a surface layer of the second semiconductor layer and is formed between the gate insulating film and a first portion of the source electrode;
  • the gate electrode at least includes a metal material having a Schottky barrier with the second semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode uses a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
  • the first portion of the source electrode contacts the n-type semiconductor region of the second semiconductor layer to form a Schottky barrier contact.
  • the work function of the metal material is greater than the work function of the corresponding material of the semiconductor layer.
  • the p-type conductive electrode material is p-type conductive polysilicon.
  • the present invention has the following beneficial effects:
  • the present invention introduces a metal material that can generate a Schottky barrier between the gate electrode and the semiconductor layer or a semiconductor material that can deplete the carriers in the semiconductor layer.
  • a metal material that can generate a Schottky barrier between the gate electrode and the semiconductor layer or a semiconductor material that can deplete the carriers in the semiconductor layer.
  • a Schottky gate or a p-type gate is introduced to generate depletion on the electron carriers of the n-type semiconductor region from the other side, thereby achieving the effect of double-side depletion.
  • the on-state current capacity is maintained and the off-state leakage is further reduced, and it is also beneficial to the regulation of the turn-on voltage; from the perspective of process technology, the key width dimension requirements can be relaxed, the requirements for photolithography & etching technology and equipment can be reduced, the process window can be expanded, and the mass production yield can be improved.
  • the present invention further provides a trench MOS diode having:
  • An n-type semiconductor layer having a first main surface on one side and a second main surface on the other side opposite thereto, and having a groove, the groove opening inward from the first main surface of the n-type semiconductor layer;
  • a cathode electrode formed on the second main surface of the n-type semiconductor layer
  • an anode electrode formed on the first main surface of the n-type semiconductor layer
  • a trench MOS gate which is buried in the trench and wrapped by the gate insulating film, is separated from the n-type semiconductor layer by the gate insulating film, and is in contact with the anode electrode;
  • the first portion of the anode electrode forms a Schottky contact with the first main surface of the n-type semiconductor layer, and the second portion of the anode electrode forms an ohmic contact with the first main surface of the n-type semiconductor layer;
  • the trench MOS gate at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the trench MOS gate at least includes a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
  • the width of the first portion of the anode electrode from the gate insulating film is in the range of 3nm to 400nm.
  • the width of the first portion of the anode electrode from the gate insulating film is in the range of 3 nm to 200 nm.
  • the trench MOS diode of the present invention can further reduce the turn-on voltage and conduction loss when forward conducting; and can reduce the off-state leakage when reverse cutting off.
  • the present invention also provides an insulated gate bipolar transistor having:
  • An electrode including a collector, an emitter, and a gate electrode, wherein the collector is formed on a surface of the p-type semiconductor layer opposite to the n-type semiconductor layer;
  • a gate insulating film which is interposed between the gate electrode and the n-type semiconductor layer;
  • the gate electrode at least includes a metal material having a Schottky barrier with the n-type semiconductor layer, and the metal material is in contact with the gate insulating film; or the gate electrode is made of a p-type conductive electrode material, and the p-type conductive electrode material is in contact with the gate insulating film.
  • the first portion of the emitter contacts the n-type semiconductor layer to form a Schottky barrier contact.
  • the width of the first portion of the emitter from the gate insulating film ranges from 3 nm to 400 nm.
  • the width of the first portion of the emitter from the gate insulating film ranges from 3 nm to 200 nm.
  • the metal material is Pt, Ni, Au, or Co.
  • the p-type conductive electrode material is p-type conductive polysilicon.
  • the insulated gate bipolar transistor of the present invention introduces a metal material capable of generating a Schottky barrier with the semiconductor layer or a p-type conductive electrode material capable of depleting the electron carriers in the semiconductor layer into the gate electrode, and introduces a Schottky gate or a p-type gate to deplete the electron carriers in the n-type semiconductor region, so that the off-state leakage can be further reduced in terms of electrical performance; and the process window can be expanded in terms of process technology, thereby improving the mass production yield.
  • FIG. 1 is a vertical cross-sectional view of an embodiment of a conventional Schottky junction trench gate MOSFET.
  • FIG2 is a vertical cross-sectional view of an embodiment of a trench gate MOSFET applied for by the present applicant in patent application number 202310325051.0.
  • FIG. 3 a is a vertical cross-sectional view of a first example of a trench gate MOSFET according to an embodiment of the present invention.
  • FIG. 3 b is a vertical cross-sectional view of a second example of a trench gate MOSFET according to an embodiment of the present invention.
  • FIG. 3 c is a vertical cross-sectional view of a third example of a trench gate MOSFET according to an embodiment of the present invention.
  • FIG. 4 a is a vertical cross-sectional view of a first example of a planar gate MOSFET according to an embodiment of the present invention.
  • FIG. 4 b is a vertical cross-sectional view of a second example of a planar gate MOSFET according to an embodiment of the present invention.
  • FIG. 5 a is a vertical cross-sectional view of a first example of a shielded gate MOSFET according to an embodiment of the present invention.
  • FIG. 5 b is a vertical cross-sectional view of a second example of a shielded gate MOSFET according to an embodiment of the present invention.
  • FIG. 5 c is a vertical cross-sectional view of a third example of a shielded gate MOSFET according to an embodiment of the present invention.
  • FIG. 5 d is a vertical cross-sectional view of a fourth example of a shielded gate MOSFET according to an embodiment of the present invention.
  • 5 e is a vertical cross-sectional view of a fifth example of a shielded gate MOSFET according to an embodiment of the present invention.
  • FIG. 5 f is a vertical cross-sectional view of a sixth example of a shielded gate MOSFET according to an embodiment of the present invention.
  • 5g is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention.
  • FIG. 6 a is a vertical cross-sectional view of a first example of a super junction MOSFET according to an embodiment of the present invention.
  • FIG. 6 b is a vertical cross-sectional view of a second example of a super junction MOSFET according to an embodiment of the present invention.
  • FIG. 7 a is a vertical cross-sectional view of a first example of a trench MOS diode according to an embodiment of the present invention.
  • FIG. 7 b is a vertical cross-sectional view of a second example of a trench MOS diode according to an embodiment of the present invention.
  • FIG. 8 a is a vertical cross-sectional view of a first example of an insulated gate bipolar transistor according to an embodiment of the present invention.
  • 8 b is a vertical cross-sectional view of a second example of an insulated gate bipolar transistor according to an embodiment of the present invention.
  • Attached figure 1 is a vertical cross-sectional view of an embodiment of an existing Schottky junction trench gate MOSFET.
  • This Schottky junction trench gate MOSFET has: a drain electrode 11, an n+ type semiconductor 21a, an n-type semiconductor 21b, and a trench located in the n-type semiconductor 21b, a gate electrode 13 located in the trench and wrapped by a gate insulating film 51a, a Schottky source electrode 12b that forms a Schottky barrier contact with the n-type semiconductor 21b, and a source electrode 12 located thereon.
  • the reverse-biased depletion layer of the Schottky barrier formed between the Schottky source electrode 12b and the n-type semiconductor 21b is widened, which inhibits the transport of electron carriers, so that only a small number of electron carriers between the drain and the source form current through the tunneling effect, resulting in poor on-state current conduction capacity of the existing Schottky junction trench gate MOSFET, and its on-state current is much smaller than the on-state current of the pn junction MOSFET under the same conditions, which has led to the Schottky junction trench gate MOSFET not being commercially available so far.
  • the Schottky junction formed by the contact between the Schottky source electrode 12 b and the n-type semiconductor 21 b in contact with the Schottky source electrode 12 b will deplete the electron carriers in the n-type semiconductor 21 b between the gate insulating film 51 a and the Schottky source electrode 12 b.
  • the width of the n-type semiconductor 21 b between the gate insulating film 51 a and the Schottky source electrode 12 b is in the range of 3 nm to 250 nm, the MOSFET shown in FIG.
  • the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, the n-type gate electrode 13a may be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is in contact with the gate insulating film 51a, and the Schottky gate electrode 13c is composed of a metal material.
  • a Schottky gate electrode 13c having a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced.
  • the MIS (metal insulator semiconductor) junction formed by the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b.
  • the Schottky junction formed by the Schottky source electrode 12b and the semiconductor region 21 will also deplete the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b.
  • the width of the Schottky source electrode 12b from the gate insulating film 51a is in the range of 3nm to 250nm, under the combined effect of these two depletion effects , the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky source electrode 12b are completely depleted, thereby blocking the electron conduction channel between the drain electrode 11 and the source electrode 12, so the MOSFET shown in FIG3a can be normally off, and compared with the MOSFET shown in FIG2, when the width of the semiconductor region 21 is the same, from the electrical performance, the MOSFET shown in FIG3a has lower off-state leakage; from the process technology, to make a normally-off MOSFET, in FIG3a, the width of the semiconductor region 21 between the gate insulating film 51a and the Schottky source electrode 12b can be relatively wider than that designed in FIG2, thereby reducing the requirements for lithography & etching technology and equipment, expanding the process window, and improving the mass production yield.
  • FIG3b is a vertical cross-sectional view of a second embodiment of a trench gate MOSFET according to an embodiment of the present invention.
  • the gate electrode 13 in this embodiment includes a P-type conductive electrode material (electrode material of the second conductive type), that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • the p-type gate electrode 13b will also have a depletion effect on the electron carriers in the semiconductor region 21.
  • the Schottky junction formed by the Schottky source electrode 12b and the semiconductor region 21 will also have a depletion effect on the electron carriers in the semiconductor region 21 located between the gate insulating film 51a and the Schottky source electrode 12b.
  • the width of the Schottky source electrode 12b to the gate insulating film 51a ranges from 3nm to 250nm, the gate electrode 13b will be depleted.
  • the MOSFET shown in FIG3b can be normally off, and compared with the MOSFET shown in FIG2, when the width of the semiconductor region 21 is the same, from the electrical performance, the MOSFET shown in FIG3a has lower off-state leakage; from the process technology, to make a normally-off MOSFET, in FIG3b, the width of the semiconductor 21 located between the gate insulating film 51a and the Schottky source electrode 12b can be relatively wider than that designed in FIG2, thereby reducing the requirements for photolithography & etching technology and equipment, expanding the process window, and improving the mass production yield.
  • FIG3c is a vertical cross-sectional view of a third embodiment of a trench gate MOSFET according to an embodiment of the present invention.
  • the MOSFET shown in FIG3c is based on the MOSFET structure shown in FIG3a, with an n+ type semiconductor 21c added between the semiconductor region 21 and the ohmic source electrode 12a.
  • Such a design can make the ohmic contact effect better and reduce the contact resistance between the ohmic source electrode 12a and the semiconductor.
  • the MOSFET comprises a drain electrode 11, an n+ type semiconductor 21a, an n- type semiconductor 21b and a semiconductor region 21, a Schottky source electrode 12b, an ohmic source electrode 12a and a source electrode 12 thereon, a gate insulating film 51a and a gate electrode 13 thereon, the gate electrode 13 comprising a Schottky gate electrode 13c, and the Schottky gate electrode 13c is composed of a metal material.
  • FIG4b is a vertical cross-sectional view of a second embodiment of a planar gate MOSFET according to an embodiment of the present invention.
  • the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • FIG5a is a vertical cross-sectional view of the first embodiment of the shielded gate MOSFET involved in the embodiment of the present invention.
  • the MOSFET shown in FIG5a is a top-bottom gate structure, having: a drain electrode 11, an n+ type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench located in the n-type semiconductor 21b, a gate electrode 13 and a shielded source electrode 12c located in the trench and wrapped by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n-type semiconductor 21b, an ohmic source electrode 12a forming an ohmic contact with the semiconductor region 21, and a source electrode 12 located thereon.
  • the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the n-type gate electrode 13a can be phosphorus-doped n-type conductive polysilicon; the Schottky gate electrode 13c is composed of a metal material.
  • FIG5b is a vertical cross-sectional view of a second embodiment of a shielded gate MOSFET according to an embodiment of the present invention.
  • the gate electrode 13 comprises a P-type conductive electrode material, that is, the gate electrode 13 comprises a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • FIG5c is a vertical cross-sectional view of a third embodiment of a shielded gate MOSFET according to an embodiment of the present invention.
  • the MOSFET shown in FIG5c is a shielded gate MOSFET with a left-right split gate structure, which is based on the shielded gate MOSFET with an upper-lower gate structure shown in FIG5a, with the structure of the shielded gate region being designed and adjusted.
  • FIG5d is a vertical cross-sectional view of a fourth embodiment of a shielded gate MOSFET according to an embodiment of the present invention.
  • the MOSFET in this embodiment is a shielded gate MOSFET with a left-right split gate structure, which is different from the shielded gate MOSFET with a left-right split gate structure shown in FIG5c in that, in this embodiment, the gate electrode 13 includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • FIG5e is a vertical cross-sectional view of a fifth embodiment of a shielded gate MOSFET according to an embodiment of the present invention.
  • the MOSFET shown in FIG5e is another shielded gate MOSFET with a left-right split gate structure, which is based on the shielded gate MOSFET with a left-right split gate structure shown in FIG5c, and the structure of the shielded gate region is designed and adjusted.
  • FIG5f is a vertical cross-sectional view of the sixth embodiment of the shielded gate MOSFET involved in the embodiment of the present invention.
  • the MOSFET shown in FIG5e is another shielded gate MOSFET with a left-right split gate structure.
  • the difference between the MOSFET in this embodiment and the MOSFET shown in FIG5e is that the gate electrode 13 in this embodiment includes a P-type conductive electrode material, that is, the gate electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • FIG. 5g is a vertical cross-sectional view of a seventh example of a shielded gate MOSFET according to an embodiment of the present invention.
  • the MOSFET shown in FIG. 5g comprises: a drain electrode 11, an n+ type semiconductor 21a in contact with the drain electrode 11, an n- type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be an n- type semiconductor 21b or a high resistance semiconductor 41), an n+ type semiconductor 21c located on the semiconductor region 21, and a groove located in the n- type semiconductor 21b, a gate electrode 13 and a shielding source electrode 12c located in the groove and wrapped by a gate insulating film 51a, a Schottky source electrode 12b forming a Schottky barrier contact with the n- type semiconductor 21b, an ohmic source electrode 12a located thereon forming an ohmic contact with the n+ type semiconductor 21c, and a source electrode 12 located thereon; wherein the gate electrode 13 comprises a Schottky gate electrode 13
  • the MOSFET shown in FIG. 5g is based on the MOSFET shown in FIG. 5a, with the structural design of the source electrode region adjusted so that the ohmic source electrode 12a is not in contact with the gate insulating film 51a. This structural design can also achieve the function of reducing off-state leakage.
  • the gate electrode 13 and the Schottky source electrode 12b can jointly deplete the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41) to achieve a better normally-off effect and smaller off-state leakage; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.
  • the width of the semiconductor region 21 is relatively wider while maintaining the normally-off function.
  • metal materials with high work function such as Pt, Ni, Au, Co, Cu, Fe, etc. can be used.
  • FIG6a is a vertical cross-sectional view of a first embodiment of a super junction MOSFET according to an embodiment of the present invention.
  • the super junction MOSFET shown in FIG6a comprises: a drain electrode 11, an n+ type semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor 21b or a high resistance semiconductor 41), a deep trench in the n-type semiconductor 21b and a p-type polysilicon 12d in the deep trench, a Schottky source electrode 12b, an ohmic source electrode 12a and a source electrode 12, a gate insulating film 51a and a Schottky gate electrode 13c thereon, wherein the Schottky gate electrode 13c is made of a metal material.
  • FIG6b is a vertical cross-sectional view of a second embodiment of a super junction MOSFET according to an embodiment of the present invention.
  • the gate electrode 13 in this embodiment comprises a P-type conductive electrode material, that is, the gate electrode 13 comprises a p-type gate electrode 13b.
  • the gate electrode 13 and the Schottky source electrode 12b can jointly deplete the electron carriers in the semiconductor region 21 (the semiconductor region 21 can be an n-type semiconductor 21b or a high-resistance semiconductor 41) to achieve a better normally-off effect and smaller off-state leakage; in addition, the requirements for key dimensions in the process technology, such as the width of the semiconductor region 21, can be relaxed, the process window can be expanded, and the process yield can be improved.
  • FIG. 7 a is a vertical cross-sectional view of a first embodiment of a trench MOS diode according to an embodiment of the present invention, which comprises: a cathode electrode 61, an n-type semiconductor layer (including an n+-type semiconductor 21a and an n-type semiconductor 21b), a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor or a high-resistance semiconductor), a trench in the n-type semiconductor 21b, a trench MOS gate 63 in the trench and wrapped by a gate insulating film 51a, a Schottky anode 62b in contact with the n-type semiconductor 21b to form a Schottky barrier contact, an ohmic anode 62a in contact with the semiconductor region 21 to form an ohmic contact, and an anode electrode 62 thereon, wherein the trench MOS gate 63 is electrically connected to the anode electrode 62.
  • the n-type semiconductor 21b trench MOS gate 63 includes an n-type gate 63a and a Schottky gate 63c, the n-type gate 63a can be n-type conductive polysilicon, the Schottky gate 63c is in contact with the gate insulating film 51a, and the Schottky gate electrode 63c is composed of a metal material.
  • the n-type semiconductor layer has a first main surface 211 on one side and a second main surface 212 on the other side opposite thereto, and the groove opens inward from the first main surface 211 of the n-type semiconductor layer.
  • the first current path is along the anode electrode 62—ohmic anode 62a—semiconductor region 21—n-type semiconductor 21b—n+ type semiconductor 21a—cathode electrode 61; the second current path is along the anode electrode 62—Schottky anode 62b—n-type semiconductor 21b—n+ type semiconductor 21a—cathode electrode 61.
  • the first current path there is no contact barrier between the ohmic anode 62a and the semiconductor region 21; in the second current path, there is a Schottky barrier between the Schottky anode 62b and the n-type semiconductor 21b; when the diode is forward-conducted, since the first current path has relatively less obstruction and requires a lower turn-on voltage than the second current path, the current flows preferentially through the first current path.
  • the trench MOS diode based on the present invention has lower turn-on voltage and conduction loss.
  • the first type is that the Schottky barrier formed by the Schottky anode 62b, the n-type semiconductor 21b and the semiconductor region 21 is reversely biased and widened, which produces a longitudinal depletion effect on the electron carriers of the n-type semiconductor 21b and a lateral depletion effect on the electron carriers in the semiconductor region 21;
  • the second type is that the trench MOS gate 63 produces a lateral depletion effect on the electron carriers in the semiconductor region 21.
  • FIG7b is a vertical cross-sectional view of a second embodiment of a trench MOS diode according to an embodiment of the present invention.
  • the trench MOS gate 63 in this embodiment includes a P-type conductive electrode material, that is, the trench MOS gate 63 includes a p-type gate 63b.
  • FIG8a is a vertical cross-sectional view of a first embodiment of an insulated gate bipolar transistor according to an embodiment of the present invention.
  • the insulated gate bipolar transistor has a collector 11, a p+ semiconductor 31a, an n+ semiconductor 21a, an n-type semiconductor 21b, a semiconductor region 21 (the semiconductor region 21 may be an n-type semiconductor 21b or a high-resistance semiconductor 41), a trench in the n-type semiconductor 21b, a gate electrode 13 in the trench and wrapped by a gate insulating film, a Schottky emitter 12b in contact with the n-type semiconductor 21b to form a Schottky barrier contact, an ohmic emitter 12a in contact with the n-type semiconductor 21b to form an ohmic contact, and an emitter 12 thereon.
  • the gate electrode 13 includes a Schottky gate electrode 13c and an n-type gate electrode 13a, and the Schottky gate electrode 13c is made of a metal material.
  • a Schottky gate electrode 13c having a Schottky barrier between the gate electrode 13 and the semiconductor region 21 is introduced.
  • the MIS (metal insulator semiconductor) junction formed by the Schottky gate electrode 13c, the gate insulating film 51a and the semiconductor region 21 will deplete the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky emitter 12b.
  • the Schottky junction formed by the Schottky emitter 12b and the semiconductor region 21 will also deplete the electron carriers in the semiconductor 21 between the gate insulating film 51a and the Schottky emitter 12b.
  • the electron carriers in the semiconductor region 21 between the Schottky source electrode 12b produce a depletion effect.
  • the width range of the Schottky emitter 12b from the gate insulating film 51a is between 3nm and 250nm, under the combined effect of these two depletion effects, the electron carriers in the semiconductor region 21 between the gate insulating film 51a and the Schottky emitter 12b are completely depleted, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12.
  • Such a design through the combined effect of the two depletion effects can reduce the off-state leakage of the device.
  • the gate electrode 13 includes a P-type conductive electrode material, that is, the electrode 13 includes a p-type gate electrode 13b, and the p-type gate electrode 13b can be boron-doped p-type conductive polysilicon.
  • the p-type gate electrode 13b will also have a depletion effect on the electron carriers in the semiconductor region 21.
  • the Schottky junction formed by the Schottky emitter 12b and the semiconductor region 21 will also have a depletion effect on the electron carriers in the semiconductor region 21 located between the gate insulating film 51a and the Schottky emitter 12b.
  • the width range of the Schottky emitter 12b from the gate insulating film 51a is between 3nm and 250nm, under the combined action of these two depletion effects, the carriers in the semiconductor region 21 are completely depleted, thereby blocking the electron carrier conduction channel between the collector 11 and the emitter 12.
  • the design of the combined action of the two depletion effects can reduce the off-state leakage of the device.
  • MOSFETs shown in the various embodiments of the present invention are all n-channel MOSFETs based on the participation of electron carriers in conduction.
  • the essence of the technical solution of the present invention is also applicable to p-channel MOSFETs based on the participation of hole carriers in conduction.
  • the material of the semiconductor may be a single element semiconductor such as germanium, silicon, etc.; the material of the semiconductor may be a compound semiconductor such as silicon carbide, gallium nitride, gallium oxide, tin oxide, etc.

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

本发明属于半导体技术领域，基于对肖特基源漏MOSFET的结构创新，提出了一种具有大的开态通流能力以及更低的关态漏电能力的场效应晶体管。以n沟道常关型的MOSFET为例，在原来利用源电极与n型半导体区形成肖特基结对n型半导体区的电子载流子从一侧产生耗尽作用的基础上，再引入肖特基栅或者p型栅对n型半导体区的电子载流子从另一侧产生耗尽，从而实现双侧耗尽的影响效果，如此，从电性能上，既维持了开态通流能力又进一步降低了关态漏电，同时也有利于开启电压的调节；从制程工艺上，可放宽关键的宽度尺寸要求，降低对光刻&刻蚀技术和设备的要求，扩大工艺窗口，提升批量化生产良率。

Description

场效应晶体管、沟槽MOS型二极管及绝缘栅双极型晶体管 技术领域
本发明属于半导体技术领域，特别地，涉及一种场效应晶体管、沟槽MOS型二极管及绝缘栅双极型晶体管。
 背景技术
肖特基源漏MOSFET结构于20世纪60年代被提出，它是利用金属源漏取代传统pn结型MOSFET的半导体掺杂源漏，并且金属源漏与半导体之间形成肖特基接触势垒。对于肖特基源漏MOSFET，当在漏源之间施加正电压时，源极与半导体材料之间形成的肖特基势垒反偏，使耗尽层扩宽来实现关断，据此，肖特基源漏MOSFET是常关型器件；肖特基源漏MOSFET的导通，是在正栅偏压的作用下形成导电沟道，由源端的载流子直接隧穿势垒进入沟道来实现的。
自肖特基源漏MOSFET诞生之初，就存在两大显著的缺点：第一，开态电流小，当肖特基源漏MOSFET的漏源电压V DS＞0时，肖特基源电极与半导体形成的肖特基接触势垒反偏使耗尽区扩宽，使得即使在栅电极和肖特基源电极之间施加正栅源电压V GS时，在漏电极和肖特基源电极之间也未能形成完整且高浓度的电子导电通道，在靠近肖特基源电极的区域始终存在一定的肖特基势垒高度，这有限的肖特基势垒高度抑制了电子载流子的输运，使得仅有少部分的电子载流子通过隧穿效应形成电流，根据电导率的计算公式σ = nqu（其中n是参与导电的电子载流子浓度，q是电子电荷量，u是一定载流子浓度条件下的迁移率），参与导电的载流子浓度n越低，电导率σ就越低。再根据电流密度J = σE（其中E代表电场强度），电导率σ越低，电流密度J就越低，这就是肖特基源漏MOSFET开态电流比同等条件下的pn结MOSFET开态电流小的原因，常规pn结MOSFET的开态电流可以达到几十安~几百安量级，而同等条件下的肖特基源漏MOSFET的开态电流只能达到毫安量级甚至更低；第二，关态漏电大，漏电流包括了来自源结通过衬底传输的热电子发射电流和来自源结的隧穿电流。
本申请人在申请号为202310325051.0的专利中，将肖特基源漏MOSFET中的纯肖特基源极调整为欧姆源极和肖特基源极的组合，其中欧姆源极介于栅绝缘膜和肖特基源极之间，通过这一结构细节的设计改进，彻底解决了肖特基源漏MOSFET的开态电流小的问题，使其开态通流能力能够与同等条件下的pn结型MOSFET的开态通流能力相媲美。同时在平衡状态下（当V DS=0&V GS=0时），可利用肖特基源极与n型半导体层形成的肖特基结对电子载流子的局部耗尽作用实现常关功能。
然而，在平衡状态下（当V DS=0&V GS=0时），仅依靠肖特基源极与n型半导体层形成的肖特基结对介于肖特基源极和栅绝缘膜层之间的n型半导体层中的电子载流子产生的单侧耗尽作用来实现常关，就需要介于栅绝缘膜和肖特基源极之间的n型半导体层以及与之接触的欧姆源极的宽度尽可能的小，以硅半导体材料为例，欧姆源极的宽度需要≤100nm，才能确保良好的常关效果，这对晶圆制造工艺尤其是光刻&刻蚀技术和设备的要求极高，工艺窗口狭窄，容错率小，容易使宽度尺寸超限而导致器件的关态漏电大。
发明内容
有鉴于此，本发明在栅电极中引入能够与半导体层形成肖特基势垒的金属材料或p型栅电极材料，使得栅电极对半导体层中的电子载流子具有耗尽作用，进而实现双侧夹断的效果，如此可放宽对关键宽度尺寸的精度控制，可降低对光刻&刻蚀技术和设备的要求，解决因工艺窗口狭窄，容易使宽度尺寸超限而导致器件的关态漏电大的问题。
为了解决上述技术问题，本发明提供一种场效应晶体管，具有：
第1导电型的半导体层；
电极，其包括漏电极、源电极以及栅电极；
栅绝缘膜，其介于所述栅电极和所述第1导电型的半导体层之间；
所述源电极的第一部分与所述第1导电型的半导体层之间存在肖特基势垒，所述源电极的第一部分和所述栅绝缘膜未接触；所述源电极的第二部分与所述第1导电型的半导体层形成欧姆接触；
所述栅电极至少包括与所述第1导电型的半导体层之间存在肖特基势垒的金属材料，所述金属材料与栅绝缘膜接触；或所述栅电极至少包括第2导电型的电极材料，所述第2导电型的电极材料与栅绝缘膜接触，其中，所述第2导电型和所述第1导电型的导电类型不同。
优选的，所述第1导电型的半导体层是n型半导体层。
优选的，所述源电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
进一步的，所述源电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
优选的，当所述第1导电型的半导体层是n型半导体层时，所述金属材料的功函数大于所述第1导电型的半导体层对应材料的功函数。
进一步的，所述金属材料是Pt、Ni、Co、Au。
优选的，当所述第1导电型的半导体层是n型半导体层时，所述第2导电型的电极材料是p型导电的多晶硅。
优选的，所述漏电极形成于所述第1导电型的半导体层的所述第1主面上，所述源电极位于所述第1导电型的半导体层的所述第2主面一侧。
进一步的，所述场效应晶体管是纵式MOSFET。
进一步的，所述纵式MOSFET是平面栅MOSFET、沟槽栅MOSFET、屏蔽栅MOSFET、超结MOSFET。
优选的，所述半导体层的材料是硅、碳化硅、氮化镓、氧化镓、氧化锡。
本发明还提供一种场效应晶体管，具有：
第1半导体层，其包括n型半导体区；
第2半导体层，其包括n型半导体区以及高阻型半导体区；
电极，其包括漏电极、源电极以及栅电极；
栅绝缘膜，其介于所述栅电极和半导体层之间；
所述漏电极，其形成于所述第1半导体层的与所述第2半导体层相反的一侧的面上；
所述源电极，其形成于所述第2半导体层的与所述第1半导体层相反的一侧的面上，所述源电极的一部分与所述第2半导体层的所述n型半导体区之间存在肖特基势垒，所述源电极的第一部分与所述栅绝缘膜未接触；所述源电极的第二部分与所述第2半导体层的所述n型半导体区接触形成欧姆接触；
所述第2半导体层的所述高阻型半导体区，其设置在靠近所述第2半导体层的表层的区域，其形成于所述栅绝缘膜和所述源电极的第一部分之间；
所述栅电极至少包括与所述第2半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述栅电极采用p型导电的电极材料，所述p型导电的电极材料与所述栅绝缘膜接触。
优选的，所述源电极的第一部分与所述第2半导体层的所述n型半导体区接触形成肖特基势垒接触。
优选的，所述金属材料的功函数大于所述半导体层对应材料的功函数。
优选的，所述p型导电的电极材料是p型导电的多晶硅。
优选的，所述半导体层的材料是氧化镓，所述高阻型半导体区的材料是氮（N）掺杂的氧化镓。
针对上述发明内容，本发明具有如下有益效果：
本发明在栅电极中引入能够与半导体层之间产生肖特基势垒的金属材料或能够对半导体层中的载流子产生耗尽作用的半导体材料，以n沟道增强型MOSFET为例，在原来利用源电极与n型半导体区形成肖特基结对n型半导体区的电子载流子从一侧产生耗尽作用的基础上，再引入肖特基栅或者p型栅对n型半导体区的电子载流子从另一侧产生耗尽，从而实现双侧耗尽的影响效果，如此，从电性能上，既维持了开态通流能力又进一步降低了关态漏电，同时也有利于开启电压的调节；从制程工艺上，可放宽关键的宽度尺寸要求，降低对光刻&刻蚀技术和设备的要求，扩大工艺窗口，提升批量化生产良率。
本发明再提供一种沟槽MOS型二极管，具有：
n型半导体层，其具有一侧的第一主面以及与之相反的另一侧的第二主面，具有沟槽，所述沟槽从所述n型半导体层的所述第一主面上向内开口；
阴极电极，其形成于所述n型半导体层的所述第二主面上；
阳极电极，其形成于所述n型半导体层的所述第一主面上；
沟槽MOS栅极，其埋入所述沟槽内并被所栅述绝缘膜包裹，其与所述n型半导体层之间隔着所述栅绝缘膜，其与所述阳极电极接触；
所述阳极电极的第一部分与所述n型半导体层的所述第一主面形成肖特基接触，所述阳极电极的第二部分与所述n型半导体层的所述第一主面接触形成欧姆接触；
所述沟槽MOS栅极至少包括与所述n型半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述沟槽MOS栅极至少包括p型导电的电极材料，所述p型导电的电极材料与所述栅绝缘膜接触。
所述阳极电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
优选的，所述阳极电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
针对本发明的沟槽MOS型二极管，其有益效果如下：
本发明的沟槽MOS型二极管，相较于传统的沟槽MOS型肖特基二极管，正向导通时，能够更进一步的降低开启电压，减小导通损耗；反向截止时，能够减小关态漏电。
本发明还提供一种绝缘栅双极型晶体管，具有：
p型半导体层；
层叠于所述p型半导体层之上的n型半导体层；
电极，其包括集电极、发射极以及栅电极，所述集电极形成于所述p型半导体层的与所述n型半导体层相反的一侧的面上；
栅绝缘膜，其介于所述栅电极和所述n型半导体层之间；
所述发射极的第一部分与所述n型半导体层之间存在肖特基势垒，所述发射极的第一部分与所述栅绝缘膜未接触，所述发射极的第二部分与所述n型半导体层形成欧姆接触；
所述栅电极至少包括与所述n型半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述栅电极采用p型导电的电极材料制成，所述p型导电的电极材料与所述栅绝缘膜接触。
优选的，所述发射极的第一部分与所述n型半导体层接触形成肖特基势垒接触。
优选的，所述发射极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
进一步的，所述发射极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
优选的，所述金属材料是Pt、Ni、Au、Co。
优选的，所述p型导电的电极材料是p型导电的多晶硅。
本发明的绝缘栅双极型晶体管，在栅电极中引入能够与半导体层之间产生肖特基势垒的金属材料或能够对半导体层中的电子载流子产生耗尽作用的p型导电的电极材料，引入了肖特基栅或p型栅对n型半导体区的电子载流子产生耗尽作用，如此从电性能上，可进一步的降低关态漏电；从制程工艺上，也可扩大工艺窗口，提升批量化生产良率。
 附图说明
为了更清楚地说明本发明的技术方案，下面将通过实施例或现有技术描述中所需要的附图作简单介绍，显而易见地，下面描述中的部分附图仅仅是本发明的一些实施例的说明，本发明要求的保护范围并不局限于实施例。对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其
他的附图。
附图1是现有肖特基结型沟槽栅MOSFET的一个实施例的垂直截面图。
附图2是本申请人在申请号为202310325051.0的专利中申请的沟槽栅MOSFET的一个实施例的垂直截面图。
附图3a是本发明的实施方式涉及的沟槽栅MOSFET的第一实施例的垂直截面图。
附图3b是本发明的实施方式涉及的沟槽栅MOSFET的第二实施例的垂直截面图。
附图3c是本发明的实施方式涉及的沟槽栅MOSFET的第三实施例的垂直截面图。
附图4a是本发明的实施方式涉及的平面栅MOSFET的第一实施例的垂直截面图。
附图4b是本发明的实施方式涉及的平面栅MOSFET的第二实施例的垂直截面图。
附图5a是本发明的实施方式涉及的屏蔽栅MOSFET的第一实施例的垂直截面图。
附图5b是本发明的实施方式涉及的屏蔽栅MOSFET的第二实施例的垂直截面图。
附图5c是本发明的实施方式涉及的屏蔽栅MOSFET的第三实施例的垂直截面图。
附图5d是本发明的实施方式涉及的屏蔽栅MOSFET的第四实施例的垂直截面图。
附图5e是本发明的实施方式涉及的屏蔽栅MOSFET的第五实施例的垂直截面图。
附图5f是本发明的实施方式涉及的屏蔽栅MOSFET的第六实施例的垂直截面图。
附图5g是本发明的实施方式涉及的屏蔽栅MOSFET的第七实施例的垂直截面图。
附图6a是本发明的实施方式涉及的超结MOSFET的第一实施例的垂直截面图。
附图6b是本发明的实施方式涉及的超结MOSFET的第二实施例的垂直截面图。
附图7a是本发明的实施方式涉及的沟槽MOS型二极管的第一实施例的垂直截面图。
附图7b是本发明的实施方式涉及的沟槽MOS型二极管的第二实施例的垂直截面图。
附图8a是本发明的实施方式涉及的绝缘栅双极型晶体管的第一实施例的垂直截面图。
附图8b是本发明的实施方式涉及的绝缘栅双极型晶体管的第二实施例的垂直截面图。
附图中的标记所对应的技术特征为：
11   漏电极（集电极）
12   源电极（发射极）
12a  欧姆源电极（欧姆发射极）
12b  肖特基源电极（肖特基发射极）
12c  屏蔽源电极
12d  p型多晶硅
13   栅电极
13a  n型栅电极
13b  p型栅电极
13c  肖特基栅电极
21   半导体区
21a  n+型半导体
21b  n-型半导体
21c  n+型半导体
211  第一主面
212  第二主面
31a  p+型半导体
31b  p-型半导体
41   高阻型半导体
51a  栅绝缘膜
51b  非栅绝缘膜
61   阴极电极
62   阳极电极
62a  欧姆阳极
62b  肖特基阳极
63   沟槽MOS栅极
63a  n型栅极
63b  p型栅极
63c  肖特基栅极
 具体实施方式
以下描述中，为了说明而不是为了限定，提出了诸如特定系统结构、技术之
类的具体细节，以便透彻理解本发明实施例。然而，本领域的技术人员应当清楚，在没有这些具体细节的其它实施例中也可以实现本发明。在其它情况中，省略对众所周知的系统、装置以及方法的详细说明，以免不必要的细节妨碍本发明的描述。
    附图1是现有肖特基结型沟槽栅MOSFET的一个实施例的垂直截面图。此肖特基结型沟槽栅MOSFET具有：漏电极11，n+型半导体21a，n-型半导体21b，以及位于n-型半导体21b中的沟槽，位于沟槽中且被栅绝缘膜51a包裹的栅电极13，与n-型半导体21b形成肖特基势垒接触的肖特基源电极12b，以及位于其上的源电极12。
附图1所示的肖特基结型沟槽栅MOSFET，由于肖特基源电极12b与n-型半导体层21b之间形成的肖特基结的存在，当只在漏电极11和源电极12之间施加正向电压时，肖特基结反偏使耗尽区扩宽，使得在漏电极11和源电极12之间未形成完整的电子导电沟道，在漏源之间无电流通过，基于此原理，附图1所示的肖特基结型沟槽栅MOSFET是常关型器件。
当在栅电极13和源电极12之间施加正电压时，由于肖特基源电极12b与n-型半导体21b之间的肖特基势垒的存在，使得在漏电极11和肖特基源电极12b之间，未能形成完整的且高浓度的电子导电通道，此时即使在漏电极11和源电极12之间施加正电压时，由于肖特基源电极12b与n-型半导体21b之间构成的肖特基势垒反偏耗尽层扩宽，这就抑制了电子载流子的输运，使得漏源之间仅有少部分的电子载流子通过隧穿效应形成电流，导致现有肖特基结型沟槽栅MOSFET的开态通流能力很差，其开态电流比同等条件下的pn结型MOSFET的开态电流小很多，这导致肖特基结型沟槽栅MOSFET至今未能商用。
附图2是本申请人在申请号为202310325051.0的专利中申请的沟槽栅MOSFET的一个实施例的垂直截面图。在该实施例中的沟槽栅MOSFET是在附图1所示的肖特基结型沟槽栅MOSFET的基础上，将与n-型半导体21b接触的肖特基源电极12b变更设计为欧姆源电极12a和肖特基源电极12b。附图2中，欧姆源电极12a与n-型半导体21b形成欧姆接触，肖特基源电极12b与n-型半导体21b形成肖特基接触。
附图2所示的MOSFET中，当漏电极11和源电极12之间的电压V DS=0及栅电极13和源电极12之间的电压V GS=0时，由于肖特基源电极12b和与之接触的n-型半导体21b接触形成的肖特基结会对位于栅绝缘膜51a和肖特基源电极12b之间的n-型半导体21b中的电子载流子产生耗尽作用，当位于栅绝缘膜51a和肖特基源电极12b之间的n-型半导体21b的宽度范围介于3nm~250nm区间时，附图2所示的MOSFET可以实现常关功能；当漏电极11和源电极12之间的电压V DS＞0及栅电极13和源电极12之间的电压V GS=0时，由于肖特基源电极12b和与之接触的n-型半导体21b接触形成的肖特基结反偏，使得耗尽区继续展宽，此时，MOSFET处于关断状态；当漏电极11和源电极12之间的电压V DS＞0，并在栅电极13和源电极12之间施加的电压V GS＞0时，随着V GS＞的增大，达到开启电压V GS（th）时，由于开启电压V GS（th）的作用，在n-型半导体21b的临近栅绝缘膜51a的区域中，形成了高浓度的电子导电通道，此时在漏电极11和源电极12之间就会有电流流过，器件导通；如此，附图2所示的MOSFET是可以设计成具有大的通流能力的常关型器件。
附图3a是本发明的实施方式涉及的沟槽栅MOSFET的第一实施例的垂直截面图。此MOSFET包括：漏电极11、层叠在漏电极11上的n+型半导体21a、层叠在n+型半导体21a上的n-型半导体21b（n+型半导体21a和n-型半导体21b均为第1导电型的半导体层）、位于n-型半导体21b中的沟槽、位于沟槽中且被栅绝缘膜51a包裹的栅电极13、位于栅绝缘膜51a与肖特基源电极12b之间的半导体区21（半导体区21可以是n-型半导体21b，也可以是高阻型半导体41）、与n-型半导体21b形成肖特基势垒接触的肖特基源电极12b、与半导体区21形成欧姆接触的欧姆源电极12a以及位于其上的源电极12；其中，栅电极13包括肖特基栅电极13c和n型栅电极13a，n型栅电极13a可以是磷掺杂的n型导电的多晶硅；肖特基栅电极13c与栅绝缘膜51a接触，肖特基栅电极13c由金属材料组成。
附图3a所示的MOSFET，在栅电极13中引入与半导体区21之间存在肖特基势垒的肖特基栅电极13c，由肖特基栅电极13c、栅绝缘膜51a以及半导体区21三者构成的MIS（金属绝缘体半导体）结会对位于栅绝缘膜51a和肖特基源电极12b之间的半导体区21中的电子载流子产生耗尽作用，加之由肖特基源电极12b与半导体区21构成的肖特基结同样会对位于栅绝缘膜51a和肖特基源电极12b之间的半导体区21中的电子载流子产生耗尽作用，当肖特基源电极12b距离栅绝缘膜51a的宽度范围介于3nm~250nm区间时，在这两种耗尽作用的共同作用下，将位于栅绝缘膜51a和肖特基源电极12b之间的半导体21中的电子载流子完全耗尽，从而阻断了漏电极11和源电极12之间的电子导电通道，因此附图3a所示的MOSFET能够实现常关，并且较之于附图2所示的MOSFET，在半导体区21的宽度一样的情况下，从电性能上，附图3a所示的MOSFET具有更低的关态漏电；从制程工艺上，要制作常关型MOSFET，附图3a中，位于栅绝缘膜51a和肖特基源电极12b之间的半导体区21的宽度尺寸可以比附图2中设计的相对更宽，从而可降低对光刻&刻蚀技术和设备的要求，扩大工艺窗口，提升批量化生产良率。
附图3b是本发明的实施方式涉及的沟槽栅MOSFET的第二实施例的垂直截面图，本实施中的MOSFET与附图3a所示的MOSFET的区别在于，本实施中的栅电极13包括P型导电的电极材料（第2导电型的电极材料），即，栅电极13包括p型栅电极13b，p型栅电极13b可以是硼掺杂的p型导电的多晶硅，p型栅电极13b同样会对半导体区21中的电子载流子产生耗尽作用，加之由肖特基源电极12b与半导体区21构成的肖特基结同样会对位于栅绝缘膜51a和肖特基源电极12b之间的半导体区21中的电子载流子产生耗尽作用，当肖特基源电极12b距离栅绝缘膜51a的宽度范围介于3nm~250nm区间时，在这两种耗尽作用的共同作用下，将位于栅绝缘膜51a和肖特基源电极12b之间的半导体21中的电子载流子完全耗尽，从而阻断了漏电极11和源电极12之间的电子导电通道，因此附图3b所示的MOSFET能够实现常关，并且较之于附图2所示的MOSFET，在半导体区21的宽度一样的情况下，从电性能上，附图3a所示的MOSFET具有更低的关态漏电；从制程工艺上，要制作常关型MOSFET，附图3b中，位于栅绝缘膜51a和肖特基源电极12b之间的半导体21的宽度尺寸可以比附图2中设计的相对更宽，从而可降低对光刻&刻蚀技术和设备的要求，扩大工艺窗口，提升批量化生产良率。
附图3c是本发明的实施方式涉及的沟槽栅MOSFET的第三实施例的垂直截面图。附图3c所示的MOSFET是在附图3a所示的MOSFET结构的基础上，在半导体区21与欧姆源电极12a之间增设了n+型半导体21c。这样的设计，可以使欧姆接触的效果更好，减小欧姆源电极12a与半导体的接触电阻。
附图4a是本发明的实施方式涉及的平面栅MOSFET的第一实施例的垂直截面图。此MOSFET具有：漏电极11，n+型半导体21a，n-型半导体21b以及半导体区21，肖特基源电极12b，欧姆源电极12a以及位于其上的源电极12，栅绝缘膜51a以及位于其上的栅电极13，栅电极13包括肖特基栅电极13c，肖特基栅电极13c由金属材料组成。
附图4b是本发明的实施方式涉及的平面栅MOSFET的第二实施例的垂直截面图，本实施例中的MOSFET与附图4a所示MOSFET的区别在于，本实施中的栅电极13包括P型导电的电极材料，即，栅电极13包括p型栅电极13b，p型栅电极13b可以是硼掺杂的p型导电的多晶硅。
对于附图4a和附图4b所示的MOSFET，同样，由栅电极13和肖特基源电极12b对半导体区21中的电子载流子的共同耗尽作用，可制作常关型器件。其具有大的开态通流能力和低的关态漏电。
附图5a是本发明的实施方式涉及的屏蔽栅MOSFET的第一实施例的垂直截面图。附图5a所示的MOSFET是上下栅结构，具有：漏电极11，n+型半导体21a，n-型半导体21b，半导体区21（半导体区21可以是n-型半导体21b，也可以是高阻型半导体41），位于n-型半导体21b中的沟槽，位于沟槽中且被栅绝缘膜51a包裹的栅电极13和屏蔽源电极12c，与n-型半导体21b形成肖特基势垒接触的肖特基源电极12b，与半导体区21形成欧姆接触的欧姆源电极12a，以及位于其上的源电极12。其中，栅电极13包括肖特基栅电极13c和n型栅电极13a，n型栅电极13a可以是磷掺杂的n型导电的多晶硅；肖特基栅电极13c由金属材料组成。
附图5b是本发明的实施方式涉及的屏蔽栅MOSFET的第二实施例的垂直截面图。本实施中的MOSFET与附图5a所示MOSFET的区别在于，本实施例中，栅电极13包括P型导电的电极材料，即，栅电极13包括p型栅电极13b，所述p型栅电极13b可以是硼掺杂的p型导电的多晶硅。
附图5c是本发明的实施方式涉及的屏蔽栅MOSFET的第三实施例的垂直截面图。附图5c所示的MOSFET是左右分栅结构的屏蔽栅MOSFET，其是在附图5a所示的上下栅结构的屏蔽栅MOSFET的基础上，对屏蔽栅区域的结构进行设计调整。
附图5d是本发明的实施方式涉及的屏蔽栅MOSFET的第四实施例的垂直截面图。本实施例中的MOSFET是左右分栅结构的屏蔽栅MOSFET，其与附图5c所示的左右分栅结构的屏蔽栅MOSFET的区别在于，本实施例中，栅电极13包括P型导电的电极材料，即，栅电极13包括p型栅电极13b，p型栅电极13b可以是硼掺杂的p型导电的多晶硅。
附图5e是本发明的实施方式涉及的屏蔽栅MOSFET的第五实施例的垂直截面图。附图5e所示的MOSFET是另一种左右分栅结构的屏蔽栅MOSFET，其是在附图5c所示的左右分栅结构的屏蔽栅MOSFET的基础上，对屏蔽栅区域的结构进行设计调整。
附图5f是本发明的实施方式涉及的屏蔽栅MOSFET的第六实施例的垂直截面图。附图5e所示的MOSFET是另一种左右分栅结构的屏蔽栅MOSFET，本实施例中的MOSFET与附图5e所示的MOSFET的区别在于，本实施中的栅电极13包括P型导电的电极材料，即，栅电极13包括p型栅电极13b，p型栅电极13b可以是硼掺杂的p型导电的多晶硅。
附图5g是本发明的实施方式涉及的屏蔽栅MOSFET的第七实施例的垂直截面图。附图5g所示的MOSFET，具有：漏电极11，与漏电极11相接触的n+型半导体21a，n-型半导体21b，半导体区21（所述半导体区21可以是n-型半导体21b，也可以是高阻型半导体41），位于半导体区21上的n+型半导体21c，以及位于n-型半导体21b中的沟槽，位于沟槽中且被栅绝缘膜51a包裹的栅电极13和屏蔽源电极12c，与n-型半导体21b形成肖特基势垒接触的肖特基源电极12b，位于其上的与n+型半导体21c形成欧姆接触的欧姆源电极12a，以及位于其上的源电极12；其中，栅电极13包括肖特基栅电极13c和n型栅电极13a，n型栅电极可以是磷掺杂的n型导电的多晶硅，肖特基栅电极13c由金属材料组成。
附图5g所示的MOSFET是在附图5a所示MOSFET的基础上，对源电极区域的结构设计进行调整，使欧姆源电极12a与栅绝缘膜51a不接触，此结构设计同样能够达到减小关态漏电的功能。
对附图5a~5g所示的屏蔽栅MOSFET，栅电极13不论是采用肖特基栅电极13c亦或是p型栅电极13b，都可以借助栅电极13和肖特基源电极12b对半导体区21（所述半导体区21可以是n-型半导体21b，也可以是高阻型半导体41）中的电子载流子的共同耗尽作用来实现更好的常关效果，更小的关态漏电；另外，可放宽制程工艺中对关键尺寸例如半导体区21宽度的要求，扩大工艺窗口，提升制程良率。
对于对附图5a~5g所示的屏蔽栅MOSFET，当肖特基源电极12b以及肖特基栅电极13c采用的金属材料的功函数越高，在保持常关功能的前提下，半导体区21的宽度就相对越宽，例如可以采用Pt、Ni、Au、Co、Cu、Fe等具有高功函数的金属材料。
附图6a是本发明的实施方式涉及的超结MOSFET的第一实施例的垂直截面图。附图6a所示的超结MOSFET，具有：漏电极11，n+型半导体21a，n-型半导体21b，半导体区21（所述半导体区21可以是n-型半导体21b，也可以是高阻型半导体41），位于n-型半导体21b中的深沟槽以及位于深沟槽中的p型多晶硅12d，肖特基源电极12b，欧姆源电极12a以及源电极12，栅绝缘膜51a以及位于其上的肖特基栅电极13c，肖特基栅电极13c由金属材料组成。
附图6b是本发明的实施方式涉及的超结MOSFET的第二实施例的垂直截面图。本实施例与附图6a所示的超结MOSFET的区别在于，本实施中的栅电极13包括P型导电的电极材料，即，栅电极13包括p型栅电极13b。
对附图6a和附图6b所示的超结MOSFET，不论是采用肖特基栅电极13c或是p型栅电极13b，都可以借助栅电极13和肖特基源电极12b对半导体区21（所述半导体区21可以是n-型半导体21b，也可以是高阻型半导体41）中的电子载流子的共同耗尽作用来实现更好的常关效果，更小的关态漏电；另外，可放宽对制程工艺中对关键尺寸例如半导体区21宽度的要求，扩大工艺窗口，提升制程良率。
附图7a是本发明的实施方式涉及的沟槽MOS型二极管的第一实施例的垂直截面图。其包括：阴极电极61，n型半导体层（包括n+型半导体21a和n-型半导体21b），半导体区21（半导体区21可以是n-型半导体，也可以是高阻型半导体），位于n-型半导体21b中的沟槽，位于沟槽中且被栅绝缘膜51a包裹的沟槽MOS栅极63，与n-型半导体21b接触形成肖特基势垒接触的肖特基阳极62b，与半导体区21接触形成欧姆接触的欧姆阳极62a，位于其上的阳极电极62，所述沟槽MOS栅极63与所述阳极电极62电连接。其中，n-型半导体21b沟槽MOS栅极63包括n型栅极63a和肖特基栅极63c，n型栅极63a可以是n型导电的多晶硅，肖特基栅极63c与栅绝缘膜51a接触，肖特基栅电极63c由金属材料组成。本实施例中，n型半导体层具有一侧的第一主面211以及与之相反的另一侧的第二主面212，沟槽从n型半导体层的第一主面211上向内开口。
附图7a所示的沟槽MOS型二极管，当在阳极电极62和阴极电极61之间施加正电压时，在阳极电极62和阴极电极61之间会有电流流过，二极管正向导通。电流的路径有两条：第一条电流路径是沿着阳极电极62—欧姆阳极62a—半导体区21—n-型半导体21b—n+型半导体21a—阴极电极61；第二条电流路径是沿着阳极电极62—肖特基阳极62b—n-型半导体21b—n+型半导体21a—阴极电极61。在第一条电流路径中，欧姆阳极62a与半导体区21之间无接触势垒；在第二条电流路径中，肖特基阳极62b与n-型半导体21b之间存在肖特基势垒；在二极管正向导通时，由于第一条电流路径的阻碍相对较小，需要的开启电压比第二条电流路径更低，因此电流优先从第一条电流路径流过。相较于传统的沟槽MOS型肖特基二极管，很显然，基于本发明的沟槽MOS型二极管有着更低开启电压和导通损耗。
附图7a所示的沟槽MOS型二极管中，当在阳极电极62和阴极电极61之间施加反向电压时，存在着两类电子载流子的耗尽作用：第一类是肖特基阳极62b与n-型半导体21b和半导体区21形成的肖特基势垒反偏展宽，对n-型半导体21b的电子载流子产生纵向耗尽作用，对半导体区21中的电子载流子产生横向耗尽作用；第二类是沟槽MOS栅极63对半导体区21中的电子载流子产生横向耗尽作用。在这两类耗尽作用的共同作用下，在阴极电极61和阳极电极62之间仅有很小的漏电流通过，二极管反向截止。
附图7b是本发明的实施方式涉及的沟槽MOS型二极管的第二实施例的垂直截面图。本实施中的沟槽MOS型二极管与附图7a所示沟槽MOS型二极管的区别在于，本实施中的沟槽MOS栅极63包括P型导电的电极材料，即，沟槽MOS栅极63包括p型栅极63b。在正向导通时，同样存在着两条电流路径，相对于传统的沟槽MOS型肖特基二极管，同样会有相对更低的开启电压和导通损耗。
附图8a是本发明的实施方式涉及的绝缘栅双极型晶体管的第一实施例的垂直截面图。其具有：集电极11，p+型半导体31a，n+型半导体21a，n-型半导体21b，半导体区21（所述半导体区21可以是n-型半导体21b，也可以是高阻型半导体41），位于n-型半导体21b中的沟槽，位于沟槽中且被栅绝缘膜包裹的栅电极13，与n-型半导体21b接触形成肖特基势垒接触的肖特基发射极12b，与n-型半导体21b接触形成欧姆接触的欧姆发射极12a，以及位于其上的发射极12。其中，栅电极13包括肖特基栅电极13c和n型栅电极13a，肖特基栅电极13c由金属材料组成。
在附图8a所示的绝缘栅双极型晶体管中，在栅电极13中引入与半导体区21之间存在肖特基势垒的肖特基栅电极13c，由肖特基栅电极13c、栅绝缘膜51a以及半导体区21三者构成的MIS（金属绝缘体半导体）结会对位于栅绝缘膜51a和肖特基发射极12b之间的半导体21中的电子载流子产生耗尽作用，加之由肖特基发射极12b与半导体区21构成的肖特基结同样会对位于栅绝缘膜51a和肖特基源电极12b之间的半导体区21中的电子载流子产生耗尽作用，当肖特基发射极12b距离栅绝缘膜51a的宽度范围介于3nm~250nm区间时，在这两种耗尽作用的共同作用下，将位于栅绝缘膜51a和肖特基发射极12b之间的半导体区21中的电子载流子完全耗尽，从而阻断了集电极11和发射极12之间的电子载流子导电通道，通过两种耗尽作用共同作用这样的设计，可以减小器件的关态漏电。
附图8b是本发明的实施方式涉及的绝缘栅双极型晶体管的第二实施例的垂直截面图。本实施例中的绝缘栅双极型晶体管与附图8a所示绝缘栅双极型晶体管的区别在于，本实施中，栅电极13包括P型导电的电极材料，即，电极13包括p型栅电极13b，所述p型栅电极13b可以是硼掺杂的p型导电的多晶硅，p型栅电极13b同样会对半导体区21中的电子载流子产生耗尽作用，加之由肖特基发射极12b与半导体区21构成的肖特基结同样会对位于栅绝缘膜51a和肖特基发射极12b之间的半导体区21中的电子载流子产生耗尽作用，当肖特基发射极12b距离栅绝缘膜51a的宽度范围介于3nm~250nm区间时，在这两种耗尽作用的共同作用下，将半导体区21中的载流子完全耗尽，从而阻断了集电极11和发射极12之间的电子载流子导电通道，通过两种耗尽作用共同作用这样的设计，可以减小器件的关态漏电。
对于本发明的各实施例所示的MOSFET，都是基于电子载流子参与导电的n沟道型MOSFET，本发明技术方案的精髓对于基于空穴载流子参与导电的p沟道型MOSFET同样适用。
本发明中，没有对半导体的材料做具体限定，所示半导体的材料可以是单质半导体例如锗、硅等；所示半导体的材料可以是化合物半导体例如碳化硅、氮化镓、氧化镓、氧化锡等。
应当理解的是，以上所述实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精髓和范围，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种场效应晶体管，包括：
    第1导电型的半导体层；
    电极，其包括漏电极、源电极以及栅电极；
    栅绝缘膜，其介于所述栅电极和所述第1导电型的半导体层之间；
    其特征在于：
    所述源电极的第一部分与所述第1导电型的半导体层之间存在肖特基势垒，所述源电极的第一部分和所述栅绝缘膜未接触；所述源电极的第二部分与所述第1导电型的半导体层形成欧姆接触；
    所述栅电极至少包括与所述第1导电型的半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述栅电极至少包括第2导电型的电极材料，所述第2导电型的电极材料与所述栅绝缘膜接触，其中，所述第2导电型和所述第1导电型的导电类型不同。
  2. 根据权利要求1所述的场效应晶体管，其特征在于，所述第1导电型是n型，所述第2导电型是p型。
  3. 根据权利要求1所述的场效应晶体管，其特征在于，所述源电极的第一部分与所述第1导电型的半导体层接触形成肖特基接触。
  4. 根据权利要求1所述的场效应晶体管，其特征在于，所述源电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
  5. 根据权利要求1所述的场效应晶体管，其特征在于，所述源电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
  6. 根据权利要求1所述的场效应晶体管，其特征在于，所述场效应晶体管是横式半导体元件或纵式半导体元件。
  7. 一种沟槽MOS型二极管，包括：
    n型半导体层，其具有一侧的第一主面以及与之相反的另一侧的第二主面，所述n型半导体层设有沟槽，所述沟槽从所述n型半导体层的所述第一主面上向内开口；
    阴极电极，其形成于所述n型半导体层的所述第二主面上；
    阳极电极，其形成于所述n型半导体层的所述第一主面上；
    沟槽MOS栅极，其埋入所述沟槽内并被栅绝缘膜包裹，所述沟槽MOS栅极与所述n型半导体层之间隔着所述栅绝缘膜且所述沟槽MOS栅极与所述阳极电极接触；
    其特征在于：
    所述阳极电极的第一部分与所述n型半导体层的所述第一主面形成肖特基接触，所述阳极电极的第二部分与所述n型半导体层的所述第一主面接触形成欧姆接触；
    所述沟槽MOS栅极至少包括与所述n型半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述沟槽MOS栅极至少包括p型导电的电极材料，所述p型导电的电极材料与所述栅绝缘膜接触；
    所述阳极电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
  8. 根据权利要求7所述的沟槽MOS型二极管，其特征在于，所述阳极电极的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
  9. 一种绝缘栅双极型晶体管，包括：
    p型半导体层；
    层叠于所述p型半导体层之上的n型半导体层；
    电极，其包括集电极、发射极以及栅电极，所述集电极形成于所述p型半导体层的与所述n型半导体层相反的一侧的面上；
    栅绝缘膜，其介于所述栅电极和所述n型半导体层之间；
    其特征在于：
    所述发射极的第一部分与所述n型半导体层之间存在肖特基势垒，所述发射极的第一部分与所述栅绝缘膜未接触，所述发射极的第二部分与所述n型半导体层形成欧姆接触；
    所述栅电极至少包括与所述n型半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述栅电极采用p型导电的电极材料制成，所述p型导电的电极材料与所述栅绝缘膜接触。
  10. 根据权利要求9所述的绝缘栅双极型晶体管，其特征在于，所述发射极的第一部分与所述n型半导体层接触形成肖特基接触。
  11. 根据权利要求9所述的绝缘栅双极型晶体管，其特征在于，所述发射的第一部分距离所述栅绝缘膜的宽度范围介于3nm~400nm区间。
  12. 根据权利要求9所述的绝缘栅双极型晶体管，其特征在于，所述发射的第一部分距离所述栅绝缘膜的宽度范围介于3nm~200nm区间。
  13. 一种场效应晶体管，包括：
    第1半导体层，其包括n型半导体区；
    第2半导体层，其包括n型半导体区以及高阻型半导体区；
    电极，其包括漏电极、源电极以及栅电极；
    栅绝缘膜，其介于所述栅电极和半导体层之间；
    其特征在于：
    所述漏电极，其形成于所述第1半导体层的与所述第2半导体层相反的一侧的面上；
    所述源电极，其形成于所述第2半导体层的与所述第1半导体层相反的一侧的面上，所述源电极的第一部分与所述第2半导体层的所述n型半导体区之间存在肖特基势垒，所述源电极的第一部分与所述栅绝缘膜未接触；所述源电极的第二部分与所述第2半导体层的所述n型半导体区接触形成欧姆接触；
    所述第2半导体层的所述高阻型半导体区，其设置在靠近所述第2半导体层的表层的区域，其形成于所述栅绝缘膜和所述源电极的第一部分之间；
    所述栅电极至少包括与所述第2半导体层之间存在肖特基势垒的金属材料，所述金属材料与所述栅绝缘膜接触；或所述栅电极采用p型导电的电极材料制成，所述p型导电的电极材料与所述栅绝缘膜接触。
  14. 根据权利要求13所述的场效应晶体管，其特征在于，所述源电极的第一部分与所述第2半导体层的所述n型半导体区接触形成肖特基势垒。
PCT/CN2024/105467 2023-07-10 2024-07-15 场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管 Ceased WO2025011663A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202310844747.4A CN119317126A (zh) 2023-07-10 2023-07-10 场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管
CN202310844747.4 2023-07-10

Publications (1)

Publication Number Publication Date
WO2025011663A1 true WO2025011663A1 (zh) 2025-01-16

Family

ID=94185022

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2024/105467 Ceased WO2025011663A1 (zh) 2023-07-10 2024-07-15 场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管

Country Status (2)

Country Link
CN (1) CN119317126A (zh)
WO (1) WO2025011663A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590595A (ja) * 1991-09-27 1993-04-09 Nissan Motor Co Ltd 半導体装置
JPH05267674A (ja) * 1992-03-23 1993-10-15 Nissan Motor Co Ltd 半導体装置
JPH09102602A (ja) * 1995-10-05 1997-04-15 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓｆｅｔ
KR20100122280A (ko) * 2009-05-12 2010-11-22 주식회사 케이이씨 쇼트키 배리어 다이오드 내장 트렌치 ｍｏｓｆｅｔ 및 그 제조 방법
CN115332354A (zh) * 2022-08-26 2022-11-11 电子科技大学 优化短路电流耐受能力的碳化硅mosfet结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590595A (ja) * 1991-09-27 1993-04-09 Nissan Motor Co Ltd 半導体装置
JPH05267674A (ja) * 1992-03-23 1993-10-15 Nissan Motor Co Ltd 半導体装置
JPH09102602A (ja) * 1995-10-05 1997-04-15 Nippon Telegr & Teleph Corp <Ntt> Ｍｏｓｆｅｔ
KR20100122280A (ko) * 2009-05-12 2010-11-22 주식회사 케이이씨 쇼트키 배리어 다이오드 내장 트렌치 ｍｏｓｆｅｔ 및 그 제조 방법
CN115332354A (zh) * 2022-08-26 2022-11-11 电子科技大学 优化短路电流耐受能力的碳化硅mosfet结构

Also Published As

Publication number Publication date
CN119317126A (zh) 2025-01-14

Similar Documents

Publication Publication Date Title
US8049223B2 (en) Semiconductor device with large blocking voltage
US8390029B2 (en) Semiconductor device for reducing and/or preventing current collapse
Im et al. Normally Off Single-Nanoribbon $\hbox {Al} _ {2}\hbox {O} _ {3}\hbox {/GaN} $ MISFET
CN101273458B (zh) 增强模式ⅲ族氮化物场效应晶体管
CN103930997B (zh) 具有凹陷电极结构的半导体器件
US6914273B2 (en) GaN-type enhancement MOSFET using hetero structure
JP4755961B2 (ja) 窒化物半導体装置及びその製造方法
US8779438B2 (en) Field-effect transistor with nitride semiconductor and method for fabricating the same
US7355254B2 (en) Pinning layer for low resistivity N-type source drain ohmic contacts
US20060219997A1 (en) Semiconductor device and fabrication method of the same
JP4039376B2 (ja) 半導体装置
JP2015065453A (ja) 半導体装置、電界効果トランジスタおよび電子装置
US9543425B2 (en) Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate
WO2022127165A1 (zh) P型栅hemt器件
US20200227543A1 (en) High electron mobility transistor (hemt) with resurf junction
JP2011142358A (ja) 窒化物半導体装置
US11894454B2 (en) Silicon carbide field-effect transistors
JP2013239735A (ja) 電界効果トランジスタ
WO2020031636A1 (ja) 半導体装置および半導体装置の製造方法
WO2024198439A1 (zh) 场效应晶体管、绝缘栅双极型晶体管及沟槽mos型二极管
WO2025011663A1 (zh) 场效应晶体管、沟槽mos型二极管及绝缘栅双极型晶体管
Im et al. First demonstration of heterojunction-free GaN nanochannel FinFETs
JP3376294B2 (ja) 半導体装置
CN118136679B (zh) 基于异质结二维电子气的双栅ldmos器件及制造方法
CN119789511B (zh) 一种平面栅GaN垂直互补场效应晶体管反相器

Legal Events

Date Code Title Description
NENP Non-entry into the national phase

Ref country code: DE