WO2024259940A1 - 交换芯片的时钟控制方法，系统和设备，以及交换板 - Google Patents

交换芯片的时钟控制方法，系统和设备，以及交换板 Download PDF

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Publication number
WO2024259940A1
WO2024259940A1 PCT/CN2023/141950 CN2023141950W WO2024259940A1 WO 2024259940 A1 WO2024259940 A1 WO 2024259940A1 CN 2023141950 W CN2023141950 W CN 2023141950W WO 2024259940 A1 WO2024259940 A1 WO 2024259940A1
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Prior art keywords
clock
signal
target
type
target device
Prior art date
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Ceased
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PCT/CN2023/141950
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English (en)
French (fr)
Inventor
张涛
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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Application filed by Suzhou Metabrain Intelligent Technology Co Ltd filed Critical Suzhou Metabrain Intelligent Technology Co Ltd
Priority to US19/116,159 priority Critical patent/US12481308B2/en
Publication of WO2024259940A1 publication Critical patent/WO2024259940A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/109—Integrated on microchip, e.g. switch-on-chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present application relate to the field of chips, and in particular, to a clock control method, system and device for a switching chip, and a switching board.
  • CXL (Compute Express Link) technology is a cache-coherent interconnect protocol based on the PCIe 5.0 (Peripheral Component Interconnect Express 5.0, a high-speed serial computer expansion bus standard (fifth generation)) physical bus.
  • PCIe 5.0 Peripheral Component Interconnect Express 5.0
  • CXL technology not only supports use in processors, memory expansion and accelerators, but also allows resource sharing for higher performance.
  • the industry has launched the CXL 2.0 (Compute Express Link 2.0) protocol, which introduces the SW (switch) function, supports connecting more devices, and allows the server to allocate corresponding resources according to workload requirements, thereby improving resource utilization and reducing overall system costs.
  • CXL SW Computer Express Link switch
  • PCIe Peripheral Component Interconnect Express
  • the relevant technology generally manually selects the clock mode according to the different inserted devices, but this method is inefficient, and the co-source clock is generally connected through a cable, and the link is long. If the quality of the selected co-source clock signal is poor, it is easy to cause the device to not be recognized by the CPU (Central Processing Unit).
  • CPU Central Processing Unit
  • the embodiments of the present application provide a clock control method, system and device for a switching chip, as well as a switching board, to at least solve the problem of low clock adaptation efficiency of the switching chip in the related art.
  • a clock control device for a switching chip comprising: a clock controller and a clock selector, wherein the clock controller is connected to the clock selector, the clock selector allows the connection of clock generators of multiple clock types, a switching chip and a target device, the switching chip uses different clock types of clock signals when controlling target devices belonging to different device types, and the multiple clock types correspond to the multiple device types; the clock controller is configured to identify the target device type to which the target device belongs among the multiple device types; the clock selector is controlled to transmit the target clock signal transmitted by the target clock generator among the multiple clock types to the switching chip and the target device, wherein the target clock generator is a clock generator of the target clock type corresponding to the target device type.
  • a first control port is deployed on the clock controller, and multiple clock ports, a first output port, a second output port and a first signal port are deployed on the clock selector, wherein the first control port is connected to the first signal port, the multiple clock ports are configured to respectively connect to clock generators of multiple clock types, the first output port is configured to connect to a switching chip, and the second output port is configured to connect to a target device; the clock controller is configured to generate a target control signal corresponding to the target device type; the target control signal is sent to the clock selector through the first control port; the clock selector is configured to receive the target control signal through the first signal port; and the target clock signal received on the target clock port corresponding to the target control signal is transmitted to the first output port and the second output port.
  • a device type port is deployed on the clock controller, wherein the device type port allows connection with a processor, and the device type port is configured to receive a target device type sent by the processor.
  • the clock control device further includes: a clock buffer, wherein the clock controller is connected to the clock buffer.
  • the clock buffer is also connected between a reference clock generator and a clock selector in a clock generator of multiple clock types; the reference clock generator is configured to generate multiple clock signals; the clock buffer is configured to cache multiple clock signals; the clock controller is configured to collect signal parameters of the multiple clock signals; the signal quality of each clock signal in the multiple clock signals is determined according to the signal parameters; and the clock buffer is controlled to transmit the reference clock signal with the highest signal quality to the clock selector.
  • a second control port is deployed on the clock controller, and multiple reference clock ports, a third output port and a second signal port are deployed on the clock buffer, wherein the second control port is connected to the second signal port, the multiple reference clock ports are configured to be connected to a reference clock generator, and the third output port is configured to be connected to a clock selector; the clock controller is configured to generate a reference control signal corresponding to a reference clock signal; the reference control signal is sent to the clock buffer through the second control port; the clock buffer is configured to receive the reference control signal through the second signal port; and the reference clock signal corresponding to the reference control signal is transmitted to the third output port.
  • the clock control device also includes: a signal collector, wherein the signal collector is connected between a reference clock generator and a clock controller; the signal collector is configured to sample multiple clock signals to obtain multiple sampling signals; the multiple sampling signals are transmitted to the clock controller; the clock controller is configured to calculate signal parameters of the multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameter, frequency parameter, slope parameter, jitter parameter; and the signal parameters of each sampling signal are converted into the signal quality of each sampling signal.
  • a clock control device includes: a clock controller and a clock selector, wherein the clock controller is connected to the clock selector, and the clock selector allows the connection of clock generators of various clock types, switching chips and target devices; the clock controller is configured to generate a target control signal corresponding to the target device type; send the target control signal to the clock selector; the clock selector is configured to receive the target control signal; and transmit the target clock signal corresponding to the target control signal to the switching chip and the target device.
  • a clock generator of multiple clock types includes: a first clock generator of a homologous type and a second clock generator of a non-homologous type, wherein a clock selector is connected to the first clock generator and the second clock generator, respectively, the first clock generator is configured to transmit a homologous clock signal, and the second clock generator is configured to transmit a non-homologous clock signal; a clock controller is configured to generate a first control signal when the target device type is a first type, wherein the first type is a device type that adopts a high-speed serial computer expansion bus standard; and to generate a second control signal when the target device type is a second type, wherein the second type is a device type that adopts a computer fast connection protocol; a first control signal or a second control signal is sent to the clock selector; the clock selector is configured to transmit the homologous clock signal to the switching chip and the target device when the first control signal is received; and to transmit the non-homologous clock signal to the switching chip
  • a reference clock generator among clock generators of multiple clock types allows generation of multiple clock signals, wherein a clock control device is configured to cache multiple clock signals and collect signal parameters of the multiple clock signals; determine the signal quality of each clock signal in the multiple clock signals based on the signal parameters; and determine the reference clock signal with the highest signal quality as the clock signal corresponding to the reference clock generator.
  • a clock control device includes: a clock controller, a clock selector and a clock buffer, wherein the clock controller is connected to the clock selector, the clock selector allows the connection of clock generators of various clock types, switching chips and target devices, and the clock buffer is connected between the reference clock generator and the clock selector; the clock controller is configured to generate a reference control signal corresponding to a reference clock signal; send the reference control signal to the clock buffer; generate a target control signal corresponding to the target device type; send the target control signal to the clock selector; the clock buffer is configured to receive the reference control signal; transmit the reference clock signal corresponding to the reference control signal to the clock selector; the clock selector is configured to receive the target control signal; and transmit the target clock signal corresponding to the target control signal to the switching chip and the target device.
  • the clock control device is further configured to: sample multiple clock signals to obtain multiple sampling signals; calculate signal parameters of the multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameter, frequency parameter, slope parameter, jitter parameter; convert the signal parameters of each sampling signal into the signal quality of each sampling signal.
  • a clock control device allows connection with a processor, wherein the clock control device is configured to receive a target device type sent by the processor.
  • a clock control system of a switching chip comprising: a switching board and a device board, wherein a switching chip and a clock control device are deployed on the switching board, and a device interface is deployed on the device board; the device interface is configured to connect a target device, wherein the clock type of the clock signal used by the switching chip when controlling target devices of different device types is different, and multiple clock types The type corresponds to multiple device types; a clock control device is configured to identify the target device type to which the target device belongs among the multiple device types; and a target clock signal transmitted by a target clock generator among the clock generators of the multiple clock types is transmitted to the switching chip and the target device, wherein the target clock generator is a clock generator of the target clock type corresponding to the target device type.
  • the system also includes: a main board, wherein a third clock generator is also deployed on the switching board, a fourth clock generator of the processor is deployed on the main board, and a clock control device includes: a clock controller and a clock selector; the clock controller is connected to the clock selector, the clock selector is connected to the third clock generator, the fourth clock generator, the switching chip and the target device, the third clock generator is configured to transmit non-homologous clock signals, and the fourth clock generator is configured to transmit homologous clock signals; the clock controller is configured to generate a first control signal when the target device type is a first type, wherein the first type is a device type using a high-speed serial computer expansion bus standard; when the target device type is a second type, a second control signal is generated, wherein the second type is a device type using a computing fast connection protocol; the first control signal is sent to the clock selector, or the second control signal; the clock selector is configured to transmit the homologous clock signal to the switching chip and the target device
  • a processor is also deployed on the main board, and the clock control device is connected to the processor, wherein the processor is connected to the target device through a switch board and a device board; the processor is configured to output the target device type of the target device during the training process of the target device; the target device type is sent to the clock control device; and the clock control device is configured to receive the target device type sent by the processor.
  • a clock control method for a switching chip which is applied to a clock control device, and the method includes:
  • a target clock signal transmitted by a target clock generator among clock generators of multiple clock types is transmitted to a switching chip and a target device, wherein the target clock generator is a clock generator of a target clock type corresponding to the target device type.
  • transmitting a target clock signal transmitted by a target clock generator among clock generators of multiple clock types to a switching chip and a target device includes:
  • the target clock signal corresponding to the target control signal is transmitted to the switching chip and the target device.
  • a clock generator of multiple clock types includes: a first clock generator of a homologous type and a second clock generator of a non-homologous type, the first clock generator being configured to transmit a homologous clock signal, and the second clock generator being configured to transmit a non-homologous clock signal;
  • the target clock signal corresponding to the target control signal is transmitted to the switching chip and the target device, including: when a first control signal is received, the homologous clock signal is transmitted to the switching chip and the target device; when a second control signal is received, the non-homologous clock signal is transmitted to the switching chip and the target device.
  • a reference clock generator among clock generators of multiple clock types is configured to generate multiple clock signals, wherein receiving the clock signals transmitted by the clock generators of multiple clock types includes:
  • the reference clock signal with the highest signal quality is determined as the clock signal transmitted by the reference clock generator.
  • collecting signal parameters of a plurality of clock signals includes:
  • Signal parameters of a plurality of sampling signals are calculated, wherein the signal parameter of each sampling signal includes at least one of the following: an amplitude parameter, a frequency parameter, a slope parameter, and a jitter parameter.
  • identifying a target device type to which a target device belongs among a plurality of device types includes:
  • a clock control device for a switching chip including:
  • a receiving module is configured to receive clock signals transmitted by clock generators of multiple clock types, wherein the clock control device is connected to the switching chip, the switching chip uses different clock types of clock signals when controlling target devices of different device types, and the multiple clock types correspond to the multiple device types;
  • an identification module configured to identify a target device type to which the target device belongs among multiple device types
  • the transmission module is configured to transmit a target clock signal transmitted by a target clock generator among clock generators of multiple clock types to a switching chip and a target device, wherein the target clock generator is a clock generator of a target clock type corresponding to the target device type.
  • a non-volatile readable storage medium in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
  • an electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock signal. Therefore, the problem of low clock adaptation efficiency of the switching chip can be solved, and the effect of improving the clock adaptation efficiency of the switching chip is achieved.
  • FIG1 is a schematic diagram 1 of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG2 is a second schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG3 is a third schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG4 is a fourth schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG5 is a fifth schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG6 is a sixth schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG7 is a seventh schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • FIG8 is a schematic diagram of a switch board according to an embodiment of the present application.
  • FIG9 is a schematic diagram of a working process of a switch board according to an embodiment of the present application.
  • FIG10 is a schematic diagram of a mainboard on which a clock generator is deployed according to an embodiment of the present application
  • FIG11 is a schematic diagram of a device board on which a target device is deployed according to an embodiment of the present application
  • FIG. 12 is a schematic diagram of a clock control system of a switching chip according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a clock control process in a clock control system of a switching chip according to an optional implementation manner of the present application;
  • FIG. 14 is a hardware structure block diagram of a mobile terminal of a clock control method for a switching chip according to an embodiment of the present application
  • 15 is a flow chart of clock control of a switching chip according to an embodiment of the present application.
  • 16 is a schematic diagram of a clock control process in a clock control system of a switching chip according to an optional implementation manner of the present application;
  • FIG. 17 is a structural block diagram of a clock control device for a switching chip according to an embodiment of the present application.
  • FIG. 18 is a schematic diagram of an electronic device according to an embodiment of the present application.
  • FIG1 is a schematic diagram of a clock control device for a switching chip according to an embodiment of the present application.
  • the clock control device for the switching chip may include: a clock controller 102 and a clock selector 104, wherein the clock controller 102 is connected to the clock selector 104, the clock selector 104 allows the connection of clock generators (106-1 to 106-n) of multiple clock types, a switching chip 108 and a target device 110, the switching chip 108 uses different clock types of clock signals when controlling target devices 110 of different device types, and the multiple clock types correspond to the multiple device types;
  • the clock controller 102 is configured to identify the type of target device 110 to which the target device 110 belongs among the multiple device types;
  • the clock selector 104 is controlled to transmit the target clock signal transmitted by the target clock generator among the multiple clock types to the switching chip 108 and the target device 110, wherein the target clock generator is a clock generator of the target clock type corresponding to the type of
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock.
  • Signal therefore, can solve the problem of low clock adaptation efficiency of the switching chip, and achieve the effect of improving the clock adaptation efficiency of the switching chip.
  • the above-mentioned clock control device is configured to receive clock signals transmitted by clock generators of multiple types, and select a clock signal corresponding to the target device from the multiple clock signals and transmit it to the switching chip and the target device, so that the switching chip can use the corresponding clock type when controlling target devices of different device types.
  • the above-mentioned clock control device may include but is not limited to a clock controller and a clock selector, and may implement the functions of the clock control device through multiple devices within the clock control device, such as: obtaining the target device type to which the target device belongs among multiple device types through the clock controller, and controlling the clock selector according to the target device type to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device.
  • the clock controller may control the clock selector to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device by controlling the level of the output target control signal, for example, when the target control signal outputs a low level, it is used to instruct the clock selector to select the same source clock. Or, when the target control signal outputs a high level, it is used to instruct the clock selector to select a non-same source clock.
  • the clock generator may be, but is not limited to, a device capable of generating and transmitting a clock signal, such as an External Crystal Oscillator (XTAL) and a crystal oscillator, etc.
  • the clock type of the clock generator may be, but is not limited to, a homologous clock and a non-homologous clock.
  • the clock generator may be, but is not limited to, a device capable of simultaneously sending multiple clock signals, for example, the clock control device receives multiple clock signals sent by the same clock generator and multiple clock signals sent by another clock generator of a different clock type. Alternatively, the clock control device receives multiple clock signals sent by the same clock generator and a single clock signal sent by another clock generator of a different clock type.
  • the switching chip may be, but is not limited to, a device having a function of controlling a target device, such as a CXL SW chip.
  • the clock type used by the switching chip may be, but is not limited to, determined according to the device type of the target device, such as, when the target device type of the target device is a PCIe device, the clock type used by the switching chip is determined to be a homologous clock. Alternatively, when the target device type of the target device is a CXL device, the clock type used by the switching chip is determined to be a non-homologous clock.
  • FIG. 2 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • a first control port 202 is deployed on the clock controller 102, and a plurality of clock ports (204-1 to 204-n) are deployed on the clock selector 104, a first output port 206, a second output port 208 and a first signal port 210, wherein the first control port 202 is connected to the first signal port 210, and the plurality of clock ports (204-1 to 204-n) are used to respectively connect clock generators (106-1 to 106-n) of a plurality of clock types.
  • the first output port 206 is configured to connect to the switching chip 108, and the second output port 208 is configured to connect to the target device 110;
  • the clock controller 102 is configured to generate a target control signal corresponding to the type of the target device 110;
  • the target control signal is sent to the clock selector 104 through the first control port 202;
  • the clock selector 104 is configured to receive the target control signal through the first signal port 210; and the target clock signal received on the target clock port 212 corresponding to the target control signal is transmitted to the first output port 206 and the second output port 208.
  • the clock controller may be but is not limited to being deployed with multiple ports, and may be but is not limited to being connected to a clock selector through a first control port deployed on the clock controller.
  • the clock controller may send a signal to the clock selector through the first control port to control the clock selector to transmit the target clock signal transmitted by the target clock generator among clock generators of multiple clock types to the switching chip and the target device.
  • the clock selector may be provided with multiple ports including but not limited to: multiple clock ports, a first output port, a second output port, a first signal port, and the like.
  • the multiple clock ports deployed on the clock selector are connected to clock generators of various clock types, and can be used for, but not limited to, receiving clock signals sent by clock generators of various clock types.
  • the first output port deployed on the clock selector is connected to the switching chip, and can be used, but not limited to, to send a clock signal corresponding to the target device to the switching chip.
  • the second output port disposed on the clock selector is connected to the target device, and can be used, but not limited to, to send a clock signal corresponding to the target device to the target device.
  • the first control port deployed on the clock controller is connected to the clock selector, which can be used, but not limited to, to send a target control signal to the clock selector.
  • the clock controller generates a corresponding target control signal according to the target device type of the target device, and then transmits the target control signal to the clock selector through the first control port.
  • the first signal port deployed on the clock selector is connected to the clock controller, and can be used but not limited to receiving a target control signal issued by the clock controller, for example: the clock controller transmits the target control signal through the first control port, and the clock selector receives the target control signal through the first signal port.
  • Figure 3 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • multiple clock ports (204-1 to 204-n) include a first clock port 302 and a second clock port 304, wherein the first clock port 302 allows connection with a first clock generator 306 of the same source type, and the second clock port 304 allows connection with a second clock generator 308 of a non-homologous type.
  • the first clock generator 306 is configured to transmit a homologous clock signal, and the second clock generator 308 is configured to transmit a non-homologous clock signal; the clock controller 102 is configured to generate a first control signal when the target device 110 type is the first type, wherein the first clock port 302 allows connection with a first clock generator 306 of the same source type, and the second clock port 304 allows connection with a second clock generator 308 of a non-homologous type.
  • the first clock generator 306 is configured to transmit a homologous clock signal, and the second clock generator 308 is configured to transmit a non-homologous clock signal.
  • One type is a device type that adopts a high-speed serial computer expansion bus standard; when the target device 110 type is a second type, a second control signal is generated, wherein the second type is a device type that adopts a computer fast connection protocol; a first control signal or a second control signal is sent to the clock selector 104 through the first control port 202; the clock selector 104 is configured to transmit a homologous clock signal to the first output port 206 and the second output port 208 when the first control signal is received; and to transmit a non-homologous clock signal to the first output port 206 and the second output port 208 when the second control signal is received.
  • multiple clock ports of the clock controller are configured to connect clock generators of multiple clock types.
  • the clock ports may include but are not limited to a first clock port and a second clock port.
  • the clock types of the clock generators connected to the first clock port and the second clock port are different.
  • the first clock generator is connected to the clock controller via a first clock port, and the first clock port is configured to receive a homologous clock signal emitted by the first clock generator.
  • the second clock generator is connected to the clock controller via a second clock port, and the second clock port is configured to receive a non-homologous clock signal emitted by the second clock generator.
  • the first control signal is used to transmit the homologous clock signal to the first output port and the second output port
  • the second control signal is used to transmit the non-homologous clock signal to the first output port and the second output port.
  • Figure 4 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • a device type port 402 is deployed on the clock controller 102, wherein the device type port 402 allows connection with a processor 404, and the device type port 402 is set to receive the target device type sent by the processor 404.
  • the above-mentioned processor can be but is not limited to being deployed on a motherboard connected to the clock control device, and the above-mentioned processor can be but is not limited to reading the target device type of the target device through the bus, for example: the processor reads the target device of the PCIe slot or the CXL slot through the PCIe bus, and sends the target device type of the target device to the clock control device.
  • a device type port is also deployed on the clock controller, and the device type port can be but is not limited to being set to connect to a processor deployed on the mainboard, and receive the target device type sent by the processor of the mainboard through the device type port.
  • the clock control device may determine the target device type of the target device according to the data received from the processor, but is not limited to, for example, taking 0x50 and 0x56 to indicate that the target device type is a PCIe device, when the clock control device receives 0x50 and 0x56 continuously, it can be determined that the target device type of the target device among multiple device types is a PCIe device. Or, taking 0x27 and 0x29 to indicate that the target device type is a CXL device, when the clock control device receives 0x27 and 0x29 continuously, it can be determined that the target device type of the target device among multiple device types is a CXL device.
  • the processor on the mainboard can be, but is not limited to, set to obtain the target device type of the target device, for example: the processor on the mainboard is connected to the target device via a set of PCIe x16 high-speed lines, and the target device type of the target device is identified via the PCIe x16 high-speed lines, and the processor then sends the target device type of the target device to the clock controller via the I2C_CPU signal.
  • Figure 5 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • the clock control device also includes: a clock buffer 502, wherein the clock controller 102 is connected to the clock buffer 502, and the clock buffer 502 is also connected between a reference clock generator 504 and a clock selector 104 in clock generators (106-1 to 106-n) of multiple clock types; the reference clock generator 504 is configured to generate multiple clock signals; the clock buffer 502 is configured to cache multiple clock signals; the clock controller 102 is configured to collect signal parameters of multiple clock signals; determine the signal quality of each clock signal in the multiple clock signals according to the signal parameters; and control the clock buffer 502 to transmit the reference clock signal with the highest signal quality to the clock selector 104.
  • multiple clock signals can be cached by a clock buffer in the clock control device, but are not limited to it.
  • the clock controller receives clock signals transmitted by clock generators of multiple clock types from the mainboard, the multiple clock signals transmitted by the mainboard are cached by the clock buffer.
  • the signal parameters of multiple clock signals can be obtained by calculating multiple clock signals cached in the clock buffer through the clock controller, but is not limited to: first, the clock controller samples the multiple clock signals cached in the clock buffer to obtain sampled signals, and calculates the signal parameters of the sampled signals.
  • the signal parameters are used to indicate the signal quality of the clock signal, and the signal parameters may include but are not limited to: amplitude, frequency, slope, jitter and other parameters of the clock signal.
  • the clock controller may, but is not limited to, select a clock signal with the best signal quality according to the signal parameters and determine it as the reference clock signal. For example, the clock controller averages the signal parameters of each clock signal and determines the clock signal with the largest average value as the clock signal with the best signal quality, i.e., the reference clock signal. Alternatively, the clock controller calculates a weighted average value for the signal parameters of each clock signal and determines the clock signal with the largest weighted average value as the clock signal with the best signal quality, i.e., the reference clock signal.
  • FIG. 6 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • a second control port 602 is deployed on the clock controller 102, and a plurality of reference clock ports (604-1 to 604-n) are deployed on the clock buffer 502, a third output port 606 and a second signal port 608, wherein the second control port 602 is connected to the second signal port 608, and the plurality of reference clock ports (604-1 to 604-n) are deployed on the clock buffer 502.
  • the reference clock ports (604-1 to 604-n) are configured to connect to the reference clock generator 504, and the third output port 606 is configured to connect to the clock selector 104; the clock controller 102 is configured to generate a reference control signal corresponding to the reference clock signal; send the reference control signal to the clock buffer 502 through the second control port 602; the clock buffer 502 is configured to receive the reference control signal through the second signal port 608; and transmit the reference clock signal corresponding to the reference control signal to the third output port 606.
  • the second control port deployed on the clock controller can be connected to, but not limited to, the second signal port of the clock buffer, and the second signal port can be used to sample multiple clock signals to obtain multiple sampling signals.
  • the reference clock port deployed on the clock buffer may be, but is not limited to, connected to a reference clock generator, and the reference clock port may be, but is not limited to, configured to receive a clock signal sent by the reference clock generator and perform a buffering operation.
  • the third output port deployed on the clock buffer can be, but is not limited to, connected to a clock selector, and can be, but is not limited to, determining a clock signal corresponding to a reference control signal based on a reference control signal issued by a clock controller, and transmitting the reference control signal to the clock selector through the third output port.
  • Figure 7 is a schematic diagram of a clock control device of a switching chip according to an embodiment of the present application.
  • the clock control device also includes: a signal collector 702, wherein the signal collector 702 is connected between the reference clock generator 504 and the clock controller 102; the signal collector 702 is configured to sample multiple clock signals to obtain multiple sampling signals; the multiple sampling signals are transmitted to the clock controller 102; the clock controller 102 is configured to calculate signal parameters of multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameters, frequency parameters, slope parameters, jitter parameters; the signal parameters of each sampling signal are converted into the signal quality of each sampling signal.
  • the signal collector is configured to sample each clock signal to obtain a plurality of sampling signals during the process in which the clock generator sends the clock signal to the clock buffer.
  • the signal collector may, but is not limited to, determine signals of multiple clock signals in the same time period as sampling signals, for example: intercepting multiple clock signals in the same time period and determining them as sampling signals.
  • the signal parameter of the sampled signal is used to indicate the signal quality of the sampled signal
  • the signal quality of the sampled signal may be determined based on, but not limited to, the average value of the amplitude parameter, the frequency parameter, the slope parameter, and the jitter parameter.
  • the signal quality of the sampled signal may be determined based on, but not limited to, the weighted average value of the amplitude parameter, the frequency parameter, the slope parameter, and the jitter parameter.
  • a switch board is also provided. Since the switch board is configured to implement the above-mentioned embodiment and optional implementation modes, the details that have been described will not be repeated.
  • FIG 8 is a schematic diagram of a switching board according to an embodiment of the present application.
  • the switching board may include: a switching chip 802 and a clock control device 804, wherein the clock control device 804 is connected to the switching chip 802, and the clock control device 804 also allows connection with a target device 806 and clock generators of multiple clock types (808-1 to 808-n); the clock types of the clock signal used by the switching chip 802 when controlling target devices 806 belonging to different device types are different, and the multiple clock types correspond to the multiple device types; the clock control device 804 is configured to identify the target device type to which the target device 806 belongs among the multiple device types; and the target clock signal transmitted by the target clock generator among the clock generators of the multiple clock types (808-1 to 808-n) is transmitted to the switching chip 802 and the target device 806, wherein the target clock generator is a clock generator of the target clock type corresponding to the target device type.
  • the target clock generator is a clock generator of the target clock type corresponding to the target device type.
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock signal. Therefore, the problem of low clock adaptation efficiency of the switching chip can be solved, and the effect of improving the clock adaptation efficiency of the switching chip is achieved.
  • a clock control device includes: a clock controller and a clock selector, wherein the clock controller is connected to the clock selector, and the clock selector allows the connection of clock generators of various clock types, switching chips and target devices; the clock controller is configured to generate a target control signal corresponding to the target device type; send the target control signal to the clock selector; the clock selector is configured to receive the target control signal; and transmit the target clock signal corresponding to the target control signal to the switching chip and the target device.
  • clock generators of multiple clock types may be deployed on a switch board, for example, multiple clock generators are deployed on the switch board.
  • clock generators of multiple clock types may be deployed on a device connected to the switch board, for example, multiple clock generators are deployed on a mainboard connected to the switch board.
  • a clock controller and a clock selector may be deployed on the switching board but are not limited to being deployed.
  • the clock controller may be generated by the target device type but is not limited to sending the target control signal to the clock selector, and controlling the clock selector to select the target clock signal for transmission to the switching chip and the target device.
  • a clock generator of multiple clock types includes: a first clock generator of a homologous type and a second clock generator of a non-homologous type, wherein a clock selector is connected to the first clock generator and the second clock generator, respectively, the first clock generator is configured to transmit a homologous clock signal, and the second clock generator is configured to transmit a non-homologous clock signal; a clock controller is configured to generate a first control signal when the target device type is a first type, wherein the first type is a device type using a high-speed serial computer expansion bus standard; and generate a second control signal when the target device type is a second type, wherein the second type is a device type using a computer fast serial computer expansion bus standard.
  • the device type of the speed connection protocol sending a first control signal, or a second control signal, to the clock selector; the clock selector is configured to transmit a homologous clock signal to the switching chip and the target device when the first control signal is received; and transmit a non-homologous clock signal to the switching chip and the target device when the second control signal is received.
  • a reference clock generator among clock generators of multiple clock types allows generation of multiple clock signals, wherein a clock control device is configured to cache multiple clock signals and collect signal parameters of the multiple clock signals; determine the signal quality of each clock signal in the multiple clock signals based on the signal parameters; and determine the reference clock signal with the highest signal quality as the clock signal corresponding to the reference clock generator.
  • the reference clock generator may generate multiple clock signals, for example, the clock control device is connected to multiple types of clock generators, which may include but are not limited to homologous clock generators and non-homologous clock generators.
  • the homologous clock generator is allowed to generate multiple clock signals.
  • the reference clock generator is a non-homologous clock generator
  • the non-homologous clock generator is allowed to generate multiple clock signals.
  • a clock control device includes: a clock controller, a clock selector and a clock buffer, wherein the clock controller is connected to the clock selector, the clock selector allows the connection of clock generators of various clock types, switching chips and target devices, and the clock buffer is connected between the reference clock generator and the clock selector; the clock controller is configured to generate a reference control signal corresponding to a reference clock signal; send the reference control signal to the clock buffer; generate a target control signal corresponding to the target device type; send the target control signal to the clock selector; the clock buffer is configured to receive the reference control signal; transmit the reference clock signal corresponding to the reference control signal to the clock selector; the clock selector is configured to receive the target control signal; and transmit the target clock signal corresponding to the target control signal to the switching chip and the target device.
  • a clock buffer is connected between the reference clock generator and the clock selector, and the clock buffer is configured to cache the clock signal sent by the reference clock generator to the clock selector.
  • the clock buffer can, but is not limited to, determine the clock signal to be sent to the clock selector based on a reference control signal corresponding to the target device type indicated by the clock controller.
  • the clock controller can be, but is not limited to, configured to control the clock buffer to send a reference clock signal to the clock selector.
  • the clock controller is also configured to control the clock selector to send a target clock signal to the switching chip and the target device.
  • the clock controller receives the target device type of the target device, and generates a reference control signal and a target control signal according to the target device type.
  • the clock controller sends the reference control signal to the clock buffer to control the clock buffer to transmit the reference clock signal to the clock selector.
  • the clock controller sends the target control signal to the clock selector to control the clock selector to transmit the target clock signal to the switching chip and the target device.
  • the clock control device is further configured to: sample multiple clock signals to obtain multiple sampling signals; calculate signal parameters of the multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameter, frequency parameter, slope parameter, jitter parameter; convert the signal parameters of each sampling signal into the signal quality of each sampling signal.
  • a clock control device allows connection with a processor, wherein the clock control device is configured to receive a target device type sent by the processor.
  • the switching board also includes: an upstream connector, a downstream connector and a third clock generator, wherein the third clock generator is connected to a clock control device, the clock control device is connected to a fourth clock generator of the processor via the upstream connector, and the clock generators of multiple clock types include a third clock generator and a fourth clock generator; the clock control device is connected to a target device via the downstream connector.
  • the clock control device may be, but is not limited to being connected to a clock generator including a third clock generator and a fourth clock generator, the third clock generator and the clock control device may be directly connected, and the fourth clock generator of the processor deployed on the non-switch board and the clock control device may be, but is not limited to being connected through an upstream connector of the switching board.
  • the downstream connector of the switching board is configured to connect to a target device, and device information of the target device may be obtained through the downstream connector, but is not limited to the device information, such as the manufacturer, capacity, rate, etc. of the target device.
  • a switching board including: a switching chip, a clock control device, a third clock generator, an upstream connector and a downstream connector.
  • FIG9 is a schematic diagram of a working process of a switching board according to an embodiment of the present application.
  • the switching chip is a CXL SW chip
  • the clock control device includes a clock controller, a clock selector and a clock buffer.
  • the clock controller is a CPLD (Complex Programmable Logic Device) control unit
  • the clock selector is a CLK MUX
  • the clock buffer is a CLK Buffer
  • the third clock generator is a CLK Generator
  • the upstream connector is an upstream CDFP (Compact Duplex Form-factor Pluggable) connector
  • the downstream connector is a downstream CDFP connector.
  • the switching board can work in the following manner:
  • XTAL supplies the internal PLL (Phase-Locked Loop) of the third clock generator, so that the third clock generator outputs a 100MHz CLK_GEN clock signal.
  • the CPLD control unit reads the relevant information of the target device of the downstream CDFP connector through the I2C and PERST_N signals, such as reading the manufacturer, capacity, rate and other relevant information of the target device through the I2C signal, and resetting the target device through the PERST_N signal.
  • the upstream CDFP connector is connected to the downstream CDFP connector through a set of PCIe x16 high-speed lines.
  • the PCIe x16 high-speed line connected to the downstream CDFP connector identifies the target device type of the target device, and the processor CPU of the upstream CDFP connector sends the target device type of the target device to the CPLD control unit through an I2C_CPU signal.
  • the uplink CDFP connector of the switching board is connected to the CDFP connector of the mainboard through a cable to receive the homologous clock signal from the mainboard.
  • the ADC sampling unit (signal collector) samples multiple homologous clock signals from the mainboard and transmits the sampled signals to the CPLD control unit through the SPI (Serial Peripheral Interface) bus.
  • the CPLD control unit calculates the signal parameters of the sampled signal: amplitude parameters, frequency parameters, slope parameters, jitter parameters, etc., and determines the homologous clock signal with the best signal quality according to the signal parameters.
  • the CPLD control unit controls the clock buffer CLK Buffer through the CLK_S signal to select the homologous clock signal with the best signal quality for output. For example, when CLK_S outputs a low level, it indicates that the signal quality of CLK_CDFP1 is the best, and the clock buffer CLK buffer outputs CLK_CDFP1 to CLK_BUF; when CLK_S outputs a high level, it indicates that the signal quality of CLK_CDFP2 is the best, and the CLK buffer outputs CLK_CDFP2 to CLK_BUF.
  • the CLK MUX selects the corresponding clock for the target device connected to the downstream CDFP connector and the CXL SW in the following way:
  • IN_1 of CLK MUX outputs the homologous clock CLK_BUF to MUX_OUT1 and MUX_OUT2 respectively, and then inputs it to CXL SW through CLK_CXL, and inputs it to the target device connected to the downstream port CDFP connector through CLK_CDFP, so that the clocks of the target device connected to the downstream port CDFP connector and CXL SW are the same clock.
  • IN_2 outputs the non-isochronous clock CLK_GEN to MUX_OUT1 and MUX_OUT2 respectively, and then inputs it to CXL SW through CLK_CXL, and inputs it to the target device connected to the downstream port CDFP connector through CLK_CDFP, so that the clocks of the target device connected to the downstream port CDFP connector and CXL SW are all non-isochronous clocks.
  • the clock control device is connected to a mainboard on which a clock generator is deployed.
  • FIG10 is a schematic diagram of a mainboard on which a clock generator is deployed according to an embodiment of the present application.
  • the mainboard includes: XTAL (a 25 MHz clock crystal), a clock generator CLK Generator, a processor CPU, and a CDFP connector.
  • the mainboard can send a clock signal to the clock control device in the following manner: the clock crystal XTAL supplies the internal PLL of the clock generator CLK Generator to output a 100 MHz PCIe clock; the CLK Generator outputs a 25 MHz C signal through the output terminal CLK_OUTO.
  • LK_CPU clock to CPU CPU is connected to the PCIe device of CDFP connector through a set of PCIe x16 high-speed lines, and is connected to the I2C device of CDFP connector through I2C;
  • CLK Generator outputs 100MHz CLK_CDFP1 to the same source clock signal to the CLK_CDFP_OUT1 port of CDFP connector through the output terminal CLK_OUT1, and outputs 100MHz CLK_CDFP2 to the same source clock signal to the CLK_CDFP_OUT2 port of CDFP connector through the output terminal CLK_OUT2;
  • CDFP connector is configured to connect to the switching chip deployed on the switching board.
  • the mainboard can send the target device type to the clock controller in the following way: the CPU is connected to the clock controller of the switching board through the I2C bus, and sends the target device type of the target device (which may include but is not limited to PCIe devices and CXL devices) to the CPLD control unit through the I2C_CPU signal.
  • the target device type of the target device which may include but is not limited to PCIe devices and CXL devices
  • FIG. 11 is a schematic diagram of a device board with a target device deployed according to an embodiment of the present application.
  • the device board includes: a CDFP connector, a PCIe slot or a CXL slot (PCIe/CXL slot), a PCIe device or a CXL device (PCIe/CXL device), and the PCIe device or the CXL device has an EEPROM (Electrically Erasable Programmable Read-Only Memory), and the EEPROM is configured to store information such as the manufacturer, capacity, and rate.
  • EEPROM Electrical Erasable Programmable Read-Only Memory
  • the CDFP connector obtains the information stored in the EEPROM through the I2C port; the CDFP connector performs a reset operation on the PCIe device or the CXL device through RST_N (which can be but is not limited to being configured to indicate a reset signal); the CDFP connector transmits a clock signal through CLK_OUT connected to CLK_IN; and the CDFP connector reads the device deployed in the slot through PCIe.
  • the device board can send the target device type to the clock control device of the switch board in the following manner:
  • the processor CPU of the mainboard When the device board is powered on, the processor CPU of the mainboard automatically identifies the target device of the PCIe slot or the CXL slot through the PCIe bus, and sends the target device type to the clock controller CPLD of the switch board through the I2C_CPU bus.
  • the clock controller CPLD continuously receives signals such as 0x50, 0x56, etc., it can be, but is not limited to, that the target device type of the target device is a PCIe device; when the clock controller CPLD continuously receives signals such as 0x27, 0x29, etc., it can be, but is not limited to, that the target device type of the target device is a CXL device.
  • a clock control system of a switching chip is also provided. Since the switching board is configured to implement the above-mentioned embodiment and optional implementation modes, the descriptions that have been made will not be repeated.
  • FIG12 is a schematic diagram of a clock control system of a switching chip according to an embodiment of the present application.
  • the clock control system of the switching chip may include: a switching board 1202 and a device board 1204, wherein a switching chip 1206 and a clock control device 1208 are deployed on the switching board 1202, and a device interface 1210 is deployed on the device board 1204; the device interface 1210 is configured to connect to a target device 1212, wherein the switching chip 1206 uses different clock types of clock signals when controlling target devices 1212 of different device types, and multiple clock types correspond to multiple device types; the clock control device 1208 is configured to identify the target device type to which the target device 1212 belongs among multiple device types; and the target clock signal transmitted by the target clock generator 1216 of the clock generators (1214-1 to 1214-n) of multiple clock types is transmitted to the switching chip 1206 and the target device 1212, wherein the target clock generator is a target clock type corresponding to the target device type.
  • the clock generator is a target clock type corresponding to the target
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock signal. Therefore, the problem of low clock adaptation efficiency of the switching chip can be solved, and the effect of improving the clock adaptation efficiency of the switching chip is achieved.
  • a first control port is deployed on the clock controller, and multiple clock ports, a first output port, a second output port and a first signal port are deployed on the clock selector, wherein the first control port is connected to the first signal port, the multiple clock ports are configured to respectively connect to clock generators of multiple clock types, the first output port is configured to connect to a switching chip, and the second output port is configured to connect to a target device; the clock controller is configured to generate a target control signal corresponding to the target device type; the target control signal is sent to the clock selector through the first control port; the clock selector is configured to receive the target control signal through the first signal port; and the target clock signal received on the target clock port corresponding to the target control signal is transmitted to the first output port and the second output port.
  • the system also includes: a main board, wherein a third clock generator is also deployed on the switching board, a fourth clock generator of the processor is deployed on the main board, and a clock control device includes: a clock controller and a clock selector; the clock controller is connected to the clock selector, the clock selector is connected to the third clock generator, the fourth clock generator, the switching chip and the target device, the third clock generator is configured to transmit non-homologous clock signals, and the fourth clock generator is configured to transmit homologous clock signals; the clock controller is configured to generate a first control signal when the target device type is a first type, wherein the first type is a device type using a high-speed serial computer expansion bus standard; when the target device type is a second type, a second control signal is generated, wherein the second type is a device type using a computing fast connection protocol; the first control signal is sent to the clock selector, or the second control signal; the clock selector is configured to transmit the homologous clock signal to the switching chip and the target device
  • the mainboard may include but is not limited to a clock generator, and the clock generator of the mainboard may provide a clock signal in the following manner but is not limited to: XTAL supplies the CLK generator internal PLL, thereby outputting a 100MHz PCIe clock.
  • the main board may include but is not limited to a clock generator and a processor, and the processor of the main board may obtain the target device type of the target device in the following manner: the CPU is connected to the clock controller of the switching board through the I2C bus, and sends the target device type of the target device to the CPLD control unit through the I2C_CPU signal (which may include but is not limited to PCIe devices and CXL devices).
  • the processor of the main board may obtain the target device type of the target device in the following manner: the CPU is connected to the clock controller of the switching board through the I2C bus, and sends the target device type of the target device to the CPLD control unit through the I2C_CPU signal (which may include but is not limited to PCIe devices and CXL devices).
  • the fourth clock generator allows the generation of multiple clock signals
  • the clock control device also includes: a clock buffer, wherein the clock buffer is connected between the fourth clock generator and the clock selector; a clock controller, configured to collect signal parameters of multiple clock signals; determine the signal quality of each clock signal in the multiple clock signals based on the signal parameters; determine the reference clock signal with the highest signal quality as the clock signal corresponding to the fourth clock generator; generate a reference control signal corresponding to the reference clock signal; send the reference control signal to the clock buffer; the clock buffer, configured to cache multiple clock signals; receive the reference control signal; and transmit the reference clock signal corresponding to the reference control signal to the clock selector.
  • a second control port is deployed on the clock controller, and multiple reference clock ports, a third output port and a second signal port are deployed on the clock buffer, wherein the second control port is connected to the second signal port, the multiple reference clock ports are configured to be connected to a reference clock generator, and the third output port is configured to be connected to a clock selector; the clock controller is configured to generate a reference control signal corresponding to a reference clock signal; the reference control signal is sent to the clock buffer through the second control port; the clock buffer is configured to receive the reference control signal through the second signal port; and the reference clock signal corresponding to the reference control signal is transmitted to the third output port.
  • the clock control device also includes: a signal collector, wherein the signal collector is connected between a reference clock generator and a clock controller; the signal collector is configured to sample multiple clock signals to obtain multiple sampling signals; the multiple sampling signals are transmitted to the clock controller; the clock controller is configured to calculate signal parameters of the multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameter, frequency parameter, slope parameter, jitter parameter; and the signal parameters of each sampling signal are converted into the signal quality of each sampling signal.
  • a processor is also deployed on the main board, and the clock control device is connected to the processor, wherein the processor is connected to the target device through a switch board and a device board; the processor is configured to output the target device type of the target device during the training process of the target device; the target device type is sent to the clock control device; and the clock control device is configured to receive the target device type sent by the processor.
  • a clock control system of a switching chip is provided.
  • Figure 13 is a schematic diagram of a clock control process in a clock control system of a switching chip according to an optional implementation mode of the present application.
  • the clock control system of the switching chip includes a main board, a switching board and a device board, wherein the main board includes a clock generator and a processor CPU deployed on the main board, and the mainboard clock generator is configured to provide a clock signal to the CPU and send a first clock signal to the switching board.
  • the switching board includes a clock buffer, a clock controller, a clock selector, a clock generator deployed on the switching board, and a switching chip CXL SW, wherein the clock buffer, the clock controller, and the clock selector are configured to parse the highest quality clock signal from the first clock signal emitted by the mainboard clock generator, and the clock controller is also configured to parse the target device (which may be but is not limited to a CXL device or a PCIe device) deployed on the device board to output a control signal to the clock buffer; the switching board clock generator is configured to output a second clock signal to the clock selector, and the first The first clock signal and the second clock signal are of different types.
  • the clock selector outputs a homologous clock or a non-homologous clock to the CXL SW and the device board under the control of a control signal sent by the clock controller.
  • the CXL device or the PCIe device is deployed on the device board.
  • the clock control system of the switching chip can work in the following manner:
  • the mainboard clock generator sends a plurality of homologous clock signals to the processor of the mainboard and the clock buffer of the switching board, and the clock buffer of the switching board performs a cache operation on each homologous clock signal.
  • the clock controller of the switching board samples the homologous clock signal sent by the mainboard clock generator, and determines the optimal homologous clock signal among multiple homologous clock signals sent by the mainboard clock generator through analysis.
  • the clock controller sends a reference control signal to the clock buffer to control the clock buffer to transmit the optimal homologous clock signal to the clock selector.
  • the switch board clock generator transmits a non-homologous clock signal to the clock selector.
  • the clock controller sends a corresponding control signal (a first control signal or a second control signal) to the clock selector according to the target device type (CXL device or PCIe device) of the target device deployed on the device board, and controls the clock selector to select a clock signal corresponding to the target device type from the homologous clock signals and the non-homologous clock signals.
  • a corresponding control signal a first control signal or a second control signal
  • the clock selector transmits the clock signal corresponding to the target device type to the CXL SW and the target device according to the control signal sent by the clock controller.
  • the clock signals of CXL SW and PCIe device can be, but are not limited to, determined as homologous clocks if they are derived from the mainboard clock generator; the clock signals of CXL SW and CXL device can be, but are not limited to, determined as non-homologous clocks if they are derived from the switch board clock generator.
  • FIG. 14 is a hardware structure block diagram of a mobile terminal of a clock control method of a switching chip in an embodiment of the present application.
  • the mobile terminal may include one or more (only one is shown in FIG. 14) processors 1402 (the processor 1402 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 1404 configured to store data, wherein the mobile terminal may also include a transmission device 1406 configured to have a communication function and an input/output device 1408.
  • processors 1402 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA
  • a transmission device 1406 configured to have a communication function and an input/output device 1408.
  • FIG. 14 is only for illustration and does not limit the structure of the mobile terminal.
  • the mobile terminal may also include more or fewer components than those shown in FIG. 14, or have a configuration different from that shown in FIG. 14.
  • the memory 1404 may be configured to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the clock control method of the switching chip in the embodiment of the present application.
  • the processor 1402 executes various functional applications and data processing by running the computer program stored in the memory 1404, that is, to implement the above method.
  • the memory 1404 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 1404 may include a memory remotely arranged relative to the processor 1402, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the transmission device 1406 is configured to receive or send data via a network.
  • the above-mentioned optional examples of the network may include a wireless network provided by a communication provider of the mobile terminal.
  • the transmission device 1406 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 1406 can be a radio frequency (Radio Frequency, referred to as RF) module, which is configured to communicate with the Internet wirelessly.
  • RF Radio Frequency
  • FIG. 15 is a flow chart of clock control of a switching chip according to an embodiment of the present application. As shown in FIG. 15 , the flow chart includes the following steps:
  • Step S1502 receiving clock signals transmitted by clock generators of multiple clock types, wherein the clock control device is connected to the switching chip, and the switching chip uses different clock types of clock signals when controlling target devices of different device types, and the multiple clock types correspond to the multiple device types;
  • Step S1504 identifying the target device type to which the target device belongs among the multiple device types
  • Step S1506 transmitting the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, wherein the target clock generator is a clock generator of the target clock type corresponding to the target device type.
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock signal. Therefore, the problem of low clock adaptation efficiency of the switching chip can be solved, and the effect of improving the clock adaptation efficiency of the switching chip is achieved.
  • the executor of the above steps can be a clock control device, which can include but is not limited to a clock controller and a clock selection, and can identify the target device type to which the target device belongs among multiple device types through the above clock controller; and can transmit the target clock signal transmitted by the target clock generator of the target clock type corresponding to the target device type to the switching chip and the target device through a clock selector but is not limited to.
  • a clock control device which can include but is not limited to a clock controller and a clock selection, and can identify the target device type to which the target device belongs among multiple device types through the above clock controller; and can transmit the target clock signal transmitted by the target clock generator of the target clock type corresponding to the target device type to the switching chip and the target device through a clock selector but is not limited to.
  • the above clock generator may be, but is not limited to, a device capable of generating and transmitting a clock signal, such as a quartz crystal (XTAL) and a crystal oscillator, etc.
  • the clock type of the above clock generator may include, but is not limited to, a homologous clock and a non-homologous clock.
  • the clock generator may be, but is not limited to, a device capable of simultaneously sending multiple clock signals, for example, the clock control device receives multiple clock signals sent by the same clock generator and multiple clock signals sent by another clock generator of a different clock type. Alternatively, the clock control device receives multiple clock signals sent by the same clock generator and a single clock signal sent by another clock generator of a different clock type.
  • the target device may be, but is not limited to, a device of multiple device types, such as RC, Switch, Endpoint, etc., which are device types using the high-speed serial computer expansion bus standard.
  • RC RC
  • Switch Endpoint
  • CXL accelerator card CXL switch, etc.
  • computing fast connection protocol a device of multiple device types
  • the switching chip may be, but is not limited to, a device having a function of controlling a target device, such as a CXL SW chip.
  • the clock type used by the switching chip may be, but is not limited to, determined according to the device type of the target device, such as, when the target device type of the target device is a PCIe device, the clock type used by the switching chip is determined to be a homologous clock. Alternatively, when the target device type of the target device is a CXL device, the clock type used by the switching chip is determined to be a non-homologous clock.
  • the target device type can be but is not limited to the clock control device transmitted to by the processor on the mainboard.
  • the processor deployed on the mainboard automatically identifies the target device of the PCIe slot or CXL slot through the PCIe bus, and informs the clock control device of the identified target device type through the I2C_CPU bus.
  • the target device type to which the target device belongs among multiple device types may be identified in the following manner but is not limited to: receiving the target device type sent by a processor to which the clock control device is connected.
  • the above-mentioned processor can be but is not limited to being deployed on a motherboard connected to the clock control device, and the above-mentioned processor can be but is not limited to reading the target device type of the target device through the bus, for example: the processor reads the target device of the PCIe slot or the CXL slot through the PCIe bus, and sends the target device type of the target device to the clock control device.
  • the above-mentioned clock control device can be but is not limited to being configured to receive the target device type, and the clock control device can be but is not limited to selecting a clock signal corresponding to the target device type from clock signals transmitted by clock generators of multiple clock types according to the target device type.
  • the clock control device may determine the target device type of the target device according to the data received from the processor, but is not limited to, for example, taking 0x50 and 0x56 to indicate that the target device type is a PCIe device, when the clock control device receives 0x50 and 0x56 continuously, it can be determined that the target device type of the target device among multiple device types is a PCIe device. Or, taking 0x27 and 0x29 to indicate that the target device type is a CXL device, when the clock control device receives 0x27 and 0x29 continuously, it can be determined that the target device type of the target device among multiple device types is a CXL device.
  • the target clock type can be determined from a plurality of clock types according to the target device type of the target device, but is not limited to: determining the clock type required by the switching chip and the target device as a homologous clock according to the target device type of the target device. Alternatively, determining the clock type required by the switching chip and the target device as a non-homogenous clock according to the target device type of the target device.
  • the clock generator that sends the target clock type may be determined as the target clock generator, but is not limited to it.
  • the two clock generators of the same clock type may be determined as the target clock generator, but is not limited to it.
  • a better one of the two clock generators of the same clock type is selected to be determined as the target clock generator.
  • the target clock signal transmitted by the target clock generator among clock generators of multiple clock types can be transmitted to the switching chip and the target device in the following manner but is not limited to: generating a target control signal corresponding to the target device type; and transmitting the target clock signal corresponding to the target control signal to the switching chip and the target device.
  • the target control signal is used to instruct the clock control device to select a target clock signal transmitted by a target clock generator from clock generators of multiple clock types for transmission.
  • a target clock generator For example, taking clock signal A and clock signal B emitted by clock generator A of the same clock type, and clock signal C and clock signal D emitted by clock generator B of non-same clock types as examples, when the target control signal indicates that the switching chip and the target device require clock signals of the same clock type, it is possible but not limited to determining that clock generator A that emits clock signal A and clock signal B is the target clock generator, and it is possible but not limited to selecting one clock signal from clock signal A and clock signal B as the target clock signal for transmission.
  • the clock control device may include, but is not limited to, a clock controller and a clock selector.
  • the clock controller may generate, but is not limited to, a target control signal corresponding to the target device type.
  • the clock selector may transmit, but is not limited to, a target clock signal corresponding to the target control signal to the switching chip and the target device.
  • the clock controller generates a target control signal according to the target device type of the target device and transmits it to the clock selector.
  • the clock selector selects the target clock signal from all clock signals for transmission according to the target control signal.
  • the clock controller generates a target control signal according to the target device type of the target device and transmits it to the clock selector.
  • the clock selector selects the first clock signal of the clock type indicated by the target control signal, and then selects the target clock signal from the first clock signal for transmission.
  • the clock controller may, but is not limited to, control the level of the target control signal output to indicate the timing.
  • the clock selector selects the corresponding target clock signal, for example, when the target control signal outputs a low level, it is used to instruct the clock selector to select the same source clock. Or, when the target control signal outputs a high level, it is used to instruct the clock selector to select a non-same source clock.
  • the target control signal can be received through the first signal port of the clock selector but is not limited to; the target clock signal received on the target clock port corresponding to the target control signal is transmitted to the first output port and the second output port.
  • a clock generator of multiple clock types includes: a first clock generator of a homologous type and a second clock generator of a non-homologous type, the first clock generator is configured to transmit a homologous clock signal, and the second clock generator is configured to transmit a non-homologous clock signal; generating a target control signal corresponding to a target device type: when the target device type is a first type, generating a first control signal, wherein the first type is a device type that adopts a high-speed serial computer expansion bus standard; when the target device type is a second type, generating a second control signal, wherein the second type is a device type that adopts a computing fast connection protocol; transmitting a target clock signal corresponding to the target control signal to a switching chip and a target device, including: when the first control signal is received, transmitting the homologous clock signal to the switching chip and the target device; when the second control signal is received, transmitting the non-homologous clock signal to the switching chip and the
  • the first control signal is used to transmit the homologous clock signal to the first output port and the second output port
  • the second control signal is used to transmit the non-homologous clock signal to the first output port and the second output port.
  • the first output port and the second output port can be, but are not limited to, configured to transmit the clock signal to the switching chip and the target device.
  • the clock signal is transmitted to the switching chip and the target device through the first output port and the second output port.
  • multiple clock ports, a first output port, a second output port and a first signal port may be deployed on the clock selector but are not limited to being deployed, wherein the first clock port allows connection to a first clock generator of the same source type, the second clock port allows connection to a second clock generator of a non-homologous type, the first clock generator is configured to transmit a homologous clock signal, and the second clock generator is configured to transmit a non-homologous clock signal.
  • a reference clock generator among clock generators of multiple clock types is configured to generate multiple clock signals, wherein clock signals transmitted by clock generators of multiple clock types may be received in the following manner but is not limited to: caching multiple clock signals; collecting signal parameters of multiple clock signals; determining the signal quality of each clock signal in the multiple clock signals based on the signal parameters; and determining the reference clock signal with the highest signal quality as the clock signal transmitted by the reference clock generator.
  • multiple clock signals can be cached by a clock buffer in the clock control device, but are not limited to it.
  • the clock controller receives clock signals transmitted by clock generators of multiple clock types from the mainboard, the multiple clock signals transmitted by the mainboard are cached by the clock buffer.
  • the signal parameters of the multiple clock signals cached in the clock buffer can be obtained by calculating, but not limited to, for example: first, the multiple clock signals cached in the clock buffer are sampled to obtain sampled signals, and the signal parameters of the sampled signals are calculated.
  • the signal parameters are used to indicate the signal quality of the clock signal, and the signal parameters may include but are not limited to: amplitude, frequency, slope, jitter and other parameters of the clock signal.
  • the clock signal with the best signal quality can be selected as the reference clock signal according to the signal parameters, but is not limited to it.
  • the signal parameters of each clock signal are averaged, and the clock signal with the largest average value is determined as the clock signal with the best signal quality, i.e., the reference clock signal.
  • the signal parameters of each clock signal are weighted averaged, and the clock signal with the largest weighted average value is determined as the clock signal with the best signal quality, i.e., the reference clock signal.
  • a second control port is deployed on the clock controller, and multiple reference clock ports, a third output port and a second signal port are deployed on the clock buffer, wherein the second control port is connected to the second signal port, the multiple reference clock ports are configured to be connected to a reference clock generator, and the third output port is configured to be connected to a clock selector; the clock controller is configured to generate a reference control signal corresponding to a reference clock signal; the reference control signal is sent to the clock buffer through the second control port; the clock buffer is configured to receive the reference control signal through the second signal port; and the reference clock signal corresponding to the reference control signal is transmitted to the third output port.
  • signal parameters of multiple clock signals can be collected in the following manner but is not limited to: sampling multiple clock signals to obtain multiple sampling signals; calculating signal parameters of the multiple sampling signals, wherein the signal parameters of each sampling signal include at least one of the following: amplitude parameter, frequency parameter, slope parameter, jitter parameter.
  • multiple clock signals in the same time period may be determined as sampling signals but are not limited to the above.
  • multiple clock signals in the same time period are intercepted and determined as sampling signals.
  • the signal parameter of the sampled signal is used to indicate the signal quality of the sampled signal
  • the signal quality of the sampled signal may be determined based on, but not limited to, the average value of the amplitude parameter, the frequency parameter, the slope parameter, and the jitter parameter.
  • the signal quality of the sampled signal may be determined based on, but not limited to, the weighted average value of the amplitude parameter, the frequency parameter, the slope parameter, and the jitter parameter.
  • the clock control device further includes: a signal collector, wherein the signal collector is connected to the reference clock generator. generator and the clock controller; a signal collector is configured to sample multiple clock signals to obtain multiple sampling signals; and transmit the multiple sampling signals to the clock controller.
  • FIG. 16 is a schematic diagram of a clock control process in a clock control system of a switching chip according to an optional embodiment of the present application. As shown in FIG. 16 , the process may include but is not limited to the following steps:
  • Step S1602 The user inserts the PCIe device or CXL device into the slot of the device board and powers on the clock control system of the entire switch chip;
  • Step S1604 during the process of the processor training the target device, the processor CPU of the mainboard reads the target device type of the target device in the device board slot;
  • Step S1606 When the target device type is read, the processor sends the target device type to the clock controller CPLD of the switch board through the I2C bus;
  • Step S1608 The clock controller CPLD analyzes the target device type
  • the clock controller parses and obtains that the target device is a CXL device), execute steps S1610 to S1618:
  • Step S1610 the clock controller CPLD outputs a high-level CXL_MODE signal (ie, a target control signal);
  • Step S1612 The clock selector CLK_MUX outputs IN_2 to MUX_OUT1 and MUX_OUT2, MUX_OUT1 outputs to the switching chip CXL SW, and MUX_OUT2 outputs to the CXL device;
  • Step S1614 the clock controller CPLD pulls up the PERST_N signal (i.e., the reference clock signal);
  • Step S1616 The switching chip CXL SW and the CXL device obtain non-homologous clocks
  • Step S1618 Clock configuration is completed.
  • the clock controller parses and obtains that the target device is a PCIe device), execute steps S1620 to S1632:
  • Step S1620 The clock controller CPLD starts the ADC sampling unit through the SPI bus and reads the sampling signal;
  • Step S1622 The clock controller CPLD calculates the signal parameters of the sampling signal and selects the reference clock signal with the highest signal quality
  • Step S1624 the clock controller CPLD outputs a low-level CXL_MODE signal (i.e., a target control signal);
  • Step S1626 The clock selector CLK MUX outputs IN_1 to MUX_OUT1 and MUX_OUT2, MUX_OUT1 outputs to the switching chip CXL SW, and MUX_OUT2 outputs to the PCIe device;
  • Step S1628 The clock controller CPLD pulls up the PERST_N signal (i.e., the reference clock signal);
  • Step S1630 The switching chip CXL SW and the PCIe device obtain the same source clock
  • Step S1632 Clock configuration is completed.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.
  • the technical solution of the present application, or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.
  • a storage medium such as ROM/RAM, a disk, or an optical disk
  • a clock control device for a switching chip is also provided, which is configured to implement the above-mentioned embodiments and optional implementation modes, and the descriptions that have been made will not be repeated.
  • the term "module” can implement a combination of software and/or hardware for a predetermined function.
  • the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.
  • FIG. 17 is a structural block diagram of a clock control device for a switching chip according to an embodiment of the present application. As shown in FIG. 17 , the device includes:
  • the receiving module 1702 is configured to receive clock signals transmitted by clock generators of multiple clock types, wherein the clock control device is connected to the switching chip, and the switching chip uses different clock types of clock signals when controlling target devices of different device types, and the multiple clock types correspond to the multiple device types;
  • An identification module 1704 is configured to identify a target device type to which a target device belongs among multiple device types
  • the transmission module 1706 is configured to transmit a target clock signal transmitted by a target clock generator among clock generators of multiple clock types to the switching chip and the target device, wherein the target clock generator is a clock generator of a target clock type corresponding to the target device type.
  • the clock controller controls the clock selector according to the target device type of the target device to transmit the target clock signal transmitted by the target clock generator among the clock generators of multiple clock types to the switching chip and the target device, so that the switching chip can automatically use the corresponding clock type when controlling target devices of different device types.
  • the target device type of the target device is obtained through the clock controller, and the clock controller controls the clock selector according to the target device type to select the transmission target clock signal to reach the switching chip and the target device, so that the switching chip and the target device can receive the corresponding target clock signal. Therefore, the problem of low clock adaptation efficiency of the switching chip can be solved, and the effect of improving the clock adaptation efficiency of the switching chip is achieved.
  • the transmission module is configured to:
  • the service status of the service running on the second operating system is monitored through the second operating system; and the target clock signal corresponding to the target control signal is transmitted to the switching chip and the target device.
  • the transmission module is further configured to:
  • Generating a target control signal corresponding to a target device type includes: generating a first control signal when the target device type is a first type, wherein the first type is a device type using a high-speed serial computer expansion bus standard; generating a second control signal when the target device type is a second type, wherein the second type is a device type using a computer fast connection protocol;
  • the target clock signal corresponding to the target control signal is transmitted to the switching chip and the target device, including: when a first control signal is received, the homologous clock signal is transmitted to the switching chip and the target device; when a second control signal is received, the non-homologous clock signal is transmitted to the switching chip and the target device.
  • the transmission module is further configured to:
  • the reference clock signal with the highest signal quality is determined as the clock signal transmitted by the reference clock generator.
  • the transmission module is further configured to:
  • Signal parameters of a plurality of sampling signals are calculated, wherein the signal parameter of each sampling signal includes at least one of the following: an amplitude parameter, a frequency parameter, a slope parameter, and a jitter parameter.
  • the identification module is further configured to:
  • the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.
  • An embodiment of the present application further provides a non-volatile readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.
  • the above-mentioned non-volatile readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store computer programs.
  • FIG. 18 is a schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 18, it includes a memory and a processor. A computer program is stored in the memory. The processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
  • the electronic device may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
  • modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation.
  • the present application is not limited to any specific combination of hardware and software.

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Abstract

本申请实施例提供了一种交换芯片的时钟控制方法，系统和设备，以及交换板，其中，该方法应用于时钟控制设备，包括：接收多种时钟类型的时钟发生器传输的时钟信号，其中，时钟控制设备与交换芯片连接，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；识别目标设备在多种设备类型中所属于的目标设备类型；将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。通过本申请，解决了交换芯片的时钟适配效率较低的问题，进而达到了提高交换芯片的时钟适配效率的效果。

Description

交换芯片的时钟控制方法，系统和设备，以及交换板
相关申请的交叉引用
本申请要求于2023年06月21日提交中国专利局，申请号为2023107435732，申请名称为“交换芯片的时钟控制方法，系统和设备，以及交换板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及芯片领域，特别的，涉及一种交换芯片的时钟控制方法，系统和设备，以及交换板。
背景技术
CXL(Compute Express Link，计算快速连接)技术是一种建立于PCIe 5.0(Peripheral Component Interconnect Express 5.0，高速串行计算机扩展总线标准(第五代))物理总线的高速缓存一致性互连协议，CXL技术不仅支持在处理器、内存扩展和加速器使用，并且允许资源共享以获得更高的性能。目前，业界已推出CXL 2.0(Compute Express Link 2.0，计算快速连接2.0)协议，引入了SW(switch，交换)的功能，支持连接更多的设备，允许服务端根据工作负载要求，分配相应的资源，从而提高资源利用率和降低整体系统成本。
由于CXL SW(Compute Express Link switch，计算快速连接交换)不仅能够支持CXL设备的工作模式，同时也支持PCIe(Peripheral Component Interconnect Express，高速串行计算机扩展总线标准)设备的应用场景，这就带来了时钟模式的问题：PCIe设备需要在SW的系统时钟与参考时钟同源的模式工作，但是CXL设备需要在非同源时钟模式工作。对于CXL SW如何兼容两种不同设备的时钟，相关技术一般根据插入设备的不同，手动选择时钟模式，但这种方法效率低下，并且同源时钟一般通过线缆连接，链路较长，如果选择的同源时钟信号质量差，就容易引起设备不被CPU(Central Processing Unit，中央处理器)识别。
针对相关技术中，交换芯片的时钟适配效率较低等问题，尚未提出有效的解决方案。
发明内容
本申请实施例提供了一种交换芯片的时钟控制方法，系统和设备，以及交换板，以至少解决相关技术中交换芯片的时钟适配效率较低的问题。
根据本申请的一个实施例，提供了一种交换芯片的时钟控制设备，包括：时钟控制器和时钟选择器，其中，时钟控制器与时钟选择器连接，时钟选择器允许连接多种时钟类型的时钟发生器、交换芯片和目标设备，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；时钟控制器，被设置为识别目标设备在多种设备类型中所属于的目标设备类型；控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
在一个示例性实施例中，时钟控制器上部署了第一控制端口，时钟选择器上部署了多个时钟端口，第一输出端口，第二输出端口和第一信号端口，其中，第一控制端口与第一信号端口连接，多个时钟端口被设置为分别连接多种时钟类型的时钟发生器，第一输出端口被设置为连接交换芯片，第二输出端口被设置为连接目标设备；时钟控制器，被设置为生成目标设备类型所对应的目标控制信号；通过第一控制端口向时钟选择器发送目标控制信号；时钟选择器，被设置为通过第一信号端口接收目标控制信号；将目标控制信号对应的目标时钟端口上接收到的目标时钟信号传输至第一输出端口和第二输出端口。
在一个示例性实施例中，多个时钟端口包括第一时钟端口和第二时钟端口，其中，第一时钟端口允许与同源类型的第一时钟发生器连接，第二时钟端口允许与非同源类型的第二时钟发生器连接，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号；时钟控制器，被设置为在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；通过第一控制端口向时钟选择器发送第一控制信号，或者，第二控制信号；时钟选择器，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至第一输出端口和第二输出端口；在接收到第二控制信号的情况下，将非同源时钟信号传输至第一输出端口和第二输出端口。
在一个示例性实施例中，时钟控制器上部署了设备类型端口，其中，设备类型端口允许与处理器连接，设备类型端口被设置为接收处理器发送的目标设备类型。
在一个示例性实施例中，时钟控制设备，还包括：时钟缓冲器，其中，时钟控制器与时钟缓冲器连 接，时钟缓冲器还连接在多种时钟类型的时钟发生器中的参考时钟发生器和时钟选择器之间；参考时钟发生器，被设置为生成多个时钟信号；时钟缓冲器，被设置为缓存多个时钟信号；时钟控制器，被设置为采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；控制时钟缓冲器将信号质量最高的参考时钟信号传输至时钟选择器。
在一个示例性实施例中，时钟控制器上部署了第二控制端口，时钟缓冲器上部署了多个参考时钟端口，第三输出端口和第二信号端口，其中，第二控制端口与第二信号端口连接，多个参考时钟端口被设置为连接参考时钟发生器，第三输出端口被设置为连接时钟选择器；时钟控制器，被设置为生成参考时钟信号所对应的参考控制信号；通过第二控制端口向时钟缓冲器发送参考控制信号；时钟缓冲器，被设置为通过第二信号端口接收参考控制信号；将参考控制信号对应的参考时钟信号传输至第三输出端口。
在一个示例性实施例中，时钟控制设备，还包括：信号采集器，其中，信号采集器连接在参考时钟发生器和时钟控制器之间；信号采集器，被设置为对多个时钟信号进行采样，得到多个采样信号；将多个采样信号传输至时钟控制器；时钟控制器，被设置为计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个采样信号的信号参数转换为每个采样信号的信号质量。
根据本申请的另一个实施例，提供了一种交换板，包括：交换芯片和时钟控制设备，其中，时钟控制设备与交换芯片连接，时钟控制设备还允许与目标设备和多种时钟类型的时钟发生器连接；交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；时钟控制设备，被设置为识别目标设备在多种设备类型中所属于的目标设备类型；将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
在一个示例性实施例中，时钟控制设备，包括：时钟控制器和时钟选择器，其中，时钟控制器与时钟选择器连接，时钟选择器允许连接多种时钟类型的时钟发生器，交换芯片和目标设备；时钟控制器，被设置为生成目标设备类型所对应的目标控制信号；向时钟选择器发送目标控制信号；时钟选择器，被设置为接收目标控制信号；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，其中，时钟选择器分别与第一时钟发生器和第二时钟发生器连接，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号；时钟控制器，被设置为在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；向时钟选择器发送第一控制信号，或者，第二控制信号；时钟选择器，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器中的参考时钟发生器允许生成多个时钟信号，其中，时钟控制设备，被设置为缓存多个时钟信号，并采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；将信号质量最高的参考时钟信号确定为参考时钟发生器对应的时钟信号。
在一个示例性实施例中，时钟控制设备，包括：时钟控制器，时钟选择器和时钟缓冲器，其中，时钟控制器与时钟选择器连接，时钟选择器允许连接多种时钟类型的时钟发生器，交换芯片和目标设备，时钟缓冲器连接在参考时钟发生器和时钟选择器之间；时钟控制器，被设置为生成参考时钟信号所对应的参考控制信号；向时钟缓冲器发送参考控制信号；生成目标设备类型所对应的目标控制信号；向时钟选择器发送目标控制信号；时钟缓冲器，被设置为接收参考控制信号；将参考控制信号对应的参考时钟信号传输至时钟选择器；时钟选择器，被设置为接收目标控制信号；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，时钟控制设备，还被设置为：对多个时钟信号进行采样，得到多个采样信号；计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个采样信号的信号参数转换为每个采样信号的信号质量。
在一个示例性实施例中，时钟控制设备允许与处理器连接，其中，时钟控制设备被设置为接收处理器发送的目标设备类型。
在一个示例性实施例中，交换板还包括：上行连接器，下行连接器和第三时钟发生器，其中，第三时钟发生器与时钟控制设备连接，时钟控制设备通过上行连接器与处理器的第四时钟发生器连接，多种时钟类型的时钟发生器包括第三时钟发生器和第四时钟发生器；时钟控制设备通过下行连接器与目标设备连接。
根据本申请的另一个实施例，提供了一种交换芯片的时钟控制系统，包括：交换板和设备板，其中，交换板上部署了交换芯片和时钟控制设备，设备板上部署了设备接口；设备接口，被设置为连接目标设备，其中，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类 型与多种设备类型对应；时钟控制设备，被设置为识别目标设备在多种设备类型中所属于的目标设备类型；将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
在一个示例性实施例中，系统还包括：主板，其中，交换板上还部署了第三时钟发生器，主板上部署了处理器的第四时钟发生器，时钟控制设备，包括：时钟控制器和时钟选择器；时钟控制器与时钟选择器连接，时钟选择器与第三时钟发生器，第四时钟发生器，交换芯片和目标设备，第三时钟发生器被设置为传输非同源时钟信号，第四时钟发生器被设置为传输同源时钟信号；时钟控制器，被设置为在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；向时钟选择器发送第一控制信号，或者，第二控制信号；时钟选择器，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，第四时钟发生器允许生成多个时钟信号，时钟控制设备，还包括：时钟缓冲器，其中，时钟缓冲器连接在第四时钟发生器和时钟选择器之间；时钟控制器，被设置为采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；将信号质量最高的参考时钟信号确定为第四时钟发生器对应的时钟信号；生成参考时钟信号所对应的参考控制信号；向时钟缓冲器发送参考控制信号；时钟缓冲器，被设置为缓存多个时钟信号；接收参考控制信号；将参考控制信号对应的参考时钟信号传输至时钟选择器。
在一个示例性实施例中，主板上还部署了处理器，时钟控制设备与处理器连接，其中，处理器通过交换板和设备板与目标设备连接；处理器，被设置为在对目标设备的训练过程中输出目标设备的目标设备类型；将目标设备类型发送至时钟控制设备；时钟控制设备，被设置为接收处理器发送的目标设备类型。
根据本申请的另一个实施例，提供了一种交换芯片的时钟控制方法，应用于时钟控制设备，方法包括：
接收多种时钟类型的时钟发生器传输的时钟信号，其中，时钟控制设备与交换芯片连接，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；
识别目标设备在多种设备类型中所属于的目标设备类型；
将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
在一个示例性实施例中，将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，包括：
生成目标设备类型所对应的目标控制信号；
将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号；
生成目标设备类型所对应的目标控制信号，包括：在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；
将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备，包括：在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器中的参考时钟发生器被设置为生成多个时钟信号，其中，接收多种时钟类型的时钟发生器传输的时钟信号，包括：
缓存多个时钟信号；
采集多个时钟信号的信号参数；
根据信号参数确定多个时钟信号中每个时钟信号的信号质量；
将信号质量最高的参考时钟信号确定为参考时钟发生器传输的时钟信号。
在一个示例性实施例中，采集多个时钟信号的信号参数，包括：
对多个时钟信号进行采样，得到多个采样信号；
计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数。
在一个示例性实施例中，识别目标设备在多种设备类型中所属于的目标设备类型，包括：
接收时钟控制设备所连接的处理器发送的目标设备类型。
根据本申请的另一个实施例，提供了一种交换芯片的时钟控制装置，包括：
接收模块，被设置为接收多种时钟类型的时钟发生器传输的时钟信号，其中，时钟控制设备与交换芯片连接，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；
识别模块，被设置为识别目标设备在多种设备类型中所属于的目标设备类型；
传输模块，被设置为将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
根据本申请的又一个实施例，还提供了一种非易失性可读存储介质，非易失性可读存储介质中存储有计算机程序，其中，计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本申请的又一个实施例，还提供了一种电子设备，包括存储器和处理器，存储器中存储有计算机程序，处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
通过本申请，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
附图说明
图1是根据本申请实施例的一种交换芯片的时钟控制设备的示意图一；
图2是根据本申请实施例的一种交换芯片的时钟控制设备的示意图二；
图3是根据本申请实施例的一种交换芯片的时钟控制设备的示意图三；
图4是根据本申请实施例的一种交换芯片的时钟控制设备的示意图四；
图5是根据本申请实施例的一种交换芯片的时钟控制设备的示意图五；
图6是根据本申请实施例的一种交换芯片的时钟控制设备的示意图六；
图7是根据本申请实施例的一种交换芯片的时钟控制设备的示意图七；
图8是根据本申请实施例的一种交换板的示意图；
图9是根据本申请实施例的一种交换板的工作过程的示意图；
图10是根据本申请实施例的一种部署了时钟发生器的主板的示意图；
图11是根据本申请实施例的一种部署了目标设备的设备板的示意图；
图12是根据本申请实施例的一种交换芯片的时钟控制系统的示意图；
图13是根据本申请可选的实施方式的一种交换芯片的时钟控制系统中时钟控制过程的示意图；
图14是本申请实施例的一种交换芯片的时钟控制方法的移动终端的硬件结构框图；
图15是根据本申请实施例的交换芯片的时钟控制的流程图；
图16是根据本申请可选的实施方式的一种交换芯片的时钟控制系统中时钟控制过程的示意图；
图17是根据本申请实施例的一种交换芯片的时钟控制装置的结构框图；
图18是根据本申请实施例的电子设备的示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本申请的实施例。
需要说明的是，本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
在本实施例中提供了一种交换芯片的时钟控制设备，图1是根据本申请实施例的一种交换芯片的时钟控制设备的示意图一，如图1所示，上述交换芯片的时钟控制设备可以包括：时钟控制器102和时钟选择器104，其中，时钟控制器102与时钟选择器104连接，时钟选择器104允许连接多种时钟类型的时钟发生器(106-1至106-n)、交换芯片108和目标设备110，交换芯片108在控制属于不同设备类型的目标设备110时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；时钟控制器102，被设置为识别目标设备110在多种设备类型中所属于的目标设备110类型；控制时钟选择器104将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片108和目标设备110，其中，目标时钟发生器是目标设备110类型所对应的目标时钟类型的时钟发生器。
通过上述设备，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟 信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
可选地，在本实施例中，上述时钟控制设备被设置为接收多种始终类型的时钟发生器传输的时钟信号，并且从多种时钟信号中选择与目标设备对应的时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时能够使用对应的时钟类型。
可选地，在本实施例中，上述时钟控制设备可以但不限于包括时钟控制器和时钟选择器，可以但不限于通过时钟控制设备内的多个器件实现时钟控制设备的功能，比如：通过时钟控制器获取目标设备在多种设备类型中所属于的目标设备类型，并根据目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，时钟控制器可以但不限于通过控制输出的目标控制信号的电平的高低的方式控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，比如：在目标控制信号输出低电平的情况下，用于指示时钟选择器选择同源时钟。或者，在目标控制信号输出高电平的情况下，用于指示时钟选择器选择非同源时钟。
可选地，在本实施例中，上述时钟发生器可以但不限于是能够产生并传输时钟信号的设备，比如：石英晶体(External Crystal Oscillator，XTAL)和晶体振荡器等等。上述时钟发生器的时钟类型可以但不限于包括：同源时钟和非同源时钟。
可选地，在本实施例中，上述时钟发生器可以但不限于是能够同时发送多个时钟信号的设备，比如：时钟控制设备接收到了同一时钟发生器发出的多个时钟信号，以及另一时钟类型不同的时钟发生器发出的多个时钟信号。或者，时钟控制设备接收到了同一时钟发生器发出的多个时钟信号，以及另一时钟类型不同的时钟发生器发出的单个时钟信号。
可选地，在本实施例中，上述交换芯片可以但不限于是具有控制目标设备的功能的器件，比如：CXL SW芯片。可以但不限于根据目标设备的设备类型确定交换芯片所使用的时钟类型，比如：在目标设备的目标设备类型为PCIe设备的情况下，确定交换芯片所使用的时钟类型为同源时钟。或者，在目标设备的目标设备类型为CXL设备的情况下，确定交换芯片所使用的时钟类型为非同源时钟。
在一个示例性实施例中，图2是根据本申请实施例的一种交换芯片的时钟控制设备的示意图二，如图2所示，时钟控制器102上部署了第一控制端口202，时钟选择器104上部署了多个时钟端口(204-1至204-n)，第一输出端口206，第二输出端口208和第一信号端口210，其中，第一控制端口202与第一信号端口210连接，多个时钟端口(204-1至204-n)用于分别连接多种时钟类型的时钟发生器(106-1至106-n)，第一输出端口206被设置为连接交换芯片108，第二输出端口208被设置为连接目标设备110；时钟控制器102，被设置为生成目标设备110类型所对应的目标控制信号；通过第一控制端口202向时钟选择器104发送目标控制信号；时钟选择器104，被设置为通过第一信号端口210接收目标控制信号；将目标控制信号对应的目标时钟端口212上接收到的目标时钟信号传输至第一输出端口206和第二输出端口208。
可选地，在本实施例中，上述时钟控制器上可以但不限于部署了多个端口，可以但不限于通过时钟控制器上部署的第一控制端口连接时钟选择器，时钟控制器可以通过第一控制端口向时钟选择器发送用于控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备的信号。
可选地，在本实施例中，时钟选择器上可以但不限于部署了多个端口包括：多个时钟端口，第一输出端口，第二输出端口和第一信号端口等等。
可选地，在本实施例中，时钟选择器上部署的多个时钟端口连接多种时钟类型的时钟发生器，可以但不限于用于接收多种时钟类型的时钟发生器发出的时钟信号。
可选地，在本实施例中，时钟选择器上部署的第一输出端口连接交换芯片，可以但不限于用于将与目标设备对应的时钟信号发送至交换芯片。
可选地，在本实施例中，时钟选择器上部署的第二输出端口连接目标设备，可以但不限于用于将与目标设备对应的时钟信号发送至目标设备。
可选地，在本实施例中，时钟控制器上部署的第一控制端口连接时钟选择器，可以但不限于用于将目标控制信号发送至接时钟选择器，比如：时钟控制器根据目标设备的目标设备类型生成对应的目标控制信号，再通过第一控制端口将目标控制信号传输至时钟选择器。
可选地，在本实施例中，时钟选择器上部署的第一信号端口连接时钟控制器，可以但不限于用于接收时钟控制器发出的目标控制信号，比如：时钟控制器通过第一控制端口将目标控制信号传输，时钟选择器通过第一信号端口接收目标控制信号。
在一个示例性实施例中，图3是根据本申请实施例的一种交换芯片的时钟控制设备的示意图三，如图3所示，多个时钟端口(204-1至204-n)包括第一时钟端口302和第二时钟端口304，其中，第一时钟端口302允许与同源类型的第一时钟发生器306连接，第二时钟端口304允许与非同源类型的第二时钟发生器308连接，第一时钟发生器306被设置为传输同源时钟信号，第二时钟发生器308被设置为传输非同源时钟信号；时钟控制器102，被设置为在目标设备110类型为第一类型的情况下，生成第一控制信号，其中，第 一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备110类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；通过第一控制端口202向时钟选择器104发送第一控制信号，或者，第二控制信号；时钟选择器104，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至第一输出端口206和第二输出端口208；在接收到第二控制信号的情况下，将非同源时钟信号传输至第一输出端口206和第二输出端口208。
可选地，在本实施例中，时钟控制器的多个时钟端口被设置为连接多种时钟类型的时钟发生器，时钟端口可以但不限于包括第一时钟端口和第二时钟端口，第一时钟端口和第二时钟端口所连接的时钟发生器的时钟类型不同。
可选地，在本实施例中，第一时钟发生器通过第一时钟端口与时钟控制器连接，第一时钟端口被设置为接收第一时钟发生器发出的同源时钟信号。
可选地，在本实施例中，第二时钟发生器通过第二时钟端口与时钟控制器连接，第二时钟端口被设置为接收第二时钟发生器发出的非同源时钟信号。
可选地，在本实施例中，上述第一控制信号用于将同源时钟信号传输至第一输出端口和第二输出端口，上述第二控制信号用于将非同源时钟信号传输至第一输出端口和第二输出端口。以通过时钟控制设备中的时钟控制器生成目标设备类型所对应的目标控制信号，第一输出端口和第二输出端口部署在时钟控制设备中的时钟选择器为例，在时钟选择器接收到第一控制信号的情况下，将同源时钟信号传输至第一输出端口和第二输出端口；在时钟选择器接收到第二控制信号的情况下，将非同源时钟信号传输至第一输出端口和第二输出端口。
在一个示例性实施例中，图4是根据本申请实施例的一种交换芯片的时钟控制设备的示意图四，如图4所示，时钟控制器102上部署了设备类型端口402，其中，设备类型端口402允许与处理器404连接，设备类型端口402被设置为接收处理器404发送的目标设备类型。
可选地，在本实施例中，上述处理器可以但不限于部署在与时钟控制设备连接的主板上，上述处理器可以但不限于通过总线读取目标设备的目标设备类型，比如：处理器通过PCIe总线读取PCIe插槽或者CXL插槽的目标设备，并将目标设备的目标设备类型发送至时钟控制设备。
可选地，在本实施例中，时钟控制器上还部署了设备类型端口，设备类型端口可以但不限于被设置为连接部署在主板上的处理器，通过设备类型端口接收主板的处理器发送的目标设备类型。
可选地，在本实施例中，时钟控制设备可以但不限于根据从处理器接收到的数据确定目标设备的目标设备类型，比如：以0x50、0x56表示目标设备类型为PCIe设备为例，在时钟控制设备连续接收到0x50、0x56的情况下，则可以确定目标设备在多种设备类型中所属于的目标设备类型为PCIe设备。或者，以0x27、0x29表示目标设备类型为CXL设备为例，在时钟控制设备连续接收到0x27、0x29的情况下，则可以确定目标设备在多种设备类型中所属于的目标设备类型为CXL设备。
可选地，在本实施例中，主板上的处理器可以但不限于被设置为获取目标设备的目标设备类型，比如：主板上的处理器与目标设备通过一组PCIe x16高速线联接，通过PCIe x16高速线识别目标设备的目标设备类型，处理器再通过I2C_CPU信号向时钟控制器发送目标设备的目标设备类型。
在一个示例性实施例中，图5是根据本申请实施例的一种交换芯片的时钟控制设备的示意图五，如图5所示，时钟控制设备，还包括：时钟缓冲器502，其中，时钟控制器102与时钟缓冲器502连接，时钟缓冲器502还连接在多种时钟类型的时钟发生器(106-1至106-n)中的参考时钟发生器504和时钟选择器104之间；参考时钟发生器504，被设置为生成多个时钟信号；时钟缓冲器502，被设置为缓存多个时钟信号；时钟控制器102，被设置为采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；控制时钟缓冲器502将信号质量最高的参考时钟信号传输至时钟选择器104。
可选地，在本实施例中，可以但不限于通过时钟控制设备中的时钟缓冲器缓存多个时钟信号，比如：在时钟控制器从主板接收多种时钟类型的时钟发生器传输的时钟信号的情况下，通过时钟缓冲器将主板传输的多个时钟信号进行缓存。
可选地，在本实施例中，可以但不限于通过时钟控制器对时钟缓冲器中缓存的多个时钟信号进行计算得到多个时钟信号的信号参数，比如：首先，时钟控制器对时钟缓冲器中缓存的多个时钟信号进行采样，得到采样信号，计算采样信号的信号参数。
可选地，在本实施例中，信号参数用于指示时钟信号的信号质量，信号参数可以但不限于包括：时钟信号的振幅、频率、斜率和抖动等等参数。
可选地，在本实施例中，时钟控制器可以但不限于将根据信号参数选择信号质量最优的时钟信号确定为参考时钟信号，比如：时钟控制器对每个时钟信号的信号参数求平均值，将平均值最大的时钟信号确定为信号质量最优的时钟信号即参考时钟信号。或者，时钟控制器对每个时钟信号的信号参数求加权平均值，将加权平均值最大的时钟信号确定为信号质量最优的时钟信号即参考时钟信号。
在一个示例性实施例中，图6是根据本申请实施例的一种交换芯片的时钟控制设备的示意图六，如图6所示，时钟控制器102上部署了第二控制端口602，时钟缓冲器502上部署了多个参考时钟端口(604-1至604-n)，第三输出端口606和第二信号端口608，其中，第二控制端口602与第二信号端口608连接，多 个参考时钟端口(604-1至604-n)被设置为连接参考时钟发生器504，第三输出端口606被设置为连接时钟选择器104；时钟控制器102，被设置为生成参考时钟信号所对应的参考控制信号；通过第二控制端口602向时钟缓冲器502发送参考控制信号；时钟缓冲器502，被设置为通过第二信号端口608接收参考控制信号；将参考控制信号对应的参考时钟信号传输至第三输出端口606。
可选地，在本实施例中，时钟控制器上部署的第二控制端口可以但不限于与时钟缓冲器的第二信号端口连接，第二信号端口可以但不限于用于对多个时钟信号进行采样，得到多个采样信号。
可选地，在本实施例中，时钟缓冲器上部署的参考时钟端口可以但不限于与参考时钟发生器连接，参考时钟端口可以但不限于被设置为接收参考时钟发生器发送的时钟信号并进行缓存操作。
可选地，在本实施例中，时钟缓冲器上部署的第三输出端口可以但不限于与时钟选择器连接，可以但不限于根据时钟控制器发出的参考控制信号确定参考控制信号对应的时钟信号，通过第三输出端口将参考控制信号传输至时钟选择器。
在一个示例性实施例中，图7是根据本申请实施例的一种交换芯片的时钟控制设备的示意图七，如图7所示，时钟控制设备，还包括：信号采集器702，其中，信号采集器702连接在参考时钟发生器504和时钟控制器102之间；信号采集器702，被设置为对多个时钟信号进行采样，得到多个采样信号；将多个采样信号传输至时钟控制器102；时钟控制器102，被设置为计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个采样信号的信号参数转换为每个采样信号的信号质量。
可选地，在本实施例中，信号采集器被设置为在时钟发生器向时钟缓冲器发送时钟信号的过程中，对每个时钟信号进行采样得到多个采样信号。
可选地，在本实施例中，信号采集器可以但不限于将多个时钟信号在同一时间段内的信号确定为采样信号，比如：截取同一时间段内的多个时钟信号，确定为采样信号。
可选地，在本实施例中，采样信号的信号参数用于指示采样信号的信号质量，比如：可以但不限于根据振幅参数、频率参数、斜率参数和抖动参数的平均值确定采样信号的信号质量。或者，可以但不限于根据振幅参数、频率参数、斜率参数和抖动参数的加权平均值确定采样信号的信号质量。
根据本申请实施例的另一个方面，还提供了一种交换板，由于该交换板被设置为实现上述实施例及可选实施方式，已经进行过说明的不再赘述。
图8是根据本申请实施例的一种交换板的示意图，如图8所示，该交换板可以包括：交换芯片802和时钟控制设备804，其中，时钟控制设备804与交换芯片802连接，时钟控制设备804还允许与目标设备806和多种时钟类型的时钟发生器(808-1至808-n)连接；交换芯片802在控制属于不同设备类型的目标设备806时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；时钟控制设备804，被设置为识别目标设备806在多种设备类型中所属于的目标设备类型；将多种时钟类型的时钟发生器(808-1至808-n)中的目标时钟发生器所传输的目标时钟信号传输至交换芯片802和目标设备806，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
通过上述交换板，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
在一个示例性实施例中，时钟控制设备，包括：时钟控制器和时钟选择器，其中，时钟控制器与时钟选择器连接，时钟选择器允许连接多种时钟类型的时钟发生器，交换芯片和目标设备；时钟控制器，被设置为生成目标设备类型所对应的目标控制信号；向时钟选择器发送目标控制信号；时钟选择器，被设置为接收目标控制信号；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，多种时钟类型的时钟发生器可以但不限于部署在交换板上，比如：交换板上部署了多个时钟发生器。或者，多种时钟类型的时钟发生器可以但不限于部署在与交换板连接的设备上，比如：多种时钟类型的时钟发生器部署在与交换板连接的主板上。
可选地，在本实施例中，交换板上可以但不限于部署了时钟控制器和时钟选择器，时钟控制器可以但不限于通过目标设备类型生成目标控制信号再将目标控制信号发送至时钟选择器，控制时钟选择器选择目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，其中，时钟选择器分别与第一时钟发生器和第二时钟发生器连接，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号；时钟控制器，被设置为在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快 速连接协议的设备类型；向时钟选择器发送第一控制信号，或者，第二控制信号；时钟选择器，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，多种时钟类型的时钟发生器中的参考时钟发生器允许生成多个时钟信号，其中，时钟控制设备，被设置为缓存多个时钟信号，并采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；将信号质量最高的参考时钟信号确定为参考时钟发生器对应的时钟信号。
可选地，在本实施例中，参考时钟发生器可以生成多个时钟信号，比如：时钟控制设备连接多种类型的时钟发生器，可以但不限于包括同源时钟发生器和非同源时钟发生器，在参考时钟发生器为同源时钟发生器的情况下，允许同源时钟发生器生成多个时钟信号。或者，在参考时钟发生器为非同源时钟发生器的情况下，允许非同源时钟发生器生成多个时钟信号。
在一个示例性实施例中，时钟控制设备，包括：时钟控制器，时钟选择器和时钟缓冲器，其中，时钟控制器与时钟选择器连接，时钟选择器允许连接多种时钟类型的时钟发生器，交换芯片和目标设备，时钟缓冲器连接在参考时钟发生器和时钟选择器之间；时钟控制器，被设置为生成参考时钟信号所对应的参考控制信号；向时钟缓冲器发送参考控制信号；生成目标设备类型所对应的目标控制信号；向时钟选择器发送目标控制信号；时钟缓冲器，被设置为接收参考控制信号；将参考控制信号对应的参考时钟信号传输至时钟选择器；时钟选择器，被设置为接收目标控制信号；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，时钟缓冲器连接在参考时钟发生器和时钟选择器之间，时钟缓冲器被设置为对参考时钟发生器向时钟选择器发送的时钟信号进行缓存，时钟缓冲器可以但不限于根据时钟控制器指示的与目标设备类型对应的参考控制信号确定向时钟选择器发送的时钟信号。
可选地，在本实施例中，时钟控制器可以但不限于被设置为控制时钟缓冲器发送参考时钟信号至时钟选择器，时钟控制器还被设置为控制时钟选择器发送目标时钟信号至交换芯片和目标设备，比如：时钟控制器接收目标设备的目标设备类型，并根据目标设备类型生成参考控制信号和目标控制信号，时钟控制器将参考控制信号发送至时钟缓冲器，控制时钟缓冲器向时钟选择器传输参考时钟信号；时钟控制器将目标控制信号发送至时钟选择器，控制时钟选择器将目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，时钟控制设备，还被设置为：对多个时钟信号进行采样，得到多个采样信号；计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个采样信号的信号参数转换为每个采样信号的信号质量。
在一个示例性实施例中，时钟控制设备允许与处理器连接，其中，时钟控制设备被设置为接收处理器发送的目标设备类型。
在一个示例性实施例中，交换板还包括：上行连接器，下行连接器和第三时钟发生器，其中，第三时钟发生器与时钟控制设备连接，时钟控制设备通过上行连接器与处理器的第四时钟发生器连接，多种时钟类型的时钟发生器包括第三时钟发生器和第四时钟发生器；时钟控制设备通过下行连接器与目标设备连接。
可选地，在本实施例中，时钟控制设备可以但不限于与包括第三时钟发生器和第四时钟发生器的时钟发生器连接，第三时钟发生器与时钟控制设备可以是直接连接的，部署在非交换板上的处理器的第四时钟发生器与时钟控制设备可以但不限于是通过交换板的上行连接器连接的。
可选地，在本实施例中，交换板的下行连接器被设置为连接目标设备，可以但不限于通过下行连接器获取目标设备的设备信息，比如：通过下行连接器获取目标设备的厂商、容量、速率等等信息。
在一个示例性实施例中，提供了一种交换板包括：交换芯片、时钟控制设备、第三时钟发生器、上行连接器和下行连接器，图9是根据本申请实施例的一种交换板的工作过程的示意图，如图9所示，交换芯片为CXL SW芯片，时钟控制设备包括时钟控制器、时钟选择器和时钟缓冲器，可选的，时钟控制器为CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)控制单元，时钟选择器为CLK MUX，时钟缓冲器为CLK Buffer，第三时钟发生器为CLK Generator，上行连接器为上行口CDFP(Compact Duplex Form-factor Pluggable，紧凑型双工外形可插拔模块)连接器，下行连接器为下行口CDFP连接器，以主板上部署了被设置为传输同源时钟信号的第一时钟发生器，第三时钟发生器CLK Generator被设置为传输非同源时钟信号为例，交换板可以通过以下方式工作：
以第三时钟发生器CLK Generator包括一颗25MHz的时钟晶体XTAL(Crystal，晶体)为例，XTAL供给第三时钟发生器内部PLL(Phase-Locked Loop，锁相环)，第三时钟发生器从而输出100MHz的CLK_GEN时钟信号。
CPLD控制单元通过I2C、PERST_N信号读取下行口CDFP连接器的目标设备的相关信息，比如：通过I2C信号读取目标设备的厂商、容量、速率等等相关信息，通过PERST_N信号对目标设备进行复位操作等等。
上行口CDFP连接器与下行口CDFP连接器通过一组PCIe x16高速线联接，上行口CDFP连接器通过与 下行口CDFP连接器联接的PCIe x16高速线识别目标设备的目标设备类型，上行口CDFP连接器的处理器CPU通过I2C_CPU信号向CPLD控制单元发送目标设备的目标设备类型。
交换板的上行口CDFP连接器通过线缆连接主板的CDFP连接器，接收来自主板的同源时钟信号，ADC采样单元(信号采集器)对来自主板的多个同源时钟信号进行采样，通过SPI(Serial Peripheral Interface，串行外设接口)总线将采样信号传输至CPLD控制单元，CPLD控制单元计算采样信号的信号参数：振幅参数、频率参数、斜率参数、抖动参数等等，根据信号参数确定信号质量最优的同源时钟信号。
以接收来自主板的时钟发生器(CLK_1)发出的同源时钟信号CLK_CDFP1和CLK_CDFP2为例，CPLD控制单元通过CLK_S信号控制时钟缓冲器CLK Buffer选择信号质量最优的同源时钟信号输出，比如：在CLK_S输出低电平的情况下，用于指示CLK_CDFP1的信号质量最优，时钟缓冲器CLK buffer将CLK_CDFP1输出至CLK_BUF；在CLK_S输出高电平的情况下，用于指示CLK_CDFP2的信号质量最优，CLK buffer将CLK_CDFP2输出至CLK_BUF。
CLK MUX在CPLD控制单元发出的CLK_MODE信号的控制下，通过以下方式为与下行口CDFP连接器互联的目标设备以及CXL SW选择对应的时钟：
以在CLK_MODE输出低电平的情况下，指示CLK MUX选择同源时钟CLK_BUF为例，CLK MUX的IN_1分别输出同源时钟CLK_BUF到MUX_OUT1、MUX_OUT2，再通过CLK_CXL输入至CXL SW，通过CLK_CDFP输入至与下行口CDFP连接器互联的目标设备，使得与下行口CDFP连接器互联的目标设备以及CXL SW的时钟都为同源时钟。
以在CLK_MODE输出高电平的情况下，指示CLK MUX选择非同源时钟CLK_GEN为例，IN_2分别输出非同源时钟CLK_GEN到MUX_OUT1、MUX_OUT2，再通过CLK_CXL输入至CXL SW，通过CLK_CDFP输入至与下行口CDFP连接器互联的目标设备，使得与下行口CDFP连接器互联的目标设备以及CXL SW的时钟都为非同源时钟。
在一个示例性实施例中，时钟控制设备与部署了时钟发生器的主板连接，图10是根据本申请实施例的一种部署了时钟发生器的主板的示意图，如图10所示，主板包括：XTAL(一颗25MHz的时钟晶体)、时钟发生器CLK Generator、处理器CPU、CDFP连接器，主板可以通过以下方法向时钟控制设备发送时钟信号：时钟晶体XTAL供给时钟发生器CLK Generator内部PLL，从而输出100MHz的PCIe时钟；CLK Generator通过输出端CLK_OUTO输出25MHz的CLK_CPU时钟到CPU，CPU通过一组PCIe x16高速线与CDFP连接器的PCIe设备连接，以及通过I2C与CDFP连接器的I2C设备连接；CLK Generator通过输出端CLK_OUT1输出100MHz的CLK_CDFP1至同源时钟信号到CDFP连接器的CLK_CDFP_OUT1端口，以及通过输出端CLK_OUT2输出100MHz的CLK_CDFP2至同源时钟信号到CDFP连接器的CLK_CDFP_OUT2端口；CDFP连接器被设置为连接交换板上部署的交换芯片。
主板可以通过以下方法向时钟控制器发送目标设备类型：CPU通过I2C总线与交换板的时钟控制器连接，通过I2C_CPU信号向CPLD控制单元发送目标设备的目标设备类型(可以但不限于包括PCIe设备和CXL设备)。
在一个示例性实施例中，提供了部署了目标设备的设备板，图11是根据本申请实施例的一种部署了目标设备的设备板的示意图，如图11所示，设备板包括：CDFP连接器、PCIe插槽或者CXL插槽(PCIe/CXL插槽)、PCIe设备或者CXL设备(PCIe/CXL设备)，PCIe设备或者CXL设备带有EEPROM(Electrically Erasable Programmable Read-Only Memory，电可擦可编程只读存储器)，EEPROM被设置为存放生产厂商、容量、速率等等信息。CDFP连接器通过I2C端口获取EEPROM中存储的信息；CDFP连接器通过RST_N(可以但不限于被设置为指示复位信号)对PCIe设备或者CXL设备进行复位操作；CDFP连接器通过CLK_OUT连接CLK_IN传输时钟信号；CDFP连接器通过PCIe读取插槽中部署的设备。设备板可以通过以下方式向交换板的时钟控制设备发送目标设备类型：
在设备板开机上电完成的情况下，主板的处理器CPU通过PCIe总线自动识别PCIe插槽或者CXL插槽的目标设备，将目标设备类型通过I2C_CPU总线发送至交换板的时钟控制器CPLD，在时钟控制器CPLD连续接收到0x50、0x56等等信号的情况下，可以但不限于认为目标设备的目标设备类型为PCIe设备；在时钟控制器CPLD连续接收到0x27、0x29等等信号的情况下，可以但不限于认为目标设备的目标设备类型为CXL设备。
根据本申请实施例的另一个方面，还提供了一种交换芯片的时钟控制系统，由于该交换板被设置为实现上述实施例及可选实施方式，已经进行过说明的不再赘述。
图12是根据本申请实施例的一种交换芯片的时钟控制系统的示意图，如图12所示，该交换芯片的时钟控制系统可以包括：交换板1202和设备板1204，其中，交换板1202上部署了交换芯片1206和时钟控制设备1208，设备板1204上部署了设备接口1210；设备接口1210，被设置为连接目标设备1212，其中，交换芯片1206在控制属于不同设备类型的目标设备1212时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；时钟控制设备1208，被设置为识别目标设备1212在多种设备类型中所属于的目标设备类型；将多种时钟类型的时钟发生器(1214-1至1214-n)中的目标时钟发生器1216所传输的目标时钟信号传输至交换芯片1206和目标设备1212，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型 的时钟发生器。
通过上述系统，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
在一个示例性实施例中，时钟控制器上部署了第一控制端口，时钟选择器上部署了多个时钟端口，第一输出端口，第二输出端口和第一信号端口，其中，第一控制端口与第一信号端口连接，多个时钟端口被设置为分别连接多种时钟类型的时钟发生器，第一输出端口被设置为连接交换芯片，第二输出端口被设置为连接目标设备；时钟控制器，被设置为生成目标设备类型所对应的目标控制信号；通过第一控制端口向时钟选择器发送目标控制信号；时钟选择器，被设置为通过第一信号端口接收目标控制信号；将目标控制信号对应的目标时钟端口上接收到的目标时钟信号传输至第一输出端口和第二输出端口。
在一个示例性实施例中，系统还包括：主板，其中，交换板上还部署了第三时钟发生器，主板上部署了处理器的第四时钟发生器，时钟控制设备，包括：时钟控制器和时钟选择器；时钟控制器与时钟选择器连接，时钟选择器与第三时钟发生器，第四时钟发生器，交换芯片和目标设备，第三时钟发生器被设置为传输非同源时钟信号，第四时钟发生器被设置为传输同源时钟信号；时钟控制器，被设置为在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；向时钟选择器发送第一控制信号，或者，第二控制信号；时钟选择器，被设置为在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，主板可以但不限于包括时钟发生器，主板的时钟发生器可以但不限于通过以下方式提供时钟信号：XTAL供给CLK generator内部PLL，从而输出100MHz的PCIe时钟。
可选地，在本实施例中，主板可以但不限于包括时钟发生器和处理器，主板的处理器可以但不限于通过以下方式获取目标设备的目标设备类型：CPU通过I2C总线与交换板的时钟控制器连接，通过I2C_CPU信号向CPLD控制单元发送目标设备的目标设备类型(可以但不限于包括PCIe设备和CXL设备)。
在一个示例性实施例中，第四时钟发生器允许生成多个时钟信号，时钟控制设备，还包括：时钟缓冲器，其中，时钟缓冲器连接在第四时钟发生器和时钟选择器之间；时钟控制器，被设置为采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；将信号质量最高的参考时钟信号确定为第四时钟发生器对应的时钟信号；生成参考时钟信号所对应的参考控制信号；向时钟缓冲器发送参考控制信号；时钟缓冲器，被设置为缓存多个时钟信号；接收参考控制信号；将参考控制信号对应的参考时钟信号传输至时钟选择器。
在一个示例性实施例中，时钟控制器上部署了第二控制端口，时钟缓冲器上部署了多个参考时钟端口，第三输出端口和第二信号端口，其中，第二控制端口与第二信号端口连接，多个参考时钟端口被设置为连接参考时钟发生器，第三输出端口被设置为连接时钟选择器；时钟控制器，被设置为生成参考时钟信号所对应的参考控制信号；通过第二控制端口向时钟缓冲器发送参考控制信号；时钟缓冲器，被设置为通过第二信号端口接收参考控制信号；将参考控制信号对应的参考时钟信号传输至第三输出端口。
在一个示例性实施例中，时钟控制设备，还包括：信号采集器，其中，信号采集器连接在参考时钟发生器和时钟控制器之间；信号采集器，被设置为对多个时钟信号进行采样，得到多个采样信号；将多个采样信号传输至时钟控制器；时钟控制器，被设置为计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个采样信号的信号参数转换为每个采样信号的信号质量。
在一个示例性实施例中，主板上还部署了处理器，时钟控制设备与处理器连接，其中，处理器通过交换板和设备板与目标设备连接；处理器，被设置为在对目标设备的训练过程中输出目标设备的目标设备类型；将目标设备类型发送至时钟控制设备；时钟控制设备，被设置为接收处理器发送的目标设备类型。
在一个示例性实施例中，提供了一种交换芯片的时钟控制系统，图13是根据本申请可选的实施方式的一种交换芯片的时钟控制系统中时钟控制过程的示意图，如图13所示，交换芯片的时钟控制系统包括主板、交换板和设备板，其中，主板包括部署在主板的时钟发生器和处理器CPU，主板时钟发生器被设置为给CPU提供时钟信号并向交换板发送第一时钟信号。
交换板包括时钟缓冲器、时钟控制器、时钟选择器、部署在交换板的时钟发生器和交换芯片CXL SW，其中，时钟缓冲器、时钟控制器和时钟选择器被设置为从主板时钟发生器发出的第一时钟信号中解析质量最高的时钟信号，时钟控制器还被设置为解析设备板上部署的目标设备(可以但不限于为CXL设备或者PCIe设备)输出控制信号到时钟缓冲器；交换板时钟发生器被设置为输出第二时钟信号到时钟选择器，第 一时钟信号与第二时钟信号的类型不同，时钟选择器在时钟控制器发出的控制信号的控制下，向CXL SW和设备板输出同源时钟或者非同源时钟；设备板上部署了CXL设备或者PCIe设备。
以第一时钟信号为同源时钟信号，第二时钟信号为非同源时钟信号为例，交换芯片的时钟控制系统可以采用以下方式工作：
主板时钟发生器向主板的处理器以及交换板的时钟缓冲器发送多个同源时钟信号，交换板的时钟缓冲器对每个同源时钟信号进行缓存操作。
在主板时钟发生器向交换板的时钟缓冲器发送同源时钟信号的过程中，交换板的时钟控制器对主板时钟发生器发出的同源时钟信号进行采样，通过分析确定主板时钟发生器发出的多个同源时钟信号中最优的同源时钟信号，时钟控制器向时钟缓冲器发出参考控制信号，控制时钟缓冲器将最优的同源时钟信号传输至时钟选择器。
交换板时钟发生器向时钟选择器传输非同源时钟信号。
时钟控制器根据设备板上部署的目标设备的目标设备类型(CXL设备或者PCIe设备)向时钟选择器发出相应的控制信号(第一控制信号或者第二控制信号)，控制时钟选择器从同源时钟信号和非同源时钟信号中选择与目标设备类型对应的时钟信号。
时钟选择器根据时钟控制器发出的控制信号，将与目标设备类型对应的时钟信号传输至CXL SW和目标设备。
可以但不限于将CXL SW与PCIe设备的时钟信号来源于主板时钟发生器确定为同源时钟；可以但不限于将CXL SW与CXL设备的时钟信号来源于交换板时钟发生器确定为非同源时钟。
本申请实施例中所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。以运行在移动终端上为例，图14是本申请实施例的一种交换芯片的时钟控制方法的移动终端的硬件结构框图。如图14所示，移动终端可以包括一个或多个(图14中仅示出一个)处理器1402(处理器1402可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和被设置为存储数据的存储器1404，其中，上述移动终端还可以包括被设置为通信功能的传输设备1406以及输入输出设备1408。本领域普通技术人员可以理解，图14所示的结构仅为示意，其并不对上述移动终端的结构造成限定。例如，移动终端还可包括比图14中所示更多或者更少的组件，或者具有与图14所示不同的配置。
存储器1404可被设置为存储计算机程序，例如，应用软件的软件程序以及模块，如本申请实施例中的交换芯片的时钟控制方法对应的计算机程序，处理器1402通过运行存储在存储器1404内的计算机程序，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器1404可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器1404可包括相对于处理器1402远程设置的存储器，这些远程存储器可以通过网络连接至移动终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输设备1406被设置为经由一个网络接收或者发送数据。上述的网络可选实例可包括移动终端的通信供应商提供的无线网络。在一个实例中，传输设备1406包括一个网络适配器(Network Interface Controller，简称为NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输设备1406可以为射频(Radio Frequency，简称为RF)模块，其被设置为通过无线方式与互联网进行通讯。
在本实施例中提供了一种运行于上述移动终端的交换芯片的时钟控制方法，图15是根据本申请实施例的交换芯片的时钟控制的流程图，如图15所示，该流程包括如下步骤：
步骤S1502，接收多种时钟类型的时钟发生器传输的时钟信号，其中，时钟控制设备与交换芯片连接，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；
步骤S1504，识别目标设备在多种设备类型中所属于的目标设备类型；
步骤S1506，将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
通过上述步骤，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
其中，上述步骤的执行主体可以为时钟控制设备，时钟控制设备可以但不限于包括时钟控制器和时钟选择，可以但不限于通过上述时钟控制器识别目标设备在多种设备类型中所属于的目标设备类型；可以但不限于通过时钟选择器将与目标设备类型对应的目标时钟类型的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备。
在上述步骤S1502提供的技术方案中，上述时钟发生器可以但不限于是能够产生并传输时钟信号的设备，比如：石英晶体(XTAL)和晶体振荡器等等。上述时钟发生器的时钟类型可以但不限于包括：同源时钟和非同源时钟。
可选地，在本实施例中，上述时钟发生器可以但不限于是能够同时发送多个时钟信号的设备，比如：时钟控制设备接收到了同一时钟发生器发出的多个时钟信号，以及另一时钟类型不同的时钟发生器发出的多个时钟信号。或者，时钟控制设备接收到了同一时钟发生器发出的多个时钟信号，以及另一时钟类型不同的时钟发生器发出的单个时钟信号。
可选地，在本实施例中，上述目标设备可以但不限于是多种设备类型中的某一设备，比如：采用高速串行计算机扩展总线标准的设备类型的RC，Switch，Endpoint等等。或者，采用计算快速连接协议的设备类型的CXL加速卡，CXL交换机等等。
可选地，在本实施例中，上述交换芯片可以但不限于是具有控制目标设备的功能的器件，比如：CXL SW芯片。可以但不限于根据目标设备的设备类型确定交换芯片所使用的时钟类型，比如：在目标设备的目标设备类型为PCIe设备的情况下，确定交换芯片所使用的时钟类型为同源时钟。或者，在目标设备的目标设备类型为CXL设备的情况下，确定交换芯片所使用的时钟类型为非同源时钟。
在上述步骤S1504提供的技术方案中，目标设备类型可以但不限于是主板上的处理器传输至的时钟控制设备，比如：在时钟控制设备启动的情况下，部署在主板上的处理器通过PCIe总线自动识别PCIe插槽或者CXL插槽的目标设备，并且将识别的目标设备类型通过I2C_CPU总线告知时钟控制设备。
在一个可选的实施方式中，可以但不限于采用以下方式识别目标设备在多种设备类型中所属于的目标设备类型：接收时钟控制设备所连接的处理器发送的目标设备类型。
可选地，在本实施例中，上述处理器可以但不限于部署在与时钟控制设备连接的主板上，上述处理器可以但不限于通过总线读取目标设备的目标设备类型，比如：处理器通过PCIe总线读取PCIe插槽或者CXL插槽的目标设备，并将目标设备的目标设备类型发送至时钟控制设备。
可选地，在本实施例中，上述时钟控制设备可以但不限于被设置为接收目标设备类型，时钟控制设备可以但不限于根据目标设备类型从多种时钟类型的时钟发生器传输的时钟信号中选择与目标设备类型对应的时钟信号。
可选地，在本实施例中，时钟控制设备可以但不限于根据从处理器接收到的数据确定目标设备的目标设备类型，比如：以0x50、0x56表示目标设备类型为PCIe设备为例，在时钟控制设备连续接收到0x50、0x56的情况下，则可以确定目标设备在多种设备类型中所属于的目标设备类型为PCIe设备。或者，以0x27、0x29表示目标设备类型为CXL设备为例，在时钟控制设备连续接收到0x27、0x29的情况下，则可以确定目标设备在多种设备类型中所属于的目标设备类型为CXL设备。
在上述步骤S1506提供的技术方案中，可以但不限于根据目标设备的目标设备类型从多种时钟类型中确定目标时钟类型，比如：根据目标设备的目标设备类型确定交换芯片和目标设备需要的时钟类型为同源时钟。或者，根据目标设备的目标设备类型确定交换芯片和目标设备需要的时钟类型为非同源时钟。
可选地，在本实施例中，可以但不限于将发送目标时钟类型的时钟发生器确定为目标时钟发生器，比如：以有两个同源时钟类型的时钟发生器与两个非同源时钟类型的时钟发生器同时发出了多个时钟信号为例，在根据目标设备的目标设备类型确定交换芯片和目标设备需要的时钟类型为同源时钟的情况下，可以但不限于将两个同源时钟类型的时钟发生器确定为目标时钟发生器。或者，从两个同源时钟类型的时钟发生器中选择较优的一个确定为目标时钟发生器。
在一个可选的实施方式中，可以但不限于采用以下方式将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备：生成目标设备类型所对应的目标控制信号；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，目标控制信号用于指示时钟控制设备从多种时钟类型的时钟发生器中选择目标时钟发生器传输的目标时钟信号进行传输，比如：以同源时钟类型的时钟发生器A发出的时钟信号A和时钟信号B，非同源时钟类型的时钟发生器B发出的时钟信号C和时钟信号D为例，在目标控制信号指示交换芯片和目标设备需要同源时钟类型的时钟信号的情况下，可以但不限于确定发出时钟信号A和时钟信号B的时钟发生器A为目标时钟发生器，可以但不限于从时钟信号A和时钟信号B中选择一个时钟信号确定为目标时钟信号进行传输。
可选地，在本实施例中，时钟控制设备可以但不限于包括时钟控制器以及时钟选择器，可以但不限于通过时钟控制器生成目标设备类型所对应的目标控制信号，可以但不限于通过时钟选择器将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备，比如：时钟控制器根据目标设备的目标设备类型生成目标控制信号传输至时钟选择器，时钟选择器根据目标控制信号从全部的时钟信号中选择目标时钟信号进行传输。或者，时钟控制器根据目标设备的目标设备类型生成目标控制信号传输至时钟选择器，时钟选择器筛选出目标控制信号所指示的时钟类型的第一时钟信号，再从第一时钟信号中选择目标时钟信号进行传输。
可选地，在本实施例中，时钟控制器可以但不限于通过控制输出的目标控制信号的电平的高低指示时 钟选择器选择对应的目标时钟信号，比如：在目标控制信号输出低电平的情况下，用于指示时钟选择器选择同源时钟。或者，在目标控制信号输出高电平的情况下，用于指示时钟选择器选择非同源时钟。
可选地，在本实施例中，可以但不限于通过时钟选择器的第一信号端口接收目标控制信号；将目标控制信号对应的目标时钟端口上接收到的目标时钟信号传输至第一输出端口和第二输出端口。
在一个可选的实施方式中，多种时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号；生成目标设备类型所对应的目标控制信号：在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备，包括：在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，上述第一控制信号用于将同源时钟信号传输至第一输出端口和第二输出端口，上述第二控制信号用于将非同源时钟信号传输至第一输出端口和第二输出端口。以通过时钟控制设备中的时钟控制器生成目标设备类型所对应的目标控制信号，第一输出端口和第二输出端口部署在时钟控制设备中的时钟选择器为例，在时钟选择器接收到第一控制信号的情况下，将同源时钟信号传输至第一输出端口和第二输出端口；在时钟选择器接收到第二控制信号的情况下，将非同源时钟信号传输至第一输出端口和第二输出端口。
可选地，在本实施例中，第一输出端口和第二输出端口可以但不限于被设置为将时钟信号传输至交换芯片和目标设备，比如：以第一输出端口连接交换芯片，第二输出端口连接目标设备为例，通过第一输出端口和第二输出端口将时钟信号传输至交换芯片和目标设备。
可选地，在本实施例中，时钟选择器上可以但不限于部署了多个时钟端口，第一输出端口，第二输出端口和第一信号端口，其中，第一时钟端口允许与同源类型的第一时钟发生器连接，第二时钟端口允许与非同源类型的第二时钟发生器连接，第一时钟发生器被设置为传输同源时钟信号，第二时钟发生器被设置为传输非同源时钟信号。
在一个可选的实施方式中，多种时钟类型的时钟发生器中的参考时钟发生器被设置为生成多个时钟信号，其中，可以但不限于采用以下方式接收多种时钟类型的时钟发生器传输的时钟信号：缓存多个时钟信号；采集多个时钟信号的信号参数；根据信号参数确定多个时钟信号中每个时钟信号的信号质量；将信号质量最高的参考时钟信号确定为参考时钟发生器传输的时钟信号。
可选地，在本实施例中，可以但不限于通过时钟控制设备中的时钟缓冲器缓存多个时钟信号，比如：在时钟控制器从主板接收多种时钟类型的时钟发生器传输的时钟信号的情况下，通过时钟缓冲器将主板传输的多个时钟信号进行缓存。
可选地，在本实施例中，可以但不限于对时钟缓冲器中缓存的多个时钟信号进行计算得到多个时钟信号的信号参数，比如：首先，对时钟缓冲器中缓存的多个时钟信号进行采样，得到采样信号，计算采样信号的信号参数。
可选地，在本实施例中，信号参数用于指示时钟信号的信号质量，信号参数可以但不限于包括：时钟信号的振幅、频率、斜率和抖动等等参数。
可选地，在本实施例中，可以但不限于根据信号参数选择信号质量最优的时钟信号确定为参考时钟信号，比如：对每个时钟信号的信号参数求平均值，将平均值最大的时钟信号确定为信号质量最优的时钟信号即参考时钟信号。或者，对每个时钟信号的信号参数求加权平均值，将加权平均值最大的时钟信号确定为信号质量最优的时钟信号即参考时钟信号。
可选地，在本实施例中，时钟控制器上部署了第二控制端口，时钟缓冲器上部署了多个参考时钟端口，第三输出端口和第二信号端口，其中，第二控制端口与第二信号端口连接，多个参考时钟端口被设置为连接参考时钟发生器，第三输出端口被设置为连接时钟选择器；时钟控制器，被设置为生成参考时钟信号所对应的参考控制信号；通过第二控制端口向时钟缓冲器发送参考控制信号；时钟缓冲器，被设置为通过第二信号端口接收参考控制信号；将参考控制信号对应的参考时钟信号传输至第三输出端口。
在一个可选的实施方式中，可以但不限于采用以下方式采集多个时钟信号的信号参数：对多个时钟信号进行采样，得到多个采样信号；计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数。
可选地，在本实施例中，可以但不限于将多个时钟信号在同一时间段内的信号确定为采样信号，比如：截取同一时间段内的多个时钟信号，确定为采样信号。
可选地，在本实施例中，采样信号的信号参数用于指示采样信号的信号质量，比如：可以但不限于根据振幅参数、频率参数、斜率参数和抖动参数的平均值确定采样信号的信号质量。或者，可以但不限于根据振幅参数、频率参数、斜率参数和抖动参数的加权平均值确定采样信号的信号质量。
可选地，在本实施例中，时钟控制设备，还包括：信号采集器，其中，信号采集器连接在参考时钟发 生器和时钟控制器之间；信号采集器，被设置为对多个时钟信号进行采样，得到多个采样信号；将多个采样信号传输至时钟控制器。
在一个示例性实施例中，提供了一种交换芯片的时钟控制系统，图16是根据本申请可选的实施方式的一种交换芯片的时钟控制系统中时钟控制过程的示意图，如图16所示，可以但不限于包括以下步骤：
步骤S1602：用户将PCIe设备或者CXL设备插在设备板的插槽中，并且对整个交换芯片的时钟控制系统进行上电；
步骤S1604：在处理器训练(training)目标设备的过程中，主板的处理器CPU读取设备板插槽中的目标设备的目标设备类型；
步骤S1606：在完成读取目标设备类型的情况下，处理器通过I2C总线将目标设备类型发送给交换板的时钟控制器CPLD；
步骤S1608：时钟控制器CPLD解析目标设备类型；
在目标设备为CXL设备的情况下(可以但不限于在接收到的数据为0x27、0x29的情况下，时钟控制器解析得到目标设备为CXL设备)，执行步骤S1610至步骤S1618：
步骤S1610：时钟控制器CPLD输出高电平的CXL_MODE信号(即目标控制信号)；
步骤S1612：时钟选择器CLK_MUX将IN_2输出给MUX_OUT1、MUX_OUT2，MUX_OUT1输出至交换芯片CXL SW，MUX_OUT2输出至CXL设备；
步骤S1614：时钟控制器CPLD将PERST_N信号(即参考时钟信号)拉高；
步骤S1616：交换芯片CXL SW与CXL设备获取非同源时钟；
步骤S1618：时钟设配完成。
在目标设备为PCIe设备的情况下(可以但不限于在接收到的数据为0x50、0x56的情况下，时钟控制器解析得到目标设备为PCIe设备)，执行步骤S1620至步骤S1632：
步骤S1620：时钟控制器CPLD通过SPI总线启动ADC采样单元，读取采样信号；
步骤S1622：时钟控制器CPLD计算采样信号的信号参数，选择信号质量最高的参考时钟信号；
步骤S1624：时钟控制器CPLD输出低电平的CXL_MODE信号(即目标控制信号)；
步骤S1626：时钟选择器CLK MUX将IN_1输出给MUX_OUT1、MUX_OUT2，MUX_OUT1输出至交换芯片CXL SW，MUX_OUT2输出至PCIe设备；
步骤S1628：时钟控制器CPLD将PERST_N信号(即参考时钟信号)拉高；
步骤S1630：交换芯片CXL SW与PCIe设备获取同源时钟；
步骤S1632：时钟设配完成。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本申请各个实施例的方法。
在本实施例中还提供了一种交换芯片的时钟控制装置，该装置被设置为实现上述实施例及可选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件，或者软件和硬件的组合的实现也是可能并被构想的。
图17是根据本申请实施例的一种交换芯片的时钟控制装置的结构框图，如图17所示，该装置包括：
接收模块1702，被设置为接收多种时钟类型的时钟发生器传输的时钟信号，其中，时钟控制设备与交换芯片连接，交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种时钟类型与多种设备类型对应；
识别模块1704，被设置为识别目标设备在多种设备类型中所属于的目标设备类型；
传输模块1706，被设置为将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，其中，目标时钟发生器是目标设备类型所对应的目标时钟类型的时钟发生器。
通过上述装置，时钟控制器根据目标设备的目标设备类型控制时钟选择器将多种时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至交换芯片和目标设备，使得交换芯片在控制不同设备类型的目标设备时，能够自动使用对应的时钟类型。也就是说，由于交换芯片需要对应与目标设备的时钟类型对应，通过时钟控制器获取目标设备的目标设备类型，时钟控制器再根据目标设备类型控制时钟选择器选择传输目标时钟信号到达交换芯片和目标设备，使得交换芯片和目标设备能够接收到对应的目标时钟信号，因此，可以解决交换芯片的时钟适配效率较低的问题，达到了提高交换芯片的时钟适配效率的效果。
在一个示例性实施例中，传输模块，被设置为：
通过第二操作系统监控第二操作系统上运行的业务的业务状态；生成目标设备类型所对应的目标控制信号；
通过第二操作系统监控第二操作系统上运行的业务的业务状态；将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，传输模块，还被设置为：
生成目标设备类型所对应的目标控制信号，包括：在目标设备类型为第一类型的情况下，生成第一控制信号，其中，第一类型为采用高速串行计算机扩展总线标准的设备类型；在目标设备类型为第二类型的情况下，生成第二控制信号，其中，第二类型为采用计算快速连接协议的设备类型；
将目标控制信号对应的目标时钟信号传输至交换芯片和目标设备，包括：在接收到第一控制信号的情况下，将同源时钟信号传输至交换芯片和目标设备；在接收到第二控制信号的情况下，将非同源时钟信号传输至交换芯片和目标设备。
在一个示例性实施例中，传输模块，还被设置为：
缓存多个时钟信号；
采集多个时钟信号的信号参数；
根据信号参数确定多个时钟信号中每个时钟信号的信号质量；
将信号质量最高的参考时钟信号确定为参考时钟发生器传输的时钟信号。
在一个示例性实施例中，传输模块，还被设置为：
对多个时钟信号进行采样，得到多个采样信号；
计算多个采样信号的信号参数，其中，每个采样信号的信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数。
在一个示例性实施例中，识别模块，还被设置为：
接收时钟控制设备所连接的处理器发送的目标设备类型。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
本申请的实施例还提供了一种非易失性可读存储介质，该非易失性可读存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述非易失性可读存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
本申请的实施例还提供了一种电子设备，图18是根据本申请实施例的电子设备的示意图，如图18所示，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述电子设备还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
本实施例中的可选示例可以参考上述实施例及示例性实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本申请的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本申请不限制于任何特定的硬件和软件结合。
以上仅为本申请的可选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (28)

  1. 一种交换芯片的时钟控制设备，其特征在于，包括：时钟控制器和时钟选择器，其中，
    所述时钟控制器与所述时钟选择器连接，所述时钟选择器允许连接多种时钟类型的时钟发生器、交换芯片和目标设备，所述交换芯片在控制属于不同设备类型的所述目标设备时使用的时钟信号的时钟类型不同，多种所述时钟类型与多种设备类型对应；
    所述时钟控制器，被设置为识别所述目标设备在多种所述设备类型中所属于的目标设备类型；控制所述时钟选择器将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，其中，所述目标时钟发生器是所述目标设备类型所对应的目标时钟类型的时钟发生器。
  2. 根据权利要求1所述的设备，其特征在于，所述时钟控制器上部署了第一控制端口，所述时钟选择器上部署了多个时钟端口，第一输出端口，第二输出端口和第一信号端口，其中，
    所述第一控制端口与所述第一信号端口连接，多个所述时钟端口被设置为分别连接多种所述时钟类型的时钟发生器，所述第一输出端口被设置为连接所述交换芯片，所述第二输出端口被设置为连接所述目标设备；
    所述时钟控制器，被设置为生成所述目标设备类型所对应的目标控制信号；通过所述第一控制端口向所述时钟选择器发送所述目标控制信号；
    所述时钟选择器，被设置为通过所述第一信号端口接收所述目标控制信号；将所述目标控制信号对应的目标时钟端口上接收到的所述目标时钟信号传输至所述第一输出端口和所述第二输出端口。
  3. 根据权利要求2所述的设备，其特征在于，多个所述时钟端口包括第一时钟端口和第二时钟端口，其中，
    所述第一时钟端口允许与同源类型的第一时钟发生器连接，所述第二时钟端口允许与非同源类型的第二时钟发生器连接，所述第一时钟发生器被设置为传输同源时钟信号，所述第二时钟发生器被设置为传输非同源时钟信号；
    所述时钟控制器，被设置为在所述目标设备类型为第一类型的情况下，生成第一控制信号，其中，所述第一类型为采用高速串行计算机扩展总线标准的设备类型；在所述目标设备类型为第二类型的情况下，生成第二控制信号，其中，所述第二类型为采用计算快速连接协议的设备类型；通过所述第一控制端口向所述时钟选择器发送所述第一控制信号，或者，所述第二控制信号；
    所述时钟选择器，被设置为在接收到所述第一控制信号的情况下，将所述同源时钟信号传输至所述第一输出端口和所述第二输出端口；在接收到所述第二控制信号的情况下，将所述非同源时钟信号传输至所述第一输出端口和所述第二输出端口。
  4. 根据权利要求1所述的设备，其特征在于，所述时钟控制器上部署了设备类型端口，其中，所述设备类型端口允许与处理器连接，
    所述设备类型端口被设置为接收所述处理器发送的所述目标设备类型。
  5. 根据权利要求1所述的设备，其特征在于，所述时钟控制设备，还包括：时钟缓冲器，其中，
    所述时钟控制器与所述时钟缓冲器连接，所述时钟缓冲器还连接在多种时钟类型的时钟发生器中的参考时钟发生器和所述时钟选择器之间；
    所述参考时钟发生器，被设置为生成多个时钟信号；
    所述时钟缓冲器，被设置为缓存多个所述时钟信号；
    所述时钟控制器，被设置为采集多个所述时钟信号的信号参数；根据所述信号参数确定多个所述时钟信号中每个所述时钟信号的信号质量；控制所述时钟缓冲器将所述信号质量最高的参考时钟信号传输至所述时钟选择器。
  6. 根据权利要求5所述的设备，其特征在于，所述时钟控制器上部署了第二控制端口，所述时钟缓冲器上部署了多个参考时钟端口，第三输出端口和第二信号端口，其中，
    所述第二控制端口与所述第二信号端口连接，多个所述参考时钟端口被设置为连接所述参考时钟发生器，所述第三输出端口被设置为连接所述时钟选择器；
    所述时钟控制器，被设置为生成所述参考时钟信号所对应的参考控制信号；通过所述第二控制端口向所述时钟缓冲器发送所述参考控制信号；
    所述时钟缓冲器，被设置为通过所述第二信号端口接收所述参考控制信号；将所述参考控制信号对应的所述参考时钟信号传输至所述第三输出端口。
  7. 根据权利要求5所述的设备，其特征在于，所述时钟控制设备，还包括：信号采集器，其中，
    所述信号采集器连接在所述参考时钟发生器和所述时钟控制器之间；
    所述信号采集器，被设置为对多个所述时钟信号进行采样，得到多个采样信号；将多个所述采样信号传输至所述时钟控制器；
    所述时钟控制器，被设置为计算多个所述采样信号的所述信号参数，其中，每个所述采样信号的所述信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个所述采样信号的所述信 号参数转换为每个所述采样信号的所述信号质量。
  8. 一种交换板，其特征在于，包括：交换芯片和时钟控制设备，其中，
    所述时钟控制设备与所述交换芯片连接，所述时钟控制设备还允许与目标设备和多种时钟类型的时钟发生器连接；
    所述交换芯片在控制属于不同设备类型的所述目标设备时使用的时钟信号的时钟类型不同，多种所述时钟类型与多种设备类型对应；
    所述时钟控制设备，被设置为识别所述目标设备在多种所述设备类型中所属于的目标设备类型；将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，其中，所述目标时钟发生器是所述目标设备类型所对应的目标时钟类型的时钟发生器。
  9. 根据权利要求8所述的交换板，其特征在于，所述时钟控制设备，包括：时钟控制器和时钟选择器，其中，
    所述时钟控制器与所述时钟选择器连接，所述时钟选择器允许连接多种所述时钟类型的时钟发生器，所述交换芯片和所述目标设备；
    所述时钟控制器，被设置为生成所述目标设备类型所对应的目标控制信号；向所述时钟选择器发送所述目标控制信号；
    所述时钟选择器，被设置为接收所述目标控制信号；将所述目标控制信号对应的所述目标时钟信号传输至所述交换芯片和所述目标设备。
  10. 根据权利要求9所述的交换板，其特征在于，多种所述时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，其中，
    所述时钟选择器分别与所述第一时钟发生器和所述第二时钟发生器连接，所述第一时钟发生器被设置为传输同源时钟信号，所述第二时钟发生器被设置为传输非同源时钟信号；
    所述时钟控制器，被设置为在所述目标设备类型为第一类型的情况下，生成第一控制信号，其中，所述第一类型为采用高速串行计算机扩展总线标准的设备类型；在所述目标设备类型为第二类型的情况下，生成第二控制信号，其中，所述第二类型为采用计算快速连接协议的设备类型；向所述时钟选择器发送所述第一控制信号，或者，所述第二控制信号；
    所述时钟选择器，被设置为在接收到所述第一控制信号的情况下，将所述同源时钟信号传输至所述交换芯片和所述目标设备；在接收到所述第二控制信号的情况下，将所述非同源时钟信号传输至所述交换芯片和所述目标设备。
  11. 根据权利要求8所述的交换板，其特征在于，多种所述时钟类型的时钟发生器中的参考时钟发生器允许生成多个时钟信号，其中，
    所述时钟控制设备，被设置为缓存多个所述时钟信号，并采集多个所述时钟信号的信号参数；根据所述信号参数确定多个所述时钟信号中每个所述时钟信号的信号质量；将所述信号质量最高的参考时钟信号确定为所述参考时钟发生器对应的时钟信号。
  12. 根据权利要求11所述的交换板，其特征在于，所述时钟控制设备，包括：时钟控制器，时钟选择器和时钟缓冲器，其中，
    所述时钟控制器与所述时钟选择器连接，所述时钟选择器允许连接多种所述时钟类型的时钟发生器，所述交换芯片和所述目标设备，所述时钟缓冲器连接在所述参考时钟发生器和所述时钟选择器之间；
    所述时钟控制器，被设置为生成所述参考时钟信号所对应的参考控制信号；向所述时钟缓冲器发送所述参考控制信号；生成所述目标设备类型所对应的目标控制信号；向所述时钟选择器发送所述目标控制信号；
    所述时钟缓冲器，被设置为接收所述参考控制信号；将所述参考控制信号对应的所述参考时钟信号传输至所述时钟选择器；
    所述时钟选择器，被设置为接收所述目标控制信号；将所述目标控制信号对应的所述目标时钟信号传输至所述交换芯片和所述目标设备。
  13. 根据权利要求11所述的交换板，其特征在于，所述时钟控制设备，还被设置为：对多个所述时钟信号进行采样，得到多个采样信号；计算多个所述采样信号的所述信号参数，其中，每个所述采样信号的所述信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数；将每个所述采样信号的所述信号参数转换为每个所述采样信号的所述信号质量。
  14. 根据权利要求8所述的交换板，其特征在于，所述时钟控制设备允许与处理器连接，其中，
    所述时钟控制设备被设置为接收所述处理器发送的所述目标设备类型。
  15. 根据权利要求8所述的交换板，其特征在于，所述交换板还包括：上行连接器，下行连接器和第三时钟发生器，其中，
    所述第三时钟发生器与所述时钟控制设备连接，所述时钟控制设备通过所述上行连接器与处理器的第四时钟发生器连接，多种所述时钟类型的时钟发生器包括所述第三时钟发生器和所述第四时钟发生器；
    所述时钟控制设备通过所述下行连接器与所述目标设备连接。
  16. 一种交换芯片的时钟控制系统，其特征在于，包括：交换板和设备板，其中，
    所述交换板上部署了交换芯片和时钟控制设备，所述设备板上部署了设备接口；
    所述设备接口，被设置为连接目标设备，其中，所述交换芯片在控制属于不同设备类型的所述目标设备时使用的时钟信号的时钟类型不同，多种所述时钟类型与多种设备类型对应；
    所述时钟控制设备，被设置为识别所述目标设备在多种所述设备类型中所属于的目标设备类型；将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，其中，所述目标时钟发生器是所述目标设备类型所对应的目标时钟类型的时钟发生器。
  17. 根据权利要求16所述的系统，其特征在于，所述系统还包括：主板，其中，
    所述交换板上还部署了第三时钟发生器，所述主板上部署了处理器的第四时钟发生器，所述时钟控制设备，包括：时钟控制器和时钟选择器；
    所述时钟控制器与所述时钟选择器连接，所述时钟选择器与所述第三时钟发生器，所述第四时钟发生器，所述交换芯片和所述目标设备，所述第三时钟发生器被设置为传输非同源时钟信号，所述第四时钟发生器被设置为传输同源时钟信号；
    所述时钟控制器，被设置为在所述目标设备类型为第一类型的情况下，生成第一控制信号，其中，所述第一类型为采用高速串行计算机扩展总线标准的设备类型；在所述目标设备类型为第二类型的情况下，生成第二控制信号，其中，所述第二类型为采用计算快速连接协议的设备类型；向所述时钟选择器发送所述第一控制信号，或者，所述第二控制信号；
    所述时钟选择器，被设置为在接收到所述第一控制信号的情况下，将所述同源时钟信号传输至所述交换芯片和所述目标设备；在接收到所述第二控制信号的情况下，将所述非同源时钟信号传输至所述交换芯片和所述目标设备。
  18. 根据权利要求17所述的系统，其特征在于，所述第四时钟发生器允许生成多个时钟信号，所述时钟控制设备，还包括：时钟缓冲器，其中，
    所述时钟缓冲器连接在所述第四时钟发生器和所述时钟选择器之间；
    所述时钟控制器，被设置为采集多个所述时钟信号的信号参数；根据所述信号参数确定多个所述时钟信号中每个所述时钟信号的信号质量；将所述信号质量最高的参考时钟信号确定为所述第四时钟发生器对应的时钟信号；生成所述参考时钟信号所对应的参考控制信号；向所述时钟缓冲器发送所述参考控制信号；
    所述时钟缓冲器，被设置为缓存多个所述时钟信号；接收所述参考控制信号；将所述参考控制信号对应的所述参考时钟信号传输至所述时钟选择器。
  19. 根据权利要求17所述的系统，其特征在于，所述主板上还部署了处理器，所述时钟控制设备与所述处理器连接，其中，
    所述处理器通过所述交换板和所述设备板与所述目标设备连接；
    所述处理器，被设置为在对所述目标设备的训练过程中输出所述目标设备的所述目标设备类型；将所述目标设备类型发送至所述时钟控制设备；
    所述时钟控制设备，被设置为接收所述处理器发送的所述目标设备类型。
  20. 一种交换芯片的时钟控制方法，其特征在于，应用于时钟控制设备，所述方法包括：
    接收多种时钟类型的时钟发生器传输的时钟信号，其中，所述时钟控制设备与交换芯片连接，所述交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种所述时钟类型与多种设备类型对应；
    识别所述目标设备在多种所述设备类型中所属于的目标设备类型；
    将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，其中，所述目标时钟发生器是所述目标设备类型所对应的目标时钟类型的时钟发生器。
  21. 根据权利要求20所述的方法，其特征在于，所述将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，包括：
    生成所述目标设备类型所对应的目标控制信号；
    将所述目标控制信号对应的所述目标时钟信号传输至所述交换芯片和所述目标设备。
  22. 根据权利要求21所述的方法，其特征在于，多种所述时钟类型的时钟发生器，包括：同源类型的第一时钟发生器和非同源类型的第二时钟发生器，所述第一时钟发生器被设置为传输同源时钟信号，所述第二时钟发生器被设置为传输非同源时钟信号；
    所述生成所述目标设备类型所对应的目标控制信号，包括：在所述目标设备类型为第一类型的情况下，生成第一控制信号，其中，所述第一类型为采用高速串行计算机扩展总线标准的设备类型；在所述目标设备类型为第二类型的情况下，生成第二控制信号，其中，所述第二类型为采用计算快速连接协议的设备类型；
    所述将所述目标控制信号对应的所述目标时钟信号传输至所述交换芯片和所述目标设备，包括：在接收到所述第一控制信号的情况下，将所述同源时钟信号传输至所述交换芯片和所述目标设备；在接收到所述第二控制信号的情况下，将所述非同源时钟信号传输至所述交换芯片和所述目标设备。
  23. 根据权利要求21所述的方法，其特征在于，多种所述时钟类型的时钟发生器中的参考时钟发生器 被设置为生成多个时钟信号，其中，所述接收多种时钟类型的时钟发生器传输的时钟信号，包括：
    缓存多个所述时钟信号；
    采集多个所述时钟信号的信号参数；
    根据所述信号参数确定多个所述时钟信号中每个所述时钟信号的信号质量；
    将所述信号质量最高的参考时钟信号确定为所述参考时钟发生器传输的时钟信号。
  24. 根据权利要求23所述的方法，其特征在于，所述采集多个所述时钟信号的信号参数，包括：
    对多个所述时钟信号进行采样，得到多个采样信号；
    计算多个所述采样信号的所述信号参数，其中，每个所述采样信号的所述信号参数包括以下至少之一：振幅参数、频率参数、斜率参数、抖动参数。
  25. 根据权利要求20所述的方法，其特征在于，所述识别所述目标设备在多种所述设备类型中所属于的目标设备类型，包括：
    接收所述时钟控制设备所连接的处理器发送的所述目标设备类型。
  26. 一种交换芯片的时钟控制装置，其特征在于，包括：
    接收模块，被设置为接收多种时钟类型的时钟发生器传输的时钟信号，其中，所述时钟控制设备与交换芯片连接，所述交换芯片在控制属于不同设备类型的目标设备时使用的时钟信号的时钟类型不同，多种所述时钟类型与多种设备类型对应；
    识别模块，被设置为识别所述目标设备在多种所述设备类型中所属于的目标设备类型；
    传输模块，被设置为将多种所述时钟类型的时钟发生器中的目标时钟发生器所传输的目标时钟信号传输至所述交换芯片和所述目标设备，其中，所述目标时钟发生器是所述目标设备类型所对应的目标时钟类型的时钟发生器。
  27. 一种非易失性可读存储介质，其特征在于，所述非易失性可读存储介质中存储有计算机程序，其中，所述计算机程序被处理器执行时实现所述权利要求20至25任一项中所述的方法的步骤。
  28. 一种电子设备，包括存储器、处理器以及存储在所述存储器上并可在所述处理器上运行的计算机程序，其特征在于，所述处理器执行所述计算机程序时实现所述权利要求20至25任一项中所述的方法的步骤。
PCT/CN2023/141950 2023-06-21 2023-12-26 交换芯片的时钟控制方法，系统和设备，以及交换板 Ceased WO2024259940A1 (zh)

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