WO2024259834A1 - Cmos半导体存储阵列及存内计算电路 - Google Patents

Cmos半导体存储阵列及存内计算电路 Download PDF

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WO2024259834A1
WO2024259834A1 PCT/CN2023/125389 CN2023125389W WO2024259834A1 WO 2024259834 A1 WO2024259834 A1 WO 2024259834A1 CN 2023125389 W CN2023125389 W CN 2023125389W WO 2024259834 A1 WO2024259834 A1 WO 2024259834A1
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field effect
effect transistor
channel field
mode
memory
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French (fr)
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王宗巍
蔡一茂
杨宇航
黄如
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors

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  • the present disclosure relates to the technical field of resistive random access memory (RRAM) and CMOS hybrid integrated circuits, and in particular to a RRAM storage unit using CMOS and a storage array circuit thereof.
  • RRAM resistive random access memory
  • Non-volatile Memory stores weights in non-volatile memory units and performs simulated vector matrix multiplication calculations in the array, avoiding the frequent transfer of data between memory and computing units, and is considered to be a promising way to solve the von Neumann bottleneck.
  • non-volatile memory devices such as RRAM, PCRAM, MRAM, FeRAM, FeFET, etc. store weights on the conductivity of the device after the weights are written.
  • the devices are organized in the form of an array, and the input voltage from one end is used as the input of the vector-matrix multiplication.
  • the array is calculated by Ohm's law and Kirchhoff's law, and the current obtained at the other end of the array is the summation result of the vector-matrix multiplication, and the summation result is usually read out using an analog-to-digital converter (ADC).
  • ADC analog-to-digital converter
  • two-terminal non-volatile memories have attracted extensive attention and research due to their higher theoretical density and reduced process cost brought by simple structure.
  • two-terminal memories need to form a storage array to achieve high-density structure and high-speed reading and writing.
  • the existing methods mainly form a 1-transistor-1 memory (1T1R) array.
  • the transistors in the mainstream method are connected to the memory array.
  • N-type is often used.
  • the maximum gate voltage that can be applied by the transistor is limited.
  • the N-type transistor has a source resistor
  • the non-zero source voltage will further reduce the gate-source voltage of the transistor. Therefore, there is a problem of insufficient driving current during the operation of the two-terminal memory at advanced nodes, which limits the further reduction of the device size and the improvement of the storage array density.
  • the purpose of the present invention is to provide a CMOS semiconductor memory array and an in-memory computing circuit to solve the problems of voltage limitation in existing memory circuits, resulting in insufficient driving current, limiting the miniaturization of devices and increasing the density of memory arrays, and so on.
  • the CMOS semiconductor storage array includes storage units distributed in a matrix array, wherein the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; and one end of the memory is connected to the drain of the P-channel field effect transistor.
  • an optional technical solution is that the gate of the N-channel field effect transistor and the gate of the P-channel field effect transistor are respectively connected to different word lines; the source of the P-channel field effect transistor is connected to the source line, and the other end of the memory is connected to the bit line.
  • the source line is connected to the positive voltage VDD
  • the saturation current of the P-channel field effect transistor is:
  • Vsg Vs ⁇ VDD
  • V tp represent intrinsic parameters of the P-channel field effect transistor
  • V sg the source-gate voltage of the P-channel field effect transistor
  • V s the source voltage of the P-channel field effect transistor
  • an optional technical solution is to include M ⁇ N storage cells, where M represents the number of rows, N represents the number of columns, and the word lines include a word line N connected to the gate of an N-channel field effect transistor, and a word line P connected to the gate of a P-channel field effect transistor; wherein the word lines N and P of the storage cells in the same column are shared, and the bit lines and source lines of the storage cells in the same row are shared.
  • the optional technical solution includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its original data; in the write 1 mode, each storage unit does not work and saves its original data; In the write mode and write 0 mode, the specified storage cell is in the state representing 1 and 0 respectively, and the voltage of the specified storage cell is less than the preset voltage VDD; in the read mode, the source line of the storage cell is connected to the read voltage, so that the read current passes through the storage cell to the bit line, and the corresponding state of the storage cell is read from the bit line.
  • an optional technical solution is that in the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to a preset voltage VDD; the P-channel field effect transistor and the N-channel field effect transistor are both in the off state.
  • an optional technical solution is that, in write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines remain in the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1.
  • an optional technical solution is that, in write 0 mode, word line N is connected to a preset voltage VDD, word line P and source line are connected to GND; after the target memory cell is selected, the bit line of the target memory cell is connected to a preset write 0 voltage, and the remaining lines maintain the state in the save mode, the current of the target memory cell flows from the bit line through the memory to the source line, and the target memory cell is written to state 0.
  • an optional technical solution is that in the read mode, the word line N is connected to the preset voltage VDD; after the target memory cell is selected, the source line is connected to the read voltage, and the remaining lines maintain the state in the save mode.
  • the read current flows from the source line through the memory to the bit line, and the corresponding state of the memory cell is read from the bit line.
  • the present disclosure also provides an in-memory computing circuit, including the above-mentioned CMOS semiconductor storage array.
  • the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional storage structure, and being conducive to improving the density of the storage array and realizing the miniaturization of the device.
  • FIG1 is a schematic diagram of the structure of a storage unit of a CMOS semiconductor storage array according to an embodiment of the present disclosure
  • FIG2 is a schematic structural diagram of a matrix array of a CMOS semiconductor storage array according to an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of operating voltages of a CMOS semiconductor memory array according to an embodiment of the present disclosure.
  • the maximum gate voltage that can be applied to the transistors in the current N-type transistor storage array is limited, and when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor, so there is a problem of insufficient driving current during the operation of the two-terminal memory at the advanced node.
  • the present invention provides a CMOS semiconductor storage array and an in-memory computing circuit, wherein the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and a PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional storage structure, and is conducive to further improving the density of the storage array and realizing the miniaturization of the device.
  • the line connecting the gate of the transistor is called the word line (Word Line, WL)
  • the line connecting the source of the transistor is called the source line (Source Line, SL)
  • the line connecting one end of the device is called the bit line (Bit Line, BL).
  • FIG. 1 and 2 respectively show a schematic structure of a memory cell and a matrix array structure of a CMOS semiconductor memory array according to an embodiment of the present disclosure.
  • the CMOS semiconductor memory array of the embodiment of the present disclosure includes a plurality of memory cells distributed in a matrix array, each memory cell further including a memory and a P-channel field effect transistor (PMOS for short) and an N-channel field effect transistor (NMOS for short) connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; and one end of the memory is connected to the drain of the P-channel field effect transistor.
  • PMOS P-channel field effect transistor
  • NMOS N-channel field effect transistor
  • the gate of the N-channel field effect transistor and the gate of the P-channel field effect transistor are respectively connected to different word lines, and the word lines include a word line N connected to the gate of the N-channel field effect transistor and a word line P connected to the gate of the P-channel field effect transistor; the source of the P-channel field effect transistor is connected to the source line, and the other end of the memory is connected to the bit line.
  • a CMOS transmission gate is connected in series with an RRAM to form a memory cell with a gating function.
  • the conduction of the transistor can be controlled by the signals on WL0 and WL1, and the corresponding operating voltages can be applied to SL and BL to operate or read the memory in the cell.
  • the PMOS as a gating device is connected to the positive voltage VDD at the source line, and the saturation current of the P-channel field effect transistor is:
  • Vsg Vs ⁇ VDD
  • V tp represent intrinsic parameters of the P-channel field effect transistor
  • V sg the source-gate voltage of the P-channel field effect transistor
  • V s the source voltage of the P-channel field effect transistor
  • the gate-source voltage drop of the PMOS can reach the voltage VDD, while for the NMOS, the maximum is only VDD-I*R, where the typical value of I*R is 0.7V.
  • the saturation current of the PMOS device will be significantly greater than that of the NMOS device of the same size.
  • the gate width W required by the PMOS is smaller, which is more conducive to improving the density of the storage array.
  • FIG2 shows a typical memory array structure formed by the memory cells of FIG1 , wherein the same row shares SL and BL, and the same column shares WLP (word line P) and WLN (word line N).
  • the figure shows the specific connection relationship between two rows and two columns; wherein, in the application process, the specific memory array structure may also include M ⁇ N memory cells, wherein M represents the number of rows, and N represents the number of columns, wherein the memory cells in the same row share word lines SL0 and SL1; and the memory cells in the same column share word lines P and N.
  • the storage array has four working modes, namely, a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its own original data; in the write 1 mode and the write 0 mode, the designated storage unit is in a state representing 1 and 0, respectively, and the voltage of the designated storage unit is less than a preset voltage VDD; in the read mode, the source line of the storage unit is connected to the read voltage, so that the read current passes through the storage unit to the bit line, and the corresponding state of the storage unit is read from the bit line.
  • all word lines N, bit lines and source lines are connected to GND, and word line P is connected to a preset voltage VDD; P-channel field effect transistors and N-channel field effect transistors are both in the off state; in the write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines maintain the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1; in the write 0 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines maintain the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the
  • FIG. 3 shows a schematic structure of an operating voltage of a memory array according to an embodiment of the present disclosure.
  • FIG. 1 to FIG. 3 there are four working modes of the storage array, namely, the save mode, the write 1 mode, the write 0 mode and the read mode; assuming that the memory writes 1 when a positive voltage is applied to SL, and the memory writes 0 when a positive voltage is applied to BL, VDD and GND are used below to represent the high level and ground in the circuit respectively.
  • the target device of the current operation is the storage cell (1, 1) in the lower right corner of FIG. 2, the operation flow shown in FIG. 3 is performed. First, the array is in an inoperative state, and all cells save data. Then, the operations of write 1, read, and write 0 are successively performed on the specified cells.
  • WLN1 is connected to VDD
  • WLP1 is connected to GND
  • SL1 is connected to the write 1 voltage
  • the connection method of the other lines is the same as the non-working state.
  • the transistor corresponding to the (1, 1) unit is turned on, and current will flow from SL1 through the memory to BL1, and the device is written to 1.
  • WLN1 is connected to VDD
  • WLP1 is connected to GND
  • SL1 is connected to the read voltage
  • the connection method of the other lines is the same as the non-working state.
  • the transistor corresponding to the (1, 1) unit is turned on, and the read current flows from SL1 through the memory to BL1.
  • the current corresponding to the device can be read from BL1.
  • WLN1 is connected to VDD
  • WLP1 is connected to GND
  • BL1 is connected to the write 0 voltage
  • the connection method of the other lines is consistent with the non-working state.
  • the transistor corresponding to the (1, 1) unit is turned on, and current will flow from BL1 through the memory to SL, and the device is written to 0.
  • the present disclosure also provides an in-memory computing circuit, including the CMOS semiconductor storage array as described above.
  • an in-memory computing circuit including the CMOS semiconductor storage array as described above.
  • the memory unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and the PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional memory structure, and facilitating further improving the density of the memory array and realizing the miniaturization of the device.

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Abstract

本公开提供一种CMOS半导体存储阵列，包括呈矩阵阵列分布的存储单元，存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接；存储器的一端与P沟道场效应晶体管的漏极连接。利用上述公开能够提高存储阵列的密度，降低对场效应晶体管的驱动能力的要求。

Description

CMOS半导体存储阵列及存内计算电路
本申请要求申请号为202310735553.0，申请日为2023年06月20日，申请创造名称为“CMOS半导体存储阵列及存内计算电路”的专利申请的优先权。
技术领域
本公开涉及阻变存储器(RRAM)和CMOS混合集成电路技术领域，具体涉及一种使用CMOS的RRAM存储单元及其存储阵列电路。
背景技术
随着人工智能与深度学习技术的不断发展，人工神经网络在自然语言处理、图像识别、自动驾驶、图神经网络等领域得到了广泛的应用。然而，逐渐增大的网络规模导致数据在内存与传统计算设备如CPU与GPU间的搬运消耗了大量的能量，这被称为冯诺依曼瓶颈。在人工神经网络算法中占据最主要部分的计算为向量矩阵乘法计算(Vector Matrix Multiplication)。基于非挥发性存储器(Non-volatile Memory，或非易失存储器)的存内计算(Compute-In-Memory)，把权重存储在非挥发性存储器单元中，并在阵列中进行模拟向量矩阵乘法计算，避免了数据在内存与计算单元间的频繁搬运，被认为是一种有希望解决冯诺依曼瓶颈的途径。
目前，非挥发性存储器器件如RRAM、PCRAM、MRAM、FeRAM、FeFET等在权值写入后，把权值存储在器件的电导值上。器件组织成阵列的形式，从一端输入电压作为向量矩阵乘法的输入，阵列中通过欧姆定律与基尔霍夫定律计算，在阵列的另一端得到的电流为向量矩阵乘法的求和结果，且求和结果通常使用模数转换器(ADC)读出。
在上述多种新型非易失存储器中，二端非易失存储器因为其更高的理论密度与简单结构带来的工艺成本降低受到广泛地关注和研究。在实际应用中，二端存储器需要形成存储阵列来实现高密度结构与高速读写。目前已有的方法主要是通过组成1晶体管-1存储器(1T1R)阵列，主流方法中的晶体管通 常采用N型。但是在实际使用中，一方面由于先进节点下电源Vdd较低，晶体管能够施加的最大栅压有限，另一方面N型晶体管在带有源极电阻时，非零的源端电压将进一步降低晶体管的栅源电压，因此在先进节点下的二端存储器操作过程中存在驱动电流不足的问题，从而限制了器件尺寸的进一步缩小，限制存储阵列密度的提升。
发明内容
鉴于上述问题，本公开的目的是提供一种CMOS半导体存储阵列及存内计算电路，以解决现有存储电路存在的电压受限，导致驱动电流不足，限制器件的小型化发展及存储阵列密度提升等问题。
本公开提供的CMOS半导体存储阵列，包括呈矩阵阵列分布的存储单元，存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接；存储器的一端与P沟道场效应晶体管的漏极连接。
此外，可选的技术方案是，N沟道场效应晶体管的栅极与P沟道场效应晶体管的栅极分别与不同的字线连接；P沟道场效应晶体管的源极与源线连接，存储器的另一端与位线连接。
此外，可选的技术方案是，源线与正电压VDD连接，P沟道场效应晶体管的饱和电流为：
其中，Vsg＝Vs<VDD，和Vtp表示P沟道场效应晶体管的固有参数，Vsg表示P沟道场效应晶体管的源栅电压，Vs表示P沟道场效应晶体管的源极电压。
此外，可选的技术方案是，包括M×N个存储单元，其中M表示行数，N表示列数，字线包括与N沟道场效应晶体管的栅极连接的字线N，以及与P沟道场效应晶体管的栅极连接的字线P；其中，位于同一列中的存储单元的字线N、字线P共用，位于同一行中的存储单元的位线、源线共用。
此外，可选的技术方案是，包括保存模式、写1模式、写0模式和读模式；其中，在保存模式下，各存储单元不工作并保存自身原有数据；在写1 模式和写0模式下，指定的存储单元分别处于表示1和0的状态，且指定的存储单元的电压小于预设电压VDD；在读模式下，存储单元的源线接读电压，使得读电流通过存储单元到达位线，并从位线上读取存储单元的对应状态。
此外，可选的技术方案是，在保存模式下，所有字线N、位线和源线均接GND，字线P接预设电压VDD；P沟道场效应晶体管和N沟道场效应晶体管均处于关断状态。
此外，可选的技术方案是，在写1模式下，字线N接预设电压VDD，字线P接GND；在选通目标存储单元后，目标存储单元的源线接预设写1电压，其余线保持保存模式下的状态，目标存储单元的电流由源线流经存储器至位线，目标存储单元被写至状态1。
此外，可选的技术方案是，在写0模式下，字线N接预设电压VDD，字线P和源线和接GND；在选通目标存储单元后，目标存储单元的位线接预设写0电压，其余线保持保存模式下的状态，目标存储单元的电流由位线流经存储器至源线，目标存储单元被写至状态0。
此外，可选的技术方案是，在读模式下，字线N接预设电压VDD；在选通目标存储单元后，源线接读电压，其余线保持保存模式下的状态，读电流由源线流经过存储器后至位线，并从位线上读取存储单元的对应状态。
另一方面，本公开还提供一种存内计算电路，包括上述CMOS半导体存储阵列。
利用上述CMOS半导体存储阵列及存内计算电路，存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接，引入PMOS形成CMOS传输门结构，从而显著降低操作电压，缓解传统存储结构中驱动能力不足的问题，有利于提高存储阵列密度，实现器件的小型化发展。
为了实现上述以及相关目的，本公开的一个或多个方面包括后面将详细说明的特征。下面的说明以及附图详细说明了本公开的某些示例性方面。然而，这些方面指示的仅仅是可使用本公开的原理的各种方式中的一些方式。此外，本公开旨在包括所有这些方面以及它们的等同物。
附图说明
通过参考以下结合附图的说明，并且随着对本公开的更全面理解，本公开的其它目的及结果将更加明白及易于理解。在附图中：
图1为本公开实施例的CMOS半导体存储阵列的存储单元的结构示意图；
图2为本公开实施例的CMOS半导体存储阵列的矩阵阵列的结构示意图；
图3为本公开实施例的CMOS半导体存储阵列的操作电压示意图。
具体实施方式
在下面的描述中，出于说明的目的，为了提供对一个或多个实施例的全面理解，阐述了许多具体细节。然而，很明显，也可以在没有这些具体细节的情况下实现这些实施例。在其它例子中，为了便于描述一个或多个实施例，公知的结构和设备以方框图的形式示出。
在目前的N型晶体管存储阵列所存在的晶体管能够施加的最大栅压有限，以及N型晶体管在带有源极电阻时，非零的源端电压将进一步降低晶体管的栅源电压，因此在先进节点下的二端存储器操作过程中存在驱动电流不足的问题。为解决上述问题，本公开提供一种CMOS半导体存储阵列及存内计算电路，存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接，引入PMOS形成CMOS传输门结构，从而显著降低操作电压，缓解传统存储结构中驱动能力不足的问题，有利于进一步提高存储阵列密度，实现器件的小型化发展。
在本公开的以下描述中，把连接晶体管栅极的线称为字线(Word Line，WL)，连接晶体管源极的线称为源线(Source Line，SL)，连接器件一端的线称为位线(Bit Line，BL)。
为详细描述本公开内的CMOS半导体存储阵列，以下将结合附图对本公开的具体实施例进行详细描述。
图1和图2分别示出了根据本公开实施例的CMOS半导体存储阵列的存储单元的示意结构以及矩阵阵列结构。
如图1和图2共同所示，本公开实施例的CMOS半导体存储阵列，包括呈矩阵阵列分布的若干个存储单元，每个存储单元进一步包括存储器以及串联连接的一个P沟道场效应晶体管(简称PMOS)和一个N沟道场效应晶体管(简称NMOS)；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接；存储器的一端与P沟道场效应晶体管的漏极连接。
具体地，在图1所述的结构中，N沟道场效应晶体管的栅极与P沟道场效应晶体管的栅极分别与不同的字线连接，字线包括与N沟道场效应晶体管的栅极连接的字线N，以及与P沟道场效应晶体管的栅极连接的字线P；P沟道场效应晶体管的源极与源线连接，存储器的另一端与位线连接。可知，在该存储单元中，一个CMOS传输门串联一个RRAM构成一个带有选通功能的存储单元。通过WL0与WL1上的信号能够控制晶体管的导通，SL与BL上施加对应的操作电压即可操作或读取单元中的存储器。
其中，作为选通器件的PMOS，在源线与正电压VDD连接，P沟道场效应晶体管的饱和电流为：
其中，Vsg＝Vs<VDD，和Vtp表示P沟道场效应晶体管的固有参数，Vsg表示P沟道场效应晶体管的源栅电压，Vs表示P沟道场效应晶体管的源极电压。
可知，在上述PMOS传输正电压时，由于其Vsg不受另一端电压的影响，使得PMOS的栅源电压降能够到达电压VDD，而对于NMOS则最高仅有VDD-I*R，其中I*R典型值为0.7V。在此情况下PMOS器件的饱和电流将显著大于同尺寸的NMOS器件。换句话说，如果要求相同的电流驱动能力，则PMOS需要的栅宽W更小，从而更有利于提升存储阵列的密度。
图2示出了由图1存储单元形成的一种典型的存储阵列结构，其中同行共用SL、BL，同列共用WLP(字线P)、WLN(字线N)。图中示出了其中两行两列的具体连接关系；其中，在应用过程中具体的存储阵列结构，也可包括M×N个存储单元，其中M表示行数，N表示列数，其中，位于同一行中的存储单元的字线SL0共用，SL1共用；位于同一列中的存储单元的字线P共用，字线N共用。
在本公开的一个具体实施方式中，存储阵列存在四种工作模式，分别为保存模式、写1模式、写0模式和读模式；其中，在保存模式下，各存储单元不工作并保存自身原有数据；在写1模式和写0模式下，指定的存储单元分别处于表示1和0的状态，且指定的存储单元的电压小于预设电压VDD；在读模式下，存储单元的源线接读电压，使得读电流通过存储单元到达位线，并从位线上读取存储单元的对应状态。
具体地，在保存模式下，所有字线N、位线和源线均接GND，字线P接预设电压VDD；P沟道场效应晶体管和N沟道场效应晶体管均处于关断状态；在写1模式下，字线N接预设电压VDD，字线P接GND；在选通目标存储单元后，目标存储单元的源线接预设写1电压，其余线保持保存模式下的状态，目标存储单元的电流由源线流经存储器至位线，目标存储单元被写至状态1；在写0模式下，字线N接预设电压VDD，字线P和源线和接GND；在选通目标存储单元后，目标存储单元的位线接预设写0电压，其余线保持保存模式下的状态，目标存储单元的电流由位线流经存储器至源线，目标存储单元被写至状态0；在读模式下，字线N接预设电压VDD；在选通目标存储单元后，源线接读电压，其余线保持保存模式下的状态，读电流由源线流经过存储器后至位线，并从位线上读取存储单元的对应状态。
作为具体示例，图3示出了根据本公开实施例的存储阵列的操作电压示意结构。
结合图1至图3共同所示，存储阵列存在四种工作模式，分别为保存模式、写1模式、写0模式和读模式；假设当SL加正电压时存储器写1，而BL加正电压时存储器写0，以下使用VDD与GND分别代指电路中的高电平与地。具体地，假设当前操作的目标器件为图2中右下角(1，1)存储单元进行如图3所示的操作流程，首先阵列处于不工作的状态，所有单元保存数据，随后对于指定单元相继执行写1，读，写0的操作。
具体地，在非工作状态下，所有WLN、BL、SL均接GND，所有WLP接VDD，此时所有晶体管处于关断状态，阵列不工作；
写1模式：WLN1接VDD，WLP1接GND，SL1接写1电压，其余线的接法与非工作状态一致，此时(1，1)单元对应的晶体管导通，将有电流由SL1流经存储器到BL1，器件被写到1。
读模式：WLN1接VDD，WLP1接GND，SL1接读电压，其余线的接法与非工作状态一致，此时(1，1)单元对应的晶体管导通，读电流由SL1流经存储器到BL1，从BL1上可读到器件对应的电流。
写0模式：WLN1接VDD，WLP1接GND，BL1接写0电压，其余线的接法与非工作状态一致，此时(1，1)单元对应的晶体管导通，将有电流由BL1流经存储器到SL，器件被写到0。
需要说明的是，本公开以上仅解释了阵列中一次操作单个存储单元的方法，每次只选通一行一列，而该技术领域具有通常知识者应了解，该操作方法可以很容易拓展到多行多列的选通上，从而能够并行的对多行多列的单元进行读写操作，从而增加阵列的数据吞吐量。
与上述CMOS半导体存储阵列相对应，本公开还提供一种存内计算电路，包括如上所述的CMOS半导体存储阵列，具体的存内计算电路的实施例，可参考CMOS半导体存储阵列实施例中的描述，此处不再进行一一赘述。
根据上述本公开的CMOS半导体存储阵列及存内计算电路，存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，P沟道场效应晶体管的源极与N沟道场效应晶体管的漏极连接；P沟道场效应晶体管的漏极与N沟道场效应晶体管的源极连接，引入PMOS形成CMOS传输门结构，从而显著降低操作电压，缓解传统存储结构中驱动能力不足的问题，有利于进一步提高存储阵列密度，实现器件的小型化发展。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本公开。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易 见的，本文中所定义的一般原理可以在不脱离本公开的精神或范围的情况下，在其他实施例中实现。因此，本公开将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种CMOS半导体存储阵列，其特征在于，包括呈矩阵阵列分布的存储单元，所述存储单元包括存储器以及串联连接的一个P沟道场效应晶体管和一个N沟道场效应晶体管；其中，
    所述P沟道场效应晶体管的源极与所述N沟道场效应晶体管的漏极连接；
    所述P沟道场效应晶体管的漏极与所述N沟道场效应晶体管的源极连接；
    所述存储器的一端与所述P沟道场效应晶体管的漏极连接。
  2. 如权利要求1所述的CMOS半导体存储阵列，其特征在于，
    所述N沟道场效应晶体管的栅极与所述P沟道场效应晶体管的栅极分别与不同的字线连接；
    所述P沟道场效应晶体管的源极与源线连接，所述存储器的另一端与位线连接。
  3. 如权利要求2所述的CMOS半导体存储阵列，其特征在于，
    所述源线与正电压VDD连接，所述P沟道场效应晶体管的饱和电流为：
    其中，Vsg＝Vs<VDD，和Vtp表示所述P沟道场效应晶体管的固有参数，Vsg表示所述P沟道场效应晶体管的源栅电压，Vs表示所述P沟道场效应晶体管的源极电压。
  4. 如权利要求2所示的CMOS半导体存储阵列，其特征在于，包括M×N个所述存储单元，其中M表示行数，N表示列数，所述字线包括与所述N沟道场效应晶体管的栅极连接的字线N，以及与所述P沟道场效应晶体管的栅极连接的字线P；其中，
    位于同一列中的存储单元的字线N、字线P共用，位于同一行中的存储单元的位线、源线共用。
  5. 如权利要求4所示的CMOS半导体存储阵列，其特征在于，包括保存模式、写1模式、写0模式和读模式；其中，
    在所述保存模式下，各存储单元不工作并保存自身原有数据；
    在所述写1模式和所述写0模式下，指定的存储单元分别处于表示1和0的状态，且所述指定的存储单元的电压小于预设电压VDD；
    在所述读模式下，所述存储单元的源线接读电压，使得读电流通过所述存储单元到达所述位线，并从所述位线上读取所述存储单元的对应状态。
  6. 如权利要求5所述的CMOS半导体存储阵列，其特征在于，
    在所述保存模式下，所有字线N、位线和源线均接GND，所述字线P接预设电压VDD；
    所述P沟道场效应晶体管和所述N沟道场效应晶体管均处于关断状态。
  7. 如权利要求5所述的CMOS半导体存储阵列，其特征在于，
    在所述写1模式下，所述字线N接预设电压VDD，所述字线P接GND；
    在选通目标存储单元后，所述目标存储单元的源线接预设写1电压，其余线保持所述保存模式下的状态，所述目标存储单元的电流由所述源线流经所述存储器至位线，所述目标存储单元被写至状态1。
  8. 如权利要求5所述的CMOS半导体存储阵列，其特征在于，
    在所述写0模式下，所述字线N接预设电压VDD，所述字线P和所述源线和接GND；
    在选通目标存储单元后，所述目标存储单元的位线接预设写0电压，其余线保持所述保存模式下的状态，所述目标存储单元的电流由所述位线流经所述存储器至源线，所述目标存储单元被写至状态0。
  9. 如权利要求5所述的CMOS半导体存储阵列，其特征在于，
    在所述读模式下，所述字线N接预设电压VDD；
    在选通目标存储单元后，所述源线接读电压，其余线保持所述保存模式下的状态，读电流由源线流经过所述存储器后至位线，并从所述位线上读取 所述存储单元的对应状态。
  10. 一种存内计算电路，其特征在于，包括如权利要求1至9任一项所述的CMOS半导体存储阵列。
PCT/CN2023/125389 2023-06-20 2023-10-19 Cmos半导体存储阵列及存内计算电路 Ceased WO2024259834A1 (zh)

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