WO2024255555A1 - 驱动电路、驱动方法、像素电路、显示面板和显示装置 - Google Patents

驱动电路、驱动方法、像素电路、显示面板和显示装置 Download PDF

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Publication number
WO2024255555A1
WO2024255555A1 PCT/CN2024/094815 CN2024094815W WO2024255555A1 WO 2024255555 A1 WO2024255555 A1 WO 2024255555A1 CN 2024094815 W CN2024094815 W CN 2024094815W WO 2024255555 A1 WO2024255555 A1 WO 2024255555A1
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WIPO (PCT)
Prior art keywords
control
electrically connected
circuit
node
transistor
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PCT/CN2024/094815
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English (en)
French (fr)
Inventor
于子阳
邱海军
胡明
蒋志亮
燕青青
赵攀
何庆
曹丹
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication of WO2024255555A1 publication Critical patent/WO2024255555A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a pixel circuit, a display panel and a display device.
  • OLED organic light-emitting diode
  • the LTPO low-temperature polycrystalline oxide
  • IGZO indium gallium zinc oxide
  • the existing OLED display still needs to initialize and write all pixel voltages within one frame.
  • most of the pixel voltages of the entire screen do not need to be updated, that is, the original display brightness can be maintained by the low-leakage LTPO TFT (thin film transistor). The repeated refresh of these pixels causes a waste of data line power consumption.
  • the embodiment of the present disclosure provides a driving circuit, including a first switch circuit and a scan signal generating circuit;
  • the first switch circuit is electrically connected to the first selection control line, the data output terminal of the source driver and the scan signal generation circuit, and is used to control the data signal provided by the data output terminal to be written into the scan signal generation circuit under the control of the first selection control signal provided by the first selection control line;
  • the scanning signal generating circuit is used to generate a scanning signal according to the data signal, and output the scanning signal through a scanning signal output terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second switch circuit
  • the second switch circuit is electrically connected to a second gate control line, the data output terminal and a data line included in the display panel, respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of a second gate control signal provided by the second gate control line;
  • the first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.
  • the first switch circuit includes a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;
  • the gate of the first transistor is electrically connected to the first selection control line, and the first electrode of the first transistor is electrically connected to the The data output terminal is electrically connected, and the second electrode of the first transistor is electrically connected to the control node;
  • a first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to a DC voltage end.
  • the second switch circuit includes a second transistor
  • a gate of the second transistor is electrically connected to the second selection control line, a first electrode of the second transistor is electrically connected to the data output terminal, and a second electrode of the second transistor is electrically connected to the data line.
  • the scan signal generating circuit includes an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;
  • the output control circuit is electrically connected to the control node, the first voltage terminal, the second voltage terminal, the output control terminal and the scan output terminal respectively, and is used to control the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and control the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal;
  • the output circuit is electrically connected to the control end, the scan output end, the output control end, the first voltage end and the second voltage end, respectively, and is used to control the connection or disconnection between the scan output end and the first voltage end under the control of the control signal provided by the control end, and to control the connection or disconnection between the scan output end and the second voltage end under the control of the potential of the output control end.
  • the scan output terminal is the scan signal output terminal; or,
  • the scanning signal generating circuit also includes an inverting circuit; the input end of the inverting circuit is electrically connected to the scanning output end, and the output end of the inverting circuit is electrically connected to the scanning signal output end.
  • the inverting circuit is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit.
  • the output control circuit includes a third transistor and a fourth transistor;
  • the gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output control terminal;
  • the gate of the fourth transistor is electrically connected to the scan output terminal, the first electrode of the fourth transistor is electrically connected to the output control terminal, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal;
  • the output circuit includes a fifth transistor, a sixth transistor and a second capacitor;
  • the gate of the fifth transistor is electrically connected to the control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the scan output terminal;
  • the gate of the sixth transistor is electrically connected to the output control terminal, the first electrode of the sixth transistor is electrically connected to the scan output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;
  • the first end of the second capacitor is electrically connected to the control end, and the second end of the second capacitor is electrically connected to the second voltage end.
  • the embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, and is characterized in that the driving method comprises: during at least part of a blank period between two display frames,
  • the first switch circuit controls, under the control of the first selection control signal, to write the data signal provided by the data output terminal of the source driver into the scanning signal generating circuit;
  • the scanning signal generating circuit generates a scanning signal according to the data signal, and outputs the scanning signal to a corresponding column scanning line of the display panel through a scanning signal output terminal.
  • the driving circuit further includes a second switch circuit; and the driving method further includes:
  • the second switch circuit controls the data output terminal of the source driver to be connected to the corresponding column data line of the display panel under the control of the second selection control signal.
  • the embodiment of the present disclosure provides a pixel circuit, including a light-emitting element, a light-emitting driving circuit and a control circuit;
  • the light-emitting driving circuit is electrically connected to the first node and the first electrode of the light-emitting element respectively, and is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node; the second electrode of the light-emitting element is electrically connected to the third voltage terminal;
  • the control circuit is electrically connected to the first gate line, the scan line, the first node and the first pole of the light-emitting element, respectively, and is used to control the connection or disconnection between the first node and the first pole of the light-emitting element under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.
  • control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line;
  • the second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.
  • control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line;
  • the second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to increase the first initial voltage terminal to a level under the control of a first initial control signal provided by the first initial control terminal.
  • the first initial voltage supplied is written into the second node.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;
  • the first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;
  • the second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal;
  • the energy storage circuit is electrically connected to the first node and is used for storing electric energy.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third initialization circuit
  • the third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.
  • the first control circuit includes a first control transistor
  • the second control circuit includes a second control transistor
  • the gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;
  • a gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.
  • the first control circuit includes a first control transistor
  • the second control circuit includes a second control transistor
  • the gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;
  • a gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.
  • the first initialization circuit includes a first initialization transistor
  • a gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.
  • the second initialization circuit includes a second initialization transistor
  • a gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.
  • the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;
  • the gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;
  • the gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node;
  • the gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.
  • the third initialization circuit includes a third initialization transistor
  • the gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.
  • the embodiment of the present disclosure provides a pixel driving method, which is applied to the above-mentioned pixel circuit.
  • the pixel driving method includes:
  • the light-emitting driving circuit generates a driving current for driving the light-emitting element under the control of the potential of the first node
  • the control circuit controls the connection or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal and the scanning signal.
  • the pixel circuit includes a first initialization circuit, a first end of the light-emitting driving circuit is electrically connected to the second node, and a second end of the light-emitting driving circuit is electrically connected to a third node and a first electrode of the light-emitting element, respectively;
  • a display period includes a first initialization time period and a second initialization time period which are set successively; and the pixel driving method includes:
  • the control circuit controls the first node to be connected to the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; the light emitting drive circuit controls the second node to be connected to the third node under the control of the potential of the first node;
  • the control circuit controls the first node and the third node to be disconnected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node.
  • the embodiment of the present disclosure provides a display panel, including a source driver and the above-mentioned driving circuit;
  • the source driver includes a data output terminal.
  • the display panel described in the embodiment of the present disclosure includes a plurality of columns of scan lines
  • a scan signal output terminal in a scan signal generating circuit in the driving circuit is electrically connected to the scan line.
  • the display panel includes a plurality of columns of data lines
  • the data output terminal is directly electrically connected to the data line; or the driving circuit includes a second switch circuit, and the second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.
  • the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,
  • the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel.
  • the first side and the second side are opposite sides.
  • the display panel described in at least one embodiment of the present disclosure further includes the above-mentioned pixel circuit.
  • An embodiment of the present disclosure further provides a display device, comprising the above-mentioned display panel.
  • FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG2 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG3 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG4 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG6B is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG7 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG8 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG11 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG12 is a timing diagram of the operation of at least one embodiment of the driving circuit shown in FIG11;
  • FIG13 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG14 is a simulation operation timing diagram of at least one embodiment of the driving circuit shown in FIG13;
  • FIG15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG. 21A is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 20 ;
  • FIG. 21B is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 20 ;
  • FIG22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG23 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure.
  • FIG25 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG26 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • FIG. 27 is a structural diagram of a display panel according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit described in the embodiment of the present disclosure includes a first switch circuit and a scan signal generating circuit
  • the first switch circuit is electrically connected to the first selection control line, the data output terminal of the source driver and the scan signal generation circuit, and is used to control the data signal provided by the data output terminal to be written into the scan signal generation circuit under the control of the first selection control signal provided by the first selection control line;
  • the scanning signal generating circuit is used to generate a scanning signal according to the data signal, and output the scanning signal through a scanning signal output terminal.
  • the driving circuit may include a first switching circuit and a scan signal generating circuit.
  • the first switching circuit under the control of a first selection control signal, controls the writing of a data signal provided by a data output terminal into the scan signal generating circuit;
  • the scan signal generating circuit generates a scan signal according to the data signal, and provides the scan signal to a column of scan lines included in the display panel, thereby controlling the transistor controlled by the column of scan lines to be turned on or off during the next frame of display time according to the scan signal.
  • the transistor controlled by the column scan line when the transistor controlled by the column scan line is turned off during the next frame display time, the pixel circuit where the transistor is located does not perform data voltage writing, and the original display brightness can be maintained through the low leakage transistor, thereby avoiding the waste of part of the power consumption caused by repeated rewriting of the pixel circuit;
  • the pixel circuit where the transistor is located When the transistor controlled by the column scan line is turned on during the next frame display time, the pixel circuit where the transistor is located writes the data voltage and refreshes the picture normally.
  • the relevant OLED (organic light-emitting diode) display needs to initialize and write data voltage to all pixel circuits within one frame display time.
  • the data voltage of most pixel circuits on the entire screen does not need to be updated, and can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFT (thin-film transistor). Repeated refresh of these pixel circuits results in a waste of data line power consumption.
  • LTPO low-temperature polycrystalline oxide
  • TFT thin-film transistor
  • the embodiment of the present disclosure designs a driving circuit that can control the scanning signal on a column of scanning lines during at least part of the blank time period between two frames of display time, so as to control the transistor controlled by the scanning line to be turned on or off during the next frame of display time according to the scanning signal, so as to control whether to refresh the data voltage of the corresponding pixel circuit, thereby realizing the update of the partial screen picture, while the remaining pictures do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or achieving ultra-low power consumption by partially updating the display picture.
  • the driving circuit includes a first switch circuit 11 and a scan signal generating circuit SD;
  • the first switch circuit 11 is electrically connected to the first selection control line SW1, the data output terminal S0 of the source driver and the scan signal generating circuit SD, and is used to control the data signal provided by the data output terminal S0 to be written into the scan signal generating circuit SD under the control of the first selection control signal provided by the first selection control line SW1;
  • the scan signal generating circuit SD is used to generate a scan signal according to the data signal, and output the scan signal through the scan signal output terminal CG.
  • the first switch circuit 11 may be electrically connected to a data output terminal of the source driver.
  • the first switch circuit includes a first transistor and a first capacitor; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;
  • the gate of the first transistor is electrically connected to the first selection control line, the first electrode of the first transistor is electrically connected to the data output terminal, and the second electrode of the first transistor is electrically connected to the control node;
  • a first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to a DC voltage end.
  • the data output terminal may be directly electrically connected to a data line, and the scan signal output terminal may be electrically connected to a scan line, but the present invention is not limited thereto.
  • the pixel circuit labeled P11 is the first row and first column
  • the pixel circuit labeled P21 is the second row and first column
  • the pixel circuit labeled P31 is the third row and first column
  • the pixel circuit labeled P41 is the fourth row and first column
  • the line labeled DL is a data line
  • the line labeled CG is a scan line
  • the line labeled NG1 is the first gate line of the first row
  • the line labeled NG2 is the first gate line of the first row
  • the line labeled NG3 is the first gate line of the third row
  • the line labeled NG4 is the first gate line of the fourth row;
  • the driving circuit includes a first switch circuit and a scan signal generating circuit SD;
  • the first switch circuit includes a first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor T1 is connected to the data line DL, and the second electrode of the first transistor is electrically connected to the scanning signal generating circuit SD;
  • DL is electrically connected to the data output terminal S0 of the source driver
  • the scan signal generating circuit SD is used for generating a scan signal according to the data signal provided by the data output terminal S0, and providing the scan signal to the scan line CGL.
  • T1 is a p-type transistor, and between two display frames, SW1 provides a low voltage signal to turn on T1 .
  • T1 is an n-type transistor, and between two display frames, SW1 provides a high voltage signal to turn on T1.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second switch circuit
  • the second switch circuit is electrically connected to a second gate control line, the data output terminal and a data line included in the display panel, respectively, and is used to control the connection or disconnection between the data output terminal and the data line under the control of a second gate control signal provided by the second gate control line;
  • the first gate control line and the second gate control line are the same gate control line, or the first gate control line and the second gate control line are different.
  • the driving circuit may further include a second switch circuit, and the second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.
  • the second switch circuit includes a second transistor
  • a gate of the second transistor is electrically connected to the second selection control line, a first electrode of the second transistor is electrically connected to the data output terminal, and a second electrode of the second transistor is electrically connected to the data line.
  • the pixel circuit labeled P11 is the first row and first column
  • the pixel circuit labeled P21 is the second row and first column
  • the pixel circuit labeled P31 is the third row and first column
  • the pixel circuit labeled P41 is the fourth row and first column
  • the line labeled DL is the data line
  • the line labeled CG is the scan line
  • the line labeled NG1 is the first gate line of the first row
  • the line labeled NG2 is the first gate line of the first row
  • the line labeled NG1 is the first gate line of the third row
  • the line labeled NG4 is The first grid line of the fourth row
  • the driving circuit includes a first switch circuit, a second switch circuit and a scan signal generating circuit SD;
  • the first switch circuit may include a first transistor T1;
  • the gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data output terminal S0 of the source driver, and the drain of T1 is electrically connected to the scan signal generating circuit SD;
  • the second switch circuit 13 includes a second transistor T2;
  • the gate of T2 is electrically connected to the first selection control line SW1, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the data output terminal S0 of the source driver;
  • the scan signal generating circuit SD is used for generating a scan signal according to the data signal provided by the data output terminal S0, and providing the scan signal to the scan line CGL.
  • T1 is a p-type transistor
  • T2 is an n-type transistor
  • SW1 provides a low voltage signal
  • T1 is turned on, so as to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD
  • the scan signal generating circuit SD is used to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL;
  • SW1 provides a high voltage signal and T2 is turned on to control the data output terminal S0 to be connected to the data line DL.
  • T1 is an n-type transistor and T2 is a p-type transistor.
  • SW1 provides a high voltage signal
  • T1 is turned on, so as to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD
  • the scan signal generating circuit SD is used to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the first column scan line CG1;
  • SW1 provides a low voltage signal and T2 is turned on to control the data output terminal S0 to be connected to the data line DL.
  • the first gate control line and the second gate control line are the same gate control line.
  • the pixel circuit labeled P11 is the first row and first column
  • the pixel circuit labeled P21 is the second row and first column
  • the pixel circuit labeled P31 is the third row and first column
  • the pixel circuit labeled P41 is the fourth row and first column
  • the line labeled DL is a data line
  • the line labeled CG is a scan line
  • the line labeled NG1 is the first gate line of the first row
  • the line labeled NG2 is the first gate line of the first row
  • the line labeled NG1 is the first gate line of the third row
  • the line labeled NG4 is the first gate line of the fourth row;
  • the driving circuit includes a first switch circuit, a second switch circuit and a scan signal generator.
  • the circuit is SD;
  • the first switch circuit may include a first transistor T1;
  • the gate of T1 is electrically connected to the first selection control line SW1, the source of T1 is electrically connected to the data line DL, and the drain of T1 is electrically connected to the scanning signal generating circuit SD;
  • the second switch circuit 13 includes a second transistor T2;
  • the gate of T2 is electrically connected to the second selection control line SW2, the source of T2 is electrically connected to the data line DL, and the drain of T2 is electrically connected to the data output terminal S0 of the source driver;
  • the scan signal generating circuit SD is used for generating a scan signal according to a data signal provided by the data output terminal S0, and providing the scan signal to the scan line CGL.
  • the first gate control line and the second gate control line are different gate control lines.
  • T1 is a p-type transistor
  • T2 is a p-type transistor
  • SW1 provides a low voltage signal
  • SW2 provides a high voltage signal
  • T1 is turned on to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD
  • the scan signal generating circuit SD is used to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL;
  • SW2 provides a low voltage signal
  • SW1 provides a high voltage signal
  • T2 is turned on to control the data output terminal S0 to be connected to the data line DL.
  • T1 is an n-type transistor and T2 is an n-type transistor.
  • SW1 provides a high voltage signal
  • SW2 provides a low voltage signal
  • T1 is turned on to write the data signal provided by the data output terminal S0 into the scan signal generating circuit SD
  • the scan signal generating circuit SD is used to generate a scan signal according to the data signal provided by the data output terminal S0, and provide the scan signal to the scan line CGL;
  • SW2 provides a high voltage signal
  • SW1 provides a low voltage signal
  • T2 is turned on to control the data output terminal S0 to be connected to the data line DL.
  • the scan signal generation circuit and the source driver are disposed on the same side of the display panel. In actual operation, the scan signal generation circuit and the source driver may be disposed on opposite sides of the display panel.
  • T1 is disposed on the upper side of the display panel where the scan signal generating circuit is disposed.
  • T1 is disposed on the upper side of the display panel where the scan signal generating circuit is disposed.
  • the scan signal generating circuit includes an output control circuit and an output circuit; the first switch circuit provides the data signal to the scan signal generating circuit through a control node;
  • the output control circuit is electrically connected to the control node, the first voltage terminal, the second voltage terminal, the output control terminal and the scan output terminal respectively, and is used to control the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and control the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal;
  • the output circuit is electrically connected to the control end, the scan output end, the output control end, the first voltage end and the second voltage end, respectively, and is used to control the connection or disconnection between the scan output end and the first voltage end under the control of the control signal provided by the control end, and to control the connection or disconnection between the scan output end and the second voltage end under the control of the potential of the output control end.
  • the scan signal generating circuit may include an output control circuit and an output circuit.
  • the output control circuit controls the connection or disconnection between the output control terminal and the first voltage terminal under the control of the potential of the control node, and controls the connection or disconnection between the output control terminal and the second voltage terminal under the control of the signal provided by the scan output terminal; the output circuit controls the connection or disconnection between the scan output terminal and the first voltage terminal under the control of the control signal provided by the control terminal, and controls the connection or disconnection between the scan output terminal and the second voltage terminal under the control of the potential of the output control terminal.
  • the scan output terminal is the scan signal output terminal; or,
  • the scanning signal generating circuit also includes an inverting circuit; the input end of the inverting circuit is electrically connected to the scanning output end, and the output end of the inverting circuit is electrically connected to the scanning signal output end.
  • the inverting circuit is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit.
  • the first switch circuit 11 is electrically connected to the first selection control line SW1, the data output terminal S0 of the source driver and the control node NC, respectively, and is used to control the connection or disconnection between the data output terminal S0 and the control node NC under the control of the first selection control signal provided by the first selection control line SW1;
  • the scanning signal generating circuit includes an output control circuit 71 and an output circuit 72;
  • the output control circuit 71 is electrically connected to the control node NC, the first voltage terminal V1, the second voltage terminal V2, the output control terminal OE and the scan signal output terminal CG, respectively, and is used to control the connection or disconnection between the output control terminal OE and the first voltage terminal V1 under the control of the potential of the control node NC, and control the connection or disconnection between the output control terminal OE and the second voltage terminal V2 under the control of the signal provided by the scan signal output terminal CG;
  • the output circuit 72 is electrically connected to the control terminal VHRD, the output control terminal OE, the scan signal output terminal CG, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the scan signal output terminal CG and the first voltage terminal V1 under the control of the potential of the control signal provided by the control terminal VHRD, and to control the connection or disconnection between the scan signal output terminal CG and the second voltage terminal V2 under the control of the potential of the output control terminal OE.
  • the scan output terminal may be a scan signal output terminal CG
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the first switch circuit 11 is electrically connected to the first selection control line SW1, the data output terminal S0 of the source driver and the control node NC, respectively, and is used to control the connection or disconnection between the data output terminal S0 and the control node NC under the control of the first selection control signal provided by the first selection control line SW1;
  • the scanning signal generating circuit includes an output control circuit 71 and an output circuit 72;
  • the output control circuit 71 is electrically connected to the control node NC, the first voltage terminal V1, the second voltage terminal V2, the output control terminal OE and the scan output terminal OP respectively, and is used to control the connection or disconnection between the output control terminal OE and the first voltage terminal V1 under the control of the potential of the control node NC1, and control the connection or disconnection between the output control terminal OE and the second voltage terminal V2 under the control of the signal provided by the scan output terminal OP;
  • the output circuit 72 is electrically connected to the control terminal VHRD, the scan output terminal OP, the output control terminal OE, the first voltage terminal V1 and the second voltage terminal V2, respectively, and is used to control the connection or disconnection between the scan output terminal OP and the first voltage terminal V1 under the control of the potential of the control terminal VHRD, and control the connection or disconnection between the scan output terminal OP and the second voltage terminal V2 under the control of the potential of the output control terminal OE;
  • the scanning signal generating circuit further includes an inverting circuit 73;
  • the input end of the inverting circuit 73 is electrically connected to the scan output end OP, and the output end of the inverting circuit 73 is electrically connected to the scan signal output end CG.
  • the inverting circuit 73 is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverting circuit 73.
  • the output control circuit includes a third transistor and a fourth transistor;
  • the gate of the third transistor is electrically connected to the control node, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the output control terminal;
  • the gate of the fourth transistor is electrically connected to the scan output terminal, the first electrode of the fourth transistor is electrically connected to the output control terminal, and the second electrode of the fourth transistor is electrically connected to the second voltage terminal;
  • the output circuit includes a fifth transistor, a sixth transistor and a second capacitor;
  • the gate of the fifth transistor is electrically connected to the control terminal, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the scan output terminal;
  • the gate of the sixth transistor is electrically connected to the output control terminal, the first electrode of the sixth transistor is electrically connected to the scan output terminal, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;
  • the first end of the second capacitor is electrically connected to the control end, and the second end of the second capacitor is electrically connected to the second voltage end.
  • the first switch circuit includes a first transistor T1 and a first capacitor C1;
  • the gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor is electrically connected to the data output terminal S0, and the drain of the first transistor T1 is electrically connected to the control node NC;
  • a first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the low voltage end VGL;
  • the output control circuit includes a third transistor T3 and a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the output control terminal OE;
  • the gate of the fourth transistor T4 is electrically connected to the scan signal output terminal CG, the source of the fourth transistor T4 is electrically connected to the output control terminal OE, and the drain of the fourth transistor T4 is electrically connected to the low voltage terminal VGL;
  • the output circuit includes a fifth transistor T5, a sixth transistor T6 and a second capacitor C2;
  • the gate of the fifth transistor T5 is electrically connected to the control terminal VHRD, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the scan signal output terminal CG;
  • the gate of the sixth transistor T6 is electrically connected to the output control terminal OE, the source of the sixth transistor T6 is electrically connected to the scan signal output terminal CG, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;
  • a first end of the second capacitor C2 is electrically connected to the control end VHRD, and a second end of the second capacitor C2 is electrically connected to the low voltage end VGL.
  • control voltage terminal is the second voltage terminal
  • first voltage terminal is the high voltage terminal
  • second voltage terminal is the low voltage terminal
  • S0 may be electrically connected to the corresponding column data line DL.
  • T1 is a p-type transistor
  • T3 is a p-type transistor
  • T4 is an n-type transistor
  • T5 is a p-type transistor
  • T6 is an n-type transistor.
  • control terminal VHRD is used for a 3V voltage signal
  • the high voltage terminal VGH can be used to provide an 8V voltage signal
  • the low voltage terminal VGL can be used to provide a -8V voltage signal.
  • the voltage value of the control signal provided by the control terminal VHRD can be greater than or equal to 3V and less than or equal to 4V
  • the voltage value of the high voltage signal provided by the high voltage terminal VGH can be greater than or equal to 7V and less than or equal to 9V
  • the voltage value of the low voltage signal provided by the low voltage terminal VGL can be greater than or equal to -9V and less than or equal to -7V, but not limited to this.
  • the period labeled TB1 is the first blank period
  • the period labeled TB2 is the second control period
  • the period labeled TX1 is the first data writing period
  • the period labeled TX2 is the second data writing period.
  • SW1 provides a low voltage signal
  • T1 is turned on
  • S0 provides a high voltage signal
  • the data line DL is connected to the high voltage signal
  • the potential of NC is a high voltage
  • T5 is turned on
  • CG is connected to VGH
  • the potential of CG is a high voltage
  • T4 is turned on, so that OE is connected to VGL, and OE outputs a low voltage signal;
  • the potential of CG is maintained at a high voltage
  • SW1 provides a low voltage signal
  • T1 is turned on
  • S0 provides a low voltage signal
  • DL receives the low voltage signal
  • the potential of NC is low voltage
  • T3 is turned on
  • OE is connected to VGH
  • the potential of OE is high voltage
  • T6 is turned on
  • CG outputs a low voltage signal
  • the potential of CG is maintained at a low voltage.
  • the voltage value of the high voltage signal connected to DL may be 7V;
  • the voltage value of the low voltage signal connected to DL may be 0V;
  • the opening degree of T6 is higher than that of T5 , so CG outputs a low voltage signal.
  • the first switch circuit includes a first transistor T1 and a first capacitor C1;
  • the gate of the first transistor T1 is electrically connected to the first selection control line SW1, the source of the first transistor is electrically connected to the data output terminal S0, and the drain of the first transistor T1 is electrically connected to the control node NC;
  • a first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the low voltage end VGL;
  • the output control circuit includes a third transistor T3 and a fourth transistor T4;
  • the gate of the third transistor T3 is electrically connected to the control node NC, the source of the third transistor T3 is electrically connected to the high voltage terminal VGH, and the drain of the third transistor T3 is electrically connected to the output control terminal OE;
  • the gate of the fourth transistor T4 is electrically connected to the control node NC, the source of the fourth transistor T4 is electrically connected to the output control terminal OE, and the drain of the fourth transistor T4 is electrically connected to the low voltage terminal VGL;
  • the output circuit includes a fifth transistor T5 and a sixth transistor T6;
  • the gate of the fifth transistor T5 is electrically connected to the control terminal VHRD, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the scan output terminal OP;
  • the gate of the sixth transistor T6 is electrically connected to the output control terminal OE, the source of the sixth transistor T6 is electrically connected to the scan output terminal OP, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL;
  • the inverting circuit comprises an inverter IV;
  • the input end of the inverter IV is electrically connected to the scan output end OP, and the output end of the inverter IV is electrically connected to the scan signal output end CG.
  • the inverter IV is used to invert the voltage signal connected to its input end to obtain an inverted voltage signal, and output the inverted voltage signal through the output end of the inverter IV.
  • the first voltage end is a high voltage end
  • the second voltage end is a low voltage end
  • S0 may be electrically connected to the data line DL.
  • control terminal VHRD is used for a 3V voltage signal
  • the high voltage terminal VGH can be used to provide an 8V voltage signal
  • the low voltage terminal VGL can be used to provide a -8V voltage signal.
  • the first blank time period, the first data writing time period, the second blank time period and the second data writing time period may be set successively;
  • SW1 provides a low voltage signal
  • T1 is turned on
  • S0 provides a high voltage signal
  • DL is connected to the high voltage signal
  • the potential of NC is high voltage
  • T5 is turned on
  • OP is connected to VGH
  • OP is turned on
  • the potential of is high voltage
  • T4 is turned on, so that OE and VGL are connected, OE outputs a low voltage signal
  • CG outputs a low voltage signal
  • the potential of CG is maintained at a low voltage
  • SW1 provides a low voltage signal
  • T1 is turned on
  • S0 provides a low voltage signal
  • DL receives the low voltage signal
  • the potential of NC is a low voltage
  • T3 is turned on
  • OE is connected to VGH
  • the potential of OE is a high voltage
  • T6 is turned on
  • OP outputs a low voltage signal
  • CG outputs a high voltage signal
  • the potential of CG is maintained at a high voltage.
  • the voltage value of the high voltage signal connected to the DL may be 7V;
  • the voltage value of the low voltage signal connected to DL may be 0V;
  • the opening degree of T6 is higher than that of T5 , so OP outputs a low voltage signal.
  • FIG. 14 is a simulation operation timing diagram of at least one embodiment of the scan signal generating circuit shown in FIG. 13 .
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method comprises: during at least a part of the blank time period between two frames of display time,
  • the first switch circuit controls, under the control of the first selection control signal, to write the data signal provided by the data output terminal of the source driver into the scanning signal generating circuit;
  • the scanning signal generating circuit generates a scanning signal according to the data signal, and outputs the scanning signal to a corresponding column scanning line of the display panel through a scanning signal output terminal.
  • the first switching circuit under the control of the first selection control signal, controls the writing of the data signal provided by the data output terminal of the source driver into the scan signal generating circuit;
  • the scan signal generating circuit generates a scan signal according to the data signal provided by the data output terminal, and outputs the scan signal to the corresponding column scan line of the display panel through the scan signal output terminal.
  • the driving circuit further includes a second switch circuit; and the driving method further includes:
  • the second switch circuit controls the data output terminal of the source driver to be connected to the corresponding column data line of the display panel under the control of the second selection control signal.
  • the driving circuit may further include a second switching circuit.
  • the second switching circuit under the control of a second selection control signal, controls the data output terminal to be connected to the corresponding column data line of the display panel to provide a data voltage to the data line.
  • the pixel circuit described in the embodiment of the present disclosure includes a light-emitting element, a light-emitting driving circuit and a control circuit;
  • the light-emitting driving circuit is electrically connected to the first node and the first electrode of the light-emitting element respectively, and is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node; the second electrode of the light-emitting element is electrically connected to the third voltage terminal;
  • the control circuit is electrically connected to the first gate line, the scan line, the first node and the first pole of the light-emitting element, respectively, and is used to control the connection or disconnection between the first node and the first pole of the light-emitting element under the control of the first gate drive signal provided by the first gate line and the scan signal provided by the scan line.
  • the pixel circuit may include a control circuit and a light-emitting driving circuit.
  • the light-emitting driving circuit generates a driving current under the control of the potential of the first node.
  • the control circuit controls the connection or disconnection between the first node and the first pole of the light-emitting element under the control of a first gate driving signal provided by a first gate line and a scanning signal provided by a scanning line.
  • the driving current may be a current that drives the light-emitting element to emit light.
  • the third voltage terminal may be a low level terminal, but is not limited thereto.
  • the light-emitting element is an organic light-emitting diode
  • the first electrode of the light-emitting element is an anode
  • the second electrode of the light-emitting element is a cathode
  • the pixel circuit may include a light emitting element E0, a control circuit 201 and a light emitting driving circuit 230;
  • the light-emitting driving circuit 230 is electrically connected to the first node N1 and the first electrode of the light-emitting element E0 respectively, and is used to generate a driving current to drive the light-emitting element E0 under the control of the potential of the first node N1; the second electrode of the light-emitting element E0 is electrically connected to the third voltage terminal V3;
  • the control circuit 201 is electrically connected to the first gate line NG, the scan line CGL, the first node N1 and the first electrode of the light-emitting element E0, respectively, and is used to control the connection or disconnection between the first node N1 and the first electrode of the light-emitting element E0 under the control of the first gate driving signal provided by the first gate line NG and the scan signal provided by the scan line CGL.
  • control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first control circuit is electrically connected to the first gate line, the first node and the intermediate node respectively, and the first control circuit is used to control the connection or disconnection between the first node and the intermediate node under the control of the first gate driving signal provided by the first gate line;
  • the second control circuit is electrically connected to the scan line, the intermediate node and the third node respectively, and is used to control the connection or disconnection between the intermediate node and the third node under the control of the scan signal provided by the scan line.
  • control circuit may include a first control circuit and a second control circuit.
  • the first control circuit controls the connection or disconnection between the first node and the intermediate node under the control of a first gate drive signal provided by a first gate line
  • the second control circuit controls the connection or disconnection between the intermediate node and the third node under the control of a scan signal provided by the scan line.
  • the control circuit includes a first control circuit 241 and a second control circuit 242; a first end of the light emitting driving circuit 230 is electrically connected to the second node N2, and a second end of the light emitting driving circuit 230 is electrically connected to a third node N3 and a first electrode of the light emitting element E0, respectively;
  • the first control circuit 241 is electrically connected to the first gate line NG, the first node N1 and the middle node NZ respectively. connected, for controlling the connection or disconnection between the first node N1 and the middle node NZ under the control of the first gate driving signal provided by the first gate line NG;
  • the second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the third node N3 respectively, and is used to control the connection or disconnection between the middle node NZ and the third node N3 under the control of the scan signal provided by the scan line CGL.
  • control circuit includes a first control circuit and a second control circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first control circuit is electrically connected to the first gate line, the third node and the intermediate node respectively, and is used to control the connection or disconnection between the third node and the intermediate node under the control of the first gate driving signal provided by the first gate line;
  • the second control circuit is electrically connected to the scan line, the intermediate node and the first node respectively, and is used to control the connection or disconnection between the intermediate node and the first node under the control of the scan signal provided by the scan line.
  • control circuit may include a first control circuit and a second control circuit, wherein the first control circuit controls the connection or disconnection between the third node and the intermediate node under the control of a first gate drive signal provided by the first gate line; and the second control circuit controls the connection or disconnection between the intermediate node and the first node under the control of a scan signal provided by the scan line.
  • the control circuit includes a first control circuit 241 and a second control circuit 242; a first end of the light emitting driving circuit 230 is electrically connected to the second node N2, and a second end of the light emitting driving circuit 230 is electrically connected to a third node N3 and a first electrode of the light emitting element E0, respectively;
  • the first control circuit 241 is electrically connected to the first gate line NG, the third node N3 and the middle node NZ respectively, and is used to control the connection or disconnection between the third node N3 and the middle node NZ under the control of the first gate driving signal provided by the first gate line NG;
  • the second control circuit 242 is electrically connected to the scan line CGL, the middle node NZ and the first node N1 respectively, and is used to control the connection or disconnection between the middle node NZ and the first node N1 under the control of the scan signal provided by the scan line CGL.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the first initialization circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the second node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the second node under the control of the first initial control signal provided by the first initial control terminal.
  • the display period may include a first initialization time period and a second initialization time period which are set successively;
  • the control circuit In the first initialization period, the control circuit generates a voltage between the first gate drive signal and the scan signal. Under the control of the first initial control signal, the first initialization circuit controls the first node to be connected to the third node; under the control of the first initial control signal, the first initialization circuit writes the first initial voltage to the second node; under the control of the potential of the first node, the light emitting driving circuit controls the second node to be connected to the third node;
  • the control circuit controls the first node and the third node to be disconnected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node.
  • the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first initialization time period, before data is written, the potentials of the first node, the second node and the third node are initialized to reduce subsequent charging differences.
  • the first initialization circuit writes the first initial voltage to the second node, and the light-emitting driving circuit controls the connection between the second node and the third node so that the driving transistor included in the light-emitting driving circuit is in a biased state, which can improve the hysteresis phenomenon.
  • the pixel circuit further includes a second initialization circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the second initialization circuit is electrically connected to the second initial control terminal, the second initial voltage terminal and the third node respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the third node under the control of the second initial control signal provided by the second initial control terminal.
  • the pixel circuit may further include a second initialization circuit
  • the second initialization circuit In a third initialization time period set between the first initialization time period and the second initialization time period, before the data writing time period, the second initialization circuit writes the second initial voltage to the third node under the control of the second initial control signal, so that at the beginning of the data writing time period, the driving transistor included in the light-emitting driving circuit can be turned on, which is convenient for data voltage writing and threshold voltage compensation.
  • the pixel circuit further includes a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the first end of the light-emitting driving circuit is electrically connected to the second node, and the second end of the light-emitting driving circuit is electrically connected to the third node and the first electrode of the light-emitting element respectively;
  • the data writing circuit is electrically connected to the second gate line, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate line;
  • the first light-emitting control circuit is electrically connected to the light-emitting control line, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control line;
  • the second light emitting control circuit is electrically connected to the light emitting control line, the third node and the first electrode of the light emitting element respectively, and is used to control the third node to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal;
  • the energy storage circuit is electrically connected to the first node and is used for storing electric energy.
  • the pixel circuit may further include a data writing circuit, a first light-emitting control circuit, a second light-emitting control circuit and an energy storage circuit; the data writing circuit is used to write the data voltage into the second node, the first light-emitting control circuit and the second light-emitting control circuit are used to control the conduction light-emitting path, and the energy storage circuit is used to store electrical energy.
  • the pixel circuit described in at least one embodiment of the present disclosure further includes a third initialization circuit
  • the third initialization circuit is electrically connected to the first initial control terminal, the third initial voltage terminal and the first pole of the light-emitting element respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the first pole of the light-emitting element under the control of the first initial control signal provided by the first initial control terminal.
  • the pixel circuit may further include a third initialization circuit, which, under the control of the first initial control signal, writes a third initial voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light and clear the residual charge in the first electrode of the light-emitting element.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light-emitting control circuit 234, a second light-emitting control circuit 235, a storage circuit 236, and a third initialization circuit 237; the second electrode of the light-emitting element E0 is electrically connected to the low level end ELVSS;
  • the first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;
  • the second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;
  • the data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;
  • the first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;
  • the second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3 and the first electrode of the light emitting element E0 respectively, and is used to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;
  • the energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy
  • the third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.
  • the third voltage terminal is a low level terminal ELVSS.
  • the pixel circuit described in at least one embodiment of the present disclosure may further include a first initialization circuit 231, a second initialization circuit 232, a data writing circuit 233, a first light emitting control circuit 234, a second light emitting control circuit 235, a storage circuit 236, and a third initialization circuit 237; the second electrode of the light emitting element E0 is electrically connected to the low level end ELVSS;
  • the first initialization circuit 231 is electrically connected to the first initial control terminal HR, the first initial voltage terminal I1 and the second node N2 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2 under the control of the first initial control signal provided by the first initial control terminal HR;
  • the second initialization circuit 232 is electrically connected to the second initial control terminal PR, the second initial voltage terminal I2 and the third node N3 respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the third node N3 under the control of the second initial control signal provided by the second initial control terminal PR;
  • the data writing circuit 233 is electrically connected to the second gate line PG, the data line DT and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DT into the second node N2 under the control of the second gate driving signal provided by the second gate line PG;
  • the first light emitting control circuit 234 is electrically connected to the light emitting control line E1, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control line E1;
  • the second light emitting control circuit 235 is electrically connected to the light emitting control line E1, the third node N3 and the first electrode of the light emitting element E0 respectively, and is used to control the third node N3 to be electrically connected to the first electrode of the light emitting element E0 and the second electrode of the light emitting element E0 to be electrically connected to the third voltage terminal V3 under the control of the light emitting control signal;
  • the energy storage circuit 236 is electrically connected to the first node N1 and is used to store electrical energy
  • the third initialization circuit 237 is electrically connected to the first initial control terminal HR, the third initial voltage terminal I3 and the first electrode of the light-emitting element E0, respectively, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the first electrode of the light-emitting element E0 under the control of the first initial control signal provided by the first initial control terminal HR.
  • the third voltage terminal is a low level terminal ELVSS.
  • the first control circuit includes a first control transistor
  • the second control circuit includes a second control transistor
  • the gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the first node, and the second electrode of the first control transistor is electrically connected to the intermediate node;
  • a gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the intermediate node, and a second electrode of the second control transistor is electrically connected to the third node.
  • the first control circuit includes a first control transistor
  • the second control circuit includes a second control transistor
  • the gate of the first control transistor is electrically connected to the first gate line, the first electrode of the first control transistor is electrically connected to the intermediate node, and the second electrode of the first control transistor is electrically connected to the third node;
  • a gate of the second control transistor is electrically connected to the scan line, a first electrode of the second control transistor is electrically connected to the first node, and a second electrode of the second control transistor is electrically connected to the intermediate node.
  • the first initialization circuit includes a first initialization transistor
  • a gate of the first initialization transistor is electrically connected to the first initial control terminal, a first electrode of the first initialization transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first initialization transistor is electrically connected to the second node.
  • the second initialization circuit includes a second initialization transistor
  • a gate of the second initialization transistor is electrically connected to the second initial control terminal, a first electrode of the second initialization transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second initialization transistor is electrically connected to the third node.
  • the data writing circuit includes a writing transistor, the first light emitting control circuit includes a first light emitting control transistor, and the second light emitting control circuit includes a second light emitting control transistor; the light emitting driving circuit includes a driving transistor, and the energy storage circuit includes a storage capacitor;
  • the gate of the write transistor is electrically connected to the second gate line, the first electrode of the write transistor is electrically connected to the data line, and the second electrode of the write transistor is electrically connected to the second node;
  • the gate of the first light emission control transistor is electrically connected to the light emission control line, the first electrode of the first light emission control transistor is electrically connected to the power supply voltage terminal, and the second electrode of the first light emission control transistor is electrically connected to the second node;
  • the gate of the second light emission control transistor is electrically connected to the light emission control line, the first electrode of the second light emission control transistor is electrically connected to the third node, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element;
  • the gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;
  • the first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a power supply voltage terminal.
  • the third initialization circuit includes a third initialization transistor
  • the gate of the third initialization transistor is electrically connected to the first initial control terminal, the first electrode of the third initialization transistor is electrically connected to the third initial voltage terminal, and the second electrode of the third initialization transistor is electrically connected to the first electrode of the light emitting element.
  • the first control circuit includes a first control transistor M1
  • the second control circuit includes a second control transistor M2
  • the light emitting driving circuit includes a driving transistor M0 ;
  • a gate of the first control transistor M1 is electrically connected to the first gate line NG, a source of the first control transistor M1 is electrically connected to the first node N1, and a second electrode of the first control transistor M1 is electrically connected to the middle node NZ;
  • the gate of the second control transistor M2 is electrically connected to the scan line CGL, the source of the second control transistor M2 is electrically connected to the middle node NZ, and the drain of the second control transistor M2 is electrically connected to the third node N3;
  • the gate of the driving transistor M0 is electrically connected to the first node N1, the source of the driving transistor M0 is electrically connected to the second node N2, and the drain of the driving transistor M0 is electrically connected to the third node N3;
  • the first initialization circuit includes a first initialization transistor M3;
  • the gate of the first initialization transistor M3 is electrically connected to the first initial control terminal HR, the source of the first initialization transistor M3 is electrically connected to the first initial voltage terminal I1, and the drain of the first initialization transistor M3 is electrically connected to the second node N2; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;
  • the second initialization circuit includes a second initialization transistor M4;
  • the gate of the second initialization transistor M4 is electrically connected to the second initial control terminal PR, the source of the second initialization transistor M4 is electrically connected to the second initial voltage terminal I2, and the drain of the second initialization transistor M4 is electrically connected to the third node N3; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;
  • the data writing circuit includes a writing transistor M5, the first light emitting control circuit includes a first light emitting control transistor M6, and the second light emitting control circuit includes a second light emitting control transistor M7; the energy storage circuit includes a storage capacitor Cst; the light emitting element is an organic light emitting diode O1;
  • the gate of the write transistor M5 is electrically connected to the second gate line PG, the source of the write transistor M5 is electrically connected to the data line DT, and the drain of the write transistor M5 is electrically connected to the second node N2;
  • the gate of the first light emission control transistor M6 is electrically connected to the light emission control line E1, the source of the first light emission control transistor M6 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the first light emission control transistor M6 is electrically connected to the second node N2;
  • a gate of the second light emission control transistor M7 is electrically connected to the light emission control line E1, a source of the second light emission control transistor M7 is electrically connected to the third node N3, and a drain of the second light emission control transistor M7 is electrically connected to the anode of the organic light emitting diode O1;
  • a first end of the storage capacitor Cst is electrically connected to the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power supply voltage terminal ELVDD;
  • the third initialization circuit includes a third initialization transistor M8;
  • the gate of the third initialization transistor M8 is electrically connected to the first initial control terminal HR, the source of the third initialization transistor M8 is electrically connected to the third initial voltage terminal I3, and the drain of the third initialization transistor M8 is electrically connected to the anode of the organic light emitting diode O1;
  • the cathode of the organic light emitting diode O1 is electrically connected to the low level end ELVSS.
  • M1 and M2 are n-type transistors, and the other transistors are p-type transistors, but the present invention is not limited thereto.
  • a frame display time may include a first initialization time period TI1, a third initialization time period TI3, a data writing time period TI4, and a second initialization time period TI5.
  • TX a second initialization period TI2 and a light-emitting period TF; during the frame display time, CG can output a high voltage signal to control M2 to turn on;
  • the third initialization period TI3 and the data writing period TX, NG outputs a high voltage signal to control M1 to be turned on;
  • the third initialization period TI3 the data writing period TX and the second initialization period TI2, E1 provides a high voltage signal, and M6 and M7 are turned off;
  • NG In the second initialization period TI2 and the light-emitting period TF, NG outputs a low voltage signal to control M1 to turn off;
  • HR outputs a low voltage signal
  • PR and PG both output high voltage signals
  • M3 is turned on to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the second node N2
  • M0 is turned on to control the connection between N2 and N3
  • M1 and M2 are turned on to control the connection between N1 and N3 to initialize the potential of the first node N1, the potential of the second node N2 and the potential of the third node N3 to reduce the subsequent charging difference
  • PR In the third initialization period TI3, PR outputs a low voltage signal, HR and PG both output high voltage signals, and M4 is turned on to write the second initial voltage Vinit2 provided by I2 into the third node N3, so that M0 can be turned on when the data writing period TX starts;
  • Vdata charges Cst, until the potential of the first node N1 becomes Vdata+Vth, and M0 is turned off; wherein Vth is the threshold voltage of M0;
  • HR provides a low voltage signal
  • PR and PG both output high voltage signals
  • M3 is turned on to write Vinit1 into the second node N2
  • M0 is turned on to connect N2 and N3.
  • the potential of N1 is a smaller positive voltage
  • the potential of N2 and the potential of N3 are higher positive voltages
  • M0 is in a bias state
  • all driving transistors included in the display panel are in a bias state, which can improve the hysteresis phenomenon.
  • the voltage value of Vinit1 may be a positive value, for example, the voltage value of Vinit1 may be greater than or equal to 4V and less than or equal to 7V;
  • the voltage value of Vinit2 and the voltage value of Vinit3 may be negative values, for example, the voltage value of Vinit2 and the voltage value of Vinit3 may be greater than or equal to -5V and less than or equal to -3V;
  • the potential of N1, the potential of N2 and the potential of N3 are all set to a reference voltage, so that in the data writing time period, the data voltage of the previous frame display time will not affect the writing of the data voltage of the current frame.
  • At least one embodiment of the pixel circuit shown in FIG20 is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a low voltage signal during at least part of the blank period between two frames of display time, and CG continues to output a low voltage signal during the next frame of display time to control M2 to be turned off, so that the data voltage is not written, so as to maintain the display screen without refreshing the screen;
  • CG is controlled to output a high voltage signal, and in the next frame display time, CG continues to output a high voltage signal to control M2 to turn on, so as to write data voltage in the data writing period to refresh the picture.
  • one frame display time may be a refresh frame.
  • the holding frame may include a holding initial time period TBC and a holding light emitting time period TBF which are set successively;
  • HR outputs a low voltage signal
  • NG outputs a low voltage signal
  • PR and PG both output high voltage signals
  • E1 provides a high voltage signal
  • M1 is turned off to control the disconnection between N1 and N3, M6 and M7 are turned off, and M5 is turned off
  • M3 and M8 are turned on
  • I1 provides a first initial voltage Vinit1 to the second node N2
  • driving transistor M0 is turned on to control the connection between N2 and N3, and the potential of the second node N2 and the potential of the third node N3 are initialized to improve the hysteresis phenomenon
  • I3 provides a third initial voltage Vinit3 to the third node N3, and initializes the potential of the anode of O1, controls O1 not to emit light, and clears the residual charge of the anode of O1;
  • E1 provides a low voltage signal
  • HR provides a high voltage signal
  • NG outputs a low voltage signal
  • PR and PG both output high voltage signals
  • M1, M2, M3, M4, M5 and M8 are all turned off
  • M6 and M7 are turned on
  • M0 drives O1 to emit light.
  • M2 is a p-type transistor.
  • At least one embodiment of the pixel circuit shown in FIG22 is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a high voltage signal during at least part of the blank period between two display frames, and CG to continuously output a low voltage signal during the next display frame to control M2 to be turned off, so that the data voltage is not written, so as to maintain the display screen without refreshing the screen;
  • the gate of the first control transistor M1 is electrically connected to the first gate line NG, the source of the first control transistor M1 is electrically connected to the middle node NZ, and the drain of the first control transistor M1 is electrically connected to the third node N3;
  • a gate of the second control transistor M2 is electrically connected to the scan line CGL, a source of the second control transistor M2 is electrically connected to the first node N1, and a drain of the second control transistor M2 is electrically connected to the intermediate node NZ.
  • both M1 and M2 are n-type transistors.
  • At least one embodiment of the pixel circuit shown in FIG23 is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a low voltage signal during at least part of the blank period between two frames of display time, and CG continues to output a low voltage signal during the next frame of display time to control M2 to turn off so as not to perform data voltage refresh on the pixel circuit.
  • Data voltage is written to maintain the display screen without refreshing the screen;
  • M2 is a p-type transistor.
  • At least one embodiment of the pixel circuit shown in FIG24 is in operation, when it is not necessary to refresh the data voltage of the pixel circuit, it is necessary to control CG to output a high voltage signal during at least part of the blank period between two display frames, and CG to continuously output a low voltage signal during the next display frame to control M2 to be turned off, so that the data voltage is not written, so as to maintain the display screen without refreshing the screen;
  • the pixel driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the pixel driving method includes:
  • the light-emitting driving circuit generates a driving current for driving the light-emitting element under the control of the potential of the first node
  • the control circuit controls the connection or disconnection between the first node and the first electrode of the light emitting element under the control of the first gate driving signal and the scanning signal.
  • the pixel circuit includes a first initialization circuit, a first end of the light-emitting driving circuit is electrically connected to the second node, and a second end of the light-emitting driving circuit is electrically connected to a third node and a first electrode of a light-emitting element, respectively;
  • a display period includes a first initialization time period and a second initialization time period which are set successively; and the pixel driving method includes:
  • the control circuit controls the first node to be connected to the third node under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; the light emitting drive circuit controls the second node to be connected to the third node under the control of the potential of the first node;
  • the control circuit controls the first node and the third node to be disconnected under the control of the first gate drive signal and the scan signal; the first initialization circuit writes the first initial voltage to the second node under the control of the first initial control signal; and the light-emitting drive circuit controls the second node and the third node to be connected under the control of the potential of the first node.
  • the display panel described in at least one embodiment of the present disclosure includes a source driver and the above-mentioned driving circuit
  • the source driver includes a data output terminal.
  • the display panel described in at least one embodiment of the present disclosure includes a plurality of columns of scan lines
  • a scan signal output terminal in a scan signal generating circuit in the driving circuit is electrically connected to the scan line.
  • the display panel may include a plurality of scan lines, and the scan signal output end is electrically connected to the scan lines to provide scan signals to the scan lines.
  • the display panel includes a plurality of columns of data lines
  • the data output terminal is directly electrically connected to the data line; or,
  • the driving circuit includes a second switch circuit, and the second switch circuit controls the connection or disconnection between the data output terminal and the data line under the control of a second selection control signal.
  • the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on the first side of the display panel; or,
  • the source driver is disposed on a first side of the display panel, and the driving circuit is disposed on a second side of the display panel.
  • the first side and the second side are opposite sides.
  • first side may be a lower side
  • second side may be an upper side
  • present invention is not limited thereto.
  • the area labeled A0 is the display area of the display panel
  • the first column of data lines is labeled DL1, the first column of scan lines is labeled CG1, the second column of data lines is labeled DL2, the second column of scan lines is labeled CG2, the third column of data lines is labeled DL3, the third column of scan lines is labeled CG3, the fourth column of data lines is labeled DL4, the fourth column of scan lines is labeled CG4; the mth column of data lines is labeled DLm, the mth column of scan lines is labeled CGm; the mth column of data lines is labeled DLM, the mth column of scan lines is labeled CGM;
  • SI is the source driver
  • the first data output terminal of the source driver S1 is labeled S1
  • the second data output terminal of the source driver S1 is labeled S2
  • the third data output terminal of the source driver S1 is labeled S3
  • the fourth data output terminal of the source driver S1 is labeled S4
  • the mth data output terminal is labeled Sm
  • the Mth data output terminal is labeled SM
  • the first first selection control line is labeled SW11
  • the second first selection control line is labeled SW21;
  • the source driver SI is electrically connected to SW11 and SW21, and is used to provide a first first gating control signal to SW11 and a second first gating control signal to SW21;
  • the first gating unit is labeled X1
  • the second gating unit is labeled X2
  • the third gating unit is labeled X3
  • the fourth gating unit is labeled X4
  • the mth gating unit is labeled Xm
  • the Mth gating unit is labeled XM;
  • Each gating unit includes a first switch circuit and a scan signal generating circuit; or each gating unit includes a first switch circuit, a second switch circuit and a scan signal generating circuit.
  • the first gating unit X1 is electrically connected to DL1 and CG1
  • the second gating unit X2 is electrically connected to DL2 and CG2
  • the third gating unit X3 is electrically connected to DL3 and CG3
  • the fourth gating unit X4 is electrically connected to DL4 and CG4
  • the mth gating unit Xm is electrically connected to DL and CGm
  • the Mth gating unit XM is electrically connected to DLM and CGM
  • the source driver SI is disposed below A0, and the first selection unit X1, the second selection unit X2, the third selection unit X3, the fourth selection unit X4, the mth selection unit Xm and the Mth selection unit XM are disposed below A0.
  • the difference between at least one embodiment of the display panel shown in FIG. 26 and at least one embodiment of the display panel shown in FIG. 25 is The first gating unit X1, the second gating unit X2, the third gating unit X3, the fourth gating unit X4, the mth gating unit Xm and the Mth gating unit XM are arranged above A0.
  • the data output terminals of the source driver SI are concentrated in the middle of the display panel to realize a narrow lower frame.
  • At least one embodiment of the display panel shown in FIG27 is combined with a FIP (Fanout In Pixel) embodiment.
  • the display panel described in at least one embodiment of the present disclosure may also include multiple rows and columns of the above-mentioned pixel circuits.
  • each gating unit may be a driving circuit as described in at least one embodiment of the present disclosure.
  • two columns of pixel circuits may be electrically connected to the same column of scan lines.
  • the disclosed embodiments provide a driving scheme for an OLED display.
  • a local refresh pixel circuit cooperates with a source driving circuit and a driving scheme, and can update a local screen image through an HCT control signal (the HCT control signal can be a data signal provided by the source driver through its data output terminal during a blank time period), while the remaining images do not need to be charged and discharged multiple times, thereby further reducing the power consumption of the OLED display, or achieving ultra-low power consumption by partially updating the display image.
  • the gate drive circuit when it is necessary to update part of the screen, such as only the date and time part needs to be updated.
  • the first gate drive signal is normally output to control the first control transistor in the pixel circuit in the display area to be normally turned on for data update; in the row where the screen does not need to be updated, the potential of the first gate drive signal is always maintained to turn off the first control transistor to ensure that the pixel brightness remains unchanged, thereby achieving local refresh in the row direction.
  • the column direction it can be achieved by controlling whether the column scan line turns on the second control transistor in the pixel circuit: in the blank period between the two frames of display time, the source driver outputs HCT pulse, writes different scan signals to the column scan line, and if the current column needs to be updated, the column scan line needs to ensure that the second control transistor is always turned on, so that the current column can be refreshed normally; if some columns do not need to be updated, the column scan line needs to ensure that the second control transistor in the pixel circuit of these columns is always turned off.
  • the display panel described in at least one embodiment of the present disclosure further includes the above-mentioned pixel circuit.
  • the display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

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Abstract

一种驱动电路、驱动方法、像素电路、显示面板和显示装置，其中驱动电路包括第一开关电路（11）和扫描信号生成电路（SD）；第一开关电路（11）在第一选通控制信号（SW1）的控制下，控制将数据输出端（S0）提供的数据信号写入扫描信号生成电路（SD）；扫描信号生成电路（SD）用于根据数据信号生成扫描信号，并通过扫描信号输出端（SG）输出扫描信号。驱动电路控制是否对相应的像素电路进行数据电压刷新，从而可以实现屏幕局部画面的更新，节省功耗。

Description

驱动电路、驱动方法、像素电路、显示面板和显示装置
相关申请的交叉引用
本申请主张在2023年6月16日在中国提交的中国专利申请号No.202310717043.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法、像素电路、显示面板和显示装置。
背景技术
OLED(有机发光二极管)显示技术具备高对比、快速响应、低功耗等优势。为了进一步降低功耗，采用LTPS(低温多晶硅)+IGZO(铟镓锌氧化物)结合而实现的LTPO(低温多晶氧化物)显示技术可以实现低帧频显示，通过减少静态画面的反复刷新来降低驱动功耗。但现有的OLED显示器在更新画面时，仍然需要在一帧内对全部像素电压进行初始化和写入。而在某些特殊画面下，整屏绝大部分像素电压不需要更新，即可以通过低漏电的LTPO TFT(薄膜晶体管)维持在原有的显示亮度，对这些像素的反复刷写造成了数据线功耗的浪费。
发明内容
本公开实施例提供一种驱动电路，包括第一开关电路和扫描信号生成电路；
所述第一开关电路与第一选通控制线、源极驱动器的数据输出端和所述扫描信号生成电路电连接，用于在所述第一选通控制线提供的第一选通控制信号的控制下，控制将所述数据输出端提供的数据信号写入所述扫描信号生成电路；
所述扫描信号生成电路用于根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号。
可选的，本公开至少一实施例所述的驱动电路还包括第二开关电路；
所述第二开关电路分别与第二选通控制线、所述数据输出端和显示面板包括的数据线电连接，用于在所述第二选通控制线提供的第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开；
所述第一选通控制线与所述第二选通控制线为同一选通控制线，或者，所述第一选通控制线与所述第二选通控制线不同。
可选的，所述第一开关电路包括第一晶体管和第一电容；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
所述第一晶体管的栅极与所述第一选通控制线电连接，所述第一晶体管的第一极与所 述数据输出端电连接，所述第一晶体管的第二极与所述控制节点电连接；
所述第一电容的第一端与所述控制节点电连接，所述第一电容的第二端与直流电压端电连接。
可选的，所述第二开关电路包括第二晶体管；
所述第二晶体管的栅极与所述第二选通控制线电连接，所述第二晶体管的第一极与所述数据输出端电连接，所述第二晶体管的第二极与所述数据线电连接。
可选的，所述扫描信号生成电路包括输出控制电路和输出电路；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
所述输出控制电路分别与所述控制节点、第一电压端、第二电压端、输出控制端和扫描输出端电连接，用于在所述控制节点的电位的控制下，控制所述输出控制端与所述第一电压端之间连通或断开，在所述扫描输出端提供的信号的控制下，控制所述输出控制端与所述第二电压端之间连通或断开；
所述输出电路分别与控制端、扫描输出端、所述输出控制端、所述第一电压端和所述第二电压端电连接，用于在所述控制端提供的控制信号的控制下，控制所述扫描输出端与所述第一电压端之间连通或断开，在所述输出控制端的电位的控制下，控制所述扫描输出端与所述第二电压端之间连通或断开。
可选的，所述扫描输出端为所述扫描信号输出端；或者，
所述扫描信号生成电路还包括反相电路；所述反相电路的输入端与所述扫描输出端电连接，所述反相电路的输出端与所述扫描信号输出端电连接，所述反相电路用于对其输入端接入的电压信号进行反相，得到反相电压信号，并通过所述反相电路的输出端输出所述反相电压信号。
可选的，所述输出控制电路包括第三晶体管和第四晶体管；
所述第三晶体管的栅极与所述控制节点电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述输出控制端电连接；
所述第四晶体管的栅极与扫描输出端电连接，所述第四晶体管的第一极与所述输出控制端电连接，所述第四晶体管的第二极与所述第二电压端电连接；
所述输出电路包括第五晶体管、第六晶体管和第二电容；
所述第五晶体管的栅极与所述控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述扫描输出端电连接；
所述第六晶体管的栅极与所述输出控制端电连接，所述第六晶体管的第一极与所述扫描输出端电连接，所述第六晶体管的第二极与所述第二电压端电连接；
所述第二电容的第一端与所述控制端电连接，所述第二电容的第二端与所述第二电压端电连接。
本公开实施例提供一种驱动方法，应用于上述的驱动电路，其特征在于，所述驱动方法包括：在两帧显示时间之间的空白时间段中的至少部分时间，
第一开关电路在第一选通控制信号的控制下，控制将源极驱动器的数据输出端提供的数据信号写入所述扫描信号生成电路；
扫描信号生成电路根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号至显示面板的相应列扫描线。
可选的，所述驱动电路还包括第二开关电路；所述驱动方法还包括：
在一帧显示时间中的数据写入时间段，第二开关电路在第二选通控制信号的控制下，控制所述源极驱动器的数据输出端与所述显示面板的相应列数据线之间连通。
本公开实施例提供一种像素电路，包括发光元件、发光驱动电路和控制电路；
所述发光驱动电路分别与第一节点和所述发光元件的第一极电连接，用于在所述第一节点的电位的控制下，产生驱动所述发光元件的驱动电流；所述发光元件的第二极与第三电压端电连接；
所述控制电路分别与第一栅线、扫描线、所述第一节点和所述发光元件的第一极电连接，用于在所述第一栅线提供的第一栅极驱动信号和所述扫描线提供的扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
可选的，所述控制电路包括第一控制电路和第二控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一控制电路分别与所述第一栅线、所述第一节点和中间节点电连接，所述第一控制电路用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第一节点与所述中间节点之间连通或断开；
所述第二控制电路分别与扫描线、所述中间节点和所述第三节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第三节点之间连通或断开。
可选的，所述控制电路包括第一控制电路和第二控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一控制电路分别与所述第一栅线、所述第三节点和中间节点电连接，用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第三节点与所述中间节点之间连通或断开；
所述第二控制电路分别与所述扫描线、所述中间节点和所述第一节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第一节点之间连通或断开。
可选的，本公开至少一实施例所述的像素电路还包括第一初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第二节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提 供的第一初始电压写入所述第二节点。
可选的，本公开至少一实施例所述的像素电路还包括第二初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第三节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第三节点。
可选的，本公开至少一实施例所述的像素电路还包括数据写入电路、第一发光控制电路、第二发光控制电路和储能电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述数据写入电路分别与第二栅线、数据线和所述第二节点电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第一发光控制电路分别与发光控制线、电源电压端和所述第二节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通或断开；
所述第二发光控制电路分别与所述发光控制线、所述第三节点和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极电连接；
所述储能电路与所述第一节点电连接，用于储存电能。
可选的，本公开至少一实施例所述的像素电路还包括第三初始化电路；
所述第三初始化电路分别与第一初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
可选的，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述第一节点电连接，所述第一控制晶体管的第二极与所述中间节点电连接；
所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述中间节点电连接，所述第二控制晶体管的第二极与所述第三节点电连接。
可选的，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述中间节点电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述第一节点电连接，所述第二控制晶体管的第二极与所述中间节点电连接。
可选的，所述第一初始化电路包括第一初始化晶体管；
所述第一初始化晶体管的栅极与所述第一初始控制端电连接，所述第一初始化晶体管的第一极与所述第一初始电压端电连接，所述第一初始化晶体管的第二极与所述第二节点电连接。
可选的，所述第二初始化电路包括第二初始化晶体管；
所述第二初始化晶体管的栅极与所述第二初始控制端电连接，所述第二初始化晶体管的第一极与所述第二初始电压端电连接，所述第二初始化晶体管的第二极与所述第三节点电连接。
可选的，所述数据写入电路包括写入晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第二发光控制电路包括第二发光控制晶体管；所述发光驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述写入晶体管的栅极与所述第二栅线电连接，所述写入晶体管的第一极与所述数据线电连接，所述写入晶体管的第二极与所述第二节点电连接；
所述第一发光控制晶体管的栅极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述电源电压端电连接，所述第一发光控制晶体管的第二极与所述第二节点电连接；
所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述第三节点电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一极电连接；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与电源电压端电连接。
可选的，所述第三初始化电路包括第三初始化晶体管；
所述第三初始化晶体管的栅极与所述第一初始控制端电连接，所述第三初始化晶体管的第一极与所述第三初始电压端电连接，所述第三初始化晶体管的第二极与所述发光元件的第一极电连接。
本公开实施例提供一种像素驱动方法，应用于上述的像素电路，所述像素驱动方法包括：
发光驱动电路在第一节点的电位的控制下，产生驱动发光元件的驱动电流；
控制电路在第一栅极驱动信号和扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
可选的，所述像素电路包括第一初始化电路，发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和发光元件的第一极电连接；显示周期包括先后设置的第一初始化时间段和第二初始化时间段；所述像素驱动方法包括：
在所述第一初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与第三节点之间连通；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
在所述第二初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与所述第三节点之间断开；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入所述第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通。
本公开实施例提供一种显示面板，包括源极驱动器和上述的驱动电路；
所述源极驱动器包括数据输出端。
可选的，本公开实施例所述的显示面板包括多列扫描线；
所述驱动电路中的扫描信号生成电路中的扫描信号输出端与所述扫描线电连接。
可选的，所述显示面板包括多列数据线；
所述数据输出端直接与数据线电连接；或者，所述驱动电路包括第二开关电路，所述第二开关电路在第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开。
可选的，所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第一侧边；或者，
所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第二侧边，所述第一侧边与所述第二侧边为相对的侧边。
可选的，本公开至少一实施例所述的显示面板还包括上述的像素电路。
本公开实施例还提供一种显示装置，包括上述的显示面板。
附图说明
图1是本公开至少一实施例所述的驱动电路的结构图；
图2是本公开至少一实施例所述的驱动电路的电路图；
图3是本公开至少一实施例所述的驱动电路的电路图；
图4是本公开至少一实施例所述的驱动电路的电路图；
图5是本公开至少一实施例所述的驱动电路的电路图；
图6A是本公开至少一实施例所述的驱动电路的电路图；
图6B是本公开至少一实施例所述的驱动电路的电路图；
图7是本公开至少一实施例所述的驱动电路的电路图；
图8是本公开至少一实施例所述的驱动电路的电路图；
图9是本公开至少一实施例所述的驱动电路的结构图；
图10是本公开至少一实施例所述的驱动电路的结构图；
图11是本公开至少一实施例所述的驱动电路的电路图；
图12是图11所示的驱动电路的至少一实施例的工作时序图；
图13是本公开至少一实施例所述的驱动电路的电路图；
图14是图13所示的驱动电路的至少一实施例的仿真工作时序图；
图15是本公开至少一实施例所述的像素电路的结构图；
图16是本公开至少一实施例所述的像素电路的结构图；
图17是本公开至少一实施例所述的像素电路的结构图；
图18是本公开至少一实施例所述的像素电路的结构图；
图19是本公开至少一实施例所述的像素电路的结构图；
图20是本公开至少一实施例所述的像素电路的电路图；
图21A是图20所示的像素电路的至少一实施例的工作时序图；
图21B是图20所示的像素电路的至少一实施例的工作时序图；
图22是本公开至少一实施例所述的像素电路的电路图；
图23是本公开至少一实施例所述的像素电路的电路图；
图24是本公开至少一实施例所述的像素电路的电路图；
图25是本公开至少一实施例所述的显示面板的结构图；
图26是本公开至少一实施例所述的显示面板的结构图；
图27是本公开至少一实施例所述的显示面板的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的驱动电路包括第一开关电路和扫描信号生成电路；
所述第一开关电路与第一选通控制线、源极驱动器的数据输出端和所述扫描信号生成电路电连接，用于在所述第一选通控制线提供的第一选通控制信号的控制下，控制将所述数据输出端提供的数据信号写入所述扫描信号生成电路；
所述扫描信号生成电路用于根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号。
在本公开实施例中，所述驱动电路可以包括第一开关电路和扫描信号生成电路，在两帧显示时间之间的空白时间段中的至少部分时间，第一开关电路在第一选通控制信号的控制下，控制将数据输出端提供的数据信号写入扫描信号生成电路；所述扫描信号生成电路根据所述数据信号生成扫描信号，并将扫描信号提供至显示面板包括的一列扫描线，从而根据所述扫描信号，控制在下一帧显示时间内，该列扫描线控制的晶体管导通或关断。
在具体实施时，当在下一帧显示时间内，该列扫描线控制的晶体管关断时，该晶体管所在的像素电路不进行数据电压写入，可以通过低漏电的晶体管维持在原有的显示亮度，避免对该像素电路的反复刷写造成的一部分功耗的浪费；
当在下一帧显示时间内，该列扫描线控制的晶体管打开时，该晶体管所在的像素电路进行数据电压写入，正常进行画面的刷新。
相关的OLED(有机发光二极管)显示器在更新画面时，需要在一帧显示时间内，对全部像素电路进行初始化和数据电压写入。而在某些特殊画面下(如AOD(全天候熄屏显示)画面、静态画面或较少更新的画面)，整屏绝大部分像素电路的数据电压不需要更新，可以通过低漏电的LTPO(低温多晶氧化物)TFT(薄膜晶体管)维持在原有的显示亮度，对这些像素电路的反复刷写造成了数据线功耗的浪费。
基于此，本公开实施例通过设计一种驱动电路，可以在两帧显示时间之间的空白时间段中的至少部分时间，控制一列扫描线上的扫描信号，以根据该扫描信号，控制在接下来的一帧显示时间，该扫描线控制的晶体管导通或关断，来控制是否对相应的像素电路进行数据电压刷新，实现屏幕局部画面的更新，而其余画面则不需要多次充放电，进而进一步降低OLED显示的功耗，或通过显示画面局部更新实现超低功耗。
如图1所示，本公开实施例所述的驱动电路包括第一开关电路11和扫描信号生成电路SD；
所述第一开关电路11与第一选通控制线SW1、源极驱动器的数据输出端S0和所述扫描信号生成电路SD电连接，用于在所述第一选通控制线SW1提供的第一选通控制信号的控制下，控制将所述数据输出端S0提供的数据信号写入所述扫描信号生成电路SD；
所述扫描信号生成电路SD用于根据所述数据信号生成扫描信号，并通过扫描信号输出端CG输出所述扫描信号。
在本公开至少一实施例中，所述第一开关电路11可以与所述源极驱动器的一个数据输出端电连接。
可选的，所述第一开关电路包括第一晶体管和第一电容；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
所述第一晶体管的栅极与所述第一选通控制线电连接，所述第一晶体管的第一极与所述数据输出端电连接，所述第一晶体管的第二极与所述控制节点电连接；
所述第一电容的第一端与所述控制节点电连接，所述第一电容的第二端与直流电压端电连接。
在本公开至少一实施例中，所述数据输出端可以直接与数据线电连接，所述扫描信号输出端可以与扫描线电连接，但不以此为限。
如图2所示，标号为P11的为第一行第一列像素电路，标号为P21的为第二行第一列像素电路，标号为P31的为第三行第一列像素电路，标号为P41的为第四行第一列像素电路；
标号为DL的为数据线，标号为CG的为扫描线，标号为NG1的为第一行第一栅线，标号为NG2的为第一行第一栅线，标号为NG3的为第三行第一栅线，标号为NG4的为第四行第一栅线；
本公开至少一实施例所述的驱动电路包括第一开关电路和扫描信号生成电路SD；
所述第一开关电路包括第一晶体管T1；
所述第一晶体管T1的栅极与所述第一选通控制线SW1电连接，所述第一晶体管T1的源极与数据线DL连接，所述第一晶体管的第二极与所述扫描信号生成电路SD电连接；
DL与源极驱动器的数据输出端S0电连接；
所述扫描信号生成电路SD用于根据所述数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL。
在图2所示的至少一实施例中，T1为p型晶体管，在两帧显示时间之间，SW1提供低电压信号，以使得T1打开。
图3所示的至少一实施例与图2所示的至少一实施例的区别在于：T1为n型晶体管，在两帧显示时间之间，SW1提供高电压信号，以使得T1打开。
本公开至少一实施例所述的驱动电路还包括第二开关电路；
所述第二开关电路分别与第二选通控制线、所述数据输出端和显示面板包括的数据线电连接，用于在所述第二选通控制线提供的第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开；
所述第一选通控制线与所述第二选通控制线为同一选通控制线，或者，所述第一选通控制线与所述第二选通控制线不同。
在具体实施时，所述驱动电路还可以包括第二开关电路，第二开关电路在第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开。
可选的，所述第二开关电路包括第二晶体管；
所述第二晶体管的栅极与所述第二选通控制线电连接，所述第二晶体管的第一极与所述数据输出端电连接，所述第二晶体管的第二极与所述数据线电连接。
如图4所示，标号为P11的为第一行第一列像素电路，标号为P21的为第二行第一列像素电路，标号为P31的为第三行第一列像素电路，标号为P41的为第四行第一列像素电路；
标号为DL的为数据线，标号为CG的为扫描线，标号为NG1的为第一行第一栅线，标号为NG2的为第一行第一栅线，标号为NG1的为第三行第一栅线，标号为NG4的为 第四行第一栅线；
本公开至少一实施例所述的驱动电路包括第一开关电路、第二开关电路和扫描信号生成电路SD；
所述第一开关电路可以包括第一晶体管T1；
T1的栅极与第一选通控制线SW1电连接，T1的源极与源极驱动器的数据输出端S0电连接，T1的漏极与所述扫描信号生成电路SD电连接；
所述第二开关电路13包括第二晶体管T2；
T2的栅极与第一选通控制线SW1电连接，T2的源极与数据线DL电连接，T2的漏极与源极驱动器的数据输出端S0电连接；
所述扫描信号生成电路SD用于根据所述数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL。
在图4所示的至少一实施例中，T1为p型晶体管，T2为n型晶体管。
本公开如图4所示的至少一实施例在工作时，在两帧显示时间之间的空白时间段中的至少部分时间，SW1提供低电压信号，T1导通，以将数据输出端S0提供的数据信号写入所述扫描信号生成电路SD，所述扫描信号生成电路SD用于根据所述数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL；
在一帧显示时间内，SW1提供高电压信号，T2打开，以控制所述数据输出端S0与数据线DL之间连通。
图5所示的至少一实施例与图4所示的至少一实施例的区别在于：T1为n型晶体管，T2为p型晶体管。
本公开如图5所示的至少一实施例在工作时，在两帧显示时间之间的空白时间段中的至少部分时间，SW1提供高电压信号，T1导通，以将数据输出端S0提供的数据信号写入所述扫描信号生成电路SD，所述扫描信号生成电路SD用于根据数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至第一列扫描线CG1；
在一帧显示时间内，SW1提供低电压信号，T2打开，以控制所述数据输出端S0与数据线DL之间连通。
在图4、图5所示的至少一实施例中，第一选通控制线与第二选通控制线为同一选通控制线。
如图6A所示，标号为P11的为第一行第一列像素电路，标号为P21的为第二行第一列像素电路，标号为P31的为第三行第一列像素电路，标号为P41的为第四行第一列像素电路；
标号为DL的为数据线，标号为CG的为扫描线，标号为NG1的为第一行第一栅线，标号为NG2的为第一行第一栅线，标号为NG1的为第三行第一栅线，标号为NG4的为第四行第一栅线；
本公开至少一实施例所述的驱动电路包括第一开关电路、第二开关电路和扫描信号生 成电路SD；
所述第一开关电路可以包括第一晶体管T1；
T1的栅极与第一选通控制线SW1电连接，T1的源极与数据线DL电连接，T1的漏极与所述扫描信号生成电路SD电连接；
所述第二开关电路13包括第二晶体管T2；
T2的栅极与第二选通控制线SW2电连接，T2的源极与数据线DL电连接，T2的漏极与源极驱动器的数据输出端S0电连接；
所述扫描信号生成电路SD用于根据数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL。
在图6A所示的至少一实施例中，第一选通控制线与第二选通控制线为不同的选通控制线。
在图6A所示的至少一实施例中，T1为p型晶体管，T2为p型晶体管。
本公开如图6A所示的至少一实施例在工作时，在两帧显示时间之间的空白时间段中的至少部分时间，SW1提供低电压信号，SW2提供高电压信号，T1导通，以将数据输出端S0提供的数据信号写入所述扫描信号生成电路SD，所述扫描信号生成电路SD用于根据数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL；
在一帧显示时间内，SW2提供低电压信号，SW1提供高电压信号，T2打开，以控制所述数据输出端S0与数据线DL之间连通。
图6B所示的至少一实施例与图6A所示的至少一实施例的区别在于：T1为n型晶体管，T2为n型晶体管。
本公开如图6B所示的至少一实施例在工作时，在两帧显示时间之间的空白时间段中的至少部分时间，SW1提供高电压信号，SW2提供低电压信号，T1导通，以将数据输出端S0提供的数据信号写入所述扫描信号生成电路SD，所述扫描信号生成电路SD用于根据数据输出端S0提供的数据信号生成扫描信号，并将所述扫描信号提供至扫描线CGL；
在一帧显示时间内，SW2提供高电压信号，SW1提供低电压信号，T2打开，以控制所述数据输出端S0与数据线DL之间连通。
在图2至图6B所示的至少一实施例中，扫描信号生成电路和源极驱动器设置于显示面板的同一侧边。在实际操作时，所述扫描信号生成电路可以与源极驱动器设置于显示面板的相对的侧边。
图7所示的至少一实施例与图2所示的至少一实施例的区别在于，T1设置于扫描信号生成电路设置于显示面板的上侧边。
图8所示的至少一实施例与图3所示的至少一实施例的区别在于，T1设置于扫描信号生成电路设置于显示面板的上侧边。
在本公开至少一实施例中，所述扫描信号生成电路包括输出控制电路和输出电路；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
所述输出控制电路分别与所述控制节点、第一电压端、第二电压端、输出控制端和扫描输出端电连接，用于在所述控制节点的电位的控制下，控制所述输出控制端与所述第一电压端之间连通或断开，在所述扫描输出端提供的信号的控制下，控制所述输出控制端与所述第二电压端之间连通或断开；
所述输出电路分别与控制端、扫描输出端、所述输出控制端、所述第一电压端和所述第二电压端电连接，用于在所述控制端提供的控制信号的控制下，控制所述扫描输出端与所述第一电压端之间连通或断开，在所述输出控制端的电位的控制下，控制所述扫描输出端与所述第二电压端之间连通或断开。
在具体实施时，所述扫描信号生成电路可以包括输出控制电路和输出电路，所述输出控制电路在所述控制节点的电位的控制下，控制所述输出控制端与所述第一电压端之间连通或断开，在所述扫描输出端提供的信号的控制下，控制所述输出控制端与所述第二电压端之间连通或断开；所述输出电路在所述控制端提供的控制信号的控制下，控制所述扫描输出端与所述第一电压端之间连通或断开，在所述输出控制端的电位的控制下，控制所述扫描输出端与所述第二电压端之间连通或断开。
可选的，所述扫描输出端为所述扫描信号输出端；或者，
所述扫描信号生成电路还包括反相电路；所述反相电路的输入端与所述扫描输出端电连接，所述反相电路的输出端与所述扫描信号输出端电连接，所述反相电路用于对其输入端接入的电压信号进行反相，得到反相电压信号，并通过所述反相电路的输出端输出所述反相电压信号。
如图9所示，第一开关电路11分别与第一选通控制线SW1、所述源极驱动器的数据输出端S0和控制节点NC电连接，用于在所述第一选通控制线SW1提供的第一选通控制信号的控制下，控制所述数据输出端S0与所述控制节点NC之间连通或断开；
所述扫描信号生成电路包括输出控制电路71和输出电路72；
所述输出控制电路71分别与所述控制节点NC、第一电压端V1、第二电压端V2、输出控制端OE和扫描信号输出端CG电连接，用于在所述控制节点NC的电位的控制下，控制所述输出控制端OE与所述第一电压端V1之间连通或断开，在所述扫描信号输出端CG提供的信号的控制下，控制所述输出控制端OE与所述第二电压端V2之间连通或断开；
所述输出电路72分别与控制端VHRD、输出控制端OE、扫描信号输出端CG、所述第一电压端V1和所述第二电压端V2电连接，用于在所述控制端VHRD提供的控制信号的电位的控制下，控制所述扫描信号输出端CG与所述第一电压端V1之间连通或断开，在所述输出控制端OE的电位的控制下，控制所述扫描信号输出端CG与所述第二电压端V2之间连通或断开。
在图9所示的扫描信号生成电路的至少一实施例中，所述扫描输出端可以为扫描信号输出端CG，所述第一电压端可以为高电压端，所述第二电压端可以为低电压端，但不以此为限。
如图10所示，第一开关电路11分别与第一选通控制线SW1、所述源极驱动器的数据输出端S0和控制节点NC电连接，用于在所述第一选通控制线SW1提供的第一选通控制信号的控制下，控制所述数据输出端S0与所述控制节点NC之间连通或断开；
所述扫描信号生成电路包括输出控制电路71和输出电路72；
所述输出控制电路71分别与所述控制节点NC、第一电压端V1、第二电压端V2、输出控制端OE和扫描输出端OP电连接，用于在所述控制节点NC1的电位的控制下，控制所述输出控制端OE与所述第一电压端V1之间连通或断开，在所述扫描输出端OP提供的信号的控制下，控制所述输出控制端OE与所述第二电压端V2之间连通或断开；
所述输出电路72分别与所述控制端VHRD、扫描输出端OP、所述输出控制端OE、所述第一电压端V1和所述第二电压端V2电连接，用于在所述控制端VHRD的电位的控制下，控制所述扫描输出端OP与所述第一电压端V1之间连通或断开，在所述输出控制端OE的电位的控制下，控制所述扫描输出端OP与所述第二电压端V2之间连通或断开；
所述扫描信号生成电路还包括反相电路73；
所述反相电路73的输入端与所述扫描输出端OP电连接，所述反相电路73的输出端与所述扫描信号输出端CG电连接，所述反相电路73用于对其输入端接入的电压信号进行反相，得到反相电压信号，并通过所述反相电路73的输出端输出所述反相电压信号。
可选的，所述输出控制电路包括第三晶体管和第四晶体管；
所述第三晶体管的栅极与所述控制节点电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述输出控制端电连接；
所述第四晶体管的栅极与扫描输出端电连接，所述第四晶体管的第一极与所述输出控制端电连接，所述第四晶体管的第二极与所述第二电压端电连接；
所述输出电路包括第五晶体管、第六晶体管和第二电容；
所述第五晶体管的栅极与所述控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述扫描输出端电连接；
所述第六晶体管的栅极与所述输出控制端电连接，所述第六晶体管的第一极与所述扫描输出端电连接，所述第六晶体管的第二极与所述第二电压端电连接；
所述第二电容的第一端与所述控制端电连接，所述第二电容的第二端与所述第二电压端电连接。
如图11所示，在图9所示的至少一实施例的基础上，
所述第一开关电路包括第一晶体管T1和第一电容C1；
所述第一晶体管T1的栅极与所述第一选通控制线SW1电连接，所述第一晶体管的源极与所述数据输出端S0电连接，所述第一晶体管T1的漏极与所述控制节点NC电连接；
所述第一电容C1的第一端与控制节点NC电连接，所述第一电容C1的第二端与所述低电压端VGL电连接；
所述输出控制电路包括第三晶体管T3和第四晶体管T4；
所述第三晶体管T3的栅极与所述控制节点NC电连接，所述第三晶体管T3的源极与高电压端VGH电连接，所述第三晶体管T3的漏极与所述输出控制端OE电连接；
所述第四晶体管T4的栅极与所述扫描信号输出端CG电连接，所述第四晶体管T4的源极与所述输出控制端OE电连接，所述第四晶体管T4的漏极与所述低电压端VGL电连接；
所述输出电路包括第五晶体管T5、第六晶体管T6和第二电容C2；
所述第五晶体管T5的栅极与控制端VHRD电连接，所述第五晶体管T5的源极与高电压端VGH电连接，所述第五晶体管T5的漏极与所述扫描信号输出端CG电连接；
所述第六晶体管T6的栅极与所述输出控制端OE电连接，所述第六晶体管T6的源极与所述扫描信号输出端CG电连接，所述第六晶体管T6的漏极与低电压端VGL电连接；
所述第二电容C2的第一端与所述控制端VHRD电连接，所述第二电容C2的第二端与所述低电压端VGL电连接。
在图11所示的扫描信号生成电路的至少一实施例中，所述控制电压端为第二电压端，第一电压端为高电压端，第二电压端为低电压端，但不以此为限。
在图11所示的扫描信号生成电路的至少一实施例中，S0可以与相应列数据线DL电连接。
在图11所示的至少一实施例中，T1为p型晶体管，T3为p型晶体管，T4为n型晶体管，T5为p型晶体管，T6为n型晶体管。
在图11所示的至少一实施例中，所述控制端VHRD用于3V电压信号，所述高电压端VGH可以用于提供8V电压信号，所述低电压端VGL可以用于提供-8V电压信号。
在本公开至少一实施例中，所述控制端VHRD提供的控制信号的电压值可以大于或的等于3V而小于或等于4V，所述高电压端VGH提供的高电压信号的电压值可以大于或等于7V而小于或等于9V，所述低电压端VGL提供的低电压信号的电压值可以大于或等于-9V而小于或等于-7V，但不以此为限。
如图12所示，图11所示的至少一实施例在工作时，标号为TB1的为第一空白时间段，标号为TB2的为第二控制时间段，标号为TX1的为第一数据写入时间段，标号为TX2的为第二数据写入时间段。
在第一空白时间段TB1中的部分时间，SW1提供低电压信号，T1打开，S0提供高电压信号，数据线DL接入高电压信号，NC的电位为高电压，T5打开，CG与VGH之间连通，CG的电位为高电压，T4打开，以使得OE与VGL之间连通，OE输出低电压信号；
在第一数据写入时间段TX1，CG的电位维持为高电压；
在第二空白时间段TB2中的部分时间，SW1提供低电压信号，T1打开，S0提供低电压信号，DL接入低电压信号，NC的电位为低电压，T3打开，OE与VGH之间连通，OE的电位为高电压，T6打开，CG输出低电压信号；
在第二数据写入时间段TX2，CG的电位维持为低电压。
图11所示的至少一实施例在工作时，在第一空白时间段TB1中的部分时间，DL接入的高电压信号的电压值可以为7V；
在第二空白时间段TB2中的部分时间，DL接入的低电压信号的电压值可以为0V；
但不以此为限。
本公开图11所示的至少一实施例在工作时，在第二空白时间段TB2中的部分时间，T6的打开程度比T5的打开程度高，因此CG输出低电压信号。
如图13所示，在图10所示的至少一实施例的基础上，
所述第一开关电路包括第一晶体管T1和第一电容C1；
所述第一晶体管T1的栅极与所述第一选通控制线SW1电连接，所述第一晶体管的源极与所述数据输出端S0电连接，所述第一晶体管T1的漏极与所述控制节点NC电连接；
所述第一电容C1的第一端与控制节点NC电连接，所述第一电容C1的第二端与所述低电压端VGL电连接；
所述输出控制电路包括第三晶体管T3和第四晶体管T4；
所述第三晶体管T3的栅极与所述控制节点NC电连接，所述第三晶体管T3的源极与高电压端VGH电连接，所述第三晶体管T3的漏极与所述输出控制端OE电连接；
所述第四晶体管T4的栅极与所述控制节点NC电连接，所述第四晶体管T4的源极与所述输出控制端OE电连接，所述第四晶体管T4的漏极与所述低电压端VGL电连接；
所述输出电路包括第五晶体管T5和第六晶体管T6；
所述第五晶体管T5的栅极与控制端VHRD电连接，所述第五晶体管T5的源极与高电压端VGH电连接，所述第五晶体管T5的漏极与所述扫描输出端OP电连接；
所述第六晶体管T6的栅极与所述输出控制端OE电连接，所述第六晶体管T6的源极与所述扫描输出端OP电连接，所述第六晶体管T6的漏极与低电压端VGL电连接；
所述反相电路包括反相器IV；
所述反相器IV的输入端与所述扫描输出端OP电连接，所述反相器IV的输出端与所述扫描信号输出端CG电连接，所述反相器IV用于对其输入端接入的电压信号进行反相，得到反相电压信号，并通过所述反相器IV的输出端输出所述反相电压信号。
在图13所示的扫描信号生成电路的至少一实施例中，第一电压端为高电压端，第二电压端为低电压端，但不以此为限。
在图13所示的扫描信号生成电路的至少一实施例中，S0可以与数据线DL电连接。
在图13所示的至少一实施例中，所述控制端VHRD用于3V电压信号，所述高电压端VGH可以用于提供8V电压信号，所述低电压端VGL可以用于提供-8V电压信号。
图13所示的扫描信号生成电路的至少一实施例在工作时，第一空白时间段、第一数据写入时间段、第二空白时间段和第二数据写入时间段可以先后设置；
在第一空白时间段中的至少部分时间，SW1提供低电压信号，T1打开，S0提供高电压信号，DL接入高电压信号，NC的电位为高电压，T5打开，OP与VGH之间连通，OP 的电位为高电压，T4打开，以使得OE与VGL之间连通，OE输出低电压信号；CG输出低电压信号；
在第一数据写入时间段，CG的电位维持为低电压；
在第二空白时间段中的至少部分时间，SW1提供低电压信号，T1打开，S0提供低电压信号，DL接入低电压信号，NC的电位为低电压，T3打开，OE与VGH之间连通，OE的电位为高电压，T6打开，OP输出低电压信号；CG输出高电压信号；
在第二数据写入时间段，CG的电位维持为高电压。
图13所示的至少一实施例在工作时，在第一空白时间段中的部分时间，DL接入的高电压信号的电压值可以为7V；
在第二空白时间段TB2中的部分时间，DL接入的低电压信号的电压值可以为0V；
但不以此为限。
本公开图13所示的至少一实施例在工作时，在第二空白时间段中的部分时间，T6的打开程度比T5的打开程度高，因此OP输出低电压信号。
图14是图13所示的扫描信号生成电路的至少一实施例的仿真工作时序图。
本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：在两帧显示时间之间的空白时间段中的至少部分时间，
第一开关电路在第一选通控制信号的控制下，控制将源极驱动器的数据输出端提供的数据信号写入所述扫描信号生成电路；
扫描信号生成电路根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号至显示面板的相应列扫描线。
在本公开实施例所述的驱动方法中，在两帧显示时间之间的空白时间段中的至少部分时间；第一开关电路在第一选通控制信号的控制下，控制将源极驱动器的数据输出端提供的数据信号写入扫描信号生成电路；所述扫描信号生成电路根据所述数据输出端提供的数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号至显示面板的相应列扫描线。
在本公开至少一实施例中，所述驱动电路还包括第二开关电路；所述驱动方法还包括：
在一帧显示时间中的数据写入时间段，第二开关电路在第二选通控制信号的控制下，控制所述源极驱动器的数据输出端与所述显示面板的相应列数据线之间连通。
在具体实施时，所述驱动电路还可以包括第二开关电路，在一帧显示时间中的数据写入时间段，所述第二开关电路在第二选通控制信号的控制下，控制数据输出端与所述显示面板的相应列数据线之间连通，以向所述数据线提供数据电压。
本公开实施例所述的像素电路包括发光元件、发光驱动电路和控制电路；
所述发光驱动电路分别与第一节点和所述发光元件的第一极电连接，用于在所述第一节点的电位的控制下，产生驱动所述发光元件的驱动电流；所述发光元件的第二极与第三电压端电连接；
所述控制电路分别与第一栅线、扫描线、所述第一节点和所述发光元件的第一极电连接，用于在所述第一栅线提供的第一栅极驱动信号和所述扫描线提供的扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
在具体实施时，所述像素电路可以包括控制电路和发光驱动电路，发光驱动电路在第一节点的电位的控制下，产生驱动电流，控制电路在第一栅线提供的第一栅极驱动信号和扫描线提供的扫描信号的控制下，控制第一节点与发光元件的第一极之间连通或断开；所述驱动电流可以为驱动所述发光元件发光的电流。
在本公开至少一实施例中，所述第三电压端可以为低电平端，但不以此为限。
可选的，所述发光元件为有机发光二极管，所述发光元件的第一极为阳极，所述发光元件的第二极为阴极。
如图15所示，所述像素电路可以包括发光元件E0、控制电路201和发光驱动电路230；
所述发光驱动电路230分别与第一节点N1和所述发光元件E0的第一极电连接，用于在所述第一节点N1的电位的控制下，产生驱动所述发光元件E0的驱动电流；所述发光元件E0的第二极与第三电压端V3电连接；
所述控制电路201分别与第一栅线NG、扫描线CGL、所述第一节点N1和所述发光元件E0的第一极电连接，用于在所述第一栅线NG提供的第一栅极驱动信号和所述扫描线CGL提供的扫描信号的控制下，控制所述第一节点N1与所述发光元件E0的第一极之间连通或断开。
在本公开至少一实施例中，所述控制电路包括第一控制电路和第二控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一控制电路分别与所述第一栅线、所述第一节点和中间节点电连接，所述第一控制电路用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第一节点与所述中间节点之间连通或断开；
所述第二控制电路分别与扫描线、所述中间节点和所述第三节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第三节点之间连通或断开。
在具体实施时，所述控制电路可以包括第一控制电路和第二控制电路，第一控制电路在第一栅线提供的第一栅极驱动信号的控制下，控制所述第一节点与所述中间节点之间连通或断开，所述第二控制电路在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第三节点之间连通或断开。
如图16所示，在图15所示的像素电路的至少一实施例的基础上，所述控制电路包括第一控制电路241和第二控制电路242；所述发光驱动电路230的第一端与第二节点N2电连接，所述发光驱动电路230的第二端分别与第三节点N3和所述发光元件E0的第一极电连接；
所述第一控制电路241分别与第一栅线NG、所述第一节点N1和中间节点NZ电连 接，用于在所述第一栅线NG提供的第一栅极驱动信号的控制下，控制所述第一节点N1与所述中间节点NZ之间连通或断开；
所述第二控制电路242分别与扫描线CGL、所述中间节点NZ和所述第三节点N3电连接，用于在所述扫描线CGL提供的扫描信号的控制下，控制所述中间节点NZ与所述第三节点N3之间连通或断开。
在本公开至少一实施例中，所述控制电路包括第一控制电路和第二控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一控制电路分别与所述第一栅线、所述第三节点和中间节点电连接，用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第三节点与所述中间节点之间连通或断开；
所述第二控制电路分别与所述扫描线、所述中间节点和所述第一节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第一节点之间连通或断开。
在具体实施时，所述控制电路可以包括第一控制电路和第二控制电路，所述第一控制电路在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第三节点与所述中间节点之间连通或断开；所述第二控制电路在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第一节点之间连通或断开。
如图17所示，在图15所示的像素电路的至少一实施例的基础上，所述控制电路包括第一控制电路241和第二控制电路242；所述发光驱动电路230的第一端与第二节点N2电连接，所述发光驱动电路230的第二端分别与第三节点N3和所述发光元件E0的第一极电连接；
所述第一控制电路241分别与所述第一栅线NG、所述第三节点N3和中间节点NZ电连接，用于在所述第一栅线NG提供的第一栅极驱动信号的控制下，控制所述第三节点N3与所述中间节点NZ之间连通或断开；
所述第二控制电路242分别与所述扫描线CGL、所述中间节点NZ和所述第一节点N1电连接，用于在所述扫描线CGL提供的扫描信号的控制下，控制所述中间节点NZ与所述第一节点N1之间连通或断开。
本公开至少一实施例所述的像素电路还包括第一初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第二节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第二节点。
在具体实施时，显示周期可以包括先后设置的第一初始化时间段和第二初始化时间段；
在所述第一初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的 控制下，控制所述第一节点与所述第三节点之间连通；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入所述第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
在所述第二初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与所述第三节点之间断开；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入所述第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通。
本公开至少一实施例所述的像素电路在工作时，在第一初始化时间段，在数据写入之前，对第一节点、第二节点和第三节点的电位进行初始化，以减小后续充电差异，在第二初始化时间段，第一初始化电路将第一初始电压写入第二节点，发光驱动电路控制第二节点与第三节点之间连通，以使得所述发光驱动电路包括的驱动晶体管处于偏压状态，能够改善迟滞现象。
本公开至少一实施例所述的像素电路还包括第二初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第三节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第三节点。
在具体实施时，所述像素电路还可以包括第二初始化电路；
在设置于第一初始化时间段和第二初始化时间段之间的第三初始化时间段，在数据写入时间段之前，第二初始化电路在第二初始控制信号的控制下，将第二初始电压写入所述第三节点，以使得在所述数据写入时间段开始时，所述发光驱动电路包括的驱动晶体管能够导通，便于进行数据电压写入和阈值电压补偿。
在本公开至少一实施例中，所述像素电路还包括数据写入电路、第一发光控制电路、第二发光控制电路和储能电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
所述数据写入电路分别与第二栅线、数据线和所述第二节点电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
所述第一发光控制电路分别与发光控制线、电源电压端和所述第二节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通或断开；
所述第二发光控制电路分别与所述发光控制线、所述第三节点和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极电连接；
所述储能电路与所述第一节点电连接，用于储存电能。
在具体实施时，所述像素电路还可以包括数据写入电路、第一发光控制电路、第二发光控制电路和储能电路；所述数据写入电路用于将数据电压写入第二节点，第一发光控制电路和第二发光控制电路用于控制导通发光路径，储能电路用于储存电能。
本公开至少一实施例所述的像素电路还包括第三初始化电路；
所述第三初始化电路分别与第一初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
在具体实施时，所述像素电路还可以包括第三初始化电路，第三初始化电路在第一初始控制信号的控制下，将第三初始电压写入所述发光元件的第一极，以控制发光元件不发光，并清除发光元件的第一极残留的电荷。
如图18所示，在图16所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一初始化电路231、第二初始化电路232、数据写入电路233、第一发光控制电路234、第二发光控制电路235、储能电路236和第三初始化电路237；所述发光元件E0的第二极与低电平端ELVSS电连接；
所述第一初始化电路231分别与第一初始控制端HR、第一初始电压端I1和所述第二节点N2电连接，用于在所述第一初始控制端HR提供的第一初始控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第二节点N2；
所述第二初始化电路232分别与第二初始控制端PR、第二初始电压端I2和所述第三节点N3电连接，用于在所述第二初始控制端PR提供的第二初始控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第三节点N3；
所述数据写入电路233分别与第二栅线PG、数据线DT和所述第二节点N2电连接，用于在所述第二栅线PG提供的第二栅极驱动信号的控制下，将所述数据线DT提供的数据电压Vdata写入所述第二节点N2；
所述第一发光控制电路234分别与发光控制线E1、电源电压端ELVDD和所述第二节点N2电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述电源电压端ELVDD与所述第二节点N2之间连通或断开；
所述第二发光控制电路235分别与所述发光控制线E1、所述第三节点N3和所述发光元件E0的第一极电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3与所述发光元件E0的第一极电连接，所述发光元件E0的第二极与第三电压端V3电连接；
所述储能电路236与所述第一节点N1电连接，用于储存电能；
所述第三初始化电路237分别与第一初始控制端HR、第三初始电压端I3和所述发光元件E0的第一极电连接，用于在所述第一初始控制端HR提供的第一初始控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压Vinit3写入所述发光元件E0的第一极。
在图18所示的像素电路的至少一实施例中，第三电压端为低电平端ELVSS。
如图19所示，在图17所示的像素电路的至少一实施例的基础上，本公开至少一实施例所述的像素电路还可以包括第一初始化电路231、第二初始化电路232、数据写入电路233、第一发光控制电路234、第二发光控制电路235、储能电路236和第三初始化电路237；所述发光元件E0的第二极与低电平端ELVSS电连接；
所述第一初始化电路231分别与第一初始控制端HR、第一初始电压端I1和所述第二节点N2电连接，用于在所述第一初始控制端HR提供的第一初始控制信号的控制下，将所述第一初始电压端I1提供的第一初始电压Vinit1写入所述第二节点N2；
所述第二初始化电路232分别与第二初始控制端PR、第二初始电压端I2和所述第三节点N3电连接，用于在所述第二初始控制端PR提供的第二初始控制信号的控制下，将所述第二初始电压端I2提供的第二初始电压Vinit2写入所述第三节点N3；
所述数据写入电路233分别与第二栅线PG、数据线DT和所述第二节点N2电连接，用于在所述第二栅线PG提供的第二栅极驱动信号的控制下，将所述数据线DT提供的数据电压Vdata写入所述第二节点N2；
所述第一发光控制电路234分别与发光控制线E1、电源电压端ELVDD和所述第二节点N2电连接，用于在所述发光控制线E1提供的发光控制信号的控制下，控制所述电源电压端ELVDD与所述第二节点N2之间连通或断开；
所述第二发光控制电路235分别与所述发光控制线E1、所述第三节点N3和所述发光元件E0的第一极电连接，用于在所述发光控制信号的控制下，控制所述第三节点N3与所述发光元件E0的第一极电连接，所述发光元件E0的第二极与第三电压端V3电连接；
所述储能电路236与所述第一节点N1电连接，用于储存电能；
所述第三初始化电路237分别与第一初始控制端HR、第三初始电压端I3和所述发光元件E0的第一极电连接，用于在所述第一初始控制端HR提供的第一初始控制信号的控制下，将所述第三初始电压端I3提供的第三初始电压Vinit3写入所述发光元件E0的第一极。
在图19所示的像素电路的至少一实施例中，第三电压端为低电平端ELVSS。
可选的，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述第一节点电连接，所述第一控制晶体管的第二极与所述中间节点电连接；
所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述中间节点电连接，所述第二控制晶体管的第二极与所述第三节点电连接。
可选的，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述中间节点电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述第一节点电连接，所述第二控制晶体管的第二极与所述中间节点电连接。
可选的，所述第一初始化电路包括第一初始化晶体管；
所述第一初始化晶体管的栅极与所述第一初始控制端电连接，所述第一初始化晶体管的第一极与所述第一初始电压端电连接，所述第一初始化晶体管的第二极与所述第二节点电连接。
可选的，所述第二初始化电路包括第二初始化晶体管；
所述第二初始化晶体管的栅极与所述第二初始控制端电连接，所述第二初始化晶体管的第一极与所述第二初始电压端电连接，所述第二初始化晶体管的第二极与所述第三节点电连接。
可选的，所述数据写入电路包括写入晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第二发光控制电路包括第二发光控制晶体管；所述发光驱动电路包括驱动晶体管，所述储能电路包括存储电容；
所述写入晶体管的栅极与所述第二栅线电连接，所述写入晶体管的第一极与所述数据线电连接，所述写入晶体管的第二极与所述第二节点电连接；
所述第一发光控制晶体管的栅极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述电源电压端电连接，所述第一发光控制晶体管的第二极与所述第二节点电连接；
所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述第三节点电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一极电连接；
所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与电源电压端电连接。
可选的，所述第三初始化电路包括第三初始化晶体管；
所述第三初始化晶体管的栅极与所述第一初始控制端电连接，所述第三初始化晶体管的第一极与所述第三初始电压端电连接，所述第三初始化晶体管的第二极与所述发光元件的第一极电连接。
如图20所示，在图18所示的像素电路的至少一实施例的基础上，所述第一控制电路包括第一控制晶体管M1，所述第二控制电路包括第二控制晶体管M2，所述发光驱动电路包括驱动晶体管M0；
所述第一控制晶体管M1的栅极与所述第一栅线NG电连接，所述第一控制晶体管M1的源极与第一节点N1电连接，所述第一控制晶体管M1的第二极与中间节点NZ电连接；
所述第二控制晶体管M2的栅极与所述扫描线CGL电连接，所述第二控制晶体管M2的源极与所述中间节点NZ电连接，所述第二控制晶体管M2的漏极与所述第三节点N3电连接；
驱动晶体管M0的栅极与第一节点N1电连接，驱动晶体管M0的源极与第二节点N2电连接，驱动晶体管M0的漏极与第三节点N3电连接；
所述第一初始化电路包括第一初始化晶体管M3；
所述第一初始化晶体管M3的栅极与所述第一初始控制端HR电连接，所述第一初始化晶体管M3的源极与所述第一初始电压端I1电连接，所述第一初始化晶体管M3的漏极与所述第二节点N2电连接；所述第一初始电压端I1用于提供第一初始电压Vinit1；
所述第二初始化电路包括第二初始化晶体管M4；
所述第二初始化晶体管M4的栅极与所述第二初始控制端PR电连接，所述第二初始化晶体管M4的源极与所述第二初始电压端I2电连接，所述第二初始化晶体管M4的漏极与所述第三节点N3电连接；所述第二初始电压端I2用于提供第二初始电压Vinit2；
所述数据写入电路包括写入晶体管M5，所述第一发光控制电路包括第一发光控制晶体管M6，所述第二发光控制电路包括第二发光控制晶体管M7；所述储能电路包括存储电容Cst；所述发光元件为有机发光二极管O1；
所述写入晶体管M5的栅极与所述第二栅线PG电连接，所述写入晶体管M5的源极与所述数据线DT电连接，所述写入晶体管M5的漏极与所述第二节点N2电连接；
所述第一发光控制晶体管M6的栅极与所述发光控制线E1电连接，所述第一发光控制晶体管M6的源极与所述电源电压端ELVDD电连接，所述第一发光控制晶体管M6的漏极与所述第二节点N2电连接；
所述第二发光控制晶体管M7的栅极与所述发光控制线E1电连接，所述第二发光控制晶体管M7的源极与所述第三节点N3电连接，所述第二发光控制晶体管M7的漏极与所述有机发光二极管O1的阳极电连接；
所述存储电容Cst的第一端与所述第一节点N1电连接，所述存储电容Cst的第二端与电源电压端ELVDD电连接；
所述第三初始化电路包括第三初始化晶体管M8；
所述第三初始化晶体管M8的栅极与所述第一初始控制端HR电连接，所述第三初始化晶体管M8的源极与所述第三初始电压端I3电连接，所述第三初始化晶体管M8的漏极与所述有机发光二极管O1的阳极电连接；
所述有机发光二极管O1的阴极与低电平端ELVSS电连接。
在图20所示的像素电路的至少一实施例中，M1和M2为n型晶体管，其他晶体管都为p型晶体管，但不以此为限。
如图21A所示，本公开图20所示的像素电路的至少一实施例在工作时，一帧显示时间可以包括先后设置的第一初始化时间段TI1、第三初始化时间段TI3、数据写入时间段 TX、第二初始化时间段TI2和发光时间段TF；在该帧显示时间，CG可以输出高电压信号，以控制M2导通；
在第一初始化时间段TI1、第三初始化时间段TI3和数据写入时间段TX，NG输出高电压信号，以控制M1导通；
在第一初始化时间段TI1、第三初始化时间段TI3、数据写入时间段TX和第二初始化时间段TI2，E1提供高电压信号，M6和M7关断；
在第二初始化时间段TI2和发光时间段TF，NG输出低电压信号，以控制M1关断；
在第一初始化时间段TI1，HR输出低电压信号，PR和PG都输出高电压信号，M3导通，以将第一初始电压端I1提供的第一初始电压Vinit1写入第二节点N2，M0导通，控制N2与N3之间连通，M1和M2导通，控制N1与N3之间连通，以对第一节点N1的电位、第二节点N2的电位和第三节点N3的电位进行初始化，以减小后续充电差异；
在第三初始化时间段TI3，PR输出低电压信号，HR和PG都输出高电压信号，M4导通，以将I2提供的第二初始电压Vinit2写入第三节点N3，以使得在数据写入时间段TX开始时，M0能够导通；
在数据写入时间段TX，HR和PR都输出高电压信号，PG输出低电压信号，M5导通，DT提供数据电压Vdata至N2；
在数据写入时间段TX开始时，M0导通，Vdata为Cst充电，直至第一节点N1的电位变为Vdata+Vth，M0关断；其中，Vth为M0的阈值电压；
在第二初始化时间段TI2，HR提供低电压信号，PR和PG都输出高电压信号，M3导通，以将Vinit1写入第二节点N2，M0导通，以使得N2与N3之间连通，此时，N1的电位为较小的正电压，N2的电位和N3的电位为较高的正电压，M0处于偏压状态，显示面板包括的所有驱动晶体管都处于偏压状态，能够改善迟滞现象。
在本公开至少一实施例中，Vinit1的电压值可以为正值，例如，Vinit1的电压值可以大于等于4V而小于等于7V；
Vinit2的电压值和Vinit3的电压值可以为负值，例如，Vinit2的电压值和Vinit3的电压值可以大于等于-5V而小于等于-3V；
但不以此为限。
本公开图20所示的像素电路的至少一实施例在工作时，在第一初始化时间段，将N1的电位、N2的电位和N3的电位都设置为基准电压，以使得在数据写入时间段，前一帧显示时间的数据电压不会影响本帧的数据电压的写入。
图20所示的像素电路的至少一实施例在工作时，在不需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出低电压信号，在接下来的一帧显示时间CG持续输出低电压信号，以控制M2关断，以不会进行数据电压写入，以维持显示画面，不刷新画面；
当需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的 至少部分时间，控制CG输出高电压信号，在接下来的一帧显示时间CG持续输出高电压信号，以控制M2开启，以在数据写入时间段进行数据电压写入，以刷新画面。
在图21A所示的工作时序图中，一帧显示时间可以为刷新帧。
如图21B所示，本公开图20所示的像素电路的至少一实施例在工作时，保持帧可以包括先后设置的保持初始时间段TBC和保持发光时间段TBF；
在保持初始时间段TBC，HR输出低电压信号，NG输出低电压信号，PR和PG都输出高电压信号，E1提供高电压信号，M1关断，以控制N1与N3之间断开，M6和M7关断，M5关断；M3和M8打开，I1提供第一初始电压Vinit1至第二节点N2，驱动晶体管M0导通，以控制N2与N3之间连通，对所述第二节点N2的电位和所述第三节点N3的电位进行初始化，改善迟滞现象；I3提供第三初始电压Vinit3至第三节点N3，并对O1的阳极的电位进行初始化，控制O1不发光，并清除O1的阳极残留的电荷；
在保持发光时间段TBF，E1提供低电压信号，HR提供高电压信号，NG输出低电压信号，PR和PG都输出高电压信号，M1、M2、M3、M4、M5和M8都关断，M6和M7打开，M0驱动O1发光。
图22所示的像素电路的至少一实施例与图20所示的像素电路的至少一实施例的区别在于：M2为p型晶体管。
图22所示的像素电路的至少一实施例在工作时，在不需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出高电压信号，在接下来的一帧显示时间CG持续输出低电压信号，以控制M2关断，以不会进行数据电压写入，以维持显示画面，不刷新画面；
当需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出低电压信号，在接下来的一帧显示时间CG持续输出高电压信号，以控制M2开启，以在数据写入时间段进行数据电压写入，以刷新画面。
图23所示的像素电路的至少一实施例与图20所示的像素电路的至少一实施例的区别在于：
所述第一控制晶体管M1的栅极与所述第一栅线NG电连接，所述第一控制晶体管M1的源极与所述中间节点NZ电连接，所述第一控制晶体管M1的漏极与所述第三节点N3电连接；
所述第二控制晶体管M2的栅极与所述扫描线CGL电连接，所述第二控制晶体管M2的源极与所述第一节点N1电连接，所述第二控制晶体管M2的漏极与所述中间节点NZ电连接。
在图23所示的像素电路的至少一实施例中，M1和M2都为n型晶体管。
图23所示的像素电路的至少一实施例在工作时，在不需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出低电压信号，在接下来的一帧显示时间CG持续输出低电压信号，以控制M2关断，以不会进行 数据电压写入，以维持显示画面，不刷新画面；
当需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出高电压信号，在接下来的一帧显示时间CG持续输出高电压信号，以控制M2开启，以在数据写入时间段进行数据电压写入，以刷新画面。
图24所示的像素电路的至少一实施例与图23所示的像素电路的至少一实施例的区别在于：M2为p型晶体管。
图24所示的像素电路的至少一实施例在工作时，在不需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出高电压信号，在接下来的一帧显示时间CG持续输出低电压信号，以控制M2关断，以不会进行数据电压写入，以维持显示画面，不刷新画面；
当需要对像素电路进行数据电压刷新时，需要在两帧显示时间之间的空白时间段中的至少部分时间，控制CG输出低电压信号，在接下来的一帧显示时间CG持续输出高电压信号，以控制M2开启，以在数据写入时间段进行数据电压写入，以刷新画面。
本公开实施例所述的像素驱动方法，应用于上述的像素电路，所述像素驱动方法包括：
发光驱动电路在第一节点的电位的控制下，产生驱动发光元件的驱动电流；
控制电路在第一栅极驱动信号和扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
在本公开至少一实施例中，所述像素电路包括第一初始化电路，发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和发光元件的第一极电连接；显示周期包括先后设置的第一初始化时间段和第二初始化时间段；所述像素驱动方法包括：
在所述第一初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与第三节点之间连通；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
在所述第二初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与所述第三节点之间断开；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入所述第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通。
本公开至少一实施例所述的显示面板包括源极驱动器和上述的驱动电路；
所述源极驱动器包括数据输出端。
本公开至少一实施例所述的显示面板包括多列扫描线；
所述驱动电路中的扫描信号生成电路中的扫描信号输出端与所述扫描线电连接。
在具体实施时，所述显示面板可以包括多列扫描线，扫描信号输出端与所述扫描线电连接，以提供扫描信号至所述扫描线。
可选的，所述显示面板包括多列数据线；
所述数据输出端直接与数据线电连接；或者，
所述驱动电路包括第二开关电路，所述第二开关电路在第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开。
在本公开至少一实施例中，所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第一侧边；或者，
所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第二侧边，所述第一侧边与所述第二侧边为相对的侧边。
例如，所述第一侧边可以为下侧边，所述第二侧边可以为上侧边，但不以此为限。
如图25所示，标号为A0的为显示面板的显示区域；
标号为DL1的为第一列数据线，标号为CG1的为第一列扫描线，标号为DL2的为第二列数据线，标号为CG2的为第二列扫描线，标号为DL3的为第三列数据线，标号为CG3的为第三列扫描线，标号为DL4的的为第四列数据线，标号为CG4的为第四列扫描线；标号为DLm的为第m列数据线，标号为CGm的为第m列扫描线；标号为DLM的为第M列数据线，标号为CGM的为第M列扫描线；
m和M都为正整数；标号为SI的为源极驱动器；
标号为S1的为源极驱动器SI的第一数据输出端，标号为S2的为源极驱动器SI的第二数据输出端，标号为S3的为源极驱动器SI的第三数据输出端，标号为S4的为源极驱动器SI的第四数据输出端，标号为Sm的为第m数据输出端，标号为SM的为第M数据输出端，标号为SW11的为第一个第一选通控制线，标号为SW21的为第二个第一选通控制线；
源极驱动器SI与SW11和SW21电连接，用于为SW11提供第一个第一选通控制信号，为SW21提供第二个第一选通控制信号；
在图25中，标号为X1的为第一选通单元，标号为X2的为第二选通单元，标号为X3的为第三选通单元，标号为X4的为第四选通单元，标号为Xm的为第m选通单元，标号为XM的为第M选通单元；
各选通单元包括第一开关电路和扫描信号生成电路；或者，各选通单元包括第一开关电路、第二开关电路和扫描信号生成电路。
如图25所示，第一选通单元X1分别与DL1和CG1电连接，第二选通单元X2分别与DL2和CG2电连接，第三选通单元X3分别与DL3和CG3电连接，第四选通单元X4分别与DL4和CG4电连接；第m选通单元Xm分别与DL和CGm电连接，第M选通单元XM分别与DLM和CGM电连接；
所述源极驱动器SI设置于A0下方，第一选通单元X1、第二选通单元X2、第三选通单元X3、第四选通单元X4、第m选通单元Xm和第M选通单元XM设置于A0下方。
图26所示的显示面板的至少一实施例与图25所示的显示面板的至少一实施例的区别 在于：第一选通单元X1、第二选通单元X2、第三选通单元X3、第四选通单元X4、第m选通单元Xm和第M选通单元XM设置于A0上方。
图27所示的显示面板的至少一实施例与图26所示的显示面板的至少一实施例的区别在于：
源极驱动器SI的各数据输出端集中于显示面板的中间，以实现下窄边框，图27所示的显示面板的至少一实施例结合FIP(Fanout In Pixel，像素中的扇出区域)实施例。本公开至少一实施例所述的显示面板还可以包括多行多列上述的像素电路。
在图25所示的显示面板的至少一实施例至图27所示的显示面板的至少一实施例中，各选通单元可以为本公开至少一实施例所述的驱动电路。
在本公开至少一实施例中，两列像素电路可以与同一列扫描线电连接。
本公开实施例提供了一种应用于OLED显示器的驱动方案，局部刷新像素电路配合源极驱动电路及驱动方案，可以通过HCT控制信号(所述HCT控制信号可以为在空白时间段，源极驱动器通过其数据输出端提供的数据信号)，实现屏幕局部画面的更新，而其余画面则不需要多次充放电，从而进一步降低OLED显示器的功耗，或通过显示画面局部更新实现超低功耗。
在本公开至少一实施例中，对于显示设备，当需要对部分画面进行更新时，如仅需要更新日期和时间部分。在行方向上，可以控制栅极驱动电路是否输出：在需要更新画面的行，正常输出第一栅极驱动信号，控制显示区域内的像素电路中的第一控制晶体管正常打开，进行数据更新；在不需要更新画面的行，始终保持第一栅极驱动信号的电位，以关闭所述第一控制晶体管，保证像素亮度不变，从而实现行方向上的局部刷新。在列方向上，可以通过控制列扫描线是否打开像素电路中的第二控制晶体管来实现：在两帧显示时间之间的空白时间段，源极驱动器输出HCT pulse(脉冲)，将不同的扫描信号写入列扫描线，如果当前列需要更新，列扫描线需保证第二控制晶体管一直开启，则当前列可以正常刷新；如果某些列不需要更新，列扫描线需保证这些列像素电路中的第二控制晶体管一直关闭。
本公开至少一实施例所述的显示面板还包括上述的像素电路。
本公开实施例所述的显示装置包括上述的显示面板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (30)

  1. 一种驱动电路，包括第一开关电路和扫描信号生成电路；
    所述第一开关电路与第一选通控制线、源极驱动器的数据输出端和所述扫描信号生成电路电连接，用于在所述第一选通控制线提供的第一选通控制信号的控制下，控制将所述数据输出端提供的数据信号写入所述扫描信号生成电路；
    所述扫描信号生成电路用于根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号。
  2. 如权利要求1所述的驱动电路，其中，还包括第二开关电路；
    所述第二开关电路分别与第二选通控制线、所述数据输出端和显示面板包括的数据线电连接，用于在所述第二选通控制线提供的第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开；
    所述第一选通控制线与所述第二选通控制线为同一选通控制线，或者，所述第一选通控制线与所述第二选通控制线不同。
  3. 如权利要求1所述的驱动电路，其中，所述第一开关电路包括第一晶体管和第一电容；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
    所述第一晶体管的栅极与所述第一选通控制线电连接，所述第一晶体管的第一极与所述数据输出端电连接，所述第一晶体管的第二极与所述控制节点电连接；
    所述第一电容的第一端与所述控制节点电连接，所述第一电容的第二端与直流电压端电连接。
  4. 如权利要求2所述的驱动电路，其中，所述第二开关电路包括第二晶体管；
    所述第二晶体管的栅极与所述第二选通控制线电连接，所述第二晶体管的第一极与所述数据输出端电连接，所述第二晶体管的第二极与所述数据线电连接。
  5. 如权利要求1所述的驱动电路，其中，所述扫描信号生成电路包括输出控制电路和输出电路；所述第一开关电路通过控制节点向所述扫描信号生成电路提供所述数据信号；
    所述输出控制电路分别与所述控制节点、第一电压端、第二电压端、输出控制端和扫描输出端电连接，用于在所述控制节点的电位的控制下，控制所述输出控制端与所述第一电压端之间连通或断开，在所述扫描输出端提供的信号的控制下，控制所述输出控制端与所述第二电压端之间连通或断开；
    所述输出电路分别与控制端、扫描输出端、所述输出控制端、所述第一电压端和所述第二电压端电连接，用于在所述控制端提供的控制信号的控制下，控制所述扫描输出端与所述第一电压端之间连通或断开，在所述输出控制端的电位的控制下，控制所述扫描输出端与所述第二电压端之间连通或断开。
  6. 如权利要求5所述的驱动电路，其中，所述扫描输出端为所述扫描信号输出端；或者，
    所述扫描信号生成电路还包括反相电路；所述反相电路的输入端与所述扫描输出端电连接，所述反相电路的输出端与所述扫描信号输出端电连接，所述反相电路用于对其输入端接入的电压信号进行反相，得到反相电压信号，并通过所述反相电路的输出端输出所述反相电压信号。
  7. 如权利要求5所述的驱动电路，其中，所述输出控制电路包括第三晶体管和第四晶体管；
    所述第三晶体管的栅极与所述控制节点电连接，所述第三晶体管的第一极与所述第一电压端电连接，所述第三晶体管的第二极与所述输出控制端电连接；
    所述第四晶体管的栅极与扫描输出端电连接，所述第四晶体管的第一极与所述输出控制端电连接，所述第四晶体管的第二极与所述第二电压端电连接；
    所述输出电路包括第五晶体管、第六晶体管和第二电容；
    所述第五晶体管的栅极与所述控制端电连接，所述第五晶体管的第一极与所述第一电压端电连接，所述第五晶体管的第二极与所述扫描输出端电连接；
    所述第六晶体管的栅极与所述输出控制端电连接，所述第六晶体管的第一极与所述扫描输出端电连接，所述第六晶体管的第二极与所述第二电压端电连接；
    所述第二电容的第一端与所述控制端电连接，所述第二电容的第二端与所述第二电压端电连接。
  8. 一种驱动方法，应用于如权利要求1至7中任一权利要求所述的驱动电路，其中，所述驱动方法包括：在两帧显示时间之间的空白时间段中的至少部分时间，
    第一开关电路在第一选通控制信号的控制下，控制将源极驱动器的数据输出端提供的数据信号写入所述扫描信号生成电路；
    扫描信号生成电路根据所述数据信号生成扫描信号，并通过扫描信号输出端输出所述扫描信号至显示面板的相应列扫描线。
  9. 如权利要求8所述的驱动方法，其中，所述驱动电路还包括第二开关电路；所述驱动方法还包括：
    在一帧显示时间中的数据写入时间段，第二开关电路在第二选通控制信号的控制下，控制所述源极驱动器的数据输出端与所述显示面板的相应列数据线之间连通。
  10. 一种像素电路，包括发光元件、发光驱动电路和控制电路；
    所述发光驱动电路分别与第一节点和所述发光元件的第一极电连接，用于在所述第一节点的电位的控制下，产生驱动所述发光元件的驱动电流；所述发光元件的第二极与第三电压端电连接；
    所述控制电路分别与第一栅线、扫描线、所述第一节点和所述发光元件的第一极电连接，用于在所述第一栅线提供的第一栅极驱动信号和所述扫描线提供的扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
  11. 如权利要求10所述的像素电路，其中，所述控制电路包括第一控制电路和第二 控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
    所述第一控制电路分别与所述第一栅线、所述第一节点和中间节点电连接，所述第一控制电路用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第一节点与所述中间节点之间连通或断开；
    所述第二控制电路分别与扫描线、所述中间节点和所述第三节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第三节点之间连通或断开。
  12. 如权利要求10所述的像素电路，其中，所述控制电路包括第一控制电路和第二控制电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
    所述第一控制电路分别与所述第一栅线、所述第三节点和中间节点电连接，用于在所述第一栅线提供的第一栅极驱动信号的控制下，控制所述第三节点与所述中间节点之间连通或断开；
    所述第二控制电路分别与所述扫描线、所述中间节点和所述第一节点电连接，用于在所述扫描线提供的扫描信号的控制下，控制所述中间节点与所述第一节点之间连通或断开。
  13. 如权利要求10所述的像素电路，其中，还包括第一初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
    所述第一初始化电路分别与第一初始控制端、第一初始电压端和所述第二节点电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第一初始电压端提供的第一初始电压写入所述第二节点。
  14. 如权利要求10所述的像素电路，其中，还包括第二初始化电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
    所述第二初始化电路分别与第二初始控制端、第二初始电压端和所述第三节点电连接，用于在所述第二初始控制端提供的第二初始控制信号的控制下，将所述第二初始电压端提供的第二初始电压写入所述第三节点。
  15. 如权利要求10所述的像素电路，其中，还包括数据写入电路、第一发光控制电路、第二发光控制电路和储能电路；所述发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和所述发光元件的第一极电连接；
    所述数据写入电路分别与第二栅线、数据线和所述第二节点电连接，用于在所述第二栅线提供的第二栅极驱动信号的控制下，将所述数据线提供的数据电压写入所述第二节点；
    所述第一发光控制电路分别与发光控制线、电源电压端和所述第二节点电连接，用于在所述发光控制线提供的发光控制信号的控制下，控制所述电源电压端与所述第二节点之间连通或断开；
    所述第二发光控制电路分别与所述发光控制线、所述第三节点和所述发光元件的第一极电连接，用于在所述发光控制信号的控制下，控制所述第三节点与所述发光元件的第一极电连接；
    所述储能电路与所述第一节点电连接，用于储存电能。
  16. 如权利要求15所述的像素电路，其中，还包括第三初始化电路；
    所述第三初始化电路分别与第一初始控制端、第三初始电压端和所述发光元件的第一极电连接，用于在所述第一初始控制端提供的第一初始控制信号的控制下，将所述第三初始电压端提供的第三初始电压写入所述发光元件的第一极。
  17. 如权利要求11所述的像素电路，其中，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
    所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述第一节点电连接，所述第一控制晶体管的第二极与所述中间节点电连接；
    所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述中间节点电连接，所述第二控制晶体管的第二极与所述第三节点电连接。
  18. 如权利要求12所述的像素电路，其中，所述第一控制电路包括第一控制晶体管，所述第二控制电路包括第二控制晶体管；
    所述第一控制晶体管的栅极与所述第一栅线电连接，所述第一控制晶体管的第一极与所述中间节点电连接，所述第一控制晶体管的第二极与所述第三节点电连接；
    所述第二控制晶体管的栅极与所述扫描线电连接，所述第二控制晶体管的第一极与所述第一节点电连接，所述第二控制晶体管的第二极与所述中间节点电连接。
  19. 如权利要求13所述的像素电路，其中，所述第一初始化电路包括第一初始化晶体管；
    所述第一初始化晶体管的栅极与所述第一初始控制端电连接，所述第一初始化晶体管的第一极与所述第一初始电压端电连接，所述第一初始化晶体管的第二极与所述第二节点电连接。
  20. 如权利要求14所述的像素电路，其中，所述第二初始化电路包括第二初始化晶体管；
    所述第二初始化晶体管的栅极与所述第二初始控制端电连接，所述第二初始化晶体管的第一极与所述第二初始电压端电连接，所述第二初始化晶体管的第二极与所述第三节点电连接。
  21. 如权利要求15所述的像素电路，其中，所述数据写入电路包括写入晶体管，所述第一发光控制电路包括第一发光控制晶体管，所述第二发光控制电路包括第二发光控制晶体管；所述发光驱动电路包括驱动晶体管，所述储能电路包括存储电容；
    所述写入晶体管的栅极与所述第二栅线电连接，所述写入晶体管的第一极与所述数据线电连接，所述写入晶体管的第二极与所述第二节点电连接；
    所述第一发光控制晶体管的栅极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述电源电压端电连接，所述第一发光控制晶体管的第二极与所述第二节点电连接；
    所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述第三节点电连接，所述第二发光控制晶体管的第二极与所述发光元件的第一极电连接；
    所述驱动晶体管的栅极与所述第一节点电连接，所述驱动晶体管的第一极与所述第二节点电连接，所述驱动晶体管的第二极与所述第三节点电连接；
    所述存储电容的第一端与所述第一节点电连接，所述存储电容的第二端与电源电压端电连接。
  22. 如权利要求16所述的像素电路，其中，所述第三初始化电路包括第三初始化晶体管；
    所述第三初始化晶体管的栅极与所述第一初始控制端电连接，所述第三初始化晶体管的第一极与所述第三初始电压端电连接，所述第三初始化晶体管的第二极与所述发光元件的第一极电连接。
  23. 一种像素驱动方法，应用于如权利要求10至22中任一权利要求所述的像素电路，所述像素驱动方法包括：
    发光驱动电路在第一节点的电位的控制下，产生驱动发光元件的驱动电流；
    控制电路在第一栅极驱动信号和扫描信号的控制下，控制所述第一节点与所述发光元件的第一极之间连通或断开。
  24. 如权利要求23所述的像素驱动方法，其中，所述像素电路包括第一初始化电路，发光驱动电路的第一端与第二节点电连接，所述发光驱动电路的第二端分别与第三节点和发光元件的第一极电连接；显示周期包括先后设置的第一初始化时间段和第二初始化时间段；所述像素驱动方法包括：
    在所述第一初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与第三节点之间连通；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通；
    在所述第二初始化时间段，所述控制电路在所述第一栅极驱动信号和所述扫描信号的控制下，控制所述第一节点与所述第三节点之间断开；所述第一初始化电路在第一初始控制信号的控制下，将第一初始电压写入所述第二节点；发光驱动电路在所述第一节点的电位的控制下，控制所述第二节点与所述第三节点之间连通。
  25. 一种显示面板，包括源极驱动器和如权利要求1至7中任一权利要求所述的驱动电路；
    所述源极驱动器包括数据输出端。
  26. 如权利要求25所述的显示面板，其中，包括多列扫描线；
    所述驱动电路中的扫描信号生成电路中的扫描信号输出端与所述扫描线电连接。
  27. 如权利要求25所述的显示面板，其中，所述显示面板包括多列数据线；
    所述数据输出端直接与数据线电连接；或者，所述驱动电路包括第二开关电路，所述第二开关电路在第二选通控制信号的控制下，控制所述数据输出端与所述数据线之间连通或断开。
  28. 如权利要求25至27中任一权利要求所述的显示面板，其中，所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第一侧边；或者，
    所述源极驱动器设置于显示面板的第一侧边，所述驱动电路设置于所述显示面板的第二侧边，所述第一侧边与所述第二侧边为相对的侧边。
  29. 如权利要求25至27中任一权利要求所述的显示面板，其中，还包括如权利要求10至22中任一权利要求所述的像素电路。
  30. 一种显示装置，包括如权利要求25至29中任一权利要求所述的显示面板。
PCT/CN2024/094815 2023-06-16 2024-05-23 驱动电路、驱动方法、像素电路、显示面板和显示装置 Ceased WO2024255555A1 (zh)

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