WO2024255541A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024255541A1
WO2024255541A1 PCT/CN2024/094321 CN2024094321W WO2024255541A1 WO 2024255541 A1 WO2024255541 A1 WO 2024255541A1 CN 2024094321 W CN2024094321 W CN 2024094321W WO 2024255541 A1 WO2024255541 A1 WO 2024255541A1
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WO
WIPO (PCT)
Prior art keywords
layer
substrate
display panel
light
orthographic projection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/094321
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English (en)
French (fr)
Inventor
刘宁
周斌
程磊磊
徐晓青
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei Xinsheng Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/996,308 priority Critical patent/US20260040774A1/en
Publication of WO2024255541A1 publication Critical patent/WO2024255541A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80515—Anodes characterised by their shape

Definitions

  • the present disclosure relates to the field of display technology, and more specifically, to a display panel and a display device.
  • transparent display panels are increasingly widely used, for example, in windows of vehicles such as cars, subways, and trains, display windows of shopping malls and supermarkets, billboards, etc.
  • the inventors have found that transparent display panels in related technologies often have dark spots caused by pixels not being able to display normally, which affects the product yield.
  • An object of the present disclosure is to provide a display panel and a display device to solve at least one of the problems existing in the prior art.
  • a display panel comprising a substrate and a plurality of pixels arranged in an array on the substrate, wherein the pixels comprise a light-emitting area and a transparent area, wherein the light-emitting area comprises a driving circuit layer, a flat layer, a first electrode, a light-emitting layer and a second electrode sequentially arranged on the substrate, wherein an orthographic projection of an edge portion of the flat layer close to the transparent area on the substrate and an orthographic projection of the first electrode on the substrate have a first overlapping area, and the light-emitting area further comprises a protruding portion, wherein a thickness of the protruding portion is less than a thickness of the flat layer, the protruding portion is closer to the substrate than the flat layer, and an orthographic projection of the protruding portion on the substrate covers the first overlapping area.
  • the light emitting area further includes a plurality of signal lines electrically connected to the pixels, and the signal lines form the protrusions.
  • the light-emitting area further includes an auxiliary electrode electrically connected to the second electrode
  • the signal line includes an auxiliary electrode wiring electrically connected to the auxiliary electrode
  • the auxiliary electrode wiring is provided with an extension portion, and the extension portion forms the protrusion.
  • the protrusion includes a first part, an orthographic projection of the first part on the substrate coincides with an orthographic projection of the first overlapping region on the substrate, and a length of the first part in a direction from the light emitting area to the transparent area is 5 ⁇ m-20 ⁇ m.
  • the protrusion further includes a second portion, and an orthographic projection of the second portion on the substrate is located on a side of the first overlapping region close to the transparent area.
  • the first electrode includes a first step portion and a second step portion
  • the orthographic projection of the first step portion on the substrate covers the orthographic projection of the boundary between the first part and the second part on the substrate
  • the orthographic projection of the second step portion on the substrate covers the orthographic projection of the edge of the second part close to the transparent area on the substrate.
  • the length of the second portion is equal to the length of the first portion.
  • a thickness ratio of the protrusion to the flat layer is 1:3-1:5.
  • the driving circuit layer includes an active layer, a gate insulating layer, a gate of a thin film transistor, a dielectric layer and a source-drain metal layer stacked in sequence, the source-drain metal layer forms the source and drain of the thin film transistor, the light-emitting area also includes a passivation layer arranged between the driving circuit layer and the flat layer, and the anode is connected to the source or drain through a via in the passivation layer.
  • the auxiliary electrode wiring is arranged in the same layer as the source and drain metal layer.
  • a second aspect of the present disclosure provides a display device, comprising the display panel provided by the first aspect of the present disclosure.
  • the technical solution disclosed in the present invention can reduce the inclination angle of the edge of the flat layer by forming a protrusion at the edge of the flat layer close to the substrate side, so that the slope of the edge of the flat layer is relatively gentle, thereby reducing the climbing difficulty of the first electrode, and can effectively reduce the risk of the first electrode breaking, thereby reducing the risk of dark spots in the display panel and improving the product yield.
  • FIG. 1 is a schematic diagram showing a pixel in a display panel in the related art.
  • FIG. 2 is a schematic cross-sectional view showing a pixel in a display panel in the related art.
  • FIG. 3 is a schematic diagram showing a microscope observation of the edge region of the flat layer shown in FIG. 1 .
  • FIG. 4 is a schematic cross-sectional view of an edge region of the flat layer shown in FIG. 1 by SEM (scanning electron microscope observation).
  • FIG. 5 is a schematic diagram showing a pixel in a display panel provided by an embodiment of the present disclosure.
  • FIG6 is a schematic cross-sectional view of a pixel in a display panel provided by an embodiment of the present disclosure.
  • FIG. 7 is a simplified schematic diagram showing the edge region of a flat layer in the related art.
  • FIG. 8 is a simplified schematic diagram showing an edge region of a planar layer in an embodiment of the present disclosure.
  • on may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.
  • first the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or parts, these parts, components, elements, regions, layers and/or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and/or part from another.
  • first part, first member, first element, first region, first layer and/or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and/or second part without departing from the teachings of the present disclosure.
  • the term "same-layer arrangement" used refers to two layers, parts, components, elements or parts that can be formed by the same preparation process (such as a patterning process, etc.), and the two layers, parts, components, elements or parts are generally formed of the same material.
  • two or more functional layers are arranged in the same layer, which means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process, thereby simplifying the preparation process of the display substrate.
  • patterning process generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc.
  • one-time patterning process means a process of forming patterned layers, components, members, etc. using one mask.
  • OLED organic light-emitting diode
  • the left side of the passivation layer (PVX) via 101 for connecting the anode (Anode) to the source (Source) of the thin film transistor (TFT) is the light-emitting area
  • the right side of the passivation layer via 101 is the transparent area.
  • the light-emitting area includes a driving circuit layer, a passivation layer (PVX) 104, a flat layer (PLN) 105, an anode, a light-emitting layer 107 and a cathode 108 sequentially arranged on the substrate 102.
  • the driving circuit layer includes an active layer (Active) 1031, a gate insulating layer (GI) 1032, a gate (Gate) 1033 of a thin film transistor, a dielectric layer (ILD) 1034 and a source-drain metal layer (SD) which are stacked in sequence, and the source-drain metal layer forms a source (Source) 10351 and a drain (Drain) 10352 of the thin film transistor.
  • Active active layer
  • GI gate insulating layer
  • Gate gate
  • SD source-drain metal layer
  • the anode is, for example, a composite structure, including a first thin film electrode 1061, for example, made of indium tin oxide (ITO), a metal electrode 1062, for example, as a reflective electrode, and a second thin film electrode 1063, for example, made of indium tin oxide (ITO), which are stacked in sequence, and the first thin film electrode 1061 is connected to the source 10351 through a passivation layer 104 via 101.
  • the light-emitting area also includes a pixel definition layer (PDL) 109 for defining the area of the light-emitting area.
  • PDL pixel definition layer
  • the OLED transparent display panel in order to improve the transmittance of the transparent area, the OLED transparent display panel will not set a flat layer in the transparent area. Therefore, the flat layer 105 in the light-emitting area will form a flat layer edge with a large edge inclination angle near the edge of the light-emitting area. In this way, when the first thin-film electrode 1061 is formed after the flat layer 105 is formed, the first thin-film electrode 1061 needs to climb a steep slope at the edge of the flat layer. The first thin-film electrode 1061 is prone to breakage due to the climbing.
  • the morphology of the edge area of the flat layer where the first thin-film electrode 1061 is prone to breakage is shown in, for example, FIGS.
  • an embodiment of the present disclosure provides a display panel, comprising a substrate and a plurality of pixels arranged in an array on the substrate, the pixels comprising a light-emitting area and a transparent area, the light-emitting area comprising a driving circuit layer, a flat layer, a first electrode, a light-emitting layer and a second electrode sequentially arranged on the substrate, an orthographic projection of an edge portion of the flat layer close to the transparent area on the substrate and an orthographic projection of the first electrode on the substrate having a first overlapping area, the light-emitting area also comprising a protruding portion, a thickness of the protruding portion being less than a thickness of the flat layer, the protruding portion being closer to the substrate than the flat layer and an orthographic projection of the protruding portion on the substrate covering the first overlapping area.
  • the display panel provided by the embodiment of the present disclosure can reduce the inclination angle of the edge of the flat layer by forming a protrusion near the substrate side at the edge of the flat layer, so that the slope of the edge of the flat layer is relatively gentle, thereby reducing the climbing difficulty of the first electrode, and can effectively reduce the risk of the first electrode breaking, thereby reducing the risk of dark spots in the display panel and improving the product yield.
  • the display panel provided in the embodiment of the present disclosure is a transparent display panel.
  • the display panel provided in the present disclosure can be an organic light-emitting diode (OLED) display panel or a light-emitting diode (LED) display panel, etc.
  • OLED organic light-emitting diode
  • LED light-emitting diode
  • the OLED transparent display panel provided by the embodiment of the present disclosure includes a substrate and a plurality of pixels arranged in an array on the substrate, each pixel including a light-emitting area and a transparent area.
  • each pixel including a light-emitting area and a transparent area.
  • the left side of the passivation layer (PVX) via 501 for connecting the anode (Anode) to the source (Source) of the thin film transistor (TFT) is the light-emitting area
  • the right side of the passivation layer via 501 is the transparent area.
  • the light-emitting area includes a driving circuit layer, a passivation layer (PVX) 504, a flat layer (PLN) 505, an anode, a light-emitting layer 507, and a cathode 508 sequentially arranged on a substrate 502.
  • PVX passivation layer
  • PPN flat layer
  • the substrate 502 may be made of glass, quartz or other materials.
  • the OLED transparent display panel may further include a barrier layer (not shown) and a buffer layer (Buffer) 509 located between the substrate 502 and the driving circuit layer.
  • the barrier layer and the buffer layer 509 may be formed on the entire surface of the substrate 502.
  • Inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride may be used, and the buffer layer 509 may also be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the barrier layer is beneficial to preventing water and oxygen from entering the OLED formed later from the bottom.
  • the buffer layer 509 is beneficial to the quality of subsequent material deposition.
  • the driving circuit layer may also be referred to as a thin film transistor (TFT) layer.
  • the driving circuit layer includes an active layer (Active) 5031, a gate insulating layer (GI) 5032, a gate (Gate) 5033 of the thin film transistor, a dielectric layer (ILD) 5034 and a source-drain metal layer (SD) which are stacked in sequence.
  • the source-drain metal layer forms a source (Source) 50351 and a drain (Drain) 50352 of the thin film transistor.
  • the driving circuit layer includes an active layer 5031 formed on the buffer layer 509 by a patterning process, a gate insulating layer 5032 formed on the active layer 5031 by deposition or the like, a gate 5033 of a thin film transistor formed on the gate insulating layer 5032 by a patterning process, a dielectric layer 5034 formed on the gate 5033 by deposition or the like, and a source-drain metal layer formed on the dielectric layer 5034, the source-drain metal layer forming a source 50351 and a drain 50352 of the thin film transistor
  • the active layer 5031 includes, for example, a semiconductor portion, and a conductive portion located on both sides of the semiconductor portion and connected to the semiconductor portion, for example, the source 50351 is electrically connected to one conductive portion of the active layer 5031 through a dielectric layer via, and the drain 50352 is electrically connected to another conductive portion of the active layer 5031 through a dielectric layer via.
  • the light-emitting area also includes a plurality of signal lines, and the signal lines include, for example, a detection line 521, a data line 522, a gate line 523, etc.
  • the data line 522 is electrically connected to the drain electrode 50352, and the gate line 523 is electrically connected to the gate electrode 5033.
  • the active layer 5031 can be made of materials such as polysilicon and metal oxides
  • the gate insulating layer 5032 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride
  • the dielectric layer 5034 can be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
  • the gate 5033 material includes metals or alloy materials such as aluminum, titanium, and cobalt.
  • the OLED transparent display panel may also include a light shielding layer (LS) 510 located on the substrate 502 and covering the TFT structure with an orthographic projection.
  • LS light shielding layer
  • the passivation layer 504 covers the source-drain metal layer and the exposed dielectric layer 5034, and the planarization layer 505 covers the passivation layer 504.
  • the anode is, for example, a composite structure, including a first thin-film electrode 5061, for example, made of indium tin oxide (ITO), a metal electrode 5062, for example, as a reflective electrode, and a second thin-film electrode 5063, for example, made of indium tin oxide (ITO), which are stacked in sequence.
  • the first thin-film electrode 5061 is connected to the source electrode 50351 through the passivation layer via 501.
  • the light-emitting area also includes a portion for limiting the light-emitting area.
  • the pixel definition layer (PDL) 509 in the region of the cathode 508 is formed by, for example, indium zinc oxide (IZO).
  • the OLED transparent display panel may also include an encapsulation layer (TFE) located on the cathode 508.
  • the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer are formed by deposition or the like.
  • the organic encapsulation layer is formed by inkjet printing.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer can be formed of inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride
  • the organic encapsulation layer can be formed of organic materials such as polyimide (PI) and epoxy resin.
  • PI polyimide
  • the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer are formed into a composite encapsulation layer, which can form multiple protections for the functional structure of the display panel and has a better encapsulation effect.
  • the buffer layer 509, the dielectric layer 5034, the light-emitting layer 507 and the cathode 508 of the light-emitting area extend to the transparent area, wherein the light-emitting layer 507 extending to the transparent area is disconnected at the edge of the light-emitting area, which will be described in detail later.
  • the thicker flat layer 505 of the resin material does not extend to the transparent area, or the flat layer is not provided in the transparent area.
  • the edge of the flat layer 505 is close to the edge of the light-emitting area, and the orthographic projection of the edge portion of the flat layer 505 close to the transparent area on the substrate 502 and the orthographic projection of the first thin film electrode 5061 on the substrate 502 have a first overlapping area.
  • the light-emitting area of the pixel also includes a protrusion 511, the thickness of the protrusion 511 is less than the thickness of the flat layer 505, the protrusion 511 is closer to the substrate 502 than the flat layer 505, and the orthographic projection of the protrusion 511 on the substrate 502 covers the first overlapping area.
  • the thickness of the protrusion 511 that is, the length of the protrusion 511 in the light emitting direction (the light emitting direction is the direction perpendicular to the substrate 502, the vertical direction in Figure 6), and the thickness of the flat layer 505 is the same.
  • the thickness of the flat layer 505 refers to its main thickness in the light emitting area and should not be regarded as the thickness in the edge slope.
  • the embodiment of the present disclosure can change the edge of the flat layer 105 in the related art shown in Figure 7, which is a slope with a large slope, into the flat layer 105 shown in Figure 8. Two slopes with smaller slopes are formed at the edge of layer 505.
  • the two slopes with smaller slopes are formed by the edge of the flat layer 505 and the edge of the passivation layer 504, respectively, so that the slope at the edge of the flat layer is relatively gentle, thereby reducing the climbing difficulty of the first thin-film electrode 5061 and effectively reducing the risk of the first thin-film electrode 5061 breaking, thereby reducing the risk of dark spots in the OLED transparent display panel and improving the product yield.
  • other necessary functional film layers may be formed in the display area of the OLED transparent display panel as needed, such as storage capacitors in the light-emitting area of the pixel, etc., which will not be described in detail here.
  • the light-emitting area further includes a plurality of signal lines electrically connected to the pixels, and the signal lines form the protrusions 511 .
  • the protrusion 511 can be formed by designing the routing shape of the signal line, avoiding the increase in preparation process and production cost caused by setting the protrusion 511, and can effectively achieve the smoothing of the edge position of the flat layer, reducing the climbing difficulty of the first thin film electrode 5061.
  • the light-emitting area also includes an auxiliary cathode electrically connected to the cathode 508, the signal line includes an auxiliary cathode wiring 524 electrically connected to the auxiliary cathode, and the auxiliary cathode wiring 524 is provided with an extension portion, which forms a protrusion 511.
  • the auxiliary electrode wiring 524 itself is located relatively close to the edge of the flat layer 505 close to the transparent area. Therefore, an extension portion is designed for the auxiliary cathode wiring 524 below the first overlapping area, and a protrusion 511 is formed by the extension portion. This can further avoid the increase in preparation process and production cost caused by setting the protrusion 511, and can effectively achieve the smoothing of the edge position of the flat layer, thereby reducing the climbing difficulty of the first thin film electrode 5061.
  • the auxiliary cathode is stacked in sequence with a first thin film electrode layer 5061', a metal electrode layer 5062' and a second thin film electrode layer 5063', wherein the side surface of the metal electrode layer 5062' close to the transparent area and the side surface away from the transparent area (i.e., the left and right side surfaces in FIG6) are respectively recessed inward, so that the auxiliary cathode as a whole forms an I-shaped structure as shown in FIG6.
  • This structure can be achieved by side etching and other processes, thereby achieving the disconnection of the light-emitting layer 507 at the top of the auxiliary cathode from the light-emitting area and the light-emitting layer 507 extending to the transparent area.
  • the auxiliary cathode The cathode 508 at the top is also disconnected from the cathode 508 in the light-emitting area and the cathode 508 extending to the transparent area, but the cathode 508 in the light-emitting area can be electrically connected to the metal electrode layer 5062' of the auxiliary cathode, thereby realizing the electrical connection between the auxiliary cathode and the cathode 508 in the light-emitting area.
  • FIG6 is only a schematic diagram of the cross-sectional morphology.
  • the auxiliary cathode and the auxiliary cathode wiring 512 are located between the sloped edge of the flat layer 505 close to the transparent area and the passivation layer via 501 for connecting the first thin film electrode 5061 to the source 50351 of the thin film transistor, for example, see FIG5.
  • the auxiliary cathode wiring 524 is disposed on the same layer as the source-drain metal layer forming the source 50351 and the drain 50352 of the thin film transistor.
  • an extension portion can be designed for the auxiliary cathode wiring 524 below the first overlapping region, thereby further simplifying the manufacturing process.
  • the protrusion 511 includes a first part, the orthographic projection of the first part on the substrate 502 coincides with the orthographic projection of the first overlapping area on the substrate 502, and the length of the first part in the direction from the light-emitting area to the transparent area is 5 ⁇ m-20 ⁇ m.
  • the first part of the protrusion 511 that is, the part of the protrusion 511 that overlaps with the positive projection of the VSS flat layer 505 on the substrate 502 as shown in Figure 8, the above design can effectively smooth the edge position of the flat layer and reduce the climbing difficulty of the first thin film electrode 5061.
  • the protrusion 511 further includes a second portion, and the orthographic projection of the second portion on the substrate 502 is located on a side of the first overlapping region close to the transparent area.
  • the second part of the protrusion 511 that is, the right part of the protrusion 511 that overlaps with the positive projection of the VSS flat layer 505 on the substrate 502 as shown in Figure 8, the above design can effectively smooth the edge position of the flat layer and reduce the climbing difficulty of the first thin film electrode 5061.
  • the length of the second portion is equal to the length of the first portion.
  • the edge of the flat layer can be effectively smoothed, reducing the climbing difficulty of the first thin film electrode 5061.
  • the equal length in this implementation allows process errors, for example, in the disclosed embodiment, the length deviation within 5% is regarded as equal.
  • the first thin-film electrode 5061 includes a first step portion and a second step portion, the orthographic projection of the first step portion on the substrate 502 covers the orthographic projection of the junction of the first part and the second part on the substrate 502, and the orthographic projection of the second step portion on the substrate 502 covers the orthographic projection of the edge of the second part close to the transparent area on the substrate 502.
  • the first thin-film electrode 5061 forms a relatively gentle step portion at the two slopes with smaller slopes at the edge of the planar layer 505, respectively.
  • the first thin-film electrode 5061 greatly reduces the difficulty of climbing at the edge of the planar layer 505, thereby effectively reducing the risk of the first thin-film electrode 5061 breaking.
  • the thickness ratio of the protrusion 511 to the flat layer 505 is 1:3-1:5.
  • the thickness of the planar layer 505 is The thickness of the protrusion 511 is The thickness ratio of the protrusion 511 to the flat layer 505 is 1:4.
  • the edge of the flat layer can be effectively smoothed, thereby reducing the climbing difficulty of the first thin-film electrode 5061 .
  • the display device can be a window display screen of a vehicle such as a car, subway, train, etc., a display window display screen of a shopping mall or supermarket, a billboard display screen, and other products or components with display functions, which are not limited in this embodiment.

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Abstract

本公开实施例公开一种显示面板及显示装置。在一具体实施方式中，显示面板包括衬底及设置在所述衬底上的阵列排布的多个像素，所述像素包括发光区和透明区，所述发光区包括依次设置在所述衬底上的驱动电路层、平坦层、第一电极、发光层和第二电极，所述平坦层的靠近所述透明区的边缘部分在所述衬底上的正投影与所述第一电极在所述衬底上的正投影存在第一交叠区域，所述发光区还包括凸起部，所述凸起部的厚度小于所述平坦层的厚度，所述凸起部相比所述平坦层靠近所述衬底且所述凸起部在所述衬底上的正投影覆盖所述第一交叠区域。该实施方式可降低第一电极出现断裂不良的风险，从而降低显示面板出现暗点不良的风险，提升产品良率。

Description

显示面板及显示装置
相关申请的交叉引用
本申请主张在2023年6月13日在中国提交的中国专利申请号No.202310706226.2的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域。更具体地，涉及一种显示面板及显示装置。
背景技术
目前，透明显示面板得到越来越广泛的应用，例如，在汽车、地铁、火车等交通工具的车窗，商场、超市的展示橱窗，广告牌等场景均以有所应用。发明人发现，相关技术中的透明显示面板，常出现像素无法正常显示导致的暗点不良，影响产品良率。
发明内容
本公开的目的在于提供一种显示面板及显示装置，以解决现有技术存在的问题中的至少一个。
为达到上述目的，本公开采用下述技术方案：
本公开第一方面提供了一种显示面板，包括衬底及设置在所述衬底上的阵列排布的多个像素，所述像素包括发光区和透明区，所述发光区包括依次设置在所述衬底上的驱动电路层、平坦层、第一电极、发光层和第二电极，所述平坦层的靠近所述透明区的边缘部分在所述衬底上的正投影与所述第一电极在所述衬底上的正投影存在第一交叠区域，所述发光区还包括凸起部，所述凸起部的厚度小于所述平坦层的厚度，所述凸起部相比所述平坦层靠近所述衬底且所述凸起部在所述衬底上的正投影覆盖所述第一交叠区域。
可选地，所述发光区还包括与所述像素电连接的多条信号线，所述信号线形成所述凸起部。
可选地，所述发光区还包括与所述第二电极电连接的辅助电极，所述信号线包括与所述辅助电极电连接的辅助电极走线，所述辅助电极走线设置有延伸部，所述延伸部形成所述凸起部。
可选地，所述凸起部包括第一部分，所述第一部分在所述衬底上的正投影与所述第一交叠区域在所述衬底上的正投影重合，在所述发光区指向所述透明区的方向上，所述第一部分的长度为5μm-20μm。
可选地，所述凸起部还包括第二部分，所述第二部分在所述衬底上的正投影位于所述第一交叠区域的靠近所述透明区一侧。
可选地，所述第一电极包括第一台阶部和第二台阶部，所述第一台阶部在所述衬底上的正投影覆盖所述第一部分与所述第二部分的交界在所述衬底上的正投影，所述第二台阶部在所述衬底上的正投影覆盖所述第二部分的靠近所述透明区的边缘在所述衬底上的正投影。
可选地，在所述发光区指向所述透明区的方向上，所述第二部分的长度等于所述第一部分的长度。
可选地，所述凸起部与所述平坦层的厚度比为1:3-1:5。
可选地，所述驱动电路层包括依次层叠设置的有源层、栅极绝缘层、薄膜晶体管的栅极、介电层和源漏金属层，所述源漏金属层形成薄膜晶体管的源极和漏极，所述发光区还包括设置于所述驱动电路层与所述平坦层之间的钝化层，所述阳极通过所述钝化层的过孔连接所述源极或漏极。
可选地，所述辅助电极走线与所述源漏金属层同层设置。
本公开第二方面提供一种显示装置，包括本公开第一方面提供的显示面板。
本公开的有益效果如下：
本公开所述技术方案，通过在平坦层边缘的靠近衬底侧形成的凸起部，可减小平坦层边缘位置的倾斜角度，使得平坦层边缘位置的坡度较为平缓，从而降低了第一电极的爬坡难度，可有效降低第一电极出现断裂不良的风险，从而降低显示面板出现暗点不良的风险，提升产品良率。
附图说明
下面结合附图对本公开的具体实施方式作进一步详细的说明。
图1示出相关技术中的显示面板中的像素的示意图。
图2示出相关技术中的显示面板中的像素的截面示意图。
图3示出图1所示中平坦层边缘区域的显微镜观察示意图。
图4示出图1所示中平坦层边缘区域的SEM(扫描电子显微镜观察)截面示意图。
图5示出本公开实施例提供的显示面板中的像素的示意图。
图6示出本公开实施例提供的显示面板中的像素的截面示意图。
图7中示出相关技术中平坦层边缘区域的简化示意图
图8示出本公开实施例中平坦层边缘区域的简化示意图。
具体实施方式
本公开中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层和/或第二部分，而不背离本公开的教导。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过相同制备工艺(例如构图工艺等)形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。例如两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺形成，从而可以简化显示基板的制备工艺。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
发明人发现，相关技术中的透明显示面板，常出现像素无法正常显示导致的暗点不良，影响产品良率。为确定透明显示面板的暗点不良的原因，发明人对透明显示面板的结构进行了研究。以有机发光二极管(Organic Light-Emitting Diode，OLED)透明显示面板为例，例如图1和图2所示，OLED透明显示面板的显示区包括衬底及设置在衬底上的阵列排布的多个像素，每个像素包括发光区和透明区，例如图1所示中，用于阳极(Anode)连接薄膜晶体管(TFT)的源极(Source)的钝化层(PVX)过孔101的左侧为发光区，钝化层过孔101的右侧为透明区。例如图1和图2所示，发光区包括依次设置在衬底102上的驱动电路层、钝化层(PVX)104、平坦层(PLN)105、阳极、发光层107和阴极108。驱动电路层包括依次层叠设置的有源层(Active)1031、栅极绝缘层(GI)1032、薄膜晶体管的栅极(Gate)1033、介电层(ILD)1034和源漏金属层(SD)，源漏金属层形成薄膜晶体管的源极(Source)10351和漏极(Drain)10352。阳极例如为复合结构，包括依次层叠设置的例如材料为氧化铟锡(ITO)的第一薄膜电极1061、例如作为反射电极的金属电极1062和例如材料为氧化铟锡(ITO)的第二薄膜电极1063，第一薄膜电极1061通过钝化层104过孔101连接源极10351。此外，如图2所示，发光区还包括用于限定发光区区域的像素界定层(PDL)109。如图1和图2所示，为了提升透明区的透光度，OLED透明显示面板不会在透明区中设置平坦层，因此，发光区中的平坦层105在靠近发光区边缘的位置会形成一个边缘倾斜角度很大的平坦层边缘，这样，在形成平坦层105之后形成第一薄膜电极1061时，第一薄膜电极1061在平坦层边缘位置需要爬一个陡坡，第一薄膜电极1061由于爬坡很容易发生断裂，易发生第一薄膜电极1061断裂的平坦层边缘区域的形貌例如图3和图4所示，其中，图4中的虚线框与图3中的虚线框位置对应，第一薄膜电极1061的断裂会导致阳极无法接收到数据信号，像素的发光区无法正常显示，造成暗点不良。
有鉴于此，本公开实施例提供一种显示面板，包括衬底及设置在所述衬底上的阵列排布的多个像素，所述像素包括发光区和透明区，所述发光区包括依次设置在所述衬底上的驱动电路层、平坦层、第一电极、发光层和第二电极，所述平坦层的靠近所述透明区的边缘部分在所述衬底上的正投影与所述第一电极在所述衬底上的正投影存在第一交叠区域，所述发光区还包括凸起部，所述凸起部的厚度小于所述平坦层的厚度，所述凸起部相比所述平坦层靠近所述衬底且所述凸起部在所述衬底上的正投影覆盖所述第一交叠区域。
本公开实施例提供的显示面板，通过在平坦层边缘的靠近衬底侧形成的凸起部，可减小平坦层边缘位置的倾斜角度，使得平坦层边缘位置的坡度较为平缓，从而降低了第一电极的爬坡难度，可有效降低第一电极出现断裂不良的风险，从而降低显示面板出现暗点不良的风险，提升产品良率。
由于像素包括透明区，因此本公开实施例提供的显示面板为透明显示面板，此外，本公开提供的显示面板可以是有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板，也可以是发光二极管(Light Emitting diode，LED)显示面板等，下面，以OLED显示面板对本公开提供的显示面板进行说明，即，下面以OLED透明显示面板进行说明。
本公开实施例提供的OLED透明显示面板，包括衬底及设置在衬底上的阵列排布的多个像素，每个像素包括发光区和透明区，例如图5所示中，用于阳极(Anode)连接薄膜晶体管(TFT)的源极(Source)的钝化层(PVX)过孔501的左侧为发光区，钝化层过孔501的右侧为透明区。例如图5和图6所示，发光区包括依次设置在衬底502上的驱动电路层、钝化层(PVX)504、平坦层(PLN)505、阳极、发光层507和阴极508。
示例性的，例如图5和图6所示，本公开实施例提供的OLED透明显示面板中：
衬底502可以为玻璃、石英等材料，OLED透明显示面板还可包括位于衬底502与驱动电路层之间的阻挡层(Barrier)(图中未示出)和缓冲层(Buffer)509。例如，阻挡层和缓冲层509可以整面形成在衬底502上。例如，阻挡层 可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料，缓冲层509也可以采用氧化硅、氮化硅、或者氮氧化硅等无机绝缘材料。阻挡层有利于从底部阻挡水、氧进入之后形成的OLED中。缓冲层509有利于后续的材料沉积质量。
驱动电路层也可称为薄膜晶体管(TFT)层，驱动电路层包括依次层叠设置的有源层(Active)5031、栅极绝缘层(GI)5032、薄膜晶体管的栅极(Gate)5033、介电层(ILD)5034和源漏金属层(SD)，源漏金属层形成薄膜晶体管的源极(Source)50351和漏极(Drain)50352。具体而言，驱动电路层包括在缓冲层509上采用构图工艺形成的有源层5031、在有源层5031上通过沉积等方式形成的栅极绝缘层5032、在栅极绝缘层5032上采用构图工艺形成的薄膜晶体管的栅极5033、在栅极5033上通过沉积等方式形成的介电层5034及在介电层5034上形成的源漏金属层，源漏金属层形成薄膜晶体管的源极50351和漏极50352，有源层5031例如包括半导体部、位于半导体部两侧且与半导体部相接的导体化部，例如源极50351通过介电层过孔与有源层5031的一个导体化部电连接，漏极50352通过介电层过孔与有源层5031的另一个导体化部电连接。例如发光区还包括多条信号线，信号线例如包括检测线521、数据线522、栅线523等，数据线522与漏极50352电连接，栅线523与栅极5033电连接。例如，有源层5031可以采用多晶硅和金属氧化物等材料，栅极绝缘层5032可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料，介电层5034可以采用氧化硅、氮化硅或者氮氧化硅等无机绝缘材料。栅极5033材料包括铝、钛、钴等金属或者合金材料。此外，如图6所示，OLED透明显示面板还可包括位于衬底502上的正投影覆盖TFT结构的遮光层(LS)510。
钝化层504覆盖源漏金属层和露出的介电层5034，平坦层505覆盖钝化层504。阳极例如为复合结构，包括依次层叠设置的例如材料为氧化铟锡(ITO)的第一薄膜电极5061、例如作为反射电极的金属电极5062和例如材料为氧化铟锡(ITO)的第二薄膜电极5063，第一薄膜电极5061通过钝化层过孔501连接源极50351。此外，如图6所示，发光区还包括用于限定发光 区区域的像素界定层(PDL)509。阴极508的材料例如为氧化铟锌(IZO)。
OLED透明显示面板还可包括位于阴极508上的封装层(TFE)。例如，封装层包括第一无机封装层、有机封装层和第二无机封装层。例如，第一无机封装层和第二无机封装层采用沉积等方式形成。有机封装层采用喷墨打印的方式形成。例如，第一无机封装层和第二无机封装层可以采用氮化硅、氧化硅、氮氧化硅等无机材料形成，有机封装层可以采用聚酰亚胺(PI)、环氧树脂等有机材料形成。由此，第一无机封装层，有机封装层以及第二无机封装层形成为复合封装层，该复合封装层可以对显示面板的功能结构形成多重保护，具有更好的封装效果。
例如图6所示，发光区的缓冲层509、介电层5034、发光层507和阴极508延伸至透明区，其中，延伸至透明区的发光层507在发光区边缘位置形成断开，后续具体说明。而为了提升透明区的透光度，例如树脂(Resin)材料的厚度较厚的平坦层505则不延伸至透明区，或者说透明区中未设置平坦层。例如图5和图6所示，平坦层505的边缘在靠近发光区边缘的位置，平坦层505的靠近透明区的边缘部分在衬底502上的正投影与第一薄膜电极5061在衬底502上的正投影存在第一交叠区域，本公开实施例提供的OLED透明显示面板中，像素的发光区还包括凸起部511，凸起部511的厚度小于平坦层505的厚度，凸起部511相比平坦层505靠近衬底502，且凸起部511在衬底502上的正投影覆盖所述第一交叠区域。其中，凸起部511的厚度，即，在出光方向(出光方向即垂直于衬底502的方向，图6中的竖直方向)上，凸起部511的长度，平坦层505的厚度同理，此外，可以理解的是，平坦层505的厚度指的是其在发光区中的主体厚度，不应视为在边缘斜坡中的厚度。
由此，通过在平坦层505的靠近透明区的边缘的设计位置下方设置(或者说衬垫上)凸起部511，在后续工艺中形成平坦层505时，具有流动性的例如树脂(Resin)的平坦层材料会形成边缘坡度较为平缓的平坦层505，例如图7和图8所示，通过设置凸起部511，本公开实施例可将图7所示的相关技术中的平坦层105的边缘为一个坡度很大的斜坡，变为图8所示的平坦 层505的边缘位置形成两个坡度较小的斜坡，如图8所示，这两个坡度较小的斜坡分别由平坦层505的边缘和钝化层504的边缘形成，从而使得平坦层边缘位置的坡度较为平缓，降低第一薄膜电极5061的爬坡难度，有效降低第一薄膜电极5061出现断裂不良的风险，从而降低OLED透明显示面板出现暗点不良的风险，提升产品良率。
本公开的一些实施例中，根据需要，OLED透明显示面板的显示区中还可以形成其他必要的功能膜层，例如在像素的发光区中的存储电容等，在此不再赘述。
在一种可能的实现方式中，本公开实施例提供的OLED透明显示面板中，发光区还包括与所述像素电连接的多条信号线，所述信号线形成凸起部511。
由此，可通过对信号线的走线形状设计形成凸起部511，避免设置凸起部511带来制备工艺及生产成本的增加，且可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。
在一种可能的实现方式中，例如图5和图6所示，本公开实施例提供的OLED透明显示面板中，发光区还包括与阴极508电连接的辅助阴极，信号线包括与辅助阴极电连接的辅助阴极走线524，辅助阴极走线524设置有延伸部，该延伸部形成凸起部511。
例如图5和图6所示，辅助电极走线524本身的位置较为靠近平坦层505的靠近透明区的边缘，因此，对第一交叠区域下方的辅助阴极走线524设计出延伸部，通过该延伸部形成凸起部511，可进一步避免设置凸起部511带来制备工艺及生产成本的增加，且可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。
在一个具体示例中，例如图6所示，辅助阴极依次层叠设置的第一薄膜电极层5061`、金属电极层5062`和第二薄膜电极层5063`，其中，金属电极层5062`的靠近透明区的一侧表面和远离透明区的一侧表面(即图6中的左右两侧表面)分别向内形成凹陷，使得辅助阴极整体形成如图6所示的工字型结构，此结构可通过侧蚀等工艺实现，由此，可实现辅助阴极顶部的发光层507与发光区中的及延伸至透明区中的发光层507形成断开，另外，辅助阴 极顶部的阴极508与发光区中的及延伸至透明区中的阴极508也形成断开，但发光区中的阴极508可与辅助阴极的金属电极层5062`电连接，从而实现辅助阴极与发光区中的阴极508的电连接。可理解的是，图6仅为截面形貌的示意，实际上，在发光区指向透明区的方向(即图5-7中的水平方向)上，辅助阴极及辅助阴极走线512，位于平坦层505的靠近透明区的具有坡度的边缘与用于第一薄膜电极5061连接薄膜晶体管的源极50351的钝化层过孔501之间，例如参见图5。
在一种可能的实现方式中，如图6所示，本公开实施例提供的OLED透明显示面板中，辅助阴极走线524与形成薄膜晶体管的源极50351和漏极50352的源漏金属层同层设置。
由此，可在进行源漏金属层的图案化构图时，对第一交叠区域下方的辅助阴极走线524进行延伸部设计，进一步简化了制备工艺。
在一种可能的实现方式中，如图8所示，本公开实施例提供的OLED透明显示面板中，凸起部511包括第一部分，所述第一部分在衬底502上的正投影与所述第一交叠区域在衬底502上的正投影重合，在所述发光区指向所述透明区的方向上，所述第一部分的长度为5μm-20μm。
其中，凸起部511的第一部分，即例如图8所示中，凸起部511的与VSS平坦层505在衬底502上正投影交叠的部分，上述设计，可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。
在一种可能的实现方式中，本公开实施例提供的OLED透明显示面板中，凸起部511还包括第二部分，所述第二部分在衬底502上的正投影位于所述第一交叠区域的靠近所述透明区一侧。
其中，凸起部511的第二部分，即例如图8所示中，凸起部511的与VSS平坦层505在衬底502上正投影交叠的部分的右侧部分，上述设计，可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。
在一种可能的实现方式中，本公开实施例提供的OLED透明显示面板中，在所述发光区指向所述透明区的方向上，所述第二部分的长度等于所述第一部分的长度。
由此，可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。需要说明的是，本实现方式中的长度相等允许工艺误差，例如，本公开实施例中，将5％以内的长度偏差视为相等。
在一种可能的实现方式中，本公开实施例提供的OLED透明显示面板中，第一薄膜电极5061包括第一台阶部和第二台阶部，所述第一台阶部在衬底502上的正投影覆盖所述第一部分与所述第二部分的交界在衬底502上的正投影，所述第二台阶部在衬底502上的正投影覆盖第二部分的靠近所述透明区的边缘在衬底502上的正投影。
例如图8所示中，平坦层505的边缘位置形成两个坡度较小的斜坡，这两个坡度较小的斜坡分别由平坦层505的边缘和钝化层504的边缘形成，第一薄膜电极5061在平坦层505的边缘位置的这两个坡度较小的斜坡位置，分别形成一个较为平缓台阶部，与图7所示的相关技术相比，第一薄膜电极5061在平坦层505的边缘位置上大幅降低了爬坡难度，从而有效降低第一薄膜电极5061出现断裂不良的风险。
在一种可能的实现方式中，凸起部511与平坦层505的厚度比为1:3-1:5。
示例性的，平坦层505的厚度为凸起部511的厚度为凸起部511与平坦层505的厚度比为1:4。
由此，通过对凸起部511的厚度设计，可有效实现对平坦层边缘位置的平缓化，降低第一薄膜电极5061的爬坡难度。
本公开的另一个实施例提供了一种显示装置，包括上述显示面板。其中，显示装置可以为汽车、地铁、火车等交通工具的车窗显示屏，商场、超市的展示橱窗显示屏，广告牌显示屏等具有显示功能的产品或部件，本实施例对此不做限定。
显然，本公开的上述实施例仅仅是为清楚地说明本公开所作的举例，而并非是对本公开的实施方式的限定，对于本领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动，这里无法对所有的实施方式予以穷举，凡是属于本公开的技术方案所引伸出的显而易见的变化或变动仍处于本公开的保护范围之列。

Claims (11)

  1. 一种显示面板，其特征在于，包括衬底及设置在所述衬底上的阵列排布的多个像素，所述像素包括发光区和透明区，所述发光区包括依次设置在所述衬底上的驱动电路层、平坦层、第一电极、发光层和第二电极，所述平坦层的靠近所述透明区的边缘部分在所述衬底上的正投影与所述第一电极在所述衬底上的正投影存在第一交叠区域，所述发光区还包括凸起部，所述凸起部的厚度小于所述平坦层的厚度，所述凸起部相比所述平坦层靠近所述衬底且所述凸起部在所述衬底上的正投影覆盖所述第一交叠区域。
  2. 根据权利要求1所述的显示面板，其特征在于，所述发光区还包括与所述像素电连接的多条信号线，所述信号线形成所述凸起部。
  3. 根据权利要求2所述的显示面板，其特征在于，所述发光区还包括与所述第二电极电连接的辅助电极，所述信号线包括与所述辅助电极电连接的辅助电极走线，所述辅助电极走线设置有延伸部，所述延伸部形成所述凸起部。
  4. 根据权利要求1所述的显示面板，其特征在于，所述凸起部包括第一部分，所述第一部分在所述衬底上的正投影与所述第一交叠区域在所述衬底上的正投影重合，在所述发光区指向所述透明区的方向上，所述第一部分的长度为5μm-20μm。
  5. 根据权利要求4所述的显示面板，其特征在于，所述凸起部还包括第二部分，所述第二部分在所述衬底上的正投影位于所述第一交叠区域的靠近所述透明区一侧。
  6. 根据权利要求5所述的显示面板，其特征在于，所述第一电极包括第一台阶部和第二台阶部，所述第一台阶部在所述衬底上的正投影覆盖所述第一部分与所述第二部分的交界在所述衬底上的正投影，所述第二台阶部在所述衬底上的正投影覆盖所述第二部分的靠近所述透明区的边缘在所述衬底上的正投影。
  7. 根据权利要求5所述的显示面板，其特征在于，在所述发光区指向所 述透明区的方向上，所述第二部分的长度等于所述第一部分的长度。
  8. 根据权利要求1所述的显示面板，其特征在于，所述凸起部与所述平坦层的厚度比为1:3-1:5。
  9. 根据权利要求3所述的显示面板，其特征在于，所述驱动电路层包括依次层叠设置的有源层、栅极绝缘层、薄膜晶体管的栅极、介电层和源漏金属层，所述源漏金属层形成薄膜晶体管的源极和漏极，所述发光区还包括设置于所述驱动电路层与所述平坦层之间的钝化层，所述阳极通过所述钝化层的过孔连接所述源极或漏极。
  10. 根据权利要求9所述的显示面板，其特征在于，所述辅助电极走线与所述源漏金属层同层设置。
  11. 一种显示装置，其特征在于，包括如权利要求1-10中任一项所述的显示面板。
PCT/CN2024/094321 2023-06-13 2024-05-21 显示面板及显示装置 Ceased WO2024255541A1 (zh)

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