WO2024252248A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024252248A1
WO2024252248A1 PCT/IB2024/055386 IB2024055386W WO2024252248A1 WO 2024252248 A1 WO2024252248 A1 WO 2024252248A1 IB 2024055386 W IB2024055386 W IB 2024055386W WO 2024252248 A1 WO2024252248 A1 WO 2024252248A1
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Prior art keywords
layer
transistor
insulating layer
conductive layer
semiconductor
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PCT/IB2024/055386
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English (en)
French (fr)
Japanese (ja)
Inventor
木村肇
大貫達也
山崎舜平
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2025525416A priority Critical patent/JPWO2024252248A1/ja
Priority to KR1020257041107A priority patent/KR20260022310A/ko
Priority to CN202480038591.3A priority patent/CN121336506A/zh
Publication of WO2024252248A1 publication Critical patent/WO2024252248A1/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices.
  • ICs integrated circuits
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a transistor with good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a transistor with high on-state current. Alternatively, an object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance. Alternatively, an object of one embodiment of the present invention is to provide a transistor that can be miniaturized. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device that can be highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.
  • an object of one embodiment of the present invention is to provide a transistor, semiconductor device, memory device, or display device that consumes low power.
  • an object of one embodiment of the present invention is to provide a memory device that operates at high speed.
  • an object of one embodiment of the present invention is to provide a method for manufacturing the transistor, semiconductor device, memory device, or display device.
  • One aspect of the present invention is a transistor having a first insulating layer and a second insulating layer, the transistor having a first conductive layer, a second conductive layer, a first semiconductor layer, a second semiconductor layer, a gate insulating layer and a gate electrode, the second insulating layer being located on the first insulating layer, the second conductive layer being located between the second insulating layer and the first insulating layer, the second semiconductor layer being located between the second conductive layer and the second insulating layer, the second semiconductor layer being in contact with the upper surface of the second conductive layer, and the first insulating layer, the second conductive layer, the second semiconductor layer being in contact with the upper surface of the second conductive layer.
  • the second semiconductor layer and the second insulating layer have an opening that reaches the first conductive layer, the first semiconductor layer contacts the upper surface of the first conductive layer that overlaps the opening, the first semiconductor layer contacts the side of the first insulating layer at the opening, the side of the second conductive layer at the opening, and the side of the second semiconductor layer at the opening, respectively, the gate electrode has a portion located on the second insulating layer, and the gate insulating layer has a portion sandwiched between the first semiconductor layer and the gate electrode within the opening.
  • one aspect of the present invention is a transistor having a first insulating layer and a second insulating layer, the transistor having a first conductive layer, a second conductive layer, a first semiconductor layer, a second semiconductor layer, a gate insulating layer and a gate electrode, the second insulating layer is located on the first insulating layer, the second conductive layer is located between the second insulating layer and the first insulating layer, the second semiconductor layer is located between the second conductive layer and the first insulating layer, the second conductive layer is in contact with the upper surface of the second semiconductor layer, and the first insulating layer, the second conductive layer , the second semiconductor layer, and the second insulating layer have an opening that reaches the first conductive layer, the first semiconductor layer contacts the upper surface of the first conductive layer that overlaps the opening, the first semiconductor layer contacts the side of the first insulating layer at the opening, the side of the second conductive layer at the opening, and the side of the second semiconductor layer at the opening, respectively, the gate electrode has
  • the third semiconductor layer is located between the first insulating layer and the second conductive layer, and the second conductive layer is in contact with the upper surface of the third semiconductor layer.
  • the second semiconductor layer is thicker than the first semiconductor layer.
  • one aspect of the present invention includes a capacitor, a transistor, a first insulating layer, and a second insulating layer, the capacitor having a first conductive layer, a second conductive layer on the first conductive layer, and a third insulating layer located between the first conductive layer and the second conductive layer, the transistor having a second conductive layer, a third conductive layer, a first semiconductor layer, a second semiconductor layer, a gate insulating layer, and a gate electrode, the second insulating layer being located on the first insulating layer, the third conductive layer being located between the second insulating layer and the first insulating layer, the second semiconductor layer being located between the third conductive layer and the second insulating layer, The second semiconductor layer is in contact with the upper surface of the third conductive layer, the first insulating layer, the third conductive layer, the second semiconductor layer, and the second insulating layer have an opening that reaches the second conductive layer, the first semiconductor layer is in contact with the upper surface of the second conductive layer that overlaps
  • one aspect of the present invention includes a capacitor, a transistor, a first insulating layer, and a second insulating layer, where the capacitor has a first conductive layer, a second conductive layer on the first conductive layer, and a third insulating layer located between the first conductive layer and the second conductive layer, and the transistor has a second conductive layer, a third conductive layer, a first semiconductor layer, a second semiconductor layer, a gate insulating layer, and a gate electrode, where the second insulating layer is located on the first insulating layer, the third conductive layer is located between the second insulating layer and the first insulating layer, and the second semiconductor layer is located between the third conductive layer and the first insulating layer, and The third conductive layer is in contact with the upper surface of the second semiconductor layer, the first insulating layer, the third conductive layer, the second semiconductor layer, and the second insulating layer have openings that reach the second conductive layer, the first semiconductor layer is in contact with the upper surface of the second conductive layer
  • the third semiconductor layer is located between the first insulating layer and the third conductive layer, and the third conductive layer is in contact with the upper surface of the third semiconductor layer.
  • the second semiconductor layer is thicker than the first semiconductor layer.
  • a transistor having good electrical characteristics can be provided.
  • a transistor having a large on-state current can be provided.
  • a transistor having a small parasitic capacitance can be provided.
  • a miniaturized transistor can be provided.
  • a semiconductor device, a memory device, or a display device that can be highly integrated can be provided.
  • a highly reliable transistor, a semiconductor device, a memory device, or a display device can be provided.
  • a transistor, a semiconductor device, a memory device, or a display device that consumes low power can be provided.
  • a memory device that operates at a high speed can be provided.
  • a method for manufacturing the above transistor, semiconductor device, memory device, or display device can be provided.
  • Fig. 1A is a plan view showing an example of a semiconductor device
  • Figs. 1B to 1E are cross-sectional views showing an example of the semiconductor device
  • Fig. 2A is a plan view showing an example of a semiconductor device
  • Fig. 2B and Fig. 2C are cross-sectional views showing an example of the semiconductor device
  • Fig. 3A is a plan view showing an example of a semiconductor device
  • Figs. 3B to 3E are cross-sectional views showing an example of the semiconductor device
  • 4A to 4F are cross-sectional views showing an example of a semiconductor device
  • Fig. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5A is a plan view showing an example of a semiconductor device
  • Figs. 5A is a plan view showing an example of
  • FIG. 5B and 5C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 6A is a plan view showing an example of a semiconductor device
  • Figs. 6B and 6C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 7A is a plan view showing an example of a semiconductor device
  • Figs. 7B and 7C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 8A is a plan view showing an example of a semiconductor device
  • Figs. 8B and 8C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 9A is a plan view showing an example of a semiconductor device
  • Figs. 9B and 9C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 10A is a plan view showing an example of a semiconductor device
  • Fig. 10B and Fig. 10C are cross-sectional views showing an example of the semiconductor device
  • Fig. 11A is a plan view showing an example of a semiconductor device
  • Fig. 11B and Fig. 11C are cross-sectional views showing an example of the semiconductor device
  • Fig. 12A is a plan view showing an example of a semiconductor device
  • Fig. 12B and Fig. 12C are cross-sectional views showing an example of the semiconductor device
  • 13A to 13D are diagrams illustrating cross sections of an oxide semiconductor
  • 14A to 14D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • Fig. 10A is a plan view showing an example of a semiconductor device
  • Fig. 10B and Fig. 10C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 11A is a plan view showing an example of a semiconductor device
  • FIG. 15A is a plan view showing an example of a storage device
  • Figs. 15B and 15C are cross-sectional views showing an example of the storage device.
  • 16A is a plan view of an example of a storage device
  • FIG 16B is a cross-sectional view of the example of the storage device.
  • 17A to 17E are cross-sectional views illustrating an example of a memory device.
  • 18A to 18D are cross-sectional views illustrating an example of a memory device.
  • Fig. 19A is a plan view of an example of a storage device
  • Figs. 19B and 19C are cross-sectional views of an example of the storage device.
  • Fig. 20A is a plan view of an example of a storage device
  • FIG. 20C are cross-sectional views of an example of the storage device.
  • Fig. 21A is a plan view showing an example of a storage device
  • Fig. 21B and Fig. 21C are cross-sectional views showing an example of the storage device.
  • 22A is a plan view illustrating an example of a transistor included in a memory device
  • FIGS. 22B and 22C are cross-sectional views illustrating an example of a transistor included in a memory device.
  • FIG. 23 is a cross-sectional view showing an example of a storage device.
  • FIG. 24 is a cross-sectional view showing an example of a storage device.
  • FIG. 25 is a block diagram illustrating a configuration example of a semiconductor device.
  • FIG. 26A to 26H are diagrams for explaining examples of the circuit configuration of a memory cell.
  • FIG. 27 is a diagram for explaining an example of a circuit configuration of a memory cell.
  • 28A and 28B are perspective views illustrating a configuration example of a semiconductor device.
  • FIG. 29 is a block diagram illustrating the CPU.
  • 30A and 30B are perspective views of a semiconductor device.
  • 31A and 31B are perspective views of a semiconductor device.
  • 32A and 32B are diagrams showing various storage devices by hierarchical level.
  • Fig. 33A is a block diagram showing a configuration example of a display device
  • Fig. 33B is a plan view showing a configuration example of a pixel
  • Fig. 33C is a circuit diagram showing a configuration example of a pixel.
  • Fig. 33A is a block diagram showing a configuration example of a display device
  • Fig. 33B is a plan view showing a configuration example of a pixel
  • Fig. 33C
  • FIG. 34A is a block diagram showing a configuration example of a drive circuit
  • Fig. 34B and Fig. 34C are circuit diagrams showing configuration examples of a drive circuit.
  • FIG. 35 is a block diagram showing an example of the configuration of a display device.
  • 36A and 36B are diagrams illustrating an example of an electronic component.
  • Fig. 37A to Fig. 37C are diagrams showing an example of a mainframe computer
  • Fig. 37D is a diagram showing an example of space equipment
  • Fig. 37E is a diagram showing an example of a storage system applicable to a data center.
  • 38A to 38F are diagrams showing an example of an electronic device.
  • 39A to 39G are diagrams showing an example of an electronic device.
  • 40A to 40F are diagrams showing an example of an electronic device.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • a transistor using an oxide semiconductor or a metal oxide in a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor.
  • a transistor having silicon in a channel formation region may be referred to as a Si transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a transistor has a region (also called a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and drain through the channel formation region.
  • a channel formation region refers to a region through which a current mainly flows.
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • the impurity of a semiconductor refers to, for example, anything other than the main component constituting the semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be said to be an impurity.
  • the defect level density of the semiconductor may increase or the crystallinity may decrease.
  • the semiconductor is an oxide semiconductor
  • examples of the impurity that changes the characteristics of the semiconductor include, for example, a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and a transition metal other than the main component of the oxide semiconductor.
  • Specific examples of the impurity include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • water may also function as an impurity.
  • oxygen vacancies also referred to as V O
  • V O oxygen vacancies
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • SIMS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more).
  • SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less).
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • the top surface shape of a certain component refers to the contour shape of the component in a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • top surface shapes roughly match refers to at least a portion of the contours of the stacked layers overlapping. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it may also be said that the top surface shapes roughly match. In addition, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned, or that the side edges are aligned or roughly matched. Note that in this specification, the phrase “edges match” refers to at least a portion of the contours of the stacked layers overlapping in a plan view.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • A covers B
  • at least a part of A covers B. Therefore, for example, it can be rephrased as saying that A has an area that covers B.
  • arrows indicating the X direction, Y direction, and Z direction may be used.
  • the "X direction” is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated.
  • the X direction, Y direction, and Z direction are directions that intersect with each other.
  • the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • FIG. 1A is a plan view of a semiconductor device including a transistor 200.
  • FIG. 1B is a cross-sectional view corresponding to dashed dotted line A1-A2 in FIG. 1A.
  • FIG. 1C is a cross-sectional view corresponding to dashed dotted line A3-A4 in FIG. 1A. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.
  • FIGS. 2A to 2C show an example in which the transistors 200 shown in FIGS. 1A to 1C are arranged in two rows and two columns.
  • the row direction is, for example, the X direction
  • the column direction is, for example, the Y direction.
  • FIG. 2A is a plan view of a semiconductor device having four transistors 200.
  • FIG. 2B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 2A.
  • FIG. 2C is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 2A.
  • FIGS. 1A to 1C show an example in which the transistors 200 shown in FIGS. 1A to 1C are arranged in two rows and two columns.
  • the row direction is, for example, the X direction
  • the column direction is, for example, the Y direction.
  • FIG. 2A is a plan view of a semiconductor device having four transistors 200.
  • FIG. 2B is
  • the conductive layer 240 and the semiconductor layer 235 each extend in the X direction, and the conductive layer 240 is shared by the transistors 200 adjacent in the X direction.
  • the conductive layer 260 extends in the Y direction, and the conductive layer 260 is shared by the transistors 200 adjacent in the Y direction.
  • the semiconductor device shown in Figures 1A to 1C includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, and an insulating layer 280, an insulating layer 281, and an insulating layer 283 on the insulating layer 210.
  • the insulating layer 210, the insulating layer 280, and the insulating layer 283 function as interlayer films. Note that the insulating layer 280 and the insulating layer 281 may be considered as components of the transistor 200.
  • the transistor 200 has a conductive layer 220, a conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • An insulating layer 280 is located on the conductive layer 220
  • a conductive layer 240 is located on the insulating layer 280
  • an insulating layer 281 is located on the conductive layer 240 and the insulating layer 280.
  • the conductive layer 220 and the conductive layer 240 are located at different heights with the insulating layer 280 sandwiched between them.
  • the transistor 200 has a semiconductor layer 235 on the conductive layer 240.
  • an opening 290 that reaches the conductive layer 220 is provided in the insulating layer 280, the conductive layer 240, the semiconductor layer 235, and the insulating layer 281.
  • the bottom of the opening 290 is, for example, the upper surface of the conductive layer 220.
  • At least some of the components of the transistor 200 are disposed inside the opening 290.
  • the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least a portion of each of them is located inside the opening 290.
  • the semiconductor layer 230 contacts the top surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 240, the side surface of the semiconductor layer 235, and the side surface of the insulating layer 281.
  • the semiconductor layer 230 may also be provided outside the opening 290.
  • the semiconductor layer 230 may be provided on the insulating layer 281.
  • the semiconductor layer 230 functions as a semiconductor layer
  • the conductive layer 260 functions as a gate electrode
  • the insulating layer 250 functions as a gate insulating layer.
  • the conductive layer 220 functions as one of the source electrode and drain electrode, and the conductive layer 240 functions as the other of the source electrode and drain electrode.
  • the semiconductor layer 230 is in contact with the upper surface of the conductive layer 220.
  • the semiconductor layer 230 is in contact with the side surface of the conductive layer 240. Since one of the source electrode and drain electrode (conductive layer 220 in this case) is located on the lower side and the other of the source electrode and drain electrode (conductive layer 240 in this case) is located on the upper side, a current flows in the vertical direction in the semiconductor layer 230. In other words, a channel is formed along the side wall of the opening 290.
  • the regions of the semiconductor layer 230 that are in contact with the conductive layer 220 and the conductive layer 240 preferably function as low resistance regions.
  • the contact resistance between the conductive layer 220 and the conductive layer 240 and the semiconductor layer 230 can be reduced.
  • the low resistance regions may reduce the electric field between the gate and the drain, thereby improving the reliability of the transistor.
  • the semiconductor layer 235 and the conductive layer 240 are in contact with each other.
  • the semiconductor layer 235 is in contact with the top surface of the conductive layer 240.
  • the side surface of the semiconductor layer 235 is in contact with the semiconductor layer 230, so that the current flowing between the source and drain of the transistor can also flow to the semiconductor layer 235. Therefore, in the transistor of one embodiment of the present invention, for example, the current flowing between the conductive layer 240 and the conductive layer 220 can flow from the conductive layer 240 to the conductive layer 220 via the semiconductor layer 235 and the semiconductor layer 230 in this order.
  • the semiconductor layer 235 Since the semiconductor layer 235 is in contact with the top surface of the conductive layer 240, the contact area with the conductive layer 240 can be increased more easily than with the semiconductor layer 230, which is in contact only with the side surface of the conductive layer 240. Therefore, by having the semiconductor layer 235 in the transistor 200, the contact resistance between the semiconductor layer and the conductive layer 240 can be reduced.
  • the semiconductor layer 230 and the semiconductor layer 235 can each have an n-type region (low resistance region) that has a higher carrier concentration than the channel formation region. The n-type region can function as a source region or a drain region.
  • the semiconductor layer 235 can be made of the same materials, compositions, crystal structures, etc. that can be used as the semiconductor layer 230.
  • the semiconductor layer 235 can be made of a material, composition, crystal structure, etc. that can be used as any of the laminated films of the semiconductor layer 230.
  • the semiconductor layer 235 can be made of the same material, composition, crystal structure, etc. as the layer in contact with the semiconductor layer 230.
  • the semiconductor layer 235 is preferably thicker than the semiconductor layer 230. By making the semiconductor layer 235 thicker, the contact area with the semiconductor layer 230 can be increased.
  • FIG. 1A shows an example in which the top surface shapes of the conductive layer 240 and the semiconductor layer 235 are the same or approximately the same.
  • the conductive layer 240 and the semiconductor layer 235 are formed using the same mask, for example, the top surface shapes of the conductive layer 240 and the semiconductor layer 235 can be the same or approximately the same. By forming them using the same mask, the manufacturing process can be simplified.
  • the transistor of one embodiment of the present invention also has an insulating layer 281.
  • the insulating layer 281 thick, the physical distance between the conductive layer 240 and the conductive layer 260 can be increased, and therefore the wiring resistance between the conductive layer 240 and the conductive layer 260 can be reduced. In addition, the leakage current between the conductive layer 240 and the conductive layer 260 can be extremely reduced.
  • each layer constituting the opening 290 preferably form a continuous surface.
  • the side surfaces of each layer form a step, it is preferable that the unevenness of the step is small.
  • the film thickness distribution of the semiconductor layer 230 provided inside the opening 290 can be made uniform.
  • the width of the opening 290 in a cross-sectional view may vary in the depth direction.
  • the width of the opening 290 may be, for example, the width at the top end of each layer in which the opening 290 is provided, the width at the bottom end, the width at half the depth of the layer, etc.
  • the insulating layer 250 is provided in the opening 290 in contact with the upper surface of the semiconductor layer 230. Also, in FIG. 1C, the insulating layer 250 has a region in contact with the upper surface of the insulating layer 281.
  • the insulating layer 250 functions as a gate insulating layer for the transistor 200. By making the gate insulating layer thin, it is possible to reduce the gate potential applied when the transistor 200 is operating. In addition, it is possible to operate the transistor 200 at high speed.
  • the sidewalls of the opening 290 can be, for example, vertical. Alternatively, the sidewalls of the opening 290 can be tapered.
  • the sidewall of the opening 290 can be made steep, and the semiconductor device can be highly integrated.
  • the angle between the top surface of the insulating layer 210 and the sidewall of the opening 290 less than 60 degrees, the coverage of the sidewall of the opening 290 by the semiconductor layer, insulating layer, conductive layer, etc. of the transistor 200 can be improved.
  • the sidewall of the opening 290 may have an inverse tapered shape.
  • the angle between the sidewall of the opening 290 and the top surface of the insulating layer 210 may be greater than 90 degrees.
  • FIG. 3A is a plan view of a semiconductor device having a transistor 200
  • FIG. 3B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 3A
  • FIG. 3C is a cross-sectional view corresponding to the dashed line A3-A4 shown in FIG. 3A.
  • the end of the semiconductor layer 235 located on the opposite side of the opening 290 is located inside the end of the conductive layer 240.
  • the end of the semiconductor layer 235 located on the opposite side of the opening 290 is located outside the end of the conductive layer 240.
  • the end of the semiconductor layer 235 covers the end of the conductive layer 240.
  • FIG. 1D is a cross-sectional view corresponding to the dashed line A1-A2 shown in Figure 1A, and differs from Figure 1B in the stacking order of the conductive layer 240 and the semiconductor layer 235.
  • Figure 1E is a cross-sectional view corresponding to the dashed line A3-A4 shown in Figure 1A, and differs from Figure 1C in the stacking order of the conductive layer 240 and the semiconductor layer 235.
  • the semiconductor layer 235 is disposed on the conductive layer 240, for example, the lower part of the semiconductor layer 235 contacts the conductive layer 240.
  • the transistor 200 shown in Figures 1D and 1E has a conductive layer 220, an insulating layer 280 on the conductive layer 220, a semiconductor layer 235 on the insulating layer 280, a conductive layer 240 on the semiconductor layer 235, an insulating layer 281 on the conductive layer 240 and on the insulating layer 280, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • FIG. 3D shows a configuration in which the stacking order of the semiconductor layer 235 and the conductive layer 240 in FIG. 3B is reversed
  • FIG. 3E shows a configuration in which the stacking order of the semiconductor layer 235 and the conductive layer 240 in FIG. 3C is reversed.
  • FIG. 4A and 4B show an example in which the semiconductor device has a semiconductor layer 237 in addition to the configurations shown in Fig. 1B and 1C.
  • Fig. 4A differs from Fig. 1B mainly in that the semiconductor layer 237 is provided between the conductive layer 240 and the insulating layer 281.
  • Fig. 4B differs from the configuration shown in Fig. 1C mainly in that the semiconductor layer 237 is provided between the conductive layer 240 and the insulating layer 281.
  • the transistor 200 shown in Figures 4A and 4B has a conductive layer 220, a semiconductor layer 237, a conductive layer 240 on the semiconductor layer 237, a semiconductor layer 235 on the conductive layer 240, a semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.
  • An insulating layer 280 is located on the conductive layer 220
  • a conductive layer 240 is located on the insulating layer 280
  • an insulating layer 281 is located on the conductive layer 240 and the insulating layer 280.
  • An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280, the semiconductor layer 237, the conductive layer 240, the semiconductor layer 235, and the insulating layer 281.
  • the semiconductor layer 237 can have an n-type region (low resistance region) with a higher carrier concentration than the channel formation region.
  • the n-type region can function as a source region or a drain region.
  • the semiconductor layer 237 can be made of the same materials, compositions, crystal structures, etc. that can be used as the semiconductor layer 230.
  • the semiconductor layer 237 can be made of a material, composition, crystal structure, etc. that can be used as any of the laminated films of the semiconductor layer 230.
  • the semiconductor layer 237 can be made of the same material, composition, crystal structure, etc. as the layer in contact with the semiconductor layer 230.
  • semiconductor layer 237 is thicker than semiconductor layer 230. By making the semiconductor layer thicker, the contact area with semiconductor layer 230 can be increased.
  • the side of the insulating layer 280 and the side of the semiconductor layer 237 coincide or roughly coincide on the sidewall of the opening 290. It is also preferable that the side of the semiconductor layer 237 and the side of the conductive layer 240 coincide or roughly coincide on the sidewall of the opening 290.
  • the top surface shapes of the semiconductor layer 237, the conductive layer 240, and the semiconductor layer 235 do not have to match.
  • the semiconductor device shown in Fig. 4E has a different shape of the conductive layer 260 from the configuration shown in Fig. 1B.
  • the conductive layer 260 is formed to fill the opening 290.
  • the thickness of the conductive layer 260 can be increased, so that the wiring resistance of the conductive layer 260 can be reduced.
  • the unevenness of the portion of the conductive layer 260 that overlaps with the opening 290 is small, so that the coverage of the film formed thereon can be improved.
  • a conductive layer 265 is provided so as to fill the recess in the conductive layer 260 that covers the opening 290.
  • the conductive layer 265 is electrically connected to the conductive layer 260.
  • the conductive layer 265 is preferably in contact with the conductive layer 260.
  • the conductive layer 265 can function as, for example, an auxiliary wiring for the conductive layer 260.
  • the auxiliary wiring has, for example, an effect of reducing wiring resistance.
  • the conductive layer 265 may be thick in the region overlapping with the opening 290, and may have low wiring resistance.
  • the conductive layer 265 may also be made of a material with lower resistance than the conductive layer 260.
  • FIG. 5A to 5C show modified examples of the semiconductor device shown in Fig. 2A to 2C.
  • the semiconductor device shown in Fig. 5A to 5C mainly differs from Fig. 2A to 2C in that the end of the semiconductor layer 230 is located outside the end of the conductive layer 260 in the cross section along A1-A2.
  • the area of the semiconductor layer 230 is smaller than that of the configurations of Fig. 6A to 6C, etc., which will be described later, so that the arrangement density of the semiconductor layer 230 of the semiconductor device can be reduced. Therefore, oxygen can be more easily supplied to the semiconductor layer 230.
  • FIG. 6A to 6C show modified examples of the semiconductor device shown in Fig. 2A to 2C.
  • the semiconductor device shown in Fig. 6A to 6C mainly differs from Fig. 2A to 2C in that the semiconductor layer 230 of two adjacent transistors 200 is shared in the cross section taken along A1-A2. In the cross section taken along A1-A2, the semiconductor layer 230 is provided across a plurality of transistors 200 arranged in the X direction. Increasing the area of the semiconductor layer 230 may facilitate processing of the semiconductor layer 230.
  • the end of the semiconductor layer 230 is located outside the end of the conductive layer 240 on the opposite side from the opening 290, but the position of the end of the semiconductor layer 230, for example the Y coordinate here, may coincide with the position of the end of the conductive layer 240, for example the Y coordinate.
  • FIG. 7A to 7C show modified examples of the semiconductor device shown in FIG. 5A to 5C.
  • the semiconductor layer 230 is not in contact with the sidewall of the opening 290 and the upper surface of the insulating layer 281 in the cross section taken along A3-A4.
  • the semiconductor layer 230 covers the upper surface of the conductive layer 220 in the opening 290. That is, in the configuration shown in FIG. 7A to 7C, the main difference is the shape of the semiconductor layer 230 in the opening 290 compared to FIG. 5A to 5C.
  • the end of the semiconductor layer 230 is located outside the opening 290 in the cross section taken along A1-A2, and is located inside the opening 290 in the cross section taken along A3-A4. Since the overlapping area between the conductive layer 260 functioning as a gate electrode and the semiconductor layer 230 is reduced, the parasitic capacitance between the gate and the semiconductor layer is reduced when the potential of the gate is increased from a low potential to a high potential, and the operating speed of the semiconductor device can be improved.
  • FIGS. 8A to 8C show modified examples of the semiconductor device shown in FIGS. 7A to 7C.
  • the semiconductor device shown in FIGS. 8A to 8C mainly differs from FIGS. 5A to 5C in that the semiconductor layer 230 of two adjacent transistors 200 is shared in the cross section taken along A1-A2. In the cross section taken along A1-A2, the semiconductor layer 230 is provided across a plurality of transistors 200 arranged in the X direction. Increasing the area of the semiconductor layer 230 may facilitate processing of the semiconductor layer 230. In addition, the parasitic capacitance between the conductive layer 260 and the semiconductor layer 230 can be reduced.
  • 9A to 9C show modified examples of the semiconductor device shown in FIGS. 2A to 2C.
  • the semiconductor device shown in FIGS. 9A to 9C is mainly different from the semiconductor device shown in FIGS. 2A to 2C in that the semiconductor layer 230 covers only a part of the sidewall of the opening 290. Since the area of the channel formation region in the semiconductor layer 230 is reduced, the parasitic capacitance of the channel can be reduced. As described later, in a memory device, when the transistor 200 is electrically connected to a capacitor, the influence of the parasitic capacitance of the channel can be reduced in a switching operation for writing charge to the capacitor, and noise in the memory device can be reduced.
  • the semiconductor layer 230 covers only one sidewall in the X direction in the opening 290, and the other sidewall is covered by the insulating layer 250 and the conductive layer 260 but is not covered by the semiconductor layer 230.
  • the semiconductor layer 230 also covers only a portion of the conductive layer 220 at the bottom of the opening 290.
  • the semiconductor layer 230 covers only one sidewall in the Y direction in the opening 290, and the other sidewall is covered by the insulating layer 250 and the conductive layer 260 but is not covered by the semiconductor layer 230.
  • 10A to 10C show modified examples of the semiconductor device shown in FIG. 2A to 2C.
  • the semiconductor device shown in FIG. 10A to 10C mainly differs from the semiconductor device shown in FIG. 2A to 2C in that the semiconductor layer 230 covers only a part of the sidewall of the opening 290 and that the top surface shape of the opening 290 is substantially rectangular rather than circular.
  • the overlapping area of the conductive layer 220 and the conductive layer 260 can be reduced, and parasitic capacitance can be reduced.
  • the opening 290 is arranged to overlap an end of the conductive layer 240 functioning as a bit line in a top view. Therefore, the line width of the conductive layer 240 can be suppressed from being narrowed. Since the influence of the opening 290 on the line width of the conductive layer 240 can be reduced, a decrease in the wiring resistance of the bit line can be suppressed.
  • the width of the conductive layer 220 is narrower than the width of the opening 290, and the conductive layer 220 is disposed inside the opening 290.
  • the semiconductor layer 230 covers the upper surface of the conductive layer 220, the side surface of the conductive layer 220, and the upper surface of the insulating layer 210 at the bottom of the opening 290.
  • the sidewall of the opening 290 is covered by the insulating layer 250 and the conductive layer 260 but is not covered by the semiconductor layer 230.
  • the semiconductor layer 230 covers only one sidewall in the Y direction in the opening 290, and the other sidewall is covered by the insulating layer 250 and the conductive layer 260 but is not covered by the semiconductor layer 230.
  • 11A to 11C show modified examples of the semiconductor device shown in Fig. 2A to 2C.
  • the semiconductor device shown in Fig. 11A to 11C mainly differs from the semiconductor device shown in Fig. 2A to 2C in that the opening 290 is rectangular and extends in the Y direction, and is provided across a plurality of transistors 200. Since the opening 290 is shaped to connect adjacent transistors 200, even if the width of the opening 290 is narrowed, processing is easy. Therefore, the integration density of the semiconductor device may be increased.
  • the opening 290 is provided extending in the Y direction. Since the opening 290 is provided to traverse the conductive layer 240, the conductive layer 240 is divided by the opening 290.
  • An insulating layer 285 is provided on the insulating layer 283, and plugs 244a and 244b are provided in the openings of the insulating layer 285, the insulating layer 283, the insulating layer 250, and the insulating layer 281.
  • the plugs 244a and 244b are electrically connected by the conductive layer 245 provided on the insulating layer 285.
  • the divided conductive layer 240 is electrically connected via the plug 244a, the conductive layer 245, and the plug 244b.
  • the conductive layers 240 of the multiple transistors 200 arranged in the X direction are electrically connected to each other by the conductive layer 245 and plugs provided in the openings of the insulating layer 285, the insulating layer 283, the insulating layer 250, and the insulating layer 281.
  • 12A to 12C show modified examples of the semiconductor device shown in FIG. 2A to 2C.
  • the semiconductor device shown in FIG. 12A to 12C mainly differs from the semiconductor device shown in FIG. 2A to 2C in that the opening 290 has a rectangular shape extending in the Y direction and is provided across a plurality of transistors 200, and that the upper surface of the conductive layer 260 is flattened. Since the conductive layer 260 and the conductive layer 240 do not overlap each other in a top view, parasitic capacitance can be reduced. Therefore, the rounding of the signal waveform of the word line can be reduced. Therefore, for example, the operating speed of the semiconductor device can be increased.
  • the opening 290 is provided so as to extend in the Y direction. Furthermore, since the width of the opening 290 in the X direction is wider than the width of the conductive layer 260 in the X direction, the conductive layer 260 is provided so as to be embedded in the opening 290. Furthermore, it is preferable that the conductive layer 260 is planarized so as to be roughly aligned with the upper surface of the insulating layer 281.
  • the opening 290 is provided to cut across the conductive layer 240, and the conductive layer 240 is divided by the opening 290.
  • the conductive layers 240 of the transistors 200 arranged in the X direction are electrically connected to each other by the insulating layer 285, the insulating layer 283, the insulating layer 250, and plugs (plugs 244a and 244b in FIG. 12B) provided in the openings of the insulating layer 281, and the conductive layer 245.
  • Fig. 14A to Fig. 14D show cross sections corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 1A.
  • an insulating layer 210 is formed on the substrate.
  • the conductive layer 220 is formed on the insulating layer 210.
  • an insulating layer 280 is formed on the insulating layer 210 and the conductive layer 220. After the insulating layer 280 is formed, a planarization process may be performed to planarize the upper surface. Next, a conductive layer that will become the conductive layer 240 and a semiconductor layer that will become the semiconductor layer 235 are formed in this order on the insulating layer 280. Next, a mask is used to remove a part of the semiconductor layer that will become the semiconductor layer 235, to form the semiconductor layer 235. Then, a mask is used to remove a part of the conductive layer that will become the conductive layer 240, to form the conductive layer 240 (FIG. 14A).
  • the mask used to form the conductive layer 240 and the mask used to form the semiconductor layer 235 may be the same mask or different masks.
  • an insulating layer 281 is formed on the semiconductor layer 235 and the insulating layer 280.
  • a mask is used to remove a portion of the insulating layer 281, a portion of the semiconductor layer 235, a portion of the conductive layer 240, and a portion of the insulating layer 280, to form an opening 290 in the area overlapping with the conductive layer 220 ( Figure 14B).
  • a semiconductor layer that will become semiconductor layer 230 is formed so as to cover the sidewall of opening 290, the upper surface of conductive layer 220, and the upper surface of insulating layer 281. After that, in the semiconductor layer that will become semiconductor layer 230, the regions located on insulating layer 281, etc. are removed to form semiconductor layer 230 (FIG. 14C).
  • an insulating layer 250 is formed on the semiconductor layer 230 and the insulating layer 281.
  • a conductive layer 260 is formed on the insulating layer 250.
  • an insulating layer 281 is formed on the conductive layer 260 and the insulating layer 281 ( Figure 14D).
  • the semiconductor device shown in Figures 1B and 1C can be manufactured.
  • the transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 230 including a channel formation region. That is, the transistor 200 is preferably an OS transistor.
  • a metal oxide also referred to as an oxide semiconductor
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, hydrogen near the oxygen vacancies may form a defect in which hydrogen is inserted into the oxygen vacancies (hereinafter sometimes referred to as VOH ), and may generate electrons that serve as carriers. For this reason, when oxygen vacancies are present in the channel formation region in the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the region of the semiconductor layer 230 in contact with the insulating layer 280 and its vicinity function as the channel formation region of the transistor 200.
  • One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region.
  • the channel formation region is sandwiched between the source region and the drain region.
  • the semiconductor layer 230 and the conductive layer 220 when the semiconductor layer 230 and the conductive layer 220 are in contact with each other, a metal compound or oxygen vacancy is formed, and the region of the semiconductor layer 230 in contact with the conductive layer 220 has low resistance. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220.
  • the semiconductor layer 230 and the conductive layer 240 when the semiconductor layer 230 and the conductive layer 240 are in contact with each other, the region of the semiconductor layer 230 in contact with the conductive layer 240 has low resistance. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 240.
  • the semiconductor layer 235 and the semiconductor layer 237 are each semiconductor layers that are in contact with the conductive layer 240, and it is preferable that the contact region has low resistance.
  • the semiconductor layer 235 and the semiconductor layer 237 each have a metal oxide that functions as a semiconductor, a metal compound or oxygen vacancy is formed by contacting the conductive layer 240, and the resistance of the semiconductor layer region that is in contact with the conductive layer 240 can be reduced.
  • the channel formation region of the transistor 200 can be formed in the entire region of the semiconductor layer 230 in the opening 290 that contacts the insulating layer 280.
  • the channel length of the transistor 200 is, for example, the distance between the source region and the drain region.
  • the channel length of the transistor 200 can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220.
  • the channel length is the distance between the end of the region where the semiconductor layer 230 and the conductive layer 220 contact each other and the end of the region where the semiconductor layer 230 and the conductive layer 240 contact each other in a cross-sectional view.
  • the channel length corresponds to the length of the side of the insulating layer 280 on the opening 290 side in a cross-sectional view.
  • the region of the semiconductor layer 230 near the conductive layer 220 may function as a source region or drain region rather than a channel formation region.
  • the channel length of the transistor 200 is the sum of the thickness of the insulating layer 280 on the conductive layer 220 and the thickness of the semiconductor layer 235.
  • the channel length of the transistor 200 can be regarded as, for example, the thickness of the insulating layer 280 on the conductive layer 220.
  • the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult.
  • the channel length can be set by the thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, and improves the frequency characteristics.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more.
  • the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is determined by, for example, the thickness of the insulating layer 280 on the conductive layer 220. Therefore, even when the channel length is increased to 60 nm or more, the occupation area of the transistor, specifically, for example, the area of the transistor as viewed from the top, is roughly determined according to the width of the opening 290. As described later, the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the width of the opening 290 can be narrower than 150 nm. That is, the transistor can have an opening width narrower than the channel length, which reduces the occupation area of the transistor and enables high integration of the semiconductor device.
  • the channel length of the transistor is set to, for example, 1 ⁇ m or less, 500 nm or less, or 300 nm or less, it is possible to improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, etc.
  • the channel length of a transistor in a semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 ⁇ m or less, 500 nm or less, or 300 nm or less.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the area occupied by the transistor 200 can be reduced compared to a horizontal transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
  • the channel width of the transistor 200 can be said to be determined by the width of the opening 290 (the diameter if the opening 290 is circular in plan view).
  • the width of the opening 290 By increasing the width of the opening 290, the channel width per unit area can be increased, and the on-current can be increased.
  • the width D of the opening 290 is limited by the exposure limit of photolithography.
  • the width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290.
  • the width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the width of the opening 290 corresponds to the diameter of the opening 290, and the channel width is the length of the circumference.
  • the channel length of the transistor 200 is at least smaller than the channel width of the transistor 200.
  • the channel length of the transistor 200 is preferably 0.1 times or more and 0.99 times or less, more preferably 0.5 times or more and 0.8 times or less, of the channel width of the transistor 200.
  • the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 230 roughly uniform, so that a gate electric field can be applied roughly uniformly to the semiconductor layer 230.
  • the opening 290 is not limited to a circular shape in plan view.
  • it may be a roughly circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape such as a rectangle with rounded corners.
  • Each layer constituting the semiconductor device of this embodiment may have a single layer structure or a multilayer structure.
  • an inorganic insulating film is preferably used for the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 283, insulating layer 285, etc.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for the insulating layer of the semiconductor device.
  • an insulating layer having a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • a barrier insulating layer against impurities such as water and hydrogen, and oxygen.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse, a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, a function of suppressing the diffusion of a corresponding substance, or a function of suppressing the permeation of a corresponding substance.
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when impurities are described as a corresponding substance, they refer to impurities in a channel formation region or a semiconductor layer, unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • Other examples include oxides containing aluminum and hafnium (hafnium aluminate).
  • Other examples include metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.
  • an insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced.
  • Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • materials with a low relative dielectric constant examples include resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 may be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include materials in which an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples of materials that can have ferroelectricity, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulating layer 130 can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • Metal oxides containing hafnium and/or zirconium can have ferroelectricity even when processed into thin films of a few nm.
  • metal oxides containing hafnium and/or zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing hafnium and/or zirconium, it is possible to miniaturize semiconductor devices.
  • a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer.
  • a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device.
  • ferroelectricity is expressed by the displacement of oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed.
  • the crystal structure of the crystals contained in the insulating layer may be one or more selected from the cubic, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems.
  • the insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.
  • the insulating layer 250 functions as a gate insulating layer for the transistor 200. It is preferable to use a material with a high dielectric constant for the insulating layer 250.
  • the insulating layer 250 preferably has a function of capturing and fixing hydrogen. This can reduce the hydrogen concentration, particularly in the channel formation region of the semiconductor layer of the transistor. Thus, VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type.
  • the material of the insulating layer having the function of capturing or fixing hydrogen includes metal oxides such as oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing magnesium. These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • the insulating layer 250 has a layered structure, it is preferable to use a layer that has the function of capturing and fixing hydrogen in one of the layers (hereinafter referred to as the first insulating layer of the insulating layer 250).
  • the insulating layer by suppressing the formation of grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels in the grain boundaries. This allows the insulating layer to function as an insulating film with low leakage current.
  • hafnium oxide is a material with a high dielectric constant
  • hafnium silicate can also be a material with a high dielectric constant depending on the silicon content. Therefore, when used as a gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.
  • EOT equivalent oxide thickness
  • an oxide containing one or both of aluminum and hafnium as the first insulating layer of the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the insulating layer 250 preferably uses a barrier insulating layer against hydrogen as the second insulating layer.
  • a barrier insulating layer against hydrogen As the second insulating layer of the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 260 to layers below the insulating layer 250 in the transistor 200.
  • Silicon nitride has high barrier properties against hydrogen and is therefore suitable as the insulating layer 250.
  • Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.
  • the second insulating layer is preferably an upper layer of the first insulating layer.
  • the insulating layer 250 has a layer capable of supplying oxygen.
  • An oxide can be used as the layer capable of supplying oxygen.
  • oxygen can be suitably supplied from the insulating layer 250 to the semiconductor layer 230.
  • silicon oxide or silicon oxynitride has a structure that is stable against heat, and therefore can be suitably used as the insulating layer 250.
  • the insulating layer 250 may have an insulating layer with a thermally stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 250 has a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 240, the conductive layer 260, etc.
  • the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 are each a barrier insulating layer against oxygen.
  • the layer in the insulating layer 250 that contacts the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280.
  • the layer has a barrier property against oxygen, which can prevent the side surface of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-current of the transistor 200 or a decrease in the field effect mobility.
  • oxidation of the conductive layer 260 can be suppressed.
  • Examples of the barrier insulating layer against oxygen include oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • silicon nitride is also an excellent insulating layer that has high barrier properties against hydrogen, as mentioned above.
  • the insulating layer 250 it is preferable to use a two-layer structure in which, from the semiconductor layer 230 side, a first insulating layer having the function of capturing or fixing hydrogen and a second insulating layer having barrier properties against hydrogen and oxygen are stacked in this order.
  • the first insulating layer can be an oxide containing one or both of aluminum and hafnium
  • the second insulating layer can be silicon nitride
  • a third insulating layer having a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having barrier properties against hydrogen and oxygen are stacked in this order as the insulating layer 250.
  • the material with a relatively low dielectric constant of the third insulating layer refers to, for example, a material with a lower dielectric constant than any one or more of the other layers in the stacked structure.
  • an oxide can be used as the third insulating layer.
  • silicon oxide or silicon oxynitride is used.
  • the second insulating layer it is possible to suppress the diffusion of oxygen contained in the third insulating layer into the conductive layer 260, and to suppress the oxidation of the conductive layer 260. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230.
  • silicon oxide or silicon oxynitride can be used as the third insulating layer
  • an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer
  • silicon nitride can be used as the second insulating layer.
  • the insulating layer 250 it is preferable to use a four-layer structure in which, from the semiconductor layer 230 side, a fourth insulating layer having a barrier property against oxygen, a third insulating layer having a material with a relatively low dielectric constant, a first insulating layer having a function of capturing or fixing hydrogen, and a second insulating layer having a barrier property against hydrogen and oxygen are stacked in this order.
  • the first insulating layer to the third insulating layer can have a structure similar to that of the layers used in the three-layer structure described above.
  • the fourth insulating layer has a barrier property against oxygen, which can suppress oxygen from being released from the semiconductor layer 230.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230.
  • aluminum oxide can be used as the fourth insulating layer
  • silicon oxide or silicon oxynitride can be used as the third insulating layer
  • an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer
  • silicon nitride can be used as the second insulating layer.
  • the thickness of the insulating layer 250 in the region that overlaps with the channel formation region of the semiconductor layer 230 is preferably 0.1 nm or more and 30 nm or less, more preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 8.0 nm or less, and more preferably 0.5 nm or more and 7.0 nm or less.
  • each layer constituting the insulating layer 250 is thin.
  • the thickness of each layer constituting the insulating layer 250 is 0.1 nm or more and 10 nm or less, or 0.1 nm or more and 5 nm or less, or 0.5 nm or more and 5 nm or less, or 1 nm or more and less than 5 nm, or 1 nm or more and 3 nm or less.
  • each layer constituting the insulating layer 250 may have a region with a thickness as described above in at least a portion.
  • the film thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • the insulating layer 280 preferably has the aforementioned barrier insulating layer against hydrogen.
  • the insulating layer 280 is provided so as to surround the semiconductor layer 230.
  • the insulating layer 280 provided on the outside of the semiconductor layer 230 has barrier properties against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 230 can be suppressed.
  • the insulating layer 280 preferably has a silicon nitride film.
  • Silicon nitride also has barrier properties against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be extracted from the semiconductor layer 230, and excessive oxygen vacancies can be prevented from being formed in the semiconductor layer 230.
  • silicon nitride for the insulating layer 280, it is possible to prevent excess oxygen from being supplied to the semiconductor layer 230. Therefore, it is possible to prevent the channel formation region of the semiconductor layer 230 from becoming excessively oxygenated, thereby improving the reliability of the transistor 200.
  • Insulating layer 280 preferably has an oxide insulating film, an oxynitride insulating film, or an insulating layer having a region containing excess oxygen, as described above.
  • an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen.
  • a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas the hydrogen concentration in the insulating layer 280 can be reduced.
  • oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 230. Therefore, when a metal oxide is used as the semiconductor layer 230, oxygen deficiency and VoH can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. This can prevent impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200.
  • the insulating layer 280 can also have a laminated structure of two or more layers.
  • the insulating layer 280 can have a structure in which a second layer that supplies oxygen is sandwiched between a first layer and a third layer that have a barrier property against oxygen.
  • oxygen can be supplied to the channel formation region of the semiconductor layer 230, and the conductive layer 220 and the conductive layer 240 can be prevented from being oxidized by oxygen from the second layer, which would increase the resistance.
  • the second layer of the insulating layer 280 preferably has an area with a higher oxygen content than at least one of the first layer and the third layer of the insulating layer 280.
  • the second layer of the insulating layer 280 is preferably a film that releases oxygen when heated. By releasing oxygen due to the heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 230.
  • the amount of released oxygen molecules from the second insulating layer is preferably equal to or greater than 1.0 ⁇ 10 14 molecules/cm 2 and less than 1.0 ⁇ 10 15 molecules/cm 2.
  • the amount of released oxygen molecules can be measured by thermal desorption spectrometry.
  • the channel length of the transistor 200 when the channel length of the transistor 200 is short, the influence of oxygen vacancies in the channel formation region and VOH on the electrical characteristics and reliability becomes particularly large. Therefore, by optimizing the amount of oxygen supplied to the semiconductor layer 230 after sufficiently reducing the hydrogen concentration in the semiconductor layer 230, a transistor with good electrical characteristics and high reliability and a short channel length can be realized, particularly when a metal oxide is used as the semiconductor layer 230.
  • the region of the semiconductor layer 230 that is in contact with the first layer of the insulating layer 280 and the region that is in contact with the third layer of the insulating layer 280 receive a smaller amount of oxygen than the region that is in contact with the second layer of the insulating layer 280. Therefore, particularly when a metal oxide is used as the semiconductor layer 230, the region of the semiconductor layer 230 that is in contact with the first layer of the insulating layer 280 and the region that is in contact with the third layer of the insulating layer 280 may have low resistance.
  • the semiconductor layer 235 may have low resistance when in contact with the third layer of the insulating layer 280.
  • the semiconductor layer 237 may have low resistance when in contact with the third layer of the insulating layer 280.
  • a material with a low dielectric constant for the second layer of the insulating layer 280. This can reduce the parasitic capacitance that occurs between the wiring.
  • silicon oxide or silicon oxynitride can be used.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the first layer of the insulating layer 280.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the first layer of the insulating layer 280.
  • magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon may be used.
  • a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the third layer of the insulating layer 280.
  • the insulating layer 281 can be made of a material that can be used as the insulating layer 280.
  • the insulating layer 281 may have a laminated structure.
  • the layer in the insulating layer 281 that is in contact with the semiconductor layer 235 may be made of a material that can be used as the third layer of the insulating layer 280, for example, a layer with a relatively low oxygen content. In such a case, the amount of oxygen supplied to the semiconductor layer 235 may decrease, causing the semiconductor layer 235 to have a low resistance.
  • the dielectric constant be low.
  • the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, so are suitable for the insulating layer 210.
  • the concentration of impurities such as water and hydrogen in the insulating layer 210 is reduced. This can prevent impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200.
  • a barrier insulating layer against hydrogen as the insulating layer 210, it is possible to suppress the diffusion of hydrogen into the semiconductor layer of the transistor 200, etc.
  • a barrier insulating layer against hydrogen for one or more of the insulating layers 283 and 285. This makes it possible to suppress the diffusion of hydrogen from above the insulating layer 283 to the semiconductor layer of the transistor 200, etc.
  • an insulating layer having the function of capturing or fixing hydrogen may be used as one or more of the insulating layers 283 and 285.
  • a material with a low dielectric constant can be used as the insulating layer 285.
  • the parasitic capacitance that occurs between wirings can be reduced.
  • the concentrations of impurities such as water and hydrogen in the insulating layer 283 and the insulating layer 285 are reduced. This can prevent impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200.
  • a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a nitride of the alloy or an oxide of the alloy may be used.
  • tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium, and aluminum nitride containing tantalum and aluminum, ruthenium oxide, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc.
  • a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • ITO indium oxide containing titanium oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • the conductive layer 260 can be made of the metal elements described above, or alloys containing the metal elements described above, or alloys combining the metal elements described above. For example, it is preferable to use a material with high conductivity, such as tungsten. In addition, it is preferable to use a conductive material that is difficult to oxidize, or a conductive material that has the function of suppressing the diffusion of oxygen, for the conductive layer 260. As described above, examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 260.
  • the conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • the conductive layer 260 may be, for example, 3 nm or more and 500 nm or less.
  • the thickness of the conductive layer 260 may be, for example, greater than or equal to the thickness of the insulating layer 250. By making the conductive layer 260 thicker, the resistance of the conductive layer 260 can be reduced.
  • the conductive layer 260 may have a laminated structure.
  • a conductive material containing nitrogen, a conductive material containing oxygen, etc. can be used as the first layer of the conductive layer 260.
  • a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed can be used.
  • the above-mentioned metal element, an alloy containing the above-mentioned metal element, or an alloy combining the above-mentioned metal elements can be used as the second layer on the first layer of the conductive layer 260.
  • tungsten can be used.
  • the conductive layer 220 and the conductive layer 240 are each a conductive layer in contact with the semiconductor layer of the transistor 200.
  • each of the conductive layer 220 and the conductive layer 240 is made of a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, an oxide conductive material, or a conductive material that has a function of suppressing oxygen diffusion.
  • conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.
  • the conductive layer 220 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen.
  • the conductive layer 220 is preferable because it can maintain its conductivity.
  • ITO, ITSO, IZO (registered trademark), etc. are preferably used as each of the conductive layer 220 and the conductive layer 240.
  • the conductive layer 220 has a three-layer structure of a first conductive layer, a second conductive layer, and a third conductive layer on the insulating layer 210 in this order, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the first conductive layer, a material with high conductivity as the second conductive layer, and a conductive material containing oxygen as the third conductive layer. Specifically, it is preferable to use titanium nitride as the first conductive layer, tungsten as the second conductive layer, and ITO or ITSO as the third conductive layer.
  • the conductive layer 220 can maintain its conductivity even when it is in contact with the semiconductor layer.
  • an oxide insulating layer is used for the insulating layer 210, it is possible to suppress excessive oxidation of the conductive layer 220 by the insulating layer 210.
  • the conductivity of the conductive layer 220 can be increased.
  • the conductive layer 240 has a laminated structure, for example, a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen can be used as the layer that is mainly in contact with the semiconductor layer.
  • the conductive layer 240 has a two-layer stacked structure, for example, a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion can be used as the first conductive layer, and a material with high conductivity can be used as the second conductive layer.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion can be used as the first conductive layer
  • a material with high conductivity can be used as the second conductive layer.
  • the conductive layer 240 can have a three-layer stacked structure in which, for example, a first conductive layer using a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing oxygen diffusion is sandwiched between a second conductive layer and a third conductive layer using a material with high conductivity.
  • ITO or ITSO as the first conductive layer of the conductive layer 240. It is also preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the second conductive layer and the third conductive layer of the conductive layer 240.
  • the semiconductor layer 230 has a channel formation region.
  • the channel formation region is i-type (intrinsic) or substantially i-type.
  • the semiconductor layer 230, the semiconductor layer 235, and the semiconductor layer 237 can each have an n-type region (low resistance region) that has a higher carrier concentration than the channel formation region.
  • the n-type region can function as a source region or a drain region.
  • the crystallinity of the semiconductor material used for the semiconductor layer 230, the semiconductor layer 235, and the semiconductor layer 237 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • metal oxides that can be used as semiconductor layer 230, semiconductor layer 235, and semiconductor layer 237.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • metal oxides include indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium Indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IG
  • indium tin oxide containing silicon gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc.
  • Ga-Sn oxide gallium tin oxide
  • Al-Sn oxide aluminum tin oxide
  • the above oxides having an amorphous structure can be used.
  • indium oxide having an amorphous structure indium tin oxide having an amorphous structure, etc. can be used.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a large period number in the periodic table instead of or in addition to indium.
  • Examples of metal elements having a large period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration may increase or the band gap may be narrowed, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • a metal oxide with a large band gap can be obtained.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained.
  • a shift in the threshold voltage of the transistor can be suppressed.
  • fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer of the transistor. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M.
  • the term "nearby composition” includes
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the In-Zn oxide may also contain a trace amount of element M.
  • the sputtering method or the ALD method can be suitably used to form the metal oxide.
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the chemical vapor deposition (CVD) method, the molecular beam epitaxy (MBE) method, the pulsed laser deposition (PLD) method, etc. may also be used to form the metal oxide film.
  • the carrier concentration of the first oxide layer is relatively high.
  • the electrical conductivity is increased, and the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced.
  • the carrier concentration of the second oxide layer is decreased, and a normally-off transistor can be obtained.
  • the electrical conductivity and carrier concentration of the two oxide layers of the semiconductor layer 230 are not limited to the above-mentioned configuration.
  • the band gap of the first metal oxide used in the first oxide layer is different from the band gap of the second metal oxide used in the second oxide layer.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide is preferably smaller than the band gap of the second metal oxide. This can reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240, and can provide a transistor with a large on-current.
  • the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the large band gap of the second metal oxide can suppress the generation and induction of carriers in the second oxide layer and at the interface between the second oxide layer and the insulating layer 250. This can improve the reliability of the transistor.
  • the semiconductor layer 230 is not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide.
  • the first metal oxide may be configured to contain a trace amount of element M or may be configured to contain no element M.
  • the first metal oxide is In-Zn oxide and the second metal oxide is In-M-Zn oxide.
  • the first metal oxide can be In-Zn oxide and the second metal oxide can be In-Ga-Zn oxide.
  • This increases the on-state current of the transistor 200 and creates a highly reliable transistor structure with little variation.
  • a second oxide layer on the first oxide layer having high crystallinity, it is also easy to improve the crystallinity of the second oxide layer. This makes it possible to improve the crystallinity of the entire semiconductor layer 230, which is preferable.
  • gallium, aluminum, or tin as the element M.
  • two layers of IGZO having different compositions from each other may be stacked.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • the semiconductor layer 230 is not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer 230 preferably has a metal oxide layer having crystallinity.
  • a metal oxide having crystallinity examples include a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a nanocrystalline (nc: nano-crystal) structure.
  • CAAC c-axis aligned crystal
  • Poly-crystal polycrystalline
  • nc nanocrystalline
  • the CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) have a c-axis orientation, and the multiple microcrystals are connected without being oriented in the a-b plane.
  • the OS film having a CAAC structure can also be said to have a structure having a layered crystal part.
  • the polycrystalline structure has grain boundaries.
  • a minute gap also called a nanocrack or microcrack
  • a minute space also called a nanospace or microspace
  • the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the minute gap or minute space is very high, for example, infinite.
  • an oxide semiconductor layer having a minute gap or minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor.
  • the CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure, and therefore can realize a highly reliable semiconductor device.
  • the crystallinity of the semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the semiconductor layer 230 can have a stacked structure of two or more oxide layers with different crystallinity.
  • the two or more oxide layers may have different compositions, or may have the same or approximately the same composition.
  • a stacked structure of a first oxide layer and a second oxide layer provided on the first oxide layer can be used, and the second oxide layer can have a region with higher crystallinity than the first oxide layer.
  • the second oxide layer can have a region with lower crystallinity than the first oxide layer. Note that, when the second oxide layer has a region with lower crystallinity than the first oxide layer, the crystallinity of the second oxide layer can be increased by performing heat treatment (also called crystallization treatment) after forming the second oxide layer.
  • the semiconductor layer 230 may also have a laminated structure of three or more layers.
  • the semiconductor layer 230 may have a third oxide layer in addition to the first oxide layer and the second oxide layer described above. It is preferable that the first oxide layer is provided on the third oxide layer, and the second oxide layer is provided on the first oxide layer.
  • the third oxide layer located below the first oxide layer can have a structure similar to that applicable to the second oxide layer. In the following, they will be collectively described as a pair of oxide layers (second oxide layer, third oxide layer) sandwiching the first oxide layer.
  • the pair of oxide layers sandwiching the first oxide layer preferably have a band gap larger than that of the first oxide layer.
  • the first oxide layer is sandwiched between the pair of oxide layers having a larger band gap, and the first oxide layer mainly functions as a current path (channel).
  • sandwiching the first oxide layer between the pair of oxide layers it is possible to reduce trap levels at the interface of the first oxide layer and in its vicinity. This makes it possible to realize a buried channel type transistor in which the channel is kept away from the insulating layer interface, and to increase the field effect mobility.
  • the influence of interface states that may be formed on the back channel side is reduced, and light deterioration (e.g., negative bias light deterioration) of the transistor can be suppressed, thereby improving the reliability of the transistor.
  • the semiconductor layer 235 and the semiconductor layer 237 can each be made of the same material, composition, crystal structure, etc. that can be used as the semiconductor layer 230.
  • the contact resistance between the semiconductor layer and the conductive layer 240 can be reduced.
  • the contact resistance between the semiconductor layer and the conductive layer 240 can be reduced.
  • the contact resistance between the semiconductor layer and the conductive layer 220 can be reduced.
  • the contact resistance between the semiconductor layer and the conductive layer 220 can be reduced.
  • the semiconductor layer 235 and the semiconductor layer 237 can each be applied with a material, composition, crystal structure, etc. that can be used as the first oxide layer of the semiconductor layer 230.
  • the semiconductor layer 235 and the semiconductor layer 237 can be applied with the same material, composition, crystal structure, etc. as the layer in contact with the semiconductor layer 230.
  • the same material, composition, crystal structure, etc. as the first oxide layer of the semiconductor layer 230 can be applied to the semiconductor layer 235 and the semiconductor layer 237, respectively, to improve the bonding between the semiconductor layer 230 and the semiconductor layer 235 and the semiconductor layer 237, respectively, and the contact resistance can be reduced.
  • the thickness of the semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, more preferably 20 nm or more and 50 nm or less.
  • the film thickness of the semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the semiconductor layer 235 and the semiconductor layer 237 are each thicker than the semiconductor layer 230.
  • the contact area with the semiconductor layer 230 can be increased.
  • a method with a high film formation speed such as a sputtering method, can be used, and productivity can be increased.
  • the thickness can be made approximately the same as that of the semiconductor layer 230.
  • the oxide semiconductor layer when forming the oxide semiconductor layer, it is preferable to use two types of film formation methods, a sputtering method and an ALD method. For example, if a first oxide semiconductor layer having a CAAC structure is formed by using a sputtering method, and then a second oxide semiconductor layer having a lower crystallinity than the CAAC structure is formed by using an ALD method, it is expected that the atomic layer of the second oxide semiconductor layer will fill or repair the gaps in the atomic-level crystal parts of the CAAC structure of the first oxide semiconductor layer. In addition, it is preferable to perform heat treatment (for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • heat treatment for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • an oxide semiconductor layer formed using the above two types of film formation methods may be called a hybrid OS.
  • the oxide semiconductor layer 370a shown in FIG. 13A has a region 372a and a region 372b located between the regions 372a.
  • the region 372a corresponds to a region of a CAAC structure (i.e., a structure having layered crystal parts), and the region 372b corresponds to a region between the CAAC structures.
  • the CAAC structure has fewer crystal grain boundaries in the a-b plane than the polycrystalline structure. Thus, even in the oxide semiconductor layer 370a having a CAAC structure, there may be a minute gap or minute space (region 372b in FIG. 13A) between the crystal parts.
  • an oxide semiconductor layer having a CAAC structure is formed by sputtering as the first oxide semiconductor layer, and then an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, is formed by ALD as the second oxide semiconductor layer.
  • an oxide semiconductor layer having a region 372a is formed by sputtering as a first oxide semiconductor layer, and then an oxide semiconductor layer having a region 372c with lower crystallinity than the CAAC structure is formed by ALD as a second oxide semiconductor layer.
  • the oxide semiconductor layer 370b has a region 372a and a region 372c. Since the ALD method can deposit atoms one layer at a time, the second oxide semiconductor layer can be formed to fill the region 372b.
  • the oxide semiconductor layer 370c has a region 372a and a region 372c.
  • 13C is a region having higher crystallinity or a higher density of crystal parts than the region 372a shown in FIG. 13B.
  • the crystallinity of either or both of the regions 372a and 372c can be increased.
  • the region 372c has, for example, a crystal part that has the same crystal structure as the crystal part of the region 372a.
  • the region 372c has, for example, a crystal part that is connected to the crystal part of the region 372a.
  • the oxide semiconductor layer 370d has a region 372a.
  • the region 372a has improved crystallinity compared to the region 372a shown in FIG. 13B and FIG. 13C, and the boundary between the region 372a and the region 372c disappears, or the boundary between the region 372a and the region 372c is no longer observed. Therefore, the entire oxide semiconductor layer 370d has a CAAC structure.
  • FIG. 13D when the entire oxide semiconductor layer 370d has a CAAC structure, a highly reliable semiconductor device can be realized. The presence or absence of the boundary between the region 372a and the region 372c can be confirmed, for example, by using cross-sectional TEM observation, cross-sectional STEM observation, or the like.
  • the small gap or the small space in the first oxide semiconductor layer can be filled by forming a second oxide semiconductor layer on the first oxide semiconductor layer or by forming a second oxide semiconductor layer on the first oxide semiconductor layer and performing heat treatment.
  • a dense oxide semiconductor layer with improved crystallinity can be obtained.
  • the dense oxide semiconductor layer with improved crystallinity is used for the channel formation region of a transistor, it is expected that an increase in the electrical resistance of the oxide semiconductor layer can be suppressed or the initial characteristics (particularly the on-current) of the transistor can be improved, making the transistor suitable for high-speed driving.
  • the oxide semiconductor layer when an oxide semiconductor layer is formed by both the sputtering method and the ALD method, if the thickness of the oxide semiconductor layer formed by the ALD method is thin, the oxide semiconductor layer can be regarded as a single-layer structure, not a stacked structure of the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer formed by the ALD method when the thickness of the oxide semiconductor layer formed by the ALD method is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably more than 0 nm and 1 nm or less, the oxide semiconductor layer formed by the two film formation methods, the sputtering method and the ALD method, can be regarded as a single-layer structure. In such a case, for example, in a cross-sectional TEM image, a cross-sectional STEM image, or the like, the boundary between the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method is not observed.
  • the thickness of the oxide semiconductor layer formed by the ALD method exceeds 3 nm, it may be considered to be a stacked structure, a multilayer structure, or a multiple structure of an oxide semiconductor layer formed by the sputtering method and an oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer is formed by both the sputtering method and the ALD method, it is preferable to use different compositions.
  • the oxide semiconductor layer formed using the above-mentioned two types of film formation methods can be regarded as a structure in which the gaps in the crystal parts of the CAAC structure are filled with atomic layers formed by the ALD method. Note that this structure can be analyzed by analytical methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, SIMS, and EDX.
  • the oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have a higher dielectric constant, film density, and film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.
  • a transistor having excellent characteristics for example, a transistor with a large on-current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.
  • Hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to become water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as VOH ) may function as a donor and generate an electron that is a carrier. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (that is, the threshold voltage has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • the oxide semiconductor layer In the channel formation region of the semiconductor layer, it is preferable to reduce VOH as much as possible and make the oxide semiconductor highly intrinsic or substantially highly intrinsic. In this way, in order to obtain an oxide semiconductor with sufficiently reduced VOH , it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for the channel formation region of a transistor, stable electrical characteristics can be imparted.
  • oxygen addition treatment supplying oxygen to an oxide semiconductor to repair oxygen vacancies may be referred to as oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , still more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and still more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and thus oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond to oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor device of this embodiment may be applied to a transistor using a material other than a metal oxide in the channel formation region.
  • a semiconductor made of a single element or a compound semiconductor may be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide, silicon germanium, indium phosphide, silicon carbide, boron nitride, and boron arsenide.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the oxide semiconductor described above is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), zirconium selenide (representatively ZrSe 2 ), and the like.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • a insulating substrate for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate, etc. are available.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available.
  • a substrate having a metal nitride, a substrate having a metal oxide, etc. are available.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate
  • a substrate in which a conductor or an insulator is provided on a semiconductor substrate a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Thin films (insulating films, semiconductor films, conductive films, and the like) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, or the like.
  • the sputtering method includes RF sputtering, which uses a high frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. There is also RF-superimposed DC sputtering, which superimposes RF and DC.
  • RF sputtering is preferably used for film formation using an insulating target.
  • DC sputtering is mainly used when forming a film using a conductive target. In addition to forming a conductive film, DC sputtering can also form an insulating film by performing reactive sputtering.
  • Pulsed DC sputtering is mainly used when forming a film of compounds such as oxides, nitrides, and carbides by reactive sputtering.
  • RF-superimposed DC sputtering allows control of ion energy during film formation and control of the potential on the target side. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Also, a high-quality film can be obtained.
  • sputtering methods examples include ionization sputtering and long-throw sputtering.
  • Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is achieved by self-bias or the like.
  • long-throw sputtering can form anisotropic films by increasing the distance between the sputtering target and the substrate.
  • CVD methods can be classified into PECVD, thermal CVD (TCVD) which uses heat, and photo CVD (Photo CVD) which uses light. They can also be further divided into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.
  • PECVD can produce high-quality films at relatively low temperatures.
  • Thermal CVD does not use plasma, so it is a film formation method that can reduce plasma damage to the workpiece.
  • wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device.
  • thermal CVD which does not use plasma, does not cause such plasma damage, so it is possible to increase the yield of semiconductor devices. Furthermore, thermal CVD does not cause plasma damage during film formation, so films with fewer defects can be obtained.
  • the ALD method may be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a plasma enhanced ALD method in which a plasma excited reactant is used.
  • the ALD method can deposit atoms one layer at a time, it has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • PEALD Pulsma Enhanced ALD
  • the use of plasma allows films to be formed at lower temperatures, which may be preferable.
  • some precursors used in the ALD method contain impurities such as carbon.
  • films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods.
  • the amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS).
  • the CVD and ALD methods are different from film formation methods in which particles released from a target or the like are deposited, and instead form a film by a reaction on the surface of the workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • the CVD and ALD methods can control the composition of the resulting film by changing the flow rate ratio of the source gases.
  • the CVD and ALD methods can form a film of any composition by changing the flow rate ratio of the source gases.
  • the CVD and ALD methods can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases.
  • the CVD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film when processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Dry etching, wet etching, sandblasting, etc. can be used to etch thin films.
  • the memory device of one embodiment of the present invention includes a memory cell.
  • the memory cell includes a transistor and a capacitor.
  • Fig. 15A is a plan view of a memory device including a transistor 200 and a capacitor 100.
  • Fig. 15B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Fig. 15A.
  • Fig. 15C is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 15A.
  • the memory device shown in Figures 15A to 15C has an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 281, and an insulating layer 283 on the memory cell 150.
  • the insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 281, and the insulating layer 283 function as interlayer films.
  • the conductive layer 110 functions as wiring.
  • the memory cell 150 has a capacitor element 100 on a conductive layer 110 and a transistor 200 on the capacitor element 100.
  • the capacitance element 100 has a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130.
  • the conductive layer 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductive layer 115 functions as the other of the pair of electrodes (sometimes called a lower electrode)
  • the insulating layer 130 functions as a dielectric.
  • the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • the insulating layer 180 has an opening 190 that reaches the conductive layer 110. At least a part of the conductive layer 115 is disposed in the opening 190.
  • the conductive layer 115 has a region that contacts the upper surface of the conductive layer 110 in the opening 190, a region that contacts the side surface of the insulating layer 180 in the opening 190, and a region that contacts at least a part of the upper surface of the insulating layer 180.
  • the insulating layer 130 is disposed so that at least a part of it is located in the opening 190.
  • the conductive layer 120 is disposed so that at least a part of it is located in the opening 190. As shown in FIG. 15B and FIG.
  • the conductive layer 120 is preferably disposed so as to fill the opening 190.
  • the films disposed inside the opening 190 are preferably formed using a method with high coverage such as the ALD method. This improves the coverage of the film.
  • the conductive layer 115, the insulating layer 130, and the conductive layer 120 are each formed using an ALD method, a metal CVD method, or the like.
  • the capacitive element 100 is configured such that the upper electrode and the lower electrode face each other with a dielectric between them, not only on the bottom surface but also on the side surfaces, allowing the capacitance per unit area to be increased. Therefore, the deeper the opening 190, the greater the capacitance of the capacitive element 100 can be. Increasing the capacitance per unit area of the capacitive element 100 in this way can stabilize the read operation of the memory device. It can also promote high integration of memory devices.
  • 15B and 15C show an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110.
  • the opening 190 has a cylindrical shape.
  • a conductive layer 115 and an insulating layer 130 are laminated along the sidewall of the opening 190 and the upper surface of the conductive layer 110.
  • a conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190.
  • a capacitance element 100 having such a configuration may be called a trench type capacitance or a trench capacitance.
  • An insulating layer 280 and an insulating layer 281 are disposed on the capacitive element 100.
  • the structure of the transistor 200 described in embodiment 1 can be applied to the transistor 200.
  • FIG. 15B and FIG. 15C an example is shown in which the conductive layer 120 is used instead of the conductive layer 220 of the transistor 200 described in embodiment 1.
  • the conductive layer 220 can also be formed by overlapping the conductive layer 120 without omitting the conductive layer 220.
  • transistor 200 the transistor 200 described in embodiment 1 can be referred to, and therefore detailed description is omitted.
  • the transistor 200 is provided so as to overlap with the capacitor 100.
  • the opening 290 in which part of the structure of the transistor 200 is provided has a region that overlaps with the opening 190 in which part of the structure of the capacitor 100 is provided.
  • the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100, so that the transistor 200 and the capacitor 100 share part of their structures.
  • the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of the memory cell 150, so that the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • the transistor 200 is not affected by the heat treatment during the manufacturing of the capacitor 100. Therefore, in the transistor 200, it is possible to suppress deterioration of electrical characteristics such as fluctuations in threshold voltage and increases in parasitic resistance, as well as increases in variations in electrical characteristics due to deterioration of electrical characteristics.
  • Figure 16A is a plan view showing an example in which 12 memory cells 150 shown in Figure 15A are arranged in three rows in the Y direction and four columns in the X direction.
  • Figure 16B is a cross-sectional view between dashed dotted lines A1-A2 shown in Figure 16A.
  • the conductive layer 110 is shared by multiple memory cells 150 arranged in the X direction.
  • Insulating layer 130 It is preferable to use a material having a high relative dielectric constant (high-k) as the insulating layer 130. By using a material having a high relative dielectric constant as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitance element 100 can be sufficiently ensured.
  • high-k high relative dielectric constant
  • the insulating layer 130 is preferably made of a laminate of insulating layers made of a material with a high relative dielectric constant, and preferably has a laminate structure of a material with a high relative dielectric constant and a material with a higher dielectric strength than the material.
  • the insulating layer 130 can be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide.
  • an insulating film laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • a laminate of insulating layers with a relatively high dielectric strength, such as aluminum oxide the dielectric strength is improved and electrostatic breakdown of the capacitance element 100 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulating layer 130.
  • materials with high relative dielectric constants and materials that can have ferroelectricity please refer to the description in embodiment 1.
  • Metal oxides containing one or both of hafnium and zirconium are preferred as the insulating layer 130 because they can have ferroelectricity even when processed into a thin film of a few nm.
  • the film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). Also, for example, the film thickness is preferably 8 nm to 12 nm.
  • a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130.
  • the ferroelectricity can be maintained even if the area (occupied area) of the ferroelectric layer in a plan view is 100 ⁇ m 2 or less, 10 ⁇ m 2 or less, 1 ⁇ m 2 or less, or 0.1 ⁇ m 2 or less.
  • the ferroelectricity even if the area is 10,000 nm 2 or less, or 1,000 nm 2 or less, the ferroelectricity may be maintained.
  • the occupied area of the capacitance element 100 can be reduced.
  • a ferroelectric material is an insulator that is polarized when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric.
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, etc.
  • a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 100, the memory device shown in this embodiment functions as a ferroelectric memory.
  • FIG. 17A shows an example in which the conductive layer 115 of the capacitance element 100 has a columnar shape.
  • the conductive layer 115 has a region formed so as to be embedded in the insulating layer 180 and a region disposed within the opening 190 of the insulating layer 180.
  • the insulating layer 130 has a region disposed so as to surround the outside of the columnar region of the conductive layer 115, a region provided along the sidewall of the opening 190, and a region covering the upper surface of the insulating layer 180.
  • the conductive layer 120 is provided on the insulating layer 180.
  • the conductive layer 120 can also have a region formed so as to embed the opening 190.
  • the capacitance element 100 shown in FIG. 17A is sometimes called a pillar-type capacitance element.
  • a conductor is formed to cover the inner wall of an opening provided in an insulator or the like, and a dielectric is formed to cover the inside of that.
  • the opening diameter of the opening provided in the insulator or the like becomes small, the coverage may decrease at the bottom of the opening or the area extending from the bottom to the side wall.
  • FIG. 17B shows an example in which the capacitance element 100 does not have a conductive layer 115, and a conductive layer 110 and a conductive layer 120 having a planar shape are arranged with an insulating layer 130 sandwiched between them.
  • the capacitance element 100 shown in FIG. 17B can be easily formed. Also, since there is no unevenness, leakage current of the capacitance element may not easily flow.
  • the memory device shown in FIG. 17C differs from FIG. 15A mainly in that the transistor 200 has a conductive layer 220, and the conductive layer 220 is provided on and in contact with the conductive layer 120.
  • FIG. 17C a layer including an insulating layer 140 and a layer in which the capacitance element 100 is disposed is shown as layer 10.
  • layer 10 shown in FIG. 17C the configuration shown in FIG. 17D or the configuration shown in FIG. 17E can be applied as appropriate.
  • the configuration shown in FIG. 17D shows an example in which the capacitance element 100 is a pillar-type capacitance element as described in FIG. 17A.
  • the configuration shown in FIG. 17E shows an example in which the capacitance element shown in FIG. 17B is applied.
  • an opening 290 may be provided in the conductive layer 220 in addition to the insulating layer 280, the insulating layer 281, the conductive layer 240, and the semiconductor layer 235.
  • a recess provided in the conductive layer 220 constitutes a part of the opening 290.
  • At least a part of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 is formed so as to fill the recess of the conductive layer 220.
  • an opening may be provided in the conductive layer 220, and the opening provided in the conductive layer 220 may constitute a part of the opening 290.
  • the conductive layer 220 is disposed so as to surround the periphery of the semiconductor layer 230.
  • FIG. 18B shows an example in which the semiconductor layer 230 contacts the upper surface of the conductive layer 120, but as shown in FIG. 18C, an insulating layer 181 may be provided between the conductive layer 120 and the semiconductor layer 230.
  • FIG. 18C differs from FIG. 18B in that an insulating layer 181 is provided between the conductive layer 120 and the semiconductor layer 230.
  • an insulating layer 181 is provided between the conductive layer 120 and the semiconductor layer 230.
  • the distance between the conductive layer 260 and the conductive layer 120 can be increased. This can reduce the parasitic capacitance between the gate of the transistor 200 and the conductive layer 120 that functions as the upper electrode of the capacitor 100. Therefore, the operating speed of the memory cell 150 composed of the transistor 200 and the capacitor 100 can be improved.
  • the configuration shown in FIG. 18D differs from FIG. 18C in that the width of the opening 190 is larger near the upper surface of the insulating layer 180 than near the lower surface of the insulating layer 180.
  • the width of the insulating layer 181 near the upper surface of the insulating layer 180 is also larger than near the lower surface of the insulating layer 180.
  • the lower surface of the semiconductor layer 230 is in contact only with the insulating layer 181 without contacting the conductive layer 220.
  • the distance between the conductive layer 260 and the conductive layer 120 can be increased. This can further reduce the parasitic capacitance between the gate of the transistor 200 and the conductive layer 120 that functions as the upper electrode of the capacitance element 100. Therefore, the operating speed of the memory cell 150 can be further improved.
  • Fig. 19A is a plan view of a memory device including a transistor 200, a transistor 200(2), and a capacitor 100.
  • Fig. 19B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Fig. 19A.
  • Fig. 19C is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 19A.
  • 19A to 19C includes an insulating layer 140 on a substrate (not shown), a memory cell 151 on the insulating layer 140, an insulating layer 183 on the insulating layer 140, an insulating layer 185, an insulating layer 180, an insulating layer 280, an insulating layer 281, and an insulating layer 283 on the memory cell 151.
  • the memory cell 151 includes a transistor 200, a capacitor 100b on the transistor 200, and a transistor 200 on the capacitor 100b.
  • the two transistors 200 included in the memory cell 151 are stacked vertically with the capacitor 100b sandwiched between them.
  • the transistor 200 located on the lower side is referred to as transistor 200(2).
  • the conductive layer 220 and the conductive layer 240 of the transistor 200(2) are referred to as the conductive layer 220(2) and the conductive layer 240(2), respectively.
  • the insulating layer 183 is an insulating layer that covers the transistor 200(2)
  • the insulating layer 185 is an insulating layer that is provided on the insulating layer 183.
  • the description of the insulating layer 283 and the insulating layer 285 can be referred to as appropriate.
  • the capacitor 100b has a conductive layer 120, a conductive layer 115, and an insulating layer 130.
  • the conductive layer 120 has a region that is provided so as to be embedded in the insulating layer 183 and the insulating layer 185, and a region that is provided so as to be embedded in the insulating layer 180.
  • the insulating layer 130 has a region that is sandwiched between the conductive layer 115 and the conductive layer 120.
  • the conductive layer 120 has a columnar shape, and the insulating layer 130 is provided so as to surround the conductive layer 120.
  • the conductive layer 115 is provided so as to surround the conductive layer 120 with the insulating layer 130 sandwiched therebetween.
  • the conductive layer 115 is also provided so as to be embedded in the insulating layer 180.
  • the conductive layer 260 of the transistor 200(2) and the conductive layer 220 of the transistor 200 are electrically connected through the conductive layer 120. It is preferable that the conductive layer 120 is provided so as to be in contact with the top surface of the conductive layer 260 of the transistor 200(2). It is also preferable that the conductive layer 220 of the transistor 200 is provided so as to be in contact with the top surface of the conductive layer 120.
  • Fig. 20A is a plan view of a memory device including a transistor 200 and a transistor 200(2).
  • Fig. 20B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Fig. 20A.
  • Fig. 20C is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 20A.
  • 20A to 20C includes an insulating layer 140 on a substrate (not shown), a memory cell 152 on the insulating layer 140, an insulating layer 280 on the insulating layer 140, an insulating layer 281, and an insulating layer 283 on the memory cell 152.
  • the memory cell 152 includes a transistor 200 and a transistor 200(2) on the transistor 200.
  • the configuration does not include the capacitor element 100b in FIGS. 19A to 19C, and the transistor 200 is provided on the insulating layer 185.
  • the conductive layer 260 of the transistor 200(2) has a region that is provided so as to be embedded in the insulating layer 185, and the upper surface of the conductive layer 260 and the upper surface of the insulating layer 185 are planarized to be approximately aligned with each other.
  • the conductive layer 220 of the transistor 200 is preferably provided so as to be in contact with the upper surface of the conductive layer 260 of the transistor 200(2).
  • the conductive layer 220 of transistor 200 and the conductive layer 260 of transistor 200(2) are electrically connected.
  • Fig. 21A is a plan view of a memory device having a transistor 200, a transistor 200(2), and a transistor 200(3).
  • Fig. 21B is a cross-sectional view corresponding to the dashed line A1-A2 shown in Fig. 21A.
  • Fig. 21C is a cross-sectional view corresponding to the dashed line A3-A4 shown in Fig. 21A.
  • 21A to 21C differ from FIG. 20A to FIG. 20C in that a transistor 200(3) is provided below and in contact with the transistor 200(2). Also, in FIG. 21A to FIG. 21C, the conductive layer 220 of the transistor 200(2) does not extend in the X direction.
  • Transistor 200(3) is provided on insulating layer 140, and transistor 200(2) and transistor 200 are provided in this order on transistor 200(3).
  • the semiconductor layer 113c of transistor 200(3) be in contact with the conductive layer 220 (referred to as conductive layer 220(2) in Figures 21B and 21C) of transistor 200(2) on the upper surface.
  • FIG. 22A is a plan view of a semiconductor layer having transistor 200(3).
  • Figure 22B is a cross-sectional view corresponding to dashed line A1-A2 shown in Figure 22A.
  • Figure 22C is a cross-sectional view corresponding to dashed line A3-A4 shown in Figure 22A.
  • Transistor 200(3) has conductive layer 111c, conductive layer 111a, semiconductor layer 113c, insulating layer 105c, and conductive layer 115c.
  • conductive layer 220(2) of transistor 200(2) is used instead of conductive layer 111a.
  • the conductive layer 111c and the conductive layer 111a function as one of the source electrode and the drain electrode of the transistor 200(3), respectively.
  • the insulating layer 105c functions as the gate insulating layer of the transistor 200(3).
  • the conductive layer 115c functions as the gate electrode of the transistor 200(3).
  • the conductive layer 111c has a region that extends in the Y direction.
  • the conductive layer 115c also has a region that extends in the X direction.
  • the conductive layer 111c is provided on the insulating layer 140, the insulating layer 103c_1 is provided on the insulating layer 140 and on the conductive layer 111c, the conductive layer 115c is provided on the insulating layer 103c_1, and the insulating layer 103c_2 is provided on the insulating layer 103c_1 and on the conductive layer 115c.
  • the insulating layer 103c_1, the conductive layer 115c, and the insulating layer 103c_2 have an opening 121c that reaches the conductive layer 111c.
  • FIG. 22A shows an example in which the shape of the opening 121c is circular in a plan view.
  • planar shape of the opening 121c By making the planar shape of the opening 121c circular, the processing accuracy when forming the opening 121c can be improved, and the opening 121c of a fine size can be formed.
  • the planar shape of the opening 121c may be, for example, a polygon such as an ellipse or a rectangle.
  • the insulating layer 105c which functions as a gate insulating layer for the transistor 200(3), is provided in the opening 121c so as to have an area in contact with a portion of the upper surface of the conductive layer 111c, the side of the insulating layer 103c_1, the side of the conductive layer 115c, and the side of the insulating layer 103c_2.
  • the semiconductor layer 113c is provided so as to cover the opening 121c via the insulating layer 105c and have a region located inside the opening 121c.
  • the semiconductor layer 113c has a region in contact with the upper surface of the insulating layer 103c_2, a region in contact with the upper surface of the insulating layer 105c, a region in contact with the side of the insulating layer 105c, and a region in contact with the upper surface of the conductive layer 111c.
  • the semiconductor layer 113c has a shape along the upper surface of the insulating layer 103c_2, the upper surface of the insulating layer 105c, the side of the insulating layer 105c, and the upper surface of the conductive layer 111c.
  • the semiconductor layer 113c has a recess at a position overlapping the opening 121c.
  • a layer 114 is provided in the recess so as to fill it.
  • the layer 114 has the function of filling the recess and flattening the upper surface.
  • the materials, composition, crystal structure, configuration, etc. that can be used for the semiconductor layer 113c can be appropriately referred to those for the semiconductor layer 230.
  • the insulating layer 107c is provided to cover the side surface at the end of the semiconductor layer 113c and the upper surface of the insulating layer 103c_2.
  • the insulating layer 107c has a function of suppressing the diffusion of impurities into the transistor 200 (3), for example, the function of suppressing diffusion into the semiconductor layer 113c.
  • the insulating layer 103c_3 is provided on the insulating layer 107c. It is preferable that the height of each of the top surfaces of the semiconductor layer 113c, the insulating layer 107c, and the insulating layer 103c_3 is approximately the same with respect to the substrate surface.
  • the insulating layer 107c and the thickness of the semiconductor layer 113c are approximately equal (i.e., when the height of the top surface of the insulating layer 107c and the height of the top surface of the semiconductor layer 113c are approximately the same), the insulating layer 103c_3 does not need to be provided.
  • the conductive layer 111a which functions as the other of the source electrode and drain electrode of the transistor 200(3), is provided in contact with the top surface of the semiconductor layer 113c, the top surface of the layer 114, the top surface of the insulating layer 107c, and the top surface of the insulating layer 103c_3.
  • the conductive layer 111a is provided so as to have a region that overlaps with the conductive layer 111c, which functions as one of the source electrode and drain electrode of the transistor 200(3).
  • the end of the conductive layer 111a is preferably roughly aligned with the end of the semiconductor layer 113c or is located outside the end of the semiconductor layer 113c. This increases the contact area between the conductive layer 111a and the semiconductor layer 113c, thereby reducing the contact resistance between the conductive layer 111a and the semiconductor layer 113c.
  • transistor 200(3) a source electrode, a drain electrode, and a gate electrode are provided overlapping each other at different heights with respect to the substrate surface.
  • the gate electrode is provided sandwiched between the source electrode and the drain electrode. Therefore, in transistor 200(3), the channel length direction corresponds to the direction along the side surface of insulating layer 105c in a cross-sectional view, and a drain current flows in this direction.
  • the channel length of the transistor 200(3) can be controlled by adjusting the film thickness of the layers (insulating layer 103c_1, conductive layer 115c, and insulating layer 103c_2) located between the source electrode and the drain electrode in a cross-sectional view. Therefore, the channel length of the transistor 200(3) can be made smaller than the limit resolution of the exposure device. In addition, the area occupied by the transistor in a planar view can be made smaller than that of a transistor having a structure in which the source electrode and the drain electrode are provided on the same plane.
  • the gate electrode (conductive layer 115c) is provided to surround the opening 121c (semiconductor layer 113c and insulating layer 105c) in a plan view. Therefore, the entire region of the semiconductor layer 113c in the opening 121c that faces the conductive layer 115c via the insulating layer 105c can be used as the channel formation region of the transistor 200(3).
  • the channel width direction of the transistor 200(3) is parallel to the XY plane, and the channel width of the transistor 200(3) corresponds to the perimeter length of the opening 121c in FIG. 22A.
  • the memory device shown in FIG. 23 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] being provided on the topmost layer. There is no particular limit to the number of memory cells that one memory layer 160 has, and it can have two or more memory cells.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be constructed.
  • Figure 24 shows an example of a cross-sectional configuration of a memory device.
  • a layer 170 having a transistor 200 and a memory layer 160 are stacked in this order on a layer 169 having a transistor 300.
  • Layer 169 may include peripheral circuits such as a sense amplifier.
  • Transistor 300 may be, for example, a Si transistor.
  • FIG. 24 an example is shown in which the transistor 300 in the layer 169 is electrically connected to the memory cell 150 in the memory layer 160.
  • the connection example shown in FIG. 24 can be applied to cases in which the transistor 300 is one of the transistors in a sense amplifier.
  • the wiring connecting memory cell 150 and layer 169 can be shortened.
  • the bit line connecting to the sense amplifier can be shortened, the bit line capacitance is reduced, and the storage capacitance of the memory cell can be reduced. Reducing the bit line capacitance enables high-speed operation of the memory device.
  • the transistors in layer 170 can be used, for example, as transistors that form peripheral circuits.
  • the transistor in layer 170 can be used in combination with the transistor in layer 169.
  • the transistor 300 in layer 169 can be a p-channel transistor, and the transistor in layer 170 can be an n-channel transistor. By combining these transistors, a CMOS circuit can be configured.
  • the memory device shown in FIG. 24 can correspond to the semiconductor device 900 described in embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. Also, the memory cell 150 corresponds to the memory cell 950.
  • the transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region.
  • the transistor 300 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 300 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 300 shown in FIG. 24 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order on the transistor 300 as an interlayer film.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.
  • the insulating layer 352 and insulating layer 354, which function as interlayer films, can be the insulating layers that can be used in the semiconductor device or memory device described above.
  • Conductive layers that function as plugs or wiring can be made of a conductive material that can be used for the conductive layer 240. It is preferable to use a high-melting point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low-resistance conductive material, such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.
  • the conductive layer 240 of the transistor 200 in the memory layer 160 is electrically connected to the low-resistance region 314b that functions as the source region or drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, the conductive layer 328, and a conductive layer that is embedded in the insulating layer of the layer 170.
  • the transistor 200 in a configuration in which the conductive layer 240 is located above the semiconductor layer 235, for example, the semiconductor layer 235 is located between the insulating layer 280 and the conductive layer 240.
  • the conductive layer 643 can be provided so as to penetrate the insulating layer 280 and the semiconductor layer 235, so that the conductive layer 643 is in contact with the conductive layer 240.
  • the conductive layer 642 is provided on the insulating layer 130 and is embedded in the insulating layer 641.
  • the conductive layer 642 can be manufactured using the same material and process as the conductive layer 120.
  • the conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130.
  • the conductive layer 645 can be manufactured using the same material and process as the conductive layer 110.
  • the conductive layer 646 is embedded in the insulating layer 648.
  • the transistor 300 and the layer 170 are electrically insulated by the insulating layer 648.
  • An insulating layer 647 is provided on the layer 170.
  • the conductive layer 645 is embedded in the insulating layer 647.
  • the transistor 200 of the layer 170 and the conductive layer 110 are electrically insulated by the insulating layer 647.
  • the memory device of this embodiment has transistors with reduced parasitic capacitance, and therefore the operating speed can be increased.
  • the memory device of this embodiment has a capacitive element and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a highly integrated memory device can be realized.
  • the memory device shown in this embodiment can be applied to, for example, the circuit diagram shown in FIG. 26A.
  • the memory cell 951 has a transistor M1 and a capacitor CA.
  • the transistor 200 as the transistor M1 and the capacitor 100 as the capacitor CA
  • the configuration of the memory cell 150 shown in FIG. 15A to FIG. 15C can be applied to FIG. 26A.
  • the wiring BIL corresponds to the conductive layer 240
  • the wiring WOL corresponds to the conductive layer 260
  • the wiring CAL corresponds to the conductive layer 110.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • an insulating layer 281 is provided between the conductive layer 240 and the conductive layer 260 which function as bit lines, and an insulating layer 280 is provided between the conductive layer 220. Therefore, the wiring capacitance between the conductive layer 240 and the conductive layer 260 and the wiring capacitance between the conductive layer 240 and the conductive layer 220 can be reduced. That is, in the memory device of one embodiment of the present invention, the parasitic capacitance of the bit line can be made extremely small.
  • the memory device shown in this embodiment can be applied to, for example, the circuit diagrams shown in Figures 26C and 26D.
  • Each of the memory cell 953 and the memory cell 954 has a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor 200 as the transistor M2
  • the transistor 200(2) as the transistor M3
  • the capacitor 100 as the capacitor CB
  • the configuration of the memory cell 151 shown in Figures 19A to 19C, etc. can be applied to Figures 26C and 26D.
  • the wiring WBL corresponds to the conductive layer 240 of the transistor 200
  • the wiring WOL corresponds to the conductive layer 260 of the transistor 200
  • the wiring CAL corresponds to the conductive layer 115
  • the wiring RBL and the wiring SL correspond to one and the other of the conductive layer 240 and the conductive layer 220 of the transistor 200(2), respectively.
  • the conductive layer 240 and the conductive layer 220 of the transistor 200(2) are respectively denoted as the conductive layer 240(2) and the conductive layer 220(2) in FIG. 19B and FIG. 19C.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL and the wiring CAL each function as a word line.
  • the conductive layer 240 of the transistor 200 which functions as a write bit line, has an insulating layer 281 between it and the wiring above it, and has an insulating layer 280 between it and the wiring below it, so that the parasitic capacitance can be made extremely small.
  • the conductive layer 240(2) of the transistor 200(2) which functions as a read bit line, can also have an extremely small parasitic capacitance.
  • the conductive layer 240 of the transistor 200 can be electrically connected to one of the conductive layers 240 and 220 of the transistor 200(2) and at least one of them can be used as the wiring BIL, thereby making it possible to apply the circuit diagram shown in FIG. 26D.
  • Memory cell 955 and memory cell 956 each have transistor M2 and transistor M3.
  • transistor 200 as transistor M2 and transistor 200(2) as transistor M3
  • the configuration of memory cell 152 shown in Figures 20A to 20C, etc. can be applied to Figures 26D and 26E.
  • FIG. 26H A circuit diagram of the memory device shown in this embodiment is shown in FIG. 26H.
  • Memory cell 957b has transistors M4, M5, and M6.
  • transistor 200 As transistor M4, transistor 200(2) as transistor M5, and transistor 200(3) as transistor M6, the configuration of memory cell 153 shown in FIGS. 21A to 21C, etc. can be applied to FIG. 26F.
  • wiring WBL corresponds to conductive layer 240 of transistor 200
  • wiring WOL corresponds to conductive layer 260 of transistor 200
  • wiring WBL corresponds to conductive layer 260 of transistor 200
  • wiring RWL corresponds to conductive layer 115c of transistor 200(3)
  • wiring RBL corresponds to 111c of transistor 200(3)
  • wiring SL corresponds to conductive layer 240 of transistor 200(2).
  • the semiconductor device 900 can function as a memory device.
  • FIG. 25 shows a block diagram illustrating a configuration example of a semiconductor device 900.
  • the semiconductor device 900 shown in FIG. 25 has a driver circuit 910 and a memory array 920.
  • the memory array 920 has one or more memory cells 950.
  • FIG. 25 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.
  • the memory device described in embodiment 2 (such as memory cell 150) can be applied to memory cell 950.
  • the drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915.
  • the peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.
  • the control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900.
  • the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.
  • the voltage generation circuit 928 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.
  • the peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950.
  • the peripheral circuit 911 has a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.
  • Each circuit in the peripheral circuit 911 can have the function of generating or outputting a fixed potential, a variable potential (e.g., a pulse voltage, a pulse signal, a clock signal, etc.), etc.
  • a variable potential e.g., a pulse voltage, a pulse signal, a clock signal, etc.
  • Si transistors, etc. may be used for peripheral circuits.
  • a single crystal substrate made of silicon or an SOI substrate having single crystal silicon can be provided with an element isolation layer, a semiconductor region, a low resistance region that functions as a source region or a drain region, etc. Also, a gate insulating layer, a gate electrode, etc. can be provided in a region that overlaps with the semiconductor layer.
  • the row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR.
  • the row decoder 941 is a circuit for specifying the row to be accessed
  • the column decoder 942 is a circuit for specifying the column to be accessed.
  • the row driver 923 has the function of selecting the row specified by the row decoder 941.
  • the column driver 924 has the function of writing data to the memory cell 950, the function of reading data from the memory cell 950, the function of retaining the read data, etc.
  • the input circuit 925 has a function of holding a signal WDA.
  • the data held by the input circuit 925 is output to the column driver 924.
  • the output data of the input circuit 925 is data (Din) to be written to the memory cell 950.
  • the data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926.
  • the output circuit 926 has a function of holding Dout.
  • the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900.
  • the data output from the output circuit 926 is the signal RDA.
  • the PSW 931 has a function of controlling the supply of V DD to the peripheral circuit 915.
  • the PSW 932 has a function of controlling the supply of V HM to the row driver 923.
  • the high power supply voltage of the semiconductor device 900 is V DD
  • the low power supply voltage is GND (ground potential).
  • V HM is a high power supply voltage used to set the word line to a high level, and is higher than V DD .
  • the signal PON1 controls the on/off of the PSW 931
  • the signal PON2 controls the on/off of the PSW 932.
  • the number of power supply domains to which V DD is supplied in the peripheral circuit 915 is one, but it may be more than one. In this case, a power switch may be provided for each power supply domain.
  • V DD 0.8 V
  • V HM 1.8 V, 2.5 V, 3.3 V, etc.
  • the high power supply voltage can be 3.3 V and the low power supply voltage can be 0 V (e.g., ground potential).
  • the high power supply voltage can be 2.5 V and the low power supply voltage can be -0.8 V.
  • the high power supply voltage can be 1.8 V and the low power supply voltage can be -1.5 V.
  • a potential higher than V DD (for example, 1.8 V, 2.5 V, or 3.3 V) can be used in the column driver 924.
  • V HM can be used in the column driver 924 as a high power supply potential higher than V DD .
  • a high power supply potential different from V DD and V HM may be used.
  • [DOSRAM] 26A shows an example of a circuit configuration of a DRAM memory cell.
  • a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM (registered trademark)).
  • the memory cell 951 includes a transistor M1 and a capacitor CA.
  • the transistor M1 may have a front gate (sometimes simply called a gate) and a back gate.
  • the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected.
  • the first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL.
  • the second terminal of capacitance element CA is connected to wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.
  • Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitance element CA into a conductive state (a state in which current can flow).
  • memory cell that can be used for memory cell 950 is not limited to memory cell 951, and the circuit configuration can be changed.
  • memory cell 952 shown in FIG. 26B may be used.
  • Memory cell 952 is an example in which the memory cell does not have a capacitance element CA and a wiring CAL.
  • the first terminal of transistor M1 is in a floating state.
  • the potential written through transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line.
  • an OS transistor has a characteristic that its off-state current is extremely small.
  • the leakage current of transistor M1 can be made extremely low. That is, since written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multi-value data or analog data can be held in memory cell 951 and memory cell 952.
  • [NOSRAM] 26C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 953 has a transistor M2, a transistor M3, and a capacitor CB.
  • a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).
  • the first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL.
  • the second terminal of capacitance element CB is connected to wiring CAL.
  • the first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL and wiring CAL function as word lines.
  • the wiring WOL may be called a write word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while holding data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.
  • Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and bringing the wiring WBL and the first terminal of the capacitance element CB into a conductive state.
  • a high-level potential is also applied to the wiring CAL.
  • a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3.
  • a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential between the first and second terminals of the capacitance element CB.
  • the gate potential of the transistor M3 decreases due to the capacitive coupling of the capacitance element CB, and the transistor M3 is turned off.
  • Data is read by applying a high-level potential to the wiring CAL and a predetermined potential to the wiring SL.
  • the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitance element CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitance element CB (or the gate of transistor M3).
  • the wiring WBL and the wiring RBL may be combined into a single wiring BIL.
  • An example of the circuit configuration of such a memory cell is shown in FIG. 26D.
  • the memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL.
  • the memory cell 954 is configured to operate the write bit line and the read bit line as a single wiring BIL.
  • Memory cell 955 shown in FIG. 26E is an example in which the capacitance element CB and the wiring CAL in memory cell 953 are omitted.
  • memory cell 956 shown in FIG. 26F is an example in which the capacitance element CB and the wiring CAL in memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.
  • OS transistor for at least transistor M2.
  • OS transistors for transistors M2 and M3.
  • the OS transistor Since the OS transistor has a characteristic that the off-state current is extremely small, the written data can be held for a long time by the transistor M2, and therefore the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. In addition, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.
  • Memory cell 953, memory cell 954, memory cell 955, and memory cell 956, in which an OS transistor is used as transistor M2, are one embodiment of NOSRAM.
  • Si transistors may be used as transistor M3.
  • Si transistors can increase the field effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.
  • the memory cell can be configured as a unipolar circuit.
  • FIG. 26G shows a gain cell type memory cell 957 having three transistors and one capacitance element.
  • the memory cell 957 has transistors M4 to M6 and a capacitance element CC.
  • the first terminal of transistor M4 is connected to the first terminal of the capacitance element CC, the second terminal of transistor M4 is connected to the wiring BIL, and the gate of transistor M4 is connected to the wiring WOL.
  • the second terminal of the capacitance element CC is connected to the first terminal of transistor M5 and the wiring GNDL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of the capacitance element CC.
  • the second terminal of transistor M6 is connected to the wiring BIL, and the gate of transistor M6 is connected to the wiring RWL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a write word line
  • the wiring RWL functions as a read word line.
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and bringing the wiring BIL and the first terminal of the capacitance element CC into electrical continuity. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitance element CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby retaining the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5.
  • Data is read by precharging the wiring BIL with a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are in a conductive state. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5) can be read.
  • the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.
  • the memory cell can be configured as a unipolar circuit.
  • the memory cell 957b shown in FIG. 26H has transistors M4 to M6, and does not have a capacitance element CC.
  • the first terminal of transistor M4 is connected to the gate of transistor M5 and node N, the second terminal of transistor M4 is connected to wiring WBL, and the gate of transistor M4 is connected to wiring WOL.
  • the first terminal of transistor M5 is connected to wiring SL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6.
  • the second terminal of transistor M6 is connected to wiring RBL, and the gate of transistor M6 is connected to wiring RWL.
  • a high-level potential is applied to the wiring WOL to turn on the transistor M4, and the wiring WBL and node N are brought into electrical continuity, so that charge is accumulated in the node N. Then, a low-level potential is applied to the wiring WOL to turn off the transistor M4, and the potential of the node N is maintained. Note that a constant potential (GND (ground potential) or low potential)) is always applied to the wiring SL.
  • GND ground potential
  • a predetermined potential is precharged to the wiring RBL.
  • the potential of the wiring SL is kept constant.
  • the potential of the wiring RWL is set to a high potential and the transistor M6 is turned on, thereby bringing the wiring RWL and the second terminal of the transistor M5 into a conductive state.
  • a high potential is applied to the second terminal of transistor M5, and GND or a low potential is applied to the first terminal.
  • a potential having a magnitude equivalent to the data written to node N is applied to the gate of transistor M5. In other words, the type of data determines whether transistor M5 is in an on state or an off state.
  • the difference between the gate potential and the source potential of transistor M5 is lower than the threshold voltage of transistor M5.
  • the difference between the gate potential and the source potential of transistor M5 is higher than the threshold voltage of transistor M5.
  • transistor M5 is turned off (transistor M6 is turned on), so no current flows from wiring RBL to wiring SL.
  • both transistors M5 and M6 are turned on, so a current flows from wiring RBL to wiring SL.
  • the data held in the memory cell can be read from the current flowing through wiring RBL or the potential of wiring RBL.
  • OS-SRAM 27 shows an example of a static random access memory (SRAM) using an OS transistor.
  • SRAM static random access memory
  • OS-SRAM oxide semiconductor SRAM
  • a memory cell 958 shown in FIG. 27 is a memory cell of an SRAM capable of backing up data.
  • Memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.
  • the first terminal of transistor M7 is connected to the wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10.
  • the gate of transistor M7 is connected to the wiring WOL.
  • the first terminal of transistor M8 is connected to the wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9.
  • the gate of transistor M8 is connected to the wiring WOL.
  • the second terminal of transistor MS1 is connected to the wiring VDL.
  • the second terminal of transistor MS2 is connected to the wiring VDL.
  • the second terminal of transistor MS3 is connected to the wiring GNDL.
  • the second terminal of transistor MS4 is connected to the wiring GNDL.
  • the second terminal of transistor M9 is connected to the first terminal of capacitance element CD1, and the gate of transistor M9 is connected to wiring BRL.
  • the second terminal of transistor M10 is connected to the first terminal of capacitance element CD2, and the gate of transistor M10 is connected to wiring BRL.
  • the second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.
  • the wiring BIL and the wiring BILB function as bit lines
  • the wiring WOL functions as a word line
  • the wiring BRL is a wiring that controls the on/off state of the transistors M9 and M10.
  • the wiring VDL is a wiring that provides a high-level potential
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.
  • the memory cell 958 forms an inverter loop with the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are on, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively.
  • a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.
  • the wirings BIL and BILB are precharged to a predetermined potential beforehand, and then a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL.
  • the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB.
  • the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL.
  • the potentials of the wirings BIL and BILB change from the precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.
  • OS transistors as the transistors M7 to M10. This allows the written data to be held for a long time by the transistors M7 to M10, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be eliminated.
  • Si transistors may be used as transistors MS1 to MS4.
  • the driving circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Also, as shown in FIG. 28A, the driving circuit 910 and memory array 920 may be provided overlapping each other. By providing the driving circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Also, as shown in FIG. 28B, the memory array 920 may be provided in multiple layers on the driving circuit 910.
  • Figure 29 shows a block diagram of the arithmetic unit 960.
  • the arithmetic unit 960 shown in Figure 29 can be applied to, for example, a CPU (Central Processing Unit).
  • the arithmetic unit 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a large number (several tens to several hundreds) of processor cores capable of parallel processing more than a CPU.
  • the arithmetic device 960 shown in FIG. 29 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990.
  • the substrate 990 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 999 and the cache interface 989 may be provided on separate chips.
  • the cache 999 is connected to a main memory provided on a separate chip via a cache interface 989.
  • the cache interface 989 has a function of supplying a portion of the data held in the main memory to the cache 999.
  • the cache interface 989 also has a function of outputting a portion of the data held in the cache 999 to the ALU 991 or register 996, etc. via the bus interface 998.
  • a memory array 920 can be provided by stacking it on the arithmetic unit 960.
  • the memory array 920 can be used as a cache.
  • the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999.
  • a drive circuit 910 is included as part of the cache interface 989.
  • the arithmetic device 960 shown in FIG. 29 is merely an example of a simplified configuration, and the actual arithmetic device 960 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic device 960 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993, decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.
  • the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates a signal for controlling the operation of the ALU 991. In addition, the interrupt controller 994 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state while the arithmetic device 960 is executing a program. The register controller 997 generates an address for the register 996, and reads and writes to the register 996 depending on the state of the arithmetic device 960.
  • the timing controller 995 also generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997.
  • the timing controller 995 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 997 selects the holding operation in the register 996 according to instructions from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.
  • Figs. 30A and 30B show perspective views of a semiconductor device 970A.
  • the semiconductor device 970A has a layer 930 in which a memory array is provided on the arithmetic device 960.
  • the layer 930 has memory arrays 920L1, 920L2, and 920L3.
  • the arithmetic device 960 and each memory array have overlapping areas.
  • Fig. 30B shows the arithmetic device 960 and layer 930 separated.
  • connection distance between them can be shortened. This allows the communication speed between them to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the layer 930 having a memory array and the arithmetic device 960 As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method of stacking the layer 930 having a memory array directly on the arithmetic device 960 (also called monolithic stacking) may be used, or a method of forming the arithmetic device 960 and the layer 930 on different substrates, bonding the two substrates, and electrically connecting them using a through via or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so it is possible to reduce not only the chip size but also the manufacturing cost.
  • the arithmetic device 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache.
  • the memory array 920L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory array 920L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory array 920L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory array 920L3 has the largest capacity and is accessed the least frequently.
  • the memory array 920L1 has the smallest capacity and is accessed the most frequently.
  • each memory array provided in the layer 930 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided.
  • the driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1.
  • the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2
  • the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.
  • the drive circuit 910L1 may function as part of the cache interface 989, or the drive circuit 910L1 may be configured to be connected to the cache interface 989.
  • the drive circuit 910L2 and the drive circuit 910L3 may also function as part of the cache interface 989, or may be configured to be connected to it.
  • the control circuit 912 can cause some of the multiple memory cells 950 in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.
  • the semiconductor device 900 can cause some of the multiple memory cells 950 to function as a cache, and the other part to function as a main memory. In other words, the semiconductor device 900 can function both as a cache and as a main memory.
  • the semiconductor device 900 according to one aspect of the present invention can function as, for example, a universal memory.
  • a layer 930 having one memory array 920 may be provided on top of the computing device 960.
  • Figure 31A shows a perspective view of the semiconductor device 970B.
  • one memory array 920 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 31A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of the areas L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of the area L1. With such a configuration, it is possible to improve the efficiency of the calculation processing and the processing speed.
  • Figure 31B shows a perspective view of semiconductor device 970C.
  • the semiconductor device 970C has a layer 930L1 having a memory array 920L1 stacked on top of a layer 930L2 having a memory array 920L2, and a layer 930L3 having a memory array 920L3 stacked on top of that.
  • the memory array 920L1 which is physically closest to the computing device 960, can be used as a higher-level cache, and the memory array 920L3, which is the furthest, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory array can be increased, thereby further improving processing power.
  • Figure 32A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that, although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Registers also have the function of storing setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed.
  • a high-capacity, non-volatile storage device such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 32A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • Figure 32B also shows an example in which SRAM is used for part of the cache and an OS memory according to one aspect of the present invention is used for the other part.
  • the lowest level cache can be called an LLC (Last Level cache).
  • LLC Low Level cache
  • the OS memory of one embodiment of the present invention has a fast operating speed and is capable of retaining data for a long period of time, making it suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.) and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 32B, not only the OS memory but also DRAM can be used for the main memory.
  • FIG. 33A is a block diagram showing a configuration example of a display device 70 which is a display device of one embodiment of the present invention.
  • the display device 70 includes a display portion 80, a scanning line driver circuit 71, a signal line driver circuit 73, a power supply circuit 75, and a reference potential generating circuit 77.
  • the display portion 80 includes a plurality of pixels 81 arranged in a matrix. Note that the power supply circuit 75 may be provided outside the display device 70.
  • the scanning line driving circuit 71 is electrically connected to the pixels 81 via the wiring 31 (wiring 31a, wiring 31b, and wiring 31c).
  • the wiring 31 extends, for example, in the row direction of the matrix.
  • the signal line driving circuit 73 is electrically connected to the pixels 81 via the wiring 33.
  • the wiring 33 extends, for example, in the column direction of the matrix.
  • the power supply circuit 75 is electrically connected to the pixels 81 via the wiring 35.
  • the wiring 35 extends, for example, in the row direction of the matrix.
  • the reference potential generating circuit 77 is electrically connected to the pixels 81 via the wiring 38.
  • the wiring 38 extends, for example, in the column direction of the matrix.
  • the pixel 81 has a display element (also called a display device), and can display an image on the display unit 80 by using the display element.
  • a display element for example, a light-emitting element (also called a light-emitting device) can be used, and specifically, an organic EL element can be used.
  • a liquid crystal element also called a liquid crystal device
  • the display element for example, a light-emitting element (also called a light-emitting device) can be used, and specifically, an organic EL element can be used.
  • a liquid crystal element also called a liquid crystal device
  • the scanning line driving circuit 71 has a function of selecting, for example, the pixels 81 to which image data is to be written, for each row. Specifically, the scanning line driving circuit 71 can select the pixels 81 to which image data is to be written, by outputting a signal to the wiring 31. Here, the scanning line driving circuit 71 can select all the pixels 81 by, for example, outputting the signal to the wiring 31 in the first row, and then outputting the signal to the wiring 31 in the second row, and so on up to the wiring 31 in the final row. Thus, the signal that the scanning line driving circuit 71 outputs to the wiring 31 is a scanning signal, and the wiring 31 provided in the display device 70 can be called a scanning line.
  • the signal line driving circuit 73 has a function of generating image data.
  • the image data is supplied to the pixels 81 via the wiring 33.
  • the scanning line driving circuit 71 can write image data to all the pixels 81 included in the row selected.
  • the image data can be expressed as a signal (image signal). Therefore, the wiring 33 provided in the display device 70 can be called a signal line.
  • the power supply circuit 75 has a function of generating a power supply potential and supplying it to the wiring 35.
  • the power supply circuit 75 has a function of generating, for example, a high power supply potential (hereinafter also simply referred to as "high potential” or “VDD”) and supplying it to the wiring 35.
  • the power supply circuit 75 may also have a function of generating a low power supply potential (hereinafter also simply referred to as "low potential” or "VSS").
  • the wiring 35 functions as a power supply line.
  • the reference potential generating circuit 77 has the function of generating a reference potential and supplying it to the wiring 38. Since the potential of the wiring 38 becomes the reference potential, the wiring 38 can be said to be a reference potential line. Note that the electrical characteristics of each pixel may be read out to the reference potential generating circuit 77 outside the pixel via the wiring 38. In other words, the reference potential generating circuit 77 may have the function of sensing the electrical characteristics of each pixel. The reference potential generating circuit 77 may sense the deterioration and variation of elements (transistors or light-emitting elements, etc.) within each pixel by reading the electrical characteristics of each pixel. The deterioration and variation of image quality may then be corrected by feeding back the read characteristics to the video signal.
  • elements transistor or light-emitting elements, etc.
  • [Signal Line Driving Circuit] 34A is a block diagram showing a configuration example of the signal line driver circuit 73.
  • the signal line driver circuit 73 includes a shift register circuit 171, latch circuits 173 ⁇ 1> to 173 ⁇ n/2>, and demultiplexer circuits 175 ⁇ 1> to 175 ⁇ n/2>, where n is an even number equal to or greater than 4.
  • the latch circuits 173 ⁇ 1> to 173 ⁇ n/2> are electrically connected to a circuit 17 provided outside the signal line driver circuit 73.
  • the latch circuit 173 is electrically connected to an input terminal of the demultiplexer circuit 175 via a wiring 34.
  • the output terminal of the demultiplexer circuit 175 is electrically connected to a wiring 33.
  • FIG. 34A shows an example in which the demultiplexer circuit 175 has two output terminals, each of which is electrically connected to a different wiring 33.
  • the two output terminals of the demultiplexer circuit 175 ⁇ 1> are electrically connected to the wiring 33[1] and the wiring 33[2], respectively.
  • the two output terminals of the demultiplexer circuit 175 ⁇ n/2> are electrically connected to the wiring 33[n-1] and the wiring 33[n], respectively.
  • the circuit 17 functions as an interface to receive image data from outside the display device 70.
  • the circuit 17 may also generate image data.
  • the image data output by the circuit 17 is supplied to the latch circuits 173 ⁇ 1> to 173 ⁇ n/2>.
  • the shift register circuit 171 has a function of generating a signal for controlling the driving of the latch circuit 173. For example, when a start pulse is supplied to the shift register circuit 171, the shift register circuit 171 sequentially outputs signals for controlling the driving of the latch circuits 173 ⁇ 1> to 173 ⁇ n/2>.
  • the latch circuit 173 has the function of holding or outputting the image data output from the circuit 17. Whether the latch circuit 173 holds or outputs the image data is selected based on a signal supplied to the latch circuit 173 from the shift register circuit 171.
  • the demultiplexer circuit 175 has a function of outputting the image data output by the latch circuit 173 from one of the output terminals of the demultiplexer circuit 175.
  • the demultiplexer circuit 175 can determine the output terminal to which the image data is output according to a selection signal input to a selection signal input terminal of the demultiplexer circuit 175.
  • the selection signal can be generated by a selection signal generation circuit 19 provided outside the signal line drive circuit 73.
  • the selection signal generation circuit 19 may be included in the signal line drive circuit 73.
  • the scale of the signal line driving circuit 73 can be reduced.
  • the number of latch circuits 173 included in the signal line driving circuit 73 can be reduced.
  • the number of transistors included in the shift register circuit 171 can be reduced.
  • the signal line drive circuit 73 will have n latch circuits 173.
  • the number of latch circuits 173 can be reduced to less than n. This allows the signal line drive circuit 73 to be smaller in scale.
  • the display device 70 can be a high-definition display device.
  • the signal line driver circuit 73 can be made smaller. Therefore, the display device 70 can be a small display device. Furthermore, the display device 70 can be a display device with a narrow frame. Note that the demultiplexer circuit 175 does not need to be provided in the signal line driver circuit 73. Furthermore, the demultiplexer circuit 175 may be provided outside the signal line driver circuit 73.
  • the demultiplexer circuit 175 has two output terminals, but the demultiplexer circuit 175 may have, for example, three or more output terminals.
  • the signal line driving circuit 73 can be configured to have n/3 demultiplexer circuits 175.
  • the number of wirings 33 electrically connected to the signal line driving circuit 73 can be reduced. This allows the display device 70 to have higher resolution, be more compact, and have a narrower frame.
  • Figure 34B is a circuit diagram showing an example of the configuration of the latch circuit 173. Note that Figure 34B also shows the circuit 17 and the shift register circuit 171 to show the connection relationship.
  • circuit diagrams may not show all of the components of a circuit.
  • a circuit may have a buffer amplifier in addition to the elements shown in the circuit diagram.
  • the latch circuit 173 is electrically connected to terminals R, D, and Q.
  • Terminal R is electrically connected to the output terminal of the shift register circuit 171.
  • Terminal D is electrically connected to the output terminal of the circuit 17.
  • Terminal Q is electrically connected to the wiring 34. From the perspective of the latch circuit 173, terminals R and D are input terminals, and terminal Q is an output terminal.
  • the latch circuit 173 includes a transistor 381, a transistor 383, a capacitance 385, and an inverter circuit 390.
  • the gate of transistor 381 and the input terminal of inverter circuit 390 are electrically connected to terminal R.
  • One of the source or drain of transistor 381 is electrically connected to terminal D.
  • the other of the source or drain of transistor 381 is electrically connected to one of the source or drain of transistor 383.
  • One of the source or drain of transistor 383 is electrically connected to one electrode of capacitor 385.
  • the other of the source or drain of transistor 383 is electrically connected to terminal Q.
  • a potential VSS can be supplied to the other electrode of capacitor 385.
  • the on and off states of transistors 381 and 383 are switched by a signal input to terminal R. For example, when a signal corresponding to a logical value of "1" is input to terminal R, transistor 381 is turned on and transistor 383 is turned off. Also, for example, when a signal corresponding to a logical value of "0" is input to terminal R, transistor 381 is turned off and transistor 383 is turned on.
  • the drive of the latch circuit 173 can be controlled by the signal input to the terminal R.
  • the terminal R is electrically connected to the output terminal of the shift register circuit 171. Therefore, the shift register circuit 171 can control the drive of the latch circuit 173.
  • the transistor 381 and the transistor 383 are preferably OS transistors.
  • the OS transistor preferably uses a metal oxide having at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region.
  • element M is aluminum, gallium, yttrium, or tin
  • the off-current of the transistor 381 and the transistor 383 can be significantly reduced. Therefore, leakage of the potential held in the capacitor 385 can be suppressed.
  • the image data held in the latch circuit 173 can be analog data. Note that digital data may be held in the latch circuit 173.
  • the signal line driver circuit 73 has a digital-analog conversion circuit (D/A conversion circuit), and the digital data output from the latch circuit 173 is converted into analog data by the D/A conversion circuit, and then the analog data is supplied to the demultiplexer circuit 175.
  • D/A conversion circuit digital-analog conversion circuit
  • a buffer circuit may be provided between transistor 381 and transistor 383.
  • the transistor 200 or the like shown in the above embodiment as the transistor 381 and the transistor 383, since the area occupied by the latch circuit 173 can be reduced.
  • Figure 34C is a circuit diagram showing an example configuration of an inverter circuit 390.
  • the inverter circuit 390 has a transistor 92, a transistor 94, a transistor 95, a transistor 97, and a capacitor 99.
  • a potential VDD can be supplied to one of the source or drain of the transistor 92, the gate of the transistor 92, and one of the source or drain of the transistor 95 in the inverter circuit 390.
  • the other of the source or drain of the transistor 92 is electrically connected to one of the source or drain of the transistor 94.
  • the other of the source or drain of the transistor 94 is electrically connected to the gate of the transistor 95.
  • the other of the source or drain of the transistor 95 is electrically connected to one electrode of the capacitor 99.
  • the gate of the transistor 95 is electrically connected to the other electrode of the capacitor 99.
  • the one electrode of the capacitor 99 is electrically connected to one of the source or drain of the transistor 97.
  • the one of the source or drain of the transistor 97 is electrically connected to the gate of the transistor 383.
  • a potential VSS can be supplied to the other of the source or drain of the transistor 94 and the other of the source or drain of the transistor 97.
  • All the transistors in the latch circuit 173 can be transistors of the same polarity, for example, n-channel transistors. This allows all the transistors in the latch circuit 173 to be the same type of transistor.
  • all the transistors in the latch circuit 173 can be OS transistors.
  • the transistor 200 or the like shown in the above embodiment can be applied to all the transistors in the latch circuit 173.
  • the latch circuit 173 By using the same type of transistor for all the transistors in the latch circuit 173, all the transistors in the latch circuit 173 can be manufactured in the same process. Therefore, the number of manufacturing steps for the latch circuit 173 can be reduced compared to when the latch circuit 173 has two or more types of transistors. In addition, by using the transistors shown in the above embodiment for all the transistors in the latch circuit 173, the latch circuit 173 can be miniaturized.
  • transistors in the latch circuit 173 do not necessarily have to be the transistors shown in the above embodiment.
  • some of the transistors may be planar type transistors.
  • At least one of the transistors 92, 94, 95, and 97 in the inverter circuit 390 does not have to be an OS transistor and may be, for example, a Si transistor.
  • one or both of the transistors 381 and 383 do not have to be an OS transistor and may be, for example, a Si transistor.
  • Figure 35 is a block diagram showing a specific configuration example of the demultiplexer circuit 175 of the signal line driving circuit 73.
  • the display unit 80 shown in Figure 35 has a plurality of pixels 81 arranged in a matrix of m rows and n columns.
  • the pixel 81 in the first row and first column is described as pixel 81[1,1]
  • the pixel 81 in the mth row and nth column is described as pixel 81[m,n].
  • Figure 35 also shows the selection signal generation circuit 19.
  • Figure 35 shows an example in which the demultiplexer circuit 175 has two transistors 93.
  • the signal line driver circuit 73 has transistors 93[1] to 93[n].
  • FIG. 35 shows an example in which the demultiplexer circuit 175 ⁇ 1> has transistors 93[1] and 93[2], and the demultiplexer circuit 175 ⁇ n/2> has transistors 93[n-1] and 93[n].
  • One of the source or drain of transistor 93[1] and one of the source or drain of transistor 93[2] function as an input terminal of demultiplexer circuit 175 ⁇ 1> and are electrically connected to wiring 34 ⁇ 1>.
  • One of the source or drain of transistor 93[n-1] and one of the source or drain of transistor 93[n] function as an input terminal of demultiplexer circuit 175 ⁇ n/2> and are electrically connected to wiring 34 ⁇ n/2>.
  • the other of the source and drain of the transistor 93[1] functions as a first output terminal of the demultiplexer circuit 175 ⁇ 1> and is electrically connected to the wiring 33[1].
  • the other of the source and drain of the transistor 93[2] functions as a second output terminal of the demultiplexer circuit 175 ⁇ 1> and is electrically connected to the wiring 33[2].
  • the other of the source and drain of the transistor 93[n-1] functions as a first output terminal of the demultiplexer circuit 175 ⁇ n/2> and is electrically connected to the wiring 33[n-1].
  • the other of the source and drain of the transistor 93[n] functions as a second output terminal of the demultiplexer circuit 175 ⁇ n/2> and is electrically connected to the wiring 33[n].
  • the gate of the transistor 93[1] functions as a selection signal input terminal of the demultiplexer circuit 175 ⁇ 1> and is electrically connected to the selection signal generation circuit 19 through the wiring 32_1.
  • the gate of the transistor 93[2] functions as a selection signal input terminal of the demultiplexer circuit 175 ⁇ 1> and is electrically connected to the selection signal generation circuit 19 through the wiring 32_2.
  • the gate of the transistor 93[n-1] functions as a selection signal input terminal of the demultiplexer circuit 175 ⁇ n/2> and is electrically connected to the selection signal generation circuit 19 through the wiring 32_1.
  • the gate of the transistor 93[n] functions as a selection signal input terminal of the demultiplexer circuit 175 ⁇ n/2> and is electrically connected to the selection signal generation circuit 19 through the wiring 32_2.
  • the selection signal generation circuit 19 can generate, for example, a first signal and a second signal as the selection signal.
  • the selection signal generation circuit 19 can output the first signal to the wiring 32_1 and the second signal to the wiring 32_2.
  • the first signal is a signal that turns the transistor 93 on and the second signal is a signal that turns the transistor 93 off, so that the demultiplexer circuit 175 can output image data from the first output terminal.
  • the first signal is a signal that turns the transistor 93 off and the second signal is a signal that turns the transistor 93 on, so that the demultiplexer circuit 175 can output image data from the second output terminal.
  • the second signal when the first signal is a signal that turns transistor 94 on, the second signal can be a signal that turns transistor 93 off, and when the first signal is a signal that turns transistor 94 off, the second signal can be a signal that turns transistor 93 on.
  • the first and second signals can be complementary to each other.
  • the first and second signals are 1-bit digital signals, when the first signal is at a high potential, the second signal is at a low potential, and when the first signal is at a low potential, the second signal is at a high potential.
  • the demultiplexer circuit 175 may have three or more transistors 93. In this case, the demultiplexer circuit 175 can have three or more output terminals.
  • FIG. 33B is a plan view showing a configuration example of a pixel 61 included in a display device.
  • the pixel 61 can have a plurality of sub-pixels 63.
  • the pixel 81 shown in FIG. 33A can be applied to each of the sub-pixels 63.
  • FIG. 33B shows an example in which the pixel 61 has sub-pixels 63R, 63G, and 63B as the sub-pixels 63.
  • the planar shape of the sub-pixels shown in FIG. 33B corresponds to the planar shape of the light-emitting region of the light-emitting element. Note that FIG.
  • 33B shows the aperture ratios (which can also be called the size or the size of the light-emitting region) of the sub-pixels 63R, 63G, and 63B as being equal or approximately equal, but one embodiment of the present invention is not limited to this.
  • the aperture ratios of the sub-pixels 63R, 63G, and 63B can each be determined appropriately.
  • the aperture ratios of subpixel 63R, subpixel 63G, and subpixel 63B may be different from one another, or two or more of them may be equal or approximately equal.
  • a stripe arrangement is applied as the arrangement method of the sub-pixels 63.
  • an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as the arrangement method of the sub-pixels 63.
  • the sub-pixels 63R, 63G, and 63B each emit light of a different color.
  • Examples of the sub-pixels 63R, 63G, and 63B include sub-pixels of three colors, red (R), green (G), and blue (B), and sub-pixels of three colors, yellow (Y), cyan (C), and magenta (M).
  • Four or more sub-pixels 63 may be provided in the pixel 61.
  • the pixel 61 may be provided with four sub-pixels of R, G, B, and white (W).
  • the display device 70 can display a full-color image on the display unit 80 by having the pixel 61 have a plurality of sub-pixels 63 that emit light of different colors.
  • the pixel 61 may be provided with sub-pixels of R, G, B, and infrared light (IR).
  • the display unit 80 may be provided with a sensor, for example, a sensor may be provided in the pixel 61.
  • the display unit 80 may have a function as a fingerprint sensor.
  • the display unit 80 may have a function as an optical or ultrasonic fingerprint sensor.
  • FIG. 33C is a circuit diagram showing an example configuration of pixel 81 shown in FIG. 33A.
  • the pixel shown in FIG. 33C has a pixel circuit 90 and a light-emitting element 91.
  • Pixel circuit 90 has transistor 41, transistor 42, transistor 43, transistor 53, capacitor 51, and capacitor 58.
  • pixel circuit 90 is a 4Tr2C type pixel circuit.
  • one configuration selected from the transistor 200, the transistor 200(2), the transistor 200(3), etc. shown in the previous embodiment can be applied to each of the transistors 41, 42, 43, and 53.
  • one configuration selected from the capacitor 100, the capacitor 100b, etc. shown in the previous embodiment can be applied to each of the capacitors 51, 58, etc.
  • the transistors M4, M5, and M6 shown in the above embodiments can be applied to the transistors 42, 41, and 43, respectively, and the wirings WOL, WBL, and SL can be applied to the wirings 31a, 33, and 35, respectively.
  • one of the source and drain of the transistor 42 is electrically connected to the wiring 33.
  • the other of the source and drain of the transistor 42 is electrically connected to one electrode of the capacitor 51 and the gate of the transistor 41.
  • the gate of the transistor 42 is electrically connected to the wiring 31a.
  • One of the source and drain of the transistor 41 is electrically connected to one of the source and drain of the transistor 43.
  • the other of the source and drain of the transistor 43 is electrically connected to the wiring 35.
  • the gate of the transistor 43 is electrically connected to the wiring 31c.
  • One electrode of the capacitor 58 is electrically connected to the other of the source and drain of the transistor 41, one of the source and drain of the transistor 53, the other electrode of the capacitor 51, and one electrode of the light-emitting element 91.
  • the other electrode of the capacitor 58 is electrically connected to the wiring 35.
  • the other of the source and drain of the transistor 53 is electrically connected to the wiring 38.
  • the gate of the transistor 53 is electrically connected to the wiring 31b.
  • the other electrode of the light-emitting element 91 is electrically connected to the wiring 37.
  • Transistor 43 functions as a switch and has the function of controlling the conductive or non-conductive state between wiring 35 and one of the source or drain of transistor 41 based on the potential of wiring 31c.
  • a current having a magnitude corresponding to the gate potential of the transistor 41 flows, for example, from the wiring 35 to the wiring 37. This causes the light-emitting element 91 to emit light with a luminance corresponding to the gate potential of the transistor 41.
  • a current from flowing to the light-emitting element 91 it is possible to prevent a current from flowing to the light-emitting element 91, and therefore prevent the light-emitting element 91 from emitting light.
  • OS transistors have higher field-effect mobility than, for example, transistors using amorphous silicon. Therefore, by using OS transistors as transistors 41 and 42, the display device 70 can be driven at high speed.
  • the off-state current of an OS transistor is extremely small. Therefore, by using an OS transistor as the transistor 42, the charge stored in the capacitor 51 can be held for a long period of time. As a result, the image data written to the subpixel 63 can be held for a long period of time, and the frequency of refresh operations (rewriting image data to the subpixel 63) can be reduced. As a result, the power consumption of the display device 70 can be reduced.
  • the source-drain voltage of the transistor 41 which is a driving transistor. Since an OS transistor has a higher withstand voltage between the source and drain compared to a Si transistor, a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor for the transistor 41, it is possible to increase the amount of current flowing through the light-emitting element 91 and increase the emission luminance of the light-emitting element 91.
  • the light-emitting element 91 for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used.
  • the light-emitting material possessed by the light-emitting element 91 include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material), and an inorganic compound (for example, a quantum dot material).
  • an LED such as a micro LED (light-emitting diode) can also be used as the light-emitting element 91.
  • the semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframe computers, space equipment, data centers (also referred to as Data Centers: DCs), and various electronic devices.
  • DCs Data Centers
  • a display device including a semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices.
  • a display device including a semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.
  • Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • a resolution of 4K, 8K, or more is preferable.
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 36A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 36A has a semiconductor device 710 in a mold 711. In FIG. 36A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as a Cu-Cu direct bonding.
  • a so-called on-chip memory configuration can be formed in which the memory is formed directly on the processor.
  • the on-chip memory configuration makes it possible to increase the operation speed of the interface between the processor and the memory.
  • connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and it is therefore possible to increase the number of connection pins.
  • Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • HBM requires many wiring connections to achieve a wide memory bandwidth. For this reason, the interposer that implements the HBM requires fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 36B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • Fig. 37A shows a perspective view of a large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 37A has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view of FIG. 37B, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 37C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 37C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for those semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be referred to.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be suitably used in an environment where radiation may be incident.
  • the OS transistor can be suitably used in outer space.
  • the OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe.
  • Examples of radiation include X-rays and neutron rays.
  • outer space refers to an altitude of 100 km or higher, for example, and the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.
  • Figure 37D shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Figure 37D also shows a planet 6804 in space.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the battery management system or battery control circuit described above is preferable because it consumes low power and has high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term data management, such as ensuring data immutability.
  • long-term data management such as ensuring data immutability.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.
  • Figure 37E shows a storage system applicable to a data center.
  • the storage system 7010 shown in Figure 37E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems typically provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the cache memory, which hold a potential corresponding to the data
  • the frequency of refreshing can be reduced and power consumption can be reduced.
  • miniaturization is possible.
  • FIG. 38A to 38F An example of a wearable device that can be worn on the head will be described with reference to Figures 38A to 38F.
  • These wearable devices have at least one of a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • the electronic device 700A shown in FIG. 38A has a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • the display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display with extremely high resolution.
  • the semiconductor device of one embodiment of the present invention can be applied to the control unit (not shown). This can reduce the power consumption of the electronic device.
  • Electronic device 700A can project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through optical member 753. Therefore, electronic device 700A is an electronic device capable of AR display.
  • the electronic device 700A may be provided with a camera capable of capturing an image in front of it as an imaging unit.
  • the electronic device 700A may be provided with an acceleration sensor such as a gyro sensor, so that the electronic device 700A can detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector may be provided to which a cable through which a video signal and a power supply potential can be connected.
  • the electronic device 700A is also provided with a battery, which can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or playing a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • Electronic device 800A shown in FIG. 38B and electronic device 800B shown in FIG. 38C each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • the display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, the electronic device can display with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the semiconductor device of one embodiment of the present invention can be applied to the control portion 824. This allows the power consumption of the electronic device to be reduced.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Electrical device 800A and electronic device 800B can each be considered electronic devices for VR.
  • a user wearing electronic device 800A or electronic device 800B can view the image displayed on display unit 820 through lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head. Note that in FIG. 38B and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 38A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • the electronic device 800B shown in FIG. 38C has an earphone unit 827.
  • the earphone unit 827 and the control unit 824 may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the mounting unit 823.
  • the earphone unit 827 and the mounting unit 823 may also have a magnet. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • Figures 38D and 38E show perspective views of a goggle-type electronic device 850A for VR.
  • Figures 38D and 38E show an example in which a pair of curved display devices 840 (display device 840_R and display device 840_L) are included in a housing 845.
  • Electronic device 850A also includes a motion detection unit 841, a gaze detection unit 842, a calculation unit 843, a communication unit 844, a lens 848, an operation button 851, a wearing device 854, a sensor 855, a dial 856, and the like.
  • the user can see one display device per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax.
  • the display device 840 is curved in an arc shape roughly centered on the user's eye. This allows the user to see more natural images because the distance from the user's eye to the display surface of the display device 840 is constant.
  • the user's eyes can be configured to be located in the normal direction of the display surface of the display device 840, so that the effect can be essentially ignored, especially in the horizontal direction, and more realistic images can be displayed.
  • lens 848 is located between display device 840 and the user's eyes.
  • FIG. 38E shows an example having dial 856 for changing the position of the lens to adjust visibility. Note that if electronic device 850A has an autofocus function, it does not need to have dial 856 for adjusting visibility.
  • Figure 38F shows a goggle-type electronic device 850B that has one display device 840. This configuration makes it possible to reduce the number of parts.
  • the display device 840 can display two images, one for the right eye and one for the left eye, side by side in two left and right areas. This makes it possible to display a stereoscopic image using binocular parallax. Note that the display device 840 may display two different images side by side using parallax, or may display two identical images side by side without using parallax.
  • a single image visible to both eyes may be displayed across the entire area of the display device 840. This allows a panoramic image to be displayed across both ends of the field of view, enhancing realism.
  • a display device can be applied to the display device 840.
  • the display device according to one embodiment of the present invention has extremely high definition, so that even if the image is enlarged using the lens 848, the user cannot see the pixels, and a more realistic image can be displayed.
  • the electronic device 6500 shown in Figure 39A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 has a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509.
  • the electronic device 6520 shown in FIG. 39B is a portable information terminal that can be used as a tablet terminal.
  • the electronic device 6520 has a housing 6501, a display unit 6502, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a control device 6509, and a connection terminal 6519.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 has, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 6502 and the control device 6509.
  • Figure 39C is a schematic cross-sectional view including the end of the housing 6501 of the electronic device 6500 or electronic device 6520 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 39D shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 39D can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG 39E shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and a control device 7215.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7215 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be used for one or both of the display portion 7000 and the control device 7215.
  • Figures 39F and 39G show an example of digital signage.
  • the digital signage 7300 shown in FIG. 39F has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 39G shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 arranged along the curved surface of the pole 7401.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can be made to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the semiconductor device and display device of one embodiment of the present invention can be applied to the vicinity of the driver's seat of an automobile, which is a moving object.
  • Figure 40A is a diagram showing the area around the windshield in the interior of a car.
  • Figure 40A shows display panels 9001a, 9001b, and 9001c attached to the dashboard, and display panel 9001d attached to a pillar.
  • the display panels 9001a to 9001c can provide various information by displaying navigation information, a speedometer, a tachometer, mileage, a fuel gauge, gear status, air conditioning settings, and the like.
  • the display items and layouts displayed on the display panels can be changed as appropriate to suit the user's preferences, improving the design.
  • the display panels 9001a to 9001c can also be used as lighting devices.
  • the display panel 9001d can display images from an imaging means installed on the vehicle body to complement the field of view (blind spots) blocked by the pillars. In other words, by displaying images from an imaging means installed on the outside of the vehicle, blind spots can be complemented and safety can be increased. In addition, by displaying images that complement the invisible parts, safety can be confirmed more naturally and without any sense of discomfort.
  • the display panel 9001d can also be used as a lighting device.
  • FIG 40B is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself through the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • the mobile information terminal 9200 shown in FIG. 40B has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • FIG 40C is a perspective view of a foldable mobile information terminal 9201.
  • the mobile information terminal 9201 has a housing 9000a, a housing 9000b, a display portion 9001, and an operation button 9056.
  • the housings 9000a and 9000b are connected by a hinge 9055, which allows the device to be folded in half.
  • the display portion 9001 of the mobile information terminal 9201 is supported by two housings (housing 9000a and housing 9000b) connected by a hinge 9055.
  • Figures 40D to 40F are perspective views showing a foldable mobile information terminal 9202. Also, Figure 40D is a perspective view of the mobile information terminal 9202 in an unfolded state, Figure 40F is a folded state, and Figure 40E is a perspective view of a state in the process of changing from one of Figures 40D and 40F to the other. In this way, the mobile information terminal 9202 can be folded into three.
  • the display unit 9001 of the mobile information terminal 9202 is supported by three housings 9000 connected by hinges 9055.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the display portion 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • the portable information terminal 9201 and the portable information terminal 9202 each have excellent portability when folded, and excellent display visibility when unfolded due to their seamless, large display areas.
  • the semiconductor device of one embodiment of the present invention can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • ADDR signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CLK: signal, GNDL: wiring, GW: signal, M10: transistor, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, VDD: potential, VDL: wiring, VSS: potential, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 10: layer, 17: circuit, 19: selection signal signal generation circuit, 31a: wiring, 31b: wiring, 31c: wiring, 31: wiring, 32_1: wiring, 32_2: wiring, 33[1]: wiring, 33[2]: wiring, 33[n-1]: wiring, 33[n]: wiring, 33: wiring, 34: wiring, 35: wiring, 37: wiring, 38: wiring, 41: transistor, 42: transistor, 43: transistor, 51: capacitance, 53: transistor, 58:

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
PCT/IB2024/055386 2023-06-09 2024-06-03 半導体装置 Ceased WO2024252248A1 (ja)

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CN202480038591.3A CN121336506A (zh) 2023-06-09 2024-06-03 半导体装置

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03291973A (ja) * 1990-04-09 1991-12-24 Fuji Xerox Co Ltd 薄膜半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2019134077A (ja) * 2018-01-31 2019-08-08 東芝メモリ株式会社 トランジスタ及び半導体記憶装置並びにトランジスタの製造方法
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03291973A (ja) * 1990-04-09 1991-12-24 Fuji Xerox Co Ltd 薄膜半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017168764A (ja) * 2016-03-18 2017-09-21 株式会社ジャパンディスプレイ 半導体装置
JP2019134077A (ja) * 2018-01-31 2019-08-08 東芝メモリ株式会社 トランジスタ及び半導体記憶装置並びにトランジスタの製造方法
JP2022049605A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 半導体装置及び半導体記憶装置

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