WO2024252247A1 - 表示装置、表示モジュール、電子機器 - Google Patents

表示装置、表示モジュール、電子機器 Download PDF

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Publication number
WO2024252247A1
WO2024252247A1 PCT/IB2024/055385 IB2024055385W WO2024252247A1 WO 2024252247 A1 WO2024252247 A1 WO 2024252247A1 IB 2024055385 W IB2024055385 W IB 2024055385W WO 2024252247 A1 WO2024252247 A1 WO 2024252247A1
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WIPO (PCT)
Prior art keywords
layer
transistor
region
electrode
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2024/055385
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English (en)
French (fr)
Japanese (ja)
Inventor
中村太紀
初見亮
池田寿雄
塚本洋介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to CN202480030975.0A priority Critical patent/CN121079731A/zh
Priority to KR1020257038455A priority patent/KR20260022295A/ko
Priority to JP2025525415A priority patent/JPWO2024252247A1/ja
Publication of WO2024252247A1 publication Critical patent/WO2024252247A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • One aspect of the present invention relates to a display device, a display module, an electronic device, or a semiconductor device.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of one aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.
  • HMDs head mounted displays
  • AR Augmented Reality
  • VR Virtual Reality
  • the frame of a liquid crystal display contains a flexible printed circuit board for connecting terminals to the outside and an external driver IC. Therefore, in order to narrow the frame, methods such as connecting the display unit and input unit to the same flexible printed circuit board or incorporating a gate driver are used.
  • Patent Document 1 describes a configuration in which a portion of a flexible display device is bent to fold back a connection terminal to the opposite side to the display surface.
  • one aspect of the present invention has an objective to provide a new display device with excellent convenience, usefulness, or reliability.
  • one objective is to provide a new display module with excellent convenience, usefulness, or reliability.
  • one objective is to provide a new electronic device with excellent convenience, usefulness, or reliability.
  • one objective is to provide a new display device, a new display module, a new electronic device, or a new semiconductor device.
  • One aspect of the present invention is a display device having a first functional layer, a second functional layer, a first substrate, and a second substrate.
  • the first functional layer has a first region and a second region, and the first functional layer is curved in the second region.
  • the first region is sandwiched between the second functional layer and the first substrate, and the first region includes a first layer and a pixel circuit.
  • the pixel circuit is sandwiched between the second functional layer and the first layer.
  • the second region is adjacent to the first region, and the second region comprises a second layer and a first shift register.
  • the second layer is continuous with the first layer, and the first shift register is formed on the second layer.
  • the second functional layer is sandwiched between the second substrate and the first region, and the second functional layer includes a display device.
  • the display device is electrically connected to the pixel circuit.
  • Another aspect of the present invention is the above-mentioned display device having a first driving circuit.
  • the first driving circuit includes a first shift register, and the first functional layer includes a signal line.
  • the signal line electrically connects the first driving circuit and the pixel circuit, and the signal line transmits a video signal.
  • first driving circuit to be arranged in the second region to supply a video signal to the signal line.
  • a pixel circuit and a display device can be arranged in the adjacent first region to display an image.
  • first functional layer is bent in the second region, it is possible to make the second region difficult to see when facing the first region.
  • region surrounding the first region in a frame-like shape difficult to see when facing the first region.
  • Another aspect of the present invention is the above-mentioned display device having a second driving circuit.
  • the second drive circuit includes a second shift register, the first functional layer has a third region and a scanning line, and the first functional layer is bent in the third region.
  • the third region is adjacent to the first region, and the third region includes a third layer and a second shift register.
  • the third layer is also continuous with the first layer, and the second shift register is formed on the third layer.
  • the scanning lines electrically connect the second drive circuit and the pixel circuits, and the scanning lines transmit selection signals.
  • a second driving circuit to be arranged in the third region to supply a selection signal to the scanning line.
  • a pixel circuit and a display device can be arranged in the adjacent first region to display an image.
  • the first functional layer is bent in the third region, it is possible to make the third region difficult to see when facing the first region.
  • Another aspect of the present invention is the above display device having a first electrode and a third driving circuit.
  • the first electrode sandwiches the second functional layer between the first functional layer, and the third drive circuit includes a third shift register.
  • the first functional layer has a fourth region and a second electrode, and the first functional layer is bent in the fourth region.
  • the fourth region is adjacent to the first region, and the fourth region includes a fourth layer and a third shift register.
  • the fourth layer is also continuous with the first layer, and the third shift register is formed on the fourth layer.
  • the second electrode forms a capacitance between the first electrode and the second electrode, the second electrode is electrically connected to a third drive circuit, and the second electrode transmits a pulse signal.
  • a third driving circuit to be placed in the fourth region and a pulse signal to be supplied to the second electrode.
  • a first electrode can be placed on the adjacent first region to detect a change in the projection capacitance between the second electrode and the first electrode. Also, the position of a finger of a user of the display device approaching the first region can be detected. Also, since the first functional layer is bent in the fourth region, the fourth region can be made difficult to see when facing the first region. Also, the region surrounding the first region in a frame-like shape can be made difficult to see when facing the first region. As a result, a novel display device with excellent convenience, usefulness, and reliability can be provided.
  • the first functional layer includes a spacer and a transistor.
  • the spacer has a first surface, a second surface, a third surface, and a first opening, and the first surface, the second surface, and the third surface are insulating.
  • the second surface faces the first surface, and the second surface is located closer to the second functional layer than the first surface.
  • the third surface connects the first surface and the second surface, and the third surface is located on a side of the first opening.
  • the transistor comprises a third electrode, a fourth electrode, a fifth electrode, a semiconductor layer and an insulating layer.
  • the third electrode comprises a region in contact with the first surface and a region overlapping with the first opening.
  • the fourth electrode has a region in contact with the second surface, a second opening, and a fourth surface.
  • the fourth surface is located on a side of the second opening, and the second opening overlaps with the first opening.
  • the fifth electrode has an area facing the third surface, and the insulating layer has an area sandwiched between the third surface and the fifth electrode.
  • the semiconductor layer has a region sandwiched between the third surface and the insulating layer, and the semiconductor layer contacts the third electrode at the first opening.
  • the semiconductor layer also contacts the fourth electrode at the fourth surface.
  • Another aspect of the present invention is the display device described above, in which the first shift register includes the transistor described above.
  • the channel length of the transistor can be shortened.
  • the on-state current of the transistor can be increased.
  • the variation in the operating characteristics of the transistor can be reduced.
  • At least a part of the first shift register can be formed in the process of forming the pixel circuit.
  • the manufacturing process of the display device can be simplified. As a result, a novel display device that is highly convenient, useful, or reliable can be provided.
  • Another aspect of the present invention is the above display device, in which the pixel circuit includes the above transistor.
  • the area occupied by the transistor can be reduced. Also, the channel length of the transistor can be shortened. Also, the on-current of the transistor can be increased. Also, the variation in the operating characteristics of the transistor can be reduced. Also, the area occupied by the pixel circuit can be reduced. Also, the resolution of the display device can be increased. As a result, a novel display device that is excellent in convenience, usefulness, and reliability can be provided.
  • Another aspect of the present invention is the above display device, in which the display device has a fifth layer, and the fifth layer contains a liquid crystal material.
  • Another aspect of the present invention is a display module having the above-mentioned display device and at least one of a connector and an integrated circuit.
  • Another aspect of the present invention is a display module having the above-mentioned display device and a light source.
  • the first layer has a transmittance of 80% or more in the visible light range.
  • the first substrate has a first end and a second end, the second end facing the first end, and the second end being located between the first end and the second layer.
  • the first substrate also has a function of distributing light incident from the first end toward the second substrate.
  • the light source faces the first end, and the light source irradiates light onto the first end.
  • the thickness of the display device can be made thinner than in a configuration in which the light source is arranged so as to sandwich the first substrate between the first region and the light source.
  • the first functional layer is bent in the second region, the second region can be made difficult to view when facing the first region.
  • the region surrounding the first region in a frame-like shape can be made difficult to view when facing the first region.
  • Another aspect of the present invention is an electronic device having the above-mentioned display device and at least one of a battery, a camera, a speaker, and a microphone.
  • the term “light-emitting device” includes an image display device that uses a light-emitting device.
  • the term “light-emitting device” may also include a module in which a connector, such as an anisotropic conductive film or TCP (Tape Carrier Package), is attached to a light-emitting device, a module in which a printed wiring board is provided at the end of a TCP, or a module in which an IC (integrated circuit) is directly mounted on a light-emitting device using the COG (chip on glass) method.
  • a connector such as an anisotropic conductive film or TCP (Tape Carrier Package)
  • TCP Transist Carrier Package
  • COG chip on glass
  • lighting fixtures and the like may have a light-emitting device.
  • a novel display device having excellent convenience, usefulness, or reliability can be provided.
  • one aspect of the present invention can provide a novel display module having excellent convenience, usefulness, or reliability.
  • one aspect of the present invention can provide a novel electronic device having excellent convenience, usefulness, or reliability.
  • a novel display device can be provided.
  • a novel display module can be provided.
  • a novel electronic device can be provided.
  • FIG. 1A and 1B are diagrams illustrating a configuration of a display device according to an embodiment.
  • 2A to 2C are diagrams illustrating a configuration of a display device according to an embodiment.
  • FIG. 3 is a diagram illustrating a configuration of the display device according to the embodiment.
  • 4A and 4B are diagrams illustrating a configuration of a display device according to an embodiment.
  • FIG. 5 is a diagram illustrating a configuration of a display device according to an embodiment.
  • 6A and 6B are diagrams illustrating a configuration of a display device according to an embodiment.
  • 7A to 7C are diagrams illustrating a configuration of a display device according to an embodiment.
  • 8A, 8C, and 8D are diagrams illustrating the configuration of a display device according to an embodiment, and FIG.
  • FIG. 8B is a diagram illustrating the operation of the display device according to an embodiment.
  • FIG. 9 is a diagram illustrating a configuration of a touch panel module according to an embodiment.
  • 10A to 10C are diagrams illustrating a configuration of a touch panel module according to an embodiment.
  • 11A to 11C are diagrams illustrating a configuration of a shift register according to an embodiment.
  • FIG. 12 is a diagram illustrating a configuration of a signal output circuit according to an embodiment.
  • FIG. 13 is a diagram illustrating a configuration of a signal output circuit according to an embodiment.
  • FIG. 14 is a diagram illustrating a configuration of a signal output circuit according to an embodiment.
  • 15A to 15D are diagrams illustrating the configuration of a transistor according to an embodiment.
  • 16A to 16F are diagrams illustrating the configuration of a transistor according to an embodiment.
  • 17A and 17B are diagrams illustrating a configuration of a transistor according to an embodiment.
  • 18A and 18B are diagrams illustrating a configuration of a transistor according to an embodiment.
  • 19A to 19D are diagrams illustrating the configuration of a transistor according to an embodiment.
  • 20A to 20D are diagrams illustrating the configuration of a transistor according to an embodiment.
  • FIG. 21 is a diagram illustrating a configuration of a signal output circuit according to an embodiment.
  • 22A and 22B are diagrams illustrating a configuration of a signal output circuit according to an embodiment.
  • 23A and 23B are diagrams illustrating a configuration of a signal output circuit according to an embodiment.
  • FIG. 24 is a diagram illustrating a configuration of a signal output circuit according to an embodiment.
  • FIG. 25 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 26 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 27 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 28 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 29 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 30 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 31 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 32 is a diagram illustrating the operation of the signal output circuit according to the embodiment.
  • FIG. 33 is a diagram illustrating a configuration of a transistor according to an embodiment.
  • FIG. 34 is a diagram for explaining the operation of the shift register according to the embodiment.
  • FIG. 35 is a diagram illustrating a configuration of a display module according to an embodiment.
  • FIG. 36 is a diagram illustrating a configuration of a display module according to an embodiment.
  • FIG. 37 is a diagram illustrating a configuration of a display module according to an embodiment.
  • FIG. 38 is a diagram illustrating a configuration of a display module according to an embodiment.
  • FIG. 39 is a diagram illustrating a configuration of a display module according to an embodiment.
  • FIG. 40 is a diagram illustrating a configuration of a display module according to an embodiment.
  • 41A to 41F are diagrams illustrating a configuration of an electronic device according to an embodiment.
  • a display device includes a first functional layer, a second functional layer, a first substrate, and a second substrate.
  • the first functional layer includes a first region and a second region, and the first functional layer is bent in the second region.
  • the first region is sandwiched between the second functional layer and the first substrate, the first region includes a first layer and a pixel circuit, and the pixel circuit is sandwiched between the second functional layer and the first layer.
  • the second region is adjacent to the first region, the second region includes a second layer and a first shift register, the second layer is continuous with the first layer, and the first shift register is formed on the second layer.
  • the second functional layer is sandwiched between the second substrate and the first region, the second functional layer includes a display device, and the display device is electrically connected to the pixel circuit.
  • first driving circuit to be arranged in the second region to supply a video signal to the signal line.
  • a pixel circuit and a display device can be arranged in the adjacent first region to display an image.
  • first functional layer is bent in the second region, it is possible to make the second region difficult to see when facing the first region.
  • region surrounding the first region in a frame-like shape difficult to see when facing the first region.
  • FIG. 1A is a perspective view that illustrates the configuration of a display device according to one embodiment of the present invention
  • FIG. 1B is a cross-sectional view that illustrates the configuration of a display device according to one embodiment of the present invention.
  • FIG. 2A is a front view illustrating a portion of the display device according to one embodiment of the present invention shown in FIG. 1B.
  • FIG. 2B is a cross-sectional view taken along the line Q1-Q2 shown in FIG. 2A
  • FIG. 2C is a cross-sectional view taken along the line Q3-Q4 shown in FIG. 2A.
  • Figure 3 is a front view illustrating a portion of a display device according to one embodiment of the present invention.
  • Figure 4A is a front view illustrating a portion of the display device according to one embodiment of the present invention shown in Figure 3, and Figure 4B is a cross-sectional view taken along the cutting line P1-P2 shown in Figure 4A.
  • Figure 5 is a diagram explaining in detail a portion of the configuration shown in Figure 4B. Note that hatching patterns are omitted for some of the configuration to avoid cluttering the diagram.
  • Figure 6A is a perspective view that illustrates the configuration of a display device according to one embodiment of the present invention
  • Figure 6B is a cross-sectional view taken along the line Q1-Q2 shown in Figure 6A.
  • a display device includes a functional layer 510, a functional layer 520, a substrate SUB1, and a substrate SUB2 (see FIGS. 1A and 1B).
  • the functional layer 510 includes a region 510_1 and a region 510_2, and the functional layer 510 is bent in the region 510_2 (see FIG. 1B).
  • the region 510_1 is sandwiched between the functional layer 520 and the substrate SUB1, and the region 510_1 includes a layer 511_1 and a pixel circuit 530.
  • the pixel circuit 530 is sandwiched between the functional layer 520 and the layer 511_1.
  • the functional layer 510 includes a transistor 200.
  • Region 510_2 is adjacent to region 510_1, and region 510_2 includes layer 511_2 and shift register SR1 (see Figures 2A and 2B). For ease of explanation, region 510_2 is deformed from a bent state to an extended state to show functional layer 510 in Figures 2A and 2B.
  • Layer 511_2 is continuous with layer 511_1, and shift register SR1 is formed on layer 511_2.
  • the layer 511 includes a layer 511_1 and a layer 511_2.
  • the layer 511 can be formed using an inorganic material, an organic material, or a stack of an inorganic material and an organic material.
  • a material containing oxygen and silicon, a material containing nitrogen and silicon, or a material containing oxygen and tungsten can be used for layer 511.
  • epoxy resin acrylic resin, silicone resin, phenol resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, EVA (ethylene vinyl acetate) resin, etc.
  • PVC polyvinyl chloride
  • PVB polyvinyl butyral
  • EVA ethylene vinyl acetate
  • the above configuration allows the layer 511_2 to be bent.
  • the pixel circuit 530 and the shift register SR1 can be formed on the layer 511.
  • deterioration and alteration of the layer 511 due to heat applied during the manufacturing process can be suppressed.
  • functional layers 510 and 520 can be produced using the fabrication process substrate on which layer 511 is formed, and after bonding to substrate SUB2, the fabrication process substrate can be peeled off from functional layer 510.
  • a laser can be irradiated toward functional layer 510 through the fabrication process substrate to peel off the fabrication process substrate from functional layer 510. This allows part of the fabrication process to proceed with the workpiece in a rigid state.
  • the fabrication process substrate can be made flexible.
  • Configuration example 1 of functional layer 520 The functional layer 520 is sandwiched between the substrate SUB2 and the region 510_1 (see FIG. 1B).
  • the functional layer 520 includes a display device 550, which is electrically connected to the pixel circuit 530.
  • a liquid crystal device 550LC can be used as the display device 550 (see FIG. 3).
  • various display devices not limited to liquid crystal devices, can be used in the display device of one embodiment of the present invention.
  • a light-emitting device can be used as the display device 550.
  • the liquid crystal device 550LC includes an electrode 551LC, an electrode 552LC, and a layer 553LC containing liquid crystal.
  • the electrode 552LC is arranged so that an electric field that controls the orientation of the liquid crystal material is formed between the electrode 551LC (see FIG. 4B).
  • the electrode 551LC is a pixel electrode.
  • the electrode 551LC may be shaped like a comb, and the electrode 552LC may be arranged so that a transverse electric field or a fringe electric field is formed between the electrode 551LC and the electrode 552LC (see FIG. 3). Note that the electrode 551LC is sandwiched between the layer 553LC containing liquid crystal and the electrode 552LC.
  • the electrode 551LC can be arranged so that a vertical electric field is formed between the electrode 552LC. Note that the layer 553LC containing liquid crystal is sandwiched between the electrode 551LC and the electrode 552LC.
  • the liquid crystal device 550LC also includes an alignment film AF1 and an alignment film AF2 (see FIG. 4B).
  • the alignment film AF1 is sandwiched between a layer 553LC containing liquid crystal and an electrode 551LC, and the alignment film AF2 sandwiches the layer 553LC containing liquid crystal between itself and the alignment film AF1.
  • a transmissive liquid crystal device that employs a vertical alignment (VA) mode can be used for the liquid crystal device 550LC.
  • VA vertical alignment
  • MVA Multi-Domain Vertical Alignment
  • PVA Plasma Vertical Alignment
  • ASV Advanced Super View
  • the operating mode is not limited to the VA mode, and liquid crystal devices operating in various modes can be used for the liquid crystal device 550LC.
  • liquid crystal devices operating in various modes can be used for the liquid crystal device 550LC.
  • FFS mode FFS mode
  • TN Transmission Nematic
  • IPS mode IPS mode
  • ASM Analy Symmetric Aligned Micro-cell
  • OCB Opticaly Compensated Birefringence
  • FLC Fluorroelectric Liquid Crystal
  • AFLC AntiFerroelectric Liquid Crystal
  • ECB Electrodefringence
  • guest host mode etc.
  • the liquid crystal device controls the transmission or non-transmission of light by utilizing the optical modulation action of polarized light and liquid crystal.
  • the optical modulation action of the liquid crystal is controlled by the electric field (including the horizontal electric field, the vertical electric field, or the oblique electric field) applied to the liquid crystal.
  • thermotropic liquid crystals low molecular weight liquid crystals
  • polymer liquid crystals polymer dispersed liquid crystals
  • PNLC polymer network liquid crystals
  • ferroelectric liquid crystals antiferroelectric liquid crystals, etc.
  • liquid crystal materials can exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, etc. depending on the conditions.
  • positive liquid crystals or negative liquid crystals can be used as the liquid crystal material, and the most suitable liquid crystal material can be used depending on the mode or design to be applied.
  • the functional layer 520 includes a light-shielding film BM, a colored layer CF, a layer 522, and a layer KB (see FIG. 4B).
  • the light-shielding film BM includes an opening, and the colored layer CF overlaps the opening of the light-shielding film BM.
  • the layer 522 is sandwiched between the colored layer CF and a layer 553LC including liquid crystal, and has insulating properties.
  • the layer KB is sandwiched between the opening 518_4 and the light-shielding film BM, and the layer KB controls the thickness of the layer 553LC including liquid crystal.
  • the functional layer 520 also includes a layer 521.
  • the layer 521 is sandwiched between the layer 553LC including liquid crystal and the functional layer 510.
  • the functional layer 510 is bent in the region 510_2, the region 510_2 can be made difficult to see when facing the region 510_1. Also, when facing the region 510_1, the region surrounding the region 510_1 in a frame-like shape can be made difficult to see. As a result, a novel display device with excellent convenience, usefulness, and reliability can be provided.
  • the functional layer 510 includes a layer 516, a layer 518, a spacer 210, and a transistor 200 (see FIG. 4B).
  • the layer 518 is sandwiched between the functional layer 520 and the spacer 210.
  • the layer 518 has an opening 518_4, and the layer 518 has insulating properties.
  • the layer 516 is sandwiched between the layer 518 and the spacer 210, and the layer 516 overlaps with the transistor 200.
  • an insulating inorganic material, an insulating organic material, or an insulating composite material containing an inorganic material and an organic material can be used for layer 518.
  • an inorganic oxide, an inorganic nitride, an inorganic oxynitride, or the like can be used for the layer 518.
  • a laminate material in which a plurality of materials selected from the inorganic oxide, inorganic nitride, inorganic oxynitride, or the like are laminated can be used for the layer 518.
  • silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like can be used for the layer 518.
  • a silicon nitride film is a dense film and has an excellent function of suppressing the diffusion of impurities.
  • a film that has an excellent function of suppressing the diffusion of impurities can be suitably used for the layer 516. This makes it possible to suppress the diffusion of impurities from the outside to the inside of the transistor 200, which impairs the operating characteristics of the transistor 200.
  • polyester, polyolefin, polyamide, polyimide, polycarbonate, polysiloxane, acrylic resin, or the like can be used for the layer 518.
  • it may be formed using a material having photosensitivity.
  • polyimide is superior to other organic materials in properties such as thermal stability, insulation, toughness, low dielectric constant, low coefficient of thermal expansion, and chemical resistance.
  • layer 518 can flatten steps resulting from the structure of the base.
  • the spacer 210 includes a surface 210_1, a surface 210_2, a surface 210_3, and an opening 210_4 (see FIG. 5).
  • the surfaces 210_1, 210_2, and 210_3 are insulating.
  • Surface 210_2 faces surface 210_1, and surface 210_2 is located closer to layer 518 than surface 210_1.
  • a stacked structure of layers 210A, 210B, and 210C can be used for spacer 210.
  • layer 210C is located between layers 210A and 210B, for example, layer 210A constitutes surface 210_1 and layer 210B constitutes surface 210_2.
  • Surface 210_3 connects surface 210_1 and surface 210_2, and surface 210_3 is located on the side of opening 210_4. Note that the surfaces and openings are not limited to the area indicated by the dashed lines in the drawing.
  • surface 210_3 is composed of the side of the opening of layer 210A, the side of the opening of layer 210B, and the side of the opening of layer 210C.
  • the transistor 200 includes an electrode 212A, an electrode 212B, an electrode 204, a semiconducting layer 208, and an insulating layer 206 (see Figures 4B and 5).
  • Electrode 212A has an area that contacts surface 210_1 and an area that overlaps opening 210_4.
  • Electrode 212B has a region in contact with surface 210_2, opening 212B_4, and surface 212B_3.
  • Surface 212B_3 is located on the side of opening 212B_4, and opening 212B_4 overlaps with opening 210_4.
  • the electrode 204 has an area facing the surface 210_3.
  • the electrode 204 functions as a gate electrode of the transistor 200.
  • the insulating layer 206 has an area sandwiched between the surface 210_3 and the electrode 204.
  • the insulating layer 206 functions as a gate insulating film for the transistor 200.
  • the semiconductor layer 208 has a region sandwiched between the surface 210_3 and the insulating layer 206.
  • the channel of the transistor 200 is formed in the semiconductor layer 208.
  • the area occupied by the transistor can be reduced. Also, the channel length of the transistor can be shortened. Also, the on-current of the transistor can be increased. Also, the variation in the operating characteristics of the transistor can be reduced. Also, the area occupied by the pixel circuit 530 can be reduced. Also, the resolution of the display device can be increased. As a result, a novel display device that is excellent in convenience, usefulness, and reliability can be provided.
  • Inorganic conductive materials, organic conductive materials, metals, conductive oxides, etc. can be used for the conductive layer 519A.
  • a metal element selected from aluminum, gold, platinum, silver, copper, chromium, tantalum, titanium, molybdenum, tungsten, nickel, iron, cobalt, palladium, or manganese can be used for the conductive layer 519A.
  • an alloy containing the above-mentioned metal element can be used for the conductive layer 519A.
  • the conductive layer 519A can be made up of a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is laminated on top of an aluminum film, and a titanium film is further formed on top of that, etc.
  • a conductive oxide containing indium can be used for the conductive layer 519A.
  • indium oxide, indium oxide-tin oxide (abbreviation: ITO), indium oxide-tin oxide containing silicon or silicon oxide (abbreviation: ITSO), indium oxide-zinc oxide, indium oxide containing tungsten oxide and zinc oxide (abbreviation: IWZO), etc. can be used.
  • a conductive oxide containing zinc can be used for the conductive layer 519A.
  • zinc oxide, zinc oxide doped with gallium, zinc oxide doped with aluminum, etc. can be used.
  • a glass substrate can be used for the substrate SUB1 and the substrate SUB2.
  • non-alkali glass can be used for the substrate SUB1 and the substrate SUB2.
  • the display device includes a driver circuit SD.
  • the driver circuit SD includes a shift register SR1 (see FIG. 2A).
  • the functional layer 510 includes a signal line S.
  • the signal line S electrically connects the driver circuit SD and the pixel circuit 530, and transmits a video signal.
  • the function of the driver circuit SD that can be used in the display device of one embodiment of the present invention will be described in detail in Embodiment 2.
  • details of a configuration that can be used for the shift register SR1 will be described in Embodiment 4.
  • a driving circuit SD can be arranged in region 510_2 to supply a video signal to the signal line S.
  • a pixel circuit 530 and a display device 550 can be arranged in the adjacent region 510_1 to display an image.
  • region 510_2 can be made difficult to see when facing region 510_1.
  • the region surrounding region 510_1 in a frame-like shape can be made difficult to see.
  • a novel display device with excellent convenience, usefulness, and reliability can be provided.
  • the signal line S is electrically connected to the electrode 212A (see FIG. 4B).
  • a wiring for supplying a signal to the liquid crystal device 550LC can be used as the signal line S.
  • the portion of the conductive layer that overlaps with the opening 210_4 of the spacer 210 is referred to as the electrode 212A.
  • the portion of the conductive layer that overlaps with the flat region of the spacer 210 is referred to as the signal line S.
  • the signal line S has light-shielding properties.
  • the same material that can be used for the conductive layer 519A can be used for the signal line S.
  • metals or alloys can be preferably used.
  • the signal line S overlaps the opening 518_4.
  • the opening 518_4 overlaps the electrode 212B and the signal line S.
  • the step formed on the opening 518_4 can be overlapped with the signal line S.
  • a flat region can be formed in the region that does not overlap with the signal line S.
  • An electrode of the display device 550 can be formed in the flat region.
  • a flat region can be formed on the electrode.
  • a layer containing liquid crystal for example, can be formed on the flat region of the electrode.
  • the signal line S can be disposed between the layer containing liquid crystal and the backlight. The signal line S can be used to block light from the backlight so that the light from the backlight does not reach the region in which the alignment is disturbed due to the step on the opening 518_4 and is formed in the layer containing liquid crystal.
  • the aperture ratio of the liquid crystal device can be increased.
  • the luminance of the display device can be increased. Power consumption can be suppressed. As a result, a novel display device with excellent convenience, usefulness, and reliability can be provided.
  • the display device of one embodiment of the present invention includes a driver circuit GD.
  • the driver circuit GD includes a shift register SR2 (see FIG. 2A). Note that functions of the driver circuit GD that can be used in the display device of one embodiment of the present invention will be described in detail in Embodiment 2. In addition, details of a structure that can be used for the shift register SR2 will be described in Embodiment 4.
  • the functional layer 510 includes a region 510_3 and a scanning line G.
  • the functional layer 510 is bent in the region 510_3.
  • a notch is provided between region 510_2 and region 510_3.
  • Various shapes can be used for the contour of the notch, but for example, as shown in FIG. 2A using the dashed line Q5-Q6, a contour drawn with a gentle curve can be used to prevent stress concentration due to bending.
  • a contour drawn with a curve with a radius of curvature of 0.1 mm or more and 10 mm or less is preferable.
  • Region 510_3 is adjacent to region 510_1, and region 510_3 includes layer 511_3 and shift register SR2 (see Figures 2A and 2C).
  • Layer 511_3 is continuous with layer 511_1, and shift register SR2 is formed on layer 511_3.
  • the scanning line G electrically connects the driving circuit GD and the pixel circuit 530, and the scanning line G transmits a selection signal.
  • a driving circuit GD to be arranged in region 510_3 to supply a selection signal to the scanning line G.
  • a pixel circuit 530 and a display device 550 can be arranged in the adjacent region 510_1 to display an image.
  • the functional layer 510 is bent in region 510_3, it is possible to make region 510_3 difficult to see when facing region 510_1.
  • a display device includes an electrode RX and a driver circuit TD.
  • the functional layer 520 is located between the electrode RX and the functional layer 510. In other words, the electrode RX sandwiches the functional layer 520 between itself and the functional layer 510 (see FIG. 4B).
  • the driver circuit TD includes a shift register SR3 (see FIG. 2A). Note that the function of the driver circuit TD that can be used in the display device of one embodiment of the present invention will be described in detail in Embodiment 3. In addition, the details of a configuration that can be used for the shift register SR3 will be described in Embodiment 4.
  • the functional layer 510 includes a region 510_4 and an electrode TX.
  • the functional layer 510 is bent in the region 510_4.
  • Region 510_4 is adjacent to region 510_1, and region 510_4 includes layer 511_4 and shift register SR3 (see Figures 2A and 2C).
  • Layer 511_4 is continuous with layer 511_1, and shift register SR3 is formed on layer 511_4.
  • a capacitance is formed between the electrodes TX and RX (see FIG. 6B).
  • the electrode TX forms a capacitance with the electrode RX.
  • the electrodes TX and RX also form a sensor element.
  • the electrode TX can be used as a common electrode for the liquid crystal device.
  • the electrode TX can be used as the electrode 552LC (see FIG. 4B).
  • the electrode TX is electrically connected to the drive circuit TD, and the electrode TX transmits a pulse signal.
  • a driving circuit TD can be arranged in the region 510_4 to supply a pulse signal to the electrode TX.
  • an electrode RX can be arranged on the adjacent region 510_1 to detect a change in the projection capacitance occurring between the electrode TX.
  • the position of the finger of a user of the display device approaching the region 510_1 can be detected.
  • the region 510_4 can be made difficult to see when facing the region 510_1.
  • the region surrounding the region 510_1 in a frame-like shape can be made difficult to see.
  • the display device shown in FIG. 7A includes a pixel portion 4502, a driver circuit portion 4504, a protective circuit 4506, and a terminal portion 4507. Note that the protective circuit 4506 may not be provided.
  • the pixel portion 4502 has a plurality of pixel circuits 4501 arranged in X rows and Y columns (X and Y are each independently a natural number of 2 or more). Each pixel circuit 4501 has a circuit that drives a display element.
  • the driver circuit section 4504 has driver circuits such as a gate driver 4504a and a source driver 4504b.
  • the gate driver 4504a outputs scanning signals to the gate lines GL_1 to GL_X.
  • the gate driver 4504a can have at least a shift register. Note that the gate driver 4504a can be used for, for example, the driver circuit GD of the display device described in Embodiment 1.
  • the source driver 4504b supplies data signals to the data lines DL_1 to DL_Y.
  • the source driver 4504b can be configured using a shift register, a digital-to-analog conversion circuit, a latch circuit, and the like. Note that the source driver 4504b can be used for the driver circuit SD described in Embodiment 1, for example.
  • the terminal portion 4507 is a portion provided with terminals for inputting power, control signals, image signals, etc. from an external circuit to the display device.
  • the protective circuit 4506 is a circuit that connects a wiring to which it is connected to another wiring when a potential outside a certain range is applied to the wiring.
  • the protective circuit 4506 shown in FIG. 7A is connected to various wirings such as a gate line and a data line. Note that in FIG. 7A, the protective circuit 4506 is shown with a hatched pattern to distinguish the protective circuit 4506 from the pixel circuit 4501.
  • the gate driver 4504a and the source driver 4504b may be provided on the same substrate as the pixel portion 4502, or an IC on which a gate driver circuit or a source driver circuit is separately formed may be mounted on the substrate on which the pixel portion 4502 is provided by using a COG (chip on glass) method or the like.
  • an FPC flexible printed circuit
  • ACF anisotropic conductive film
  • the pixel portion 4502 and the gate driver 4504a are preferably manufactured over the same substrate and through the same process.
  • Figure 7B shows an example of a pixel circuit configuration that can be applied to pixel circuit 4501.
  • the pixel circuit 4501 shown in FIG. 7B includes a liquid crystal device 4570, a transistor 4550, and a capacitor 4560.
  • a data line DL_n, a gate line GL_m, a potential supply line, and the like are connected to the pixel circuit 4501.
  • the data line DL_n can be used as the signal line S described in Embodiment 1, for example.
  • the gate line GL_m can be used as the scanning line G. Details of a structure that can be used for the transistor 4550 will be described in Embodiment 4.
  • the potential of one of the pair of electrodes of the liquid crystal device 4570 is set appropriately according to the specifications of the pixel circuit 4501.
  • the orientation state of the liquid crystal device 4570 is set by the data written thereto. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal device 4570 of each of the multiple pixel circuits 4501. Also, a different potential may be applied to one of the pair of electrodes of the liquid crystal device 4570 of the pixel circuit 4501 of each row.
  • the pixel circuit 4501 shown in FIG. 7C includes a transistor 4552, a transistor 4554, a capacitor 4562, and a light-emitting element 4572.
  • the pixel circuit 4501 is connected to a data line DL_n, a gate line GL_m, a potential supply line VL_a, a potential supply line VL_b, and the like.
  • a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other.
  • the current flowing through the light-emitting element 4572 is controlled according to the potential applied to the gate of the transistor 4554, thereby controlling the light emission brightness from the light-emitting element 4572.
  • FIG. 8A shows a circuit diagram of a pixel circuit 4400.
  • the pixel circuit 4400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 4401.
  • the pixel circuit 4400 is connected to wirings S1, S2, G1, and G2. Details of the structure that can be used for the transistor M1 and the transistor M2 are described in embodiment 4.
  • the gate of the transistor M1 is connected to the wiring G1, one of the source and drain is connected to the wiring S1, and the other is connected to one electrode of the capacitor C1.
  • the gate of the transistor M2 is connected to the wiring G2, one of the source and drain is connected to the wiring S2, and the other is connected to the other electrode of the capacitor C1 and the circuit 4401.
  • the circuit 4401 is a circuit including at least one display element.
  • the display element has a liquid crystal device.
  • various elements can be used as the display element, and typically, light-emitting elements such as organic EL elements and LED elements, or MEMS (Micro Electro Mechanical Systems) elements can be applied.
  • the node connecting transistor M1 and capacitance C1 is node N1
  • the node connecting transistor M2 and circuit 4401 is node N2.
  • the pixel circuit 4400 can maintain the potential of node N1 by turning off transistor M1. Also, the potential of node N2 can be maintained by turning off transistor M2. Also, by writing a predetermined potential to node N1 via transistor M1 while transistor M2 is turned off, the potential of node N2 can be changed according to the change in the potential of node N1 due to capacitive coupling via capacitor C1.
  • a transistor using an oxide semiconductor can be used as one or both of the transistors M1 and M2. Therefore, the potential of the node N1 or the node N2 can be held for a long period of time due to an extremely low off-current. Note that when the period during which the potential of each node is held is short (specifically, when the frame frequency is 30 Hz or more), a transistor using a semiconductor such as silicon may be used.
  • Fig. 8B is a timing chart related to the operation of the pixel circuit 4400. Note that, for ease of explanation, the influence of various resistances such as wiring resistance, parasitic capacitance, and threshold voltage of a transistor is not taken into consideration here.
  • Period T1 is a period in which a potential is written to node N2
  • period T2 is a period in which a potential is written to node N1.
  • Period T1 In the period T1, a potential that turns on the transistor is applied to both the wiring G1 and the wiring G2. A fixed potential Vref is supplied to the wiring S1, and a first data potential Vw is supplied to the wiring S2.
  • the node N1 is supplied with a potential Vref from the wiring S1 through the transistor M1.
  • the node N2 is supplied with a first data potential Vw from the wiring S2 through the transistor M2. Therefore, the potential difference Vw - Vref is held in the capacitor C1.
  • Period T2 In the next period T2, a potential that turns on the transistor M1 is applied to the wiring G1, and a potential that turns off the transistor M2 is applied to the wiring G2.
  • a second data potential Vdata is supplied to the wiring S1.
  • a predetermined constant potential is applied to the wiring S2, or the wiring S2 may be in a floating state.
  • the second data potential Vdata is applied to the node N1 from the wiring S1 through the transistor M1.
  • the potential of the node N2 changes by a potential dV in response to the second data potential Vdata due to capacitive coupling by the capacitor C1. That is, a potential obtained by adding the first data potential Vw and the potential dV is input to the circuit 4401.
  • the potential dV is shown to be a positive value in FIG. 8B, it may be a negative value. That is, the second data potential Vdata may be lower than the potential Vref .
  • the potential dV is roughly determined by the capacitance value of the capacitor C1 and the capacitance value of the circuit 4401.
  • the potential dV becomes close to the second data potential Vdata .
  • the pixel circuit 4400 can combine two types of data signals to generate a potential to be supplied to the circuit 4401 including a display element, making it possible to perform gradation correction within the pixel circuit 4400.
  • the pixel circuit 4400 can also generate a potential that exceeds the maximum potential that can be supplied by a source driver connected to the wiring S1 and the wiring S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. When a liquid crystal device is used, overdrive driving or the like can be realized.
  • HDR high dynamic range
  • Example using liquid crystal device 8C includes a circuit 4401LC.
  • the circuit 4401LC includes a liquid crystal device LC and a capacitor C2.
  • the liquid crystal device LC has one electrode connected to the node N2 and one electrode of the capacitor C2, and the other electrode connected to a wiring to which a potential V com2 is applied.
  • the capacitor C2 has the other electrode connected to a wiring to which a potential V com1 is applied.
  • Capacitor C2 functions as a storage capacitor. Note that capacitor C2 can be omitted if not required.
  • the pixel circuit 4400LC can supply a high voltage to the liquid crystal device LC, so that, for example, high-speed display can be achieved by overdriving, and liquid crystal materials with high driving voltages can be used.
  • the gradation can be corrected according to the operating temperature, the deterioration state of the liquid crystal device LC, etc.
  • Example using light-emitting element 8D includes a circuit 4401EL.
  • the circuit 4401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.
  • the transistor M3 has a gate connected to the node N2 and one electrode of the capacitor C2, a source and a drain connected to a wiring to which a potential VH is applied, and the other connected to one electrode of the light-emitting element EL.
  • the other electrode of the capacitor C2 is connected to a wiring to which a potential Vcom is applied.
  • the other electrode of the light-emitting element EL is connected to a wiring to which a potential VL is applied.
  • Transistor M3 has the function of controlling the current supplied to the light-emitting element EL.
  • Capacitor C2 functions as a storage capacitor. Capacitor C2 can be omitted if not required.
  • the anode side of the light-emitting element EL is connected to the transistor M3, but the cathode side of the light-emitting element EL may be connected to the transistor M3.
  • the values of the potentials VH and VL can be changed as appropriate.
  • the pixel circuit 4400EL can achieve, for example, HDR display by applying a high potential to the gate of the transistor M3 to pass a large current through the light-emitting element EL.
  • a correction signal to the wiring S1 or wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3, the light-emitting element EL, and the like.
  • circuit is not limited to the examples shown in Figures 8C and 8D, and may include additional transistors, capacitance, etc.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • Figure 9 is a block diagram of the touch panel module 6500.
  • FIGS 10A to 10C are schematic diagrams of a touch panel module 6500 incorporating an IC 6520.
  • the touch panel module 6500 includes a touch panel 6510 and an IC 6520 (see FIG. 9).
  • the touch panel 6510 includes a display portion 6511 , an input portion 6512 , a scanning line driver circuit 6513 , a sensor driver circuit 6503 , and a detection circuit 6504 .
  • the display portion 6511 has a plurality of pixels, a plurality of signal lines, and a plurality of scanning lines, and has a function of displaying an image.
  • the display unit 6511 preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferable.
  • the pixel density (resolution) of the pixels provided in the display unit 6511 is preferably 300 ppi or more, preferably 500 ppi or more, more preferably 800 ppi or more, more preferably 1000 ppi or more, and more preferably 1200 ppi or more.
  • the display unit 6511 having such a high resolution and high resolution makes it possible to enhance the sense of realism and depth.
  • the input portion 6512 has a plurality of sensor elements that detect contact or proximity of a detected object to the touch panel 6510, and functions as a touch sensor.
  • the scanning line driver circuit 6513 has a function of outputting a scanning signal to the scanning line of the display portion 6511.
  • the display portion 6511 and the input portion 6512 are separately illustrated as the configuration of the touch panel 6510 here, but a so-called in-cell touch panel having both a function of displaying an image and a function as a touch sensor may be used. Note that, for example, the region 510_1 of the display device described in embodiment 1 can be used for the display portion 6511.
  • a capacitance type can be applied as a touch sensor type that can be used as the input unit 6512.
  • capacitance types include a surface capacitance type and a projected capacitance type.
  • projected capacitance types include a self-capacitance type and a mutual capacitance type. The mutual capacitance type is preferable because it enables simultaneous multi-point detection.
  • various types of sensors that can detect the approach, contact, or pressure of a detectable object such as a finger or stylus can also be applied to the input unit 6512.
  • various types of sensors can be used, such as a resistive film type, a surface acoustic wave type, an infrared type, and an optical type.
  • Typical in-cell touch panels include hybrid in-cell and full in-cell.
  • the hybrid in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on both the substrate supporting the display element and the opposing substrate, or on the opposing substrate.
  • the full in-cell type refers to a configuration in which electrodes constituting a touch sensor are provided on the substrate supporting the display element.
  • a full in-cell touch panel is preferable because it simplifies the configuration of the opposing substrate.
  • a full in-cell type is preferable because it simplifies the manufacturing process and reduces manufacturing costs if the electrodes constituting the display element also serve as the electrodes constituting the touch sensor.
  • the sensor driver circuit 6503 has a function of outputting a signal for driving a sensor element included in the input portion 6512.
  • a combination of a shift register circuit and a buffer circuit can be used as the sensor driver circuit 6503.
  • the sensor driver circuit 6503 can be used for the driver circuit TD described in Embodiment 1, for example.
  • the detection circuit 6504 has a function of amplifying an output signal from the sensor element of the input portion 6512 and outputting the amplified signal to the AD conversion circuit 6507 .
  • the IC 6520 includes a circuit unit 6501, a signal line driver circuit 6502, and an AD conversion circuit 6507.
  • the circuit unit 6501 includes a timing controller 6505, an image processing circuit 6506, and the like.
  • the signal line driver circuit 6502 has a function of outputting an analog image signal (also called a video signal) to a signal line of the display portion 6511.
  • the signal line driver circuit 6502 can have a combination of a shift register, a digital-analog converter (DAC), a latch circuit, a buffer circuit, and the like.
  • the touch panel 6510 may also have a demultiplexer circuit connected to the signal line.
  • the AD conversion circuit 6507 has a function of converting an analog signal input from the detection circuit 6504 into a digital signal and outputting the digital signal to the circuit unit 6501.
  • the AD conversion circuit 6507 can have a configuration including an amplifier circuit in addition to an analog-digital converter (ADC).
  • ADC analog-digital converter
  • the image processing circuit 6506 of the circuit unit 6501 has a function of generating and outputting a signal that drives the display portion 6511 of the touch panel 6510, a function of generating and outputting a signal that drives the input portion 6512, and a function of analyzing the signal output from the input portion 6512 and outputting it to the CPU 6540.
  • the image processing circuit 6506 has a function of generating a video signal according to an instruction from the CPU 6540.
  • the image processing circuit 6506 also has a function of performing signal processing on the video signal in accordance with the specifications of the display unit 6511, converting it into an analog video signal, and supplying it to the signal line driving circuit 6502.
  • the image processing circuit 6506 also has a function of generating a driving signal to be output to the sensor driving circuit 6503 according to an instruction from the CPU 6540.
  • the image processing circuit 6506 also has a function of analyzing a signal input from the detection circuit 6504 via the AD conversion circuit 6507, and outputting it to the CPU 6540 as position information.
  • the timing controller 6505 has a function of generating and outputting signals (signals such as a clock signal and a start pulse signal) to be output to the scanning line driver circuit 6513 and the sensor driver circuit 6503 based on a synchronization signal included in the video signal processed by the image processing circuit 6506.
  • the timing controller 6505 may also have a function of generating and outputting a signal that specifies the timing at which the detection circuit 6504 outputs a signal.
  • the timing controller 6505 outputs a signal that is synchronized with the signal to be output to the scanning line driver circuit 6513 and the signal to be output to the sensor driver circuit 6503.
  • the touch panel 6510 can be driven by dividing one frame period into a period in which pixel data is rewritten and a period in which sensing is performed.
  • the detection sensitivity and detection accuracy can be improved.
  • the image processing circuit 6506 can be configured to have, for example, a processor.
  • a microprocessor such as a DSP (Digital Signal Processor) or a GPU (Graphics Processing Unit) can be used.
  • These microprocessors may also be configured to be realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).
  • the image processing circuit 6506 performs various data processing, program control, etc. by interpreting and executing commands from various programs using the processor.
  • the programs that can be executed by the processor may be stored in a memory area of the processor or in a separately provided storage device.
  • a transistor which uses an oxide semiconductor in a channel formation region and has extremely low off-state current for at least one of the display portion 6511, the input portion 6512, the scanning line driver circuit 6513, the sensor driver circuit 6503, and the detection circuit 6504 of the touch panel 6510.
  • the transistor Since the off-state current of the transistor is extremely low, the transistor can be used as a switch for storing charge (data) flowing into a capacitor that functions as a memory element, thereby ensuring a long data storage period.
  • the transistor may also be applied to the circuit unit 6501, the signal line driver circuit 6502, the AD conversion circuit 6507, the CPU 6540 provided externally, and the like, of the IC 6520.
  • the image processing circuit 6506 is operated only when necessary, and the information of the immediately preceding process is saved in the memory element in other cases, thereby enabling so-called normally-off computing, in which the power supply to the image processing circuit 6506 is cut off when not in use, and the power consumption of the touch panel module 6500 and the electronic device in which it is implemented can be reduced.
  • the circuit unit 6501 has a configuration including a timing controller 6505 and an image processing circuit 6506, but the image processing circuit 6506 itself or a circuit having some of the functions of the image processing circuit 6506 may be provided outside the IC 6520.
  • the CPU 6540 may assume the functions of the image processing circuit 6506 or some of the functions.
  • the circuit unit 6501 may have a configuration including a signal line driver circuit 6502, a timing controller 6505, and an AD conversion circuit 6507.
  • the circuit unit 6501 may not be included in the IC 6520.
  • the IC 6520 may have a signal line driver circuit 6502 and an AD conversion circuit 6507.
  • an IC including the circuit unit 6501 may be provided separately, and multiple ICs 6520 that do not have the circuit unit 6501 may be arranged.
  • the IC 6520 may be arranged in combination with an IC that has only the signal line driver circuit 6502.
  • ⁇ Configuration Example 3 of Touch Panel Module> 10A includes a substrate 6531, a counter substrate 6532, a plurality of FPCs 6533, an IC 6520, an IC 6530, and the like.
  • a display portion 6511, an input portion 6512, a scanning line driver circuit 6513, a sensor driver circuit 6503, and a detection circuit 6504 are provided between the substrate 6531 and the counter substrate 6532.
  • the IC 6520 and the IC 6530 are mounted on the substrate 6531 by a mounting method such as a COG (chip on glass) method.
  • IC6530 is an IC having only the signal line driver circuit 6502 or the signal line driver circuit 6502 and the circuit unit 6501 in the above-mentioned IC6520. Signals are supplied to the IC6520 and IC6530 from the outside via the FPC6533. Also, signals can be output from the IC6520 or IC6530 to the outside via the FPC6533.
  • Figure 10A shows an example of a configuration in which two scanning line driver circuits 6513 are provided to sandwich the display portion 6511. Also, a configuration having an IC 6530 in addition to an IC 6520 is shown. This type of configuration can be suitably used when the display portion 6511 has extremely high resolution.
  • ⁇ Configuration Example 4 of Touch Panel Module> 10B shows an example in which one IC 6520 and one FPC 6533 are mounted. In this way, it is preferable to reduce the number of parts by consolidating the functions into one IC 6520. Also, in FIG. 10B, an example in which the scanning line driver circuit 6513 is disposed along one of two short sides of the display portion 6511 that is closer to the FPC 6533 is shown.
  • a configuration in which the FPC 6533, IC 6520 (and IC 6530), etc. are arranged on the short side of the display section 6511 allows for a narrow frame, and therefore can be suitably used in electronic devices such as smartphones, mobile phones, and tablet terminals.
  • ⁇ Configuration Example 5 of Touch Panel Module> 10C shows an example of a configuration having a PCB (Printed Circuit Board) 6534 on which an image processing circuit 6506 and the like are mounted.
  • An IC 6520 and an IC 6530 on a substrate 6531 are electrically connected to the PCB 6534 by an FPC 6533.
  • a configuration not having the image processing circuit 6506 described above can be applied to the IC 6520.
  • PCB6534 as shown in FIG. 10C can be suitably used in, for example, television devices, monitor devices, tablet terminals, or notebook personal computers.
  • IC6520 and IC6530 may be mounted on FPC6533 instead of substrate 6531.
  • IC6520 and IC6530 can be mounted on FPC6533 by a mounting method such as COF or TAB.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • n is an integer equal to or greater than 1 signal output circuits 110.
  • the first-stage (first) signal output circuit 110 may be referred to as signal output circuit 110[1]
  • the n-th stage (n-th) signal output circuit 110 may be referred to as signal output circuit 110[n].
  • the shift register 100 also has two signal output circuits 110 (signal output circuit 110[n+1] and signal output circuit 110[n+2]) which are dummy circuits.
  • the terminals and input/output signals of the signal output circuit 110 may be described in the same manner as above.
  • the signal OUT of the signal output circuit 110[i] may be described as the signal OUT[i].
  • the shift register 100 also has wirings 101 to 104 to which four signals CLK (signals CLK_1 to CLK_4) that are clock signals are supplied, and wirings 105 to 108 to which four signals PWC (signals PWC_1 to PWC_4) are supplied.
  • Signal CLK_1 is supplied to wiring 101
  • signal CLK_2 is supplied to wiring 102
  • signal CLK_3 is supplied to wiring 103
  • signal CLK_4 is supplied to wiring 104.
  • Signal PWC_1 is supplied to wiring 105
  • signal PWC_2 is supplied to wiring 106
  • signal PWC_3 is supplied to wiring 107
  • signal PWC_4 is supplied to wiring 108.
  • the signal output circuit 110 has terminals 111 to 118 (see FIG. 11B). Terminals 111, 112, and 113 are each electrically connected to different wirings among wirings 101 to 104.
  • terminal 111 is electrically connected to wiring 101
  • terminal 112 is electrically connected to wiring 102
  • terminal 113 is electrically connected to wiring 103. That is, a signal CLK_1 is supplied to terminal 111, a signal CLK_2 is supplied to terminal 112, and a signal CLK_3 is supplied to terminal 113.
  • a signal CLK_k is supplied to terminal 111[i] of signal output circuit 110[i] (see FIG. 11C).
  • k is an integer between 1 and 4, and when i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i-4 ⁇ g, where g is the quotient obtained by dividing i by 4.
  • a signal CLK_k+1 is supplied to terminal 112[i] of signal output circuit 110[i].
  • k is an integer between 1 and 4, and when k+1 is 5, k is set to 1.
  • i is 3 or less, k is equal to i, and when i is 4 or more, k is equal to i-4 ⁇ g.
  • terminal 114[i] is electrically connected to terminal 117[i+1] (not shown) of the next stage signal output circuit 110[i+1] (not shown). Therefore, terminal 117[i] is electrically connected to terminal 114[i-1] (not shown).
  • terminal 114 of signal output circuit 110[1] is electrically connected to terminal 117 of signal output circuit 110[2]. Furthermore, a start pulse SP is supplied to terminal 117 of signal output circuit 110[1].
  • the terminal 115[i] is electrically connected to the terminal 114[i+2] (not shown) of the signal output circuit 110[i+2] (not shown) two stages later.
  • the terminal 115 of the signal output circuit 110[1] is electrically connected to the terminal 114 of the signal output circuit 110[3]
  • the terminal 115 of the signal output circuit 110[2] is electrically connected to the terminal 114 of the signal output circuit 110[4]. Therefore, the terminal 115 of the signal output circuit 110[n-1] is electrically connected to the terminal 114 of the signal output circuit 110[n+1]
  • the terminal 115 of the signal output circuit 110[n] is electrically connected to the terminal 114 of the signal output circuit 110[n+2]. Note that the signal output circuit 110[n+1] and the signal output circuit 110[n+2] do not have to have the terminal 115.
  • the terminal 118[i] is electrically connected to any one of the wirings 105 to 108.
  • the terminal 118 of the signal output circuit 110[1] is electrically connected to the wiring 105
  • the terminal 118 of the signal output circuit 110[2] is electrically connected to the wiring 106.
  • the signal PWC_k is supplied to the terminal 118[i] of the signal output circuit 110[i].
  • k is an integer of 1 to 4, and when i is 4 or less, k is equal to i, and when i is 5 or more, k is equal to i-4 ⁇ g.
  • a signal OUT[i] is output from terminal 116[i].
  • a signal OUT[1] is output from terminal 116 of signal output circuit 110[1].
  • a signal OUT[n] is output from terminal 116 of n-th stage signal output circuit 110[n]. Note that “Signal OUT[i] is output from terminal 116[i]” can be read as “Signal OUT[i] is supplied to terminal 116[i]."
  • a signal SROUT[i] is supplied to terminal 114[i].
  • a signal SROUT[i] is output from terminal 114[i].
  • a signal SROUT[1] is output from terminal 114 of signal output circuit 110[1].
  • a signal SROUT[n] is output from terminal 114 of n-th stage signal output circuit 110[n]. Note that "Signal SROUT[i] is output from terminal 114[i]” can be read as “Signal SROUT[i] is supplied to terminal 114[i]."
  • the signal output circuit 110a includes transistors 10[1] to 10[11] and capacitors 20[1] to 20[3].
  • the gate of transistor 10[1] is electrically connected to terminal 117 and the gate of transistor 10[6].
  • the source of transistor 10[1] is electrically connected to the drain of transistor 10[2], and the drain of transistor 10[1] is electrically connected to wiring 131.
  • the gate of transistor 10[2] is electrically connected to one terminal of capacitor 20[1].
  • the source of transistor 10[2] is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6], and wiring 132.
  • the gate of transistor 10[3] is electrically connected to terminal 113, the drain of transistor 10[3] is electrically connected to wiring 131, and the source of transistor 10[3] is electrically connected to the drain of transistor 10[4].
  • the gate of transistor 10[4] is electrically connected to terminal 112, and the drain of transistor 10[4] is electrically connected to the source of transistor 10[3].
  • the source of transistor 10[4] is electrically connected to the gates of transistor 10[2], transistor 10[9], and transistor 10[11], and one terminal of capacitor 20[1].
  • Capacitor 20[1] has the function of suppressing the potential fluctuation of node ND[1] when node ND[1] is in a floating state and maintaining the potential of node ND[1].
  • the gate of transistor 10[5] is electrically connected to terminal 115, and the drain of transistor 10[5] is electrically connected to wiring 131.
  • the source of transistor 10[5] is electrically connected to the gate of transistor 10[2], the gate of transistor 10[9], the gate of transistor 10[11], and the drain of transistor 10[6].
  • the gate of transistor 10[7] is electrically connected to wiring 131, and one of the source and drain of transistor 10[7] is electrically connected to the source of transistor 10[1] and the drain of transistor 10[2].
  • the other of the source and drain of transistor 10[7] is electrically connected to the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10[10], and one terminal of capacitor 20[3].
  • node ND[2] the region where the source or drain of transistor 10[7], the source of transistor 10[1], and the drain of transistor 10[2] are electrically connected. Also, in this specification, the region where the source or drain of transistor 10[7], the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10[10], and one terminal of capacitor 20[3] are electrically connected is referred to as node ND[3].
  • the drain of transistor 10[8] is electrically connected to terminal 111.
  • the source of transistor 10[8] is electrically connected to the other terminal of capacitance 20[2], terminal 114, and the drain of transistor 10[9].
  • the drain of transistor 10[10] is electrically connected to terminal 118.
  • the source of transistor 10[10] is electrically connected to the other terminal of capacitance 20[3], terminal 116, and the drain of transistor 10[11].
  • the source of transistor 10[9] and the source of transistor 10[11] are electrically connected to wiring 132.
  • drain of transistor 10[1], the drain of transistor 10[3], the drain of transistor 10[5], and the gate of transistor 10[7] may each be electrically connected to different wirings.
  • the source of transistor 10[6], the source of transistor 10[9], and the source of transistor 10[11] may each be electrically connected to different wirings.
  • the drain of transistor 10[1] may be electrically connected to wiring 131[1]
  • the drain of transistor 10[3] may be electrically connected to wiring 131[2]
  • the drain of transistor 10[5] may be electrically connected to wiring 131[3]
  • the gate of transistor 10[7] may be electrically connected to wiring 131[4].
  • the source of transistor 10[6] may be electrically connected to wiring 132[1]
  • the source of transistor 10[9] may be electrically connected to wiring 132[2]
  • the source of transistor 10[11] may be electrically connected to wiring 132[3]. Note that, as shown in FIG. 14, when the capacitance value of capacitor 20[3] can be sufficiently secured, the formation of capacitor 20[2] may be omitted.
  • a signal RIN is supplied to terminal 115, a signal LIN is supplied to terminal 117, a signal SROUT is supplied to terminal 114, and a signal OUT is supplied to terminal 116.
  • a signal CLK_1 is supplied to terminal 111, a signal CLK_2 is supplied to terminal 112, a signal CLK_3 is supplied to terminal 113, and a signal PWC_1 is supplied to terminal 118.
  • the signal CLK_2 is supplied to the terminal 111
  • the signal CLK_3 is supplied to the terminal 112
  • the signal CLK_4 is supplied to the terminal 113
  • the signal PWC_2 is supplied to the terminal 118.
  • FIG. 15A is a plan view of the transistor 10.
  • FIG. 15B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 15A.
  • FIG. 15C is a perspective view showing a cutaway portion of the transistor 10.
  • FIG. 15D is an equivalent circuit diagram of the transistor 10.
  • some of the components of the transistor 10 are omitted in FIGS. 15A and 15C.
  • the insulating layer 164 and the like shown in FIG. 15B are omitted in FIGS. 15A and 15C.
  • Figures 16A and 16B are enlarged views of the transistor 10 shown in Figure 15B.
  • Figure 16C is a view of the opening 159 from the Z direction.
  • Transistor 10 has insulating layer 154 on substrate 153, and conductive layer 155 on insulating layer 154. It also has insulating layer 156 on conductive layer 155, insulating layer 157 on insulating layer 156, and insulating layer 158 on insulating layer 157. It also has conductive layer 160 on insulating layer 158.
  • an opening 159 is provided in the conductive layer 160, the insulating layer 158, the insulating layer 157, and the insulating layer 156 in a region overlapping with a part of the conductive layer 155 (see FIG. 15B and FIG. 16A).
  • the opening 159 has a semiconductor layer 161.
  • the semiconductor layer 161 has a region overlapping with the bottom of the opening 159 and a region overlapping with the side of the opening 159.
  • the semiconductor layer 161 has a region in contact with the side of the insulating layer 158, a region in contact with the side of the insulating layer 157, and a region in contact with the side of the insulating layer 156.
  • a part of the semiconductor layer 161 is electrically connected to the conductive layer 160, and another part of the semiconductor layer 161 is electrically connected to the conductive layer 155.
  • an insulating layer 162 is provided on the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and a conductive layer 163 is provided on the insulating layer 162.
  • an insulating layer 164 is provided on the insulating layer 162 and the conductive layer 163.
  • the insulating layer 162 has a region that overlaps with the side of the opening 159 through the semiconductor layer 161.
  • the conductive layer 163 is provided to cover the semiconductor layer 161. Therefore, the conductive layer 163 has a region that extends beyond the end of the semiconductor layer 161.
  • the conductive layer 163 has a region that overlaps with the side of the opening 159 through the insulating layer 162 and the semiconductor layer 161.
  • the conductive layer 155 has a region that functions as one of the source electrode and drain electrode of the transistor 10.
  • the conductive layer 160 has a region that functions as the other of the source electrode and drain electrode of the transistor 10. For example, when the conductive layer 155 functions as the drain electrode of the transistor 10, the conductive layer 160 functions as the source electrode of the transistor 10.
  • the semiconductor layer 161 has a region that functions as a semiconductor layer in which the channel of the transistor 10 is formed, the insulating layer 162 has a region that functions as a gate insulating layer, and the conductive layer 163 has a region that functions as a gate electrode.
  • the transistor 10 is provided in a region that includes the opening 159.
  • the source electrode and drain electrode of transistor 10 are arranged in the Z direction. Therefore, the source and drain of transistor 10 are each arranged at different positions in the Z direction. For example, when the top surface of substrate 153 is used as a reference, the source and drain of transistor 10 are each arranged at different distances from the top surface of substrate 153, which is the reference.
  • Such a transistor is also called a "vertical channel transistor,” “vertical channel transistor,” “vertical transistor,” or “VFET (Vertical Field Effect Transistor).”
  • Id drain current
  • the direction in which Id (drain current) flows includes a component in the Z direction (vertical direction).
  • transistor 10 which is a vertical channel transistor
  • the angle ⁇ (see FIG. 16A) between the surface on which semiconductor layer 161 is formed on conductive layer 155 and the direction in which Id flows is 5 degrees or more and 110 degrees or less, or 10 degrees or more and 90 degrees or less, or 30 degrees or more and 90 degrees or less, or 60 degrees or more and 90 degrees or less.
  • the semiconductor layer 161 has an area that contacts the side of the insulating layer 157. Therefore, Id flows along the side of the insulating layer 157. Therefore, the angle ⁇ between the formation surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows can be interpreted as the angle ⁇ between the formation surface of the semiconductor layer 161 on the conductive layer 155 and the side of the insulating layer 157.
  • Vertical channel transistors have source and drain electrodes arranged in the Z direction, which reduces the area occupied by the transistor. By using vertical channel transistors in a semiconductor device, the area occupied by the semiconductor device can be significantly reduced.
  • substrate There is no significant limit to the material used for the substrate. It can be determined in consideration of the presence or absence of light transmission and the heat resistance to a degree that can withstand heat treatment, depending on the purpose.
  • insulating substrates such as glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, and sapphire substrates can be used.
  • semiconductor substrates, flexible substrates, laminated films, base film, etc. may also be used.
  • the semiconductor substrate may be, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • the semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.
  • a large-area glass substrate such as a sixth generation (1500 mm x 1850 mm), seventh generation (1870 mm x 2200 mm), eighth generation (2200 mm x 2400 mm), ninth generation (2400 mm x 2800 mm), or tenth generation (2950 mm x 3400 mm) substrate can be used.
  • This allows a large display device to be manufactured.
  • by increasing the size of the substrate more display devices can be produced from one substrate, thereby reducing production costs.
  • Materials for flexible substrates, laminated films, base films, etc. that can be used include, for example, polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resins, polyimides, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamides (nylon, aramid, etc.), polysiloxanes, cycloolefin resins, polystyrene, polyamideimide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resins, cellulose nanofibers, etc.
  • polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN)
  • PET polyethylene naphthalate
  • PEN polyacrylonitrile
  • acrylic resins polyimides
  • polymethyl methacrylate polycarbonate
  • PC polyethersulf
  • a lightweight semiconductor device including the transistor 10 can be provided.
  • a semiconductor device that is resistant to shocks can be provided.
  • a semiconductor device that is less likely to break can be provided.
  • the material used for the flexible substrate for the substrate may have a linear expansion coefficient of 1 ⁇ 10 ⁇ 3 /K or less, 5 ⁇ 10 ⁇ 5 /K or less, or 1 ⁇ 10 ⁇ 5 /K or less.
  • aramid is suitable as a flexible substrate because of its low linear expansion coefficient.
  • a metal element selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a semiconductor represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the method for forming the conductive material is not particularly limited, and various methods such as vapor deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), sputtering, and spin coating can be used.
  • a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be used as the conductive material.
  • a layer formed of a Cu-X alloy can be processed by a wet etching process, which makes it possible to reduce manufacturing costs.
  • an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium may be used as the conductive material.
  • a conductive material that can be used for the conductive layer a conductive material containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide with added silicon oxide, can be used.
  • a conductive material containing nitrogen such as titanium nitride, tantalum nitride, or tungsten nitride, can be used.
  • the conductive layer can have a layered structure in which a conductive material containing oxygen, a conductive material containing nitrogen, or a material containing the above-mentioned metal element is appropriately combined.
  • the conductive layer may have a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, or a three-layer structure in which a titanium layer is laminated on an aluminum layer on the titanium layer, and a titanium layer is further laminated on the aluminum layer.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • the conductive layer may have a stacked structure that combines the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • the conductive layer may have a three-layer structure in which a conductive layer containing copper is laminated on a conductive layer containing at least one of indium or zinc and oxygen, and a conductive layer containing at least one of indium or zinc and oxygen is further laminated on top of that.
  • multiple conductive layers containing at least one of indium or zinc and oxygen may be laminated and used as the conductive layer.
  • Each insulating layer is made of a single layer or a stack of insulating materials selected from aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. Also, a plurality of oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.
  • the method for forming the insulating material is not particularly limited, and various methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.
  • an oxynitride refers to a material that contains more nitrogen than oxygen.
  • An oxynitride refers to a material that contains more oxygen than nitrogen.
  • the content of each element can be measured, for example, using Rutherford backscattering spectrometry (RBS).
  • the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material that is difficult for impurities to penetrate.
  • an insulating material containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.
  • Examples of insulating materials that are difficult for impurities to penetrate include aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and silicon nitride.
  • an insulating layer that can function as a planarization layer may be used as the insulating layer.
  • materials for the insulating layer that can function as a planarization layer include acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors thereof.
  • low dielectric constant materials low-k materials
  • siloxane resin PSG (phosphorus glass), BPSG (borophosphorus glass), etc.
  • multiple insulating layers made of these materials may be stacked.
  • the siloxane resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material.
  • the siloxane resin may use an organic group (e.g., an alkyl group or an aryl group) or a fluoro group as a substituent.
  • the organic group may also have a fluoro group.
  • a CMP process may be performed on the surface of the insulating layer, etc.
  • the unevenness of the surface of the insulating layer, etc. can be reduced, and the coverage of the insulating layer and conductive layer that will be formed later can be improved.
  • the semiconductor layer 161 a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor), such as silicon or germanium, can be used.
  • a semiconductor of a single element, a compound semiconductor, or a layered material also referred to as an atomic layer material, a two-dimensional material, or the like
  • an organic material having semiconductor properties or a metal oxide having semiconductor properties also referred to as an oxide semiconductor
  • these semiconductor materials may contain impurities as dopants.
  • single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon may be used as the semiconductor layer 161.
  • LTPS low temperature polysilicon
  • Transistors using amorphous silicon for the semiconductor layer 161 can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer 161 have high field effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the semiconductor layer 161 have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • the semiconductor layer 161 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (typically MoS 2 ), molybdenum selenide (typically MoSe 2 ), molybdenum tellurium (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten tellurium (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), and zirconium selenide (typically ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 moly MoTe 2
  • tungsten sulfide typically WS 2
  • tungsten selenide typically
  • an oxide semiconductor has a band gap of 2 eV or more
  • a transistor also referred to as an "OS transistor" using an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed has an extremely low off-state current. Therefore, the power consumption of a semiconductor device including an OS transistor can be reduced.
  • an OS transistor operates stably even in a high-temperature environment and has little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environmental temperature range of room temperature or higher and 200° C. or lower. In addition, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.
  • an OS transistor as the transistor 10. Since an OS transistor has a high withstand voltage between the source and drain, the channel length can be shortened. Therefore, the on-current can be increased. An OS transistor is suitable for a vertical channel transistor.
  • the channel length can be 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L can be 100 nm or more and 1 ⁇ m or less.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • element M is a metal element or semimetal element that has a high bond energy with oxygen, for example, a metal element or semimetal element that has a higher bond energy with oxygen than indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may contain one or more metal elements having a large periodic number instead of or in addition to indium.
  • metal elements having a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be realized.
  • In-Zn oxide is used for the semiconductor layer of an OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc.
  • an In-Sn oxide is used for the semiconductor layer of an OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of tin.
  • an In-Sn-Zn oxide is used for the semiconductor layer of an OS transistor
  • a metal oxide in which the atomic ratio of indium is higher than that of tin can be used.
  • a metal oxide in which the atomic ratio of zinc is higher than that of tin is preferable to use.
  • In-Al-Zn oxide is used for the semiconductor layer of an OS transistor, a metal oxide in which the atomic ratio of indium is higher than that of aluminum can be used. Furthermore, it is preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of aluminum.
  • a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium.
  • In-M-Zn oxide is used for the semiconductor layer of an OS transistor
  • a metal oxide in which the atomic ratio of indium to the number of atoms of the metal element is higher than the atomic ratio of element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • the sum of the atomic ratios of the metal elements can be the atomic ratio of element M.
  • the sum of the atomic ratio of gallium and the atomic ratio of aluminum can be the atomic ratio of element M.
  • the atomic ratios of indium, element M, and zinc are within the above-mentioned range.
  • a metal oxide in which the ratio of the number of indium atoms to the sum of the atomic numbers of the metal elements among the main component elements contained in the metal oxide is 30 atomic % or more and 100 atomic %, preferably 30 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 95 atomic %, more preferably 35 atomic % or more and 90 atomic %, more preferably 40 atomic % or more and 90 atomic %, more preferably 45 atomic % or more and 90 atomic %, more preferably 50 atomic % or more and 80 atomic %, more preferably 60 atomic % or more and 80 atomic %, more preferably 70 atomic % or more and 80 atomic %.
  • In-M-Zn oxide it is preferable that the ratio of the number of indium atoms to the total number of atoms of indium, element M, and zinc is in the above-mentioned
  • the field effect mobility of the transistor can be increased by increasing the ratio of the number of indium atoms to the sum of the number of atoms of the metal elements among the main component elements contained in the metal oxide.
  • a circuit capable of high-speed operation can be manufactured.
  • the area occupied by the circuit can be reduced. For example, when the transistor is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, the signal delay in each wiring can be reduced and display unevenness can be suppressed.
  • the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • composition of metal oxides can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide is preferably formed by sputtering or ALD.
  • the atomic ratio of the target may differ from the atomic ratio of the metal oxide.
  • the atomic ratio of zinc in the metal oxide may be smaller than the atomic ratio of the target.
  • the atomic ratio of zinc in the metal oxide may be about 40% to 90% of the atomic ratio of zinc contained in the target.
  • a transistor with high reliability when a positive bias is applied can be obtained.
  • a transistor with a small amount of variation in threshold voltage in a PBTS test can be obtained.
  • defect levels at or near the interface between the semiconductor layer and the gate insulating layer are defect levels at or near the interface between the semiconductor layer and the gate insulating layer.
  • the reason why the use of a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer can suppress the variation in threshold voltage in the PBTS test is thought to be, for example, as follows.
  • the gallium contained in the metal oxide has the property of attracting oxygen more easily than other metal elements (e.g., indium or zinc). Therefore, it is presumed that at the interface between the metal oxide containing a large amount of gallium and the gate insulating layer, gallium combines with excess oxygen in the gate insulating layer, making it easier to create carrier (here, electron) trap sites. Therefore, it is thought that when a positive potential is applied to the gate, carriers are trapped at the interface between the semiconductor layer and the gate insulating layer, causing the threshold voltage to vary.
  • a metal oxide in which the atomic ratio of indium is higher than that of gallium can be applied to the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than that of gallium. In other words, it is preferable to apply a metal oxide in which the atomic ratios of metal elements satisfy In>Ga and Zn>Ga to the semiconductor layer.
  • the semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is higher than 0 atomic % and 50 atomic % or less, preferably 0.1 atomic % to 40 atomic % or less, more preferably 0.1 atomic % to 35 atomic % or less, more preferably 0.1 atomic % to 30 atomic % or less, more preferably 0.1 atomic % to 25 atomic % or less, more preferably 0.1 atomic % to 20 atomic % or less, more preferably 0.1 atomic % to 15 atomic % or less, and more preferably 0.1 atomic % to 10 atomic % or less.
  • a metal oxide that does not contain gallium may be applied to the semiconductor layer of an OS transistor.
  • In-Zn oxide may be applied to the semiconductor layer.
  • the field effect mobility of the transistor can be increased by increasing the atomic ratio of indium to the atomic number of metal elements contained in the metal oxide.
  • the metal oxide becomes highly crystalline, so that the fluctuation in the electrical characteristics of the transistor is suppressed and the reliability can be increased.
  • a metal oxide that does not contain gallium and zinc, such as indium oxide may be applied to the semiconductor layer. By using a metal oxide that does not contain gallium, the fluctuation in the threshold voltage, particularly in a PBTS test, can be made extremely small.
  • an oxide containing indium and zinc can be used for the semiconductor layer.
  • gallium has been used as a representative example, the present invention can also be applied to the case where element M is used instead of gallium. It is preferable to use a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M for the semiconductor layer. It is also preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M.
  • Light incident on a transistor may cause the transistor's electrical characteristics to fluctuate.
  • transistors applied to areas where light can be incident have small fluctuations in electrical characteristics under light irradiation and high reliability against light. Reliability against light can be evaluated, for example, by the amount of variation in threshold voltage in an NBTIS test.
  • a transistor with high reliability against light can be obtained.
  • a transistor with a small variation in threshold voltage in an NBTIS test can be obtained.
  • a metal oxide in which the atomic ratio of element M is equal to or greater than the atomic ratio of indium has a larger band gap, and the variation in threshold voltage of the transistor in an NBTIS test can be reduced.
  • the band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, more preferably 2.5 eV or more, more preferably 3.0 eV or more, more preferably 3.2 eV or more, more preferably 3.3 eV or more, more preferably 3.4 eV or more, and more preferably 3.5 eV or more.
  • metal oxides in which the ratio of the number of atoms of element M to the number of atoms of the contained metal element is 20 atomic % or more and 70 atomic % or less, preferably 30 atomic % or more and 70 atomic % or less, more preferably 30 atomic % or more and 60 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, and more preferably 50 atomic % or more and 60 atomic % or less are suitable as semiconductor layers.
  • metal oxides can be used in which the atomic ratio of indium to the atomic number of the metal element is equal to or less than the atomic ratio of gallium.
  • metal oxides in which the ratio of the number of gallium atoms to the number of atoms of the contained metal elements is 20 atomic % or more and 60 atomic % or less, preferably 20 atomic % or more and 50 atomic % or less, more preferably 30 atomic % or more and 50 atomic % or less, more preferably 40 atomic % or more and 60 atomic % or less, more preferably 50 atomic % or more and 60 atomic % or less are particularly suitable.
  • a metal oxide with a high content of element M By applying a metal oxide with a high content of element M to the semiconductor layer, a transistor with high reliability against light can be obtained. By applying this transistor to a transistor that requires high reliability against light, a semiconductor device with high reliability can be obtained.
  • the two or more metal oxide layers in the semiconductor layer may have different compositions.
  • gallium or aluminum as the element M.
  • a laminate structure may be used, which includes any one selected from indium oxide, indium gallium oxide, and IGZO, and any one selected from IAZO, IAGZO, and ITZO (registered trademark).
  • the band gaps of the first and third semiconductor layers are larger than the band gap of the second semiconductor layer is preferable. With this configuration, it is possible to make the main current path the second layer, resulting in a so-called buried channel structure.
  • the semiconductor layer is preferably a metal oxide layer having crystallinity.
  • a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a nano-crystalline (nc: nano-crystal) structure, or the like can be used.
  • CAAC c-axis aligned crystal
  • nc nano-crystalline
  • the density of defect levels in the semiconductor layer can be reduced, and a highly reliable display device can be realized.
  • the semiconductor layer of the OS transistor may have a stacked structure of two or more metal oxide layers with different crystallinity.
  • a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer may be used, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer.
  • the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer.
  • the two or more metal oxide layers in the semiconductor layer may have the same or approximately the same composition.
  • the same sputtering target can be used to form the stacked structure, which can reduce manufacturing costs.
  • the same sputtering target can be used to form a stacked structure of two or more metal oxide layers with different crystallinity by changing the oxygen flow rate ratio. Note that the two or more metal oxide layers in the semiconductor layer may have different compositions.
  • the channel length L is determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Therefore, a transistor with a short channel length L can be manufactured with high precision.
  • the characteristic variation between the multiple transistors 10 is also reduced. Therefore, the operation of a semiconductor device including the transistor 10 can be stabilized and the reliability can be improved.
  • the reduction in the characteristic variation increases the degree of freedom in the circuit design of the semiconductor device and the operating voltage can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.
  • the oxide semiconductor in the region in contact with the insulating layer 161 becomes n-type and can function as a source region or a drain region.
  • a material containing silicon, nitrogen, and hydrogen may be used for the insulating layer.
  • silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen may be used.
  • the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161 are preferably made of a conductive material that makes the oxide semiconductor n-type.
  • a conductive material containing nitrogen may be used.
  • a conductive material containing titanium or tantalum and nitrogen may be used.
  • Another conductive material may be provided over the conductive material containing nitrogen.
  • a material in which hydrogen is reduced and which contains oxygen for the insulating layer 157 For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 161, which is an oxide semiconductor, is in contact with the insulating layer 157 in which hydrogen is reduced, the semiconductor layer 161 is less likely to become n-type. Furthermore, when the semiconductor layer 161, which is an oxide semiconductor, is in contact with the insulating layer 157 containing oxygen, oxygen vacancies in the semiconductor layer 161 are reduced, and the characteristics of the transistor 10 are stabilized, leading to improved reliability.
  • the insulating layer 157 preferably contains excess oxygen.
  • excess oxygen refers to oxygen that is released by heating.
  • a material containing excess oxygen it is preferable to use a material through which oxygen is difficult to permeate for the insulating layer 156 and the insulating layer 158.
  • an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used as a material through which oxygen is difficult to permeate.
  • insulating layer 157 an insulating layer containing silicon and oxygen (insulating layer 157) is between two insulating layers containing silicon and nitrogen (insulating layer 156, insulating layer 158).
  • the insulating layer 156 and the insulating layer 158 may be made of a material that does not contain hydrogen or contains very little hydrogen.
  • silicon nitride or silicon oxynitride containing very little hydrogen may be used.
  • the region where the semiconductor layer 161 contacts the insulating layer 156 and the region where the semiconductor layer 161 contacts the insulating layer 158 are not made n-type. Therefore, the region of the semiconductor layer 161 that contacts the conductive layer 160 functions as one of the source (source region) or the drain (drain region).
  • the region of the semiconductor layer 161 that contacts the conductive layer 155 functions as the other of the source (source region) or the drain (drain region).
  • the thickness ts obtained by adding up the thicknesses of the insulating layer 156, the insulating layer 157, and the insulating layer 158 corresponds to the channel length L of the transistor 10 (see FIG. 16A).
  • the channel length L can be controlled by adjusting the thicknesses of insulating layers 156, 157, and 158.
  • the channel length L can be set to 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L can be set to 100 nm or more and 1 ⁇ m or less.
  • insulating layer 156 insulating layer 157, insulating layer 1528 between conductive layer 155 and conductive layer 160 is shown, but the number of insulating layers between conductive layer 155 and conductive layer 160 is not limited to this.
  • the insulating layer between conductive layer 155 and conductive layer 160 can be one layer or two layers. Also, it can be four or more layers.
  • the perimeter p of the opening 159 is the channel width W of the transistor 10 (see FIG. 16C).
  • the perimeter p may be determined, for example, at a position half the thickness t (t/2) or half the thickness ts (ts/2) of the insulating layer 157.
  • the perimeter at any position of the opening 159 may be the channel width W as necessary.
  • the perimeter p at the bottom of the opening 159 may be the channel width W, or the perimeter p at the top of the opening 159 may be the channel width W.
  • the outline (planar shape) of the opening 159 viewed from the Z direction is shown as a circle, but is not limited to this.
  • the outline of the opening 159 viewed from the Z direction can be an ellipse (see FIG. 16D). It can also be a rectangle (see FIG. 16E). Note that FIG. 16E shows a rectangle with rounded corners.
  • the outline of the opening 159 viewed from the Z direction can be a shape that includes one or both of straight and curved portions (see FIG. 16F).
  • the parasitic capacitance occurring between the gate and the source is different from the parasitic capacitance occurring between the gate and the drain.
  • 17A and 17B show plan views similar to those of FIG. 15A.
  • the conductive layer 163 overlaps the conductive layer 160 around the periphery of the opening 159 so as to surround the opening 159, and overlaps the conductive layer 160 at the bottom of the opening 159.
  • FIG 17A the area that functions as capacitance C1 when viewed from the Z direction is indicated by a hatched pattern.
  • the area where conductive layer 160 and conductive layer 163 overlap each other on insulating layer 154 with semiconductor layer 161 and insulating layer 162 interposed therebetween functions as capacitance C1 (see Figures 16B and 17A). Note that insulating layer 154 and insulating layer 162 are omitted from Figure 17A.
  • FIG 17B the area that functions as capacitance C2 when viewed from the Z direction is indicated with a hatched pattern.
  • the area where conductive layer 155 and conductive layer 163 overlap with semiconductor layer 161 and insulating layer 162 in between functions as capacitance C2 (see Figures 16B and 17B). Note that insulating layer 154 and insulating layer 162 are omitted from Figure 17B.
  • the overlap area of the conductive layer 163 and the conductive layer 160 can be easily adjusted, and the electrical characteristics of the transistor 10 are unlikely to be affected. For example, by increasing the overlap area of the conductive layer 163 and the conductive layer 160, the capacitance value of the capacitor C1 can be increased.
  • a conductive layer 166 adjacent to the semiconductor layer 161 may be provided in the insulating layer 157.
  • the conductive layer 166 is provided without contacting the semiconductor layer 161.
  • the conductive layer 166 is preferably provided to surround the semiconductor layer 161.
  • the conductive layer 166 can function as a backgate electrode of the transistor 10.
  • the transistor 10 shown in FIG. 18A functions as a transistor having a backgate (backgate electrode).
  • FIG. 18B is an equivalent circuit diagram of the transistor 10 shown in FIG. 18A.
  • the backgate electrode will be explained.
  • the backgate electrode is formed of a conductive layer, and is arranged so that the gate electrode and the backgate electrode sandwich the channel formation region of the semiconductor layer. Therefore, the backgate electrode can function in the same manner as the gate electrode.
  • the potential of the backgate electrode may be the same as that of the gate electrode, or may be the GND potential or any other potential.
  • the gate electrode and the back gate electrode are formed of a conductive layer, they have a function of preventing an electric field generated outside the transistor from acting on the channel formation region of the semiconductor layer (particularly an electric field shielding function against static electricity, etc.). As a result, the characteristic variation between transistors is reduced. In addition, the deterioration of the transistor characteristics due to the GBTS test is suppressed. For example, by having a back gate electrode, the variation in threshold voltage before and after the GBTS test can be suppressed. Furthermore, the variation in threshold voltage before and after the GBTS test is smaller for a transistor having a back gate electrode than for a transistor without a back gate electrode.
  • GBTS (NBTS and PBTS) testing is a type of accelerated testing that allows for the evaluation, in a short period of time, of changes in transistor characteristics (aging) that occur over a long period of use.
  • the amount of change in a transistor's threshold voltage before and after a GBTS test is an important indicator for examining reliability. The smaller the amount of change in threshold voltage before and after a GBTS test, the more reliable the transistor is.
  • the back gate electrode when light is incident from the back gate electrode side, can be formed from a conductive film having light-shielding properties to prevent the light from entering the semiconductor layer from the back gate electrode side.
  • the gate electrode can be formed from a conductive film having light-shielding properties to prevent the light from entering the semiconductor layer from the gate electrode side.
  • the gate electrode and the back gate electrode can block the electric field generated by the drain electrode from acting on the semiconductor layer. This can suppress the fluctuation in the on-current rise voltage caused by the fluctuation in the drain voltage. This effect is particularly noticeable when a potential is supplied to the gate electrode and the back gate electrode.
  • the apparent channel width W of the transistor 10 can be increased.
  • the resistance between the source and drain when the transistor 10 is in the on state decreases, and Id in the on state can be increased.
  • Figure 19A is a plan view of transistor 10 including transistor 10a and transistor 10b.
  • Figure 19B is a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 19A.
  • Figure 19C is a perspective view showing a cutaway portion of transistor 10 including transistor 10a and transistor 10b.
  • Figure 19D is an equivalent circuit diagram of transistor 10 including transistor 10a and transistor 10b. To make the configuration of transistor 10 easier to understand, some of the components of transistor 10 are omitted in Figures 19A and 19C.
  • Transistors 10a and 10b have the same configuration as transistor 10 described with reference to Figures 15 and 16.
  • Transistor 10a is provided in a region including opening 159a
  • transistor 10b is provided in a region including opening 159b. Openings 159a and 159b can be formed in the same manner as opening 159.
  • a part of the conductive layer 155 functions as one of the source electrode or drain electrode of transistor 10a, and another part of the conductive layer 155 functions as one of the source electrode or drain electrode of transistor 10b.
  • a part of the conductive layer 160 functions as the other of the source electrode or drain electrode of transistor 10a, and another part of the conductive layer 160 functions as the other of the source electrode or drain electrode of transistor 10b.
  • a part of the conductive layer 163 functions as the gate electrode of transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of transistor 10b.
  • one of the source or drain of transistor 10a is electrically connected to one of the source or drain of transistor 10b, and the other of the source or drain of transistor 10a is electrically connected to the other of the source or drain of transistor 10b.
  • the gate of transistor 10a is electrically connected to the gate of transistor 10b.
  • transistors 10a and 10b By connecting multiple transistors 10 (here, transistors 10a and 10b) in series, the apparent channel length L of transistor 10 can be increased. Increasing channel length L can improve the saturation characteristics of transistor 10.
  • Figure 20A is a plan view of transistor 10 including transistor 10a and transistor 10b.
  • Figure 20B is a cross-sectional view of the portion indicated by dashed line A1-A2 in Figure 20A.
  • Figure 20C is a perspective view showing a cutaway portion of transistor 10 including transistor 10a and transistor 10b.
  • Figure 20D is an equivalent circuit diagram of transistor 10 including transistor 10a and transistor 10b. To make the configuration of transistor 10 easier to understand, some of the components of transistor 10 are omitted in Figures 20A and 20C.
  • Transistors 10a and 10b have a similar configuration to transistor 10 described using Figure 19, but differ in that conductive layer 155 is separated into conductive layer 155a and conductive layer 155b.
  • the conductive layer 155a functions as one of the source electrode or drain electrode of the transistor 10a, and a part of the conductive layer 160 functions as the other of the source electrode or drain electrode of the transistor 10a. Another part of the conductive layer 160 functions as one of the source electrode or drain electrode of the transistor 10b, and the conductive layer 155b functions as the other of the source electrode or drain electrode of the transistor 10b.
  • a part of the conductive layer 163 functions as the gate electrode of the transistor 10a, and another part of the conductive layer 163 functions as the gate electrode of the transistor 10b.
  • transistor 10a and transistor 10b switch between the on state and the off state simultaneously, and function as one transistor 10.
  • Figure 21 is a diagram showing an example of the planar configuration of the signal output circuit 110a.
  • Figure 22A is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A1-A2 in Figure 21.
  • Figure 22A is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A2-A3 in Figure 21.
  • Figure 23A is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A4-A5 in Figure 21.
  • Figure 23B is a diagram showing an example of the cross-sectional configuration of the portion shown by the dashed line passing through A6-A7 in Figure 21.
  • the signal output circuit 110a has an insulating layer 154 on the substrate 148, and a conductive layer 155 (for example, conductive layer 155[1] and conductive layer 155[3] in FIG. 22A, conductive layer 155[3] and conductive layer 155[4] in FIG. 22B, conductive layer 155[10] and conductive layer 155[11] in FIG. 23A) on the insulating layer 154.
  • a conductive layer 155 for example, conductive layer 155[1] and conductive layer 155[3] in FIG. 22A, conductive layer 155[3] and conductive layer 155[4] in FIG. 22B, conductive layer 155[10] and conductive layer 155[11] in FIG. 23A
  • the stacked configuration of the signal output circuit 110a which uses the VFET described above for the transistor 10, has some common parts with the example configuration of the transistor 10 described above. Therefore, the following mainly describes the parts that differ from the example configuration of the transistor 10 described above.
  • the reference numerals of components related to transistor 10[1] may be given the reference numerals for identifying [1].
  • the conductive layer 163 functioning as the gate electrode of transistor 10[1] may be referred to as conductive layer 163[1].
  • the reference numerals of components common to multiple transistors 10 may be given the reference numerals for identifying one of the multiple transistors 10.
  • the conductive layer 163 functioning as the gate electrode of each of transistors 10[2], transistor 10[9], and transistor 10[11] may be referred to as conductive layer 163[2].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[3] may be referred to as the opening 159[3] and the semiconductor layer 161[3].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[4] may be referred to as the opening 159[4] and the semiconductor layer 161[4].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[7] may be referred to as the opening 159[7] and the semiconductor layer 161[7].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[8] may be referred to as the opening 159[8] and the semiconductor layer 161[8].
  • the opening 159 and the semiconductor layer 161 of the transistor 10[10] may be referred to as the opening 159[10] and the semiconductor layer 161[10].
  • the signal output circuit 110a has conductive layers 181[1] to 181[4] on the insulating layer 158 (see FIG. 21 and FIG. 23A).
  • the conductive layers 181 (conductive layers 181[1] to 181[4]) can be formed using the same material and method as the conductive layer 160. In addition, the conductive layer 181 can be formed at the same time as the conductive layer 160.
  • the signal output circuit 110a also has an insulating layer 187 on the insulating layer 164.
  • the insulating layer 187 preferably functions as a planarizing layer that reduces steps caused by transistors, capacitors, wiring, and the like formed in the lower layers.
  • An organic insulating film is suitable as a material that functions as a planarizing layer. After the insulating layer 187 is formed using an inorganic or organic material, the insulating layer 187 may be subjected to a planarizing process using a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • the signal output circuit 110a also has conductive layers 191 to 199, wiring 131, and wiring 132 on the insulating layer 187 (see FIG. 21, FIG. 22A, FIG. 22B, and FIG. 23A).
  • the conductive layers 191 to 199, wiring 131, and wiring 132 can be formed using the same materials and methods as the other conductive layers.
  • the conductive layer 191 functions as the terminal 111 shown in FIG.
  • the conductive layer 192 functions as the terminal 112
  • the conductive layer 193 functions as the terminal 113
  • the conductive layer 194 functions as the terminal 114
  • the conductive layer 195 functions as the terminal 115
  • the conductive layer 196 functions as the terminal 116
  • the conductive layer 197 functions as the terminal 117
  • the conductive layer 198 functions as the terminal 118.
  • openings penetrating the insulating layers 162, 164, and 187 are provided on the conductive layers 160[2], 160[3], 181[1], 181[2], 181[3], and 181[4], respectively.
  • the wiring 132 and the conductive layer 160[2] are electrically connected in the opening provided on the conductive layer 160[2]. More specifically, the wiring 132 and the conductive layer 160[2] are electrically connected at the bottom of the opening provided on the conductive layer 160[2].
  • Two openings are provided on the conductive layer 160[3]. In one of the two openings, the wiring 131 and the conductive layer 160[3] are electrically connected. In the other of the two openings, the conductive layer 199 and the conductive layer 160[3] are electrically connected.
  • the conductive layer 191 and the conductive layer 181[1] are electrically connected in an opening provided on the conductive layer 181[1].
  • the conductive layer 194 and the conductive layer 181[2] are electrically connected in an opening provided on the conductive layer 181[3].
  • the conductive layer 198 and the conductive layer 181[3] are electrically connected in an opening provided on the conductive layer 181[4].
  • the conductive layer 196 and the conductive layer 181[4] are electrically connected in an opening provided on the conductive layer 181[4].
  • the signal output circuit 110a has openings penetrating the insulating layer 164 and the insulating layer 187 on each of the conductive layers 163[1], 163[3], 163[4], 163[5], and 163[7].
  • the conductive layer 197 and the conductive layer 163[1] are electrically connected.
  • the conductive layer 193 and the conductive layer 163[3] are electrically connected.
  • the conductive layer 192 and the conductive layer 163[4] are electrically connected.
  • the conductive layer 195 and the conductive layer 163[5] are electrically connected.
  • the conductive layer 199 and the conductive layer 163[7] are electrically connected.
  • the conductive layer 160[3] and the conductive layer 163[7] are electrically connected via the conductive layer 199.
  • the signal output circuit 110a has openings penetrating the insulating layers 156, 157, and 158 on each of the conductive layers 155[1], 155[2], 155[3], 155[4], 155[8], 155[9], 155[10], and 155[11].
  • the conductive layer 160[3] and the conductive layer 155[1] are electrically connected.
  • the conductive layer 160[1] and the conductive layer 155[2] are electrically connected.
  • the conductive layer 160[4] and the conductive layer 155[3] are electrically connected.
  • the conductive layer 181[1] and the conductive layer 155[8] are electrically connected.
  • the conductive layer 181[3] and the conductive layer 155[10] are electrically connected.
  • Two openings are provided on conductive layer 155[9]. In one of the two openings, conductive layer 160[8] and conductive layer 155[9] are electrically connected. In the other of the two openings, conductive layer 181[2] and conductive layer 155[9] are electrically connected.
  • Two openings are provided on the conductive layer 155[11]. In one of the two openings, the conductive layer 160[10] and the conductive layer 155[11] are electrically connected. In the other of the two openings, the conductive layer 181[4] and the conductive layer 155[11] are electrically connected.
  • the signal output circuit 110a has openings penetrating the insulating layers 156, 157, and 158 on the conductive layers 155[4] and 155[7], respectively.
  • the conductive layer 163[2] and the conductive layer 155[4] are electrically connected (see FIG. 23B).
  • the conductive layer 163[8] and the conductive layer 155[7] are electrically connected.
  • the conductive layer 155[4] also functions as the conductive layer 155[5] and the conductive layer 155[6].
  • the conductive layer 160[1] also functions as the conductive layer 160[7].
  • the conductive layer 160[2] also functions as the conductive layer 160[6], the conductive layer 160[9], and the conductive layer 160[11].
  • the conductive layer 160[3] also functions as the conductive layer 160[5].
  • the conductive layer 163[1] also functions as the conductive layer 163[6].
  • the conductive layer 163[2] also functions as the conductive layer 163[9] and the conductive layer 163[11].
  • the conductive layer 163[8] also functions as the conductive layer 163[10].
  • conductive layer 155[4] and conductive layer 160[6] overlap via insulating layer 156, insulating layer 157, and insulating layer 158 functions as capacitance 20[1].
  • the capacitance C1 of the transistor 10[8] can be used as the capacitance 20[2].
  • the capacitance C1 of the transistor 10[8] it is not necessary to separately provide the capacitance 20[2], and therefore a semiconductor device with a small occupancy area can be realized (see FIG. 21). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[8].
  • the capacitance C1 of the transistor 10[10] can be used as the capacitance 20[3].
  • the capacitance C1 of the transistor 10[10] it is not necessary to separately provide the capacitance 20[3], and therefore a semiconductor device with a small occupation area can be realized (see FIG. 21 and FIG. 23A). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[10].
  • Figure 24 shows a circuit diagram of the signal output circuit 110a when the capacitance C1 of the transistor 10[8] is used as the capacitance 20[2] and the capacitance C1 of the transistor 10[10] is used as the capacitance 20[3].
  • Transistors other than transistor 10[10] and transistor 10[10] may be configured with transistors other than VFETs. However, in order to realize a semiconductor device with a reduced occupation area, it is preferable to use many transistors according to one embodiment of the present invention in the signal output circuit 110a. Therefore, it is preferable to use transistors according to one embodiment of the present invention for all transistors included in the signal output circuit 110a.
  • Figure 25 is a timing chart for explaining an example of the operation of the signal output circuit 110a[i].
  • Figures 26 to 32 are circuit diagrams for explaining an example of the operation of the signal output circuit 110a[i].
  • an "H” indicating potential H or an “L” indicating potential L may be written next to the wiring, etc.
  • an "H” or “L” may be enclosed in letters next to an electrode where a potential change has occurred.
  • an "x" symbol may be written over the transistor.
  • a potential H (VDD) is supplied to wiring 131, and a potential L (VSS) is supplied to wiring 132. It is also assumed that a signal CLK_1 is supplied to terminal 111, a signal CLK_2 is supplied to terminal 112, a signal CLK_3 is supplied to terminal 113, and a signal PWC_1 is supplied to terminal 118.
  • the signal CLK_1 is at a potential L
  • the signal CLK_2 is at a potential H
  • the signal CLK_3 is at a potential H
  • the signal PWC_1 is at a potential L
  • the signal LIN is at a potential L.
  • the transistors 10[2], 10[3], 10[4], 10[9], and 10[11] are in an on state.
  • the transistors 10[1], 10[5], 10[6], 10[7], 10[8], and 10[10] are in an off state.
  • the signal CLK_4 and the signals PWC_2 to PWC_4 are at potential L.
  • the signal CLK_4 and the signals PWC_2 to PWC_4 are not related to the operation of the signal output circuit 110a[i] described here, and therefore are not used in describing the operation of the signal output circuit 110a[i].
  • signal CLK_2 becomes potential L
  • signal LIN becomes potential H (see Figures 25 and 26).
  • transistor 10[1] and transistor 10[6] are turned on.
  • the potential of node ND[1] becomes potential L
  • transistor 10[2], transistor 10[9], and transistor 10[11] are turned off.
  • potentials of nodes ND[2] and ND[3] become a potential (potential H-Vth) that is lower than potential H by the Vth of transistor 10[1].
  • potential H-Vth is set to be equal to or higher than the Vth of the transistor. Therefore, transistors 10[8] and 10[10] are turned on.
  • Potential L is output from terminal 116 as signal OUT, and potential L is output from terminal 114 as signal SROUT.
  • signal CLK_1 becomes potential H
  • signal CLK_3 becomes potential L
  • signal PWC_1 becomes potential H (see FIG. 25).
  • transistor 10[3] is turned off.
  • the potential of node ND[3] is potential H-Vth, so the potential of terminal 114 becomes potential H-Vth-Vth, and the potential of terminal 116 becomes potential H-Vth-Vth.
  • terminal 114 and node ND[3] are connected (capacitively coupled) via capacitance 20[2].
  • Terminal 116 and node ND[3] are connected via capacitance 20[3].
  • Capacitor 20[2] and capacitor 20[3] function as bootstrap capacitance. Therefore, as the potentials of terminal 114 and terminal 116 increase, the potential of node ND[3] increases.
  • node ND[2] also rises, but the moment the potential of node ND[2] exceeds the potential H-Vth, transistors 10[1] and 10[7] are turned off, and nodes ND[2] and ND[3] are put into a floating state.
  • the potential of node ND[3] also rises to potential H-Vth+potential H (2 ⁇ potential H-Vth) (time T2b; see Figures 25 and 28). Because this potential is higher than potential H+Vth, the potentials of terminals 114 and 116 can be set to potential H.
  • signal CLK_2 is at potential H
  • signal PWC_1 is at potential L
  • signal LIN is at potential L (see Figures 25 and 29).
  • transistor 10[4] is turned on.
  • the potential of terminal 116 is at potential L.
  • transistor 10[6] is turned off, and nodes ND[1] and ND[2] are in a floating state.
  • signal CLK_1 is at potential L
  • signal CLK_3 is at potential H
  • signal RIN is at potential H (see Figures 25 and 30). Then, transistors 10[3] and 10[5] are turned on, and the potential of node ND[1] is at potential H. When the potential of node ND[1] is at potential H, transistors 10[2], 10[9], and 10[11] are turned on.
  • transistor 10[2] When transistor 10[2] is turned on, the potential of node ND[2] becomes potential L. Then, transistor 10[7] is turned on, and the potential of node ND[3] also becomes potential L. Therefore, transistors 10[8] and 10[10] are turned off. In addition, when transistors 10[9] and 10[11] are turned on, potential L is supplied to terminal 114, and the potential of terminal 116 (potential L) is maintained.
  • signal CLK_2 becomes potential L (see Figures 25 and 31). Then, transistor 10[4] is turned off.
  • potential L is supplied to terminal 114 and terminal 116 until potential H is supplied to terminal 117 as signal LIN.
  • potential L is output as signal OUT and signal SROUT until potential H is supplied to terminal 117 as signal LIN.
  • signal output circuit [i] can output pulse signals from terminals 114 and 116 in synchronization with a specific combination of signals.
  • the pulse width of signal SROUT which is the pulse signal output from terminal 114 (the time during which potential H is output), is linked to signal CLK.
  • the pulse width of signal OUT which is the pulse signal output from terminal 116 (the time during which potential H is output), is linked to signal PWC.
  • the signal output circuit [i] includes a capacitive element that functions as a bootstrap capacitance, and thus can reliably output a power supply potential (potential H) from the terminal 114 and the terminal 116. Therefore, the signal output circuit [i] according to one embodiment of the present invention has a small output impedance, and can reliably supply potential H to a load such as a circuit connected to the terminal 114 or the terminal 116. Therefore, the operation of a semiconductor device including the signal output circuit [i] according to one embodiment of the present invention is stabilized, and the reliability of the semiconductor device can be improved.
  • the capacitance C1 of the transistor 10[1] is preferably formed between the node ND[1] and the gate of the transistor 10[1].
  • the capacitance C2 of the transistor 10[1] is preferably formed between the wiring 131 to which the power supply potential is supplied and the gate of the transistor 10[1] (see FIG. 33).
  • the node ND[1] is in a floating state except during the period when both the signals CLK_2 and CLK_3 are at the potential H.
  • the capacitance C1 of each of the transistors 10[2], 10[6], 10[9], and 10[11] be formed between the wiring 132 to which the power supply potential is supplied and the gate.
  • the conductive layer 160[2] be electrically connected to the wiring 132 (see FIG. 21).
  • the conductive layer 160[2] functions as a source electrode of each of the transistors 10[2], 10[6], 10[9], and 10[11].
  • each capacitance C1 is connected in parallel to the capacitance 20[1]. This enhances the effect of suppressing the potential fluctuation of the node ND[1] (see FIG. 33).
  • the capacitance C2 of each of the transistors 10[4] and 10[5] between the node ND[1] and the gate. It is also preferable to form the capacitance C1 of the transistor 10[5] between the gate and the wiring 131 to which the power supply potential is supplied.
  • the conductive layer 160[3] is electrically connected to the wiring 131 (see FIG. 21). The conductive layer 160[3] functions as a drain electrode of the transistor 10[5].
  • the capacitance C1 of the transistor 10[4] between the drain and gate of the transistor 10[4].
  • the conductive layer 160[3] functions as the drain electrode of the transistor 10[3].
  • the capacitance value of the parasitic capacitance generated between the node ND [3] and the gate of the transistor 10 [7] is smaller than the capacitance values of the capacitance 20 [2] and the capacitance 20 [3]. Therefore, in the transistor 10 [7], it is preferable that the capacitance C1 is generated between one of the source or drain of the transistor 10 [7] and the gate, and the capacitance C2 is generated between the other of the source or drain of the transistor 10 [7] and the gate (see FIG. 33).
  • Fig. 34 is a timing chart for explaining an operation example of the shift register 100.
  • a signal LIN[1] with a potential H is supplied to the signal output circuit 110[1].
  • a signal with a potential H is output as the signal OUT[1] in synchronization with the signal LIN[1], the signal CLK_1, the signal CLK_4, and the signal PWC_1.
  • a potential L is output as signal OUT[1].
  • a potential H is output as signal OUT[2] in synchronization with signals CLK_1, CLK_2, and PWC_2.
  • a potential L is output as signal OUT[2].
  • a potential H is output as signal OUT[3] in synchronization with signals CLK_3, CLK_4, and PWC_3.
  • potential L is output as signal OUT[3].
  • potential H is output as signal OUT[4] in synchronization with signals CLK_3, CLK_4, and PWC_4. In this manner, potential H is output as signal OUT in order from the 1st stage to the n+2th stage.
  • a transistor used in a semiconductor device such as a signal output circuit according to one embodiment of the present invention
  • a transistor having a structure other than a VFET such as a planar or staggered transistor
  • a VFET may be used in combination with a transistor having a structure other than a VFET.
  • Figure 35 is a perspective view illustrating the configuration of a display module according to one embodiment of the present invention.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • the display device of this embodiment can also be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • Display device 5050A has a configuration in which substrate 5152 and substrate 5151 are bonded together.
  • substrate 5152 is indicated by a dashed line.
  • the display device 5050A has a display portion 5162, a connection portion 5140, a circuit portion 5164, wiring 5165, etc.
  • FIG. 35 shows an example in which an IC 5173 and an FPC 5172 are mounted on the display device 5050A. Therefore, the configuration shown in FIG. 35 can also be said to be a display module having the display device 5050A, an IC, and an FPC.
  • connection portion 5140 is provided outside the display portion 5162.
  • the connection portion 5140 can be provided along one side or multiple sides of the display portion 5162.
  • the connection portion 5140 may be single or multiple.
  • FIG. 35 shows an example in which the connection portion 5140 is provided so as to surround the four sides of the display portion.
  • the connection portion 5140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode. Note that the connection portion 5140 does not have to be provided if it is not necessary, such as when the common electrode is provided on the substrate 5151 side.
  • the circuit portion 5164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 5164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the wiring 5165 has a function of supplying signals and power to the display portion 5162 and the circuit portion 5164.
  • the signals and power are input to the wiring 5165 from the outside via the FPC 5172, or are input to the wiring 5165 from the IC 5173.
  • an IC 5173 is provided on a substrate 5151 by a COG method, a COF method, or the like.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 5173.
  • the display device 5050A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method, or the like.
  • the vertical transistor of one embodiment of the present invention can be applied to, for example, one or both of the display portion 5162 and the circuit portion 5164 of the display device 5050A.
  • the vertical transistor of one embodiment of the present invention can also be applied to the IC 5173.
  • the vertical transistor of one embodiment of the present invention when the vertical transistor of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the vertical transistor of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the vertical transistor of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in the display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the display unit 5162 is an area that displays an image in the display device 5050A, and has a number of periodically arranged pixels 5210.
  • Figure 35 shows an enlarged view of one pixel 5210.
  • the pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied.
  • Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.
  • the pixel 5210 shown in FIG. 35 has a subpixel 5210R that emits red light, a subpixel 5210G that emits green light, and a subpixel 5210B that emits blue light.
  • Each of the subpixels 5210R, 5210G, and 5210B has a display element and a circuit that controls the driving of the display element.
  • a liquid crystal element for example, a liquid crystal element can be used.
  • Examples include a transmissive liquid crystal element, a reflective liquid crystal element, and a semi-transmissive liquid crystal element.
  • various elements e.g., light-emitting elements other than liquid crystal elements can be used as display elements.
  • light-emitting elements include self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini LEDs and micro LEDs.
  • a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type.
  • a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot material may be used.
  • Figure 36 shows an example of a cross section of the display device 5050A when a portion of the region including the FPC 5172, the conductive material 5242, a portion of the circuit portion 5164, a portion of the display portion 5162, a portion of the connection portion 5140, and a portion of the region including the end portion are cut.
  • the display device shown in Figure 36 has a liquid crystal device that operates in VA mode.
  • the substrates 5151 and 5152 are bonded together by an adhesive layer. Liquid crystal is sealed in the area surrounded by the substrates 5151, 5152, and the adhesive layer.
  • the substrate 5152 has a polarizing plate POL2 on its outer surface.
  • the substrate 5151 has a polarizing plate POL1 on its outer surface.
  • a backlight can be provided outside polarizing plate POL2 or outside polarizing plate POL1.
  • transistors in the circuit portion 5164 and the transistors in the display portion 5162 may have the same structure or different structures.
  • the multiple transistors in the circuit portion 5164 may all have the same structure or may be a combination of transistors with different structures.
  • the conductive particles CP are electrically connected to a conductive layer provided on the substrate 5151 side at the connection portion 5140. This allows a potential or signal to be supplied from an FPC or IC arranged on the substrate 5151 side.
  • the conductive particles CP can be made of organic resin or silica particles whose surfaces are coated with a metal material. Nickel or gold is preferably used as the metal material because it can reduce contact resistance. It is also preferable to use particles coated with layers of two or more metal materials, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the conductive particles CP. In this case, the conductive particles CP may be crushed in the vertical direction. This increases the contact area with the conductive layer that is electrically connected to it, reducing contact resistance and suppressing the occurrence of problems such as poor connection.
  • the display device shown in Fig. 37 includes a liquid crystal device that operates in the FFS mode.
  • the pixel electrodes have a comb-like shape or a shape with slits in a plan view.
  • the common electrode is disposed so as to overlap with the pixel electrodes.
  • Figure 38 shows an example in which the pixel electrode and common electrode are arranged upside down.
  • the common electrode has a comb-like or slit-like shape in a plan view, and is provided on the pixel electrode via an insulating layer.
  • Display device configuration example 3 The display device shown in FIG. 39 includes a liquid crystal device operating in the IPS mode.
  • the pixel electrode and the common electrode are both provided on the same insulating layer.
  • the pixel electrode and the common electrode each have a comb-like shape in a plan view, and are arranged so as to interdigitate with each other. It is preferable that the pixel electrode and the common electrode are formed by processing the same conductive film.
  • Display Device Configuration Example 4 40 includes a display device including a liquid crystal device operating in an FFS mode and a light source LS.
  • the display module also includes a flexible substrate 5153. By attaching the substrate 5153 to the layer 511, the layer 511_2 can be reinforced while maintaining the flexibility of the layer 511_2.
  • Layer 511_1 has a transmittance of 80% or more in the visible light range. This allows the light from the backlight to efficiently reach the transmissive liquid crystal display device.
  • Substrate 5151LG has end EG1 and end EG2.
  • End EG2 is the end opposite end EG1. Since layer 511_2 is bent, end EG2 is located between end EG1 and layer 511_2.
  • the substrate 5151LG also has a function of distributing the light incident from the end EG1 toward the substrate 5152.
  • the substrate 5151LG is a light guide plate.
  • a diffusion plate can be used between the substrate 5151LG and the polarizing plate POL1.
  • the light source LS faces the end EG1, and the light source LS irradiates light onto the end EG1.
  • a white LED can be used as the light source LS.
  • the size of the light source LS to be smaller than in a configuration in which the light source LS is arranged so as to sandwich the substrate SUB1 between the light source LS and region 510_1.
  • the thickness of the display device can be made thinner than in a configuration in which the light source LS is arranged so as to sandwich the substrate SUB1 between the light source LS and region 510_1.
  • region 510_2 can be made difficult to view when facing region 510_1.
  • the region surrounding region 510_1 in a frame-like shape can be made difficult to view.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • the semiconductor device of one embodiment of the present invention can also be applied to portions other than the display portion of an electronic device.
  • portions other than the display portion of an electronic device For example, by using the semiconductor device of one embodiment of the present invention in a control portion of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • the electronic device 7500 shown in FIG. 41A is a portable information terminal that can be used as a smartphone.
  • the electronic device 7500 includes a housing 7001, a display portion 7002, a power button 7003, a button 7004, a speaker 7005, a microphone 7006, a camera 7007, a light source 7008, and the like.
  • the display portion 7002 has a touch panel function.
  • a display device of one embodiment of the present invention can be applied to the display portion 7002.
  • Figure 41B is a schematic cross-sectional view including the end of the housing 7001 on the microphone 7006 side.
  • the display panel 7011, the optical member 7012, and the touch sensor panel 7013 are fixed to the protective member 7010 by an adhesive layer (not shown).
  • a part of the display panel 7011 is folded back, and an FPC 7015 is connected to the folded back part.
  • An IC 7016 is mounted on the FPC 7015.
  • the FPC 7015 is connected to a terminal provided on a printed circuit board 7017.
  • FIG 41C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 shown in FIG. 41C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • a display device can be applied to the display portion 7000.
  • Figures 41E and 41F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 41E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 41F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • a display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • BM light-shielding film
  • CF colored layer
  • CLK signal
  • CP conductive particle
  • DL data line
  • dV potential
  • GD driving circuit
  • GL gate line
  • H potential
  • KB layer
  • LC liquid crystal device
  • LIN signal
  • LS light source
  • OUT signal
  • PWC signal
  • RIN signal
  • RX electrode
  • SD driving circuit
  • SP start pulse
  • TD driving circuit
  • TX driving circuit
  • V com potential
  • V data second data potential
  • VDD high power supply potential
  • VL potential supply line
  • V ref potential
  • VSS low power supply potential
  • V w first data potential
  • 10 transistor
  • 100 shift register
  • 104 wiring
  • 106 wiring
  • 107 wiring
  • 108 wiring
  • 110 signal output circuit
  • 111 terminal
  • 112 terminal
  • 113 terminal
  • 114 terminal

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
PCT/IB2024/055385 2023-06-08 2024-06-03 表示装置、表示モジュール、電子機器 Ceased WO2024252247A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202480030975.0A CN121079731A (zh) 2023-06-08 2024-06-03 显示装置、显示模块、电子设备
KR1020257038455A KR20260022295A (ko) 2023-06-08 2024-06-03 표시 장치, 표시 모듈, 전자 기기
JP2025525415A JPWO2024252247A1 (https=) 2023-06-08 2024-06-03

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JP2023094681 2023-06-08
JP2023-094681 2023-06-08

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011141523A (ja) * 2009-10-16 2011-07-21 Semiconductor Energy Lab Co Ltd 液晶表示装置、及び当該液晶表示装置を具備する電子機器
JP2011221072A (ja) * 2010-04-05 2011-11-04 Seiko Epson Corp 電気光学装置及び電子機器
JP2012128006A (ja) * 2010-12-13 2012-07-05 Sony Corp 表示装置及び電子機器
JP2015118373A (ja) * 2013-11-15 2015-06-25 株式会社半導体エネルギー研究所 表示パネル、電子機器
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017138354A (ja) * 2016-02-01 2017-08-10 株式会社ジャパンディスプレイ 表示装置、および表示装置の作製方法
US20180068919A1 (en) * 2016-09-06 2018-03-08 Samsung Display Co., Ltd. Display apparatus
JP2019012229A (ja) * 2017-06-30 2019-01-24 株式会社ジャパンディスプレイ 表示装置
WO2020071010A1 (ja) * 2018-10-02 2020-04-09 株式会社ジャパンディスプレイ 表示装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011141523A (ja) * 2009-10-16 2011-07-21 Semiconductor Energy Lab Co Ltd 液晶表示装置、及び当該液晶表示装置を具備する電子機器
JP2011221072A (ja) * 2010-04-05 2011-11-04 Seiko Epson Corp 電気光学装置及び電子機器
JP2012128006A (ja) * 2010-12-13 2012-07-05 Sony Corp 表示装置及び電子機器
JP2015118373A (ja) * 2013-11-15 2015-06-25 株式会社半導体エネルギー研究所 表示パネル、電子機器
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2017138354A (ja) * 2016-02-01 2017-08-10 株式会社ジャパンディスプレイ 表示装置、および表示装置の作製方法
US20180068919A1 (en) * 2016-09-06 2018-03-08 Samsung Display Co., Ltd. Display apparatus
JP2019012229A (ja) * 2017-06-30 2019-01-24 株式会社ジャパンディスプレイ 表示装置
WO2020071010A1 (ja) * 2018-10-02 2020-04-09 株式会社ジャパンディスプレイ 表示装置

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KR20260022295A (ko) 2026-02-19
CN121079731A (zh) 2025-12-05

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