WO2024252246A1 - 半導体装置、半導体装置の作製方法 - Google Patents

半導体装置、半導体装置の作製方法 Download PDF

Info

Publication number
WO2024252246A1
WO2024252246A1 PCT/IB2024/055384 IB2024055384W WO2024252246A1 WO 2024252246 A1 WO2024252246 A1 WO 2024252246A1 IB 2024055384 W IB2024055384 W IB 2024055384W WO 2024252246 A1 WO2024252246 A1 WO 2024252246A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive layer
oxide
insulating layer
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2024/055384
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
井坂史人
恵木勇司
沼田至優
徳丸亮
石川純
手塚祐朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2025525414A priority Critical patent/JPWO2024252246A1/ja
Publication of WO2024252246A1 publication Critical patent/WO2024252246A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]

Definitions

  • One aspect of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.
  • examples of technical fields related to one aspect of the present invention include semiconductor devices, display devices, liquid crystal display devices, light emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, inspection methods thereof, and methods of using thereof.
  • Non-Patent Document 1 research and development of memories using ferroelectrics is being actively carried out.
  • Non-Patent Document 2 research on ferroelectric HfO2 -based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), research on hafnium oxide-based ferroelectrics (Non-Patent Document 4 ), and demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using ferroelectric Hf0.5Zr0.5O2 with CMOS (Non-Patent Document 5) are also being actively carried out.
  • FeRAM Ferroelectric Random Access Memory
  • Non-Patent Documents 1 to 5 various research and development efforts are being conducted on ferroelectrics.
  • Non-Patent Document 4 reports on possible crystal structures of HfO2 and their respective polarization-electric field characteristics, as shown in FIG.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that occupies a small area. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that consumes low power. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that has a large storage capacity.
  • problems associated with one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not preclude the existence of other problems.
  • the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that the problems associated with one embodiment of the present invention do not need to solve all of the problems listed above and other problems.
  • One embodiment of the present invention solves at least one of the problems listed above and other problems.
  • One aspect of the present invention is a semiconductor device having a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer.
  • the first conductive layer has a first recess.
  • the ferroelectric layer has a region formed along the first recess.
  • the ferroelectric layer has a second recess in a region overlapping the first recess.
  • the second conductive layer is provided so as to fill the second recess.
  • the ferroelectric layer has hafnium, zirconium, and oxygen.
  • one or both of the first conductive layer and the second conductive layer contain titanium and nitrogen.
  • one or both of the first conductive layer and the second conductive layer contain tungsten.
  • One aspect of the present invention is a semiconductor device having a capacitive element and a transistor on the capacitive element.
  • the capacitive element has a first conductive layer, a ferroelectric layer on the first conductive layer, and a second conductive layer on the ferroelectric layer.
  • the ferroelectric layer has hafnium, zirconium, and oxygen.
  • the top surface of the second conductive layer has a region that contacts at least a portion of the bottom surface of the oxide semiconductor layer of the transistor.
  • one or both of the first conductive layer and the second conductive layer contain titanium and nitrogen.
  • one or both of the first conductive layer and the second conductive layer contain tungsten.
  • the first conductive layer has a first recess
  • the ferroelectric layer has a region formed along the first recess
  • the ferroelectric layer has a second recess in a region overlapping the first recess
  • the second conductive layer is provided so as to fill the second recess.
  • the channel of the transistor is formed along the side of the opening in the insulating layer.
  • the oxide semiconductor layer preferably contains one or both of indium and zinc.
  • One aspect of the present invention is a method for manufacturing a semiconductor device, which includes forming a first conductive layer on a substrate, forming a ferroelectric layer on the first conductive layer, and forming a second conductive layer on the ferroelectric layer.
  • the first conductive layer is formed by a metal CVD method with the substrate at a first temperature.
  • the ferroelectric layer is formed by an ALD method using a precursor containing hafnium, a precursor containing zirconium, and an oxidizing agent.
  • the second conductive layer is formed by a metal CVD method with the substrate at a second temperature.
  • the second temperature is 250°C or more and 325°C or less.
  • the first temperature is higher than the second temperature.
  • the first conductive layer and the second conductive layer are formed using titanium chloride and ammonia.
  • the first conductive layer and the second conductive layer are formed using tungsten hexafluoride.
  • the first conductive layer has a first recess
  • the ferroelectric layer is formed along the first recess
  • the ferroelectric layer has a second recess in a region overlapping with the first recess
  • the second conductive layer is formed to fill the second recess.
  • a novel semiconductor device can be provided.
  • a semiconductor device with a small occupancy area can be provided.
  • a semiconductor device with high reliability can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a semiconductor device with a large storage capacity can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects. Therefore, one embodiment of the present invention may not have the effects listed above.
  • the other effects are effects not mentioned in this section, which will be described below. Those skilled in the art can derive the other effects from the descriptions in the specification or drawings, etc., and can be extracted appropriately from these descriptions.
  • One embodiment of the present invention has at least one of the effects listed above and other effects.
  • Fig. 1A is a plan view showing a configuration example of a semiconductor device
  • Fig. 1B and Fig. 1C are cross-sectional views showing the configuration example of a semiconductor device.
  • 2A to 2F are cross-sectional views showing configuration examples of a semiconductor device.
  • 3A to 3D are cross-sectional views showing configuration examples of a semiconductor device.
  • Fig. 4A is a plan view showing a configuration example of a semiconductor device
  • Fig. 4B and Fig. 4C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 5A is a plan view showing a configuration example of a semiconductor device
  • Fig. 5B and Fig. 5C are cross-sectional views showing the configuration example of a semiconductor device.
  • FIG. 6A to 6H are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 7A to 7D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 8 is a diagram for explaining possible crystal structures of HfO 2 and their respective polarization-electric field characteristics, as disclosed in Non-Patent Document 4.
  • Fig. 9A is a plan view showing a configuration example of a semiconductor device
  • Fig. 9B and Fig. 9C are cross-sectional views showing the configuration example of a semiconductor device.
  • 10A is a plan view showing a configuration example of a semiconductor device
  • FIG. 10B is a cross-sectional view showing the configuration example of a semiconductor device.
  • FIG. 10B is a cross-sectional view showing the configuration example of a semiconductor device.
  • FIG. 11 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 12 is a cross-sectional view showing a configuration example of a semiconductor device.
  • Fig. 13A is a diagram for explaining an example of a circuit configuration of a memory cell
  • Fig. 13B is a graph showing an example of a hysteresis characteristic
  • Fig. 13C is a timing chart showing an example of a method for driving a memory cell.
  • 14A to 14C are diagrams showing configuration examples of a storage device.
  • Fig. 15A is a diagram showing an example of the configuration of a storage device
  • Fig. 15B is a schematic diagram of a memory string included in the storage device.
  • Fig. 15A is a diagram showing an example of the configuration of a storage device
  • Fig. 15B is a schematic diagram of a memory string included in the storage device.
  • 16A is a diagram showing an example of the configuration of a storage device
  • Fig. 16B is a schematic diagram of a memory string included in the storage device.
  • 17A and 17B are diagrams showing an example of a semiconductor device.
  • 18A and 18B are perspective views showing an example of an electronic component.
  • 19A to 19J are diagrams showing an example of an electronic device.
  • 20A to 20E are diagrams showing an example of an electronic device.
  • 21A to 21C are diagrams showing an example of an electronic device.
  • FIG. 22 is a diagram showing an example of space equipment.
  • FIG. 23 is a schematic cross-sectional view illustrating a sample prepared in the example.
  • 24A to 24E are diagrams showing the results of GIXRD measurements.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices and may have semiconductor devices.
  • the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc., in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc., disclosed in the drawings, etc.
  • layers and resist masks, etc. may be unintentionally reduced by processes such as etching, but descriptions of this may be omitted in order to facilitate understanding of the invention.
  • a resist mask is formed by a lithography method (photolithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, nanoimprinting, etc.) and then an etching process (removal process) is performed, the resist mask is removed after the etching process is completed, unless otherwise specified.
  • a lithography method photolithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, nanoimprinting, etc.
  • plan views also called “top views”
  • oblique views some components may be omitted to make the invention easier to understand.
  • Some hidden lines may also be omitted.
  • ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Even if a term does not have an ordinal number in this specification, ordinal numbers may be added in the claims to avoid confusion between components. The ordinal numbers added in this specification may differ from those added in the claims. Even if a term has an ordinal number in this specification, ordinal numbers may be omitted in the claims.
  • electrode in this specification and the like do not functionally limit these components.
  • electrode may be used as a part of “wiring”, and vice versa.
  • the terms “electrode” and “wiring” include cases where multiple “electrodes” and “wiring” are integrated together.
  • terminal may be used as a part of “wiring” or “electrode”, and vice versa.
  • terminal includes cases where multiple “electrodes”, “wiring”, “terminals”, etc. are integrated together.
  • an “electrode” can be a part of a “wiring” or “terminal”, and for example, a “terminal” can be a part of a “wiring” or “electrode”.
  • terms such as “electrode”, “wiring”, and “terminal” may be replaced with terms such as "region” in some cases.
  • supplying a signal means supplying a predetermined potential to wiring or the like. Therefore, it may be possible to read “signal” as a term such as “potential”. It may also be possible to read terms such as “potential” as a term such as “signal”. It may also be possible to read “signal” as a term such as “potential”.
  • a “signal” may be a variable potential or a fixed potential. For example, it may be a power supply potential.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • the term “capacitive element” may be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor.
  • the terms “capacitive element”, “parasitic capacitance”, or “gate capacitance” may be rephrased as the term “capacitance”.
  • the term “capacitance” may be rephrased as the term “capacitive element”, “parasitic capacitance”, or “gate capacitance”.
  • a “capacitance” (including a “capacitance” having three or more terminals) is configured to include an insulating layer and a pair of conductive layers sandwiching the insulating layer. Therefore, the term “pair of conductive layers" in “capacitance” may be rephrased as a “pair of electrodes", a “pair of conductive regions", a “pair of regions", or a “pair of terminals”. In addition, the term “one of the pair of terminals” may be referred to as “one terminal” or “first terminal”. In addition, the term “the other of the pair of terminals” may be referred to as “the other terminal” or “second terminal”. The value of the capacitance may be, for example, 0.05 fF or more and 10 pF or less. It may also be, for example, between 1 pF and 10 ⁇ F.
  • source and drain of a transistor may be interchangeable when transistors of different conductivity types are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” can be used interchangeably.
  • gate refers to a gate electrode and a part or all of a gate wiring.
  • a gate wiring refers to a wiring that electrically connects the gate electrode of at least one transistor to another electrode or another wiring.
  • source refers to a source region, a source electrode, and part or all of a source wiring.
  • a source region refers to a region of a semiconductor layer whose resistivity is equal to or lower than a certain value.
  • a source electrode refers to a conductive layer that includes a portion connected to a source region.
  • a source wiring refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or another wiring.
  • drain refers to the drain region, drain electrode, and part or all of the drain wiring.
  • the drain region refers to the region of the semiconductor layer whose resistivity is equal to or lower than a certain value.
  • the drain electrode refers to the conductive layer that includes a portion connected to the drain region.
  • the drain wiring refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or another wiring.
  • the transistors shown in this specification are enhancement type (normally off type) field effect transistors.
  • the threshold voltage (also referred to as "Vth") of the transistors is greater than 0V unless otherwise specified.
  • the transistors shown in this specification are p-channel transistors, the Vth of the transistors is less than or equal to 0V unless otherwise specified.
  • the Vth of multiple transistors of the same conductivity type is the same.
  • off-state current refers to the current (also referred to as “drain current” or “Id”) that flows between the source and drain when the transistor is in an off state (also referred to as a “non-conducting state” or “cut-off state”).
  • the off-state refers to a state in which the potential difference (also referred to as “gate voltage” or “Vg") between the gate and source with respect to the source as a reference is lower than the threshold voltage in an n-channel transistor, and a state in which Vg is higher than the threshold voltage in a p-channel transistor.
  • the off-state current of an n-channel transistor may refer to the drain current when Vg is lower than Vth.
  • the term “leakage current” may be used to mean the same thing as “off-state current.”
  • the term “off-state current” may refer to, for example, a current that flows between the source and drain when a transistor is in an off state.
  • the on-current refers to Id when a transistor is in an on state (also called a "conducting state").
  • the on-state refers to a state in which Vg is equal to or greater than Vth for an n-channel transistor, and a state in which Vg is equal to or less than the threshold voltage for a p-channel transistor.
  • the on-current of an n-channel transistor may refer to the drain current when Vg is equal to or greater than Vth.
  • VDD high power supply potential
  • VSS low power supply potential
  • GND ground potential GND
  • voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Also, “potential” is relative, and the potential applied to wiring, etc. may change depending on the reference potential. Therefore, “voltage” and “potential” can sometimes be used interchangeably.
  • the terms “above,” “below,” “upward,” or “below” indicating the position of the components may be used for convenience in describing the positional relationship between the components with reference to the drawings. Furthermore, the positional relationship between the components may change as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression “insulating layer located above the conductive layer” can be rephrased as “insulating layer located below the conductive layer” by rotating the orientation of the drawing shown by 180 degrees. For example, the expression “insulating layer located above the opening” may include “insulating layer located on the side of the opening.”
  • electrode B on insulating layer A does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • electrode B overlapping insulating layer A does not limit the state in which electrode B is formed on insulating layer A, but does not exclude the state in which electrode B is formed under insulating layer A or the state in which electrode B is formed on the right (or left) side of insulating layer A.
  • electrode B adjacent to insulating layer A does not require that insulating layer A and electrode B are formed in direct contact, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less.
  • substantially parallel or “roughly parallel” refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.
  • substantially perpendicular or “approximately perpendicular” refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.
  • arrows indicating the X-direction, Y-direction, and Z-direction may be attached.
  • the "X-direction” is the direction along the X-axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y-direction” and "Z-direction”.
  • the X-direction, Y-direction, and Z-direction are directions that intersect with each other.
  • the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other.
  • one of the X-direction, Y-direction, and Z-direction may be called the "first direction” or “first direction”.
  • the other may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • the conductive layer 120 may be divided into conductive layer 120a and conductive layer 120b.
  • FIGS. 1A to 1C are plan views and cross-sectional views illustrating a configuration example of a semiconductor device according to one embodiment of the present invention.
  • FIG. 1A is a plan view of the semiconductor device.
  • FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A as viewed from the Y direction.
  • FIG. 1C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in FIG. 1A as viewed from the X direction. Note that some elements have been omitted from the plan view of FIG. 1A for clarity.
  • the semiconductor device of one embodiment of the present invention has an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a capacitor element 100 on the conductive layer 110, and an insulating layer 180.
  • the insulating layer 140 and the insulating layer 180 function as interlayer films, and the conductive layer 110 functions as wiring.
  • the capacitance element 100 has a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130.
  • the conductive layer 120 functions as one of a pair of electrodes (sometimes called an upper electrode)
  • the conductive layer 115 functions as the other of the pair of electrodes (sometimes called a lower electrode)
  • the insulating layer 130 functions as a dielectric. That is, the capacitance element 100 constitutes a MIM (Metal-Insulator-Metal) capacitance.
  • a material that can have ferroelectricity is used as the insulating layer 130.
  • the insulating layer 130 has ferroelectricity. Therefore, the capacitance element 100 functions as a ferroelectric capacitor.
  • the insulating layer 180 has an opening 190 that reaches the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190.
  • the conductive layer 115 has a region that contacts the upper surface of the conductive layer 110 in the opening 190 and a region that contacts the side surface of the insulating layer 180 in the opening 190.
  • the conductive layer 115 has a recess in the region that overlaps with the opening 190. Note that in the configuration shown in Figures 1B and 1C, the conductive layer 115 has a region that contacts at least a portion of the upper surface of the insulating layer 180.
  • the insulating layer 130 is arranged so that at least a portion of it is located in the opening 190.
  • the insulating layer 130 has a region that contacts the upper surface of the conductive layer 115 at the opening 190.
  • the insulating layer 130 has a region that is formed along the recess of the conductive layer 115.
  • the insulating layer 130 has a recess in a region that overlaps with the recess of the conductive layer 115. Note that in the configuration shown in Figures 1B and 1C, the insulating layer 130 has a region that contacts at least a portion of the upper surface of the insulating layer 180.
  • the conductive layer 120 is arranged so that at least a portion of it is located in the opening 190.
  • the conductive layer 120 has a region that contacts the upper surface of the insulating layer 130 in the opening 190.
  • the conductive layer 120 is also provided so as to fill a recess in the insulating layer 130. In other words, the conductive layer 120 is provided so as to fill the opening 190.
  • the capacitive element 100 has an upper electrode and a lower electrode that face each other with a dielectric between them, not only on the bottom surface but also on the side surfaces, and this allows for a larger capacitance per unit area than a parallel plate type capacitive element. Therefore, the deeper the opening 190, the larger the capacitance of the capacitive element 100 can be.
  • the sidewalls of the opening 190 are preferably perpendicular to the upper surface of the conductive layer 110.
  • the opening 190 has a cylindrical shape. With this configuration, miniaturization or high integration of the semiconductor device can be achieved.
  • the sidewalls of the opening 190 can have a tapered shape relative to the upper surface of the conductive layer 110.
  • the coverage of the conductive layer 115 and the like can be improved, and defects such as voids can be reduced.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, there is a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • a conductive layer 115 and an insulating layer 130 are laminated along the sidewall of the opening 190 and the upper surface of the conductive layer 110.
  • a conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190.
  • a capacitance element 100 having such a configuration may be called a trench type capacitance or a trench capacitance.
  • the opening 190 is circular in plan view, but the present invention is not limited to this.
  • the opening 190 can be, for example, a circle, an ellipse, or other nearly circular shape, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or other polygon with rounded corners.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • the opening 190 is preferably circular in plan view. By making the opening circular, the processing accuracy when forming the opening can be improved, and an opening of a fine size can be formed.
  • a circle is not limited to a perfect circle.
  • Each layer constituting the semiconductor device of this embodiment may have a single layer structure or a stacked structure.
  • FIGS. 1B and 1C show an example in which the conductive layer 115 and the conductive layer 120 each have a single layer structure.
  • FIGS. 3A and 3B show an example in which the conductive layer 115 and the conductive layer 120 each have a stacked structure.
  • the insulating layer 130 is made of a material that can have ferroelectric properties.
  • materials that can have ferroelectricity refers to a material that can have hysteresis characteristics in the relationship between the strength of the electric field (electric field strength) applied to the material and the magnitude of polarization, or a material in which polarization can occur spontaneously even in the absence of an external electric field (an electric field applied to the material from the outside). Therefore, materials that can have ferroelectricity include materials that have one or more of ferroelectricity, antiferroelectricity, and ferroelectricity.
  • a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer. Therefore, the insulating layer 130 may be read as a ferroelectric layer. Furthermore, in this specification, a device having such a ferroelectric layer may be referred to as a ferroelectric device.
  • Examples of materials that can have ferroelectricity include oxides having one or both of hafnium and zirconium.
  • oxides having one or both of hafnium and zirconium include hafnium oxide, zirconium oxide, and hafnium zirconium oxide.
  • materials that can have ferroelectricity include materials obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set, and for example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include materials obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be appropriately set, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x (X is a real number greater than 0)), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 having a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulating layer can have a laminated structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • the insulating layer 130 it is preferable to use an oxide containing one or both of hafnium and zirconium, and it is more preferable to use hafnium zirconium oxide.
  • hafnium zirconium oxide is used as the insulating layer 130, the insulating layer 130 contains hafnium, zirconium, and oxygen.
  • hafnium oxide which is one of the materials that can be used for the insulating layer 130.
  • hafnium oxide is known to have various crystal structures. For example, it can have crystal structures such as monoclinic (space group: P21 /c), orthorhombic (space group: Pbca or Pca21 ), tetragonal (space group: P42 /nmc), and cubic (space group: Fm-3m) (see FIG. 8).
  • each of the above crystal structures can undergo phase change. The same is true for hafnium zirconium oxide.
  • hafnium zirconium oxide the monoclinic, tetragonal, and cubic crystal structures have an inversion center. Therefore, hafnium oxide containing crystals having these crystal structures is a paraelectric substance that does not have remanent polarization.
  • the orthorhombic crystal structure having a space group of Pca2 1 does not have a central symmetry. Therefore, in the orthorhombic crystal structure having a space group of Pca2 1 , oxygen is displaced by an external electric field, so that ferroelectricity is expressed in hafnium oxide containing crystals having an orthorhombic crystal structure having a space group of Pca2 1 .
  • the expression of ferroelectricity depends on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulating layer 130 to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer 130 to contain crystals having an orthorhombic crystal structure with a space group of Pca2 1 , since ferroelectricity is exhibited. In addition, by increasing the proportion of crystals having an orthorhombic crystal structure in the insulating layer 130, the remanent polarization can be increased.
  • crystals having a monoclinic, tetragonal, or cubic crystal structure are stable at normal pressure, while crystals having an orthorhombic crystal structure are metastable at normal pressure. Therefore, it is presumed that crystals having a monoclinic, tetragonal, or cubic crystal structure are unlikely to undergo a phase transition to an orthorhombic crystal structure even when subjected to heat treatment or the like.
  • crystals that are stable at normal pressure may be referred to as a stable phase
  • crystals that are metastable at normal pressure may be referred to as a metastable phase.
  • the insulating layer 130 has a high content of metastable phases. It is also preferable that the insulating layer 130 has a low content of stable phases. In other words, it is preferable that the insulating layer 130 has a high content of crystals having an orthorhombic crystal structure and a low content of crystals having a monoclinic, tetragonal, or cubic crystal structure. For example, it is preferable that the sum of the content of crystals having a monoclinic crystal structure, the content of crystals having a tetragonal crystal structure, and the content of crystals having a cubic crystal structure is low.
  • the content of crystals having a monoclinic crystal structure, the content of crystals having a tetragonal crystal structure, and the content of crystals having a cubic crystal structure are each low.
  • the crystal structure of the crystals contained in the insulating layer 130 can be evaluated, for example, using X-ray diffraction (XRD: X-Ray Diffraction). Specifically, it can be evaluated using the XRD spectrum obtained by grazing-incidence X-ray diffraction (GIXRD) measurement.
  • GIXRD grazing-incidence X-ray diffraction
  • the GIXRD method is also called the thin film method or the Seemann-Bohlin method. In the following, the XRD spectrum obtained by GIXRD measurement may be simply referred to as the XRD spectrum.
  • a peak refers to a convex shape that appears in an XRD spectrum. Note that one peak may be formed by overlapping multiple peaks. Furthermore, peak intensity refers to the maximum value of a convex shape (peak) that appears in an XRD spectrum. Furthermore, peak position refers to the value of the X-ray diffraction angle (2 ⁇ ) at the maximum value of a convex shape (peak) that appears in an XRD spectrum.
  • hafnium zirconium oxide contains crystals having an orthorhombic, tetragonal, or cubic crystal structure
  • hafnium zirconium oxide contains crystals having a monoclinic crystal structure
  • the vicinity of a specific angle A in the XRD spectrum refers to the range from A-0.5° to A+0.5°.
  • the first peak is detected, and the second and third peaks are not detected, in the analysis of the insulating layer 130 by X-ray diffraction.
  • first peak and the second peak may overlap.
  • first peak and the third peak may overlap.
  • the XRD spectrum can be subjected to waveform separation to calculate the intensity of each peak.
  • the intensity of each peak can be calculated by fitting the actually measured XRD spectrum with a composite spectrum of peaks set for each crystal structure.
  • the crystal content in the insulating layer 130 can be evaluated using electron diffraction (ED) mapping using a high-resolution transmission electron microscope (TEM).
  • ED electron diffraction
  • an element that increases the oxygen vacancy concentration in the oxide is added to an oxide having one or both of hafnium and zirconium.
  • examples of such elements include Group 3 elements (also called Group IIIa elements) in the periodic table.
  • the Group 3 elements in the periodic table added to the oxide are more preferably one or more selected from scandium, lanthanum, and yttrium, and even more preferably one or both of lanthanum and yttrium. In this specification and the like, the Group 3 elements in the periodic table may be simply called Group 3 elements.
  • hafnium and zirconium tend to have a valence of +4.
  • Group 3 elements tend to have a valence of +3. Therefore, by adding an element with a different valence from hafnium and zirconium to an oxide containing either or both of hafnium and zirconium, the concentration of oxygen vacancies in the oxide can be increased.
  • the grain size of the crystals contained in the oxide By reducing the grain size of the crystals contained in the oxide and reducing the grain size variation, the dielectric breakdown voltage of the oxide increases, making it possible to achieve high voltage resistance. Also, it is possible to reduce the amount of leakage current.
  • the oxide may be more likely to produce crystals having an orthorhombic crystal structure than crystals having a monoclinic crystal structure. This is presumably due to the addition of an element with an ionic radius larger than those of hafnium and zirconium. From this point of view, lanthanum and yttrium are particularly preferable as the Group 3 element to be added to the above oxide.
  • the content of Group 3 element added to the oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%.
  • the content of Group 3 element refers to the ratio of the number of atoms of Group 3 element to the sum of the number of atoms of all metal elements contained in the ferroelectric layer.
  • the insulating layer 130 preferably contains one or both of hafnium and zirconium, at least one Group 3 element, and oxygen, more preferably contains hafnium, zirconium, at least one Group 3 element, and oxygen, and even more preferably contains hafnium, zirconium, one or both of lanthanum and yttrium, and oxygen.
  • the insulating layer 130 preferably uses an oxide containing one or both of hafnium and zirconium to which at least one Group 3 element has been added, more preferably uses hafnium zirconium oxide to which at least one Group 3 element has been added, and even more preferably uses hafnium zirconium oxide to which one or both of lanthanum and yttrium have been added.
  • the content of at least one of the group 3 elements in the insulating layer 130 is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%.
  • the content of lanthanum in the insulating layer 130 is preferably in the above range.
  • the sum of the lanthanum content and the yttrium content in the insulating layer 130 is preferably in the above range.
  • an oxide having one or both of hafnium and zirconium may be formed, followed by forming an oxide having at least one Group 3 element, and then performing a heat treatment to form an oxide having one or both of hafnium and zirconium and at least one Group 3 element.
  • an oxide having at least one Group 3 element may be formed, followed by forming an oxide having one or both of hafnium and zirconium, and then performing a heat treatment to form an oxide having one or both of hafnium and zirconium and at least one Group 3 element.
  • an oxide containing one or both of hafnium and zirconium may be formed, and a treatment for adding a Group 3 element may be performed to form an oxide containing one or both of hafnium and zirconium and at least one Group 3 element.
  • oxygen vacancies may be formed in the oxide containing one or both of hafnium and zirconium during the treatment for adding the Group 3 element.
  • the addition of the Group 3 element can promote an increase in the concentration of oxygen vacancies in the oxide.
  • the treatment for adding the Group 3 element can be performed, for example, by ion doping or ion implantation.
  • the insulating layer 130 may be a single layer or a multilayer of the insulating material described in the section [Insulating layer] below.
  • an inorganic insulating film for each of the insulating layers (insulating layer 140, insulating layer 180, etc.) of the semiconductor device.
  • the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film.
  • oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • nitride insulating film examples include a silicon nitride film and an aluminum nitride film.
  • Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film.
  • Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film.
  • An organic insulating film may be used for the insulating layer of the semiconductor device.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the insulating layer of the semiconductor device may be made of the above-mentioned material that may have ferroelectricity.
  • the insulating layer of the semiconductor device may be made of the insulating material described in the [Insulating Layer] of the second embodiment described later.
  • insulating layer 140 and insulating layer 180 function as interlayer films, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring can be reduced. Silicon oxide and silicon oxynitride are thermally stable, and therefore are suitable for insulating layer 140 and insulating layer 180, respectively.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc.
  • a nitride of the alloy or an oxide of the alloy may be used.
  • a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide.
  • ITO indium oxide containing titanium oxide
  • ITSO indium tin oxide containing silicon
  • IZO indium zinc oxide
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • Conductive materials based on tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • the conductive layer 115 it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • titanium nitride or tantalum nitride can be used.
  • the conductive layer 115 contains titanium and nitrogen.
  • the conductive layer 115 is preferably made of a conductive material having a function of absorbing oxygen. Since the conductive layer 115 is in contact with the insulating layer 130, the conductive layer 115 can absorb oxygen from the insulating layer 130 and increase the oxygen vacancy concentration in the insulating layer 130 by using a conductive material having a function of absorbing oxygen as the conductive layer 115. Therefore, the residual polarization can be increased.
  • conductive materials having a function of absorbing oxygen include metal elements, alloys containing metal elements, and alloys combining metal elements. In addition, oxides of the alloys may be used as alloys containing the above-mentioned metal elements. Specific examples include tungsten, molybdenum, ruthenium, titanium, and tantalum. These conductive materials are also conductive materials that do not contain nitrogen. In this specification, etc., a conductive material that does not contain nitrogen refers to a conductive material with a nitrogen concentration of 1 atomic % or less.
  • tungsten is a conductive material with high conductivity and can be suitably used for the conductive layer 115.
  • ruthenium is suitable for use for the conductive layer 115 because its oxide also has conductivity. Therefore, it is preferable to use tungsten or ruthenium for the conductive layer 115.
  • the conductive layer 115 contains tungsten.
  • the oxygen vacancy concentration in the insulating layer 130 has a gradient in the direction from the conductive layer 115 toward the sidewall or bottom surface of the opening 190. In other words, it can be said that the direction in which oxygen vacancies are generated is the same as the direction from the conductive layer 115 toward the sidewall or bottom surface of the opening 190.
  • a layer 118 may be formed between the conductive layer 115 and the insulating layer 130 as shown in Figures 2A and 2B.
  • the metal contained in the conductive layer 115 is metal MX
  • the layer 118 contains metal MX and oxygen.
  • the oxygen concentration of the layer 118 is higher than the oxygen concentration of the conductive layer 115.
  • the concentration of metal MX in the layer 118 is lower than the concentration of metal MX in the conductive layer 115.
  • capacitive element 100 When layer 118 is formed between conductive layer 115 and insulating layer 130, capacitive element 100 has conductive layer 115, layer 118 on conductive layer 115, insulating layer 130 on layer 118, and conductive layer 120 on insulating layer 130.
  • the layer 118 may be conductive or insulating.
  • the layer 118 When the layer 118 is conductive, the layer 118 has a region that functions as the other of the pair of electrodes of the capacitor 100.
  • the layer 118 When the layer 118 is insulating, the physical distance between the conductive layer 115 and the conductive layer 120 can be increased, and the parasitic capacitance generated between the conductive layer 115 and the conductive layer 120 can be reduced.
  • Figures 3A and 3B show an example in which the conductive layer 115 has a two-layer structure of a conductive layer 115a and a conductive layer 115b on the conductive layer 115a.
  • tungsten can be used for the conductive layer 115a
  • titanium nitride or tantalum nitride can be used for the conductive layer 115b.
  • the titanium nitride or tantalum nitride is in contact with the insulating layer 130.
  • one or both of the conductive layer 115a and the conductive layer 115b may have a stacked structure.
  • the conductive layer 115a has a two-layer structure of a first conductive layer and a second conductive layer on the first conductive layer
  • titanium nitride or tantalum nitride can be used for each of the first conductive layer of the conductive layer 115a and the conductive layer 115b
  • tungsten can be used for the second conductive layer of the conductive layer 115a.
  • the insulating layer 130 can prevent the conductive layer 115 from being oxidized.
  • the insulating layer 180 can prevent the conductive layer 115 from being oxidized.
  • the conductive layer 120 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • titanium nitride or tantalum nitride can be used.
  • the conductive layer 120 contains titanium and nitrogen.
  • the conductive layer 120 is preferably made of a conductive material that has the function of absorbing oxygen. Since the conductive layer 120 is in contact with the insulating layer 130, by using a conductive material that has the function of absorbing oxygen as the conductive layer 120, oxygen can be absorbed from the insulating layer 130, and the concentration of oxygen vacancies in the insulating layer 130 can be increased. Therefore, the residual polarization can be increased.
  • the conductive layer 120 is preferably made of the above-mentioned conductive material that does not contain nitrogen, and more preferably made of tungsten.
  • the oxygen vacancy concentration in the insulating layer 130 has a gradient in the direction from the lower surface of the conductive layer 120 to the upper surface of the conductive layer 120. In other words, it can be said that the direction in which oxygen vacancies are generated is the same as the direction from the lower surface of the conductive layer 120 to the upper surface of the conductive layer 120.
  • a layer 128 may be formed between the insulating layer 130 and the conductive layer 120, as shown in Figures 2C and 2D.
  • the layer 128 contains metal MY and oxygen.
  • the oxygen concentration of the layer 128 is higher than the oxygen concentration of the conductive layer 120.
  • the concentration of metal MY in the layer 128 is lower than the concentration of metal MY in the conductive layer 120.
  • capacitive element 100 When layer 128 is formed between insulating layer 130 and conductive layer 120, capacitive element 100 has conductive layer 115, insulating layer 130 on conductive layer 115, layer 128 on insulating layer 130, and conductive layer 120 on layer 128.
  • the layer 128 may be conductive or insulating.
  • the layer 128 When the layer 128 is conductive, the layer 128 has a region that functions as one of a pair of electrodes of the capacitor 100.
  • the layer 128 When the layer 128 is insulating, the physical distance between the conductive layer 115 and the conductive layer 120 can be increased, and the parasitic capacitance generated between the conductive layer 115 and the conductive layer 120 can be reduced.
  • 3A and 3B show an example in which the conductive layer 120 has a two-layer structure of a conductive layer 120a and a conductive layer 120b on the conductive layer 120a.
  • the conductive layer 120a is provided so as to fill a recess in the insulating layer 130
  • the conductive layer 120b is provided so that its lower surface is located above the upper surface of the insulating layer 180 or the insulating layer 130, as shown in FIG. 3C and FIG. 3D.
  • titanium nitride or tantalum nitride for the conductive layer 120a and tungsten for the conductive layer 120b.
  • the titanium nitride or tantalum nitride is in contact with the insulating layer 130.
  • an oxide insulator is used for the insulating layer 130, it is possible to prevent the conductive layer 120 from being oxidized by the insulating layer 130.
  • tungsten for the conductive layer 120a and titanium nitride or tantalum nitride for the conductive layer 120b.
  • oxygen is absorbed from the insulating layer 130, increasing the concentration of oxygen vacancies in the insulating layer 130, thereby increasing the remanent polarization.
  • one or both of the conductive layer 120a and the conductive layer 120b may have a laminated structure.
  • the conductive layer 120a has a two-layer structure of a first conductive layer and a second conductive layer on the first conductive layer, it is possible to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen for the first conductive layer of the conductive layer 120a, a material with high conductivity for the second conductive layer of the conductive layer 120a, and a conductive material containing oxygen for the conductive layer 120b.
  • titanium nitride or tantalum nitride for the first conductive layer of the conductive layer 120a, tungsten for the second conductive layer of the conductive layer 120a, and ITSO for the conductive layer 120b.
  • titanium nitride or tantalum nitride for the first conductive layer of the conductive layer 120a
  • tungsten for the second conductive layer of the conductive layer 120a
  • ITSO for the conductive layer 120b.
  • a layer 118 may be formed between the conductive layer 115 and the insulating layer 130, and a layer 128 may be formed between the insulating layer 130 and the conductive layer 120.
  • the capacitance element 100 has the conductive layer 115, the layer 118 on the conductive layer 115, the insulating layer 130 on the layer 118, the layer 128 on the insulating layer 130, and the conductive layer 120 on the layer 128.
  • a conductive material with high conductivity such as tungsten, can be used as the conductive layer 110.
  • a conductive material with high conductivity such as tungsten
  • the conductivity of the conductive layer 110 can be improved and the conductive layer 110 can function sufficiently as a wiring.
  • the conductive layer 110 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a stacked layer.
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen, in a single layer or a stacked layer.
  • titanium nitride or ITSO may be used.
  • a structure in which titanium nitride is stacked on tungsten may be used.
  • a structure in which tungsten is stacked on a first titanium nitride, and a second titanium nitride is stacked on the tungsten may be used.
  • an insulating substrate As a substrate for forming the semiconductor device according to one embodiment of the present invention, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide.
  • Examples of the semiconductor substrate include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Examples of the conductive substrate include a substrate having a metal nitride and a substrate having a metal oxide.
  • Examples of the conductive substrate include a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or an insulator is provided on a conductive substrate.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Figure 4A is a plan view of the semiconductor device.
  • Figure 4B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 4A as viewed from the Y direction.
  • Figure 4C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 4A as viewed from the X direction. Note that some elements are omitted from the plan view of Figure 4A for clarity.
  • the shape of the conductive layer 115 of the semiconductor device shown in Figures 4A to 4C is different from the shape of the conductive layer 115 of the semiconductor device shown in Figures 1A to 1C.
  • differences from the content explained using Figures 1A to 1C will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the conductive layer 115 does not contact the upper surface of the insulating layer 180.
  • the height of the upper surface of the conductive layer 115 is the same as the height of the upper surface of the insulating layer 180.
  • a conductive layer 115 may be provided so as to fill the opening 190.
  • the height of the upper surface of the conductive layer 115 is the same as the height of the upper surface of the insulating layer 180.
  • the insulating layer 130 and the conductive layer 120 can be formed on a substrate having a flat upper surface. Therefore, the formation of the insulating layer 130 and the conductive layer 120 is not limited to a film formation method having good coverage.
  • a semiconductor device can be manufactured with high productivity by forming one or both of the insulating film to be the insulating layer 130 and the conductive film to be the conductive layer 120 using a sputtering method having a high film formation rate.
  • the insulating layer 130 can be formed flat.
  • the insulating layer 130 can be configured not to cover the corners of the upper surface of the conductive layer 115. Therefore, electric field concentration on the insulating layer 130 can be suppressed. This makes it possible to suppress dielectric breakdown of the insulating layer 130 and provide a highly reliable semiconductor device.
  • Figures 5B and 5C are cross-sectional views of the semiconductor device, and Figure 5A is a plan view of the semiconductor device.
  • the opening 190 is a rectangle with rounded corners in a plan view.
  • the capacitance of the capacitance element 100 can be increased compared to when the opening 190 is circular in a plan view.
  • the opening 190 may be approximately circular or polygonal in a plan view.
  • FIG. 6A A manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 6A to Fig. 7D.
  • Fig. 6A, Fig. 6C, Fig. 6E, Fig. 7A, and Fig. 7C are cross-sectional views of the semiconductor device as viewed from the X direction
  • Fig. 6B, Fig. 6D, Fig. 6F, Fig. 7B, and Fig. 7D are cross-sectional views of the semiconductor device as viewed from the Y direction. Note that the description of the materials and formation methods of each element may be omitted for parts that are similar to those described above.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD).
  • CVD chemical vapor deposition
  • MBE molecular beam epitaxy
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner.
  • RF sputtering is mainly used when depositing insulating films
  • DC sputtering is mainly used when depositing metal conductive films.
  • Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.
  • CVD methods can also be classified into plasma CVD (PECVD) methods, which use plasma, thermal CVD (TCVD: Thermal CVD) methods, which use heat, and photo CVD (Photo CVD) methods, which use light. They can also be further classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal CVD) methods, depending on the source gas used.
  • PECVD plasma CVD
  • TCVD Thermal CVD
  • Photo CVD Photo CVD
  • MCVD Metal CVD
  • MOCVD Metal CVD
  • the plasma CVD method can produce high-quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma.
  • wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. At this time, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device.
  • thermal CVD method which does not use plasma, such plasma damage does not occur, so the yield of semiconductor devices can be increased.
  • plasma damage does not occur during film formation, so a film with fewer defects can be obtained.
  • the ALD method can be a thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy, or a PEALD method in which a plasma-excited reactant is used.
  • the CVD and ALD methods are different from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surfaces of openings with high aspect ratios.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.
  • the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases.
  • the CVD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors.
  • a film of any composition can be formed by controlling the number of cycles of each precursor.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film when processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Dry etching, wet etching, sandblasting, etc. can be used to etch thin films.
  • a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used as the dry etching apparatus.
  • the capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes.
  • a high-frequency voltage of the same frequency may be applied to each of the parallel plate electrodes.
  • a configuration may be used in which multiple different high-frequency voltages are applied to the parallel plate electrodes.
  • Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus.
  • DF-CCP dual-frequency capacitively coupled plasma
  • a configuration may be used in which multiple high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes.
  • a configuration may be used in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes.
  • a dry etching apparatus having a high-density plasma source can be used.
  • ICP inductively coupled plasma
  • the etching apparatus can be set appropriately according to the object to be etched.
  • reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side in the above-mentioned dry etching apparatus to generate a self-bias potential.
  • reactive ion etching etching is performed by accelerating ion species in the plasma and colliding them with the workpiece, so that highly anisotropic etching can be performed.
  • a substrate (not shown) is prepared, and an insulating layer 140 is formed on the substrate (see FIGS. 6A and 6B).
  • the insulating layer 140 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • the conductive layer 110 is formed on the insulating layer 140 (see FIG. 6A and FIG. 6B).
  • the conductive layer 110 can be formed by forming a conductive film on the insulating layer 140 and patterning the conductive film by a lithography method.
  • the conductive film can be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating layer 180 is formed on the insulating layer 140 and the conductive layer 110.
  • the insulating layer 180 may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate. Note that it is preferable to perform a CMP process after the insulating layer 180 is formed to planarize the upper surface. By performing the planarization process on the insulating layer 180, the conductive layer 115 can be suitably formed.
  • the upper surface of the insulating layer 180 has an upwardly convex curved shape.
  • the opening 190 may be formed by lithography.
  • the opening 190 may be formed by dry etching or wet etching. Dry etching is suitable for forming an opening 190 with a high aspect ratio because it allows anisotropic etching. However, the opening 190 may also be formed by appropriately using dry etching and wet etching.
  • a conductive film 115F is formed in contact with the upper surface of the conductive layer 110, the side surface of the insulating layer 180, and part of the upper surface of the insulating layer 180 (see Figures 6C and 6D).
  • the conductive film 115F is a film that will become the conductive layer 115 in a later process.
  • the conductive film 115F can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • At least a portion of the conductive film 115F is deposited in the opening 190 with a large aspect ratio. Therefore, it is preferable to deposit the conductive film 115F using a deposition method with good coverage. For example, it is preferable to deposit the conductive film 115F using an ALD method, a CVD method, or the like, and it is more preferable to deposit the conductive film 115F using a metal CVD method.
  • the conductive film 115F is processed by lithography to form the conductive layer 115 (see FIG. 6E and FIG. 6F).
  • the conductive film 115F can be processed by dry etching or wet etching. Dry etching is suitable for fine processing.
  • the conductive layer 115 is formed so as to contact the sidewall and bottom surface of the opening 190 and have a recess in the area overlapping with the opening 190. Note that when the conductive film 115F is processed, a part of the insulating layer 180 is processed, and the thickness of the insulating layer 180 in the area not overlapping with the conductive layer 115 may become thin.
  • an insulating film 130F is formed on the insulating layer 180 and the conductive layer 115 (see FIG. 6G and FIG. 6G).
  • the insulating film 130F is a film that will become the insulating layer 130 in a later process.
  • the insulating film 130F can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.
  • the insulating film 130F is preferably formed using the ALD method.
  • the insulating film 130F is preferably formed to a thin thickness, and it is necessary to make the variation in thickness small.
  • the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent, etc.) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so that precise film thickness adjustment is possible.
  • the ALD method can deposit atomic layers one by one on the bottom and side of the opening or recess, so that the insulating film 130F can be formed with good coverage on the recess of the conductive layer 115.
  • a film of any composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Therefore, an oxide in which at least one of the content rates of Group 3 elements is within the above range can be formed.
  • a precursor containing hafnium, a precursor containing zirconium, and an oxidizing agent can be used.
  • the precursor containing hafnium tetrakis(ethylmethylamido)hafnium (TEMAHf), HfCl4 , etc. can be used.
  • the precursor containing zirconium tetrakis(ethylmethylamido)zirconium (TEMAZr), ZrCl4 , etc. can be used.
  • the oxidizing agent any one or more selected from O2 , O3 , N2O , NO2 , H2O , and H2O2 can be used.
  • the insulating film 130F may not have crystallinity immediately after the insulating film 130F is formed.
  • the surface of the conductive layer 115 may be oxidized by the oxidizing agent, forming the layer 118 shown in FIG. 2A, etc.
  • the insulating film 130F is formed along the recesses in the conductive layer 115.
  • the insulating film 130F also has recesses in the areas that overlap with the recesses in the conductive layer 115.
  • an RTA Rapid Thermal Anneal
  • a resistance heating furnace or a microwave heating device
  • the use of an RTA device is preferable because it may improve the ferroelectricity of the insulating film 130F that becomes the insulating layer 130.
  • an LRTA Low Rapid Thermal Anneal
  • GRTA Gas Rapid Thermal Anneal
  • the LRTA device is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.
  • the GRTA device is a device that performs heat treatment using high-temperature gas.
  • the gas used is an inert gas such as argon or nitrogen that does not react with the workpiece during heat treatment. Note that the method of performing heat treatment using an LRTA device is sometimes called the lamp-based RTA method or the LRTA method.
  • the treatment temperature is preferably 300°C or more and 700°C or less, more preferably 400°C or more and 600°C or less, and even more preferably 400°C or more and 500°C or less.
  • the treatment time is preferably 5 seconds or more and 1 hour or less, more preferably 5 seconds or more and 5 minutes or less, and even more preferably 1 minute or more and 5 minutes or less.
  • the heat treatment is performed in a nitrogen atmosphere at 450°C for 1 minute using an LRTA device.
  • the heat treatment may be performed after the formation of the insulating film 130F, and does not have to be performed immediately after the formation of the insulating film 130F.
  • the heat treatment may be performed after the formation of the conductive film 120F, after the formation of the conductive layer 120, and after the formation of the insulating layer 130, as described below.
  • the heat treatment may be performed multiple times instead of once.
  • the LRTA atmosphere may be an inert gas atmosphere such as Ar or He, other than a nitrogen atmosphere.
  • the heat treatment may be performed using an annealing furnace instead of an LRTA.
  • the above heat treatment may oxidize the surface of the conductive layer 115, forming layer 118 as shown in FIG. 2A, etc. Furthermore, if the above heat treatment is performed after the formation of the conductive film 120F, the bottom surface of the conductive film 120F may be oxidized, forming a film that becomes layer 128 as shown in FIG. 2C, etc.
  • a conductive film 120F is formed on the insulating film 130F (see FIGS. 6G and 6H).
  • the conductive film 120F is formed so as to fill the recesses of the insulating film 130F.
  • the conductive film 120F is a film that will become the conductive layer 120 in a later process.
  • the conductive film 120F can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.
  • At least a portion of the conductive film 120F is deposited in a recess in the insulating layer 130. Because the recess has a large aspect ratio, it is preferable to deposit the conductive film 120F using a deposition method with good coverage. For example, it is preferable to deposit the conductive film 120F using an ALD method, a CVD method, or the like, and it is more preferable to deposit the conductive film 120F using a metal CVD method.
  • the substrate temperature is high when the conductive film 120F is formed, a stable phase may be formed in the insulating film 130F due to the influence of heat, and the insulating layer 130 formed later may not exhibit ferroelectricity. Therefore, it is preferable that the substrate temperature is low when the conductive film 120F is formed. On the other hand, if the substrate temperature is too low, the adsorption reaction of the raw material gas does not occur, and the film is not formed. Therefore, for example, the temperature when the conductive film 120F is formed is preferably from room temperature to 325°C, and more preferably from 250°C to 325°C. In this way, by forming the conductive film 120F at a low substrate temperature, it is possible to suppress the formation of a stable phase in the insulating film 130F.
  • the insulating film 130F is not affected by the heat during the formation of the conductive film 115F. Therefore, the substrate temperature during the formation of the conductive film 115F can be made high. For example, the substrate temperature during the formation of the conductive film 115F can be made higher than the substrate temperature during the formation of the conductive film 120F. By increasing the substrate temperature during the formation of the conductive film 115F, the resistivity of the conductive film 115F can be reduced. In addition, the hydrogen concentration in the conductive film 115F can be reduced.
  • the temperature during the formation of the conductive film 115F is preferably greater than 325°C and less than 700°C, more preferably greater than 350°C and less than 500°C, and even more preferably greater than 400°C and less than 450°C.
  • the conductive film 120F and the insulating film 130F are processed by lithography to form the conductive layer 120 and the insulating layer 130 (see FIG. 1B and FIG. 1C).
  • the conductive film 120F and the insulating film 130F can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing.
  • the conductive film 120F and the insulating film 130F may be processed under different conditions. Note that when the conductive film 120F and the insulating film 130F are processed, a part of the insulating layer 180 may be processed, and the thickness of the insulating layer 180 in the region that does not overlap with the conductive layer 120 and the insulating layer 130 may become thin.
  • the semiconductor device shown in Figures 1A to 1C can be manufactured.
  • a sacrificial layer is formed so as to fill the opening 190.
  • the sacrificial layer can be made of a material that will be removed in a later process. Note that the sacrificial layer may be made of a conductive material, a semiconductor material, or an insulating material.
  • a planarization process is performed to expose the upper surface of the insulating layer 180, and to planarize the upper surfaces of the sacrificial layer, the conductive layer 115, and the insulating layer 180.
  • the height of the upper surface of the conductive layer 115 coincides with the height of the upper surface of the insulating layer 180.
  • CMP process is suitable as the planarization process.
  • the planarization process at least a portion of the sacrificial layer and the conductive layer 115 are removed. Note that a portion of the insulating layer 180 may be removed by the planarization process.
  • the sacrificial layer is removed to expose the recesses in the conductive layer 115 (see FIGS. 7A and 7B).
  • the sacrificial layer can be removed by dry etching or wet etching. When removing the sacrificial layer, it is preferable to use etching conditions that provide a high selectivity between the sacrificial layer and the conductive layer 115 so that the conductive layer 115 is not removed.
  • an insulating film 130F is formed on the insulating layer 180 and the conductive layer 115, and a conductive film 120F is formed on the insulating film 130F (see FIGS. 7C and 7D). Note that the method for forming the insulating film 130F and the conductive film 120F can be seen in the description of FIGS. 6G to 6H.
  • the conductive film 120F and the insulating film 130F are then processed using lithography to form the conductive layer 120 and the insulating layer 130 (see FIGS. 4B and 4C).
  • the processing method for the conductive film 120F and the insulating film 130F can be seen from the above.
  • the semiconductor device shown in Figures 4A to 4C can be manufactured.
  • the semiconductor device according to one embodiment of the present invention includes a memory cell.
  • the memory cell includes a transistor and a capacitor.
  • Fig. 9A is a plan view of a semiconductor device having a transistor 200A and a capacitor 100.
  • Fig. 9B is a cross-sectional view taken along dashed line A1-A2 in Fig. 9A.
  • Fig. 9C is a cross-sectional view taken along dashed line A3-A4 in Fig. 9A.
  • 9A to 9C includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a memory cell 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 283, an insulating layer 285, and a conductive layer 265 on the insulating layer 285.
  • the insulating layer 140, the insulating layer 180, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer films.
  • the conductive layer 110 and the conductive layer 265 function as wirings.
  • the memory cell 150 has a capacitance element 100 on a conductive layer 110 and a transistor 200A on the capacitance element 100.
  • an insulating layer 280 is disposed on the capacitive element 100, and a transistor 200A is disposed on the insulating layer 280.
  • the insulating layer 280 has a portion located on the insulating layer 180 and a portion located on the conductive layer 120b.
  • Transistor 200A has a conductive layer 120, a conductive layer 240 on insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on oxide semiconductor layer 230, and a conductive layer 260 on insulating layer 250.
  • Conductive layer 120 has conductive layer 120a and conductive layer 120b on conductive layer 120a.
  • Conductive layer 240 has conductive layer 240a and conductive layer 240b on conductive layer 240a.
  • the oxide semiconductor layer 230 functions as a semiconductor layer
  • the conductive layer 260 functions as a gate electrode
  • the insulating layer 250 functions as a gate insulating layer
  • the conductive layer 120 functions as one of the source electrode and the drain electrode
  • the conductive layer 240 functions as the other of the source electrode and the drain electrode.
  • the conductive layer 265 functions as a gate wiring.
  • At least a part of the region of the oxide semiconductor layer 230 in contact with the insulating layer 280 functions as a channel formation region of the transistor 200A.
  • One of the region of the oxide semiconductor layer 230 in contact with the conductive layer 120 and the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.
  • transistor 200A the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction)
  • transistor 200A can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • a vertical transistor is suitable for memory cell 150.
  • a vertical transistor can have a source electrode, a semiconductor layer, and a drain electrode stacked on top of each other, so the area it occupies can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a flat plane.
  • the transistor 200A is provided so as to overlap with the capacitor 100.
  • the opening 290 and the opening 270 in which part of the structure of the transistor 200A is provided have an area overlapping with the opening 190 in which part of the structure of the capacitor 100 is provided.
  • the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200A and as the upper electrode of the capacitor 100, so that the transistor 200A and the capacitor 100 share part of the structure.
  • the transistor 200A and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This allows the occupied area of the memory cell 150 to be reduced, so that the memory cell 150 can be arranged at a high density and the memory capacity of the memory device can be increased.
  • the memory device can be highly integrated.
  • FIGS. 9B and 9C an example is shown in which the width of the opening 190 is smaller than the width of the opening 290 and the width of the opening 270.
  • the width of opening 190 is the same as or smaller than the width of opening 290.
  • the width of opening 190 is the same as or smaller than the width of opening 270.
  • the transistor 200A is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, in the transistor 200A, it is possible to suppress deterioration of electrical characteristics such as fluctuations in threshold voltage and increases in parasitic resistance, as well as increases in variations in electrical characteristics due to deterioration of electrical characteristics.
  • the capacitance of the capacitance element 100 can be increased by increasing the depth of the opening 190. Increasing the capacitance per unit area of the capacitance element 100 in this manner can stabilize the read operation of the memory device. In addition, miniaturization or high integration of the memory device can be promoted.
  • transistor 200A Next, we will explain the details of transistor 200A.
  • the insulating layer 280 and the conductive layer 240 have an opening 290 that reaches the conductive layer 120b.
  • the opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240.
  • the opening in the region where the insulating layer 280 overlaps with the conductive layer 120b is a part of the opening 290
  • the opening in the region where the conductive layer 240 overlaps with the conductive layer 120b is another part of the opening 290.
  • the sidewall of the opening 290 includes the side surface of the insulating layer 280 and the side surface of the conductive layer 240.
  • the shape and size of the opening 290 in a plan view may differ depending on each layer. In addition, when the top surface shape of the opening 290 is circular, the openings in each layer may be concentric or not concentric.
  • a recess is provided in the conductive layer 120b.
  • the opening 290 can be said to be an opening that reaches the bottom surface of the recess in the conductive layer 120b.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located in the opening 290.
  • the oxide semiconductor layer 230 contacts the upper surface and side surface (which may also be called the bottom surface and side surface of the recess) of the conductive layer 120b through the opening 290, and contacts the side surface of the insulating layer 280, the side surface of the conductive layer 240a, and the upper surface and side surface of the conductive layer 240b in the opening 290.
  • the upper surface of the conductive layer 120b has an area that contacts at least a part of the bottom surface of the oxide semiconductor layer 230.
  • the insulating layer 250 is located inside the oxide semiconductor layer 230 in the opening 290
  • the conductive layer 260 is located inside the insulating layer 250 in the opening 290.
  • the portions of the oxide semiconductor layer 230 and the insulating layer 250 that are disposed within the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor layer 230 is provided to cover the bottom and sidewalls of the opening 290
  • the insulating layer 250 is provided to cover the oxide semiconductor layer 230.
  • the conductive layer 260 is provided to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 290.
  • the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be made lower than the height of the top surface of the conductive layer 120b that contacts the insulating layer 280, based on the top surface of the insulating layer 140, compared to when the conductive layer 120b does not have the recess.
  • the height of each surface can be determined based on the surface on which the memory cell or transistor is formed.
  • the top surface of the insulating layer 140 is used as the reference.
  • the surface used as the reference is not particularly limited, and may be, for example, the top surface of the substrate on which the transistor or semiconductor device is provided.
  • This increases the contact area between the side surface of the conductive layer 120b and the oxide semiconductor layer 230, and reduces the contact resistance between the conductive layer 120b and the oxide semiconductor layer 230. This makes it possible to suppress a decrease in the on-current of the transistor 200A caused by the contact resistance between the conductive layer 120b and the oxide semiconductor layer 230.
  • a gate electric field is easily applied to the channel formation region of the oxide semiconductor layer 230, which can improve the electrical characteristics of the transistor 200A. Furthermore, a gate electric field is easily applied to the region of the oxide semiconductor layer 230 in contact with the conductive layer 120b, which can increase the on-current of the transistor 200A. In addition, whether the conductive layer 120 or the conductive layer 240 is used for the drain electrode, the electrical characteristics of the transistor 200A can be improved.
  • a conductive material containing oxygen for the conductive layer 120b is preferable to use. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 120b.
  • a conductive material containing oxygen for the conductive layer 240a is preferable to use. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240a.
  • a conductive material containing oxygen is used for the layer closest to the channel formation region in the stacked structure, and the contact resistance with the oxide semiconductor layer 230 is reduced, whereby the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.
  • the conductive material containing oxygen it is preferable to use a metal oxide having conductivity (also referred to as an oxide conductor).
  • the insulating layer 283 is provided to cover the side surface of the conductive layer 240 and the top surface and side surface of the oxide semiconductor layer 230.
  • the insulating layer 283 has an opening 270 that reaches the oxide semiconductor layer 230 at a position overlapping with the opening 290. At least some of the components of the transistor 200A are disposed in the opening 270.
  • the insulating layer 250 and the conductive layer 260 are disposed such that at least some of them are located in the opening 270.
  • the insulating layer 250 contacts the oxide semiconductor layer 230 and the insulating layer 283 in the opening 270.
  • the portion of the insulating layer 250 that is disposed within the opening 270 is provided to reflect the shape of the opening 270.
  • the insulating layer 250 is provided so as to cover the sidewall of the opening 270 (the side surface of the insulating layer 283).
  • the conductive layer 260 is provided so as to fill at least a portion of the recess in the insulating layer 250 that reflects the shape of the opening 270.
  • the conductive layer 260 does not overlap the top surface of the conductive layer 240, so that the parasitic capacitance generated between the conductive layer 240 and the conductive layer 260 can be reduced.
  • the maximum width of the conductive layer 260 is smaller than the width of the opening 290. In this way, when the maximum width of the conductive layer 260 is smaller than the width of the opening 290, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Note that, for example, as shown in FIG. 9B or FIG. 9C, the magnitude relationship between the two widths in a semiconductor device according to one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.
  • the width of the opening 290 may vary in the depth direction.
  • the width of the opening 290 used here is the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view.
  • the minimum value of the width of the opening 290 in the conductive layer 240 is used as the width of the opening 290.
  • the width of the opening 270 is the same as the width of the opening 290.
  • the width of the opening 270 preferably does not exceed the sum of the width of the opening 290 and twice the thickness of the oxide semiconductor layer 230. This can prevent the insulating layer 283 and the insulating layer 285 from being located inside the opening 290.
  • the width of the opening 270 preferably does not exceed the sum of the width of the opening 290 and twice the thickness of the insulating layer 250.
  • it is more preferable that the width of the opening 270 is the same as or smaller than the width of the opening 290.
  • the conductive layer 260 does not overlap the upper surface of the conductive layer 240 is mainly shown, but the conductive layer 260 may have a portion overlapping the upper surface of the conductive layer 240. The smaller the overlapping portion, the smaller the parasitic capacitance that occurs between conductive layer 260 and conductive layer 240, which is preferable.
  • the width of the opening 270 may vary in the depth direction.
  • the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 283 in a cross-sectional view.
  • the height of the upper surface of the conductive layer 260 and the height of the upper surface of the insulating layer 285 are the same or approximately the same.
  • the conductive layer 265 is provided on the insulating layer 285, the insulating layer 283, and the conductive layer 260, and is in contact with the upper surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are electrically connected to each other.
  • the insulating layer 283 and the insulating layer 285 are located between the conductive layer 265 and the conductive layer 240. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance generated between the conductive layer 265 and the conductive layer 240.
  • the transistor 200A has a configuration in which the parasitic capacitance between the other of the source electrode and the drain electrode and the gate electrode, and the parasitic capacitance between the other of the source electrode and the drain electrode and the gate wiring are reduced. Therefore, the frequency characteristics of the circuit can be improved.
  • FIG. 9B shows a configuration in which the end of the conductive layer 240a, the end of the conductive layer 240b, and the end of the oxide semiconductor layer 230 are aligned outside the opening 290.
  • the conductive layer 240a, the conductive layer 240b, and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because it is possible to reduce the number of masks required to manufacture a semiconductor device. Note that the present invention is not limited to this. For example, in the X direction or Y direction, any of the end of the oxide semiconductor layer 230, the end of the conductive layer 240a, and the end of the conductive layer 240b may be located inside or outside the other end.
  • the conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 120.
  • the conductive layer 240 is not provided inside the opening 290 of the insulating layer 280.
  • the conductive layer 240 does not have a region in contact with the side of the insulating layer 280 in the opening 290.
  • the opening 290 can be formed in the conductive layer 240 and the insulating layer 280 at once.
  • the film thickness distribution of the oxide semiconductor layer 230 provided inside the opening 290 can be made uniform.
  • FIGS. 9B and 9C show a configuration in which the side of the conductive layer 240 in the opening 290 and the side of the insulating layer 280 in the opening 290 are aligned or approximately aligned, but the present invention is not limited to this.
  • the side of the conductive layer 240 in the opening 290 and the side of the insulating layer 280 in the opening 290 may be discontinuous.
  • the inclination of the side of the conductive layer 240 in the opening 290 and the inclination of the side of the insulating layer 280 in the opening 290 may be different from each other.
  • the taper angle of the side of the conductive layer 240 in the opening 290 is smaller than the taper angle of the side of the insulating layer 280 in the opening 290.
  • Transistor 200A has a metal oxide (also called an oxide semiconductor) that functions as a semiconductor in the oxide semiconductor layer 230 including the channel formation region.
  • transistor 200A can be said to be an OS transistor.
  • oxygen vacancies ( VO ) and impurities are present in a channel formation region in an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate and the reliability may be reduced. Furthermore, a defect in which hydrogen is introduced into an oxygen vacancy (hereinafter sometimes referred to as VOH ) may generate electrons that serve as carriers. For this reason, when an oxygen vacancy is present in a channel formation region in an oxide semiconductor, an OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the oxide semiconductor layer 230 is provided inside the opening 290 of the insulating layer 280.
  • the transistor 200A has a configuration in which one of the source electrode and the drain electrode (conductive layer 120 here) is located on the lower side and the other of the source electrode and the drain electrode (conductive layer 240 here) is located on the upper side, so that a current flows in the vertical direction. In other words, a channel is formed along the side surface of the opening 290 of the insulating layer 280.
  • the insulating layer 280 contacts the entire outer periphery of the oxide semiconductor layer 230. Therefore, the channel formation region of the transistor 200A can be formed on the entire outer periphery of the oxide semiconductor layer 230 within the opening 290 (the entire region in contact with the insulating layer 280).
  • the channel length of transistor 200A is the distance between the source region and the drain region. In other words, it can be said that the channel length of transistor 200A is determined by the thickness of insulating layer 280 on conductive layer 120. It can also be said that the channel length corresponds to the length of the side of insulating layer 280 on the opening 290 side.
  • the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult; however, in one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200A can be made into a very fine structure below the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200A, improving the frequency characteristics.
  • the exposure limit of photolithography e.g. 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the area occupied by the transistor 200A can be reduced compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 arranged at the center faces the side surface of the oxide semiconductor layer 230 through the insulating layer 250. That is, in a plan view, the entire circumference of the oxide semiconductor layer 230 becomes a channel formation region.
  • the channel width of the transistor 200A is determined by the outer periphery length of the oxide semiconductor layer 230.
  • the channel width of the transistor 200A is determined by the width of the opening 290 (the diameter when the opening 290 is circular in a plan view).
  • the width of the opening 290 is limited by the exposure limit of photolithography.
  • the width of the opening 290 is set by the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290.
  • the width of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width can be calculated as "D x ⁇ ".
  • the channel length of the transistor 200A is at least smaller than the channel width of the transistor 200A.
  • the channel length of the transistor 200A is preferably 0.1 times or more and 0.99 times or less, more preferably 0.5 times or more and 0.8 times or less, of the channel width of the transistor 200A.
  • the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.
  • the opening 290 and the opening 270 are circular in plan view, but the present invention is not limited to this.
  • the opening 290 and the opening 270 can be, for example, a circle, an approximately circular shape such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, or a star-shaped polygon, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • the opening 290 and the opening 270 are preferably circular. By making them circular, the processing accuracy when forming the openings can be improved, and openings of fine size can be formed.
  • Each layer constituting the semiconductor device of this embodiment may have a single layer structure or a multilayer structure.
  • the oxide semiconductor layer 230 has a channel formation region.
  • the channel formation region is i-type (intrinsic) or substantially i-type.
  • the oxide semiconductor layer 230 further has a source region and a drain region.
  • the source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.
  • the crystallinity of the semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of a metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the metal oxide preferably contains one or both of indium and zinc.
  • the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the oxide semiconductor layer 230 may be, for example, indium oxide (In oxide), IZO (registered trademark), ITO, indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also written as IGTO), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-A Indium tin zinc oxide (In-Sn-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table instead of or in addition to indium.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration may increase or the band gap may be narrowed, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • a metal oxide with a large band gap can be obtained.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained.
  • a shift in the threshold voltage of the transistor can be suppressed.
  • fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the oxide semiconductor layer 230. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is greater than or equal to the atomic ratio of M.
  • the term "nearby composition” includes
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the In-Zn oxide may also contain a trace amount of element M.
  • energy dispersive X-ray spectrometry EDX
  • XPS XPS
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. In addition, it may be difficult to quantify element M, or element M may not be detected.
  • the metal oxide can be formed by sputtering or ALD.
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the metal oxide may also be formed by CVD, MBE, PLD, or other methods.
  • the oxide semiconductor layer 230 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the oxide semiconductor layer 230 may have the same or approximately the same composition.
  • the two or more metal oxide layers in the oxide semiconductor layer 230 may have different compositions.
  • the oxide semiconductor layer 230 has a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer.
  • a material having a higher conductivity than the second metal oxide layer for the first metal oxide layer it is preferable to use a material having a higher conductivity than the second metal oxide layer for the first metal oxide layer.
  • a material having a higher conductivity for the first metal oxide layer in contact with the source electrode and the drain electrode conductive layer 120 and conductive layer 240
  • the contact resistance between the oxide semiconductor layer 230 and the conductive layer 120 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, and a transistor having a large on-current can be obtained.
  • the threshold voltage of the transistor 200A may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the first metal oxide layer for the second metal oxide layer.
  • the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as normally-off.
  • the oxide semiconductor layer 230 As described above, by forming the oxide semiconductor layer 230 into a stacked structure and using a material having a higher conductivity than the second metal oxide layer for the first metal oxide layer, a normally-off transistor with a large on-current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the first metal oxide layer is preferably higher than that of the second metal oxide layer.
  • the electrical conductivity is increased, and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 120 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced, resulting in a transistor with a large on-current.
  • the electrical conductivity is decreased, resulting in a normally-off transistor.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the first metal oxide layer may be made of a material having a lower conductivity than the second metal oxide layer.
  • the carrier concentration of the first metal oxide layer may be lower than the carrier concentration of the second metal oxide layer.
  • the band gap of the first metal oxide used in the first metal oxide layer is different from the band gap of the second metal oxide used in the second metal oxide layer.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the first metal oxide layer is preferably smaller than the band gap of the second metal oxide used in the second metal oxide layer. This can reduce the contact resistance between the oxide semiconductor layer 230 and the conductive layer 120 and the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240, and can provide a transistor with a large on-current.
  • the transistor 200A is an n-channel transistor
  • the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the large band gap of the second metal oxide can suppress the generation and induction of carriers in the second metal oxide layer and at the interface between the second metal oxide layer and the insulating layer 250. This can improve the reliability of the transistor.
  • the oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide.
  • the first metal oxide may be configured to contain a trace amount of element M or to contain no element M.
  • the first metal oxide used in the first metal oxide layer is In-Zn oxide
  • the second metal oxide used in the second metal oxide layer is In-M-Zn oxide.
  • the first metal oxide can be In-Zn oxide
  • the second metal oxide can be In-Ga-Zn oxide.
  • This increases the on-state current of transistor 200A and creates a highly reliable transistor structure with minimal variation.
  • the conductive layer 120 or the conductive layer 240 in the case of a stacked structure, the layer closest to the channel formation region of the oxide semiconductor layer 230
  • In-Zn oxide or In-Sn-Zn oxide for the oxide semiconductor layer 230 (or the first metal oxide layer)
  • ITO or ITSO for the conductive layer 120b and the conductive layer 240a in FIG. 9B and FIG. 9C
  • In-Zn oxide or In-Sn-Zn oxide for the first metal oxide layer
  • In-Ga-Zn oxide for the second metal oxide layer In-Ga-Zn oxide for the second metal oxide layer.
  • oxide semiconductor layer 230 is not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.
  • the oxide semiconductor layer 230 preferably has a metal oxide layer having crystallinity.
  • a metal oxide having crystallinity examples include a CAAC (c-axis aligned crystalline) structure, a polycrystalline (poly-crystalline) structure, and a nanocrystalline (nc: nano-crystalline) structure.
  • CAAC c-axis aligned crystalline
  • poly-crystalline polycrystalline
  • nanocrystalline nano-crystalline
  • the CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) have a c-axis orientation and are connected without being oriented in the a-b plane.
  • an OS film with a CAAC structure can be said to have a structure with layered crystal parts.
  • the polycrystalline structure has grain boundaries.
  • a minute gap also called a nanocrack or microcrack
  • a minute space also called a nanospace or microspace
  • the electrical resistance of the oxide semiconductor layer increases. This is because the electrical resistance of the minute gap or minute space is very high, for example, infinite.
  • an oxide semiconductor layer having a minute gap or minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor.
  • the CAAC structure has fewer grain boundaries in the a-b plane than the polycrystalline structure, and therefore can realize a highly reliable semiconductor device.
  • the crystallinity of the oxide semiconductor layer 230 can be analyzed by, for example, XRD, TEM, or ED. Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • the oxide semiconductor layer 230 may have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the first metal oxide layer and the second metal oxide layer may have different compositions, or may have the same or approximately the same composition.
  • a metal oxide having a high ratio of Zn to In is used for the first metal oxide layer, the crystallinity of the first metal oxide layer can be increased.
  • a second metal oxide layer on the first metal oxide layer having high crystallinity, it is also easy to increase the crystallinity of the second metal oxide layer. This makes it possible to increase the crystallinity of the entire oxide semiconductor layer 230, which is preferable.
  • gallium, aluminum, or tin as the element M.
  • two layers of IGZO having different compositions may be stacked.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • the oxide semiconductor layer 230 may also have a stacked structure of three or more layers.
  • the oxide semiconductor layer 230 may have a three-layer structure having a third metal oxide layer, a first metal oxide layer on the third metal oxide layer, and a second metal oxide layer on the first metal oxide layer.
  • the above-mentioned configurations can be applied to the first metal oxide layer and the second metal oxide layer.
  • the third metal oxide layer can have a configuration similar to that applicable to the second metal oxide layer. In the following, they will be described together as a pair of metal oxide layers sandwiching the first metal oxide layer.
  • the pair of metal oxide layers sandwiching the first metal oxide layer preferably have a band gap larger than that of the first metal oxide layer.
  • the first metal oxide layer is sandwiched between the pair of metal oxide layers having a larger band gap, and the first metal oxide layer mainly functions as a current path (channel).
  • sandwiching the first metal oxide layer between the pair of metal oxide layers it is possible to reduce trap levels at the interface of the first metal oxide layer and in its vicinity. This makes it possible to realize a buried channel type transistor in which the channel is kept away from the insulating layer interface, and to increase the field effect mobility.
  • the influence of the interface state that may be formed on the back channel side is reduced, and light deterioration (e.g., negative bias light deterioration) of the transistor can be suppressed, thereby improving the reliability of the transistor.
  • the thickness of the oxide semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • the thickness of the oxide semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • the oxide semiconductor layer when forming the oxide semiconductor layer, it is preferable to use two types of film formation methods, a sputtering method and an ALD method. For example, if a first oxide semiconductor layer having a CAAC structure is formed by using a sputtering method, and then a second oxide semiconductor layer having a lower crystallinity than the CAAC structure is formed by using an ALD method, it is expected that the atomic layer of the second oxide semiconductor layer will fill or repair the gaps in the atomic-level crystal parts of the CAAC structure of the first oxide semiconductor layer. In addition, it is preferable to perform heat treatment (for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • heat treatment for example, 100° C. or more and 500° C. or less, preferably 200° C. or more and 450° C. or less, more preferably 300° C.
  • an oxide semiconductor layer formed using the above two types of film formation methods may be called a hybrid OS.
  • the small gap or the small space in the first oxide semiconductor layer can be filled by forming a second oxide semiconductor layer on the first oxide semiconductor layer or by forming a second oxide semiconductor layer and performing heat treatment.
  • a dense oxide semiconductor layer with increased crystallinity can be obtained.
  • the dense oxide semiconductor layer with increased crystallinity is used for the channel formation region of a transistor, it is expected that an increase in the electrical resistance of the oxide semiconductor layer can be suppressed or the initial characteristics (particularly the on-current) of the transistor can be improved, making the transistor suitable for high-speed driving.
  • the oxide semiconductor layer when an oxide semiconductor layer is formed by both the sputtering method and the ALD method, if the thickness of the oxide semiconductor layer formed by the ALD method is thin, the oxide semiconductor layer can be regarded as a single-layer structure, not a stacked structure of the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer formed by the ALD method when the thickness of the oxide semiconductor layer formed by the ALD method is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably more than 0 nm and 1 nm or less, the oxide semiconductor layer formed by the two film formation methods, the sputtering method and the ALD method, can be regarded as a single-layer structure. In such a case, for example, in a cross-sectional TEM image, a cross-sectional STEM image, or the like, the boundary between the oxide semiconductor layer formed by the sputtering method and the oxide semiconductor layer formed by the ALD method is not observed.
  • the thickness of the oxide semiconductor layer formed by the ALD method exceeds 3 nm, it may be considered to be a stacked structure, a multilayer structure, or a multiple structure of an oxide semiconductor layer formed by the sputtering method and an oxide semiconductor layer formed by the ALD method.
  • the oxide semiconductor layer is formed by both the sputtering method and the ALD method, it is preferable to use different compositions.
  • the oxide semiconductor layer formed using the above-mentioned two types of film formation methods can be regarded as a structure in which the gaps in the crystal parts of the CAAC structure are filled with atomic layers formed by the ALD method. Note that this structure can be analyzed by analytical methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, secondary ion mass spectrometry (SIMS), and EDX.
  • analytical methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, secondary ion mass spectrometry (SIMS), and EDX.
  • the oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have a higher dielectric constant, film density, and film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.
  • a transistor having excellent characteristics for example, a transistor with a large on-current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a highly reliable transistor, etc.
  • Hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to become water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor. Furthermore, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as VOH ) may function as a donor and generate an electron that is a carrier. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (that is, the threshold voltage has a negative value). Furthermore, hydrogen in an oxide semiconductor is easily mobile due to stress such as heat or an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • VOH in the oxide semiconductor layer 230 it is preferable to reduce VOH in the oxide semiconductor layer 230 as much as possible to make the oxide semiconductor layer 230 highly pure intrinsic or substantially highly pure intrinsic.
  • it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for a channel formation region of a transistor stable electrical characteristics can be imparted.
  • oxygen addition treatment oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , still more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and still more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as a channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, and thus oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond to oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material in the channel formation region.
  • another semiconductor material include semiconductors made of single elements, or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.
  • Silicon that can be used as a semiconductor material for transistors includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • the semiconductor layer of the transistor may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), zirconium selenide (representatively ZrSe 2 ), and the like.
  • Insulating layer For insulating layers (insulating layer 140, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device, the insulating material described in [Insulating Layer] in Embodiment 1 can be used.
  • a material that can have ferroelectricity can be used for the insulating layer of the semiconductor device.
  • the explanation in embodiment 1 can be referred to, and therefore a detailed explanation is omitted.
  • an insulating layer having a function of suppressing the permeation of impurities and oxygen for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulating layers that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxide nitride, and silicon nitride.
  • an insulating layer such as a gate insulating layer that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen).
  • an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be reduced.
  • Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.
  • the insulating layer 280 preferably has a barrier insulating layer against hydrogen.
  • the insulating layer 280 is provided so as to surround the oxide semiconductor layer 230.
  • the insulating layer 280 provided on the outside of the oxide semiconductor layer 230 has a barrier property against hydrogen, so that the diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed.
  • Materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon oxynitride.
  • a barrier insulating layer refers to an insulating layer having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when described as a corresponding substance refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • the insulating layer 280 has one or both of an aluminum oxide film and a silicon nitride film.
  • Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 280, oxygen can be extracted from the oxide semiconductor layer 230, and an excessive amount of oxygen vacancies can be prevented from being formed in the oxide semiconductor layer 230.
  • the insulating layer 280 by using silicon nitride for the insulating layer 280, it is possible to prevent excess oxygen from being supplied to the oxide semiconductor layer 230. Therefore, it is possible to prevent the channel formation region of the oxide semiconductor layer 230 from becoming excessively oxygenated, thereby improving the reliability of the transistor 200A.
  • Insulating layer 280 preferably has an oxide insulating film, an oxynitride insulating film, or an insulating layer having a region containing excess oxygen, as described above.
  • an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen.
  • a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas the hydrogen concentration in the insulating layer 280 can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.
  • the thickness of the insulating layer 280 on the conductive layer 120 corresponds to the channel length of the transistor 200A, so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200A.
  • insulating layer 280 it is preferable to use a single layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film as the insulating layer 280.
  • a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order as the insulating layer 280.
  • the insulating layer 250 preferably has a function of capturing hydrogen and fixing hydrogen.
  • the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in a channel formation region of the transistor) can be reduced.
  • VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • the material of the insulating layer having the function of capturing or fixing hydrogen includes metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, for example, oxides containing hafnium and zirconium.
  • these metal oxides preferably have an amorphous structure.
  • the amorphous structure may be realized by including silicon in these oxides.
  • the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • the layer in contact with the oxide semiconductor layer 230 has a function of capturing and fixing hydrogen. This makes it possible to more effectively capture or fix hydrogen contained in the oxide semiconductor layer 230. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.
  • hafnium silicate or the like may be used as the layer of the insulating layer 250 in contact with the oxide semiconductor layer 230.
  • the layer has an amorphous structure.
  • the layer By making the layer an amorphous structure, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the layer can be improved. This makes the film thickness distribution of the insulating layer 250 uniform, and reduces the number of areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer 250. In addition, the film thickness distribution of the film provided on the insulating layer 250 can be made uniform.
  • the insulating layer 250 can function as an insulating film with low leakage current.
  • hafnium oxide is a high dielectric constant (high-k) material
  • hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulation layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulation layer. It is also possible to reduce the equivalent oxide thickness (EOT) of the gate insulation layer.
  • EOT equivalent oxide thickness
  • an oxide containing one or both of aluminum and hafnium as the insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.
  • the aforementioned barrier insulating layer against hydrogen is preferable to use as the insulating layer 250.
  • a barrier insulating layer against hydrogen is used as the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 260 into the oxide semiconductor layer 230.
  • silicon nitride has high barrier properties against hydrogen and is therefore suitable as the insulating layer 250.
  • the insulating layer 250 may have an insulating layer with a structure that is stable against heat, such as silicon oxide or silicon oxynitride.
  • the insulating layer 250 may have an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.
  • the insulating layer 250 may have an insulating layer with a thermally stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.
  • the insulating layer 250 has a barrier insulating layer against oxygen. This can prevent the conductive layer 240 and the conductive layer 260 from being oxidized.
  • the layer in contact with the conductive layer 240 is a barrier insulating layer against oxygen.
  • the layer in contact with the conductive layer 240 and the layer in contact with the conductive layer 260 are each preferably a barrier insulating layer against oxygen.
  • the conductive layer 260 By using a barrier insulating layer against hydrogen and oxygen for the layer of the insulating layer 250 that contacts the conductive layer 260, it is possible to prevent the conductive layer 260 from being oxidized. In addition, it is possible to prevent oxygen contained in the oxide semiconductor layer 230 from diffusing into the conductive layer 260 and forming oxygen vacancies in the oxide semiconductor layer 230.
  • Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).
  • the layer in insulating layer 250 that contacts conductive layer 240 is preferably less permeable to oxygen than insulating layer 280.
  • the layer has a barrier property against oxygen, which can prevent the side surface of conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-current or a decrease in the field effect mobility of transistor 200A.
  • each layer constituting the insulating layer 250 is preferably a thin film.
  • the subthreshold swing value also called S value
  • the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with a constant drain voltage in the subthreshold region.
  • each layer constituting the insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.
  • each layer constituting the insulating layer 250 may have a region with the above-mentioned thickness in at least a portion.
  • a three-layer structure is preferably used in which a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.
  • a material having a low dielectric constant of the first insulating layer silicon oxide or silicon oxynitride is preferably used.
  • the first insulating layer is a layer in contact with the oxide semiconductor layer 230. By using an oxide for the first insulating layer, oxygen can be supplied to the oxide semiconductor layer 230.
  • the third insulating layer it is possible to suppress the diffusion of oxygen contained in the first insulating layer to the conductive layer 260 and suppress the oxidation of the conductive layer 260. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the first insulating layer to the oxide semiconductor layer 230.
  • a four-layer structure is preferably used in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the oxide semiconductor layer 230 side.
  • the first insulating layer to the third insulating layer can have a similar structure to the layers used in the above-mentioned three-layer structure.
  • the fourth insulating layer is a layer in contact with the oxide semiconductor layer 230.
  • the fourth insulating layer has a barrier property against oxygen, so that oxygen can be prevented from being released from the oxide semiconductor layer 230.
  • aluminum oxide may be used as the fourth insulating layer.
  • Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.
  • the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are preferably made of aluminum oxide, silicon oxide, hafnium oxide, and silicon nitride, respectively.
  • the film thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • a three-layer structure for the insulating layer 250 in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, and a second insulating layer having a function of capturing or fixing hydrogen are stacked in this order from the oxide semiconductor layer 230 side. In other words, it is not necessary to provide a third insulating layer.
  • the insulating layer 283 is preferably a barrier insulating layer against hydrogen. This can suppress the diffusion of hydrogen from above the insulating layer 283 to the oxide semiconductor layer 230.
  • a silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 283.
  • silicon nitride deposited by sputtering As the insulating layer 283. Sputtering does not require the use of hydrogen-containing molecules in the deposition gas, and therefore the hydrogen concentration in the insulating layer 283 can be reduced. Furthermore, by depositing the insulating layer 283 by sputtering, silicon nitride with high density can be formed.
  • an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 283.
  • the insulating layer 283 aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.
  • the insulating layer 283 may also have a laminated structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen.
  • the insulating layer 283 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulating layer 285 functions as an interlayer film, it is preferable to use a material with a low dielectric constant as described above. For example, it is preferable that the insulating layer 285 has a silicon oxide film.
  • the concentration of impurities such as water and hydrogen in the insulating layer 140 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.
  • a barrier insulating layer against hydrogen as the insulating layer 140. This makes it possible to suppress the diffusion of hydrogen into the oxide semiconductor layer 230.
  • a silicon nitride film as the insulating layer 140.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • the conductive layer 120 and the conductive layer 240 are each a conductive layer in contact with the oxide semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also called an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion.
  • the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120 and the conductive layer 240.
  • the conductive layer 120 or the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. It is preferable to use, for example, ITO, ITSO, IZO (registered trademark), etc. as each of the conductive layer 120 and the conductive layer 240.
  • FIGS. 9B and 9C show an example in which the conductive layer 120 has a laminated structure of a conductive layer 120a and a conductive layer 120b on the conductive layer 120a.
  • the conductive layer 120a and the conductive layer 120b may each have a single-layer structure or a laminated structure.
  • the conductive layer 120a has a two-layer structure of a first conductive layer and a second conductive layer on the first conductive layer
  • a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the first conductive layer, a material with high conductivity as the second conductive layer, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 120b.
  • titanium nitride as the first conductive layer
  • tungsten as the second conductive layer
  • an oxide conductor e.g., ITO, ITSO, or IZO (registered trademark)
  • titanium nitride is in contact with the insulating layer 180, and the oxide conductor is in contact with the oxide semiconductor layer 230.
  • the oxide conductor has a lower contact resistance with the oxide semiconductor layer 230, so that the current path between the source and drain can be shortened and the on-current of the transistor can be increased.
  • the conductive layer 120 can maintain conductivity even when in contact with the oxide semiconductor layer 230.
  • the conductivity of the conductive layer 120 can be increased by using a metal material (here, tungsten) having a higher conductivity than the oxide conductor and titanium nitride as the second conductive layer.
  • Figures 9B and 9C show an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.
  • the conductive layer 240a may be made of a material having a higher conductivity than the conductive layer 240b
  • the conductive layer 240b may be made of a material having a higher conductivity than the conductive layer 240a.
  • a conductive material containing oxygen as the conductive layer 240a, and a material having a higher conductivity than the conductive layer 240a as the conductive layer 240b.
  • an oxide conductor e.g., ITO, ITSO, or IZO (registered trademark)
  • ruthenium, tungsten, titanium nitride, or tantalum nitride as the conductive layer 240b.
  • the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.
  • a conductive material containing oxygen may be used as the conductive layer 240b, and a material having a higher conductivity than the conductive layer 240b may be used as the conductive layer 240a.
  • the oxide semiconductor layer 230 is in contact with the side surface of the conductive layer 240a and the upper surface and side surface of the conductive layer 240b, and is not in contact with the upper surface of the conductive layer 240a.
  • the area of the oxide semiconductor layer 230 in contact with the conductive layer 240b is larger than the area of the oxide semiconductor layer 230 in contact with the conductive layer 240a.
  • the oxide conductor when an oxide conductor is used for the conductive layer 240b and a material having a higher conductivity than the oxide conductor, such as tungsten, is used for the conductive layer 240a, the oxide conductor is mainly in contact with the oxide semiconductor layer 230.
  • the conductive layer 240 can maintain conductivity even when in contact with the oxide semiconductor layer 230.
  • the conductive layer 240a can be made more conductive by using a material having a higher conductivity than the conductive layer 240b.
  • the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240b can be reduced, and the decrease in the on-current of the transistor 200A caused by the contact resistance can be suppressed.
  • the conductive layer 260 is preferably made of a highly conductive material such as tungsten.
  • the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen.
  • examples of the conductive material include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed for the conductive layer 260 may be used.
  • the conductive material containing the above-mentioned metal element and nitrogen for example, titanium nitride, tantalum nitride, etc.
  • one or more of ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, IZO (registered trademark), and ITSO may be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • the conductivity of the conductive layer 260 can be increased.
  • the conductive layer 260 may also have a laminated structure of three or more layers.
  • the conductive layer 260 may have a three-layer structure of tantalum nitride, titanium nitride on tantalum nitride, and tungsten on titanium nitride.
  • the conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265.
  • the conductive layer 265 may have the same structure as the conductive layer 260. For example, a two-layer structure of titanium nitride and tungsten may be applied.
  • the memory cell 150 including the transistor 200A and the capacitor 100 described in this embodiment can be used as a memory cell of a storage device.
  • the transistor 200A is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor.
  • the transistor 200A has a small off-state current; therefore, by using the transistor 200A in a storage device, stored content can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the storage device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200A allow high-speed reading and writing of the storage device.
  • a memory cell array can be formed by arranging memory cells 150 in a three-dimensional matrix.
  • Figure 10A is a plan view of a semiconductor device of one embodiment of the present invention.
  • Figure 10A shows an example in which 2 x 2 memory cells (memory cells 150a to 150d) are arranged in the X direction and the Y direction.
  • Figure 10B is a cross-sectional view taken along dashed line A3-A4 in Figure 10A.
  • two memory cells memory cell 150a and memory cell 150b in Figure 10B
  • a common wiring conductive layer 246
  • each of the memory cells 150a and 150b shown in FIG. 10A and FIG. 10B has the same configuration as the memory cell 150.
  • the memory cell 150a has a capacitor element 100a and a transistor 200a
  • the memory cell 150b has a capacitor element 100b and a transistor 200b.
  • the memory cells 150c and 150d shown in FIG. 10A also have the same configuration as the memory cell 150. Therefore, in the semiconductor device shown in FIG. 10A and FIG. 10B, structures having the same functions as the structures constituting the semiconductor device shown in FIG. 9A to FIG. 9C are denoted by the same reference numerals. For details of the memory cells 150a to 150d, the description of the memory cell 150 in ⁇ Example of memory cell configuration> can be referred to.
  • a conductive layer 265 functioning as a wiring WL is provided in each of the memory cells 150a and 150b.
  • one conductive layer 265 is provided in common to the memory cells 150a and 150c, and another conductive layer 265 is provided in common to the memory cells 150b and 150d.
  • a conductive layer 240 functioning as a part of the wiring BL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b.
  • the other conductive layer 240 is provided in common to the memory cells 150c and 150d.
  • the wiring WL and the wiring BL will be described later.
  • Figure 10B shows an example in which conductive layer 240 has a two-layer structure consisting of conductive layer 240a and conductive layer 240b on conductive layer 240a.
  • the 10A and 10B have conductive layers 245 and 246 that are electrically connected to memory cells 150a and 150b and function as plugs (which can also be called connection electrodes).
  • the conductive layer 245 is disposed in openings formed in the insulating layers 140, 180, and 280, and is in contact with the bottom surface of the conductive layer 240a.
  • the conductive layer 246 is disposed in openings formed in the insulating layers 287, 285, and 283, and the oxide semiconductor layer 230, and is in contact with the top surface of the conductive layer 240b.
  • the conductive layers 245 and 246 can be formed using a conductive material that can be used for the conductive layer 240, or the like.
  • the conductive layer 246 may be in contact with the upper surface of the conductive layer 240a. That is, the conductive layer 240b may have an opening at a position overlapping with the conductive layer 246. Alternatively, the conductive layer 246 may be in contact with the upper surface of the oxide semiconductor layer 230. That is, the oxide semiconductor layer 230 does not need to have an opening at a position overlapping with the conductive layer 246. As a connection point between the memory cell and the plug, it is preferable that, among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having a low contact resistance with the conductive layer 246 is in contact with the conductive layer 246.
  • the conductive layer 245 can be in contact with the bottom surface of the conductive layer 240b or the bottom surface of the oxide semiconductor layer 230. That is, the conductive layer 240a may have an opening at a position overlapping with the conductive layer 246.
  • a layer having a low contact resistance with the conductive layer 245 be in contact with the conductive layer 245.
  • the layer having low wiring resistance be in contact with the conductive layer 245 and the conductive layer 246.
  • the insulating layer 287 functions as an interlayer film, it is preferable that the insulating layer 287 has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wiring can be reduced.
  • the concentration of impurities such as water and hydrogen in the insulating layer 287 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.
  • the conductive layer 245 and the conductive layer 246 function as plugs or wirings for electrically connecting a circuit element, such as a switch, a transistor, a capacitor, an inductor, a resistor, and a diode, a wiring, an electrode, or a terminal, to the memory cell 150a and the memory cell 150b.
  • a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, and a diode
  • the conductive layer 245 can be electrically connected to a sense amplifier (not shown) provided under the semiconductor device shown in FIG. 10B
  • the conductive layer 246 can be electrically connected to a similar semiconductor device (not shown) provided over the semiconductor device shown in FIG. 10B.
  • the conductive layer 245 and the conductive layer 246 function as part of the wiring BL. In this way, by providing a similar semiconductor device or the like above or below the semiconductor device shown in FIG. 10B, the memory capacity per unit area can be increased.
  • the memory cell 150a and the memory cell 150b are configured to be line-symmetrical with respect to the perpendicular bisector of the dashed dotted line A3-A4. Therefore, the transistor 200a and the transistor 200b are also arranged in line-symmetrical positions with the conductive layer 245 and the conductive layer 246 sandwiched therebetween.
  • the conductive layer 240 functions as the other of the source electrode and drain electrode of the transistor 200a and as the other of the source electrode and drain electrode of the transistor 200b.
  • the transistor 200a and the transistor 200b share the conductive layer 245 and the conductive layer 246 that function as plugs. In this way, by configuring the connection between the two transistors and the plug as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.
  • the conductive layer 110 functioning as the wiring PL may be provided in each of the memory cells 150a and 150b, or may be provided in common to the memory cells 150a and 150b. However, as shown in FIG. 10B, the conductive layer 110 is provided apart from the conductive layer 245 so that the conductive layer 110 and the conductive layer 245 are not short-circuited.
  • the wiring PL will be described later.
  • FIG. 11 shows an example in which the four memory cells shown in FIG. 10A are stacked in n layers (n is an integer of 3 or more) in the Z direction.
  • FIG. 11 is a cross-sectional view between dashed lines A3-A4 shown in FIG. 10A.
  • the semiconductor device shown in FIG. 11 has n memory layers 160.
  • memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost layer.
  • the number of memory cells in one memory layer 160 is not particularly limited, and two or more memory cells can be included.
  • the memory cells in n memory layers 160 are electrically connected to a sense amplifier (not shown) provided below n memory layers 160 by conductive layers 245, 246, 247, 248, etc.
  • FIG. 11 shows an example in which the conductive layer 245 is in contact with the bottom surface of the conductive layer 240, and the conductive layer 246 is in contact with the top surface of the oxide semiconductor layer 230.
  • various modes are possible for the connection points between the plugs such as the conductive layer 245 and the conductive layer 246 and each memory cell, and are not limited to the configuration shown in FIG. 11.
  • the cells can be integrated and arranged without increasing the area occupied by the memory cell array.
  • a 3D memory cell array can be constructed.
  • Figure 12 shows an example of the cross-sectional configuration of a semiconductor device in which a layer having memory cells is stacked on a layer in which a driver circuit including a sense amplifier is provided.
  • a memory cell 150 (transistor 200A and capacitor 100) is provided above transistor 310.
  • Transistor 310 is one of the transistors contained in the sense amplifier.
  • the bit line can be shortened by configuring the sense amplifier so that it overlaps with the memory cell 150. This reduces the bit line capacitance, enabling the memory device to operate at high speed.
  • the semiconductor device shown in FIG. 12 can correspond to the memory device 300 described in embodiment 3. Specifically, the transistor 310 corresponds to the transistor included in the sense amplifier 46 in the memory device 300. Also, the memory cell 150 corresponds to the semiconductor device 10.
  • the transistor 310 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that is a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region.
  • the transistor 310 may be either a p-channel type or an n-channel type.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • a conductive layer 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulating layer 315.
  • the conductive layer 316 may be made of a material that adjusts the work function.
  • Such a transistor 310 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulating layer that contacts the upper part of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 310 shown in FIG. 12 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • the conductive layer functioning as a plug or wiring may be given the same reference symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.
  • an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film on the transistor 310.
  • a conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326.
  • the conductive layer 328 and the conductive layer 330 function as plugs or wiring.
  • the insulating layer that functions as an interlayer film may also function as a planarizing film that covers the uneven shape below it.
  • the upper surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve flatness.
  • a wiring layer may be provided on the insulating layer 326 and the conductive layer 330.
  • insulating layer 350, insulating layer 352, and insulating layer 354 are stacked in this order.
  • conductive layer 356 is formed on insulating layer 350, insulating layer 352, and insulating layer 354. Conductive layer 356 functions as a plug or wiring.
  • the insulating layer 352 and insulating layer 354, which function as interlayer films, can be the insulating layers that can be used in the semiconductor device or memory device described above.
  • Conductive layers that function as plugs or wiring can be made of a conductive material that can be used for the conductive layer 240. It is preferable to use a high-melting point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductive layer from a low-resistance conductive material, such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.
  • the conductive layer 240 of the transistor 200A is electrically connected to the low-resistance region 314b that functions as the source region or drain region of the transistor 310 via the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.
  • the conductive layer 643 is embedded in the insulating layer 280.
  • the conductive layer 642 is provided on the insulating layer 180 and embedded in the insulating layer 641.
  • the conductive layer 644 is embedded in the insulating layer 180.
  • the conductive layer 645 is covered by the insulating layer 180.
  • the conductive layer 645 can be manufactured using the same material and process as the conductive layer 110.
  • the conductive layer 646 is embedded in the insulating layer 648.
  • the transistor 310 and the conductive layer 110 are electrically insulated by the insulating layer 648.
  • the semiconductor device of this embodiment has a transistor with reduced parasitic capacitance, and therefore the operating speed can be increased.
  • the semiconductor device of this embodiment has a capacitive element and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a highly integrated semiconductor device can be realized.
  • Fig. 13A shows an equivalent circuit diagram of the memory cell 150.
  • the memory cell 150 shown in Fig. 13A functions as a DRAM type (1Tr1C type) memory element having one transistor M and one capacitance element Cfe.
  • the capacitance element Cfe is a ferroelectric capacitor having a material that can have ferroelectricity as a dielectric layer between two electrodes. Therefore, the memory cell 150 functions as an FeRAM.
  • the transistor M shown in FIG. 13A corresponds to the transistor 200A, and the capacitance element Cfe corresponds to the capacitance element 100.
  • One of the source and drain of the transistor M is connected to one of a pair of electrodes of the capacitance element Cfe.
  • the other of the source and drain of the transistor M is connected to the wiring BL.
  • the gate of the transistor M is connected to the wiring WL.
  • the other of the pair of electrodes of the capacitance element Cfe is connected to the wiring PL.
  • the wiring BL corresponds to the conductive layer 240
  • the wiring WL corresponds to the conductive layer 265
  • the wiring PL corresponds to the conductive layer 110.
  • the conductive layer 265 is provided extending in the X direction
  • the conductive layer 240 is provided extending in the Y direction.
  • the wiring BL and the wiring WL are provided to cross each other.
  • the wiring PL (conductive layer 110) is provided in a planar shape, but the present invention is not limited to this.
  • the wiring PL may be provided parallel to the wiring WL (conductive layer 265) or parallel to the wiring BL (conductive layer 240).
  • semiconductor layer in which the channel of the transistor M is formed can be used as the semiconductor layer in which the channel of the transistor M is formed.
  • a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination.
  • the semiconductor material for example, silicon or germanium can be used.
  • compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.
  • an OS transistor has a characteristic of having a high withstand voltage between the source and drain. Therefore, by using an OS transistor as the transistor M, a high voltage can be applied to the transistor M even if the transistor M is miniaturized. By miniaturizing the transistor M, the area occupied by the memory cell 150 can be reduced. For example, the area occupied by each memory cell 150 shown in FIG. 13A can be 1/3 to 1/6 of the area occupied by each cell of a static random access memory (SRAM). Therefore, the memory cells 150 can be arranged at a high density. This makes it possible to realize a storage device with a large storage capacity.
  • SRAM static random access memory
  • the memory cell can be called an "OS memory.”
  • OS memory a DRAM-type OS memory may be called a DOSRAM (registered trademark).
  • DOSRAM registered trademark
  • FeDOSRAM FeDOSRAM
  • the wiring WL functions as a word line, and the on and off states of the transistor M can be controlled by controlling the potential of the wiring WL.
  • the transistor M is an n-channel transistor, the transistor M can be turned on by setting the potential of the wiring WL to a high potential, and the transistor M can be turned off by setting the potential of the wiring WL to a low potential.
  • the wiring BL functions as a bit line, and when the transistor M is on, the potential of the wiring BL is supplied to one electrode of the capacitance element Cfe.
  • the wiring PL functions as a plate line. A potential is supplied to the other electrode of the capacitance element Cfe via the wiring PL.
  • the ferroelectric layer of the capacitance element Cfe has a hysteresis characteristic.
  • Fig. 13B is a graph showing an example of the hysteresis characteristic.
  • the horizontal axis indicates a voltage applied to the ferroelectric layer.
  • the voltage can be, for example, the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe.
  • the vertical axis indicates the polarization of the ferroelectric layer, and a positive value indicates that positive charges are biased toward one electrode side of the capacitance element Cfe, and negative charges are biased toward the other electrode side of the capacitance element Cfe.
  • a negative value of the polarization indicates that positive charges are biased toward the other electrode side of the capacitance element Cfe, and negative charges are biased toward one electrode side of the capacitance element Cfe.
  • the voltage shown on the horizontal axis of the graph in FIG. 13B may be the difference between the potential of the other electrode of the capacitance element Cfe and the potential of one electrode of the capacitance element Cfe.
  • the polarization shown on the vertical axis of the graph in FIG. 13B may be a positive value when positive charges are biased toward the other electrode side of the capacitance element Cfe and negative charges are biased toward one electrode side of the capacitance element Cfe, and a negative value when positive charges are biased toward one electrode side of the capacitance element Cfe and negative charges are biased toward the other electrode side of the capacitance element Cfe.
  • the hysteresis characteristics of the ferroelectric layer can be represented by curve 51 and curve 52.
  • the voltages at the intersections of curve 51 and curve 52 are VSP and VSP. It can be said that VSP and -VSP have different polarities.
  • VSP and -VSP can be called saturation polarization voltages.
  • VSP may be called the first saturation polarization voltage
  • -VSP may be called the second saturation polarization voltage
  • FIG. 13B shows a case where the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are equal, but the absolute values of the two may be different.
  • Vc the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 51 and the polarization of the ferroelectric layer is zero
  • -Vc the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer changes according to curve 52 and the polarization of the ferroelectric layer is zero
  • Vc and -Vc can be called coercive voltages.
  • the value of Vc and the value of Vc can be said to be between -VSP and VSP.
  • Vc may be called the first coercive voltage
  • -Vc may be called the second coercive voltage.
  • the absolute value of the first coercive voltage and the absolute value of the second coercive voltage are equal, but the absolute values of the two may be different.
  • the maximum value of polarization is called “residual polarization Pr” and the minimum value is called “residual polarization -Pr.”
  • the difference between the remnant polarization Pr and the remnant polarization -Pr is called “residual polarization 2Pr.”
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe can be expressed as the difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode of the capacitance element Cfe.
  • the other electrode of the capacitance element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, it is possible to control the voltage applied to the ferroelectric layer of the capacitance element Cfe.
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe is the potential difference between the potential of one electrode of the capacitance element Cfe and the potential of the other electrode (wiring PL) of the capacitance element Cfe.
  • the transistor M is an n-channel transistor.
  • Figure 13C is a timing chart showing an example of a method for driving the memory cell 150.
  • Figure 13C shows an example of writing and reading binary digital data to the memory cell 150.
  • Figure 13C shows an example of writing data "1" to the memory cell 150 from time T01 to time T02, reading and rewriting from time T03 to time T05, reading from time T11 to time T13 and writing data "0" to the memory cell 150, reading and rewriting from time T14 to time T16, and reading from time T17 to time T19 and writing data "1" to the memory cell 150.
  • the sense amplifier electrically connected to the wiring BL is supplied with Vref as a reference potential.
  • Vref the potential of the wiring BL
  • data "1" is read by the bit line driver circuit.
  • data "0" is read by the bit line driver circuit.
  • the potential of the wiring WL is set to a high potential (H). This turns on the transistor M. Furthermore, the potential of the wiring BL is set to Vw. Since the transistor M is on, the potential of one electrode of the capacitance element Cfe is Vw. Furthermore, the potential of the wiring PL is set to GND. From the above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND". This allows data "1" to be written to the memory cell 150. Therefore, it can be said that the period from time T01 to time T02 is a period during which a write operation is performed.
  • Vw is preferably equal to or greater than VSP, for example, and is preferably equal to VSP.
  • GND is a ground potential, but it does not necessarily have to be a ground potential as long as the memory cell 150 can be driven to satisfy the purpose of one aspect of the present invention. For example, if the absolute value of the first saturation polarization voltage is different from the absolute value of the second saturation polarization voltage, and the absolute value of the first coercive voltage is different from the absolute value of the second coercive voltage, GND can be a potential other than ground.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitance element Cfe from time T01 to time T02 can be set to VSP or higher, from time T02 to time T03, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 52 shown in FIG. 13B. From the above, from time T02 to time T03, no polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe.
  • the potential of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential (L). This turns off the transistor M. This completes the write operation, and data "1" is stored in the memory cell 150.
  • the potentials of the wiring BL and the wiring PL can be any potential as long as no polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or higher than the second coercive voltage -Vc.
  • the potential of the wiring WL is set to a high potential. This causes the transistor M to be turned on.
  • the potential of the wiring PL is set to Vw.
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw".
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND" from time T01 to time T02. Therefore, polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe.
  • a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref.
  • the bit line driver circuit can read out the data "1" stored in the memory cell 150. Therefore, it can be said that the period from time T03 to time T04 is a period during which a read operation is performed.
  • Vref is higher than GND and lower than Vw, but it may be higher than Vw, for example.
  • the period from time T04 to time T05 can be said to be a period during which a rewrite operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. As a result, the rewrite operation is completed, and data "1" is held in the memory cell 150.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "1" is stored in the memory cell 150, the potential of the wiring BL becomes higher than Vref, and the data "1" stored in the memory cell 150 is read out. Therefore, the period from time T11 to time T12 can be said to be a period in which a read operation is performed.
  • the potential of the wiring BL is set to GND. Since the transistor M is in the on state, the potential of one electrode of the capacitance element Cfe is set to GND. In addition, the potential of the wiring PL is set to Vw. From the above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw". This allows data "0" to be written to the memory cell 150. Therefore, it can be said that the period from time T12 to time T13 is a period during which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND.
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitance element Cfe from time T12 to time T13 can be set to -VSP or less, from time T13 to time T14, the polarization amount of the ferroelectric layer of the capacitance element Cfe changes according to the curve 51 shown in FIG. 13B. From the above, no polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe from time T13 to time T14.
  • the potential of the wiring BL and the wiring PL are set to GND, the potential of the wiring WL is set to a low potential. This turns off the transistor M. This completes the write operation, and data "0" is stored in the memory cell 150.
  • the potentials of the wiring BL and the wiring PL can be set to any potential as long as no polarization reversal occurs in the ferroelectric layer of the capacitance element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitance element Cfe is equal to or lower than the first coercive voltage Vc.
  • the potential of the wiring WL is set to a high potential. This causes the transistor M to be in an on state. Also, the potential of the wiring PL is set to Vw.
  • the potential of the wiring PL is set to Vw.
  • the voltage applied to the ferroelectric layer of the capacitance element Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "GND-Vw" at time T12 to time T13. Therefore, no polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe. Therefore, the amount of current flowing through the wiring BL is smaller than when polarization inversion occurs in the ferroelectric layer of the capacitance element Cfe.
  • the bit line driver circuit can read out the data "0" stored in the memory cell 150. Therefore, the period from time T14 to time T15 can be said to be the period during which the read operation is performed.
  • the period from time T15 to time T16 can be said to be a period in which a rewrite operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. As a result, the rewrite operation is completed, and data "0" is held in the memory cell 150.
  • the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since data "0" is stored in the memory cell 150, the potential of the wiring BL becomes lower than Vref, and the data "0" stored in the memory cell 150 is read out. Therefore, the period from time T17 to time T18 can be said to be a period in which a read operation is performed.
  • the potential of the wiring BL is Vw. Since the transistor M is on, the potential of one electrode of the capacitance element Cfe is Vw. In addition, the potential of the wiring PL is GND. From the above, the voltage applied to the ferroelectric layer of the capacitance element Cfe is "Vw-GND". This allows data "1" to be written to the memory cell 150. Therefore, the period from time T18 to time T19 can be said to be a period during which a write operation is performed.
  • the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. This completes the write operation, and data "1" is held in the memory cell 150.
  • Memory cell 150 which uses a ferroelectric layer for the capacitance element Cfe, functions as a non-volatile memory element that can retain written information even when the power supply is stopped.
  • DRAM requires periodic refresh operations, which increases power consumption.
  • the memory cell 150 which uses a ferroelectric layer for the capacitance element Cfe, does not require refresh operations, so power consumption can be reduced.
  • a memory element or memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory” or an "FE memory”.
  • the memory cell 150 is both a ferroelectric memory and an FE memory.
  • the FE memory is expected to achieve a rewrite count of 1 ⁇ 10 10 or more, preferably 1 ⁇ 10 12 or more, and more preferably 1 ⁇ 10 15 or more.
  • the FE memory is also expected to achieve an operating frequency of 10 MHz or more, preferably 1 GHz or more.
  • FE memory there is a correlation between the residual polarization 2Pr and data retention capacity, and as the residual polarization 2Pr decreases, the data retention capacity decreases.
  • the period until the residual polarization 2Pr decreases by 5% is called the "memory retention period”.
  • FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more at an environmental temperature of 150°C or 200°C.
  • FE memory can also be applied to cache memory and registers of CPUs and GPUs (Graphics Processing Units).
  • a Noff-CPU Normally off CPU
  • a Noff-GPU Normally off CPU
  • FIG. 14A is a block diagram illustrating a configuration example of a memory device 300 according to one embodiment of the present invention.
  • the memory device 300 illustrated in FIG. 14A includes a driver circuit 21 and a memory array 20.
  • the memory array 20 includes a plurality of semiconductor devices 10.
  • FIG. 14A illustrates an example in which the memory array 20 includes a plurality of semiconductor devices 10 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or more).
  • the semiconductor device 10 can correspond to the memory cell 150 described in embodiment 2.
  • rows and columns extend in directions perpendicular to each other.
  • the X direction is referred to as the "rows” and the Y direction is referred to as the “columns”, but the X direction may be referred to as the “columns” and the Y direction as the "rows”.
  • the semiconductor device 10 in the first row and first column is indicated as semiconductor device 10[1,1] and the semiconductor device 10 in the mth row and nth column is indicated as semiconductor device 10[m,n].
  • an arbitrary row may be indicated as row i.
  • An arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the semiconductor device 10 in the ith row and jth column is indicated as semiconductor device 10[i,j].
  • when “i+ ⁇ " ( ⁇ is a positive or negative integer) is indicated, "i+ ⁇ " is not less than 1 and does not exceed m.
  • j+ ⁇ is not less than 1 and does not exceed n.
  • the memory array 20 also includes m wirings WL extending in the row direction (X direction), m wirings PL extending in the row direction (X direction), and n wirings BL extending in the Z direction. Note that although the n wirings BL extend in the Z direction, in order to make it easier to understand the relationship between the wirings WL and PL and the wirings BL, in FIG. 14A the n wirings BL are shown extending in the column direction (Y direction).
  • the first wiring WL (first row) is indicated as wiring WL[1], and the mth wiring WL (mth row) is indicated as wiring WL[m].
  • the first wiring PL (first row) is indicated as wiring PL[1]
  • the mth wiring PL (mth row) is indicated as wiring PL[m].
  • the first wiring BL (first column) is indicated as wiring BL[1]
  • the nth wiring BL (nth column) is indicated as wiring BL[n].
  • the multiple semiconductor devices 10 arranged in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row.
  • the multiple semiconductor devices 10 arranged in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • the drive circuit 21 has a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 300. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 300.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the semiconductor device 10.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.
  • the row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WL specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the semiconductor device 10, the function of reading data from the semiconductor device 10, the function of holding the read data, etc.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is data (Din) to be written to the semiconductor device 10.
  • the data (Dout) read from the semiconductor device 10 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 300.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply potential of the memory device 300 is VDD
  • the low power supply potential is GND (ground potential).
  • VHM is a high power supply potential used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power supply domain.
  • the driving circuit 21 and the memory array 20 may be provided on the same plane. Also, as shown in FIG. 14B, a layer including the memory array 20 may be provided directly above a layer including the driving circuit 21.
  • the driving circuit 21 and the memory array 20 in an overlapping manner, the signal propagation distance between the driving circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the driving circuit 21 and the memory array 20 are reduced, and power consumption and signal delay can be reduced. Also, the memory device 300 can be made smaller.
  • FIG. 14B shows one layer of memory array 20 on drive circuit 21, but multiple layers of memory array 20 may be provided on drive circuit 21.
  • FIG. 14C shows an example in which k layers (k is an integer of 2 or more) of memory arrays 20 are provided on drive circuit 21.
  • the memory array 20 provided on the first layer is shown as memory array 20[1]
  • the memory array 20 provided on the second layer is shown as memory array 20[2]
  • the memory array 20 provided on the kth layer is shown as memory array 20[k].
  • FIG. 15A is a schematic diagram illustrating an example of the configuration of a memory device 300.
  • the memory device 300 shown in FIG. 15A has six layers of memory arrays 20 provided on a drive circuit 21. As described above, in FIG. 15A and other figures, the memory array 20 provided on the third layer is shown as memory array 20[3], the memory array 20 provided on the fourth layer is shown as memory array 20[4], the memory array 20 provided on the fifth layer is shown as memory array 20[5], and the memory array 20 provided on the sixth layer is shown as memory array 20[6].
  • Each memory array 20 has a plurality of semiconductor devices 10 arranged in a matrix, and wiring WL and wiring PL extending in the X direction. Note that, to make the drawings easier to understand, the wiring WL and wiring PL of each of the memory arrays 20 in the first to fifth layers have been omitted.
  • the memory device 300 shown in FIG. 15A also has multiple wirings BL extending in the Z direction.
  • the wirings BL are formed through each of the six layers of memory arrays 20 and are electrically connected to the drive circuit 21. When viewed from the Z direction, the multiple wirings BL are arranged in a matrix.
  • connection distance between the semiconductor device 10 and the drive circuit 21 can be made shorter than when the wiring BL is extended in the X or Y direction. This shortens the signal propagation distance between the semiconductor device 10 and the drive circuit 21, thereby increasing the operating speed of the memory device. In addition, the parasitic capacitance associated with the wiring BL is reduced, thereby reducing power consumption.
  • each memory array 20 in each layer one of the multiple semiconductor devices 10 included in the memory array 20 is electrically connected to one of the multiple wirings BL. Therefore, in the memory device 300 shown in FIG. 15A, a total of six semiconductor devices 10 are electrically connected to one wiring BL, one from each memory array 20 in each layer.
  • a configuration in which multiple memory cells (semiconductor device 10) are electrically connected to one wiring BL is also called a "memory string.” Therefore, it can be said that the memory device 300 shown in FIG. 15A is configured to include multiple memory strings.
  • FIG. 15B shows a schematic diagram of a memory string included in the memory device 300 shown in FIG. 15A. Note that, in order to make the drawing easier to understand, the wiring WL and wiring PL electrically connected to the semiconductor device 10 are omitted from the schematic diagram of the memory string shown in FIG. 15B. Also, a part of the equivalent circuit of the memory string is shown in FIG. 15B.
  • FIG. 16A is a schematic diagram illustrating an example of the configuration of a storage device 300.
  • the storage device 300 shown in FIG. 16A is a modified version of the storage device 300 shown in FIG. 15A. Therefore, to avoid repetition of explanation, differences from the storage device 300 shown in FIG. 15A will be mainly described.
  • the memory device 300 shown in FIG. 16A differs from the memory device 300 shown in FIG. 15A in that, in each memory array 20 in each layer, two of the multiple semiconductor devices 10 included in the memory array 20 are electrically connected to one of the multiple wirings BL. In other words, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.
  • Figure 16B shows a schematic diagram of a memory string in the memory device 300 shown in Figure 16A.
  • Figure 16B also shows a portion of an equivalent circuit of the memory string.
  • the memory device 300 shown in FIG. 16A can reduce the number of wirings BL compared to the memory device 300 shown in FIG. 15A. Therefore, the area occupied by the memory device 300 is reduced.
  • the semiconductor device 10 is an FE memory, and can retain written information for a long period of time even if the power supply is stopped.
  • the refresh operation required for DRAM is not required, a memory device 300 with low power consumption can be realized.
  • FIG. 17A and 17B show an example of a chip 1200 on which a semiconductor device of one embodiment of the present invention is mounted.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • a technology for integrating a plurality of circuits (systems) on one chip in this manner may be called a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
  • Bumps (not shown) are provided on the chip 1200, which are connected to the first surface of the package substrate 1201, as shown in FIG. 17B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a storage device 1221 or a flash memory 1222.
  • the semiconductor device 10 may be used for the storage device 1221.
  • the semiconductor device 10 may be used instead of the flash memory 1222.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the semiconductor device 10 may be used for the memory.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using an oxide semiconductor, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.
  • the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit.
  • the analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the memory device 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include a mouse, a keyboard, and a game controller. Examples of such interfaces that can be used include a Universal Serial Bus (USB) and a High-Definition Multimedia Interface (HDMI (registered trademark)).
  • USB Universal Serial Bus
  • HDMI High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • circuits can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
  • the package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the storage device 1221, and the motherboard 1203 on which the flash memory 1222 is provided can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles.
  • a product-sum operation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • Fig. 18A shows a perspective view of an electronic component 700 and a substrate (mounting substrate 704) on which the electronic component 700 is mounted.
  • the electronic component 700 shown in Fig. 18A has a memory device 720 in a mold 711.
  • Fig. 18A omits a portion of the electronic component 700 in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711.
  • the lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 720 by wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722.
  • the memory device 300 can be used for the memory device 720. Therefore, the driver circuit layer 721 can be a layer including a driver circuit 21. Furthermore, a single layer or multiple layers of memory array 20 can be used for the memory circuit layer 722. Therefore, the driver circuit layer 721 can be a layer including a memory array 20.
  • Figure 18B shows a perspective view of electronic component 730.
  • Electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 720 provided on interposer 731.
  • the memory device 720 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).
  • the package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like.
  • the interposer 731 may be a silicon interposer, a resin interposer, or the like.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV Through Silicon Via
  • interposer 731 It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at lower cost than integrated circuits. On the other hand, wiring on silicon interposers can be formed using semiconductor processes, making it easy to form fine wiring that is difficult to achieve with resin interposers.
  • HBM requires many wiring connections to achieve a wide memory bandwidth. For this reason, the interposer that implements the HBM requires fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that implements the HBM.
  • SiP, MCM, etc. that use silicon interposers
  • deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is less likely to occur.
  • the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 18B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.
  • the semiconductor device can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book terminals, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related devices, and the like.
  • IoT Internet of Things
  • computer includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.
  • FIGS. 19A to 19J and 20A to 20E show how an electronic component 700 or an electronic component 730 including the semiconductor device is included in each electronic device.
  • [mobile phone] 19A is a mobile phone (smartphone), which is one type of information terminal.
  • the information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.
  • the information terminal 5500 can hold temporary files (e.g., caches when using a web browser) that are generated when an application is executed.
  • [Wearable devices] 19B illustrates an information terminal 5900, which is an example of a wearable terminal.
  • the information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.
  • the wearable terminal can store temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • FIG. 19C shows a desktop information terminal 5300.
  • the desktop information terminal 5300 has a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.
  • the desktop information terminal 5300 can store temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.
  • a smartphone, a wearable terminal, and a desktop information terminal are shown as examples of electronic devices in Figs. 19A to 19C, respectively, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied.
  • information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.
  • [electric appliances] 19D illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance.
  • the electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.
  • the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).
  • a semiconductor device can be applied to an electric refrigerator-freezer 5800.
  • the electric refrigerator-freezer 5800 can transmit and receive information such as food ingredients stored in the electric refrigerator-freezer 5800 and expiration dates of the food ingredients to an information terminal or the like via the Internet or the like.
  • the electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.
  • an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water servers, air conditioners and other heating and cooling appliances, washing machines, dryers, and audiovisual equipment.
  • [Gaming consoles] 19E shows a portable game machine 5200, which is an example of a game machine.
  • the portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.
  • FIG. 19F illustrates a stationary game machine 7500, which is an example of a game machine.
  • the stationary game machine 7500 has a main body 7520 and a controller 7522.
  • the controller 7522 can be connected to the main body 7520 wirelessly or by wire.
  • the controller 7522 can include a display unit that displays game images, and an input interface other than buttons, such as a touch panel, a stick, a rotary knob, or a sliding knob.
  • the shape of the controller 7522 is not limited to the shape shown in FIG. 19F, and the shape of the controller 7522 may be changed in various ways depending on the genre of the game.
  • a trigger is used as a button, and a controller shaped like a gun can be used.
  • a controller shaped like a musical instrument, a musical device, or the like can be used.
  • a stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures or voice.
  • the images from the game consoles described above can be output by display devices such as television sets, computer displays, game displays, and head-mounted displays.
  • a low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized.
  • the low power consumption can reduce heat generation from the circuit, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • FIG. 19E shows a portable game machine.
  • FIG. 19F shows a stationary game machine for home use.
  • electronic devices according to one embodiment of the present invention are not limited to this. Examples of electronic devices according to one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.
  • the semiconductor device described in the above embodiment can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.
  • Figure 19G illustrates an automobile 5700, which is an example of a moving object.
  • an instrument panel that provides various information by displaying a speedometer, tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. Also, around the driver's seat, there may be a display device that shows this information.
  • the display device can display an image from an imaging device (not shown) installed in the automobile 5700, thereby compensating for vision obstructed by pillars and blind spots around the driver's seat, thereby improving safety.
  • an imaging device not shown
  • blind spots can be compensated for and safety can be improved.
  • the semiconductor device described in the above embodiment can temporarily store information, and therefore, for example, the semiconductor device can be used to store necessary temporary information in a system that performs automatic driving of the automobile 5700, road guidance, risk prediction, and the like.
  • the display device may be configured to display temporary information such as road guidance and risk prediction.
  • the display device may be configured to store images from a driving recorder installed in the automobile 5700.
  • moving bodies are not limited to automobiles.
  • moving bodies can also include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).
  • FIG 19H shows a digital camera 6240, which is an example of an imaging device.
  • the digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240.
  • the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and the housing 6241 may be integrated.
  • the digital camera 6240 may also be configured so that a strobe device, viewfinder, etc. can be separately attached.
  • a low-power digital camera 6240 can be realized.
  • low power consumption can reduce heat generation from the circuit, so that the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • the semiconductor device described in the above embodiment can be applied to a video camera.
  • FIG. 19I shows a video camera 6300, which is an example of an imaging device.
  • the video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like.
  • the operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302.
  • the first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306.
  • the image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.
  • the video camera 6300 can store temporary files generated during encoding.
  • ICD implantable cardioverter defibrillator
  • FIG. 19J is a schematic cross-sectional view showing an example of an ICD.
  • the ICD main body 5400 has at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.
  • the ICD body 5400 is placed in the body by surgery, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.
  • the ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve through pacing (fast ventricular tachycardia, ventricular fibrillation, etc.), treatment is given by electric shock.
  • the ICD main body 5400 must constantly monitor the heart rate in order to perform pacing and electric shocks appropriately. For this reason, the ICD main body 5400 has a sensor for detecting the heart rate.
  • the ICD main body 5400 can also store in the electronic component 700 heart rate data acquired by the sensor, the number of times pacing treatment has been performed, the time, etc.
  • the antenna 5404 can receive power, which is then charged into the battery 5401.
  • the ICD main body 5400 also has multiple batteries, which can increase safety. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can continue to function, so the ICD main body 5400 also functions as an auxiliary power source.
  • an antenna that can transmit physiological signals may be provided, and a system may be configured to monitor cardiac activity such that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.
  • PC expansion device The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.
  • Figure 20A shows an example of such an expansion device, a portable expansion device 6100 equipped with a chip capable of storing information, which is external to a PC.
  • the expansion device 6100 can store information using the chip by connecting it to a PC, for example, via USB.
  • Figure 20A shows a portable expansion device 6100
  • the expansion device according to one aspect of the present invention is not limited to this, and may be, for example, a relatively large expansion device equipped with a cooling fan or the like.
  • the expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104.
  • the board 6104 is housed in the housing 6101.
  • the board 6104 is provided with a circuit for driving the semiconductor device described in the above embodiment.
  • an electronic component 700 and a controller chip 6106 are attached to the board 6104.
  • the USB connector 6103 functions as an interface for connecting to an external device.
  • SD card The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to electronic devices such as information terminals and digital cameras.
  • FIG 20B is a schematic diagram of the external appearance of an SD card
  • Figure 20C is a schematic diagram of the internal structure of the SD card.
  • the SD card 5110 has a housing 5111, a connector 5112, and a board 5113.
  • the connector 5112 functions as an interface for connecting to an external device.
  • the board 5113 is housed in the housing 5111.
  • the board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device.
  • an electronic component 700 and a controller chip 5115 are attached to the board 5113.
  • the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation.
  • a write circuit, a row driver, a read circuit, etc. provided in the electronic component may be incorporated in the controller chip 5115 instead of the electronic component 700.
  • a wireless chip with wireless communication capabilities may also be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, making it possible to read and write data from and to the electronic component 700.
  • SSD Solid State Drive
  • electronic devices such as information terminals.
  • FIG 20D is a schematic diagram of the appearance of an SSD
  • Figure 20E is a schematic diagram of the internal structure of the SSD.
  • the SSD 5150 has a housing 5151, a connector 5152, and a board 5153.
  • the connector 5152 functions as an interface for connecting to an external device.
  • the board 5153 is housed in the housing 5151.
  • the board 5153 is provided with a memory device and a circuit for driving the memory device.
  • the board 5153 is provided with an electronic component 700, a memory chip 5155, and a controller chip 5156.
  • the capacity of the SSD 5150 can be increased by providing an electronic component 700 on the back side of the board 5153 as well.
  • a work memory is incorporated in the memory chip 5155.
  • a DRAM chip may be used for the memory chip 5155.
  • the controller chip 5156 is incorporated with a processor, an ECC circuit, and the like.
  • the circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation.
  • the controller chip 5156 may also be provided with a memory that functions as a work memory.
  • the computer 5600 shown in FIG. 21A is an example of a large computer (supercomputer) mainly used for scientific and technological calculations.
  • a huge amount of calculations must be processed at high speed, so power consumption is high and the chip generates a lot of heat.
  • the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is expected to exceed 10 24 (yota) bytes or 10 30 (quetta) bytes.
  • a supercomputer with low power consumption can be realized.
  • the low power consumption can reduce heat generation from the circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.
  • a supercomputer with low power consumption can be realized. This is expected to reduce the amount of digital data in the world and to make a significant contribution to measures against global warming.
  • Computer 5600 has multiple rack-mounted computers 5620 stored in rack 5610.
  • Computer 5620 can have the configuration shown in the perspective view of FIG. 21B, for example.
  • computer 5620 has motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • PC card 5621 is inserted into slot 5631.
  • PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.
  • the PC card 5621 shown in FIG. 21C is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 21C illustrates semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628, but for these semiconductor devices, the following description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 can be used as a reference.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark), and the like.
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, artificial intelligence learning and inference.
  • the electronic devices can be made smaller and consume less power.
  • the semiconductor device of one embodiment of the present invention consumes less power, heat generation from the circuit can be reduced. Therefore, adverse effects of the heat on the circuit itself, peripheral circuits, and modules can be reduced.
  • electronic devices that operate stably even in high-temperature environments can be realized. Therefore, the reliability of the electronic devices can be improved.
  • the semiconductor device of one embodiment of the present invention includes an OS transistor.
  • the OS transistor has small change in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in space.
  • FIG. 22 a specific example of application of the semiconductor device of one embodiment of the present invention to space equipment will be described with reference to FIG. 22 .
  • Figure 22 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example in outer space.
  • outer space refers to an altitude of, for example, 100 km or higher, but the outer space described in this specification can include the thermosphere, mesosphere, and stratosphere.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • a semiconductor device including an OS transistor which is one embodiment of the present invention, is preferably used for the control device 6807.
  • the OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • HfZrOx Hafnium zirconium oxide (X is a real number greater than 0)) was used as the insulating layer.
  • HfZrOx is a material that can have ferroelectricity.
  • ⁇ Sample structure and preparation method> 23 shows a schematic cross-sectional view of a sample 800.
  • the sample 800 has a substrate 801, an insulating layer 802 on the substrate 801, a conductive layer 803 on the insulating layer 802, an insulating layer 804 on the conductive layer 803, and a conductive layer 805 on the insulating layer 804.
  • the conductive layer 805 has a two-layer structure of a conductive layer 805a and a conductive layer 805b on the conductive layer 805a.
  • sample 800 a method for manufacturing the sample 800 will be described.
  • sample 800 four samples (sample 800A, sample 800B, sample 800C, and sample 800D) were manufactured, which have different conditions for forming the conductive layer 805 and different conditions for heat treatment after forming the conductive layer 805.
  • a silicon substrate was prepared as the substrate 801.
  • a silicon oxide film with a thickness of 100 nm was formed as the insulating layer 802 using thermal oxidation processing.
  • a first titanium nitride film having a thickness of 20 nm was formed by metal CVD as the conductive layer 803.
  • the first titanium nitride film was formed by supplying 50 sccm of titanium chloride ( TiCl4 ) and 2700 sccm of ammonia ( NH3 ) to a reaction chamber of a CVD apparatus, controlling the pressure in the reaction chamber to 667 Pa, setting the distance between the substrate stage and the gas injection stage to 3 mm, and setting the substrate temperature to 400°C.
  • the thickness of the HfZrOX film was set to 12 nm.
  • Tetrakis(ethylmethylamido)hafnium (TEMAHf) and tetrakis(ethylmethylamido)zirconium (TEMAZr) were used as precursors, and ozone (O 3 ) was used as an oxidizing agent.
  • the film formation temperature was set to 250° C.
  • a second titanium nitride film with a thickness of 5 nm was formed as the conductive layer 805a by a metal CVD method. Note that, in common to samples 800A to 800D, the conditions for forming the second titanium nitride film were the same as those for the first titanium nitride film, except for the substrate temperature. The substrate temperature when forming the second titanium nitride film was 400°C for sample 800A, 340°C for sample 800B, and 300°C for samples 800C and 800D.
  • a tungsten film with a thickness of 30 nm was formed as the conductive layer 805b by metal CVD. In common with samples 800A to 800D, the tungsten film was formed in three steps.
  • the deposition gas flow rates were set to 160 sccm of tungsten hexafluoride, 400 sccm of silane, 6000 sccm of argon, and 2000 sccm of nitrogen, and the pressure inside the chamber during deposition was set to 1000 Pa to form a portion of the tungsten film.
  • the deposition gas flow rates were set to 250 sccm of tungsten hexafluoride, 4000 sccm of hydrogen, 2000 sccm of argon, and 200 sccm of nitrogen, and the pressure in the chamber during deposition was set to 10,666 Pa to form another part of the tungsten film.
  • the deposition gas flow rates were set to 250 sccm of tungsten hexafluoride, 2200 sccm of hydrogen, 2000 sccm of argon, and 200 sccm of nitrogen, and the pressure in the chamber during deposition was set to 10,666 Pa to form another part of the tungsten film.
  • the substrate temperatures in the first, second, and third steps were 400°C for sample 800A, 345°C for sample 800B, and 300°C for samples 800C and 800D.
  • sample 800 (samples 800A to 800D) was prepared.
  • sample 810 was prepared as a comparative example.
  • Sample 810 had a structure in which the conductive layer 805 in sample 800 was not provided, and the other configurations and preparation conditions were the same as those of sample 800C.
  • Table 1 shows the deposition conditions and heat treatment conditions of the conductive layer 805a and the conductive layer 805b in each of sample 810 and samples 800A to 800D. Note that in Table 1, a hyphen (-) is added to the conductive layer 805 of sample 810 to indicate that the conductive layer 805 is not included. In addition, in Table 1, a hyphen (-) is added to the heat treatment conditions of samples 800A to 800C to indicate that the heat treatment was not performed.
  • GIXRD> The crystal state of the HfZrO X film corresponding to the insulating layer 804 of each of the sample 810 and the samples 800A to 800D was investigated by GIXRD measurement, which is one type of XRD analysis method.
  • the conductive layers 805a and 805b were removed by wet etching in each of the samples 800A to 800D.
  • a multifunctional thin film material evaluation X-ray diffraction device D8 DISCOVER Hybrid/TXS manufactured by Bruker was used.
  • the measurement conditions when using this device were an X-ray output of 50 kV and 100 mA, an incident angle ⁇ of 0.5°, and a scanning range 2 ⁇ of 20° to 50°.
  • Figures 24A to 24E show the results of GIXRD measurements.
  • Figures 24A to 24E show the relationship between the diffraction angle (2 ⁇ ) of X-rays and the detected signal intensity.
  • the vertical axis indicates intensity
  • the horizontal axis indicates the diffraction angle (2 ⁇ ).
  • Figure 24A shows the GIXRD measurement results of sample 810
  • Figure 24B shows the GIXRD measurement results of sample 800A
  • Figure 24C shows the GIXRD measurement results of sample 800B
  • Figure 24D shows the GIXRD measurement results of sample 800C
  • Figure 24E shows the GIXRD measurement results of sample 800D.
  • peaks were detected at the first peak position, the second peak position, and the third peak position in sample 800A and sample 800B.
  • the peaks detected at the first peak position, the second peak position, and the third peak position correspond to the first peak, the second peak, and the third peak, respectively, described in embodiment 1.
  • the first peak, the second peak, and the third peak were detected in sample 800A and sample 800B.
  • the ratio of the peak intensity of the second peak to the peak intensity of the first peak is called the second peak intensity ratio
  • the ratio of the peak intensity of the third peak to the peak intensity of the first peak is called the third peak intensity ratio
  • sample 800C a peak was detected at the first peak position, but no peaks were detected at the second and third peak positions. In other words, in sample 800C, the first peak was detected, but the second and third peaks were not detected.
  • the ferroelectricity of the insulating layer 804 can be increased by lowering the substrate temperature when forming the conductive layer 805.
  • BL wiring, Cfe: capacitance element, PL: wiring, WL: wiring, 10: semiconductor device, 20: memory array, 21: drive circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 51: curve, 52: curve, 100a: capacitance element, 100b: capacitance element, 100: capacitance element, 110: conductive layer, 115a: conductive layer, 115b: conductive layer, 115F: conductive film, 115: conductive layer, 118 : layer, 120a: conductive layer, 120b: conductive layer, 120F: conductive film, 120: conductive layer, 128: layer, 130F: insulating film, 130: insulating layer, 140: insulating layer, 150a: memory cell, 150b: memory cell, 150c: memory cell,

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
PCT/IB2024/055384 2023-06-09 2024-06-03 半導体装置、半導体装置の作製方法 Ceased WO2024252246A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025525414A JPWO2024252246A1 (https=) 2023-06-09 2024-06-03

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023-095844 2023-06-09
JP2023095844 2023-06-09

Publications (1)

Publication Number Publication Date
WO2024252246A1 true WO2024252246A1 (ja) 2024-12-12

Family

ID=93795183

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2024/055384 Ceased WO2024252246A1 (ja) 2023-06-09 2024-06-03 半導体装置、半導体装置の作製方法

Country Status (2)

Country Link
JP (1) JPWO2024252246A1 (https=)
WO (1) WO2024252246A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
US9837435B1 (en) * 2017-01-20 2017-12-05 Phison Electronics Corp. Three-dimensional non-volatile memory structure and manufacturing method thereof
WO2022064306A1 (ja) * 2020-09-22 2022-03-31 株式会社半導体エネルギー研究所 強誘電体デバイス、および半導体装置
US20220359762A1 (en) * 2020-12-03 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for forming the same
WO2023042022A1 (ja) * 2021-09-17 2023-03-23 株式会社半導体エネルギー研究所 半導体装置、記憶装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
US9837435B1 (en) * 2017-01-20 2017-12-05 Phison Electronics Corp. Three-dimensional non-volatile memory structure and manufacturing method thereof
WO2022064306A1 (ja) * 2020-09-22 2022-03-31 株式会社半導体エネルギー研究所 強誘電体デバイス、および半導体装置
US20220359762A1 (en) * 2020-12-03 2022-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method for forming the same
WO2023042022A1 (ja) * 2021-09-17 2023-03-23 株式会社半導体エネルギー研究所 半導体装置、記憶装置

Also Published As

Publication number Publication date
JPWO2024252246A1 (https=) 2024-12-12

Similar Documents

Publication Publication Date Title
WO2024116037A1 (ja) 半導体装置
WO2024047487A1 (ja) 記憶装置
US20250151254A1 (en) Semiconductor device and method for manufacturing the semiconductor device
US20250212387A1 (en) Semiconductor device and method for manufacturing the semiconductor device
US20250126843A1 (en) Semiconductor device and method for manufacturing the semiconductor device
US20250133824A1 (en) Semiconductor device
JP7798787B2 (ja) 半導体装置
KR20240066264A (ko) 반도체 장치
WO2024252246A1 (ja) 半導体装置、半導体装置の作製方法
US20250226234A1 (en) Method for manufacturing stack and method for manufacturing semiconductor device
US20250185340A1 (en) Semiconductor device
US20250126777A1 (en) Electronic device, method for manufacturing the electronic device, semiconductor device, method for manufacturing the semiconductor device, and storage device
US20250113545A1 (en) Semiconductor device
TW202410417A (zh) 半導體裝置
WO2024134407A1 (ja) 半導体装置
CN118872402A (zh) 半导体装置及半导体装置的制造方法
KR20240149947A (ko) 반도체 장치
WO2024089571A1 (ja) 半導体装置、半導体装置の作製方法、及び電子機器
WO2025046432A1 (ja) 半導体装置、及び半導体装置の作製方法
CN118872401A (zh) 半导体装置
WO2024100489A1 (ja) 半導体装置、半導体装置の作製方法、及び電子機器
WO2024079585A1 (ja) トランジスタ及び記憶装置
WO2025027443A1 (ja) コンピュータ、情報処理装置、サーバ、及び記憶装置
CN118591879A (zh) 电子装置、电子装置的制造方法、半导体装置、半导体装置的制造方法、存储装置
CN118679862A (zh) 半导体装置及半导体装置的制造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24818875

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2025525414

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2025525414

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE