WO2024251239A1 - 集成电路组件、处理器和片上系统 - Google Patents

集成电路组件、处理器和片上系统 Download PDF

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Publication number
WO2024251239A1
WO2024251239A1 PCT/CN2024/097972 CN2024097972W WO2024251239A1 WO 2024251239 A1 WO2024251239 A1 WO 2024251239A1 CN 2024097972 W CN2024097972 W CN 2024097972W WO 2024251239 A1 WO2024251239 A1 WO 2024251239A1
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Prior art keywords
layer
wafer
wafer layer
layers
logic
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PCT/CN2024/097972
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English (en)
French (fr)
Inventor
张喆
李双辰
许晗
卓有为
魏学超
牛迪民
郑宏忠
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Alibaba China Co Ltd
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Alibaba China Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Definitions

  • the embodiments of the present disclosure relate to the field of computer technology, and more particularly to an integrated circuit component, a processor, and a system on chip.
  • 3D wafer-level packaging refers to the packaging technology of stacking two or more wafer layers in the same package in a vertical direction without changing the size of the package.
  • the main features of 3D wafer-level packaging include: multi-function, high performance, large capacity, and high density. Therefore, the integrated circuit components of 3D wafer-level packaging can provide larger on-chip storage capacity to meet the needs of basic model calculations, and 3D wafer-level packaging has become the current trend of technological development.
  • embodiments of the present disclosure provide an integrated circuit component, a processor, and a system on chip to at least partially solve the above problems.
  • an integrated circuit component comprising at least two wafer layers, each wafer layer comprising a front side and a back side, wherein, among the at least two wafer layers, the first wafer layer and the second wafer layer are stacked front to front, and the second wafer layer and the third wafer layer are stacked front to back respectively, the second wafer layer is processed by through silicon vias, a redistribution layer and a hybrid bonding, and the at least two wafer layers are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer.
  • the at least two wafer layers also include a third wafer layer, the second wafer layer and the third wafer layer are stacked front to back, and the other wafer layers among the at least three wafer layers except the second wafer layer are subjected to at least one of through silicon vias, redistribution layers and hybrid bonding processes.
  • the front side of the second wafer layer is subjected to hybrid bonding processing, and the back side of the second wafer layer is subjected to through silicon via, redistribution layer and hybrid bonding processing.
  • the component includes three wafer layers, the front side of the first wafer layer is subjected to hybrid bonding processing, and the front side of the third wafer layer is subjected to hybrid bonding processing.
  • pins are led out from the back side of the first wafer layer or the back side of the third wafer layer.
  • the three wafer layers are all wafers; or, the second wafer layer is a wafer, one of the first wafer layer and the third wafer layer is a chip, and the other is a wafer; or, the second wafer layer is a chip.
  • the data flow of the three wafer layers includes: the data flow from the first wafer layer to the second wafer layer passes through: a data source point, a hybrid bonding metal medium of the first wafer layer, a hybrid bonding metal medium of the second wafer layer, and a data target point; and/or the data flow from the second wafer layer to the first wafer layer passes through: a data source point, a hybrid bonding metal medium of the second wafer layer, a hybrid bonding metal medium of the first wafer layer, and a data target point; and/or the data flow from the second wafer layer to the third wafer layer passes through: a data source point, a through silicon via metal medium of the second wafer layer, a redistribution layer metal medium of the second wafer layer, a hybrid bonding metal medium of the second wafer layer, a hybrid bonding metal medium of the third wafer layer, and a data target point; and/or the data flow from the third wafer layer to the second wafer layer passes through: a data source point, a through
  • the data flow from the first wafer layer to the second wafer layer and then to the third wafer layer passes through: the data source point, the hybrid bonding metal medium of the first wafer layer, the hybrid bonding metal medium on the front of the second wafer layer, the through silicon via metal medium on the back of the second wafer layer, the redistribution layer metal medium on the back of the second wafer layer, the hybrid bonding metal medium on the back of the second wafer layer, the hybrid bonding metal medium on the back of the third wafer layer, and the data target point; and/or the data flow from the third wafer layer to the second wafer layer and then to the first wafer layer passes through: the data source point, the hybrid bonding metal medium of the third wafer layer, the hybrid bonding metal medium on the back of the second wafer layer, the redistribution layer metal medium on the back of the second wafer layer, the through silicon via metal medium on the back of the second wafer layer, the hybrid bonding metal medium on the front of the second wafer layer, the hybrid bonding metal medium of the first
  • At least one wafer layer among the three wafer layers is a logic layer, and the logic layer is connected to the pins.
  • the outer wafer layer of the three wafer layers is a logic layer, and the remaining wafer layers are storage layers.
  • the wafer layers on both sides of the three wafer layers are logic layers, and the wafer layer between the logic layers on both sides is a storage layer.
  • the three wafer layers are all logic layers.
  • the logic layer includes: at least one of a data flow logic unit, a computing logic unit or a storage logic unit, the data flow logic adopts a reduced instruction set stream artificial intelligence engine or an on-chip network; the computing logic adopts a resistive memory or a reduced instruction set; the storage logic adopts a resistive memory or a static random access memory; and the storage layer adopts a dynamic random access memory.
  • the configuration of the data flow logic unit includes: the type of domain-specific architecture, whether the storage architecture requires a register; if the logic layer includes the computing logic unit, the configuration of the computing logic unit includes: fixed precision, mixed precision, and the size of the computing storage array matches the bandwidth of the storage layer; if the logic layer includes the storage logic unit, the configuration of the storage logic unit includes: at least one of the storage array size and the storage array type; the configuration of the storage layer includes: the number of storage blocks, the number of corresponding hybrid bonded input and output ports, and whether the bandwidth can match the size of the computing storage array of the computing logic.
  • any one of the three wafer layers is a logic layer
  • any one of the three wafer layers adjusts the correspondence between each unit in the wafer layer and each unit in other wafer layers according to the yield of other wafer layers.
  • any one of the three wafer layers is a logic layer
  • the logic layer configures logic units according to requirements.
  • the logic layer configured in the three wafer layers reuses other wafer layers.
  • the number of hybrid bonding metal media and the number of through silicon via metal media on the three wafer layers are independently configured.
  • a processor comprising: an integrated circuit component according to the first aspect.
  • a system on chip comprising: at least one processor, wherein the processor is the processor described in the second aspect.
  • the integrated circuit component includes at least two wafer layers, each wafer layer includes a front side and a back side, wherein, in the at least two wafer layers, the first wafer layer and the second wafer layer are stacked front to front, the second wafer layer and the third wafer layer are stacked front to back, respectively, the second wafer layer is processed by through silicon vias, a redistribution layer and a hybrid bonding process, and at least two wafer layers are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer.
  • At least two wafer layers in the embodiment of the present disclosure are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer, thereby realizing 3D wafer-level packaging of multiple wafer layers.
  • the integrated circuit component of the embodiment of the present disclosure can provide a larger on-chip storage capacity to meet the needs of basic model calculations.
  • 1a to 1h are schematic diagrams of wafer layer processing.
  • FIG. 2 a is a schematic diagram of an integrated circuit component according to an embodiment of the present disclosure.
  • FIG. 2 b is a schematic diagram of another embodiment of an integrated circuit component according to the present disclosure.
  • FIG. 3 is a schematic diagram of a packaging process of an integrated circuit component according to another embodiment of the present disclosure.
  • 4a and 4b are schematic diagrams of two further embodiments of integrated circuit components according to the present disclosure.
  • 5a and 5c are schematic diagrams of three further embodiments of integrated circuit components according to the present disclosure.
  • FIG. 6 a is a schematic diagram of yet another embodiment of an integrated circuit component according to the present disclosure.
  • FIG. 6 b is a schematic block diagram of a data flow logic unit in a logic layer according to the present invention.
  • FIG. 6c is a schematic block diagram of an in-memory processing unit in a logic layer according to the present invention.
  • FIG. 6 d is a schematic block diagram of a storage layer according to the present invention.
  • FIG. 7a and 7b are schematic diagrams of two further embodiments of integrated circuit components according to the present disclosure.
  • FIG. 8 is a schematic diagram of yet another embodiment of an integrated circuit component according to the present disclosure.
  • FIGS. 9a and 9b are schematic diagrams of yet another embodiment of an integrated circuit component according to the present disclosure.
  • FIG. 10 is a schematic diagram of yet another embodiment of an integrated circuit component according to the present disclosure.
  • FIG. 11 is a structural block diagram of a processor according to another embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a system on chip according to another embodiment of the present disclosure.
  • Coupled can be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other.
  • Connected can be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other.
  • Coupled can be used to indicate that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and/or that two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).
  • the terms “above,””below,””between,” and “on” refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy.
  • one material or material disposed above or below another material may be in direct contact, or may have a
  • a material disposed between two materials or materials may be in direct contact with both layers, or may have one or more intermediate layers.
  • a first material or material "on” a second material or material is in direct contact with the second material/materials.
  • a list of items connected by the term “at least one of” or “one or more of” may mean any combination of the listed items.
  • the phrase “at least one of A, B, or C” may mean A; B; C; A and B; A and C; B and C; or A, B, and C.
  • circuit or “module” may refer to one or more passive and/or active components that are arranged to cooperate with each other to provide a desired functionality.
  • signal may refer to at least one current signal, voltage signal, or magnetic signal.
  • substantially “close,” “approximately,” “close to,” and “approximately” generally refer to within +/- 10% of a target value.
  • the wafer layer is composed of pure silicon (Si) and includes a front side and a back side.
  • the front side of the wafer layer is the main working surface for chip production on the wafer.
  • the front side usually has a specific orientation and lattice structure, and is configured to grow or build transistors, circuits and other semiconductor devices thereon, that is, a wiring layer is provided on the front side.
  • the back side of the wafer layer is also called the back surface or backing, which is opposite to the front side.
  • the back side is usually flat, has no crystal structure, and is configured to provide mechanical stability for supporting and handling the wafer.
  • the back side usually has no circuits or devices, and may be specially treated or coated to meet specific needs, such as enhancing adhesion or improving thermal conduction.
  • 3D wafer-level packaging refers to an integrated circuit component consisting of two or more wafer layers.
  • Hybrid bonding is a method to obtain denser interconnections between stacked chips.
  • the hybrid bonding process allows one wafer layer to be stacked with the front side facing the front side of another wafer layer.
  • the interlayer wiring between the front side of one wafer layer and the front side of another wafer layer is formed by hybrid bonding.
  • the bonding points on the front side of one wafer layer are bonded to the bonding points on the front side of another wafer layer by position alignment.
  • Through-Silicon Vias mainly functions as electrical extension and interconnection on the Z-axis (the coordinate axis perpendicular to the plane of the wafer layer).
  • the redistribution layer plays the role of electrical extension and interconnection of the XY plane (the plane where the wafer layer is located).
  • RDL is the most critical technology. Through RDL, the IO Pad is fanned in or out to form different types of wafer-level packaging.
  • interlayer wiring between the back side of one wafer layer and the front side of another wafer layer is formed by through silicon vias, rewiring, and hybrid bonding.
  • Through silicon vias can connect the front side and the back side of one wafer layer, and rewiring is used to re-form wiring on the back side of one wafer layer based on the position of the through silicon vias, so that the back side of one wafer layer is hybrid bonded with the front side of another wafer layer through rewiring.
  • the intra-layer wiring of the first wafer layer (for example, at least some of the wiring nodes in the intra-layer wiring serve as bonding points) is connected to the intra-layer wiring of the second wafer layer (for example, at least some of the wiring nodes in the intra-layer wiring serve as bonding points) through front-to-front inter-layer wiring.
  • the intra-layer wiring of the second wafer layer is connected to the intra-layer wiring of the third wafer layer through the front-to-back inter-layer wiring.
  • the intra-layer wiring of the first wafer layer and the intra-layer wiring of the third wafer layer are connected through the inter-layer wiring between the first wafer layer and the second wafer layer and the inter-layer wiring between the second wafer layer and the third wafer layer.
  • Figures 1a to 1h in which the arrows indicate the direction of the front side of the wafer layer; 11 indicates Si dielectric; 12 indicates the metal dielectric for transmitting electrical signals, including: metal layer, through silicon via, redistribution layer, hybrid bonding, pins, etc.; the other parts indicate insulating dielectrics.
  • Figure 1a is the initial wafer layer
  • Figure 1b is the wafer layer after hybrid bonding.
  • Figure 1c for the initial wafer layer
  • Figure 1d for the wafer layer after through silicon via.
  • Figure 1e for the initial wafer layer, and Figure 1f for the wafer layer after redistribution layer lead-out pins.
  • Figure 1g is a wafer layer with through silicon via, redistribution layer, and hybrid bonding on the back side, and hybrid bonding on the front side.
  • Figure 1h is a wafer layer with through silicon via, redistribution layer, and hybrid bonding on the back side.
  • FIG2a shows an integrated circuit component of an embodiment
  • the integrated circuit component includes at least two wafer layers, namely, W1, W2, W3, ... Wn, n ⁇ 2.
  • Each wafer layer includes a front side (the outer surface opposite to the outer surface of the substrate where Si is located as shown in the figure) and a back side (the outer surface of the substrate where Si is located as shown in the figure).
  • the first wafer layer W1 and the second wafer layer W2 are stacked front to front, and the second wafer layer W2 and the third wafer layer W3 are stacked front to back in sequence.
  • the second wafer layer W2 is processed by through silicon vias, a redistribution layer and a hybrid bonding process, and at least two wafer layers are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer.
  • At least two wafer layers are interconnected through silicon vias, redistribution layers, and hybrid bonding of each layer, thereby achieving 3D wafer-level packaging of multiple wafer layers.
  • the front side of the wafer layer is the side where the wiring layer is set, and denser and more reliable wiring is achieved through hybrid bonding on the front side of the wafer layer, which is beneficial to reduce the data transmission delay of the front side wiring of the wafer layer and improve the data transmission efficiency, thereby providing a larger on-chip storage capacity to meet the needs of basic model calculations.
  • the back side of the wafer layer is one side of the substrate.
  • Through silicon via process is performed on the back side of the wafer layer to guide the wiring to the back side of the wafer layer.
  • the back side of the wafer layer is fully utilized while being compatible with related processes to achieve denser and more reliable wiring.
  • denser and more reliable wiring is achieved on the back side of the wafer layer in the middle layer, and the wiring is led out of the 3D wafer package through silicon vias on the back side of the wafer layer used as the back side of the 3D wafer package.
  • the electrode pad Package Assembly Drawing, PAD
  • PAD Package Assembly Drawing
  • FIG2b shows another integrated circuit component provided by an embodiment of the present disclosure, wherein the integrated circuit component includes at least three wafer layers, namely W1, W2, W3, ... Wn, n ⁇ 3.
  • the first wafer layer W1 is stacked front to front with the second wafer layer W2, and the second wafer layer W2 is stacked front to back with the third wafer layer W3.
  • the third wafer layer W3 is stacked front to back with the fourth wafer layer W4, ..., the N-1th wafer layer Wn-1 is stacked front to back with the Nth wafer layer Wn.
  • the second wafer layer is processed by through silicon vias, a redistribution layer, and a hybrid bonding process
  • the other wafer layers are processed by at least one of through silicon vias, a redistribution layer, and a hybrid bonding process.
  • at least three wafer layers are interconnected through the through silicon vias, redistribution layers, and hybrid bonding of each layer, thereby realizing 3D wafer-level packaging of multiple wafer layers.
  • the front side of the wafer layer is the side where the wiring layer is provided, and denser and more reliable wiring is achieved on the front side of the wafer layer through hybrid bonding, which is beneficial to reducing the data transmission delay of the front wiring of the wafer layer and improving the data transmission efficiency, thereby providing a larger on-chip storage capacity to meet the needs of basic model calculations.
  • the integrated circuit component of the embodiment of the present disclosure includes three wafer layers, namely W1, W2, and W3.
  • FIG3a is the initial first wafer layer W1.
  • FIG3b is the front side of the first wafer layer W1 after hybrid bonding.
  • FIG3c is the front side of the second wafer layer W2 after hybrid bonding, and stacked face to face with the front side of the first wafer layer W1 after hybrid bonding.
  • FIG3d is the back side of the second wafer layer W2 in FIG3c after through silicon via, redistribution layer and hybrid bonding.
  • FIG3e is the front side of the third wafer layer W3 after hybrid bonding, and the front side of the third wafer layer W3 is stacked with the back side of the second wafer layer W2.
  • the first wafer layer and the third wafer layer are interconnected through hybrid bonding, and the second wafer layer is interconnected through silicon vias, a redistribution layer and hybrid bonding, so that the packaging process is simpler and the packaging cost is reduced.
  • hybrid bonding is used to achieve denser and more reliable wiring on the front side of the wafer layer.
  • the front-to-front stacking process enhances the data transmission efficiency between adjacent wafer layers and reduces the delay between different wafer layers.
  • the adjacent wafer layers serve as logic layers and storage layers respectively, which provides data reading and writing efficiency.
  • data transmission efficiency is also provided.
  • the adjacent wafer layers are respectively used as the logic layer (i.e., the logic process layer) and the storage layer (i.e., the storage process layer) to provide data reading and writing efficiency, and the adjacent wafer layers are respectively used as the logic layer or the storage layer to provide data transmission efficiency.
  • the back side of the first wafer layer W1 leads to the first pin D1; see Figure 4b, the back side of the third wafer layer W3 leads to the second pin D2.
  • the present disclosure facilitates the pin design of integrated circuit components.
  • all three wafer layers are wafers or the second wafer layer is a wafer, and one of the first wafer layer and the third wafer layer is a chip, and the other is a wafer.
  • the three wafer layers are all wafers; referring to Figure 5b, the first wafer layer W1 and the second wafer layer W2 are wafers, and the third wafer layer W3 is a chip; referring to Figure 5c, the first wafer layer W1 is a chip, and the second wafer layer W2 and the third wafer layer W3 are wafers.
  • the implementation methods of the three-layer wafer layer of the integrated circuit component of the embodiment of the present disclosure are diversified, and one of the first wafer layer and the third wafer layer can use chips.
  • the packaging method of the embodiment of the present disclosure is more flexible and can provide more diverse 3D integrated packaging design options.
  • all three wafer layers are wafers, which reduces the alignment process requirements of the three wafer layers.
  • factors other than the alignment process requirements e.g., power efficiency indicators
  • the integrated circuit components for example, mechanical properties, compatibility with traditional processes, electrical properties (e.g., data transmission delay), heat dissipation performance, etc. can be considered.
  • the second wafer layer is a wafer
  • one of the first wafer layer and the third wafer layer is a chip
  • the other is a wafer. That is, the chip is on the outside of the integrated circuit component, which reduces the alignment process requirements between the wafer layers compared to the case where the chip is between the wafers. Since the chip can be a wafer layer completed by packaging (for example, using 2D or 2.5D packaging), the packaging method is more flexible and can provide more diverse 3D integrated packaging design options.
  • the second wafer layer is a chip.
  • the chip alignment process between the wafer layers is more demanding than the case where the chip is on one side, if Focusing on other factors and placing the chip in the middle wafer layer (for example, placing the chip in the storage layer will result in better heat dissipation performance) will still ensure other performance indicators.
  • the wafer layer completed by packaging (for example, using 2D or 2.5D packaging) is fully utilized, making the packaging method more flexible and providing more diverse 3D integrated packaging design options.
  • the data flow from the first wafer layer W1 to the second wafer layer W2 passes through: the data source point, the hybrid bonding metal medium of the first wafer layer W1, the hybrid bonding metal medium of the second wafer layer W2, and the data target point.
  • the delay is small.
  • the data flow from the second wafer layer W2 to the first wafer layer W1 passes through: the data source point, the hybrid bonding metal medium of the second wafer layer W2, the hybrid bonding metal medium of the first wafer layer W1, and the data target point.
  • the delay is small.
  • hybrid bonding is used through a front-to-front stacking setup to reduce the delay between different wafer layers.
  • the data flow from the second wafer layer W2 to the third wafer layer W3 passes through: the data source point, the through silicon via metal medium of the second wafer layer W2, the redistribution layer metal medium of the second wafer layer W2, the hybrid bonding metal medium of the second wafer layer W2, the hybrid bonding metal medium of the third wafer layer W3, and the data target point.
  • the delay is in progress.
  • the data flow from the third wafer layer W3 to the second wafer layer W2 passes through: the data source point, the hybrid bonding metal medium of the third wafer layer W3, the hybrid bonding metal medium of the second wafer layer W2, the redistribution layer metal medium of the second wafer layer W2, the through silicon via metal medium of the second wafer layer W2, and the data target point.
  • the delay is in progress.
  • the back side of the wafer layer is pre-processed based on the redistribution layer and the through silicon via process, and then hybrid bonding is adopted in the front-to-back stacking setting to reduce the delay between different wafer layers.
  • the pre-processing of the redistribution layer and through-silicon via process will increase the delay, but it is compatible with related processes while ensuring the processing efficiency and mechanical properties of the 3D wafer.
  • the data flow from the first wafer layer W1 to the second wafer layer W2 and then to the third wafer layer W3 passes through: data source point, hybrid bonding metal medium of the first wafer layer W1, hybrid bonding metal medium on the front of the second wafer layer W2, through silicon via metal medium on the back of the second wafer layer W2, redistribution layer metal medium on the back of the second wafer layer W2, hybrid bonding metal medium on the back of the second wafer layer W2, hybrid bonding metal medium on the third wafer layer W3, and data target point.
  • the delay is large.
  • the data flow from the third wafer layer W3 to the second wafer layer W2, and then to the first wafer layer W1 passes through: the data source point, the hybrid bonding metal medium of the third wafer layer W3, the hybrid bonding metal medium on the back of the second wafer layer W2, the redistribution layer metal medium on the back of the second wafer layer W2, the through silicon via metal medium on the back of the second wafer layer W2, the The hybrid bonding metal medium on the front of the second wafer layer W2, the hybrid bonding metal medium on the first wafer layer W1, and the data target point.
  • the delay is large.
  • the delay between non-adjacent different wafer layers may be greater than the delay between adjacent different wafer layers.
  • the integrated circuit component of the disclosed embodiment realizes data flow between three wafer layers.
  • the disclosed embodiment can design data flow between three wafer layers as needed, so that the delay of data flow meets the needs of data transmission.
  • At least one wafer layer among the three wafer layers is a logic layer, and the remaining wafer layers are storage layers, and the logic layer is connected to the pins.
  • the outer wafer layer of the three wafer layers is a logic layer, and the remaining wafer layers are storage layers.
  • the heat dissipation requirement of the logic layer is higher than that of the storage layer, which ensures the heat dissipation performance of the integrated circuit components.
  • the logic layer has a larger proportion and is more suitable for configuration into a DSA such as a CPU or other DSA with a more complex control process.
  • the first wafer layer is a logic layer
  • the second wafer layer is a storage layer
  • the third wafer layer is a storage layer.
  • the first wafer layer is a storage layer
  • the second wafer layer is a storage layer
  • the third wafer layer is a logic layer.
  • the wafer layers on both sides of the three wafer layers are logic layers, and the wafer layer between the two logic layers is a storage layer, so that the heat dissipation performance of the integrated circuit component is optimized.
  • the outer wafer layer of the three wafer layers is the logic layer, and the remaining wafer layers are the storage layer and the logic layer.
  • the heat dissipation requirement of the logic layer is higher than that of the storage layer, and the heat dissipation capacity of the storage layer is higher than that of the logic layer.
  • the storage layer can be beneficial to the heat dissipation of the logic layer, thereby ensuring the heat dissipation performance of the integrated circuit component to a certain extent.
  • the proportion of the storage layer is relatively large, and it is more suitable to be configured as a DSA with higher computing requirements such as a GPU or TPU.
  • the chip is configured as a logic layer
  • the wafer is configured as a storage layer
  • the chip is located on the outside of the integrated circuit component
  • the wafer is located in the middle layer of the component, thereby ensuring the heat dissipation performance and reducing process requirements such as alignment process compared to the case where the chip is located in the middle layer of the integrated circuit component.
  • the first wafer layer is a logic layer
  • the second wafer layer is a logic layer
  • the third wafer layer is a storage layer.
  • the first wafer layer is a storage layer
  • the second wafer layer is a logic layer
  • the third wafer layer is a logic layer.
  • the first wafer layer is a logic layer
  • the second wafer layer is a logic layer
  • the third wafer layer is a logic layer. All three wafer layers are logic layers, and the heat dissipation performance is poorer than the above example, but the low-latency interconnection between the logic layers is greatly improved, achieving better data processing capabilities and process control performance than the above example.
  • the pins ( D1 or D2 ) connected to the logic layer are all located on the outer layers of the three wafer layers.
  • Table 1 the selection of the logic layer and the storage layer and the heat dissipation are shown in Table 1.
  • the six options given in Table 1 correspond to the above six embodiments respectively.
  • the first, third, and sixth embodiments have excellent heat dissipation
  • the second and fifth embodiments are excellent
  • the fourth embodiment is good.
  • the integrated circuit assembly of the embodiment of the present disclosure can design three wafer layers as logic layers or storage layers according to heat dissipation requirements.
  • the embodiment of the present disclosure provides a more flexible design solution.
  • the logic layer includes: one of a data flow logic unit, a computing logic unit or a storage logic unit, the data flow logic can adopt PE or on-chip network; the computing logic adopts resistive random access memory-processing-in-memory (Resistive Random Access Memory-Processing-in-Memory, RRAM-PIM) or high-performance fifth-generation reduced instruction set (High performance RISC-V, HP-RV); the storage logic adopts resistive random access memory (used as memory) or static random access memory; the storage logic adopts RRAM-Memory (Resistive Random Access Memory-Memory, resistive random access memory-memory) or SRAM; the storage layer adopts DRAM technology.
  • the computing logic adopts resistive random access memory-processing-in-memory (Resistive Random Access Memory-Processing-in-Memory, RRAM-PIM) or high-performance fifth-generation reduced instruction set (High performance RISC-V, HP-RV)
  • the data flow logic in the text only shows an example of a DSA or an on-chip network or an accelerator, and can also be replaced by a data flow logic unit of other DSAs or accelerators.
  • the HP-RV in the text is an example of a CPU, which can be replaced by a computing logic unit of various types of CPUs.
  • the storage layer uses dynamic random access memory.
  • the logic layer configures logic units according to requirements.
  • the disclosed embodiments can configure the logic units of the logic layer more flexibly, so that the integrated circuit components can provide more diverse memory forms.
  • the disclosed embodiments can provide dedicated memory or a dedicated domain-specific architecture (DSA) engine for PE (Processing Element) by configuring the logic units of the logic layer.
  • DSA domain-specific architecture
  • any one of the three wafer layers is configured according to the requirements. Therefore, the embodiments of the present disclosure can provide various 3D integration design options for advanced artificial intelligence models (GPT/LLM).
  • GPS/LLM advanced artificial intelligence models
  • the three-layer wafer layer includes a first logic layer and a second logic layer, and the first logic layer and the second logic layer are different units in a data flow logic unit, a computing logic unit, and a storage logic unit. Integrating the logic layers and storage layers of different logics into the integrated circuit component improves the data reading and writing efficiency, computing efficiency, and overall data processing efficiency.
  • the data flow logic unit and the computing logic unit combine the advantages of parallel computing and serial computing
  • the data flow logic unit and the storage computing unit combine the advantages of data reading and writing
  • the computing logic unit and the storage computing unit combine the advantages of data reading and writing, and so on.
  • Table 2 provides four types of options as examples of three-layer wafer layers, but the embodiments of the present disclosure are not limited to these four types.
  • each wafer layer in the integrated circuit component can be a logic layer or a memory layer, and the integrated circuit component includes both the logic layer and the memory layer.
  • Example 1 In a specific implementation of the present disclosure, a specific description is given through Example 1.
  • the first wafer layer W1 is PE
  • the second wafer layer W2 is DRAM
  • the third wafer layer W3 is RRAM-PIM (Resistive Random Access Memory-Processing-in-Memory)/SRAM.
  • the first wafer layer W1 is a logic layer, including a data flow logic unit
  • the second wafer layer W2 is a storage layer, including a memory block
  • the third wafer layer W3 is a logic layer, including a computing logic unit.
  • the first wafer layer W1 is PE, that is, the first wafer layer W1 includes a data flow logic unit.
  • the data flow logic unit of the type of Domain-Specific Architecture includes a computing logic subunit, and underlying modules such as a memory controller and/or a physical layer.
  • the computing logic subunit includes, but is not limited to: a vector processing unit (VPU) or a general matrix matrix multiplication (GEMM), etc.
  • VPU vector processing unit
  • GEMM general matrix matrix multiplication
  • the computing logic subunit performs memory access to the memory block in the storage layer through the memory controller via inter-layer wiring (e.g., 3D interconnection).
  • the data flow logic unit may also include a scratchpad, which may be a local cache or a shared cache in the computing logic subunit.
  • the second wafer layer W2 is DRAM, that is, the second wafer layer W2 includes storage logic units.
  • the configuration of the storage layer includes: the number of memory banks, the number of corresponding hybrid bonded input and output (HB IO), and whether the bandwidth can match the size of the computing storage array of the computing logic. More specifically, each memory bank is configured with functional modules such as decoding/control/buffering.
  • the third wafer layer W3 is RRAM-PIM/SRAM, that is, the third wafer layer W3 includes a computing logic unit/storage logic unit.
  • the computing logic unit is an in-memory processing unit, and the configuration of the in-memory processing unit includes a computing subunit, and the computing subunit includes an integer (Integral, INT) precision subunit and/or a floating point (BF (brain float)/FP (floating point) precision subunit).
  • the computing subunit includes an in-memory computing (Compute In Memory, CIM) unit array (Array), and the computing subunit can also be configured with a peripheral circuit (for example, including a coprocessor interface) module, a bus-based direct memory access (DMA) module, and underlying modules such as a memory controller and/or a physical layer.
  • CIM Computer In Memory
  • Array an in-memory computing (Compute In Memory, CIM) unit array (Array)
  • Array In-memory computing
  • peripheral circuit for example, including a coprocessor interface
  • DMA bus-based direct memory access
  • underlying modules such as a memory controller and/or a physical layer.
  • each data flow logic unit is connected by intra-layer wiring; in the second wafer layer W2, each memory block is connected by intra-layer wiring; in the third wafer layer W3, each computing logic unit/storage logic unit is connected by intra-layer wiring. Further, the data flow logic unit directly or indirectly accesses the second wafer layer through the inter-layer wiring between the first wafer layer and the second wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the second wafer layer.
  • the data flow logic unit accesses the third wafer layer through the inter-layer wiring between the first wafer layer and the third wafer layer, and then accesses the corresponding computing logic unit/storage logic unit through the intra-layer wiring of the third wafer layer, and the computing logic unit/storage logic unit is used as a cache of the data flow logic unit.
  • the computing logic unit/storage logic unit accesses the second wafer layer through the inter-layer wiring between the third wafer layer and the second wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the second wafer layer.
  • the first wafer layer W1 is PE
  • the second wafer layer W2 is SRAM/RRAM-PIM
  • the third wafer layer W3 is DRAM.
  • the first wafer layer W1 is a logic layer, including data flow logic units
  • the second wafer layer W2 is a logic layer, including storage logic units or computing logic units
  • the third wafer layer W3 is a storage layer, including memory blocks.
  • each data flow logic unit is connected by intra-layer wiring; in the second wafer layer W2, each computing logic unit/storage logic unit is connected by intra-layer wiring; in the third wafer layer W3, each memory block is connected by intra-layer wiring.
  • the data flow logic unit accesses the second wafer layer through the inter-layer wiring between the first wafer layer and the second wafer layer, and then accesses the corresponding computing logic unit/storage logic unit through the intra-layer wiring of the second wafer layer, and the computing logic unit/storage logic unit is used as a cache of the data flow logic unit.
  • the computing logic unit/storage logic unit accesses the third wafer layer through the inter-layer wiring between the second wafer layer and the third wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the third wafer layer.
  • the first wafer layer W1 is PE
  • the second wafer layer W2 is DRAM
  • the third wafer layer W3 is DRAM.
  • the first wafer layer W1 is a logic layer, including data flow logic units
  • the second wafer layer W2 is a storage layer, including memory blocks
  • the third wafer layer W3 is a storage layer, including memory blocks.
  • each data flow logic unit is connected through intra-layer wiring; in the second wafer layer W2, each memory block is connected through intra-layer wiring; in the third wafer layer W3, each memory block is connected through intra-layer wiring.
  • the data flow logic unit directly or indirectly accesses the second wafer layer through the inter-layer wiring between the first wafer layer and the second wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the second wafer layer.
  • the data flow logic unit directly or indirectly accesses the third wafer layer through the inter-layer wiring between the first wafer layer and the third wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the third wafer layer.
  • the first wafer layer W1 is PE
  • the second wafer layer W2 is DRAM
  • the third wafer layer W3 is HP-RV (or other CPU).
  • the first wafer layer W1 is a logic layer, including data flow logic units
  • the second wafer layer W2 is a storage layer, including memory blocks
  • the third wafer layer W3 is a logic layer, including computing logic units.
  • each data flow logic unit is connected by intra-layer wiring; in the second wafer layer W2, each memory block is connected by intra-layer wiring; in the third wafer layer W3, each computing logic unit is connected by intra-layer wiring.
  • the data flow logic unit directly or indirectly accesses the second wafer layer through the inter-layer wiring between the first wafer layer and the second wafer layer, and then accesses the corresponding memory block through the intra-layer wiring of the second wafer layer.
  • the data flow logic unit accesses the third wafer layer through the inter-layer wiring between the first wafer layer and the third wafer layer, and then accesses (for example, through DMA) the corresponding computing logic unit through the intra-layer wiring of the third wafer layer.
  • the computing logic unit can be a processing unit of the control plane, and the data flow logic unit can be a processing unit of the data plane, which is used to assist the data processing of the control plane.
  • the computing logic unit accesses the second wafer layer through the inter-layer wiring between the third wafer layer and the second wafer layer, and then accesses (for example, through DMA) the corresponding memory block through the intra-layer wiring of the second wafer layer.
  • Network on Chip can be used as an example of intra-layer wiring in the first wafer layer.
  • Figure 7a is a schematic diagram of the one-to-one correspondence between the first wafer layer W1, the second wafer layer W2, and the third wafer layer W3;
  • Figure 7b is a schematic diagram of the non-one-to-one correspondence between the first wafer layer W1, the second wafer layer W2, and the third wafer layer W3.
  • any one of the three wafer layers when any one of the three wafer layers is a logic layer, it includes at least two Types of logic units.
  • a schematic diagram of heterogeneity among the first wafer layer W1 , the second wafer layer W2 , and the third wafer layer W3 , that is, the first wafer layer W1 includes two types of logic units, RRAM-PIM and SRAM.
  • any one of the three wafer layers adjusts the correspondence between each unit in the wafer layer and each unit in the other wafer layers according to the yield of the other wafer layers.
  • bad block 1 may exist in Example 1, since the RRAM-PIM yield of the third wafer layer W3 is relatively low, bad block 1 may exist.
  • the non-bad block 2 between the RRAM-PIM of the third wafer layer W3 can be selected more flexibly through the rewiring layer to replace the bad block 1 for correspondence.
  • the bare die of the third wafer layer W3 has been manufactured, and the bare die of the third wafer layer W3 can be flexibly processed without changing the bare die of the third wafer layer W3, which is compatible with the production process of the bare die of the third wafer layer W3, reduces the yield standard for the third wafer layer, and ensures a lower processing cost for the integrated circuit component.
  • the logic layer when any one of the three wafer layers is a logic layer, the logic layer can be configured with logic units based on demand.
  • the logic layer configured in the three wafer layers reuses other wafer layers.
  • the third wafer layer W3 is configured with a customized domain-specific architecture (DSA).
  • DSA domain-specific architecture
  • the customized third wafer layer W3 can reuse the completed first wafer layer W1 and second wafer layer W2. That is, no matter what kind of domain-specific architecture (DSA) is customized for the third wafer layer W3, the completed first wafer layer W1 and second wafer layer W2 can be reused.
  • the disclosed embodiment is a non-von Neumann architecture, thereby reducing the storage bottleneck problem caused by data movement.
  • the multi-layer 3D heterogeneous data flow architecture provided by the disclosed embodiment provides 3D memory to improve the memory of the system on chip and meet the large memory requirements of the basic model.
  • the diversified configuration of the logic layer of the disclosed embodiment provides various 3D integration design options for advanced artificial intelligence models (GPT/LLM).
  • the processor 1100 of this embodiment includes: a processor core 1101 and an integrated circuit component 1102 .
  • the system on chip 1200 of this embodiment includes multiple processors 1210 .
  • each step in the program can refer to the corresponding description of the corresponding steps and units in the above method embodiment, which will not be repeated here.
  • the specific working process of the above-described devices and modules can refer to the corresponding process description in the above method embodiment, which will not be repeated here.
  • the above-described methods according to the embodiments of the present disclosure may be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium downloaded over a network and will be stored in a local recording medium, so that the methods described herein may be stored in a computer using a general-purpose computer, a dedicated processor, or a programmable or dedicated Such software processing on a recording medium with hardware (such as an ASIC or FPGA).
  • a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk
  • computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium downloaded over a network and will be stored in a local recording medium
  • Such software processing on a recording medium with hardware such as an ASIC or FPGA
  • a computer, processor, microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code, which, when accessed and executed by the computer, processor or hardware, implements the methods described herein.
  • a storage component e.g., RAM, ROM, flash memory, etc.
  • software or computer code which, when accessed and executed by the computer, processor or hardware, implements the methods described herein.
  • the execution of the code converts the general-purpose computer into a special-purpose computer configured to perform the methods shown herein.
  • the integrated circuit component includes at least two wafer layers, each wafer layer includes a front side and a back side, wherein, in the at least two wafer layers, the first wafer layer and the second wafer layer are stacked front to front, the second wafer layer and the third wafer layer are stacked front to back, respectively, the second wafer layer is processed by through silicon vias, a redistribution layer and a hybrid bonding process, and at least two wafer layers are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer.
  • At least two wafer layers in the embodiments of the present disclosure are interconnected through the through silicon vias, the redistribution layer and the hybrid bonding of each layer, thereby realizing 3D wafer-level packaging of multiple wafer layers, and the integrated circuit component of the embodiments of the present disclosure can provide a larger on-chip storage capacity to meet the needs of basic model calculations.

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Abstract

本公开实施例提供一种集成电路组件、处理器和片上系统，所述集成电路组件包括至少两层晶圆层，每层晶圆层包括正面与背面，其中，在所述至少两层晶圆层中，第一层晶圆层与第二层晶圆层正面对正面堆叠，所述第二层晶圆层和所述第三晶圆层依次为正面对背面堆叠，所述第二层晶圆层经过硅通孔、重布线层以及混合键合处理，所述至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。

Description

集成电路组件、处理器和片上系统
本公开要求于2023年06月07日提交中国专利局、申请号202310673218.2、申请名称“集成电路组件、处理器和片上系统”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及计算机技术领域，尤其涉及一种集成电路组件、处理器和片上系统。
背景技术
3D晶圆级封装，是指在不改变封装体尺寸的前提下，在同一个封装体内于垂直方向叠放两层以上晶圆层的封装技术。3D晶圆级封装的主要特点包括：多功能、高效能、大容量、高密度。因此，3D晶圆级封装的集成电路组件能够提供更大的片上存储容量以满足基础模型计算的需求，3D晶圆级封装成为目前技术发展的趋势。
因此，3D晶圆级封装的集成电路组件如何构建数据流架构成为现有技术中亟待解决的技术问题。
发明内容
有鉴于此，本公开实施例提供一种集成电路组件、处理器和片上系统，以至少部分解决上述问题。
根据本公开实施例的第一方面，提供了一种集成电路组件，包括至少两层晶圆层，每层晶圆层包括正面与背面，其中，在所述至少两层晶圆层中，第一层晶圆层与第二层晶圆层正面对正面堆叠，所述第二层晶圆层和所述第三晶圆层依次为正面对背面堆叠，所述第二层晶圆层经过硅通孔、重布线层以及混合键合处理，所述至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。
在本公开的另一实现方式中，所述至少两层晶圆层还包括第三层晶圆层，所述第二层晶圆层与所述第三层晶圆层正面对背面堆叠，所述至少三层晶圆层中除所述第二层晶圆层以外的其他晶圆层经过硅通孔、重布线层以及混合键合处理中至少其一。
在本公开的另一实现方式中，所述第二层晶圆层的正面经过混合键合处理，所述第二层晶圆层的背面经过硅通孔、重布线层以及混合键合处理。
在本公开的另一实现方式中，所述组件包括三层晶圆层，所述第一层晶圆层的正面经过混合键合处理，所述第三层晶圆层的正面经过混合键合处理。
在本公开的另一实现方式中，所述第一层晶圆层的背面或所述第三层晶圆层的背面引出管脚。
在本公开的另一实现方式中，所述三层晶圆层均为晶圆片；或者，所述第二层晶圆层为晶圆片，所述第一层晶圆层和所述第三层晶圆层其中之一为芯片，另一个为晶圆片；或者，所述第二层晶圆层为芯片。
在本公开的另一实现方式中，所述三层晶圆层的数据流动包括：所述第一层晶圆层到第二层晶圆层的数据流动经过：数据源点、第一层晶圆层的混合键合金属介质、第二层晶圆层的混合键合金属介质、数据目标点；和/或所述第二层晶圆层到第一层晶圆层的数据流动经过：数据源点、第二层晶圆层的混合键合金属介质、第一层晶圆层的混合键合金属介质、数据目标点；和/或所述第二层晶圆层到第三层晶圆层的数据流动经过：数据源点、第二层晶圆层的硅通孔金属介质、第二层晶圆层的重布线层金属介质、第二层晶圆层的混合键合金属介质、第三层晶圆层的混合键合金属介质、数据目标点；和/或所述第三层晶圆层到第二层晶圆层的数据流动经过：数据源点、第三层晶圆层的混合键合金属介质、第二层晶圆层的混合键合金属介质、第二层晶圆层的重布线层金属介质、第二层晶圆层的硅通孔金属介质、数据目标点；和/或所述第一层晶圆层到第二层晶圆层，再到第三层晶圆层的数据流动经过：数据源点、第一层晶圆层的混合键合金属介质、第二层晶圆层正面的混合键合金属介质、第二层晶圆层背面的硅通孔金属介质、第二层晶圆层背面的重布线层金属介质、第二层晶圆层背面的混合键合金属介质、第三层晶圆层的混合键合金属介质、数据目标点；和/或所述第三层晶圆层到第二层晶圆层，再到第一层晶圆层的数据流动经过：数据源点、第三层晶圆层的混合键合金属介质、第二层晶圆层背面的混合键合金属介质、第二层晶圆层背面的重布线层金属介质、第二层晶圆层背面的硅通孔金属介质、第二层晶圆层正面的混合键合金属介质、第一层晶圆层的混合键合金属介质、数据目标点。
在本公开的另一实现方式中，所述三层晶圆层中至少一层晶圆层为逻辑层，所述逻辑层与所述管脚连接。
在本公开的另一实现方式中，所述三层晶圆层中的处于外侧的晶圆层为逻辑层，其余晶圆层为存储层。
在本公开的另一实现方式中，所述三层晶圆层中两侧的晶圆层均为逻辑层，两侧的逻辑层之间的晶圆层为存储层。
在本公开的另一实现方式中，所述三层晶圆层均为逻辑层。
在本公开的另一实现方式中，所述逻辑层包括：数据流逻辑单元、计算逻辑单元或者存储逻辑单元中至少其一，所述数据流逻辑采用精简指令集流人工智能引擎或者片上网络；所述计算逻辑采用阻变式存储器或者精简指令集；所述存储逻辑采用阻变式存储器或者静态随机存取存储器；所述存储层采用动态随机存取内存。
在本公开的另一实现方式中，若所述逻辑层包括所述数据流逻辑单元，则数据流逻辑单元的配置包括：领域专用架构的类型、存储架构是否需要暂存器；若所述逻辑层包括所述计算逻辑单元，则计算逻辑单元的配置包括：固定精度、混合精度、计算存储阵列的大小与所述存储层的带宽匹配；若所述逻辑层包括所述存储逻辑单元，则存储逻辑单元的配置包括：存储阵列大小和存储阵列种类中的至少一者；所述存储层的配置包括：存储块的数量，对应的混合键合输入输出口的数量以及带宽是否能与所述计算逻辑的计算存储阵列的大小匹配。
在本公开的另一实现方式中，所述三层晶圆层中的任意一层晶圆层为逻辑层时，包 括至少两种类型的逻辑单元。
在本公开的另一实现方式中，所述三层晶圆层中的任意一层晶圆层根据其他晶圆层的良品率，调整所述晶圆层中的各单元与其他晶圆层的各单元的对应关系。
在本公开的另一实现方式中，所述三层晶圆层中的任意一层晶圆层为逻辑层时，所述逻辑层根据需求进行逻辑单元的配置。
在本公开的另一实现方式中，所述三层晶圆层中进行配置的逻辑层复用其他晶圆层。
在本公开的另一实现方式中，所述三层晶圆层上的混合键合金属介质的数量与硅通孔金属介质的数量为独立配置。
根据本公开实施例的第二方面，提供了一种处理器，包括：根据第一方面所述的集成电路组件。
根据本公开实施例的第三方面，提供了一种片上系统，包括：至少一个处理器，所述处理器为第二方面所述的处理器。
在本公开实施例的方案中，集成电路组件包括至少两层晶圆层，每层晶圆层包括正面与背面，其中，在至少两层晶圆层中，第一层晶圆层与第二层晶圆层正面对正面堆叠，第二层晶圆层和第三晶圆层依次为正面对背面堆叠，第二层晶圆层经过硅通孔、重布线层以及混合键合处理，至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。本公开实施例中的至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接，从而实现多层晶圆层的3D晶圆级封装，本公开实施例的集成电路组件可以提供更大的片上存储容量以满足基础模型计算的需求。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本公开实施例中记载的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1a至图1h为晶圆层进行处理的的示意图。
图2a为根据本公开的集成电路组件的一实施例的示意图。
图2b为根据本公开的集成电路组件的另一实施例的示意图。
图3为根据本公开的集成电路组件另一实施例进行封装的过程的示意图。
图4a和图4b为根据本公开的集成电路组件再两个实施例的示意图。
图5a和图5c为根据本公开的集成电路组件再三个实施例的示意图。
图6a为根据本公开的集成电路组件再一实施例的示意图。
图6b为根据本发明的逻辑层中的数据流逻辑单元的示意性框图。
图6c为根据本发明的逻辑层中的存内处理单元的示意性框图。
图6d为根据本发明的存储层的示意性框图。
图7a和图7b为根据本公开的集成电路组件再两个实施例的示意图。
图8为根据本公开的集成电路组件再一实施例的示意图。
图9a和图9b为根据本公开的集成电路组件再一实施例的示意图。
图10为根据本公开的集成电路组件再一实施例的示意图。
图11为根据本公开的另一实施例的处理器的结构框图。
图12为根据本公开的另一实施例的片上系统的结构示意图。
具体实施方式
在下面的描述中阐述了很多具体细节以便于充分理解本说明书。但是本说明书能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本说明书内涵的情况下做类似推广，因此本说明书不受下面公开的具体实施的限制。
为了使本领域的人员更好地理解本公开实施例中的技术方案，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、详细地描述，显然，所描述的实施例是本公开实施例一部分实施例，而不是全部的实施例。基于本公开实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本公开实施例保护的范围。
在下面的详细描述中对附图进行参考，这些附图形成详细描述的一部分并且图示了示例性实施例。另外，要理解，可以利用其他实施例，并且可以进行结构和/或逻辑改变，而不脱离要求权利的主题的范围。还应该注意的是，方向和参考(例如上、下、顶、底等)可以用于便于附图中特征的描述。因此，以下详细描述将不在限制意义上被理解，并且要求权利的主题的范围由所附权利要求及其等效物来限定。
在下面的描述中，阐述了众多细节。然而，对于本领域技术人员来说将显而易见的是，可以在没有这些特定细节的情况下实践本文中的实施例。在一些情况下，公知的方法和装置以框图形式示出，而不是详细示出，以避免模糊本文中的实施例。在此说明书通篇对“实施例”或“一个实施例”或“一些实施例”的引用意味着结合该实施例描述的特定特征、结构、功能或特性被包括在本文中的至少一个实施例中。因此，在此说明书通篇各处中出现短语“在实施例中”或“在一个实施例中”或“一些实施例”不一定是指同一实施例。此外，在一个或多个实施例中，特定特征、结构、功能或特性可以以任何合适的方式组合。例如，第一实施例可以在与两个实施例关联的特定特征、结构、功能或特性不相互排斥的任何情况下与第二实施例组合。
如在描述和所附权利要求中所使用的，单数形式“一(a、an)”和“该”意图也包括复数形式，除非上下文另有明确指示。还将理解，如本文中使用的术语“和/或”指的是并且包含关联的列出项中一个或多个的任何和所有可能的组合。
术语“耦合”和“连接”连同它们的派生词在本文中可以用来描述组件之间的功能或结构关系。应该理解，这些术语不意图作为彼此的同义词。相反，在特定实施例中，“连接”可用于指示两个或多于两个元件与彼此直接物理、光或电接触。“耦合”可以用于指示两个或多于两个元件与彼此直接或间接(在它们之间有其他中间元件)物理接触或电接触，和/或两个或多于两个元件与彼此协作或交互(例如，如在因果关系中)。
如本文中所使用的术语“在…上方”、“在…下方”、“在…之间”和“在…上”是指一个组件或材料相对于其他组件或材料的相对位置，其中此类物理关系是值得注意的。例如，在材料的上下文中，设置在另一材料上方或下方的一个材料或材料可以直接接触，或者可以具有一个 或多个中间材料。而且，设置在两个材料或材料之间的一个材料可以与两个层直接接触，或者可以具有一个或多个中间层。相比之下，第二材料或材料“上”的第一材料或材料与该第二材料/材料直接接触。在组件组装的上下文中要进行类似区分。
如在此描述通篇以及在权利要求中所使用的，由术语“中的至少一个”或“中的一个或多个”连接的项目的列表可意味着所列出项目的任何组合。例如，短语“A、B或C中的至少一个”可意味着A；B；C；A和B；A和C；B和C；或者A、B和C。
术语“电路”或“模块”可以指一个或多个无源和/或有源组件，它们被布置成与彼此协作以提供期望的功能。术语“信号”可以指至少一个电流信号、电压信号或磁信号。术语“基本上”、“靠近”、“近似”、“接近”和“大约”通常指在目标值的+/-10％内。
下面结合本公开实施例附图进一步说明本公开实施例具体实现。
晶圆层(Wafer)由纯硅(Si)构成，包括正面与背面。晶圆层的正面是晶圆上进行芯片制作的主要工作表面。正面通常具有特定的取向和晶格结构，被设置为在其上生长或构建晶体管、电路和其他半导体器件，即，正面设置有布线层。晶圆层的背面也称为背面表面或背衬，与正面相对。背面通常是平坦的，没有晶体结构，被设置为提供支撑和处理晶圆的机械稳定性。背面通常没有电路或器件，并且可以进行特殊的处理或涂层以满足特定需求，例如增强粘附性或改善热传导。
3D晶圆级封装是指两个以上晶圆层封装构成的集成电路组件。
混合键合(HB，Hybrid bonding)，是一种在相互堆叠的芯片之间获得更密集互连的方法，混合键合工艺允许一晶圆层正面对另一晶圆层的正面堆叠。
具体地，在正面对正面堆叠的情况下，一晶圆层的正面与另一晶圆层的正面之间的层间布线通过混合键合形成，例如，一晶圆层的正面上的若干键合点与另一晶圆层的正面上的键合点通过位置对齐形成键合。
硅通孔(TSV，Through-Silicon Vias)，主要功能是Z轴(垂直于晶圆层所在平面的坐标轴)电气延伸和互联的作用。
重布线层(RDL，Re-distribution Layer)，起着XY平面(晶圆层所在平面)电气延伸和互联的作用。在先进封装的FIWLP(Fan-In Wafer Level Package)，FOWLP(Fan-Out Wafer Level Package)中，RDL是最为关键的技术，通过RDL将IO Pad进行扇入Fan-In或者扇出Fan-Out，形成不同类型的晶圆级封装。
具体地，在正面对背面堆叠的情况下，一晶圆层的背面与另一晶圆层的正面之间的层间布线通过硅通孔、重新布线、以及混合键合形成。硅通孔能够连接一晶圆层的正面和背面，重新布线用于在一晶圆层的背面基于硅通孔的位置重新形成布线，以便一晶圆层的背面通过重新布线与另一晶圆层的正面进行混合键合。
应理解，第一层晶圆层的层内布线(例如，层内布线中的至少部分布线节点作为键合点)与第二层晶圆层的层内布线(例如，层内布线中的至少部分布线节点作为键合点)通过正面对正面的层间布线连接。
还应理解，第二层晶圆层的层内布线与第三层晶圆层的层内布线通过正面对背面的层间布线连接。
还应理解，第一层晶圆层的层内布线与第三层晶圆层的层内布线通过第一层晶圆层与第二层晶圆层的层间布线以及第二层晶圆层与第三层晶圆层之间的层间布线连接。
参见图1a至图1h，图中箭头表示晶圆层正面的方向；11表示Si介质；12表示传递电信号的金属介质，包括：金属层、硅通孔、重布线层、混合键合、管脚等；其他部分表示绝缘介质。其中，图1a为初始晶圆层，图1b为经过混合键合处理的晶圆层。参见图1c为初始晶圆层，图1d为经过硅通孔处理的晶圆层。参见图1e为初始晶圆层，图1f为经过重布线层引出管脚处理的晶圆层。图1g为背面经过硅通孔、重布线层、混合键合处理，正面经过混合键合处理的晶圆层。图1h为背面经过硅通孔、重布线层、混合键合处理的晶圆层。
下面将结合图2a和图2b来描述两个不同实施例的集成电路组件。
图2a示出了一个实施例的集成电路组件，集成电路组件包括至少两层晶圆层，即，W1，W2，W3，……Wn，n≥2。每层晶圆层包括正面(附图示出的与Si所在的基板的外表面相对的外表面)与背面(附图示出的Si所在的基板的外表面)。第一层晶圆层W1与第二层晶圆层W2正面对正面堆叠，第二层晶圆层W2和第三晶圆层W3依次为正面对背面堆叠，第二层晶圆层W2经过硅通孔、重布线层以及混合键合处理，至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。
在本公开实施例中，至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接，从而实现多层晶圆层的3D晶圆级封装。
也就是说，晶圆层的正面为设置有布线层的一侧，在晶圆层的正面通过混合键合实现了更密集且可靠的布线，有利于减小晶圆层的正面布线的数据传输延迟且提高数据传输效率，从而可以提供更大的片上存储容量以满足基础模型计算的需求。
晶圆层的背面为基板的一侧，在晶圆层的背面进行硅通孔工艺处理，将布线引导至晶圆层的背面，并且通过重布线层以及混合键合工艺处理，在兼容了相关工艺的同时充分地利用晶圆层的背面实现更密集且可靠的布线，尤其是在3D晶圆封装(集成电路组件的示例)中，处于中间层的晶圆层的背面实现更密集且可靠的布线，在用作3D晶圆封装的背面的晶圆层背面通过硅通孔实现了布线从3D晶圆封装中引出。此外，还可以采用电极垫(Package Assembly Drawing，PAD)工艺制作3D封装的引脚。
图2b示出了本公开实施例提供的另一集成电路组件，集成电路组件包括至少三层晶圆层，即W1，W2，W3，……Wn，n≥3。其中第一层晶圆层W1与第二层晶圆层W2正面对正面堆叠，第二层晶圆层W2与第三层晶圆层W3正面对背面堆叠。第三层晶圆层W3与第四层晶圆层W4正面对背面堆叠，……,第N-1层晶圆层Wn-1与第N层晶圆层Wn正面对背面堆叠。
第二层晶圆层经过硅通孔、重布线层以及混合键合处理，其他晶圆层经过硅通孔、重布线层以及混合键合处理中至少其一。在本公开实施例中，至少三层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接，从而实现多层晶圆层的3D晶圆级封装。晶圆层的正面为设置有布线层的一侧，在晶圆层的正面通过混合键合实现了更密集且可靠的布线，有利于减小晶圆层的正面布线的数据传输延迟且提高数据传输效率，从而可以提供更大的片上存储容量以满足基础模型计算的需求。
在本公开一具体实现中，本公开实施例集成电路组件包括三层晶圆层，即W1，W2，W3。 图3a为初始的第一层晶圆层W1。图3b为第一层晶圆层W1的正面经过混合键合处理。图3c为第二层晶圆层W2的正面经过混合键合处理，并与正面经过混合键合处理的第一层晶圆层W1正面对正面堆叠。图3d为图3c中的第二层晶圆层W2的背面经过硅通孔、重布线层以及混合键合处理。图3e为正面经过混合键合处理的第三层晶圆层W3，且第三层晶圆层W3的正面与第二层晶圆层W2的背面堆叠。
本公开实施例中的第一层晶圆层和第三层晶圆层通过混合键合、第二层晶圆层通过硅通孔、重布线层以及混合键合，实现三层晶圆层之间的相互连接，封装工艺更加简便，降低了封装成本。
也就是说，在晶圆层的正面通过混合键合实现了更密集且可靠的布线，正面对正面堆叠工艺加强了相邻晶圆层之间的数据传输效率，减小了不同晶圆层之间的延迟，这时，相邻晶圆层分别作为逻辑层与存储层是提供了数据的读写效率，在相邻晶圆层分别均作为逻辑层或者均作为存储层也提供了数据传输效率。
相应地，兼容了相关工艺的同时能够保证加工的效率和3D晶圆的机械性能，在正面对背面的堆叠工艺充分地利用晶圆层的背面实现更密集且可靠的布线。这时，相邻晶圆层分别作为逻辑层(即，逻辑工艺层)与存储层(即，存储工艺层)提供了数据的读写效率，在相邻晶圆层分别均作为逻辑层或者均作为存储层也提供了数据传输效率。
在本公开一具体实现中，参见图4a，第一层晶圆层W1的背面引出第一引脚D1；参见图4b，第三层晶圆层W3的背面引出第二引脚D2。本公开实施例便于实现集成电路组件的引脚设计。
在本公开一具体实现中，三层晶圆层均为晶圆片或者第二层晶圆层为晶圆片，第一层晶圆层和第三层晶圆层其中之一为芯片，另一个为晶圆片。
具体地，参见图5a，三层晶圆层均为晶圆片；参见图5b，第一层晶圆层W1和第二层晶圆层W2为晶圆片，第三层晶圆层W3为芯片；参见图5c，第一层晶圆层W1为芯片，第二层晶圆层W2和第三层晶圆层W3为晶圆片。
本公开实施例集成电路组件三层晶圆层的实现方式多样化，可以第一层晶圆层和第三层晶圆层其中之一可采用芯片，本公开实施例封装方式更加灵活，能够提供更多样化的3D集成封装设计选择。
应理解，在一些示例中，三层晶圆层均为晶圆片，减小了三层晶圆层的对齐工艺要求。在这种情况下，对齐工艺要求之外的考量因素(例如，功效指标)进行集成电路组件进行配置，例如，可以考量机械性能、对传统工艺的兼容性、电气性能(例如，数据传输延迟)、散热性能等。
在另一些示例中，第二层晶圆层为晶圆片，第一层晶圆层和第三层晶圆层其中之一为芯片，另一个为晶圆片。也就是说，芯片处于集成电路组件的外侧，相比于芯片处于晶圆片之间的情况，减小了晶圆层之间的对齐工艺要求。由于芯片可以为封装(例如，采用2D或2.5D封装)完成的晶圆层，使封装方式更加灵活，能够提供更多样化的3D集成封装设计选择。
在另一些示例中，第二层晶圆层为芯片。在第一层晶圆层和第三层晶圆层均为晶圆片的情况下，虽然芯片在晶圆层之间对齐工艺相比于芯片在一侧的情况工艺要求较高，但是如果 侧重考量其他因素将芯片设置成中间的晶圆层(例如，将芯片为存储层，会带来更好的散热性能)，仍然会保证了其他的功效指标。
在第一层晶圆层和第三层晶圆层中的至少一者为芯片的情况下，充分地利用了封装(例如，采用2D或2.5D封装)完成的晶圆层，使封装方式更加灵活，能够提供更多样化的3D集成封装设计选择。
示例性地，参见图3e，以三层晶圆层的数据流动进行说明。
第一层晶圆层W1到第二层晶圆层W2的数据流动经过：数据源点、第一层晶圆层W1的混合键合金属介质、第二层晶圆层W2的混合键合金属介质、数据目标点。数据流动方向为第一层晶圆层W1到第二层晶圆层W2时，延时小。
第二层晶圆层W2到第一层晶圆层W1的数据流动经过：数据源点、第二层晶圆层W2的混合键合金属介质、第一层晶圆层W1的混合键合金属介质、数据目标点。数据流动方向为第二层晶圆层W2到第一层晶圆层W1时，延时小。
也就是说，通过正面对正面的堆叠设置采用混合键合，减小了不同晶圆层之间的延迟。
第二层晶圆层W2到第三层晶圆层W3的数据流动经过：数据源点、第二层晶圆层W2的硅通孔金属介质、第二层晶圆层W2的重布线层金属介质、第二层晶圆层W2的混合键合金属介质、第三层晶圆层W3的混合键合金属介质、数据目标点。数据流动方向为第二层晶圆层W2到第三层晶圆层W3时，延时中。
第三层晶圆层W3到第二层晶圆层W2的数据流动经过：数据源点、第三层晶圆层W3的混合键合金属介质、第二层晶圆层W2的混合键合金属介质、第二层晶圆层W2的重布线层金属介质、第二层晶圆层W2的硅通孔金属介质、数据目标点。数据流动方向为第三层晶圆层W3到第二层晶圆层W2时，延时中。
也就是说，基于重布线层和硅通孔工艺对晶圆层的背面预处理，然后在通过正面对背面的堆叠设置采用混合键合，减小了不同晶圆层之间的延迟。
由于重布线层和硅通孔工艺的预处理相比于直接采用混合键合，会增大延迟，但是兼容了相关工艺的同时能够保证加工的效率和3D晶圆的机械性能。
相应地，对于逻辑层到逻辑层、逻辑层到存储层、以及存储层到存储层，这三者存在不同的组件应用延迟需求，可以匹配相应的延迟需求与上述的不同堆叠方式对于的延迟，优化集成电路组件的应用。
第一层晶圆层W1到第二层晶圆层W2，再到第三层晶圆层W3的数据流动经过：数据源点、第一层晶圆层W1的混合键合金属介质、第二层晶圆层W2正面的混合键合金属介质、第二层晶圆层W2背面的硅通孔金属介质、第二层晶圆层W2背面的重布线层金属介质、第二层晶圆层W2背面的混合键合金属介质、第三层晶圆层W3的混合键合金属介质、数据目标点。数据流动方向为第一层晶圆层W1到第二层晶圆层W2，再到第三层晶圆层W3时，延时大。
第三层晶圆层W3到第二层晶圆层W2，再到第一层晶圆层W1的数据流动经过：数据源点、第三层晶圆层W3的混合键合金属介质、第二层晶圆层W2背面的混合键合金属介质、第二层晶圆层W2背面的重布线层金属介质、第二层晶圆层W2背面的硅通孔金属介质、第 二层晶圆层W2正面的混合键合金属介质、第一层晶圆层W1的混合键合金属介质、数据目标点。数据流动方向为第三层晶圆层W3到第二层晶圆层W2，再到第一层晶圆层W1时，延时大。
不失一般性地，非相邻的不同晶圆层之间的延迟会大于相邻的不同晶圆层之间的延迟。
本公开实施例的集成电路组件实现了三层晶圆层之间的数据流动，本公开实施例可以根据需要设计三层晶圆层之间的数据流动，从而令数据流动的延时满足数据传输的需要。
在本公开一具体实现中，三层晶圆层中至少一层晶圆层为逻辑层，其余晶圆层为存储层，逻辑层与引脚连接。
在一个示例中，三层晶圆层中的处于外侧的晶圆层为逻辑层，其余晶圆层为存储层，逻辑层的散热要求高于存储层的散热要求，保证了集成电路组件的散热性能。此外，在这种情况下，逻辑层的比重较大，更适于配置成诸如CPU或其他控制流程比较复杂的DSA。
例如，第一层晶圆层为逻辑层，第二层晶圆层为存储层，第三层晶圆层为存储层。又例如，第一层晶圆层为存储层，第二层晶圆层为存储层，第三层晶圆层为逻辑层。
作为更优选的示例，三层晶圆层中的处于两侧的晶圆层均为逻辑层，两个逻辑层之间的晶圆层为存储层，使集成电路组件的散热性能达到最优。
可替代地，三层晶圆层中的处于外侧的晶圆层为逻辑层，其余晶圆层为存储层和逻辑层，逻辑层的散热要求高于存储层的散热要求，同时存储层的散热能力高于逻辑层的散热能力，存储层能够有利于逻辑层的散热，从而一定程度上保证了集成电路组件的散热性能。此外，这种情况下，存储层的比重较大，更适于配置成诸如GPU或TPU等并且计算要求较高的DSA。
又例如，芯片配置成逻辑层，晶圆片配置成存储层，芯片处于集成电路组件的外侧，晶圆片处于组件的中间层，保证了散热性能，且相比于芯片处于集成电路组件的中间层的情况，减小了诸如对齐工艺等的工艺要求。
例如，第一层晶圆层为逻辑层，第二层晶圆层为逻辑层，第三层晶圆层为存储层。又例如，第一层晶圆层为存储层，第二层晶圆层为逻辑层，第三层晶圆层为逻辑层。
可替代地，第一层晶圆层为逻辑层，第二层晶圆层为逻辑层，第三层晶圆层为逻辑层。三层晶圆层均为逻辑层，散热性能相对于上述示例较差，但是极大地提高了逻辑层之间的低延迟互联，实现了比上述示例更优的数据处理能力和流程控制性能。
由于第一层晶圆层W1的背面引出第一引脚D1，第三层晶圆层W3的背面引出第二引脚D2，因此逻辑层连接的引脚(D1或者D2)均位于三层晶圆层的外层。
具体地，参见表一，逻辑层与存储层的选择以及散热情况如表一所示。表一给出的六种选项分别对应上述六种实施例，在各个表项对应的实施例中，第1种、第3种、以及第6种散热极优，第2种和第5种为优，第4种为良好。
表一

本公开实施例的集成电路组件可以根据散热需要设计三层晶圆层为逻辑层或者存储层，本公开实施例提供了更为灵活的设计方案。
在本公开一具体实现中，逻辑层包括：数据流逻辑单元、计算逻辑单元或者存储逻辑单元中其一，数据流逻辑可以采用PE或者片上网络；计算逻辑采用阻变式存储器-存内处理(Resistive Random Access Memory-Processing-in-Memory，RRAM-PIM)或者高性能第五代精简指令集(High performance RISC-V，HP-RV)；存储逻辑采用阻变式存储器(用作存储器)或者静态随机存取存储器；存储逻辑采用RRAM-Memory(Resistive Random Access Memory-Memory，电阻式随机存取内存-存储器)或者SRAM；存储层采用DRAM工艺。
应理解，对于文中的数据流逻辑，仅仅示出了DSA或片上网络或加速器的示例，也可以替代为其他DSA或加速器的数据流逻辑单元。文中的HP-RV是CPU的示例，其可以替代为各种类型的CPU的计算逻辑单元。
存储层采用动态随机存取内存。
在本公开一具体实现中，三层晶圆层中的任意一层晶圆层为逻辑层时，所述逻辑层根据需求进行逻辑单元的配置。
本公开实施例能够更灵活地配置逻辑层的逻辑单元，从而令集成电路组件能够提供更加多样化的内存形式。本公开实施例通过配置逻辑层的逻辑单元，能够为PE(Processing Element，处理单元)提供专用存储器或专用领域专用架构(DSA)引擎。
在本公开一具体实现中，三层晶圆层中的任意一层晶圆层根据需求进行配置。因此，本公开实施例可以为高级人工智能模型(GPT/LLM)提供各种3D集成设计选择。
在另一些示例中，三层晶圆层包括第一逻辑层和第二逻辑层，第一逻辑层和第二逻辑层为数据流逻辑单元、计算逻辑单元、存储逻辑单元中的不同单元。将不同逻辑的逻辑层与存储层集成到集成电路组件中，提高了数据读写效率、计算效率和整体数据处理效率。例如，数据流逻辑单元和计算逻辑单元融合了并行计算与串行计算的优势，数据流逻辑单元和存储计算单元融合了数据读写优势，计算逻辑单元和存储计算单元融合了数据读写优势，等等。
更具体地，参见表二，表二给出四类选项作为三层晶圆层的示例，但本公开实施例并不限于此四类。
表二
在表二的各个范例中，集成电路组件中的每层晶圆层可以为逻辑层或存储层，并且集成电路组件同时包括逻辑层和存储层。
在本公开一具体实现中，通过范例1进行具体说明。
参见图6a，第一层晶圆层W1为PE，第二层晶圆层W2为DRAM，第三层晶圆层W3为RRAM-PIM(Resistive Random Access Memory-Processing-in-Memory，电阻式随机存取内存-存内处理)/SRAM。不失一般性地，第一层晶圆层W1为逻辑层，包括数据流逻辑单元；第二层晶圆层W2为存储层，包括内存块；第三层晶圆层W3为逻辑层，包括计算逻辑单元。
第一层晶圆层W1为PE，即第一层晶圆层W1包括数据流逻辑单元。具体地，如图6b所示，领域专用架构(Domain-Specific Architecture，DSA)的类型的数据流逻辑单元包括计算逻辑子单元、以及内存控制器和/或物理层等底层模块。计算逻辑子单元包括但不限于：向量处理单元(VPU)或者通用矩阵的矩阵乘法(GEMM)等。其中，计算逻辑子单元通过内存控制器经由层间布线(例如，3D互连)对存储层中的内存块进行内存访问。数据流逻辑单元还可以包括暂存器(Scratchpad)，暂存器可以为计算逻辑子单元中的本地缓存或共享缓存。
第二层晶圆层W2为DRAM，即第二层晶圆层W2包括存储逻辑单元。具体地，如图6d所示，存储层的配置包括：内存块(Memory Bank)的数量，对应的混合键合输入输出(HB IO)的数量以及带宽是否能与计算逻辑的计算存储阵列的大小匹配。更具体地，每个内存块配置有解码/控制/缓冲等功能模块。
第三层晶圆层W3为RRAM-PIM/SRAM，即第三层晶圆层W3包括计算逻辑单元/存储逻辑单元。示例性地，如图6c所示，计算逻辑单元为存内处理单元，存内处理单元的配置包括计算子单元，计算子单元包括整型(Integral，INT)精度子单元和/或浮点型(BF(brain float)/FP(floating point)精度子单元)。其中，计算子单元包括存内计算(Compute In Memory，CIM)单元阵列(Array)，计算子单元中还可以配置有外围电路(例如，包括协处理器接口)模块、基于总线的直接内存访问(DMA)模块、以及内存控制器和/或物理层等底层模块。
应理解，在第一层晶圆层W1中，各个数据流逻辑单元通过层内布线连接；在第二层晶圆层W2中，各个内存块通过层内布线连接；在第三层晶圆层W3中，各个计算逻辑单元/存储逻辑单元通过层内布线连接。进一步地，数据流逻辑单元通过第一层晶圆层与第二层晶圆层之间的层间布线直接地或间接地访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问对应的内存块。数据流逻辑单元通过第一层晶圆层与第三层晶圆层之间的层间布线访问第三层晶圆层，进而通过第三层晶圆层的层内布线访问对应的计算逻辑单元/存储逻辑单元，计算逻辑单元/存储逻辑单元用作数据流逻辑单元的缓存。计算逻辑单元/存储逻辑单元通过第三层晶圆层与第二层晶圆层之间的层间布线访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问对应的内存块。
在范例2中，第一层晶圆层W1为PE，第二层晶圆层W2为SRAM/RRAM-PIM，第三层晶圆层W3为DRAM。不失一般性地，第一层晶圆层W1为逻辑层，包括数据流逻辑单元；第二层晶圆层W2为逻辑层，包括存储逻辑单元或计算逻辑单元；第三层晶圆层W3为存储层，包括内存块。
应理解，在第一层晶圆层W1中，各个数据流逻辑单元通过层内布线连接；在第二层晶圆层W2中，各个计算逻辑单元/存储逻辑单元通过层内布线连接；在第三层晶圆层W3中，各个内存块通过层内布线连接。进一步地，数据流逻辑单元通过第一层晶圆层与第二层晶圆层之间的层间布线访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问对应的计算逻辑单元/存储逻辑单元，计算逻辑单元/存储逻辑单元用作数据流逻辑单元的缓存。计算逻辑单元/存储逻辑单元通过第二层晶圆层与第三层晶圆层之间的层间布线访问第三层晶圆层，进而通过第三层晶圆层的层内布线访问对应的内存块。
在范例3中，第一层晶圆层W1为PE，第二层晶圆层W2为DRAM，第三层晶圆层W3为DRAM。不失一般性地，第一层晶圆层W1为逻辑层，包括数据流逻辑单元；第二层晶圆层W2为存储层，包括内存块；第三层晶圆层W3为存储层，包括内存块。
应理解，在第一层晶圆层W1中，各个数据流逻辑单元通过层内布线连接；在第二层晶圆层W2中，各个内存块通过层内布线连接；在第三层晶圆层W3中，各个内存块通过层内布线连接。进一步地，数据流逻辑单元通过第一层晶圆层与第二层晶圆层之间的层间布线直接地或间接地访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问对应的内存块。数据流逻辑单元通过第一层晶圆层与第三层晶圆层之间的层间布线直接地或间接地访问第三层晶圆层，进而通过第三层晶圆层的层内布线访问对应的内存块。
在范例4中，第一层晶圆层W1为PE，第二层晶圆层W2为DRAM，第三层晶圆层W3为HP-RV(或其他CPU)。不失一般性地，第一层晶圆层W1为逻辑层，包括数据流逻辑单元；第二层晶圆层W2为存储层，包括内存块；第三层晶圆层W3为逻辑层，包括计算逻辑单元。
应理解，在第一层晶圆层W1中，各个数据流逻辑单元通过层内布线连接；在第二层晶圆层W2中，各个内存块通过层内布线连接；在第三层晶圆层W3中，各个计算逻辑单元通过层内布线连接。进一步地，数据流逻辑单元通过第一层晶圆层与第二层晶圆层之间的层间布线直接地或间接地访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问对应的内存块。数据流逻辑单元通过第一层晶圆层与第三层晶圆层之间的层间布线访问第三层晶圆层，进而通过第三层晶圆层的层内布线访问(例如，通过DMA)对应的计算逻辑单元，计算逻辑单元可以为控制平面的处理单元，数据流逻辑单元可以为数据平面的处理单元，用于辅助控制平面的数据处理。计算逻辑单元通过第三层晶圆层与第二层晶圆层之间的层间布线访问第二层晶圆层，进而通过第二层晶圆层的层内布线访问(例如，通过DMA)对应的内存块。
不失一般性地，片上网络(Network on Chip，NOC)可以作为第一层晶圆层中的层内布线的示例。
进一步地，三层晶圆层上的混合键合金属介质的数量与硅通孔金属介质的数量为独立配置。因此，第一层晶圆层W1、第二层晶圆层W2、第三层晶圆层W3之间的关系无需一一对应。参见图7a和图7b，图7a为第一层晶圆层W1、第二层晶圆层W2、第三层晶圆层W3之间的关系一一对应示意图；图7b为第一层晶圆层W1、第二层晶圆层W2、第三层晶圆层W3之间的关系未一一对应示意图。
在本公开一具体实现中，所述三层晶圆层中的任意一层晶圆层为逻辑层时，包括至少两 种类型的逻辑单元。
示例性地，参见图8，第一层晶圆层W1、第二层晶圆层W2、第三层晶圆层W3之间的异构示意图，即第一层晶圆层W1包括两种类型的逻辑单元，RRAM-PIM和SRAM。
在本公开一具体实现中，三层晶圆层中的任意一层晶圆层根据其他晶圆层的良品率，调整晶圆层中的各单元与其他晶圆层的各单元的对应关系。参见图9a，在示例1中，由于第三层晶圆层W3的RRAM-PIM良率较低，可以存在坏块1，参见图9b，在第二层晶圆层W2进行重布线层的时候，可以更为灵活地通过重布线层选择第三层晶圆层W3的RRAM-PIM之间非坏块2代替坏块1进行对应。也就是说，在这种情况下，第三层晶圆层W3的裸片已经制造完成，可以不改变第三层晶圆层W3的裸片，对第二层晶圆层W2的裸片进行灵活地加工，兼容了第三层晶圆层W3的裸片的生产过程，降低了对第三层晶圆层的良率标准，保证了集成电路组件的较低加工成本。
在本公开的集成电路组件的一具体实现中，三层晶圆层中的任意一层晶圆层为逻辑层时，可以基于需求，逻辑层根据需求进行逻辑单元的配置。三层晶圆层中进行配置的逻辑层复用其他晶圆层。示例性地，在第一层晶圆层W1、第二层晶圆层W2已经完成后，根据不同的需要定制不同的第三层晶圆层W3，即第三层晶圆层W3配置自定制的领域专用架构(DSA)。具体参见图10，定制的第三层晶圆层W3，可复用已经完成的第一层晶圆层W1、第二层晶圆层W2。即，无论第三层晶圆层W3定制何种领域专用架构(DSA)，均可复用已经完成的第一层晶圆层W1、第二层晶圆层W2。
本公开实施例为非冯·诺依曼体系结构，从而减少数据移动所带来的存储瓶颈问题。本公开实施例所提供的多层3D异构数据流架构，提供了可以3D内存，以改进片上系统的内存，并满足基础模型的大内存需求。本公开实施例逻辑层的多样化配置，为高级人工智能模型(GPT/LLM)提供各种3D集成设计选择。
图11为根据本公开的另一实施例的处理器的结构框图。本实施例的处理器1100包括：处理器核1101以及集成电路组件1102。
图12为根据本公开的另一实施例的片上系统的结构示意图。本实施例的片上系统1200包括多个处理器1210。
此外，程序中各步骤的具体实现可以参见上述方法实施例中的相应步骤和单元中对应的描述，在此不赘述。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的设备和模块的具体工作过程，可以参考前述方法实施例中的对应过程描述，在此不再赘述。
需要指出，根据实施的需要，可将本公开实施例中描述的各个部件/步骤拆分为更多部件/步骤，也可将两个或多个部件/步骤或者部件/步骤的部分操作组合成新的部件/步骤，以实现本公开实施例的目的。
上述根据本公开实施例的方法可在硬件、固件中实现，或者被实现为可存储在记录介质(诸如CD ROM、RAM、软盘、硬盘或磁光盘)中的软件或计算机代码，或者被实现通过网络下载的原始存储在远程记录介质或非暂时机器可读介质中并将被存储在本地记录介质中的计算机代码，从而在此描述的方法可被存储在使用通用计算机、专用处理器或者可编程或专 用硬件(诸如ASIC或FPGA)的记录介质上的这样的软件处理。可以理解，计算机、处理器、微处理器控制器或可编程硬件包括可存储或接收软件或计算机代码的存储组件(例如，RAM、ROM、闪存等)，当所述软件或计算机代码被计算机、处理器或硬件访问且执行时，实现在此描述的方法。此外，当通用计算机访问被设置为实现在此示出的方法的代码时，代码的执行将通用计算机转换为被设置为执行在此示出的方法的专用计算机。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及方法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本公开实施例的范围。
以上实施方式用于说明本公开实施例，而并非对本公开实施例的限制，有关技术领域的普通技术人员，在不脱离本公开实施例的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本公开实施例的范畴，本公开实施例的专利保护范围应由权利要求限定。
工业实用性
本公开实施例所提供的集成电路组件、处理器和片上系统，集成电路组件包括至少两层晶圆层，每层晶圆层包括正面与背面，其中，在至少两层晶圆层中，第一层晶圆层与第二层晶圆层正面对正面堆叠，第二层晶圆层和第三晶圆层依次为正面对背面堆叠，第二层晶圆层经过硅通孔、重布线层以及混合键合处理，至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。本公开实施例中的至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接，从而实现多层晶圆层的3D晶圆级封装，本公开实施例的集成电路组件可以提供更大的片上存储容量以满足基础模型计算的需求。

Claims (20)

  1. 一种集成电路组件，包括至少两层晶圆层，每层晶圆层包括正面与背面，其中，在所述至少两层晶圆层中，第一层晶圆层与第二层晶圆层正面对正面堆叠，所述第二层晶圆层和所述第三晶圆层依次为正面对背面堆叠，所述第二层晶圆层经过硅通孔、重布线层以及混合键合处理，所述至少两层晶圆层通过各层的硅通孔、重布线层以及混合键合进行相互连接。
  2. 根据权利要求1所述的组件，其中，所述至少两层晶圆层还包括第三层晶圆层，所述第二层晶圆层与所述第三层晶圆层正面对背面堆叠，所述至少三层晶圆层中除所述第二层晶圆层以外的其他晶圆层经过硅通孔、重布线层以及混合键合处理中至少其一。
  3. 根据权利要求2所述的组件，其中，所述第二层晶圆层的正面经过混合键合处理，所述第二层晶圆层的背面经过硅通孔、重布线层以及混合键合处理。
  4. 根据权利要求3所述的组件，其中，所述组件包括三层晶圆层，所述第一层晶圆层的正面经过混合键合处理，所述第三层晶圆层的正面经过混合键合处理。
  5. 根据权利要求4所述的组件，其中，所述第一层晶圆层的背面或所述第三层晶圆层的背面引出管脚。
  6. 根据权利要求5所述的组件，其中，所述三层晶圆层均为晶圆片；
    或者，
    所述第二层晶圆层为晶圆片，所述第一层晶圆层和所述第三层晶圆层其中之一为芯片，另一个为晶圆片；
    或者，所述第二层晶圆层为芯片。
  7. 根据权利要求6所述的组件，其中，所述三层晶圆层的数据流动包括：
    所述第一层晶圆层到第二层晶圆层的数据流动经过：数据源点、第一层晶圆层的混合键合金属介质、第二层晶圆层的混合键合金属介质、数据目标点；和/或
    所述第二层晶圆层到第一层晶圆层的数据流动经过：数据源点、第二层晶圆层的混合键合金属介质、第一层晶圆层的混合键合金属介质、数据目标点；和/或
    所述第二层晶圆层到第三层晶圆层的数据流动经过：数据源点、第二层晶圆层的硅通孔金属介质、第二层晶圆层的重布线层金属介质、第二层晶圆层的混合键合金属介质、第三层晶圆层的混合键合金属介质、数据目标点；和/或
    所述第三层晶圆层到第二层晶圆层的数据流动经过：数据源点、第三层晶圆层的混合键合金属介质、第二层晶圆层的混合键合金属介质、第二层晶圆层的重布线层金属介质、第二层晶圆层的硅通孔金属介质、数据目标点；和/或
    所述第一层晶圆层到第二层晶圆层，再到第三层晶圆层的数据流动经过：数据源点、第一层晶圆层的混合键合金属介质、第二层晶圆层正面的混合键合金属介质、第二层晶圆层背面的硅通孔金属介质、第二层晶圆层背面的重布线层金属介质、第二层晶圆层背面的混合键合金属介质、第三层晶圆层的混合键合金属介质、数据目标点；和/或
    所述第三层晶圆层到第二层晶圆层，再到第一层晶圆层的数据流动经过：数据源点、第三层晶圆层的混合键合金属介质、第二层晶圆层背面的混合键合金属介质、第二层晶 圆层背面的重布线层金属介质、第二层晶圆层背面的硅通孔金属介质、第二层晶圆层正面的混合键合金属介质、第一层晶圆层的混合键合金属介质、数据目标点。
  8. 根据权利要求7所述的组件，其中，所述三层晶圆层中至少一层晶圆层为逻辑层，所述逻辑层与所述管脚连接。
  9. 根据权利要求8所述的组件，其中，所述三层晶圆层中的处于外侧的晶圆层为逻辑层，其余晶圆层为存储层。
  10. 根据权利要求8所述的组件，其中，所述三层晶圆层中两侧的晶圆层均为逻辑层，两侧的逻辑层之间的晶圆层为存储层。
  11. 根据权利要求8所述的组件，其中，所述三层晶圆层均为逻辑层。
  12. 根据权利要求8-11中任一项所述的组件，其中，所述逻辑层包括：数据流逻辑单元、计算逻辑单元或者存储逻辑单元中至少其一，所述数据流逻辑采用精简指令集流人工智能引擎或者片上网络；所述计算逻辑采用阻变式存储器或者精简指令集；所述存储逻辑采用阻变式存储器或者静态随机存取存储器；
    所述存储层采用动态随机存取内存。
  13. 根据权利要求12所述的组件，其中，若所述逻辑层包括所述数据流逻辑单元，则数据流逻辑单元的配置包括：领域专用架构的类型、存储架构是否需要暂存器；
    若所述逻辑层包括所述计算逻辑单元，则计算逻辑单元的配置包括：固定精度、混合精度、计算存储阵列的大小与所述存储层的带宽匹配；
    若所述逻辑层包括所述存储逻辑单元，则存储逻辑单元的配置包括：存储阵列大小和存储阵列种类中的至少一者；
    所述存储层的配置包括：存储块的数量，对应的混合键合输入输出口的数量以及带宽是否能与所述计算逻辑的计算存储阵列的大小匹配。
  14. 根据权利要求12所述的组件，其中，所述三层晶圆层中的任意一层晶圆层为逻辑层时，包括至少两种类型的逻辑单元。
  15. 根据权利要求12所述的组件，其中，所述三层晶圆层中的任意一层晶圆层根据其他晶圆层的良品率，调整所述晶圆层中的各单元与其他晶圆层的各单元的对应关系。
  16. 根据权利要求12所述的组件，其中，所述三层晶圆层中的任意一层晶圆层为逻辑层时，所述逻辑层根据需求进行逻辑单元的配置。
  17. 根据权利要求12所述的组件，其中，所述三层晶圆层中进行配置的逻辑层复用其他晶圆层。
  18. 根据权利要求12所述的组件，其中，所述三层晶圆层上的混合键合金属介质的数量与硅通孔金属介质的数量为独立配置。
  19. 一种处理器，包括：
    根据权利要求1-18任一项所述的集成电路组件。
  20. 一种片上系统，包括：
    至少一个处理器，所述处理器为根据权利要求19所述的处理器。
PCT/CN2024/097972 2023-06-07 2024-06-07 集成电路组件、处理器和片上系统 Ceased WO2024251239A1 (zh)

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