WO2024250366A1 - 一种显示面板及其制备方法 - Google Patents

一种显示面板及其制备方法 Download PDF

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Publication number
WO2024250366A1
WO2024250366A1 PCT/CN2023/104771 CN2023104771W WO2024250366A1 WO 2024250366 A1 WO2024250366 A1 WO 2024250366A1 CN 2023104771 W CN2023104771 W CN 2023104771W WO 2024250366 A1 WO2024250366 A1 WO 2024250366A1
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Prior art keywords
electrode
layer
array substrate
doping type
semiconductor layer
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PCT/CN2023/104771
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English (en)
French (fr)
Inventor
刘卫来
孙亮
朱平
周威龙
施磊
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US18/565,389 priority Critical patent/US20250098368A1/en
Publication of WO2024250366A1 publication Critical patent/WO2024250366A1/zh
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    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/30—Active-matrix LED displays
    • H10H29/34—Active-matrix LED displays characterised by the geometry or arrangement of subpixels within a pixel, e.g. relative disposition of the RGB subpixels
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    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/813—Bodies having a plurality of light-emitting regions, e.g. multi-junction LEDs or light-emitting devices having photoluminescent regions within the bodies
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    • H10H20/01—Manufacture or treatment
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    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
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    • H10H29/80—Constructional details
    • H10H29/962—Stacked configurations of light-emitting semiconductor components or devices, the components or devices emitting at different wavelengths
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Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same.
  • Micro-LED (Micro Light-Emitting Diode) displays have ultra-high density pixel resolution and self-luminous characteristics. Compared with OLED and LCD displays, Micro-LED displays are easier to accurately adjust color, have longer luminous life and higher brightness, and are thinner and more power-saving, with broad market application prospects.
  • the method of realizing full-color display of Micro-LED is: additionally set a quantum dot film layer in the display panel, and use the blue light LED chip to excite the quantum dots in the quantum dot film layer to generate colored light.
  • the thickness of the quantum dot film layer needs to be set thicker, but the thicker quantum dot film layer will restrict the size of the display pixels, making it difficult to improve the resolution of the display panel and increase the manufacturing cost.
  • the present application provides a display panel and a method for preparing the same, which can effectively improve the problems of difficult to improve resolution, high manufacturing cost and light crosstalk in existing Micro-LED display panels.
  • the present application provides a display panel, which includes: an array substrate; a plurality of pixel unit groups, which are arranged on one side of the array substrate, each of the pixel unit groups consists of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in their orthographic projections on the array substrate, wherein the first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are stacked sequentially in a direction away from the array substrate.
  • the first luminous color is red; the second luminous color is one of blue and green; and the third luminous color is the other of blue and green.
  • the first pixel unit includes a first semiconductor layer of a first doping type, the first light-emitting unit layer, and a second semiconductor layer of a second doping type, which are sequentially stacked in a direction away from the array substrate;
  • the second pixel unit includes a third semiconductor layer of a second doping type, the second light-emitting unit layer, a fourth semiconductor layer of a first doping type, the third light-emitting unit layer, and a fifth semiconductor layer of a second doping type, which are sequentially stacked in a direction away from the array substrate; wherein the first doping type is one of N-type or P-type, and the second doping type is the other of N-type or P-type.
  • the first pixel unit also includes: a first electrode, which is in contact with the first semiconductor layer of the first doping type; a second electrode, which is in contact with the second semiconductor layer of the second doping type; the second pixel unit also includes: a third electrode, which is in contact with the third semiconductor layer of the second doping type; a fourth electrode, which is in contact with the fourth semiconductor layer of the first doping type; a fifth electrode, which is in contact with the fifth semiconductor layer of the second doping type; wherein the first electrode and the fourth electrode are of the same electrode type, both are one type of anode or cathode, and the first electrode and the fourth electrode are electrically connected; wherein the second electrode, the third electrode and the fifth electrode are of the same electrode type, both are another type of anode or cathode, and the second electrode, the third electrode and the fifth electrode are insulated.
  • the fourth semiconductor layer of the first doping type includes a first portion not covered by the third light-emitting unit layer, and the fourth electrode is in contact with the first portion.
  • the array substrate includes: a plurality of pad groups, each pad group corresponds to one pixel unit group, wherein the pad groups include: a first pad, a second pad, a third pad and a fourth pad, the first pad being electrically connected to the first electrode and the fourth electrode, respectively; the second pad being electrically connected to the second electrode, the third pad being electrically connected to the third electrode, and the fourth pad being electrically connected to the fifth electrode.
  • the pad groups include: a first pad, a second pad, a third pad and a fourth pad, the first pad being electrically connected to the first electrode and the fourth electrode, respectively; the second pad being electrically connected to the second electrode, the third pad being electrically connected to the third electrode, and the fourth pad being electrically connected to the fifth electrode.
  • the first electrode is arranged on a side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is in contact and electrically connected with the first pad;
  • the third electrode is arranged on a side of the third semiconductor layer of the second doping type facing the array substrate, and the third electrode is in contact and electrically connected with the third pad.
  • the surface of the second semiconductor layer of the second doping type facing away from the array substrate is at a first distance from the array substrate; the surface of the fifth semiconductor layer of the second doping type facing away from the array substrate is at a second distance from the array substrate; wherein the second distance is greater than the first distance.
  • the first electrode is arranged on a side of the first semiconductor layer of the first doping type facing the array substrate, and the first electrode is electrically connected to the first pad;
  • the third electrode is arranged on a side of the third semiconductor layer of the second doping type facing the array substrate, wherein the display panel also includes a plurality of insulating protrusions, the insulating protrusions are arranged between the third electrode and the array substrate, and the third electrode is electrically connected to the third pad through via holes in the insulating protrusions.
  • the distance between the surface of the insulating protrusion facing away from the array substrate and the array substrate is a third distance; the distance between the surface of the second semiconductor layer of the second doping type facing away from the array substrate and the array substrate is a fourth distance; wherein the third distance is equal to the fourth distance.
  • the present application provides a method for preparing a display panel, the method comprising the following steps:
  • a first pixel composite layer is formed on one side of a first substrate, wherein the first pixel composite layer includes a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type that are sequentially stacked;
  • a second pixel composite layer is formed on one side of a second substrate, wherein the second pixel composite layer includes a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type that are sequentially stacked;
  • the first pixel composite layer Before bonding the side of the first pixel composite layer away from the first substrate to the side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; before bonding the side of the second pixel composite layer away from the second substrate to the side of the array substrate and removing the second substrate, the second pixel composite layer is patterned;
  • the present application provides a display panel and a preparation method thereof, wherein the display panel includes an array substrate and a plurality of pixel unit groups, each pixel unit group consists of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in the orthographic projection on the array substrate, the first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are sequentially stacked in a direction away from the array substrate.
  • each pixel unit group consists of a first pixel unit and a second pixel unit, and the second pixel unit includes two light-emitting unit layers having different light-emitting colors that are stacked, it is possible to improve resolution, reduce costs, and improve display quality while achieving full-color display; and the light-emitting efficiency of the red light-emitting unit layer can be effectively improved, thereby effectively improving the overall light-emitting efficiency of the display panel.
  • FIG. 1 is a schematic diagram of a film layer structure of a pixel unit group disposed on one side of an array substrate provided in Embodiment 1 of the present application.
  • FIG. 2 is a schematic structural diagram corresponding to step S01 in the method for preparing a display panel provided in the first embodiment of the present application.
  • FIG. 3 is a schematic structural diagram corresponding to step S02 in the method for preparing a display panel provided in the first embodiment of the present application.
  • FIG. 4 is a schematic structural diagram corresponding to step S03 in the method for preparing a display panel provided in the first embodiment of the present application.
  • FIG. 5 is a schematic structural diagram corresponding to step S04 in the method for preparing a display panel provided in the first embodiment of the present application.
  • FIG. 6 is a schematic structural diagram corresponding to step S05 in the method for preparing a display panel provided in the first embodiment of the present application.
  • FIG. 7 is a schematic structural diagram corresponding to step S06 in the method for manufacturing a display panel provided in the first embodiment of the present application.
  • FIG. 8 is a schematic diagram of a film layer structure of a pixel unit group disposed on one side of an array substrate provided in Embodiment 2 of the present application.
  • FIG. 9 is a schematic structural diagram corresponding to step S11 in the method for manufacturing a display panel provided in the second embodiment of the present application.
  • FIG. 10 is a schematic structural diagram corresponding to step S12 in the method for manufacturing a display panel provided in the second embodiment of the present application.
  • FIG. 11 is a schematic structural diagram corresponding to step S13 in the method for preparing a display panel provided in the second embodiment of the present application.
  • FIG. 12 is a schematic structural diagram corresponding to step S14 in the method for preparing a display panel provided in the second embodiment of the present application.
  • FIG. 13 is a schematic structural diagram corresponding to step S15 in the method for preparing a display panel provided in the second embodiment of the present application.
  • FIG. 14 is a schematic structural diagram corresponding to step S16 in the method for preparing a display panel provided in the second embodiment of the present application.
  • FIG. 15 is a schematic structural diagram corresponding to step S17 in the method for preparing a display panel provided in the second embodiment of the present application.
  • FIG. 16 is a schematic structural diagram corresponding to step S18 in the method for preparing a display panel provided in the second embodiment of the present application.
  • each pixel unit group includes a red pixel unit, a green pixel unit and a blue pixel unit, wherein the red pixel unit includes a blue light LED chip and a red quantum dot film layer arranged above the blue light LED chip, the green pixel unit includes a blue light LED chip and a green quantum dot film layer arranged above the blue light LED chip, and the blue pixel unit includes a blue light LED chip.
  • the light-emitting unit in each pixel unit that is, the LED chip, emits blue light
  • an additional quantum dot film layer is required to achieve full color display by exciting the quantum dots in the quantum dot film layer with monochromatic light.
  • the quantum dot film layer will restrict the size of the display pixels, making it difficult to improve the resolution of the display panel and increase the manufacturing cost. At the same time, it is also easy to cause the problem of light crosstalk between adjacent pixel units.
  • the first embodiment of the present application provides a display panel that can achieve full color without the need for a quantum dot film layer, thereby improving the resolution of the display panel, reducing manufacturing costs and improving display quality.
  • FIG1 is a schematic diagram of the film structure of a pixel unit group provided in the first embodiment of the present application and arranged on one side of the array substrate.
  • the first embodiment of the present application provides a display panel
  • the display panel includes an array substrate 10 and a plurality of pixel unit groups 20, the pixel unit groups 20 are arranged on one side of the array substrate 10, each of the pixel unit groups 20 is composed of a first pixel unit 21 and a second pixel unit 22, and the first pixel unit 21 and the second pixel unit 22 are arranged in a staggered orthographic projection on the array substrate 10, wherein the first pixel unit 21 includes a first light-emitting unit layer 213 having a first light-emitting color; the second pixel unit 22 includes a second light-emitting unit layer 223 having a second light-emitting color and a third light-emitting unit layer 226 having a third light-emitting color, and the second light-emitting unit layer 223 and the third light-emitting color,
  • the first pixel unit 21 can display the first luminous color through the first luminous unit layer 213; the second pixel unit 22 can display the second luminous color through the second luminous unit layer 223, and/or display the third luminous color through the third luminous unit layer 226. Therefore, the display panel can directly realize full-color display through the first pixel unit 21 and the second pixel unit 22 in the pixel unit group 20, without the need for a quantum dot film layer, which can effectively reduce the manufacturing cost, and can eliminate the problem of pixel unit size being restricted and light crosstalk caused by the provision of a quantum dot film layer, so that the size of the first pixel unit 21 and the second pixel unit 22 can be made smaller, thereby improving the resolution and display quality.
  • the present application enables the second pixel unit 22 to emit the second light-emitting color and/or the third light-emitting color by stacking the second light-emitting unit layer 223 and the third light-emitting unit layer 226 in sequence in a direction away from the array substrate 10, thereby realizing the display function of two pixel units in the related art through one pixel unit, thereby reducing the number of pixel units; compared with the structure in the related art in which light-emitting unit layers of different colors are stacked in the horizontal direction, the present application can save space in the horizontal direction, reduce the layout area of the pixel unit group 20, further improve the resolution of the display panel, and can reduce the number of transfer times of the pixel unit in the process, simplify the production and preparation process, and reduce the production cost.
  • the first luminescent color is red; the second luminescent color is one of blue and green; and the third luminescent color is the other of blue and green.
  • the material of the light-emitting unit layer with blue and green luminescent colors is usually InGaN/GaN quantum well material.
  • the coaxial growth of the light-emitting unit layer with blue luminescent color and the light-emitting unit layer with green luminescent color can ensure good epitaxial quality and obtain high light extraction efficiency.
  • the material of the light-emitting unit layer with red luminescent color is usually AlGaInP/GaInP quantum well material.
  • the difference in materials makes it difficult for the light-emitting unit layer with red luminescent color to grow coaxially with the light-emitting unit layer with blue luminescent color and the light-emitting unit layer with green luminescent color.
  • the present application can ensure the luminous effect of the pixel unit and improve the manufacturing yield by selecting the first luminescent color as red; the second luminescent color as one of blue and green; and the third luminescent color as the other of blue and green.
  • the first pixel unit 21 since in the direction perpendicular to the array substrate 10, the first pixel unit 21 has no other light-emitting unit layer except the light-emitting unit layer with red light-emitting color, thereby ensuring the luminous efficiency of the light-emitting unit layer with red light-emitting color; and the luminous efficiency of the red light-emitting unit layer is currently the main factor restricting the overall luminous efficiency of the Micro-LED display panel, so improving the luminous efficiency of the red light-emitting unit layer can effectively improve the overall luminous efficiency of the display panel.
  • the present application can effectively take into account both the resolution of the display panel and the overall luminous efficiency.
  • the first pixel unit 21 includes a first semiconductor layer 212 of a first doping type, the first light-emitting unit layer 213, and a second semiconductor layer 214 of a second doping type, which are sequentially stacked in a direction away from the array substrate 10;
  • the second pixel unit 22 includes a third semiconductor layer 222 of a second doping type, the second light-emitting unit layer 223, a fourth semiconductor layer 224 of a first doping type, the third light-emitting unit layer 226, and a fifth semiconductor layer 227 of a second doping type, which are sequentially stacked in a direction away from the array substrate 10; wherein the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
  • the first semiconductor layer 212 and the second semiconductor layer 214 located on both sides of the first light-emitting unit layer 213 have different doping types, a PN junction can be formed, and the light-emitting state of the first light-emitting unit layer 213 can be controlled by the conduction and cutoff of the PN junction;
  • the second pixel unit 22 provided in the present application since the third semiconductor layer 222 and the fourth semiconductor layer 224 on both sides of the second light-emitting unit layer 223 have different doping types, a PN junction can be formed, and the light-emitting state of the second light-emitting unit layer 223 can be controlled by the conduction and cutoff of the PN junction; in addition, since the fifth semiconductor layer 227 and the fourth semiconductor layer 224 on both sides of the third light-emitting unit layer 226 have different doping types, a PN junction can be formed, and the light-emitting state of the third light-emitting unit layer 226 can
  • the first doping type is P type; the second doping type is N type, wherein a periodic stress adjustment layer and a current diffusion layer are further provided between the second doping type second semiconductor layer 214 and the first light emitting unit layer 213; a periodic stress adjustment layer and a current diffusion layer are further provided between the second doping type third semiconductor layer 222 and the second light emitting unit layer 223; a periodic stress adjustment layer and a current diffusion layer are further provided between the second doping type fifth semiconductor layer 227 and the third light emitting unit layer 226; a periodic stress adjustment layer, a current diffusion layer and a first Bragg reflection layer are further provided between the first doping type first semiconductor layer 212 and the first light emitting unit layer 213, and the first Bragg reflection layer can transmit red light; a periodic stress adjustment layer, a current diffusion layer and a second Bragg reflection layer are further provided between the first doping type fourth semiconductor layer 224 and the third light emitting unit layer 226, and the second Bragg reflection layer can transmit blue light and green light.
  • the first pixel unit 21 also includes: a first electrode 211 and a second electrode 215, the first electrode 211 is in contact with the first semiconductor layer 212 of the first doping type; the second electrode 215 is in contact with the second semiconductor layer 214 of the second doping type; the second pixel unit 22 also includes: a third electrode 221, a fourth electrode 225 and a fifth electrode 228, the third electrode 221 is in contact with the third semiconductor layer 222 of the second doping type; the fourth electrode 225 is in contact with the fourth semiconductor layer 224 of the first doping type; the fifth electrode 228 is in contact with the fifth semiconductor layer 227 of the second doping type.
  • the first electrode 211 and the fourth electrode 225 are of the same electrode type, and are both anodes or cathodes, and the first electrode 211 and the fourth electrode 225 are electrically connected, that is, the first electrode 211 and the fourth electrode 225 are both anodes, or the first electrode 211 and the fourth electrode 225 are both cathodes. Since the first electrode 211 and the fourth electrode 225 are of the same electrode type, the first electrode 211 and the fourth electrode 225 can be electrically connected to the same pad on the array substrate 10, thereby reducing the number of pads, simplifying the structure of the display panel, and reducing the difficulty of binding.
  • the second electrode 215, the third electrode 221 and the fifth electrode 228 are of the same electrode type, and are all anodes or cathodes, and the second electrode 215, the third electrode 221 and the fifth electrode 228 are insulated, that is, the second electrode 215, the third electrode 221 and the fifth electrode 228 are cathodes, or the second electrode 215, the third electrode 221 and the fifth electrode 228 are anodes.
  • the first light-emitting unit layer 213, the second light-emitting unit layer 223 and the third light-emitting unit layer 226 can be independently controlled by the second electrode 215, the third electrode 221 and the fifth electrode 228, respectively, to achieve independent light emission of the first light-emitting unit layer 213, the second light-emitting unit layer 223 and the third light-emitting unit layer 226.
  • the first doping type fourth semiconductor layer 224 includes a first portion 2241 not covered by the third light emitting unit layer 226 , and the fourth electrode 225 is in contact with the first portion 2241 .
  • the fourth electrode 225 can be set on the side of the first part 2241 away from the second light-emitting unit layer 223, thereby reducing the difficulty of setting the fourth electrode 225.
  • the array substrate 10 includes: a plurality of pad groups 11, each pad group 11 corresponds to one pixel unit group 20, wherein the pad group 11 includes: a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114, the first pad 111 is electrically connected to the first electrode 211 and the fourth electrode 225, respectively; the second pad 112 is electrically connected to the second electrode 215, the third pad 113 is electrically connected to the third electrode 221, and the fourth pad 114 is electrically connected to the fifth electrode 228.
  • the first pad 111 is electrically connected to the first electrode 211 and the fourth electrode 225 respectively, the first electrode 211 and the fourth electrode 225 can be controlled by one pad, thereby reducing the number of pads set; since the second pad 112 is electrically connected to the second electrode 215, the third pad 113 is electrically connected to the third electrode 221, and the fourth pad 114 is electrically connected to the fifth electrode 228, the second electrode 215, the third electrode 221 and the fifth electrode 228 can be controlled by the second pad 112, the third pad 113 and the third pad 113 respectively, thereby realizing independent light emission of the first light-emitting unit layer 213, the second light-emitting unit layer 223 and the third light-emitting unit layer 226.
  • the array substrate 10 is an integrated circuit wafer, and the integrated circuit wafer includes a driving circuit layer and a plurality of pad groups 11 arranged on the driving circuit layer.
  • the first electrode 211 is arranged on the side of the first semiconductor layer 212 of the first doping type facing the array substrate 10, and the first electrode 211 is in contact and electrically connected to the first pad 111;
  • the third electrode 221 is arranged on the side of the third semiconductor layer 222 of the second doping type facing the array substrate 10, and the third electrode 221 is in contact and electrically connected to the third pad 113.
  • the first pixel unit 21 and the second pixel unit 22 are arranged on one side of the array substrate 10 by metal bonding, for example. Since the first electrode 211 is in contact and electrically connected with the first pad 111, and the third electrode 221 is in contact and electrically connected with the third pad 113, the connection structure of the electrodes is simplified, making the display panel thinner and lighter, and the first pixel unit 21 and the second pixel unit 22 can be formed by chip bonding in terms of process, simplifying the production process.
  • the surface of the second semiconductor layer 214 of the second doping type is away from the array substrate 10, and the distance between it and the array substrate 10 is a first distance; the surface of the fifth semiconductor layer 227 of the second doping type is away from the array substrate 10, and the distance between it and the array substrate 10 is a second distance; wherein the second distance is greater than the first distance.
  • the overall thickness of the second pixel unit 22 is greater than the overall thickness of the first pixel unit 21.
  • the bonding metal layer arranged on the side of the third semiconductor layer 222 away from the second light-emitting unit layer 223 can fully contact the bonding metal layer on one side of the array substrate 10 to complete metal bonding and form the third electrode 221.
  • the display panel also includes a plurality of connecting lines 50, the second electrode 215 is electrically connected to the second pad 112 through the connecting lines 50, the fourth electrode 225 is electrically connected to the third pad 113 through the connecting lines 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 through the connecting lines 50.
  • the display panel further includes an insulating layer 40 , and the insulating layer 40 is disposed between the connecting line 50 and the first pixel unit 21 and between the connecting line 50 and the second pixel unit 22 .
  • the first embodiment of the present application further provides a method for manufacturing a display panel, the method for manufacturing a display panel comprising the following steps:
  • a first pixel composite layer is formed on one side of a first substrate, wherein the first pixel composite layer includes a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type that are sequentially stacked;
  • a second pixel composite layer is formed on one side of a second substrate, wherein the second pixel composite layer includes a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type that are sequentially stacked;
  • the first pixel composite layer Before the step of bonding the side of the first pixel composite layer away from the first substrate to the side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; before the step of bonding the side of the second pixel composite layer away from the second substrate to the side of the array substrate and removing the second substrate, the second pixel composite layer is patterned.
  • FIG. 2 is a schematic diagram of the structure corresponding to step S01 in the method for preparing a display panel provided in Example 1 of the present application
  • FIG. 3 is a schematic diagram of the structure corresponding to step S02 in the method for preparing a display panel provided in Example 1 of the present application
  • FIG. 4 is a schematic diagram of the structure corresponding to step S03 in the method for preparing a display panel provided in Example 1 of the present application
  • FIG. 5 is a schematic diagram of the structure corresponding to step S04 in the method for preparing a display panel provided in Example 1 of the present application
  • FIG. 6 is a schematic diagram of the structure corresponding to step S05 in the method for preparing a display panel provided in Example 1 of the present application
  • FIG. 7 is a schematic diagram of the structure corresponding to step S06 in the method for preparing a display panel provided in Example 1 of the present application.
  • the method for preparing a display panel includes the following steps:
  • a first pixel composite layer 102 is formed on one side of a first substrate 101, wherein the first pixel composite layer 102 includes a second semiconductor layer 214 of a second doping type, a first light-emitting unit layer 213, and a first semiconductor layer 212 of a first doping type which are sequentially stacked; a second pixel composite layer 104 is formed on one side of a second substrate 103, wherein the second pixel composite layer 104 includes a fifth semiconductor layer 227 of a second doping type, a third light-emitting unit layer 226, a fourth semiconductor layer 224 of a first doping type, a second light-emitting unit layer 223, and a third semiconductor layer 222 of a second doping type which are sequentially stacked.
  • the first substrate 101 is a GaAs substrate; the second doping type is N-type, and the second semiconductor layer 214 includes GaAs material; the first doping type is P-type, and the first type semiconductor layer includes GaP material; the second substrate 103 is a sapphire substrate, or a substrate containing at least one of GaN, AlN, Si, and SiC; the fifth semiconductor layer 227 and the third semiconductor layer 222 include at least one of GaN, AlGaN, and AlInGaN materials; and the fourth semiconductor layer 224 includes GaN material.
  • Step S03 Bonding the side of the first pixel composite layer 102 away from the first substrate 101 to the side of an array substrate 10, and removing the first substrate 101.
  • Step S03 specifically includes: forming a first metal bonding layer on the side of the first pixel composite layer 102 away from the first substrate 101, and the material of the first metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a second metal bonding layer on the side of the array substrate 10, and the material of the second metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the first metal bonding layer to the second metal bonding layer, bonding the side of the first pixel composite layer 102 away from the first substrate 101 to the side of the array substrate 10, and removing the first substrate 101.
  • the first metal bonding layer is bonded to one side of an array substrate 10, wherein the first metal bonding layer is bonded to the second metal bonding layer to form a first electrode 211 of a first pixel unit 21, and the array substrate 10 includes a plurality of pad groups 11, each pad group 11 includes a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114; the first electrode 211 is in contact and electrically connected with the first pad 111, the thickness of the first electrode 211 is 0.1 micron to 3 microns, and the first electrode 211 also has a reflective function; the first substrate 101 is removed.
  • Step S05 bonding the side of the second pixel composite layer 104 facing away from the second substrate 103 to one side of the array substrate 10 , and removing the second substrate 103 .
  • Step S05 specifically includes: forming a third metal bonding layer on the side of the second pixel composite layer 104 away from the second substrate 103, and the material of the third metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a fourth metal bonding layer on one side of the array substrate 10, and the material of the fourth metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the second pixel composite layer 104 away from the second substrate 103 to the side of the array substrate 10 by bonding the third bonding layer to the fourth bonding layer, wherein the third metal bonding layer and the fourth metal bonding layer are bonded to form a third electrode 221 of the second pixel unit 22, the third electrode 221 is in contact and electrically connected with the third pad 113, the thickness of the third electrode 2
  • S06 forming a second electrode 215 on a side of the second semiconductor layer 214 of the second doping type away from the array substrate 10; forming a fourth electrode 225 on a side of the fourth semiconductor layer 224 of the first doping type away from the array substrate 10; and forming a fifth electrode 228 on a side of the fifth semiconductor layer 227 of the second doping type away from the array substrate 10.
  • the second electrode 215 is electrically connected to the second pad 112 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the first pixel unit 21;
  • the fourth electrode 225 is electrically connected to the third pad 113 via a connecting wire 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the second pixel unit 22.
  • the first pixel composite layer 102 is patterned before the step of bonding the side of the first pixel composite layer 102 facing away from the first substrate 101 to the side of an array substrate 10 and removing the first substrate 101; and the second pixel composite layer 104 is patterned before the step of bonding the side of the second pixel composite layer 104 facing away from the first substrate 101 to the side of the array substrate 10 and removing the second substrate 103; therefore, the production preparation process of the display panel can be simplified and the process steps can be reduced.
  • FIG8 is a schematic diagram of the film structure of a pixel unit group 20 provided on one side of an array substrate 10 according to the second embodiment of the present application.
  • the second embodiment of the present application provides a display panel, the display panel comprising an array substrate 10 and a plurality of pixel unit groups 20, the pixel unit groups 20 being arranged on one side of the array substrate 10, each of the pixel unit groups 20 being composed of a first pixel unit 21 and a second pixel unit 22, and the orthographic projections of the first pixel unit 21 and the second pixel unit 22 on the array substrate 10 being staggered, wherein the first pixel unit 21 comprises a first light-emitting unit layer 213 having a first light-emitting color; the second pixel unit 22 comprises a second light-emitting unit layer 223 having a second light-emitting color and a third light-emitting unit layer 226 having a third light-emitting color, and the second light-emitting unit layer 223 and the third light-emitting
  • the structure of the display panel provided in the second embodiment of the present application is similar to the structure of the display panel provided in the first embodiment of the present application, and the same parts will not be described in detail in the second embodiment of the present application.
  • the first electrode 211 is arranged on the side of the first semiconductor layer 212 of the first doping type facing the array substrate 10, and the first electrode 211 is in contact and electrically connected with the first pad 111;
  • the third electrode 221 is arranged on the side of the third semiconductor layer 222 of the second doping type facing the array substrate 10, wherein the display panel also includes a plurality of insulating protrusions 30, the insulating protrusions 30 are arranged between the third electrode 221 and the array substrate 10, and the third electrode 221 is electrically connected to the third pad 113 through the via hole 31 in the insulating protrusion 30.
  • the display panel since the display panel also includes a plurality of insulating protrusions 30, the insulating protrusions 30 are arranged between the third electrode 221 and the array substrate 10, and the third electrode 221 is electrically connected to the third pad 113 through the via hole 31 in the insulating protrusion 30, therefore, the alignment accuracy requirement when the first pixel unit 21 and the array substrate 10 are bonded can be reduced; the alignment accuracy requirement when the second pixel unit 22 and the array substrate 10 are bonded can be reduced; and this is beneficial to reducing the production cost of the display panel.
  • the distance between the surface of the insulating protrusion 30 on the side away from the array substrate 10 and the array substrate 10 is a third distance; the distance between the surface of the second semiconductor layer 214 of the second doping type on the side away from the array substrate 10 and the array substrate 10 is a fourth distance; wherein the third distance is equal to the fourth distance.
  • a first pixel composite layer is formed on one side of a first substrate, wherein the first pixel composite layer includes a second semiconductor layer of a second doping type, a first light-emitting unit layer, and a first semiconductor layer of a first doping type that are sequentially stacked;
  • a second pixel composite layer is formed on one side of a second substrate, wherein the second pixel composite layer includes a fifth semiconductor layer of a second doping type, a third light-emitting unit layer, a fourth semiconductor layer of a first doping type, a second light-emitting unit layer, and a third semiconductor layer of a second doping type that are sequentially stacked;
  • the first pixel composite layer After bonding the side of the first pixel composite layer away from the first substrate to the side of an array substrate and removing the first substrate, the first pixel composite layer is patterned; after bonding the side of the second pixel composite layer away from the second substrate to the side of the array substrate and removing the second substrate, the second pixel composite layer is patterned, wherein after completing the patterning of the first pixel composite layer, an insulating protrusion is formed in the patterned area of the first pixel composite layer, and a via hole is formed passing through the insulating protrusion, the surface of the insulating protrusion away from the array substrate is at a third distance from the array substrate, the surface of the first pixel composite layer away from the array substrate is at a fourth distance from the array substrate, and the third distance is equal to the fourth distance; then, the side of the second pixel composite layer away from the second substrate is bonded to the side of the array substrate, and the second substrate is removed.
  • Figure 9 is a schematic structural diagram corresponding to step S11 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 10 is a schematic structural diagram corresponding to step S12 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 11 is a schematic structural diagram corresponding to step S13 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 12 is a schematic structural diagram corresponding to step S14 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 13 is a schematic structural diagram corresponding to step S15 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 14 is a schematic structural diagram corresponding to step S16 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 15 is a schematic structural diagram corresponding to step S17 in the method for preparing a display panel provided in Example 2 of the present application
  • Figure 16 is a schematic structural diagram corresponding to step S18 in the
  • a first pixel composite layer 102 is formed on one side of a first substrate 101, wherein the first pixel composite layer 102 includes a second semiconductor layer 214 of a second doping type, a first light-emitting unit layer 213, and a first semiconductor layer 212 of a first doping type which are sequentially stacked; a second pixel composite layer 104 is formed on one side of a second substrate 103, wherein the second pixel composite layer 104 includes a fifth semiconductor layer 227 of a second doping type, a third light-emitting unit layer 226, a fourth semiconductor layer 224 of a first doping type, a second light-emitting unit layer 223, and a third semiconductor layer 222 of a second doping type which are sequentially stacked.
  • Step S12 Bonding the side of the first pixel composite layer 102 away from the first substrate 101 to the side of an array substrate 10, and removing the first substrate 101.
  • Step S12 specifically includes: forming a first metal bonding layer on the side of the first pixel composite layer 102 away from the first substrate 101, and the material of the first metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a second metal bonding layer on the side of the array substrate 10, and the material of the second metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the first pixel composite layer 102 away from the first substrate 101 to the side of an array substrate 10 by bonding the first metal bonding layer to the second metal bonding layer.
  • the first metal bonding layer is bonded to the second metal bonding layer to form a first composite metal layer 105, and the first composite metal layer 105 is subsequently used to form a first electrode 211 of a first pixel unit 21, wherein the array substrate 10 includes a plurality of pad groups 11, each pad group 11 includes a first pad 111, a second pad 112, a third pad 113 and a fourth pad 114, the first electrode 211 is in contact and electrically connected with the first pad 111, the thickness of the first electrode 211 is 0.1 micron to 3 microns, and the first electrode 211 also has a reflective function; the first substrate 101 is removed.
  • the distance between the surface of the insulating protrusion 30 on the side away from the array substrate 10 and the array substrate 10 is a third distance
  • the distance between the surface of the first pixel composite layer 102 on the side away from the array substrate 10 and the array substrate 10 is a fourth distance
  • the third distance is equal to the fourth distance.
  • CMP chemical mechanical polishing
  • the step of forming an insulating protrusion 30 in the patterned area of the first pixel composite layer 102 specifically includes: forming an insulating protrusion layer in the patterned area of the first pixel composite layer 102 and on the side of the first composite metal layer 105 away from the array substrate 10, at this time, the insulating protrusion layer covers the first pixel composite layer 102; then, performing a CMP process on the insulating protrusion layer to remove the insulating protrusion layer on the side of the first pixel composite layer 102 away from the array substrate 10, so that the distance between the surface of the insulating protrusion 30 on the side away from the array substrate 10 and the array substrate 10 is equal to the distance between the surface of the first pixel composite layer 102 on the side away from the array substrate 10 and the array substrate 10.
  • Step S16 Bonding the side of the second pixel composite layer 104 facing away from the second substrate 103 to one side of the array substrate 10 , and removing the second substrate 103 .
  • Step S16 specifically includes: forming a third metal bonding layer on the side of the second pixel composite layer 104 away from the first substrate 101, and the material of the third metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; forming a fourth metal bonding layer on one side of the array substrate 10, and the material of the fourth metal bonding layer can be any one of Au, Sn, In, Ti, and Cu; bonding the side of the second pixel composite layer 104 away from the second substrate 103 to the side of the array substrate 10 by bonding the third bonding layer to the fourth bonding layer, wherein the third metal bonding layer and the fourth metal bonding layer are bonded to form a second composite metal layer 106, and the second composite metal layer 106 is subsequently used to form a third electrode 221 of the second pixel unit 22, and the third electrode
  • the second electrode 215 is electrically connected to the second pad 112 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the first pixel unit 21;
  • the fourth electrode 225 is electrically connected to the third pad 113 via a connecting wire 50, and the fifth electrode 228 is electrically connected to the fourth pad 114 via a connecting wire 50, and an insulating layer 40 is formed between the connecting wire 50 and the second pixel unit 22.
  • the first pixel composite layer 102 is patterned; after the step of bonding the side of the second pixel composite layer 104 facing away from the first substrate 101 to the side of the array substrate 10 and removing the second substrate 103, the second pixel composite layer 104 is patterned; therefore, the bonding alignment accuracy requirements can be greatly reduced, which is beneficial to reducing the production cost of the display panel.
  • the present application provides a display panel and a method for preparing the same.
  • the display panel includes an array substrate and a plurality of pixel unit groups, each pixel unit group consists of a first pixel unit and a second pixel unit, and the first pixel unit and the second pixel unit are staggered in the orthographic projection on the array substrate, the first pixel unit includes a first light-emitting unit layer having a first light-emitting color; the second pixel unit includes a second light-emitting unit layer having a second light-emitting color and a third light-emitting unit layer having a third light-emitting color, and the second light-emitting unit layer and the third light-emitting unit layer are sequentially stacked in a direction away from the array substrate.
  • each pixel unit group consists of a first pixel unit and a second pixel unit, and the second pixel unit includes two light-emitting unit layers having different light-emitting colors that are stacked, it is possible to achieve full-color display while improving resolution, reducing costs, and improving display quality.

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Abstract

本申请提供一种显示面板及其制备方法，显示面板包括阵列基板和多个像素单元组，每个像素单元组由一个第一像素单元和一个第二像素单元组成，第一像素单元包括第一发光单元层；第二像素单元包括第二发光单元层和第三发光单元层，且第二发光单元层和第三发光单元层在背离阵列基板的方向上依次层叠设置。

Description

一种显示面板及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及其制备方法。
 背景技术
微型发光二极管（Micro Light-Emitting Diode，简称Micro-LED）显示具有超高密度的像素分辨率和自主发光的特性。相比OLED和LCD显示，Micro-LED显示色彩更容易准确的调试，有更长的发光寿命和更高的亮度，同时更具轻薄及省电优势，具有广泛的市场应用前景。
相关技术中，实现Micro-LED全彩化显示的方式为：在显示面板中额外设置量子点膜层，利用蓝光LED芯片激发量子点膜层中的量子点，从而产生彩色光。此种全彩化的方式为了保证色彩转换和光效提取效率，需要将量子点膜层的厚度设置的较厚，但较厚的量子点膜层会制约显示像素的尺寸，使得显示面板的分辨率难以提高，并增加制造成本，同时还容易产生相邻显示像素出光串扰的问题，此问题亟待解决。
 发明概述
本申请提供一种显示面板及其制备方法，能够有效改善现有的Micro-LED显示面板存在的分辨率难以提高，制造成本高和出光串扰的问题。
一方面，本申请提供一种显示面板，所述显示面板包括：阵列基板；多个像素单元组，设置在所述阵列基板的一侧，每个所述像素单元组由一个第一像素单元和一个第二像素单元组成，且所述第一像素单元和所述第二像素单元在所述阵列基板上的正投影错位设置，其中，所述第一像素单元包括具有第一发光颜色的第一发光单元层；所述第二像素单元包括具有第二发光颜色的第二发光单元层和具有第三发光颜色的第三发光单元层，且所述第二发光单元层和所述第三发光单元层在背离所述阵列基板的方向上依次层叠设置。
可选的，所述第一发光颜色为红色；所述第二发光颜色为蓝色和绿色的一种；所述第三发光颜色为蓝色和绿色的另一种。
可选的，所述第一像素单元包括在背离所述阵列基板的方向上依次层叠设置的第一掺杂类型的第一半导体层、所述第一发光单元层、第二掺杂类型的第二半导体层；所述第二像素单元包括在背离所述阵列基板的方向上依次层叠设置的第二掺杂类型的第三半导体层、所述第二发光单元层、第一掺杂类型的第四半导体层、所述第三发光单元层、第二掺杂类型的第五半导体层；其中，所述第一掺杂类型为N型或P型的一种，所述第二掺杂类型为N型或P型的另一种。
可选的，所述第一像素单元还包括：第一电极，与所述第一掺杂类型的第一半导体层相接触；第二电极，与所述第二掺杂类型的第二半导体层相接触；所述第二像素单元还包括：第三电极，与所述第二掺杂类型的第三半导体层相接触；第四电极，与所述第一掺杂类型的第四半导体层相接触；第五电极，与所述第二掺杂类型的第五半导体层相接触；其中，所述第一电极和所述第四电极的电极类型相同，均为阳极或阴极的一种，且所述第一电极和所述第四电极电连接；其中，所述第二电极、所述第三电极和所述第五电极的电极类型相同，均为阳极或阴极的另一种，且所述第二电极、所述第三电极和所述第五电极绝缘设置。
可选的，所述第一掺杂类型的第四半导体层包括未被所述第三发光单元层所覆盖的第一部分，所述第四电极与所述第一部分相接触。
可选的，所述阵列基板包括：多个焊盘组，每个焊盘组对应一个所述像素单元组，其中，所述焊盘组包括：第一焊盘、第二焊盘、第三焊盘和第四焊盘，所述第一焊盘分别与所述第一电极和所述第四电极电连接；所述第二焊盘与所述第二电极电连接，所述第三焊盘与所述第三电极电连接，所述第四焊盘与所述第五电极电连接。
可选的，所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，所述第一电极与所述第一焊盘接触电连接；所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，所述第三电极与所述第三焊盘接触电连接。
可选的，所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第一距离；所述第二掺杂类型的第五半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第二距离；其中，所述第二距离大于所述第一距离。
可选的，所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，且所述第一电极与所述第一焊盘接触电连接；所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，其中，所述显示面板还包括多个绝缘凸起，所述绝缘凸起设置在所述第三电极和阵列基板之间，所述第三电极通过所述绝缘凸起中的过孔与所述第三焊盘电连接。
可选的，所述绝缘凸起背离所述阵列基板一侧的表面与所述阵列基板之间的距离为第三距离；所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面与所述阵列基板之间的距离为第四距离；其中，所述第三距离等于所述第四距离。
另一方面，本申请提供一种显示面板的制备方法，所述显示面板的制备方法包括以下步骤：
在一第一衬底的一侧形成第一像素复合层，所述第一像素复合层包括依次层叠设置的第二掺杂类型的第二半导体层、第一发光单元层、第一掺杂类型的第一半导体层；在一第二衬底的一侧形成第二像素复合层，所述第二像素复合层包括依次层叠设置的第二掺杂类型的第五半导体层、第三发光单元层、第一掺杂类型的第四半导体层、第二发光单元层、第二掺杂类型的第三半导体层；
将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底；
将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底；
其中，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之前，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之前，对所述第二像素复合层进行图案化处理；
或，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之后，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之后，对所述第二像素复合层进行图案化处理，其中，完成所述第一像素复合层的图案化处理之后，在所述第一像素复合层的图案化区域形成绝缘凸起，并形成贯穿所述绝缘凸起的过孔，所述绝缘凸起背离所述阵列基板的一侧的表面与所述阵列基板的距离为第三距离，所述第一像素复合层背离所述阵列基板的一侧的表面与所述阵列基板的距离为第四距离，所述第三距离等于所述第四距离；之后，将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底。
有益效果
本申请提供一种显示面板及其制备方法，显示面板包括阵列基板和多个像素单元组，每个像素单元组由一个第一像素单元和一个第二像素单元组成，且第一像素单元和第二像素单元在阵列基板上的正投影错位设置，第一像素单元包括具有第一发光颜色的第一发光单元层；第二像素单元包括具有第二发光颜色的第二发光单元层和具有第三发光颜色的第三发光单元层，且第二发光单元层和第三发光单元层在背离阵列基板的方向上依次层叠设置。本申请提供的显示面板中，由于每个像素单元组由一个第一像素单元和一个第二像素单元，且第二像素单元包括层叠设置的具有不同发光颜色的两种发光单元层，从而能够在实现全彩化显示的同时，提高分辨率，降低成本，提高显示质量；并可有效提升红色发光单元层的发光效率，进而能够有效提高显示面板的整体发光效率。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例一提供的设置在阵列基板的一侧的像素单元组的膜层结构示意图。
图2为本申请实施例一提供的显示面板的制备方法中步骤S01所对应的结构示意图。
图3为本申请实施例一提供的显示面板的制备方法中步骤S02所对应的结构示意图。
图4为本申请实施例一提供的显示面板的制备方法中步骤S03所对应的结构示意图。
图5为本申请实施例一提供的显示面板的制备方法中步骤S04所对应的结构示意图。
图6为本申请实施例一提供的显示面板的制备方法中步骤S05所对应的结构示意图。
图7为本申请实施例一提供的显示面板的制备方法中步骤S06所对应的结构示意图。
图8为本申请实施例二提供的设置在阵列基板的一侧的像素单元组的膜层结构示意图。
图9为本申请实施例二提供的显示面板的制备方法中步骤S11所对应的结构示意图。
图10为本申请实施例二提供的显示面板的制备方法中步骤S12所对应的结构示意图。
图11为本申请实施例二提供的显示面板的制备方法中步骤S13所对应的结构示意图。
图12为本申请实施例二提供的显示面板的制备方法中步骤S14所对应的结构示意图。
图13为本申请实施例二提供的显示面板的制备方法中步骤S15所对应的结构示意图。
图14为本申请实施例二提供的显示面板的制备方法中步骤S16所对应的结构示意图。
图15为本申请实施例二提供的显示面板的制备方法中步骤S17所对应的结构示意图。
图16为本申请实施例二提供的显示面板的制备方法中步骤S18所对应的结构示意图。
附图标记：
阵列基板10；焊盘组11；第一焊盘111；第二焊盘112；第三焊盘113；第四焊盘114；像素单元组20；第一像素单元21；第一电极211；第一半导体层212；第一发光单元层213；第二半导体层214；第二电极215；第二像素单元22；第三电极221；第三半导体层222；第二发光单元层223；第四半导体层224；第一部分2241；第四电极225；第三发光单元层226；第五半导体层227；第五电极228；绝缘凸起30；过孔31；绝缘层40；连接线50；第一衬底101；第一像素复合层102；第二衬底103；第二像素复合层104；第一复合金属层105；第二复合金属层106；
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。以下分别进行详细说明，需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
相关技术中，Micro-LED显示面板实现全彩化的架构设计为；每个像素单元组包括红色像素单元、绿色像素单元和蓝色像素单元，其中，红色像素单元包括蓝光LED芯片和设置蓝光LED芯片的上方的红色量子点膜层，绿色像素单元包括蓝光LED芯片和设置在蓝光LED芯片的上方有绿色量子点膜层，蓝色像素单元包括蓝光LED芯片。此种显示架构中，由于各个像素单元中的发光单元，也即LED芯片，其发光颜色均为蓝色，因此，需要额外设置的量子点膜层，以通过单色光激发量子点膜层中的量子点来实现显示全彩化。但量子点膜层会制约显示像素的尺寸，使得显示面板的分辨率难以提高，并增加制造成本，同时还容易产生相邻像素单元之间出光串扰的问题。
实施例一
第一方面，本申请实施例一提供一种显示面板，能够在无需设置量子点膜层的同时，实现全彩化，进而提高显示面板的分辨率，降低制造成本和提高显示质量。
图1为本申请实施例一提供的设置在阵列基板的一侧的像素单元组的膜层结构示意图。参照图1所示，本申请实施例一提供一种显示面板，所述显示面板包括阵列基板10和多个像素单元组20，所述像素单元组20设置在所述阵列基板10的一侧，每个所述像素单元组20由一个第一像素单元21和一个第二像素单元22组20成，且所述第一像素单元21和所述第二像素单元22在所述阵列基板10上的正投影错位设置，其中，所述第一像素单元21包括具有第一发光颜色的第一发光单元层213；所述第二像素单元22包括具有第二发光颜色的第二发光单元层223和具有第三发光颜色的第三发光单元层226，且所述第二发光单元层223和所述第三发光单元层226在背离所述阵列基板10的方向上依次层叠设置。
本申请提供的所述像素单元组20中，所述第一像素单元21可以通过第一发光单元层213显示所述第一发光颜色；所述第二像素单元22可以通过所述第二发光单元层223显示所述第二发光颜色，和/或通过所述第三发光单元层226显示所述第三发光颜色。因此，所述显示面板能够直接通过所述像素单元组20中的所述第一像素单元21和所述第二像素单元22实现全彩化显示，无需量子点膜层，能够有效降低制造成本，并且，能够消除因设置量子点膜层而导致的像素单元尺寸被制约和出光串扰的问题，使得所述第一像素单元21和所述第二像素单元22的尺寸可以做的更小，从而能够提高分辨率和显示质量。
另外，本申请通过所述第二发光单元层223和所述第三发光单元层226在背离所述阵列基板10的方向上依次层叠设置的方式，使所述第二像素单元22能够发出第二发光颜色和/或第三发光颜色，从而通过一个像素单元实现相关技术中两个像素单元的显示功能，从而能够减少像素单元的数量；相较于相关技术中将不同颜色的发光单元层在水平方向进行堆叠的结构，本申请可节省水平方向上的空间，降低像素单元组20的布局面积，进一步提高显示面板的分辨率，并能够在工艺上减少像素单元的转移次数，简化生产制备工艺，降低生产制造成本。
在本申请的一些实施例中，所述第一发光颜色为红色；所述第二发光颜色为蓝色和绿色的一种；所述第三发光颜色为蓝色和绿色的另一种。
本申请的发明人研究发现，具有蓝色发光颜色和绿色发光颜色的发光单元层的材质通常为InGaN/GaN量子阱材料，具有蓝色发光颜色的发光单元层和具有绿色发光颜色的发光单元层同轴生长可以保证较好的外延质量得到较高的出光效率。另外，具有红色发光颜色的发光单元层的材质通常为AlGaInP/GaInP量子阱材料，材料上的差异，使得具有红色发光颜色的发光单元层，难以和具有蓝色发光颜色的发光单元层和具有绿色发光颜色的发光单元层同轴生长。本申请通过将所述第一发光颜色选定为红色；所述第二发光颜色选定为蓝色和绿色的一种；所述第三发光颜色选定为蓝色和绿色的另一种，能够保证像素单元的发光效果，提高制备良率。
此外，相较于相关技术中将红色发光层、绿色发光层和蓝色发光层在垂直方向进行堆叠的结构，本申请由于在垂直于所述阵列基板10的方向上，所述第一像素单元21中除具有红色发光颜色的发光单元层外，并无其他发光单元层，从而能够保证具有红色发光颜色的发光单元层的发光效率；而目前红色发光单元层的发光效率是制约Micro-LED显示面板整体发光效率的主要因素，因此红色发光单元层的发光效率提升可有效提升显示面板的整体发光效率。
综上，相较于现有技术，本申请可有效兼顾显示面板的分辨率和整体的发光效率。
在本申请的一些实施例中，所述第一像素单元21包括在背离所述阵列基板10的方向上依次层叠设置的第一掺杂类型的第一半导体层212、所述第一发光单元层213、第二掺杂类型的第二半导体层214；所述第二像素单元22包括在背离所述阵列基板10的方向上依次层叠设置的第二掺杂类型的第三半导体层222、所述第二发光单元层223、第一掺杂类型的第四半导体层224、所述第三发光单元层226、第二掺杂类型的第五半导体层227；其中，所述第一掺杂类型为N型或P型的一种，所述第二掺杂类型为N型或P型的另一种。
本申请提供的所述第一像素单元21中，由于位于所述第一发光单元层213两侧的所述第一半导体层212和所述第二半导体层214的掺杂类型不同，因此，能够形成PN结，进而可以通过PN结的导通和截至控制所述第一发光单元层213的发光状态；本申请提供的所述第二像素单元22中，由于所述第二发光单元层223两侧的所述第三半导体层222和所述第四半导体层224的掺杂类型不同，因此，能够形成PN结，进而可以通过PN结的导通和截至控制所述第二发光单元层223的发光状态；另外，由于所述第三发光单元层226两侧的所述第五半导体层227和所述第四半导体层224的掺杂类型不同，因此，能够形成PN结，进而可以通过PN结的导通和截至控制所述第三发光单元层226的发光状态。进而，可以通过所述显示面板中的驱动电路独立控制所述第一发光单元层213、所述第二发光单元层223和所述第三发光单元层226的发光状态，实现全彩化显示。
在本申请的一些实施例中，所述第一掺杂类型为P型；所述第二掺杂类型为N型，其中，所述第二掺杂类型的第二半导体层214和所述第一发光单元层213之间还设置有周期应力调节层及电流扩散层；所述第二掺杂类型的第三半导体层222和所述第二发光单元层223之间还设置有周期应力调节层及电流扩散层；所述第二掺杂类型的第五半导体层227和所述第三发光单元层226之间还设置有周期应力调节层及电流扩散层；所述第一掺杂类型的第一半导体层212和所述第一发光单元层213之间还设置有周期应力调节层、电流扩散层及第一布拉格反射层，所述第一布拉格反射层能够透射红色光；所述第一掺杂类型的第四半导体层224和所述第三发光单元层226之间还设置有周期应力调节层、电流扩散层及第二布拉格反射层，所述第二布拉格反射层能够透射蓝色光和绿色光。可选的，所述第一布拉格反射层、第二布拉格反射层包括至少一个复合膜层，所述复合膜层为SiO2和Ti3O5形成的叠层结构。
在本申请的一些实施例中，所述第一像素单元21还包括：第一电极211和第二电极215，所述第一电极211与所述第一掺杂类型的第一半导体层212相接触；所述第二电极215与所述第二掺杂类型的第二半导体层214相接触；所述第二像素单元22还包括：第三电极221、第四电极225和第五电极228，所述第三电极221与所述第二掺杂类型的第三半导体层222相接触；所述第四电极225与所述第一掺杂类型的第四半导体层224相接触；所述第五电极228与所述第二掺杂类型的第五半导体层227相接触。
其中，所述第一电极211和所述第四电极225的电极类型相同，均为阳极或阴极的一种，且所述第一电极211和所述第四电极225电连接，也即，所述第一电极211和所第四电极225均为阳极，或所述第一电极211和所第四电极225均为阴极。由于所述第一电极211和所述第四电极225的电极类型相同，因此，可以通过将所述第一电极211和所述第四电极225电连接的方式，使其与阵列基板10上的同一个焊盘电连接，从而减少焊盘数量，简化显示面板的结构，降低绑定难度。
其中，所述第二电极215、所述第三电极221和所述第五电极228的电极类型相同，均为阳极或阴极的另一种，且所述第二电极215、所述第三电极221和所述第五电极228绝缘设置，也即，所述第二电极215、所述第三电极221和所述第五电极228均为阴极，或所述第二电极215、所述第三电极221和所述第五电极228均为阳极。由于所述第二电极215、所述第三电极221和所述第五电极228绝缘设置，因此，可以通过所述第二电极215、所述第三电极221和所述第五电极228分别对所述第一发光单元层213、所述第二发光单元层223和所述第三发光单元层226进行独立控制，实现所述第一发光单元层213、所述第二发光单元层223和所述第三发光单元层226的独立发光。
在本申请的一些实施例中，所述第一掺杂类型的第四半导体层224包括未被所述第三发光单元层226所覆盖的第一部分2241，所述第四电极225与所述第一部分2241相接触。
本申请提供的所述显示面板中，由于所述第一掺杂类型的第四半导体层224中的所述第一部分2241未被所述第三发光单元层226所覆盖，因此，可以将所述第四电极225电极设置在所述第一部分2241背离所述第二发光单元层223的一侧，降低第四电极225的设置难度。
在本申请的一些实施例中，所述阵列基板10包括：多个焊盘组11，每个焊盘组11对应一个所述像素单元组20，其中，所述焊盘组11包括：第一焊盘111、第二焊盘112、第三焊盘113和第四焊盘114，所述第一焊盘111分别与所述第一电极211和所述第四电极225电连接；所述第二焊盘112与所述第二电极215电连接，所述第三焊盘113与所述第三电极221电连接，所述第四焊盘114与所述第五电极228电连接。
本申请提供的所述显示面板中，由于所述第一焊盘111分别与所述第一电极211和所述第四电极225电连接，从而能够利用一个焊盘对所述第一电极211和所述第四电极225进行控制，减少焊盘设置数量；由于所述第二焊盘112与所述第二电极215电连接，所述第三焊盘113与所述第三电极221电连接，所述第四焊盘114与所述第五电极228电连接，因此，可以通过所述第二焊盘112、所述第三焊盘113和所述第三焊盘113分别对所述第二电极215、所述第三电极221和所述第五电极228进行控制，从而能够实现所述第一发光单元层213、所述第二发光单元层223和所述第三发光单元层226的独立发光。
可选的，所述阵列基板10为集成电路晶圆，所述集成电路晶圆包括驱动电路层和设置在所述驱动电路层上的多个所述焊盘组11。
在本申请的一些实施例中，所述第一电极211设置在所述第一掺杂类型的第一半导体层212朝向所述阵列基板10的一侧，所述第一电极211与所述第一焊盘111接触电连接；所述第三电极221设置在所述第二掺杂类型的第三半导体层222朝向所述阵列基板10的一侧，所述第三电极221与所述第三焊盘113接触电连接。
本申请提供的所述显示面板中，所述第一像素单元21和所述第二像素单元22例如通过金属键合的方式，设置在所述阵列基板10的一侧。由于所述第一电极211与所述第一焊盘111接触电连接，所述第三电极221与所述第三焊盘113接触电连接，从而简化了电极的连接结构，使所述显示面板更为轻薄，并且可以在工艺上通过芯片键合的方式形成所述第一像素单元21和所述第二像素单元22，简化生产制备工艺。
在本申请的一些实施例中，所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧的表面，与所述阵列基板10之间的距离为第一距离；所述第二掺杂类型的第五半导体层227背离所述阵列基板10的一侧的表面，与所述阵列基板10之间的距离为第二距离；其中，所述第二距离大于所述第一距离。
本申请提供的所述显示面板中，由于所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离，大于所述第二掺杂类型的第五半导体层227背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离，因此，所述第二像素单元22的整体厚度大于所述第一像素单元21的整体厚度，因此，当所述第一像素单元21通过金属键合工艺形成于所述阵列基板10的一侧后，在所述第二像素单元22通过金属键合工艺形成于所述阵列基板10的一侧的过程中，确保设置在所述第三半导体层222远离所述第二发光单元层223的一侧的键合金属层能够与所述阵列基板10一侧的键合金属层充分接触，完成金属键合，形成所述第三电极221。
在本申请的一些实施例中，所述显示面板还包括多条连接线50，所述第二电极215通过所述连接线50与所述第二焊盘112电连接，所述第四电极225通过所述连接线50与所述第三焊盘113电连接，所述第五电极228通过所述连接线50与所述第四焊盘114电连接。
在本申请的一些实施例中，所述显示面板还包括绝缘层40，所述绝缘层40设置在所述连接线50与所述第一像素单元21之间以及所述连接线50与所述第二像素单元22之间。
第二方面，本申请实施例一还提供一种显示面板的制备方法，所述显示面板的制备方法包括以下步骤：
在一第一衬底的一侧形成第一像素复合层，所述第一像素复合层包括依次层叠设置的第二掺杂类型的第二半导体层、第一发光单元层、第一掺杂类型的第一半导体层；在一第二衬底的一侧形成第二像素复合层，所述第二像素复合层包括依次层叠设置的第二掺杂类型的第五半导体层、第三发光单元层、第一掺杂类型的第四半导体层、第二发光单元层、第二掺杂类型的第三半导体层；
将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底；
将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底；
其中，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之前，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之前，对所述第二像素复合层进行图案化处理。
具体的，图2为本申请实施例一提供的显示面板的制备方法中步骤S01所对应的结构示意图；图3为本申请实施例一提供的显示面板的制备方法中步骤S02所对应的结构示意图；图4为本申请实施例一提供的显示面板的制备方法中步骤S03所对应的结构示意图；图5为本申请实施例一提供的显示面板的制备方法中步骤S04所对应的结构示意图；图6为本申请实施例一提供的显示面板的制备方法中步骤S05所对应的结构示意图；图7为本申请实施例一提供的显示面板的制备方法中步骤S06所对应的结构示意图。结合图1-图7所示，所述显示面板的制备方法包括以下步骤：
S01：在一第一衬底101的一侧形成第一像素复合层102，所述第一像素复合层102包括依次层叠设置的第二掺杂类型的第二半导体层214、第一发光单元层213、第一掺杂类型的第一半导体层212；在一第二衬底103的一侧形成第二像素复合层104，所述第二像素复合层104包括依次层叠设置的第二掺杂类型的第五半导体层227、第三发光单元层226、第一掺杂类型的第四半导体层224、第二发光单元层223、第二掺杂类型的第三半导体层222。其中，所述第一衬底101为GaAs衬底；所述第二掺杂类型为N型，所述第二半导体层214包括GaAs材料；所述第一掺杂类型为P型，所述第一类型半导体层包括GaP材料；所述第二衬底103为蓝宝石衬底，或包含GaN、AlN、Si、SiC中的至少一种的衬底；所述第五半导体层227、所述第三半导体层222包括GaN、AlGaN、AlInGaN材料中的至少一种；所述第四半导体层224包括GaN材料。
S02：对所述第一像素复合层102进行图案化处理。
S03：将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，并移除所述第一衬底101。步骤S03具体包括：在所述第一像素复合层102背离所述第一衬底101的一侧形成第一金属键合层，所述第一金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；在所述阵列基板10的一侧形成第二金属键合层，所述第二金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；通过所述第一金属键合层与所述第二金属键合层键合的方式，将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，其中，所述第一金属键合层与所述第二金属键合层键合后形成第一像素单元21的第一电极211，所述阵列基板10包括多个焊盘组11，每个焊盘组11包括第一焊盘111、第二焊盘112、第三焊盘113和第四焊盘114；所述第一电极211与所述第一焊盘111接触电连接，所述第一电极211的厚度为0.1微米至3微米，所述第一电极211还具有反光功能；移除所述第一衬底101。
S04：对所述第二像素复合层104进行图案化处理。
S05：将所述第二像素复合层104背离所述第二衬底103的一侧键合到所述阵列基板10的一侧，并移除所述第二衬底103。步骤S05具体包括：在所述第二像素复合层104背离所述第二衬底103的一侧形成第三金属键合层，所述第三金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；在所述阵列基板10的一侧形成第四金属键合层，所述第四金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；通过所述第三键合层与所述第四键合层键合的方式，将所述第二像素复合层104背离所述第二衬底103的一侧键合到所述阵列基板10的一侧，其中，所述第三金属键合层与所述第四金属键合层键合形成第二像素单元22的第三电极221，所述第三电极221与所述第三焊盘113接触电连接，所述第三电极221的厚度为0.1微米至3微米，所述第三电极221还具有反光功能；移除所述第二衬底103。
S06：在所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧形成第二电极215；在所述第一掺杂类型的第四半导体层224背离所述阵列基板10的一侧形成所述第四电极225；在所述第二掺杂类型的第五半导体层227背离所述阵列基板10的一侧形成第五电极228。其中，所述第二电极215通过连接线50与所述第二焊盘112电连接，所述连接线50与所述第一像素单元21之间形成有绝缘层40；所述第四电极225通过连接线50与所述第三焊盘113电连接，所述第五电极228通过连接线50与第四焊盘114电连接，所述连接线50和所述第二像素单元22之间形成有绝缘层40。
本申请提供的所述显示面板的制备方法中，由于在将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，并移除所述第一衬底101的步骤之前，对所述第一像素复合层102进行图案化处理；在将所述第二像素复合层104背离所述第一衬底101的一侧键合到所述阵列基板10的一侧，移除所述第二衬底103的步骤之前，对所述第二像素复合层104进行图案化处理；因此，能够简化所述显示面板的生产制备工艺，减少工艺步骤。
实施例二
图8为本申请实施例二提供的设置在阵列基板10的一侧的像素单元组20的膜层结构示意图。参照图8所示，本申请实施例二提供一种显示面板，所述显示面板包括阵列基板10和多个像素单元组20，所述像素单元组20设置在所述阵列基板10的一侧，每个所述像素单元组20由一个第一像素单元21和一个第二像素单元22组20成，且所述第一像素单元21和所述第二像素单元22在所述阵列基板10上的正投影错位设置，其中，所述第一像素单元21包括具有第一发光颜色的第一发光单元层213；所述第二像素单元22包括具有第二发光颜色的第二发光单元层223和具有第三发光颜色的第三发光单元层226，且所述第二发光单元层223和所述第三发光单元层226在背离所述阵列基板10的方向上依次层叠设置。
需要说明的是，本申请实施例二提供的所述显示面板的结构与本申请实施例一提供的所述显示面板的结构相类似，本申请实施例二对于相同部分不再赘述。
不同的是，所述第一电极211设置在所述第一掺杂类型的第一半导体层212朝向所述阵列基板10的一侧，且所述第一电极211与所述第一焊盘111接触电连接；所述第三电极221设置在所述第二掺杂类型的第三半导体层222朝向所述阵列基板10的一侧，其中，所述显示面板还包括多个绝缘凸起30，所述绝缘凸起30设置在所述第三电极221和阵列基板10之间，所述第三电极221通过所述绝缘凸起30中的过孔31与所述第三焊盘113电连接。
本申请实施例提供的所述显示面板中，由于所述显示面板还包括多个绝缘凸起30，所述绝缘凸起30设置在所述第三电极221和阵列基板10之间，所述第三电极221通过所述绝缘凸起30中的过孔31与所述第三焊盘113电连接，因此，能够降低所述第一像素单元21和所述阵列基板10键合时的对位精度要求；降低所述第二像素单元22和所述阵列基板10键合时的对位精度要求；有利于降低显示面板的生产制造成本。
在本申请的一些实施例中，所述绝缘凸起30背离所述阵列基板10一侧的表面与所述阵列基板10之间的距离为第三距离；所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离为第四距离；其中，所述第三距离等于所述第四距离。
本申请提供的所述显示面板中，由于所述第三距离等于所述第四距离，因此，能够使所述绝缘凸起30背离所述阵列基板10一侧的表面与所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧的表面位于同一水平面，从而能够为后续所述第二像素单元22的形成提供平坦化条件，保证所述第二像素单元22的形成质量，提高显示面板的显示效果。
第二方面，本申请实施例二还提供一种显示面板的制备方法，所述显示面板的制备方法包括以下步骤：
在一第一衬底的一侧形成第一像素复合层，所述第一像素复合层包括依次层叠设置的第二掺杂类型的第二半导体层、第一发光单元层、第一掺杂类型的第一半导体层；在一第二衬底的一侧形成第二像素复合层，所述第二像素复合层包括依次层叠设置的第二掺杂类型的第五半导体层、第三发光单元层、第一掺杂类型的第四半导体层、第二发光单元层、第二掺杂类型的第三半导体层；
将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底；
将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底；
其中，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之后，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之后，对所述第二像素复合层进行图案化处理，其中，完成所述第一像素复合层的图案化处理之后，在所述第一像素复合层的图案化区域形成绝缘凸起，并形成贯穿所述绝缘凸起的过孔，所述绝缘凸起背离所述阵列基板的一侧的表面与所述阵列基板的距离为第三距离，所述第一像素复合层背离所述阵列基板的一侧的表面与所述阵列基板的距离为第四距离，所述第三距离等于所述第四距离；之后，将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底。
具体的，图9为本申请实施例二提供的显示面板的制备方法中步骤S11所对应的结构示意图；图10为本申请实施例二提供的显示面板的制备方法中步骤S12所对应的结构示意图；图11为本申请实施例二提供的显示面板的制备方法中步骤S13所对应的结构示意图；图12为本申请实施例二提供的显示面板的制备方法中步骤S14所对应的结构示意图；图13为本申请实施例二提供的显示面板的制备方法中步骤S15所对应的结构示意图；图14为本申请实施例二提供的显示面板的制备方法中步骤S16所对应的结构示意图；图15为本申请实施例二提供的显示面板的制备方法中步骤S17所对应的结构示意图；图16为本申请实施例二提供的显示面板的制备方法中步骤S18所对应的结构示意图。结合图8-图16所示，所述显示面板的制备方法包括以下步骤：
S11：在一第一衬底101的一侧形成第一像素复合层102，所述第一像素复合层102包括依次层叠设置的第二掺杂类型的第二半导体层214、第一发光单元层213、第一掺杂类型的第一半导体层212；在一第二衬底103的一侧形成第二像素复合层104，所述第二像素复合层104包括依次层叠设置的第二掺杂类型的第五半导体层227、第三发光单元层226、第一掺杂类型的第四半导体层224、第二发光单元层223、第二掺杂类型的第三半导体层222。其中，所述第一衬底101为GaAs衬底；所述第二掺杂类型为N型，所述第二半导体层214包括GaAs材料；所述第一掺杂类型为P型，所述第一类型半导体层包括GaP材料；所述第二衬底103为蓝宝石衬底，或包含GaN、AlN、Si、SiC中的至少一种的衬底；所述第五半导体层227、所述第三半导体层222包括GaN、AlGaN、AlInGaN材料中的至少一种；所述第四半导体层224包括GaN材料。
S12：将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，并移除所述第一衬底101。步骤S12具体包括：在所述第一像素复合层102背离所述第一衬底101的一侧形成第一金属键合层，所述第一金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；在所述阵列基板10的一侧形成第二金属键合层，所述第二金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；通过所述第一金属键合层与所述第二金属键合层键合的方式，将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，所述第一金属键合层与所述第二金属键合层键合后形成第一复合金属层105，所述第一复合金属层105后续用于形成第一像素单元21的第一电极211，其中，所述阵列基板10包括多个焊盘组11，每个焊盘组11包括第一焊盘111、第二焊盘112、第三焊盘113和第四焊盘114，所述第一电极211与所述第一焊盘111接触电连接，所述第一电极211的厚度为0.1微米至3微米，所述第一电极211还具有反光功能；移除所述第一衬底101。
S13：对所述第一像素复合层102和所述第一复合金属层105进行图案化处理，图案化后的所述第一复合金属层105形成多个所述第一电极211。
S14：在所述第一像素复合层102的图案化区域形成绝缘凸起30。可选的，所述绝缘凸起30背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离为第三距离，所述第一像素复合层102背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离为第四距离，所述第三距离等于所述第四距离。具体可以通过化学机械研磨（CMP）工艺，使所述绝缘凸起30背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离，与所述第一像素复合层102背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离相等。进一步地，在所述第一像素复合层102的图案化区域形成绝缘凸起30的步骤具体包括：在所述第一像素复合层102的图案化区域以及所述第一复合金属层105背离所述阵列基板10的一侧形成绝缘凸起层，此时，所述绝缘凸起层覆盖所述第一像素复合层102；然后，对所述绝缘凸起层执行CMP工艺，以去除所述第一像素复合层102背离所述阵列基板10的一侧的所述绝缘凸起层，使得所述绝缘凸起30背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离，与所述第一像素复合层102背离所述阵列基板10的一侧的表面与所述阵列基板10之间的距离相等。
S15：对所述绝缘凸起30进行蚀刻，形成过孔31，并在所述过孔31内沉积导电材料，所述导电材料与所述第三焊盘113电连接。
S16：将所述第二像素复合层104背离所述第二衬底103的一侧键合到所述阵列基板10的一侧，并移除所述第二衬底103。步骤S16具体包括：在所述第二像素复合层104背离所述第一衬底101的一侧形成第三金属键合层，所述第三金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；在所述阵列基板10的一侧形成第四金属键合层，所述第四金属键合层的材质可以为Au、Sn、In、Ti、Cu中的任意一种；通过所述第三键合层与所述第四键合层键合的方式，将所述第二像素复合层104背离所述第二衬底103的一侧键合到所述阵列基板10的一侧，其中，所述第三金属键合层与所述第四金属键合层键合形成第二复合金属层106，所述第二复合金属层106后续用于形成第二像素单元22的第三电极221，所述第三电极221与所述第三焊盘113接触电连接，所述第三电极221的厚度为0.1微米至3微米，所述第三电极221还具有反光功能；移除所述第二衬底103。
S17：对所述第二像素复合层104和所述第二复合金属层106进行图案化处理，图案化后的所述第二复合金属层106形成多个所述第三电极221。
S18：在所述第二掺杂类型的第二半导体层214背离所述阵列基板10的一侧形成第二电极215；在所述第一掺杂类型的第四半导体层224背离所述阵列基板10的一侧形成所述第四电极225；在所述第二掺杂类型的第五半导体层227背离所述阵列基板10的一侧形成第五电极228。其中，所述第二电极215通过连接线50与所述第二焊盘112电连接，所述连接线50与所述第一像素单元21之间形成有绝缘层40；所述第四电极225通过连接线50与所述第三焊盘113电连接，所述第五电极228通过连接线50与第四焊盘114电连接，所述连接线50和所述第二像素单元22之间形成有绝缘层40。
本申请提供的所述显示面板的制备方法中，由于在将所述第一像素复合层102背离所述第一衬底101的一侧键合到一阵列基板10的一侧，并移除所述第一衬底101的步骤之后，对所述第一像素复合层102进行图案化处理；在将所述第二像素复合层104背离所述第一衬底101的一侧键合到所述阵列基板10的一侧，移除所述第二衬底103的步骤之后，对所述第二像素复合层104进行图案化处理；因此，能够大大降低键合的对位精度要求，有利于降低显示面板的生产制造成本。
综上所述，本申请提供一种显示面板及其制备方法，显示面板包括阵列基板和多个像素单元组，每个像素单元组由一个第一像素单元和一个第二像素单元组成，且第一像素单元和第二像素单元在阵列基板上的正投影错位设置，第一像素单元包括具有第一发光颜色的第一发光单元层；第二像素单元包括具有第二发光颜色的第二发光单元层和具有第三发光颜色的第三发光单元层，且第二发光单元层和第三发光单元层在背离阵列基板的方向上依次层叠设置。本申请提供的显示面板中，由于每个像素单元组由一个第一像素单元和一个第二像素单元，且第二像素单元包括层叠设置的具有不同发光颜色的两种发光单元层，从而能够在实现全彩化显示的同时，提高分辨率，降低成本，提高显示质量。
以上对本申请实施例所提供的一种显示面板及其制备方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括：
    阵列基板；
    多个像素单元组，设置在所述阵列基板的一侧，每个所述像素单元组由一个第一像素单元和一个第二像素单元组成，且所述第一像素单元和所述第二像素单元在所述阵列基板上的正投影错位设置，其中，
    所述第一像素单元包括具有第一发光颜色的第一发光单元层；
    所述第二像素单元包括具有第二发光颜色的第二发光单元层和具有第三发光颜色的第三发光单元层，且所述第二发光单元层和所述第三发光单元层在背离所述阵列基板的方向上依次层叠设置。
  2. 根据权利要求1所述的显示面板，其中，所述第一发光颜色为红色；所述第二发光颜色为蓝色；所述第三发光颜色为绿色。
  3. 根据权利要求2所述的显示面板，其中，
    所述第一像素单元包括在背离所述阵列基板的方向上依次层叠设置的第一掺杂类型的第一半导体层、所述第一发光单元层、第二掺杂类型的第二半导体层；
    所述第二像素单元包括在背离所述阵列基板的方向上依次层叠设置的第二掺杂类型的第三半导体层、所述第二发光单元层、第一掺杂类型的第四半导体层、所述第三发光单元层、第二掺杂类型的第五半导体层；
    其中，所述第一掺杂类型为N型或P型的一种，所述第二掺杂类型为N型或P型的另一种。
  4. 根据权利要求3所述的显示面板，其中，
    所述第一像素单元还包括：
    第一电极，与所述第一掺杂类型的第一半导体层相接触；
    第二电极，与所述第二掺杂类型的第二半导体层相接触；
    所述第二像素单元还包括：
    第三电极，与所述第二掺杂类型的第三半导体层相接触；
    第四电极，与所述第一掺杂类型的第四半导体层相接触；
    第五电极，与所述第二掺杂类型的第五半导体层相接触；
    其中，所述第一电极和所述第四电极的电极类型相同，均为阳极或阴极的一种，且所述第一电极和所述第四电极电连接；
    其中，所述第二电极、所述第三电极和所述第五电极的电极类型相同，均为阳极或阴极的另一种，且所述第二电极、所述第三电极和所述第五电极绝缘设置。
  5. 根据权利要求4所述的显示面板，其中，所述第一掺杂类型的第四半导体层包括未被所述第三发光单元层所覆盖的第一部分，所述第四电极与所述第一部分相接触。
  6. 根据权利要求4所述的显示面板，其中，所述阵列基板包括：多个焊盘组，每个焊盘组对应一个所述像素单元组，
    其中，所述焊盘组包括：第一焊盘、第二焊盘、第三焊盘和第四焊盘，
    所述第一焊盘分别与所述第一电极和所述第四电极电连接；所述第二焊盘与所述第二电极电连接，所述第三焊盘与所述第三电极电连接，所述第四焊盘与所述第五电极电连接。
  7. 根据权利要求6所述的显示面板，其中，
    所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，所述第一电极与所述第一焊盘接触电连接；
    所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，所述第三电极与所述第三焊盘接触电连接。
  8. 根据权利要求7所述的显示面板，其中，
    所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第一距离；
    所述第二掺杂类型的第五半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第二距离；
    其中，所述第二距离大于所述第一距离。
  9. 根据权利要求6所述的显示面板，其中，
    所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，且所述第一电极与所述第一焊盘接触电连接；
    所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，其中，所述显示面板还包括多个绝缘凸起，所述绝缘凸起设置在所述第三电极和阵列基板之间，所述第三电极通过所述绝缘凸起中的过孔与所述第三焊盘电连接。
  10. 根据权利要求9所述的显示面板，其中，
    所述绝缘凸起背离所述阵列基板一侧的表面与所述阵列基板之间的距离为第三距离；
    所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面与所述阵列基板之间的距离为第四距离；
    其中，所述第三距离等于所述第四距离。
  11. 根据权利要求1所述的显示面板，其中，所述第一发光颜色为红色；所述第二发光颜色为绿色；所述第三发光颜色为蓝色；所述第一像素单元包括在背离所述阵列基板的方向上依次层叠设置的第一掺杂类型的第一半导体层、所述第一发光单元层、第二掺杂类型的第二半导体层；
    所述第二像素单元包括在背离所述阵列基板的方向上依次层叠设置的第二掺杂类型的第三半导体层、所述第二发光单元层、第一掺杂类型的第四半导体层、所述第三发光单元层、第二掺杂类型的第五半导体层；
    其中，所述第一掺杂类型为N型或P型的一种，所述第二掺杂类型为N型或P型的另一种。
  12. 根据权利要求11所述的显示面板，其中，
    所述第一像素单元还包括：
    第一电极，与所述第一掺杂类型的第一半导体层相接触；
    第二电极，与所述第二掺杂类型的第二半导体层相接触；
    所述第二像素单元还包括：
    第三电极，与所述第二掺杂类型的第三半导体层相接触；
    第四电极，与所述第一掺杂类型的第四半导体层相接触；
    第五电极，与所述第二掺杂类型的第五半导体层相接触；
    其中，所述第一电极和所述第四电极的电极类型相同，均为阳极或阴极的一种，且所述第一电极和所述第四电极电连接；
    其中，所述第二电极、所述第三电极和所述第五电极的电极类型相同，均为阳极或阴极的另一种，且所述第二电极、所述第三电极和所述第五电极绝缘设置。
  13. 根据权利要求12所述的显示面板，其中，所述第一掺杂类型的第四半导体层包括未被所述第三发光单元层所覆盖的第一部分，所述第四电极与所述第一部分相接触。
  14. 根据权利要求12所述的显示面板，其中，所述阵列基板包括：多个焊盘组，每个焊盘组对应一个所述像素单元组，
    其中，所述焊盘组包括：第一焊盘、第二焊盘、第三焊盘和第四焊盘，
    所述第一焊盘分别与所述第一电极和所述第四电极电连接；所述第二焊盘与所述第二电极电连接，所述第三焊盘与所述第三电极电连接，所述第四焊盘与所述第五电极电连接。
  15. 根据权利要求14所述的显示面板，其中，
    所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，所述第一电极与所述第一焊盘接触电连接；
    所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，所述第三电极与所述第三焊盘接触电连接。
  16. 根据权利要求15所述的显示面板，其中，
    所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第一距离；
    所述第二掺杂类型的第五半导体层背离所述阵列基板的一侧的表面，与所述阵列基板之间的距离为第二距离；
    其中，所述第二距离大于所述第一距离。
  17. 根据权利要求14所述的显示面板，其中，
    所述第一电极设置在所述第一掺杂类型的第一半导体层朝向所述阵列基板的一侧，且所述第一电极与所述第一焊盘接触电连接；
    所述第三电极设置在所述第二掺杂类型的第三半导体层朝向所述阵列基板的一侧，其中，所述显示面板还包括多个绝缘凸起，所述绝缘凸起设置在所述第三电极和阵列基板之间，所述第三电极通过所述绝缘凸起中的过孔与所述第三焊盘电连接。
  18. 根据权利要求17所述的显示面板，其中，
    所述绝缘凸起背离所述阵列基板一侧的表面与所述阵列基板之间的距离为第三距离；
    所述第二掺杂类型的第二半导体层背离所述阵列基板的一侧的表面与所述阵列基板之间的距离为第四距离；
    其中，所述第三距离等于所述第四距离。
  19. 一种显示面板的制备方法，其中，所述显示面板的制备方法包括以下步骤：
    在一第一衬底的一侧形成第一像素复合层，所述第一像素复合层包括依次层叠设置的第二掺杂类型的第二半导体层、第一发光单元层、第一掺杂类型的第一半导体层；在一第二衬底的一侧形成第二像素复合层，所述第二像素复合层包括依次层叠设置的第二掺杂类型的第五半导体层、第三发光单元层、第一掺杂类型的第四半导体层、第二发光单元层、第二掺杂类型的第三半导体层；
    将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底；
    将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底；
    其中，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之前，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之前，对所述第二像素复合层进行图案化处理。
  20. 一种显示面板的制备方法，其中，所述显示面板的制备方法包括以下步骤：
    在一第一衬底的一侧形成第一像素复合层，所述第一像素复合层包括依次层叠设置的第二掺杂类型的第二半导体层、第一发光单元层、第一掺杂类型的第一半导体层；在一第二衬底的一侧形成第二像素复合层，所述第二像素复合层包括依次层叠设置的第二掺杂类型的第五半导体层、第三发光单元层、第一掺杂类型的第四半导体层、第二发光单元层、第二掺杂类型的第三半导体层；
    将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底；
    将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底；
    其中，在将所述第一像素复合层背离所述第一衬底的一侧键合到一阵列基板的一侧，并移除所述第一衬底的步骤之后，对所述第一像素复合层进行图案化处理；在将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底的步骤之后，对所述第二像素复合层进行图案化处理，其中，完成所述第一像素复合层的图案化处理之后，在所述第一像素复合层的图案化区域形成绝缘凸起，并形成贯穿所述绝缘凸起的过孔，所述绝缘凸起背离所述阵列基板的一侧的表面与所述阵列基板的距离为第三距离，所述第一像素复合层背离所述阵列基板的一侧的表面与所述阵列基板的距离为第四距离，所述第三距离等于所述第四距离；之后，将所述第二像素复合层背离所述第二衬底的一侧键合到所述阵列基板的一侧，并移除所述第二衬底。
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