WO2024243770A1 - 异步电路、其实现方法、芯片、介质、产品及电子设备 - Google Patents

异步电路、其实现方法、芯片、介质、产品及电子设备 Download PDF

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Publication number
WO2024243770A1
WO2024243770A1 PCT/CN2023/096808 CN2023096808W WO2024243770A1 WO 2024243770 A1 WO2024243770 A1 WO 2024243770A1 CN 2023096808 W CN2023096808 W CN 2023096808W WO 2024243770 A1 WO2024243770 A1 WO 2024243770A1
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Prior art keywords
asynchronous
handshake
circuit
stage
clock
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English (en)
French (fr)
Inventor
陶明慧
黄宇皓
欧阳伟龙
王侃文
虞志益
李智宇
肖山林
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Huawei Technologies Co Ltd
Sun Yat Sen University
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Huawei Technologies Co Ltd
Sun Yat Sen University
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Priority to PCT/CN2023/096808 priority Critical patent/WO2024243770A1/zh
Priority to CN202380083260.7A priority patent/CN120548525A/zh
Publication of WO2024243770A1 publication Critical patent/WO2024243770A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt

Definitions

  • the present application relates to the field of circuit design technology, and in particular to an asynchronous circuit, an implementation method, a chip, a medium, a product and an electronic device thereof.
  • Asynchronous circuits can be divided into single-track circuits and dual-track circuits.
  • Dual-track circuits embed timing information into the encoding of data, so they are delay-insensitive and data-driven, have low timing requirements, and are more robust, but their area is more than twice that of the corresponding synchronous circuits.
  • Single-track circuits have combinational logic circuits similar to synchronous circuits, and their area is similar to that of synchronous circuits. They are suitable for migration to synchronous EDA tools for design, but single-track circuits require delay matching to ensure the validity of the data, and have high timing requirements. Due to the advantages in area and practical convenience, chips currently choose single-track circuits more for asynchronous circuit design.
  • Synchronous circuits perform timing analysis and optimization on chips based on global clocks, but asynchronous circuits do not have a global clock signal.
  • Asynchronous circuits rely on asynchronous handshake protocols to implement data exchange at all levels of circuits. In order to ensure the correctness of the functions of asynchronous circuits, certain constraints need to be followed between handshake signals.
  • the basic principle of timing analysis of asynchronous single-track circuits is relative timing constraints (RTC), which means that in order to ensure that the asynchronous single-track circuit meets the setup time and hold time constraints, the asynchronous handshake controller needs to delay the matching control handshake trigger interval, and this interval needs to have a relative size relationship with the data path delay.
  • RTC relative timing constraints
  • Traditional synchronous EDA tools use static timing analysis (STA), which automatically analyzes whether the data path meets the timing constraints by setting the period and duty cycle of the synchronous circuit clock. Therefore, how to implement timing analysis and chip design of asynchronous circuits based on current EDA tools is a research difficulty in the industry.
  • the present application provides an asynchronous circuit, an implementation method thereof, a chip, a medium, a product and an electronic device for implementing timing analysis and chip design of the asynchronous circuit based on EDA tools.
  • an asynchronous circuit which may include: a control path and a data path.
  • the control path may specifically include a multi-stage asynchronous handshake controller and a delay unit, wherein the delay unit is inserted between each stage of the asynchronous handshake controller in the multi-stage asynchronous handshake controller; each stage of the asynchronous handshake controller is used to generate a pulse signal, and the delay unit is used to control the asynchronous circuit to meet relative timing constraints.
  • an asynchronous handshake controller is used to first form a multi-stage asynchronous data stream to form an asynchronous pipeline.
  • the asynchronous circuit needs to undergo delay matching and delay units are inserted between the asynchronous handshake controllers to control the relative timing constraints of the entire asynchronous pipeline. If the asynchronous pipeline needs to be expanded, a series of click templates can be inserted into the middle stage of the multi-stage asynchronous handshake controller, so that more levels of asynchronous pipelines can be formed.
  • the first level in the multi-level asynchronous handshake controller is a source end handshake controller with a pair of output handshake protocols
  • the last level in the multi-level asynchronous handshake controller is a receiving end handshake controller with a pair of input handshake protocols
  • the other levels in the multi-level asynchronous handshake controller are two-phase single-rail handshake controllers with a pair of input handshake protocols and a pair of output handshake protocols.
  • the data path may include a multi-level trigger circuit and a combinational logic circuit, and the combinational logic circuit is inserted between the trigger circuits of each level in the multi-level trigger circuit.
  • the multi-level trigger circuit and the multi-level asynchronous handshake controller are set one by one, and each level of the trigger circuit may include one or more triggers.
  • the first level asynchronous handshake controller and the corresponding first level trigger circuit constitute a first level asynchronous data stream, and it can be considered that the asynchronous circuit contains a multi-level asynchronous data stream.
  • the trigger circuits of each level are used to capture and store data according to the pulse signal generated by the corresponding level asynchronous handshake controller, and the combinational logic circuit can process the data.
  • a start signal can be input to the first-level asynchronous handshake controller of the control path to start the asynchronous pipeline.
  • Each level of asynchronous handshake controller will generate the first pulse (fire) signal in sequence at the first level.
  • the data is captured and stored and sent to the combinational logic circuit for data processing and then transmitted to the next level of trigger circuit, until the last level of trigger circuit outputs valid data to complete the data asynchronous transmission.
  • a phase decoupling click template can be used to construct an intermediate level in a multi-level asynchronous handshake controller to implement a handshake protocol for two-phase bundled data.
  • the first-level and last-level asynchronous handshake controllers respectively use variants of the click template to form the head and tail of the control path, namely, the source-end handshake controller and the receiving-end handshake controller, thereby realizing the construction of a complete control pipeline, greatly increasing the availability of the pipeline, and eliminating the need for additional switching circuits at the head and tail of the control path, which can simplify circuit design.
  • a phase decoupled click template can be used to construct an intermediate level in a multi-level asynchronous handshake controller to implement a handshake protocol for two-phase bundled data.
  • the two-phase single-rail handshake controller specifically includes: an XOR gate, an XOR gate, an AND gate, and a phase register.
  • the two input ends of the XOR gate are used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal and an input response signal.
  • the two input ends of the XOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols includes an output request signal and an output response signal.
  • the output end of the XOR gate and the output end of the XOR gate are respectively connected to the two input ends of the AND gate, and the output end of the AND gate is respectively connected to the clock input end of the phase register and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the phase register may include a first phase register and a second phase register.
  • a first delay amount may be individually set between the first phase register and the previous asynchronous handshake controller, and a second delay amount may be individually set between the second phase register and the next asynchronous handshake controller.
  • the first delay amount and the second delay amount may be the same or different, making the circuit design more flexible.
  • the clock input end of the first phase register and the clock input end of the second phase register are both connected to the output end of the AND gate, and the data input end and the data latch output end of the first phase register are both used to transmit a pair of input response signals in the input handshake protocol, and the data input end and the data latch output end of the second phase register are both used to transmit a pair of output request signals in the output handshake protocol.
  • the phase register may also be one to reduce the area occupied by the phase register in the circuit, and the clock input end of the phase register is connected to the output end of the AND gate, and the data input end and the data latch output end of the phase register are both used to transmit a pair of input response signals in the input handshake protocol and a pair of output request signals in the output handshake protocol.
  • the input request signal When the previous asynchronous data stream needs to send valid data, the input request signal will be flipped, and the XOR gate will perform an XOR operation with the input response signal to generate a high-level signal output to one input end of the AND gate.
  • the next asynchronous data stream receives valid data sent by the current asynchronous data stream, it will flip the output response signal, and perform an XOR operation with the output request signal in the XOR gate to generate a high-level signal output to the other input end of the AND gate.
  • the AND gate When both inputs of the AND gate receive high-level signals at the same time, the AND gate will generate a high pulse (click) signal as the clock signal output.
  • the click signal will trigger the phase register to flip, changing the value of the input response signal and the output request signal, thus completing a handshake protocol.
  • This handshake protocol is two-phase, that is, each flip of the input request signal represents the arrival of valid data, rather than a high level being valid.
  • the source handshake controller of the first level in the multi-level asynchronous handshake controller specifically includes: at least two levels of synchronizers, an XOR gate, an AND gate and a phase register.
  • the input end of each level of synchronizer in the at least two levels of synchronizers is used to transmit a start signal, and the output end of the last level of synchronizer in the at least two levels of synchronizers is connected to an input end of the AND gate.
  • a two-level synchronizer can generally be set to eliminate the burrs of the start signal and ensure the stability of the handshake signal inside the asynchronous pipeline.
  • the two input ends of the XOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols include an output request signal and an output response signal.
  • the output end of the XOR gate is connected to the other input end of the AND gate.
  • the output end of the AND gate is respectively connected to the clock input end of the phase register, the clock input end of each level of synchronizer in the at least two levels of synchronizers, and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register are both used to transmit an output request signal in a pair of output handshake protocols.
  • the source handshake controller can generate a pulse signal output when the received start signal is pulled high, and can correctly stop generating local pulse signals when the asynchronous start signal is turned off.
  • the source handshake controller can improve the integrity of the control pipeline, without the need to connect an additional switching circuit at the head of the control pipeline, which can simplify the circuit design.
  • the receiving end handshake controller of the last stage in the multi-stage asynchronous handshake controller specifically includes: an XOR gate and a phase register.
  • the input end of the XOR gate is used to transmit a pair of input handshake protocols
  • the pair of input handshake protocols includes an input request signal and an input response signal.
  • the output end of the XOR gate is connected to the clock input end of the phase register, and the output end of the XOR gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register are both used to transmit a pair of input response signals in the input handshake protocol.
  • the receiving end handshake controller can continuously consume the input request signal.
  • the last stage of the multi-stage asynchronous handshake controller it can improve the integrity of the control pipeline. There is no need to connect an additional switching circuit at the end of the control pipeline, which can simplify the circuit design.
  • the present application also provides a chip, which may include multiple logic circuits, at least some of which are the above-mentioned asynchronous circuits provided in the first aspect.
  • Other logic circuits may also include synchronous circuits, which are not limited here.
  • the chip provided by the present application can be applied to various digital logic chips, especially chips such as Internet of Things chips, artificial intelligence chips, neural network chips, etc., which have huge demands for low-power circuits and high-throughput computing.
  • the characteristics of asynchronous circuits such as no clock, data drive, and high robustness can meet the needs of these chips.
  • the present application provides a method for implementing an asynchronous circuit, which may specifically include: declaring clocks for multi-stage asynchronous handshake controllers in the asynchronous circuit and restoring the clock propagation path.
  • the asynchronous circuit may be the above-mentioned asynchronous circuit without a delay unit provided in the first aspect of the present application, or an asynchronous circuit with a delay unit inserted, or other asynchronous circuits, which are not limited in the present application.
  • the asynchronous circuit is initially synthesized.
  • Delay matching is performed on the multi-stage asynchronous handshake controller, that is, delay units are inserted between each stage of the asynchronous handshake controller (which is also the clock propagation path), and each delay unit may specifically include multiple clock buffer units.
  • the initial delay amount of the delay unit inserted between different stages of asynchronous handshake controllers can be searched in the asynchronous circuit database.
  • the edge_shift of each sub-clock may be readjusted to the minimum value. For example, 0.01 makes the delay in the clock propagation path almost entirely composed of delay units.
  • Synthesize the asynchronous circuit. perform timing analysis on the synthesis results to determine whether the asynchronous circuit after the delay unit is inserted meets the timing constraints. If the timing constraints are not met, adjust the delay unit according to the synthesis results, and synthesize the asynchronous circuit again until the asynchronous circuit with the adjusted delay unit passes the timing constraints. Finally, the timing constraint results can be output.
  • the asynchronous circuit implementation method provided by the present application can perform unified timing analysis on the control part (i.e., control path) and data part (data path) of the asynchronous circuit, use the propagation process of the main clock (i.e., source clock) and the sub-clock to capture the handshake signal in the asynchronous handshake controller, unify the data path and control path of the asynchronous circuit in the clock analysis, and ensure that all circuits of the asynchronous circuit are subject to timing constraints. It can also convert the relative timing constraints of the asynchronous circuit into static timing analysis that can be recognized by traditional EDA tools, and use EDA tools to perform circuit optimization and timing constraints on the asynchronous circuit, so as to effectively improve the efficiency of designing asynchronous single-track circuits.
  • the first level of a multi-level asynchronous handshake controller in a control path of an asynchronous circuit may be a source-end handshake controller having a pair of output handshake protocols
  • the last level of the multi-level asynchronous handshake controller may be a receiving-end handshake controller having a pair of input handshake protocols
  • the other levels of the multi-level asynchronous handshake controller may be a two-phase single-rail handshake controller having a pair of input handshake protocols and a pair of output handshake protocols.
  • a phase decoupled click template can be used to construct an intermediate level in a multi-level asynchronous handshake controller to implement a handshake protocol for two-phase bundled data.
  • the two-phase single-rail handshake controller specifically includes: an XOR gate, an XOR gate, an AND gate, and a phase register.
  • the two input ends of the XOR gate are used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal and an input response signal.
  • the two input ends of the XOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols includes an output request signal and an output response signal.
  • the output end of the XOR gate and the output end of the XOR gate are respectively connected to the two input ends of the AND gate, and the output end of the AND gate is respectively connected to the clock input end of the phase register and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the phase register may include a first phase register and a second phase register.
  • a first delay unit may be separately set between the first phase register and the previous asynchronous handshake controller, and a second delay unit may be separately set between the second phase register and the next asynchronous handshake controller.
  • the delay amounts of the first delay unit and the second delay unit may be the same or different, so that the circuit design is more flexible.
  • the clock input end of the first phase register and the clock input end of the second phase register are both connected to the output end of the AND gate, and the data input end and the data latch output end of the first phase register are both used to transmit a pair of input response signals in the input handshake protocol, and the data input end and the data latch output end of the second phase register are both used to transmit a pair of output request signals in the output handshake protocol.
  • the phase register may also be one to reduce the area occupied by the phase register in the circuit, and the clock input end of the phase register is connected to the output end of the AND gate, and the data input end and the data latch output end of the phase register are both used to transmit a pair of input response signals in the input handshake protocol and a pair of output request signals in the output handshake protocol.
  • the input request signal When the previous level asynchronous data stream needs to send valid data, the input request signal will be flipped, and the XOR gate and the input response signal will be XORed to generate a high-level signal output to one input of the AND gate.
  • the next level asynchronous data stream receives the valid data sent by the current level asynchronous data stream, it will flip the output response signal, and the XOR gate and the output request signal will be XORed to generate a high-level signal output to the other input of the AND gate.
  • the two inputs of the AND gate receive high-level signals at the same time, the AND gate will generate a high-pulse (click) signal as a clock signal output.
  • the click signal triggers the phase register to flip, changing the value of the input response signal and the output request signal, thereby completing a handshake protocol.
  • This handshake protocol is two-phase, that is, each flip of the input request signal represents the arrival of valid data, rather than a high level being valid.
  • phase decoupling click template cannot be used to form A complete asynchronous pipeline also requires two click template variants, the source and sink, to form the head and tail of the asynchronous pipeline, which greatly increases the availability of the pipeline, and requires a start signal to control the start and close of the asynchronous pipeline.
  • the source template is a click template with only one pair of output handshake protocols
  • the sink template is a click template with only one pair of input handshake protocols.
  • the source template can continuously consume input request signals.
  • the source handshake controller of the first level in the multi-level asynchronous handshake controller specifically includes: at least two levels of synchronizers, an exclusive OR gate, an AND gate and a phase register.
  • the input end of each level of synchronizer in at least two levels of synchronizers is used to transmit a start signal, and the output end of the last level of synchronizer in at least two levels of synchronizers is connected to an input end of the AND gate.
  • generally two levels of synchronizers can be set, which can eliminate the burrs of the start signal and ensure the stability of the handshake signal inside the asynchronous pipeline.
  • the two input ends of the exclusive OR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols include an output request signal and an output response signal.
  • the output end of the exclusive OR gate is connected to the other input end of the AND gate.
  • the output end of the AND gate is respectively connected to the clock input end of the phase register, the clock input end of each level of synchronizer in at least two levels of synchronizers, and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register are both used to transmit an output request signal in a pair of output handshake protocols.
  • the source handshake controller can generate a pulse signal output when the received start signal is pulled high, and can correctly stop generating local pulse signals when the asynchronous start signal is turned off.
  • the source handshake controller can improve the integrity of the control pipeline, without the need to connect an additional switching circuit at the head of the control pipeline, which can simplify the circuit design.
  • the receiving end handshake controller of the last stage in the multi-stage asynchronous handshake controller specifically includes: an XOR gate and a phase register.
  • the input end of the XOR gate is used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal and an input response signal.
  • the output end of the XOR gate is connected to the clock input end of the phase register, and the output end of the XOR gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register are both used to transmit a pair of input response signals in the input handshake protocol.
  • the receiving end handshake controller can continuously consume the input request signal, and as the last stage of the multi-stage asynchronous handshake controller, it can improve the integrity of the control pipeline, and there is no need to additionally connect a switching circuit at the end of the control pipeline, which can simplify the circuit design.
  • the data path of the asynchronous circuit may include a multi-stage trigger circuit and a combinational logic circuit (function block), and the combinational logic circuit is inserted between the trigger circuits of each stage in the multi-stage trigger circuit.
  • the multi-stage trigger circuit and the multi-stage asynchronous handshake controller are set in a one-to-one correspondence, and each stage of the trigger circuit may include one or more triggers.
  • the first-stage asynchronous handshake controller and the corresponding first-stage trigger circuit constitute a first-stage asynchronous data stream, and it can be considered that the asynchronous circuit contains a multi-stage asynchronous data stream.
  • the asynchronous handshake controllers of each stage are used to generate pulse signals, and the trigger circuits of each stage are used to capture and store data according to the pulse signals generated by the corresponding-stage asynchronous handshake controllers, and the combinational logic circuit can process the data.
  • the asynchronous circuit constructed includes a multi-level asynchronous data flow to form an asynchronous pipeline.
  • the asynchronous circuit needs to undergo delay matching in subsequent steps, and a delay unit is inserted between the asynchronous handshake controllers to control the relative timing constraints of the entire asynchronous pipeline. If the asynchronous pipeline needs to be expanded, a click template connected in series can be inserted in the middle stage of the multi-level asynchronous handshake controller, so that more levels of asynchronous pipelines can be formed.
  • a start signal can be input to the first-level asynchronous handshake controller of the control path to start the asynchronous pipeline, and the asynchronous handshake controllers of each level will generate the first pulse (fire) signal in sequence at the first level.
  • the data is captured and stored and sent to the combinational logic circuit for data processing and then transmitted to the next level of the trigger circuit until the last level of the trigger circuit outputs valid data to complete the asynchronous transmission of data.
  • This application uses a source template that can use an asynchronous start signal to generate an asynchronous handshake source without glitches, a standard click module, and a sink module that can continuously consume handshake signals to build a complete control pipeline. There is no need to connect additional switching circuits at the beginning and end of the control pipeline, which can simplify the circuit design.
  • the function of the control pipeline is that when the asynchronous start signal is pulled high, the entire control pipeline can normally generate a pulse signal from the first-level asynchronous handshake controller, and when the asynchronous start signal is turned off, it can correctly stop generating local pulse signals.
  • gate-level mapping can also be performed on the logic gate circuits in each level of the asynchronous handshake controller of the asynchronous circuit.
  • Gate-level mapping refers to the mapping between the ports of each logic gate circuit corresponding to the logic code and the ports of each logic gate circuit corresponding to the process, that is, when describing the click unit at the Verilog level, the devices in the process library are directly used for modeling.
  • the logic gate circuits involved in the mapping process can specifically be logic gate circuits such as XOR gates, XNOR gates, and AND gates.
  • the devices in the process library are directly used for modeling, so that the commands of the timing constraints can be directly declared to the specified pins, and at the same time, they are not bound to a specific process, so as to achieve an effect that is independent of the process and improve the flexibility of the design.
  • the output port of the AND gate in the first-stage asynchronous handshake controller (i.e., the source-end handshake controller) can be defined as the master clock (also referred to as the source clock) according to the above-mentioned gate-level mapping.
  • the master clock also referred to as the source clock
  • a clock tree is formed between the master clock and each sub-clock.
  • each phase register used to transmit an output request signal of a pair of output handshake protocols in each stage of the asynchronous handshake controller can be defined as sub-clocks.
  • the master clock needs to declare the period and duty cycle in the subsequent timing constraints, and the sub-clock needs to specify the offset.
  • the sum of the number of master clocks and sub-clocks is equal to the total number of stages of the asynchronous handshake controller.
  • the logic gate circuits such as AND gates, OR gates, etc.
  • the logic gate circuits can be restored to unified attributes to avoid the tool being unable to distinguish the generation of the clock rising and falling edges.
  • the "set_case_analysis" command can be used to restore the attributes.
  • the timing loop in the clock propagation path needs to be interrupted to ensure the normal analysis of the propagation path in the ASIC process.
  • each sub-clock may be set with the same offset (edge_shift) relative to the main clock to ensure that the tool can perform initial synthesis with certain constraints.
  • Synthesis in the chip design process refers to the process of mapping chip design code to transistors.
  • the synthesis of the asynchronous clock tree can also be optimized: in order to meet the requirements of the asynchronous clock propagation path, the connection between the asynchronous clocks at various levels is actively interrupted during the clock tree synthesis to ensure that the pulse signal generated locally by each level of the asynchronous handshake controller can balance the clock tree separately, without starting to balance the skew of the clock tree from the main clock of the first level of the asynchronous handshake controller, causing the EDA tool to insert an invalid clock buffer unit as a delay unit on the clock propagation path.
  • the clock input end (C end) of the phase register in the multi-level asynchronous handshake controller is set to exclude pin in the clock tree synthesis stage to achieve the purpose of interrupting the global clock tree and forming a local clock tree.
  • the inserted delay unit it is possible to directly see whether the inserted delay unit is appropriate and whether it passes the timing constraint through the static timing analysis report. If the slack value in the timing analysis report is positive, it proves that the delay matching margin is sufficient and the iteration can be stopped; if the slack value is negative, it means that iteration is still required, that is, more delay units need to be inserted and re-synthesized until the slack value is positive.
  • the timing analysis report when adjusting the delay unit according to the synthesis result, can be compared.
  • the relationship between the offset of each sub-clock and the inserted delay unit is that when the delay unit is larger than the offset of the sub-clock, the delay unit is reduced, and when the delay unit is smaller than the offset of the sub-clock, the delay unit is increased.
  • the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a plurality of programs, the plurality of programs being configured to be executed by one or more processors, and the plurality of programs including instructions for executing the method according to the third aspect.
  • the present application provides a computer program product, which includes a plurality of programs, which are configured to be executed by one or more processors, and which include instructions for executing the method according to the third aspect.
  • the present application provides an electronic device comprising one or more processors; and a memory comprising computer instructions, which, when executed by one or more processors of the electronic device, enable the electronic device to execute the method according to the third aspect.
  • FIG1a is a schematic diagram of the structure of an asynchronous circuit provided by an embodiment of the present application before a delay unit is inserted;
  • FIG1b is a schematic diagram of the structure of an asynchronous circuit provided by an embodiment of the present application after a delay unit is inserted;
  • FIG2a is a schematic diagram of a structure of a two-phase single-rail handshake controller in an asynchronous circuit provided by an embodiment of the present application;
  • FIG2 b is another structural schematic diagram of a two-phase single-rail handshake controller in an asynchronous circuit provided in an embodiment of the present application;
  • FIG3a is a schematic diagram of a structure of a source handshake controller in an asynchronous circuit provided in an embodiment of the present application
  • FIG3b is a schematic diagram of a structure of a receiving end handshake controller in an asynchronous circuit provided in an embodiment of the present application;
  • FIG4 is a flow chart of a method for implementing an asynchronous circuit according to an embodiment of the present application.
  • FIG5 is a schematic diagram of gate-level mapping of an asynchronous circuit provided in an embodiment of the present application.
  • FIG6 is a schematic diagram of clock declaration of an asynchronous circuit provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a clock propagation path for recovering an asynchronous circuit provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of setting a clock input terminal of a phase register of an asynchronous circuit according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a timing analysis report of an asynchronous circuit provided in an embodiment of the present application.
  • references to "one embodiment” or “some embodiments” in this specification mean that one or more embodiments of the present application include a particular feature, structure or characteristic described in conjunction with the embodiment.
  • the phrases “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean “one or more but not all embodiments”.
  • the terms “include”, “comprising”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized.
  • the asynchronous circuit, implementation method, chip, medium, product and electronic device provided in the present application can be applied to various digital logic chips, especially suitable for chips such as Internet of Things chips, artificial intelligence chips, neural network chips, etc. that have huge demands for low-power circuits and high-throughput computing.
  • the characteristics of asynchronous circuits such as no clock, data drive, and high robustness can meet the needs of these chips.
  • An asynchronous circuit may include: a control path 100 and a data path 200.
  • the control path 100 may specifically include a multi-stage asynchronous handshake controller 110 and a delay unit 120, wherein the delay unit 120 is inserted between the various levels of asynchronous handshake controllers in the multi-stage asynchronous handshake controller 110; the various levels of asynchronous handshake controllers 110 are used to generate pulse signals, and the delay unit 120 is used to control the asynchronous circuit to meet the relative timing constraints.
  • the asynchronous handshake controller 110 when constructing an asynchronous circuit, the asynchronous handshake controller 110 is used to first form a multi-stage asynchronous data stream (a three-stage asynchronous data stream is taken as an example in FIG. 1a) to form an asynchronous pipeline.
  • the asynchronous circuit needs to undergo delay matching, and the delay unit 120 is inserted between the asynchronous handshake controllers 110 to control the relative timing constraints of the entire asynchronous pipeline.
  • a click template connected in series can be inserted in the middle level of the multi-stage asynchronous handshake controller 110, so that more levels of asynchronous pipelines can be formed.
  • the first level in the multi-level asynchronous handshake controller 110 is a source handshake controller 112 having a pair of output handshake protocols
  • the last level in the multi-level asynchronous handshake controller 110 is a receiving handshake controller 113 having a pair of input handshake protocols
  • the other levels in the multi-level asynchronous handshake controller 110 are two-phase single-rail handshake controllers 111 having a pair of input handshake protocols and a pair of output handshake protocols.
  • the data path 200 may include a multi-level trigger circuit 210 and a combinational logic circuit 220, and the combinational logic circuit 220 is inserted between the trigger circuits 210 of each level in the multi-level trigger circuit 210.
  • the multi-level trigger circuit 210 and the multi-level asynchronous handshake controller 110 are arranged one by one, and each level of the trigger circuit 210 may include one or more triggers D.
  • the first level of asynchronous handshake controller 110 and the corresponding first level trigger circuit 210 constitute a first level of asynchronous data flow, and it can be considered that the asynchronous circuit contains a multi-level asynchronous data flow.
  • the trigger circuit 210 of each level is used to capture and store data according to the pulse signal generated by the corresponding level of asynchronous handshake controller 110, and the combinational logic circuit 220 can process the data.
  • a start signal can be input to the first-level asynchronous handshake controller 112 of the control path 100 to start the asynchronous pipeline, and each level of asynchronous handshake controller 110 will sequentially generate the first pulse (fire) signal at the first level.
  • the valid data In_Data is input to the data path 200
  • each level of trigger circuit 210 receives the pulse signal generated by the corresponding level of asynchronous handshake controller 110
  • the data is captured and stored and sent to the combinational logic circuit 220 for data processing and then transmitted to the next level of trigger circuit 210, until the last level of trigger circuit 210 outputs the valid data Out_Data to complete the data asynchronous transmission.
  • a phase decoupling click template can be used to construct the middle level in the multi-level asynchronous handshake controller to implement the handshake protocol of two-phase bundled data.
  • the first-level and last-level asynchronous handshake controllers respectively use variants of the click template to form the head and tail of the control path, namely the source handshake controller and the receiving handshake controller, thereby realizing the construction of a complete control pipeline, greatly increasing the availability of the pipeline, and eliminating the need to connect additional switching circuits at the beginning and end of the control path, which can simplify the circuit design.
  • a phase decoupled click template can be used to construct an intermediate level, realizing the handshake protocol of two-phase bundled data.
  • the two-phase single-rail handshake controller 111 specifically includes: an XOR gate, an XOR gate, an AND gate and a phase register.
  • the two input ends of the XOR gate are used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal In_Req and an input response signal In_Ack.
  • the two input ends of the XOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols includes an output request signal Out_Req and an output response signal Out_Ack.
  • the output end of the XOR gate and the output end of the XOR gate are respectively connected to the two input ends of the AND gate, and the output end of the AND gate is respectively connected to the clock input end of the phase register and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the phase register may include a first phase register Pi and a second phase register Po.
  • a first delay unit may be separately set between the first phase register Pi and the previous asynchronous handshake controller, and a second delay unit may be separately set between the second phase register Po and the next asynchronous handshake controller.
  • the delay amounts of the first delay unit and the second delay unit may be the same or different, making the circuit design more flexible.
  • the clock input terminal of the first phase register Pi and the clock input terminal of the second phase register Pi are both connected to the output terminal of the AND gate, and the data input terminal and the data latch output terminal of the first phase register Pi are both used to transmit a pair of input response signals In_Ack in the input handshake protocol, and the data input terminal and the data latch output terminal of the second phase register Po are both used to transmit a pair of output request signals Out_Req in the output handshake protocol.
  • the phase register can also be one to reduce the area occupied by the phase register in the circuit.
  • the clock input terminal of the phase register P is connected to the output terminal of the AND gate, and the data input terminal and the data latch output terminal of the phase register P are both used to transmit an input response signal In_Ack in a pair of input handshake protocols and an output request signal Out_Req in a pair of output handshake protocols.
  • the input request signal In_Req When the previous asynchronous data stream needs to send valid data In_Data, the input request signal In_Req will be flipped, and the XOR operation with the input response signal In_Ack will be performed in the XOR gate to generate a high-level signal output to one input end of the AND gate.
  • the output response signal Out_Ack When the next asynchronous data stream receives the valid data Out_Data sent by the current asynchronous data stream, the output response signal Out_Ack will be flipped, and the XOR operation with the output request signal Out_Req will be performed in the XOR gate to generate a high-level signal output to the other input end of the AND gate.
  • the source handshake controller 112 of the first level in the multi-level asynchronous handshake controller specifically includes: at least two levels of synchronizers, an XNOR gate, an AND gate and a phase register P.
  • the input end of each level synchronizer S (Set) in at least two levels of synchronizers is used to transmit the start signal start, and the output end of the last level synchronizer S in at least two levels of synchronizers is connected to an input end of the AND gate.
  • two levels of synchronizers S can generally be set to eliminate the burrs of the start signal and ensure the stability of the handshake signal inside the asynchronous pipeline.
  • the two input ends of the XNOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols include an output request signal Out_Req and an output response signal Out_Ack.
  • the output end of the XNOR gate is connected to the other input end of the AND gate.
  • the output end of the AND gate is respectively connected to the clock input end of the phase register P, the clock input end of each level synchronizer in at least two levels of synchronizers, and the clock input end of the trigger D, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the data input terminal and the data latch output terminal of the phase register P are used to transmit a pair of output request signals Out_Req in the output handshake protocol.
  • the source handshake controller 112 can generate a pulse signal output when the received start signal is pulled high, and can correctly stop when the asynchronous start signal is turned off.
  • the source handshake controller 112 as the first stage of the multi-stage asynchronous handshake controller can improve the integrity of the control pipeline, and does not need to connect an additional switching circuit at the head of the control pipeline, which can simplify the circuit design.
  • the receiving end handshake controller 113 of the last stage in the multi-stage asynchronous handshake controller specifically includes: an XOR gate and a phase register P.
  • the input end of the XOR gate is used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal In_Req and an input response signal In_Ack.
  • the output end of the XOR gate is connected to the clock input end of the phase register P, and the output end of the XOR gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register P are both used to transmit the input response signal In_Ack in a pair of input handshake protocols.
  • the receiving end handshake controller 113 can continuously consume the input request signal In_req. As the last stage of the multi-stage asynchronous handshake controller, it can improve the integrity of the control pipeline, and there is no need to connect an additional switching circuit at the end of the control pipeline, which can simplify the circuit design.
  • an embodiment of the present application also provides a chip, which may include multiple logic circuits, at least some of which are the above-mentioned asynchronous circuits provided in the embodiment of the present application.
  • Other logic circuits may also include synchronous circuits, which are not limited here.
  • the chip provided in this application can be applied to various digital logic chips, especially chips such as Internet of Things chips, artificial intelligence chips, neural network chips, etc., which have huge demands for low-power circuits and high-throughput computing.
  • the characteristics of asynchronous circuits such as no clock, data drive, and high robustness can meet the needs of these chips.
  • the following will describe the implementation method of the asynchronous circuit provided by some embodiments of the present application in conjunction with the example of the above-mentioned asynchronous circuit.
  • the method can be executed by a processor of an electronic device such as a computer. Although the execution of some embodiments of the present disclosure is described herein with a processor, this is only for illustration and does not limit the scope of the present disclosure. Other computing devices, such as a graphics processor, etc., can be used to implement the methods of some embodiments of the present disclosure.
  • the implementation method of the asynchronous circuit provided in the embodiment of the present application may specifically include the following steps:
  • the asynchronous circuit can be the above-mentioned asynchronous circuit provided in the embodiment of the present application without inserting the delay unit, and the circuit structure is described in Figure 1a, which will not be repeated here; it can also be an asynchronous circuit with a delay unit inserted, and the circuit structure is described in Figure 1b, which will not be repeated here; it can also be other asynchronous circuits, which are not limited in the present application.
  • the asynchronous circuit may include a control path and a data path
  • the control path may include a multi-level asynchronous handshake controller
  • the first level of the multi-level asynchronous handshake controller may be a source-end handshake controller with a pair of output handshake protocols
  • the last level of the multi-level asynchronous handshake controller may be a receiving-end handshake controller with a pair of input handshake protocols
  • the other levels of the multi-level asynchronous handshake controller may be a two-phase single-rail handshake controller with a pair of input handshake protocols and a pair of output handshake protocols.
  • a phase decoupling click template can be used to construct an intermediate level in a multi-level asynchronous handshake controller to implement a handshake protocol for two-phase bundled data.
  • the two-phase single-rail handshake controller 111 specifically includes: an XOR gate, an XOR gate, an AND gate, and a phase register.
  • the two input ends of the XOR gate are used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal In_Req and an input response signal In_Ack.
  • the two input ends of the XOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols includes an output request signal Out_Req and an output response signal Out_Ack.
  • the output end of the XOR gate and the output end of the XOR gate are respectively connected to the two input ends of the AND gate, and the output end of the AND gate is respectively connected to the clock input end of the phase register and the clock input end of the trigger, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the phase register may include a first phase register Pi and a second phase register Po.
  • a first delay unit may be separately provided between the first phase register Pi and the previous asynchronous handshake controller, and a second phase register Po may be separately provided between the first phase register Pi and the previous asynchronous handshake controller.
  • a second delay unit can be separately set between the first-level asynchronous handshake controllers, and the delay amounts of the first delay unit and the second delay unit can be the same or different, making the circuit design more flexible.
  • the clock input end of the first phase register Pi and the clock input end of the second phase register Pi are both connected to the output end of the AND gate, and the data input end and the data latch output end of the first phase register Pi are both used to transmit a pair of input response signals In_Ack in the input handshake protocol, and the data input end and the data latch output end of the second phase register Po are both used to transmit a pair of output request signals Out_Req in the output handshake protocol.
  • the phase register can also be one to reduce the area occupied by the phase register in the circuit, and the clock input end of the phase register P is connected to the output end of the AND gate, and the data input end and the data latch output end of the phase register P are both used to transmit a pair of input response signals In_Ack in the input handshake protocol and a pair of output request signals Out_Req in the output handshake protocol.
  • the source handshake controller 112 of the first level in the multi-level asynchronous handshake controller specifically includes: at least two levels of synchronizers, an XNOR gate, an AND gate, and a phase register P.
  • the input end of each level synchronizer S (Set) in at least two levels of synchronizers is used to transmit the start signal start, and the output end of the last level synchronizer S in at least two levels of synchronizers is connected to an input end of the AND gate.
  • two levels of synchronizers S can generally be set to eliminate the burrs of the start signal and ensure the stability of the handshake signal inside the asynchronous pipeline.
  • the two input ends of the XNOR gate are used to transmit a pair of output handshake protocols, and the pair of output handshake protocols include an output request signal Out_Req and an output response signal Out_Ack.
  • the output end of the XNOR gate is connected to the other input end of the AND gate.
  • the output end of the AND gate is respectively connected to the clock input end of the phase register P, the clock input end of each level synchronizer in at least two levels of synchronizers, and the clock input end of the trigger D, and the output end of the AND gate is used to generate a pulse signal as a clock signal.
  • the data input terminal and the data latch output terminal of the phase register P are both used to transmit a pair of output request signals Out_Req in the output handshake protocol.
  • the source-end handshake controller 112 can generate a pulse signal output when the received start signal is pulled high, and can correctly stop generating a local pulse signal when the asynchronous start signal is turned off.
  • the source-end handshake controller 112, as the first stage of a multi-stage asynchronous handshake controller, can improve the integrity of the control pipeline, without the need to connect an additional switching circuit at the head of the control pipeline, which can simplify the circuit design.
  • the receiving end handshake controller 113 of the last stage in the multi-stage asynchronous handshake controller specifically includes: an XOR gate and a phase register P.
  • the input end of the XOR gate is used to transmit a pair of input handshake protocols, and the pair of input handshake protocols includes an input request signal In_Req and an input response signal In_Ack.
  • the output end of the XOR gate is connected to the clock input end of the phase register P, and the output end of the XOR gate is used to generate a pulse signal as a clock signal.
  • the data input end and the data latch output end of the phase register P are both used to transmit the input response signal In_Ack in a pair of input handshake protocols.
  • the receiving end handshake controller 113 can continuously consume the input request signal In_req. As the last stage of the multi-stage asynchronous handshake controller, it can improve the integrity of the control pipeline, and there is no need to connect an additional switching circuit at the end of the control pipeline, which can simplify the circuit design.
  • the data path 200 (data path) of the asynchronous circuit may include a multi-stage trigger circuit 210 and a combinational logic circuit 220 (function block), and the combinational logic circuit 220 is inserted between the trigger circuits 210 of each stage in the multi-stage trigger circuit 210.
  • the multi-stage trigger circuit 210 and the multi-stage asynchronous handshake controller 110 are arranged one by one, and each stage of the trigger circuit 210 may include one or more triggers D.
  • the first-stage asynchronous handshake controller 110 and the corresponding first-stage trigger circuit 210 constitute a first-stage asynchronous data stream, and it can be considered that the asynchronous circuit contains a multi-stage asynchronous data stream.
  • the asynchronous handshake controller 110 of each stage is used to generate a pulse signal
  • the trigger circuit 210 of each stage is used to capture and store data according to the pulse signal generated by the corresponding stage asynchronous handshake controller 110, and the combinational logic circuit 220 can process the data.
  • Gate-level mapping refers to the mapping between the ports of each logic gate circuit corresponding to the logic code and the ports of each logic gate circuit corresponding to the process, that is, when describing the click unit at the Verilog level, directly use the devices in the process library for modeling.
  • the logic gate circuits involved in the mapping process can specifically be the XOR gate, XNOR gate and AND gate logic gate circuits circled by the dotted box in Figure 5. Since the ports of the logic gate circuit need to be declared when performing timing constraints later, the devices in the process library are directly used for modeling, so that the commands of the timing constraints can be directly declared to the specified pins, and at the same time, they are not bound to a specific process, achieving an effect that is independent of the process and improving the flexibility of the design.
  • the output port of the AND gate in the first-stage asynchronous handshake controller (i.e., the source-end handshake controller 112) can be defined as the master clock (also referred to as the source clock) according to the above-mentioned gate-level mapping.
  • the master clock also referred to as the source clock
  • a clock tree is formed between the master clock and each sub-clock.
  • each phase register P used to transmit an output request signal of a pair of output handshake protocols in each stage of the asynchronous handshake controller can be defined as sub-clocks.
  • the master clock needs to declare the period and duty cycle in the subsequent timing constraints, and the sub-clock needs to specify the offset.
  • the sum of the number of master clocks and sub-clocks is equal to the total number of stages of the asynchronous handshake controller 110.
  • the logic gate circuits such as AND gates, OR gates, etc.
  • the logic gate circuits with non-unified attributes in the clock propagation path can be restored to unified attributes to avoid the tool being unable to distinguish the generation of the clock rising and falling edges.
  • the "set_case_analysis" command can be used to restore the attributes, as shown in the dotted circle in FIG7.
  • the timing loop in the clock propagation path shown in the dotted box in FIG7 needs to be interrupted to ensure the normal analysis of the propagation path in the ASIC process.
  • each sub-clock can be set with the same offset (edge_shift) relative to the main clock to ensure that the tool can perform initial synthesis with certain constraints.
  • Synthesis in the chip design process refers to the process of mapping chip design code to transistors.
  • the synthesis of the asynchronous clock tree can also be optimized: in order to meet the requirements of the asynchronous clock propagation path, the connection between the asynchronous clocks at various levels is actively interrupted during the clock tree synthesis to ensure that the pulse signal generated locally by each level of the asynchronous handshake controller can balance the clock tree separately, and the clock tree skew will not be balanced from the main clock of the first level of the asynchronous handshake controller, causing the EDA tool to insert an invalid clock buffer unit as a delay unit on the clock propagation path.
  • the clock input end (C end) of the phase register in the multi-level asynchronous handshake controller is set to exclude pin in the clock tree synthesis stage to achieve the purpose of interrupting the global clock tree and forming a local clock tree.
  • Delay matching is performed on the multi-stage asynchronous handshake controller, that is, a delay unit is inserted between each stage of the asynchronous handshake controller (which is also the clock propagation path), and each delay unit may specifically include multiple clock buffer units. Specifically, the initial delay amount of the delay unit inserted between different stages of asynchronous handshake controllers can be found in the asynchronous circuit database.
  • the edge_shift of each sub-clock may be readjusted to a minimum value, such as 0.01, so that the delay in the clock propagation path is almost entirely composed of delay units.
  • step S8 is executed; if the timing constraint is met, the timing constraint result can be output.
  • the left side is the timing analysis report before delay matching is inserted
  • the right side is the timing analysis report after delay matching is inserted. If the slack value in the timing analysis report is positive, it proves that the margin of delay matching is sufficient and iteration can be stopped; if the slack value is negative, it means that iteration is still needed, that is, the delay unit needs to be adjusted and re-synthesized until the slack value is positive.
  • the relationship between the offset of each sub-clock in the timing analysis report and the inserted delay unit can be compared.
  • the delay unit is larger than the offset of the sub-clock, the delay unit is reduced, and when the delay unit is smaller than the offset of the sub-clock, the delay unit is increased.
  • step S9 synthesize the asynchronous circuit again, and then return to step S7.
  • the asynchronous circuit implementation method provided by the present application can perform unified timing analysis on the control part (i.e., control path) and data part (data path) of the asynchronous circuit, use the propagation process of the main clock (i.e., source clock) and the sub-clock to capture the handshake signal in the asynchronous handshake controller, unify the data path and control path of the asynchronous circuit in the clock analysis, and ensure that all circuits of the asynchronous circuit are subject to timing constraints. It can also convert the relative timing constraints of the asynchronous circuit into static timing analysis that can be recognized by traditional EDA tools, and use EDA tools to perform circuit optimization and timing constraints on the asynchronous circuit, so as to effectively improve the efficiency of designing asynchronous single-track circuits.
  • an embodiment of the present disclosure provides an electronic device, including: one or more processors; and a memory including computer instructions, which, when executed by one or more processors of the electronic device, causes the electronic device to execute the above-mentioned implementation method of the asynchronous circuit. Since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the above-mentioned implementation method of the asynchronous circuit, the implementation of the electronic device provided by the embodiment of the present disclosure can refer to the implementation of the above-mentioned implementation method of the asynchronous circuit provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.
  • the embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the implementation method of the above-mentioned asynchronous circuit is implemented. Since the principle of solving the problem by the computer-readable storage medium is similar to the principle of solving the problem by the implementation method of the above-mentioned asynchronous circuit, the implementation of the computer-readable storage medium provided by the embodiment of the present disclosure can refer to the implementation of the implementation method of the above-mentioned asynchronous circuit provided by the embodiment of the present disclosure, and the repeated parts will not be repeated.
  • the program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions/operations specified in the flow chart and/or block diagram to be implemented.
  • the program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.
  • machine-readable storage media would include electrical connections based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage medium, or a computer programmable read-only memory. storage device, a magnetic storage device, or any suitable combination of the above.

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Abstract

本申请公开了一种异步电路、其实现方法、芯片、介质、产品及电子设备，异步电路的控制通路包括多级异步握手控制器，第一级异步握手控制器为具有一对输出握手协议的源端握手控制器，最后一级异步握手控制器为具有一对输入握手协议的收端握手控制器，其他级异步握手控制器为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器。可以使用主时钟和子时钟的传播过程来捕捉异步握手控制器中的握手信号，将数据通路和控制通路统一在时钟分析中，确保对所有电路进行时序约束。并能够将异步电路的相对时序约束转化成能被传统EDA工具识别的静态时序分析，利用EDA工具对异步电路进行电路优化和时序约束，提高设计异步单轨电路的效率。

Description

异步电路、其实现方法、芯片、介质、产品及电子设备 技术领域
本申请涉及电路设计技术领域，尤其涉及一种异步电路、其实现方法、芯片、介质、产品及电子设备。
背景技术
异步电路虽早在上个世纪就已提出，但是由于其较为复杂的设计流程，和同步电子设计自动化(electronic design automation，EDA)工具的蓬勃发展，导致异步电路在很长一段时间内鲜有人问津。但是，物联网(internet of things，IoT)芯片和人工智能芯片等新兴产业的快速发展与需求，对低功耗电路和高吞吐量计算都提出了极大的挑战，让学术界甚至产业界重新关注起了具有无时钟、数据驱动、高鲁棒性特点的异步电路。
异步电路可以分为单轨电路和双轨电路。双轨电路是将时序信息内嵌入数据的编码之中，因此具有延迟不敏感和数据驱动的特性，对时序要求低，鲁棒性更强，但面积是相应同步电路的两倍以上。而单轨电路具有和同步电路相似的组合逻辑电路，面积和同步电路相近，适合迁移到同步EDA工具上进行设计，但单轨电路需要进行延时匹配，以保证数据的有效性，对时序要求高。由于面积上的优势和实际便捷性，目前芯片更多的选择单轨电路来进行异步电路设计。
异步单轨电路设计的一大难点是如何对其进行时序分析。同步电路是基于全局时钟对芯片进行时序分析和优化，但异步电路不存在一个全局时钟信号，异步电路是靠异步握手协议来实现各级电路的数据交换，为了保证异步电路功能的正确性，握手信号之间需要遵循一定的约束。异步单轨电路时序分析的基本原理是相对时序约束(relative timing constraints，RTC)，其含义为：为保证异步单轨电路满足建立时间(setup time)和保持时间(hold time)约束，异步握手控制器需要延迟匹配控制握手触发的间隔，该间隔需要与数据通路延迟有相对大小关系。传统的同步EDA工具使用的是静态时序分析(static timing constraints，STA)，通过设置同步电路时钟的周期和占空比等，使用工具自动分析数据通路是否满足时序约束。因此，如何基于目前的EDA工具实现异步电路的时序分析和芯片设计是业界的研究难点。
发明内容
本申请提供一种异步电路、其实现方法、芯片、介质、产品及电子设备，用以基于EDA工具实现异步电路的时序分析和芯片设计。
第一方面，本申请提供了一种异步电路，可以包括：控制通路和数据通路。控制通路具体可以包括多级异步握手控制器和延迟单元，延迟单元插入在多级异步握手控制器中各级异步握手控制器之间；各级异步握手控制器用于产生脉冲信号，延迟单元用于控制异步电路满足相对时序约束。在构建异步电路时，会采用异步握手控制器先形成多级异步数据流，构成异步流水线。之后，异步电路需要经过延迟匹配，在异步握手控制器之间插入延迟单元，才可以控制整个异步流水线的相对时序约束。如果需要扩展异步流水线，可以在多级异步握手控制器的中间级插入串联的click模板，则可以形成更多级的异步流水线。多 级异步握手控制器中的第一级为具有一对输出握手协议的源端握手控制器，多级异步握手控制器中的最后一级为具有一对输入握手协议的收端握手控制器，多级异步握手控制器中的其他级为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器。数据通路可以包括多级触发电路和组合逻辑电路，组合逻辑电路插入在多级触发电路中的各级触发电路之间。多级触发电路和多级异步握手控制器一一对应设置，每级触发电路可以包括一个或多个触发器，一级异步握手控制器和对应的一级触发电路(以包含一个触发器为例)构成一级异步数据流，可以认为在异步电路中包含多级异步数据流。各级触发电路用于根据对应级异步握手控制器产生的脉冲信号对数据进行捕捉和存储，组合逻辑电路可以对数据进行处理。
在启动异步电路时，可以向控制通路的第一级异步握手控制器输入起始信号，启动异步流水线，各级异步握手控制器会按顺序在第一级开始产生第一个脉冲(fire)信号。有效数据输入至数据通路后，在每级触发电路接收到对应级异步握手控制器产生的脉冲信号后，对数据进行捕捉和存储并发送至组合逻辑电路进行数据处理后传输至下一级触发电路，直至最后一级触发电路输出有效数据完成数据异步传输。
在本申请提供的上述异步电路的控制通路的一种实现方式中，可以采用相位解耦click模板来构建多级异步握手控制器中的中间级，实现两相捆绑数据的握手协议。而第一级和最后一级异步握手控制器分别采用click模板的变体以形成控制通路的头和尾，即源端握手控制器和收端握手控制器，实现了构建完整的控制流水线，大大增加了流水线的可用性，并且无需在控制通路的首尾额外接入转接电路，可以简化电路设计。
在本申请的一种实现方式中，可以采用相位解耦click模板来构建多级异步握手控制器中的中间级，实现两相捆绑数据的握手协议。两相单轨握手控制器具体包括：异或门、同或门、与门和相位寄存器。异或门的两个输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号和输入应答信号。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号和输出应答信号。异或门的输出端和同或门的输出端分别与与门的两个输入端连接，与门的输出端分别与相位寄存器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。
在本申请的一种实现方式中，相位寄存器可以包括第一相位寄存器和第二相寄存器。第一相位寄存器与上一级异步握手控制器之间可以单独设置第一延迟量，第二相寄存器与下一级异步握手控制器之间可以单独设置第二延迟量，第一延迟量和第二延迟量可以相同也可以不同，使得电路设计更灵活。第一相位寄存器的时钟输入端和第二相位寄存器的时钟输入端均与与门的输出端连接，第一相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号，第二相位寄存器的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号。或者，相位寄存器也可以为一个，以减小相位寄存器在电路中所占面积，该相位寄存器的时钟输入端与与门的输出端连接，该相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号和一对输出握手协议中的输出请求信号。
当上一级异步数据流需要发送有效数据时，会对输入请求信号进行一次翻转，在异或门与输入应答信号进行异或操作产生一个高电平信号输出至与门的一个输入端。而下一级异步数据流在接收到本级异步数据流发送的有效数据时,会对输出应答信号进行一次翻转，在同或门与输出请求信号进行同或操作产生一个高电平信号输出至与门的另一个输入端。 当与门的两个输入端同时接收到高电平信号时，与门会产生一个拉高的脉冲(click)信号作为时钟信号输出。click信号会触发相位寄存器翻转，改变输入应答信号和输出请求信号的值，从而完成一次握手协议。这种握手协议是两相的，即输入请求信号的每一次翻转都代表着一个有效数据的到来，而不是高电平才有效。
在本申请的一种实现方式中，多级异步握手控制器中第一级的源端握手控制器具体包括：至少两级同步器、同或门、与门和相位寄存器。至少两级同步器中每级同步器的输入端均用于传输起始信号，至少两级同步器中最后一级同步器的输出端与与门的一个输入端连接。在源端握手控制器中，一般可以设置两级同步器，即可消除起始信号的毛刺，保证异步流水线内部握手信号的稳定。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号和输出应答信号。同或门的输出端与与门的另一个输入端连接。与门的输出端分别与相位寄存器的时钟输入端、至少两级同步器中每级同步器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。相位寄存器的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号。源端握手控制器可以在接收到的start信号拉高时，产生脉冲信号输出，在异步start信号关闭时，能够正确的停止产生本地脉冲信号。源端握手控制器作为多级异步握手控制器的第一级可以提高控制流水线的完整性，无需在控制流水线的头部额外接入转接电路，可以简化电路设计。
在本申请的一种实现方式中，多级异步握手控制器中最后一级的收端握手控制器具体包括：异或门和相位寄存器。异或门的输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号和输入应答信号。异或门的输出端与相位寄存器的时钟输入端连接，异或门的输出端用于产生脉冲信号作为时钟信号。相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号。收端握手控制器可以源源不断的消耗输入请求信号，作为多级异步握手控制器的最后一级可以提高控制流水线的完整性，无需在控制流水线的尾部额外接入转接电路，可以简化电路设计。
第二方面，本申请还提供了一种芯片，可以包括多个逻辑电路，多个逻辑电路中的至少部分逻辑电路为第一方面提供的上述异步电路。其他逻辑电路也可以包括同步电路，在此不做限定。本申请提供的芯片可以应用于各种数字逻辑芯片，尤其适用于诸如物联网芯片、人工智能芯片、神经网络芯片等对低功耗电路和高吞吐量计算都有巨大需求的芯片，异步电路的无时钟、数据驱动、高鲁棒性等特点可以满足这些芯片的需求。
第二方面中任一方面中的任一可能设计可以达到的技术效果，请参照上述第一方面中的任一可能设计可以达到的技术效果，这里不再重复赘述。本申请的这些方面或其它方面在以下实施例的描述中会更加简明易懂。
第三方面，本申请提供了一种异步电路的实现方法，可以具体包括：对异步电路中的多级异步握手控制器进行时钟声明，并恢复时钟传播路径。示例性的，该异步电路可以为本申请第一方面提供的上述未插入延迟单元的异步电路，也可以是插入延迟单元的异步电路，还可以是其他异步电路，本申请对此不做限定。对时钟传播路径设置设定偏移量后，对异步电路进行初次综合。对多级异步握手控制器进行延迟匹配，即在各级异步握手控制器之间(也是时钟传播路径)插入延迟单元，每个延迟单元可以具体包括多个时钟缓冲单元。具体地，在不同级异步握手控制器之间插入的延迟单元的初始延迟量可以在异步电路数据库中查找。去除设定偏移量，具体可以把各子时钟的edge_shift重新调整为最小值例 如0.01，使得时钟传播路径内的延迟几乎都是由延迟单元所构成。对异步电路进行综合。之后对综合结果进行时序分析，确定插入延迟单元后的异步电路是否满足时序约束。在不满足时序约束时，根据综合结果调整延迟单元，对异步电路再次进行综合，直至经过调整后的延迟单元的异步电路通过时序约束。最后，可以输出时序约束结果。
本申请提供的异步电路实现方法，可以对异步电路的控制部分(即控制通路)和数据部分(数据通路)进行统一的时序分析，使用主时钟(即源时钟)和子时钟的传播过程来捕捉异步握手控制器中的握手信号，将异步电路的数据通路和控制通路统一在时钟分析中，确保对异步电路的所有电路进行时序约束。并能够将异步电路的相对时序约束转化成能被传统EDA工具识别的静态时序分析，利用EDA工具对异步电路进行电路优化和时序约束，来有效提高设计异步单轨电路的效率。
在本申请的一种实现方式中，异步电路的控制通路中多级异步握手控制器中的第一级可以为具有一对输出握手协议的源端握手控制器，多级异步握手控制器中的最后一级可以为具有一对输入握手协议的收端握手控制器，多级异步握手控制器中的其他级可以为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器。
在本申请的一种实现方式中，可以采用相位解耦click模板来构建多级异步握手控制器中的中间级，实现两相捆绑数据的握手协议。两相单轨握手控制器具体包括：异或门、同或门、与门和相位寄存器。异或门的两个输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号和输入应答信号。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号和输出应答信号。异或门的输出端和同或门的输出端分别与与门的两个输入端连接，与门的输出端分别与相位寄存器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。
在本申请的一种实现方式中，相位寄存器可以包括第一相位寄存器和第二相寄存器。第一相位寄存器与上一级异步握手控制器之间可以单独设置第一延迟单元，第二相寄存器与下一级异步握手控制器之间可以单独设置第二延迟单元，第一延迟单元和第二延迟单元的延迟量可以相同也可以不同，使得电路设计更灵活。第一相位寄存器的时钟输入端和第二相位寄存器的时钟输入端均与与门的输出端连接，第一相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号，第二相位寄存器的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号。或者，相位寄存器也可以为一个，以减小相位寄存器在电路中所占面积，该相位寄存器的时钟输入端与与门的输出端连接，该相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号和一对输出握手协议中的输出请求信号。
当上一级异步数据流需要发送有效数据时，会对输入请求信号进行一次翻转，在异或门与输入应答信号进行异或操作产生一个高电平信号输出至与门的一个输入端。而下一级异步数据流在接收到本级异步数据流发送的有效数据时,会对输出应答信号进行一次翻转，在同或门与输出请求信号进行同或操作产生一个高电平信号输出至与门的另一个输入端。当与门的两个输入端同时接收到高电平信号时，与门会产生一个拉高的脉冲(click)信号作为时钟信号输出。click信号会触发相位寄存器翻转，改变输入应答信号和输出请求信号的值，从而完成一次握手协议。这种握手协议是两相的，即输入请求信号的每一次翻转都代表着一个有效数据的到来，而不是高电平才有效。
在本申请的一种实现方式中，在本申请实施例中，仅采用相位解耦click模板无法构成 完整的异步流水线，还需要源端(source)和收端(sink)两个click模板的变体以形成异步流水线的头和尾，以大大增加流水线的可用性，并且需要一个起始(start)信号控制异步流水线的启动与关闭。Source模板是只有一对输出握手协议的click模板，sink模板是只有一对输入握手协议的click模板，source模板可以源源不断的消耗输入请求信号。
在本申请的一种实现方式中，在本申请实施例中，多级异步握手控制器中第一级的源端握手控制器具体包括：至少两级同步器、同或门、与门和相位寄存器。至少两级同步器中每级同步器的输入端均用于传输起始信号，至少两级同步器中最后一级同步器的输出端与与门的一个输入端连接。在源端握手控制器中，一般可以设置两级同步器，即可消除起始信号的毛刺，保证异步流水线内部握手信号的稳定。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号和输出应答信号。同或门的输出端与与门的另一个输入端连接。与门的输出端分别与相位寄存器的时钟输入端、至少两级同步器中每级同步器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。相位寄存器的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号。源端握手控制器可以在接收到的start信号拉高时，产生脉冲信号输出，在异步start信号关闭时，能够正确的停止产生本地脉冲信号。源端握手控制器作为多级异步握手控制器的第一级可以提高控制流水线的完整性，无需在控制流水线的头部额外接入转接电路，可以简化电路设计。
在本申请的一种实现方式中，在本申请实施例中，多级异步握手控制器中最后一级的收端握手控制器具体包括：异或门和相位寄存器。异或门的输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号和输入应答信号。异或门的输出端与相位寄存器的时钟输入端连接，异或门的输出端用于产生脉冲信号作为时钟信号。相位寄存器的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号。收端握手控制器可以源源不断的消耗输入请求信号，作为多级异步握手控制器的最后一级可以提高控制流水线的完整性，无需在控制流水线的尾部额外接入转接电路，可以简化电路设计。
在本申请的一种实现方式中，在本申请实施例中，异步电路的数据通路(data path)可以包括多级触发电路和组合逻辑电路(function block)，组合逻辑电路插入在多级触发电路中的各级触发电路之间。多级触发电路和多级异步握手控制器一一对应设置，每级触发电路可以包括一个或多个触发器，一级异步握手控制器和对应的一级触发电路(以包含一个触发器为例)构成一级异步数据流，可以认为在异步电路中包含多级异步数据流。各级异步握手控制器用于产生脉冲信号，各级触发电路用于根据对应级异步握手控制器产生的脉冲信号对数据进行捕捉和存储，组合逻辑电路可以对数据进行处理。
在本申请的一种实现方式中，在本申请实施例中，构建完成的异步电路中包括了多级异步数据流，构成异步流水线。异步电路需要经过后续步骤的延迟匹配，在异步握手控制器之间插入延迟单元，才可以控制整个异步流水线的相对时序约束。如果需要扩展异步流水线，可以在多级异步握手控制器的中间级插入串联的click模板，则可以形成更多级的异步流水线。在启动异步电路时，可以向控制通路的第一级异步握手控制器输入起始信号，启动异步流水线，各级异步握手控制器会按顺序在第一级开始产生第一个脉冲(fire)信号。有效数据输入至数据通路后，在每级触发电路接收到对应级异步握手控制器产生的脉冲信号后，对数据进行捕捉和存储并发送至组合逻辑电路进行数据处理后传输至下一级触发电路，直至最后一级触发电路输出有效数据完成数据异步传输。
本申请采用一个可以使用异步起始信号无毛刺产生异步握手源的source模板、一个标准的click模块和一个可以源源不断消耗握手信号的sink模块构建完整的控制流水线，无需在控制流水线的首尾额外接入转接电路，可以简化电路设计。该控制流水线所具有的功能为在异步起始信号拉高时，整个控制流水线可以正常的从第一级异步握手控制器产生脉冲信号，在异步起始信号关闭时，能够正确的停止产生本地脉冲信号。
在本申请的一种实现方式中，在对异步电路中的多级异步握手控制器进行时钟声明之前，还可以先对异步电路的各级异步握手控制器中的逻辑门电路进行门级映射(mapping)。门级映射是指逻辑代码对应的各逻辑门电路的各端口到工艺对应的各逻辑门电路的端口之间的映射，即在verilog层面描述click单元时，直接采用工艺库中的器件进行建模。映射过程中涉及的逻辑门电路具体可以为异或门、同或门以及与门这些逻辑门电路。由于后续进行时序约束时需要声明到逻辑门电路的各端口，直接采用工艺库中的器件进行建模，使时序约束的命令可以直接声明到指定的管脚(pin)，同时不绑定特定工艺，达到与工艺无关的效果，提高了设计的灵活性。
在本申请的一种实现方式中，在对多级异步握手控制器进行时钟声明时，可以按照上述门级映射，将第一级异步握手控制器(即源端握手控制器)中与门的输出端口定义为主时钟(也可以称为源时钟)，为了使DC工具能更好地识别主时钟和子时钟之间的关系，在主时钟和各子时钟之间形成时钟树，可以将各级异步握手控制器(即源端握手控制器和两相单轨握手控制器)中用于传输一对输出握手协议的输出请求信号的各相位寄存器的输出端口分别定义为子时钟。主时钟在后续的时序约束时需要声明周期和占空比，子时钟需要指定偏移量。主时钟与子时钟的数量之和等于异步握手控制器的总级数。
在本申请的一种实现方式中，在恢复时钟传播路径时，可以将时钟传播路径中存在的具有非单因素决定(non-unate)属性的逻辑门电路(例如可以与门、或门等))恢复为单因素决定(unate)属性，以避免工具无法分辨时钟上下降沿的产生，例如可以采用“set_case_analysis”命令恢复属性。并且，需要打断时钟传播路径中的时序环路，才能保证ASIC流程中传播路径的正常分析。
在本申请的一种实现方式中，可以对各子时钟设置相对主时钟相同的偏移量(edge_shift)，以确保工具能够以一定约束进行初次综合。其中，在芯片设计流程中的综合是指将芯片设计代码映射到晶体管的过程。
在本申请的一种实现方式中，在进行初次综合后，还可以对异步时钟树的综合进行优化：为了满足异步时钟传播路径的要求，在进行时钟树综合时主动打断各级异步时钟的之间联系，以确保每级异步握手控制器本地产生的脉冲信号可以分别做时钟树的平衡，而不会从第一级异步握手控制器的主时钟就开始平衡时钟树的偏移(skew)，导致EDA工具在时钟传播路径上插入无效的时钟缓冲单元作为延迟单元。例如使用synopsys的ICC工具时，在时钟树综合阶段对多级异步握手控制器中的相位寄存器的时钟输入端(C端)设置为exclude pin，实现打断全局时钟树、形成局部时钟树的目的。
在本申请的一种实现方式中，具体可以直接通过静态时序分析报告即可看到插入的延迟单元是否合适，是否通过时序约束。在时序分析报告中若slack值为正，则证明延迟匹配的余量已足够，可以停止迭代；若slack值为负，则说明还需要迭代即需要插入更多的延迟单元重新综合，直至slack值为正为止。
在本申请的一种实现方式中，根据综合结果调整延迟单元时，可以比对时序分析报告 中的各子时钟的偏移量与插入的延迟单元之间的关系，在延迟单元大于子时钟的偏移量时，减少延迟单元，在延迟单元小于子时钟的偏移量时，增加延迟单元。
第四方面，本申请提供了一种计算机可读存储介质。计算机可读存储介质存储多个程序，多个程序被配置为一个或多个处理器执行，多个程序包括用于执行根据第三方面的方法的指令。
第五方面，本申请提供了一种计算机程序产品。该计算机程序产品包括多个程序，多个程序被配置为一个或多个处理器执行，多个程序包括用于执行根据第三方面的方法的指令。
第六方面，本申请提供了一种电子设备，包括一个或多个处理器；包括计算机指令的存储器，计算机指令在由电子设备的一个或多个处理器执行时使得电子设备执行根据第三方面的方法。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1a为本申请实施例提供的异步电路在未插入延迟单元之前的结构示意图；
图1b为本申请实施例提供的异步电路在插入延迟单元之后的结构示意图；
图2a为本申请实施例提供的异步电路中两相单轨握手控制器的一种结构示意图；
图2b为本申请实施例提供的异步电路中两相单轨握手控制器的另一种结构示意图；
图3a为本申请实施例提供的异步电路中源端握手控制器的一种结构示意图；
图3b为本申请实施例提供的异步电路中收端握手控制器的一种结构示意图；
图4为本申请实施例提供的异步电路的实现方法的流程示意图；
图5为本申请实施例提供的异步电路进行门级映射的示意图；
图6为本申请实施例提供的异步电路进行时钟声明的示意图；
图7为本申请实施例提供的异步电路恢复时钟传播路径的示意图；
图8为本申请实施例提供的异步电路设置相位寄存器的时钟输入端的示意图；
图9为本申请实施例提供的异步电路的时序分析报告的示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实 施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
另外，在图中相同的附图标记表示相同或类似的结构，因而将省略对它们的重复描述。本申请中所描述的表达位置与方向的词，均是以附图为例进行的说明，但根据需要也可以做出改变，所做改变均包含在本申请保护范围内。本申请的附图仅用于示意相对位置关系不代表真实比例。
本申请提供的一种异步电路、其实现方法、芯片、介质、产品及电子设备可以应用于各种数字逻辑芯片，尤其适用于诸如物联网芯片、人工智能芯片、神经网络芯片等对低功耗电路和高吞吐量计算都有巨大需求的芯片，异步电路的无时钟、数据驱动、高鲁棒性等特点可以满足这些芯片的需求。
本申请实施例提供的一种异步电路，参照图1a和图1b，可以包括：控制通路100和数据通路200。控制通路100具体可以包括多级异步握手控制器110和延迟单元120，延迟单元120插入在多级异步握手控制器110中各级异步握手控制器之间；各级异步握手控制器110用于产生脉冲信号，延迟单元120用于控制异步电路满足相对时序约束。参照图1a，在构建异步电路时，会采用异步握手控制器110先形成多级异步数据流(图1a中以三级异步数据流为例)，构成异步流水线。参照图1b，异步电路需要经过延迟匹配，在异步握手控制器110之间插入延迟单元120，才可以控制整个异步流水线的相对时序约束。如果需要扩展异步流水线，可以在多级异步握手控制器110的中间级插入串联的click模板，则可以形成更多级的异步流水线。多级异步握手控制器110中的第一级为具有一对输出握手协议的源端握手控制器112，多级异步握手控制器110中的最后一级为具有一对输入握手协议的收端握手控制器113，多级异步握手控制器110中的其他级为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器111。数据通路200可以包括多级触发电路210和组合逻辑电路220，组合逻辑电路220插入在多级触发电路210中的各级触发电路210之间。多级触发电路210和多级异步握手控制器110一一对应设置，每级触发电路210可以包括一个或多个触发器D，一级异步握手控制器110和对应的一级触发电路210(以包含一个触发器D为例)构成一级异步数据流，可以认为在异步电路中包含多级异步数据流。各级触发电路210用于根据对应级异步握手控制器110产生的脉冲信号对数据进行捕捉和存储，组合逻辑电路220可以对数据进行处理。
参照图1a和图1b，在本申请实施例中，在启动异步电路时，可以向控制通路100的第一级异步握手控制器112输入起始信号，启动异步流水线，各级异步握手控制器110会按顺序在第一级开始产生第一个脉冲(fire)信号。有效数据In_Data输入至数据通路200后，在每级触发电路210接收到对应级异步握手控制器110产生的脉冲信号后，对数据进行捕捉和存储并发送至组合逻辑电路220进行数据处理后传输至下一级触发电路210，直至最后一级触发电路210输出有效数据Out_Data完成数据异步传输。
在本申请实施例提供的上述异步电路的控制通路中，可以采用相位解耦click模板来构建多级异步握手控制器中的中间级，实现两相捆绑数据的握手协议。而第一级和最后一级异步握手控制器分别采用click模板的变体以形成控制通路的头和尾，即源端握手控制器和收端握手控制器，实现了构建完整的控制流水线，大大增加了流水线的可用性，并且无需在控制通路的首尾额外接入转接电路，可以简化电路设计。
在本申请实施例中，可以采用相位解耦click模板来构建多级异步握手控制器中的中间 级，实现两相捆绑数据的握手协议。参照图2a和图2b，两相单轨握手控制器111具体包括：异或门、同或门、与门和相位寄存器。异或门的两个输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号In_Req和输入应答信号In_Ack。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号Out_Req和输出应答信号Out_Ack。异或门的输出端和同或门的输出端分别与与门的两个输入端连接，与门的输出端分别与相位寄存器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。
参照图2a，相位寄存器可以包括第一相位寄存器Pi和第二相寄存器Po。第一相位寄存器Pi与上一级异步握手控制器之间可以单独设置第一延迟单元，第二相寄存器Po与下一级异步握手控制器之间可以单独设置第二延迟单元，第一延迟单元和第二延迟单元的延迟量可以相同也可以不同，使得电路设计更灵活。第一相位寄存器Pi的时钟输入端和第二相位寄存器Pi的时钟输入端均与与门的输出端连接，第一相位寄存器Pi的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack，第二相位寄存器Po的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号Out_Req。
或者，参照图2b，相位寄存器也可以为一个，以减小相位寄存器在电路中所占面积，该相位寄存器P的时钟输入端与与门的输出端连接，该相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack和一对输出握手协议中的输出请求信号Out_Req。
当上一级异步数据流需要发送有效数据In_Data时，会对输入请求信号In_Req进行一次翻转，在异或门与输入应答信号In_Ack进行异或操作产生一个高电平信号输出至与门的一个输入端。而下一级异步数据流在接收到本级异步数据流发送的有效数据Out_Data时,会对输出应答信号Out_Ack进行一次翻转，在同或门与输出请求信号Out_Req进行同或操作产生一个高电平信号输出至与门的另一个输入端。当同时满足In_Req≠In_Ack和Out_Req＝Out_Ack时，即与门的两个输入端同时接收到高电平信号时，与门会产生一个拉高的脉冲(click)信号作为时钟信号输出。click信号会触发相位寄存器翻转，改变输入应答信号In_Ack和输出请求信号Out_Req的值，从而完成一次握手协议。这种握手协议是两相的，即输入请求信号In_Req的每一次翻转都代表着一个有效数据In_Data的到来，而不是高电平才有效。
在本申请实施例中，参照图3a，多级异步握手控制器中第一级的源端握手控制器112具体包括：至少两级同步器、同或门、与门和相位寄存器P。至少两级同步器中每级同步器S(Set)的输入端均用于传输起始信号start，至少两级同步器中最后一级同步器S的输出端与与门的一个输入端连接。在源端握手控制器112中，一般可以设置两级同步器S，即可消除起始信号的毛刺，保证异步流水线内部握手信号的稳定。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号Out_Req和输出应答信号Out_Ack。同或门的输出端与与门的另一个输入端连接。与门的输出端分别与相位寄存器P的时钟输入端、至少两级同步器中每级同步器的时钟输入端和触发器D的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号Out_Req。源端握手控制器112可以在接收到的start信号拉高时，产生脉冲信号输出，在异步start信号关闭时，能够正确的停 止产生本地脉冲信号。源端握手控制器112作为多级异步握手控制器的第一级可以提高控制流水线的完整性，无需在控制流水线的头部额外接入转接电路，可以简化电路设计。
在本申请实施例中，参照图3b，多级异步握手控制器中最后一级的收端握手控制器113具体包括：异或门和相位寄存器P。异或门的输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号In_Req和输入应答信号In_Ack。异或门的输出端与相位寄存器P的时钟输入端连接，异或门的输出端用于产生脉冲信号作为时钟信号。相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack。收端握手控制器113可以源源不断的消耗输入请求信号In_req，作为多级异步握手控制器的最后一级可以提高控制流水线的完整性，无需在控制流水线的尾部额外接入转接电路，可以简化电路设计。
基于同一发明构思，本申请实施例还提供了一种芯片，可以包括多个逻辑电路，多个逻辑电路中的至少部分逻辑电路为本申请实施例提供的上述异步电路。其他逻辑电路也可以包括同步电路，在此不做限定。本申请提供的芯片可以应用于各种数字逻辑芯片，尤其适用于诸如物联网芯片、人工智能芯片、神经网络芯片等对低功耗电路和高吞吐量计算都有巨大需求的芯片，异步电路的无时钟、数据驱动、高鲁棒性等特点可以满足这些芯片的需求。
下面将结合上述异步电路的示例来描述本申请一些实施例提供的异步电路的实现方法。该方法可以由诸如计算机之类的电子设备的处理器执行。虽然在此以处理器来描述本公开的一些实施例的执行，但是这仅是示意，而非对本公开的范围进行限制。可以使用其它计算装置，例如图形处理器等，来实施本公开的一些实施例的方法。
参照图4，本申请实施例提供的异步电路的实现方法，可以具体包括以下步骤：
S2、对异步电路中的多级异步握手控制器进行时钟声明，并恢复时钟传播路径。
示例性的，该异步电路可以为本申请实施例提供的上述未插入延迟单元的异步电路，电路结构参见图1a处描述，此处不做赘述；也可以是插入延迟单元的异步电路，电路结构参见图1b处描述，此处不做赘述；还可以是其他异步电路，本申请对此不做限定。
示例性的，异步电路可以包括控制通路和数据通路，控制通路可以包括多级异步握手控制器，多级异步握手控制器中的第一级可以为具有一对输出握手协议的源端握手控制器，多级异步握手控制器中的最后一级可以为具有一对输入握手协议的收端握手控制器，多级异步握手控制器中的其他级可以为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器。
示例性的，可以采用相位解耦click模板来构建多级异步握手控制器中的中间级，实现两相捆绑数据的握手协议。例如，参照图2a和图2b，两相单轨握手控制器111具体包括：异或门、同或门、与门和相位寄存器。异或门的两个输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号In_Req和输入应答信号In_Ack。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号Out_Req和输出应答信号Out_Ack。异或门的输出端和同或门的输出端分别与与门的两个输入端连接，与门的输出端分别与相位寄存器的时钟输入端和触发器的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。
参照图2a，相位寄存器可以包括第一相位寄存器Pi和第二相寄存器Po。第一相位寄存器Pi与上一级异步握手控制器之间可以单独设置第一延迟单元，第二相寄存器Po与下 一级异步握手控制器之间可以单独设置第二延迟单元，第一延迟单元和第二延迟单元的延迟量可以相同也可以不同，使得电路设计更灵活。第一相位寄存器Pi的时钟输入端和第二相位寄存器Pi的时钟输入端均与与门的输出端连接，第一相位寄存器Pi的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack，第二相位寄存器Po的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号Out_Req。或者，参照图2b，相位寄存器也可以为一个，以减小相位寄存器在电路中所占面积，该相位寄存器P的时钟输入端与与门的输出端连接，该相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack和一对输出握手协议中的输出请求信号Out_Req。
示例性的，参照图3a，多级异步握手控制器中第一级的源端握手控制器112具体包括：至少两级同步器、同或门、与门和相位寄存器P。至少两级同步器中每级同步器S(Set)的输入端均用于传输起始信号start，至少两级同步器中最后一级同步器S的输出端与与门的一个输入端连接。在源端握手控制器112中，一般可以设置两级同步器S，即可消除起始信号的毛刺，保证异步流水线内部握手信号的稳定。同或门的两个输入端用于传输一对输出握手协议，一对输出握手协议包括输出请求信号Out_Req和输出应答信号Out_Ack。同或门的输出端与与门的另一个输入端连接。与门的输出端分别与相位寄存器P的时钟输入端、至少两级同步器中每级同步器的时钟输入端和触发器D的时钟输入端连接，与门的输出端用于产生脉冲信号作为时钟信号。相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输出握手协议中的输出请求信号Out_Req。源端握手控制器112可以在接收到的start信号拉高时，产生脉冲信号输出，在异步start信号关闭时，能够正确的停止产生本地脉冲信号。源端握手控制器112作为多级异步握手控制器的第一级可以提高控制流水线的完整性，无需在控制流水线的头部额外接入转接电路，可以简化电路设计。
示例性的，参照图3b，多级异步握手控制器中最后一级的收端握手控制器113具体包括：异或门和相位寄存器P。异或门的输入端用于传输一对输入握手协议，一对输入握手协议包括输入请求信号In_Req和输入应答信号In_Ack。异或门的输出端与相位寄存器P的时钟输入端连接，异或门的输出端用于产生脉冲信号作为时钟信号。相位寄存器P的数据输入端和数据锁存输出端均用于传输一对输入握手协议中的输入应答信号In_Ack。收端握手控制器113可以源源不断的消耗输入请求信号In_req，作为多级异步握手控制器的最后一级可以提高控制流水线的完整性，无需在控制流水线的尾部额外接入转接电路，可以简化电路设计。
示例性的，参照图1a和图1b，异步电路的数据通路200(data path)可以包括多级触发电路210和组合逻辑电路220(function block)，组合逻辑电路220插入在多级触发电路210中的各级触发电路210之间。多级触发电路210和多级异步握手控制器110一一对应设置，每级触发电路210可以包括一个或多个触发器D，一级异步握手控制器110和对应的一级触发电路210(以包含一个触发器D为例)构成一级异步数据流，可以认为在异步电路中包含多级异步数据流。各级异步握手控制器110用于产生脉冲信号，各级触发电路210用于根据对应级异步握手控制器110产生的脉冲信号对数据进行捕捉和存储，组合逻辑电路220可以对数据进行处理。
参照图4，在本申请一些实施例中，在对异步电路中的多级异步握手控制器进行时钟声明之前，还可以包括：
S1、对异步电路的各级异步握手控制器中的逻辑门电路进行门级映射(mapping)。门级映射是指逻辑代码对应的各逻辑门电路的各端口到跟工艺对应的各逻辑门电路的端口之间的映射，即在verilog层面描述click单元时，直接采用工艺库中的器件进行建模。
以本申请实施例提供的上述异步电路为例，映射过程中涉及的逻辑门电路具体可以为图5中虚线框圈出的异或门、同或门以及与门这些逻辑门电路。由于后续进行时序约束时需要声明到逻辑门电路的各端口，直接采用工艺库中的器件进行建模，使时序约束的命令可以直接声明到指定的管脚(pin)，同时不绑定特定工艺，达到与工艺无关的效果，提高了设计的灵活性。
参照图6，在本申请实施例中，在对多级异步握手控制器110进行时钟声明时，可以按照上述门级映射，将第一级异步握手控制器(即源端握手控制器112)中与门的输出端口定义为主时钟(也可以称为源时钟)，为了使DC工具能更好地识别主时钟和子时钟之间的关系，在主时钟和各子时钟之间形成时钟树，可以将各级异步握手控制器(即源端握手控制器112和两相单轨握手控制器111)中用于传输一对输出握手协议的输出请求信号的各相位寄存器P的输出端口分别定义为子时钟。主时钟在后续的时序约束时需要声明周期和占空比，子时钟需要指定偏移量。主时钟与子时钟的数量之和等于异步握手控制器110的总级数。
参照图7，在本申请实施例中，在恢复时钟传播路径时，可以将时钟传播路径中存在的具有非单因素决定(non-unate)属性的逻辑门电路(例如可以与门、或门等))恢复为单因素决定(unate)属性，以避免工具无法分辨时钟上下降沿的产生，例如可以采用“set_case_analysis”命令恢复属性，参照图7中虚线圈所示。并且，需要打断图7中虚线框所示的时钟传播路径中的时序环路，才能保证ASIC流程中传播路径的正常分析。
通过上述时钟声明和恢复时钟传播路径，可以实现传播时序约束。
S3、对时钟传播路径设置设定偏移量后，对异步电路进行初次综合。
在本申请实施例中，可以对各子时钟设置相对主时钟相同的偏移量(edge_shift)，以确保工具能够以一定约束进行初次综合。其中，在芯片设计流程中的综合是指将芯片设计代码映射到晶体管的过程。
参照图8，在本申请实施例中，在进行初次综合后，还可以对异步时钟树的综合进行优化：为了满足异步时钟传播路径的要求，在进行时钟树综合时主动打断各级异步时钟的之间联系，以确保每级异步握手控制器本地产生的脉冲信号可以分别做时钟树的平衡，而不会从第一级异步握手控制器的主时钟就开始平衡时钟树的偏移(skew)，导致EDA工具在时钟传播路径上插入无效的时钟缓冲单元作为延迟单元。例如使用synopsys的ICC工具时，在时钟树综合阶段对多级异步握手控制器中的相位寄存器的时钟输入端(C端)设置为exclude pin，实现打断全局时钟树、形成局部时钟树的目的。
S4、对多级异步握手控制器进行延迟匹配，即在各级异步握手控制器之间(也是时钟传播路径)插入延迟单元，每个延迟单元可以具体包括多个时钟缓冲单元。具体地，在不同级异步握手控制器之间插入的延迟单元的初始延迟量可以在异步电路数据库中查找。
S5、去除设定偏移量，具体可以把各子时钟的edge_shift重新调整为最小值例如0.01，使得时钟传播路径内的延迟几乎都是由延迟单元所构成。
S6、对异步电路进行综合。
S7、对综合结果进行时序分析，确定插入延迟单元后的异步电路是否满足时序约束。
在本申请实施例中，具体可以直接通过静态时序分析报告即可看到插入的延迟单元是否合适，是否通过时序约束。在不满足时序约束时，执行步骤S8；在满足时序约束时，可以输出时序约束结果。
参照图9，左侧为插入延迟匹配之前的时序分析报告，右侧为插入延迟匹配后的时序分析报告。在时序分析报告中若slack值为正，则证明延迟匹配的余量已足够，可以停止迭代；若slack值为负，则说明还需要迭代即需要调整延迟单元后重新综合，直至slack值为正为止。
S8、根据综合结果调整延迟单元。
在本申请实施例中，根据综合结果调整延迟单元时，可以比对时序分析报告中的各子时钟的偏移量与插入的延迟单元之间的关系，在延迟单元大于子时钟的偏移量时，减少延迟单元，在延迟单元小于子时钟的偏移量时，增加延迟单元。
S9、对异步电路再次进行综合，之后返回执行步骤S7。
本申请提供的异步电路实现方法，可以对异步电路的控制部分(即控制通路)和数据部分(数据通路)进行统一的时序分析，使用主时钟(即源时钟)和子时钟的传播过程来捕捉异步握手控制器中的握手信号，将异步电路的数据通路和控制通路统一在时钟分析中，确保对异步电路的所有电路进行时序约束。并能够将异步电路的相对时序约束转化成能被传统EDA工具识别的静态时序分析，利用EDA工具对异步电路进行电路优化和时序约束，来有效提高设计异步单轨电路的效率。
基于同一发明构思，本公开实施例提供了一种电子设备，包括：一个或多个处理器；以及包括计算机指令的存储器，计算机指令在由电子设备的一个或多个处理器执行时使得电子设备执行上述异步电路的实现方法。由于该电子设备解决问题的原理与上述异步电路的实现方法解决问题的原理相似，因此，本公开实施例提供的该电子设备的实施可以参见本公开实施例提供的上述异步电路的实现方法的实施，重复之处不再赘述。
基于同一发明构思，本公开实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时实现上述异步电路的实现方法。由于该计算机可读存储介质解决问题的原理与上述异步电路的实现方法解决问题的原理相似，因此，本公开实施例提供的该计算机可读存储介质的实施可以参见本公开实施例提供的上述异步电路的实现方法的实施，重复之处不再赘述。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储 存设备、磁储存设备、或上述内容的任何合适组合。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (16)

  1. 一种异步电路，其特征在于，包括：控制通路和数据通路；
    所述控制通路包括多级异步握手控制器和延迟单元，所述延迟单元插入在所述多级异步握手控制器中各级异步握手控制器之间；所述各级异步握手控制器用于产生脉冲信号，所述延迟单元用于控制所述异步电路满足相对时序约束；
    所述多级异步握手控制器中的第一级为具有一对输出握手协议的源端握手控制器，所述多级异步握手控制器中的最后一级为具有一对输入握手协议的收端握手控制器，所述多级异步握手控制器中的其他级为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器；
    所述数据通路包括多级触发电路和组合逻辑电路，所述组合逻辑电路插入在所述多级触发电路中的各级触发电路之间；所述各级触发电路用于根据对应级异步握手控制器产生的脉冲信号对数据进行捕捉和存储。
  2. 如权利要求1所述的异步电路，其特征在于，所述源端握手控制器包括：至少两级同步器、同或门、与门和相位寄存器；
    所述至少两级同步器中每级同步器的输入端均用于传输起始信号，所述同或门的输入端用于传输一对输出握手协议，所述至少两级同步器中最后一级同步器的输出端和所述同或门的输出端分别与所述与门的输入端连接，所述与门的输出端分别与所述相位寄存器的时钟输入端、所述至少两级同步器中每级同步器的时钟输入端和所述触发电路的时钟输入端连接，所述与门的输出端用于产生所述脉冲信号；
    所述相位寄存器的数据输入端和数据锁存输出端均用于传输所述一对输出握手协议中的输出请求信号。
  3. 如权利要求1所述的异步电路，其特征在于，所述收端握手控制器包括：异或门和相位寄存器；
    所述异或门的输入端用于传输一对输入握手协议，所述异或门的输出端与所述相位寄存器的时钟输入端连接，所述异或门的输出端用于产生所述脉冲信号；所述相位寄存器的数据输入端和数据锁存输出端均用于传输所述一对输入握手协议中的输入应答信号。
  4. 如权利要求1所述的异步电路，其特征在于，所述两相单轨握手控制器包括：异或门、同或门、与门和相位寄存器；
    所述异或门的输入端用于传输一对输入握手协议，所述同或门的输入端用于传输一对输出握手协议，所述异或门的输出端和所述同或门的输出端分别与所述与门的输入端连接，所述与门的输出端分别与所述相位寄存器的时钟输入端和所述触发电路的时钟输入端连接，所述与门的输出端用于产生所述脉冲信号；
    所述相位寄存器用于传输所述一对输入握手协议中的输入应答信号和所述一对输出握手协议中的输出请求信号。
  5. 如权利要求4所述的异步电路，其特征在于，所述相位寄存器包括第一相位寄存器 和第二相位寄存器，所述第一相位寄存器的时钟输入端和所述第二相位寄存器的时钟输入端均与所述与门的输出端连接，所述第一相位寄存器的数据输入端和数据锁存输出端均用于传输所述一对输入握手协议中的输入应答信号，所述第二相位寄存器的数据输入端和数据锁存输出端均用于传输所述一对输出握手协议中的输出请求信号。
  6. 一种芯片，其特征在于，包括多个逻辑电路，所述多个逻辑电路中的至少部分逻辑电路为异步电路，所述异步电路包括控制通路和数据通路；
    所述控制通路包括多级异步握手控制器和延迟单元，所述延迟单元插入在所述多级异步握手控制器中各级异步握手控制器之间；所述各级异步握手控制器用于产生脉冲信号，所述延迟单元用于控制所述异步电路满足相对时序约束；
    所述多级异步握手控制器中的第一级为具有一对输出握手协议的源端握手控制器，所述多级异步握手控制器中的最后一级为具有一对输入握手协议的收端握手控制器，所述多级异步握手控制器中的其他级为具有一对输入握手协议和一对输出握手协议的两相单轨握手控制器；
    所述数据通路包括多级触发电路和组合逻辑电路，所述组合逻辑电路插入在所述多级触发电路中的各级触发电路之间；所述各级触发电路用于根据对应级异步握手控制器产生的脉冲信号对数据进行捕捉和存储。
  7. 一种异步电路的实现方法，其特征在于，包括：
    对异步电路中的多级异步握手控制器进行时钟声明，并恢复时钟传播路径；
    对所述时钟传播路径设置设定偏移量后，对所述异步电路进行初次综合；
    对所述多级异步握手控制器插入延迟单元进行延迟匹配，并去除所述设定偏移量，对所述异步电路进行综合；
    在确定综合后的异步电路未通过时序约束时，根据综合结果调整所述延迟单元，对所述异步电路再次进行综合，直至经过调整后的延迟单元的异步电路通过时序约束。
  8. 如权利要求7所述的实现方法，其特征在于，在对异步电路中的多级异步握手控制器进行时钟声明之前，还包括：
    对所述异步电路的各级异步握手控制器中的逻辑门电路进行门级映射，所述门级映射用于在逻辑代码对应的各逻辑门电路的端口与工艺对应的各逻辑门电路的端口之间进行映射。
  9. 如权利要求7或8所述的实现方法，其特征在于，所述对所述多级异步握手控制器进行时钟声明，包括：
    将所述多级异步握手控制器中第一级异步握手控制器的与门的输出端口定义为主时钟，将多级异步握手控制器中用于传输一对输出握手协议的输出请求信号的各相位寄存器的输出端口分别定义为子时钟。
  10. 如权利要求9所述的实现方法，其特征在于，所述恢复时钟传播路径，还包括：
    将时钟传播路径中存在的具有非单因素决定属性的逻辑门电路恢复为单因素决定属 性，并打断时钟传播路径中的时序环路。
  11. 如权利要求9所述的实现方法，其特征在于，在进行初次综合后，还包括：
    打断各级异步握手控制器之间的异步时钟联系。
  12. 如权利要求11所述的实现方法，其特征在于，打断各级异步握手控制器之间的异步时钟联系，包括：
    将所述多级异步握手控制器中的相位寄存器的时钟输入端设置为exclude_pin。
  13. 如权利要求9-12任一项所述的实现方法，其特征在于，根据综合结果调整所述延迟单元，包括：
    在所述综合结果中确定所述子时钟的偏移量大于所述延迟单元时，增加所述延迟单元；
    在所述综合结果中确定所述子时钟的偏移量小于所述延迟单元时，减少所述延迟单元。
  14. 一种计算机可读存储介质，其特征在于，存储多个程序，所述多个程序被配置为一个或多个处理器执行，所述多个程序包括用于执行权利要求7-13中任一项所述的方法的指令。
  15. 一种计算机程序产品，其特征在于，所述计算机程序产品包括多个程序，所述多个程序被配置为一个或多个处理器执行，所述多个程序包括用于执行权利要求7-13中任一项所述的方法的指令。
  16. 一种电子设备，其特征在于，包括：
    一个或多个处理器；以及
    包括计算机指令的存储器，所述计算机指令在由所述电子设备的所述一个或多个处理器执行时使得所述电子设备执行权利要求7-13中任一项所述的方法。
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