WO2024239228A1 - 驱动电路、驱动方法、驱动模组和显示装置 - Google Patents

驱动电路、驱动方法、驱动模组和显示装置 Download PDF

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Publication number
WO2024239228A1
WO2024239228A1 PCT/CN2023/095760 CN2023095760W WO2024239228A1 WO 2024239228 A1 WO2024239228 A1 WO 2024239228A1 CN 2023095760 W CN2023095760 W CN 2023095760W WO 2024239228 A1 WO2024239228 A1 WO 2024239228A1
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WIPO (PCT)
Prior art keywords
transistor
electrically connected
terminal
node
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/095760
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English (en)
French (fr)
Inventor
于子阳
邱海军
胡明
蒋志亮
承天一
吴建鹏
王梦奇
魏齐
陈文波
张跳梅
艾思飞
刘聪
徐倩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380009175.6A priority Critical patent/CN119604926B/zh
Priority to US18/294,003 priority patent/US12272303B2/en
Priority to PCT/CN2023/095760 priority patent/WO2024239228A1/zh
Publication of WO2024239228A1 publication Critical patent/WO2024239228A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device.
  • the AOD display screen is a screen that controls the partial lighting of the screen without lighting the entire mobile phone screen
  • static screens or seldom updated screens most of the pixel circuits on the entire screen do not need to update the pixel voltage, that is, most of the pixel circuits can be maintained at the original display brightness through low-leakage LTPO (low-temperature polycrystalline oxide) TFT (thin-film transistor), and the repeated rewriting of these pixel circuits causes a waste of power consumption.
  • LTPO low-temperature polycrystalline oxide
  • TFT thin-film transistor
  • an embodiment of the present disclosure provides a driving circuit, including a driving signal generating circuit, a gating circuit, an output control circuit, and an output circuit;
  • the driving signal generating circuit is electrically connected to the N-1th driving signal output terminal and the Nth driving signal output terminal respectively, and is used to perform a shift operation on the N-1th driving signal provided by the N-1th driving signal output terminal, and obtain and output the Nth driving signal through the Nth driving signal output terminal;
  • the gating circuit is electrically connected to the first node, the gating input terminal and the gating control terminal respectively, and is used for controlling the gating input signal provided by the gating input terminal to be written into the first node under the control of the gating control signal provided by the gating control terminal;
  • the first end of the output control circuit is electrically connected to the N-th level drive signal output end, and the second end of the output control circuit is electrically connected to the first node, and is used to perform a negative AND operation on the N-th level drive signal and the potential of the second end of the output control circuit to obtain a first output signal;
  • the output circuit is used to invert the first output signal to obtain an output drive signal and provide it through the output drive terminal;
  • N is a positive integer.
  • the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.
  • the gating control terminal includes a first gating control terminal and a second gating control terminal;
  • the gating circuit includes a first transistor and a second transistor;
  • the gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;
  • the gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;
  • the first gating control terminal is an N-1th level driving signal output terminal
  • the second gating control terminal is an Nth level driving signal output terminal
  • the first transistor is an n-type transistor
  • the second transistor is a p-type transistor
  • the first gating control terminal is an N-th level driving signal output terminal
  • the second gating control terminal is an N-1-th level driving signal output terminal
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the first gating control terminal is connected to the inverted signal of the N-1th level driving signal
  • the second gating control terminal is the output terminal of the Nth level driving signal
  • the first transistor and the second transistor are both p-type transistors
  • the first gating control terminal is an output terminal of the Nth level driving signal, and the second gating control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,
  • the first gating control terminal is the N-1th level driving signal terminal
  • the second gating control terminal is connected to the inverted signal of the Nth level driving signal
  • the first transistor and the second transistor are both n-type transistors
  • the first gating control terminal is connected to the inverted signal of the Nth level driving signal
  • the second gating control terminal is the N-1th level driving signal terminal
  • the first transistor and the second transistor are both n-type transistors.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit
  • the first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the first node respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first voltage maintaining circuit
  • the first end of the first voltage maintaining circuit is electrically connected to the first node
  • the second end of the first voltage maintaining circuit is electrically connected to a DC voltage end or a second node
  • the first voltage maintaining circuit is used to maintain the potential of the first node.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second voltage maintaining circuit, and the first node is electrically connected to the second end of the output control circuit through the second voltage maintaining circuit;
  • the second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit
  • the input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to a third node and the second terminal of the output control circuit;
  • the first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter
  • the second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter
  • the sustain control circuit is electrically connected to the sustain control terminal, the third node and the first node respectively, and is used to control the connection or disconnection between the third node and the first node under the control of a sustain control signal provided by the sustain control terminal.
  • the maintenance control end includes a first maintenance control end and a second maintenance control end;
  • the sustain control circuit includes a third transistor and a fourth transistor
  • the gate of the third transistor is electrically connected to the first sustain control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node;
  • the gate of the fourth transistor is electrically connected to the second sustain control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;
  • the first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or,
  • the first sustain control terminal is a second clock signal terminal
  • the second sustain control terminal is a first clock signal terminal
  • the first inverter includes a fifth transistor and a sixth transistor
  • the second inverter includes a seventh transistor and an eighth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node;
  • the gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;
  • the fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;
  • the gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node;
  • the gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second voltage terminal;
  • the seventh transistor is a p-type transistor
  • the eighth transistor is an n-type transistor.
  • the first initialization circuit includes a ninth transistor, and the first voltage maintaining circuit includes a first capacitor;
  • the gate of the ninth transistor is electrically connected to the initial control terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;
  • the first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the DC voltage end or the second node.
  • the gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;
  • the gate of the fourteenth transistor is electrically connected to the fourth node, the first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the output driving terminal;
  • the gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;
  • the sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.
  • the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor;
  • a gate of the 20th transistor is electrically connected to the first clock signal terminal, a first electrode of the 20th transistor is electrically connected to the first voltage terminal, and a second electrode of the 20th transistor is electrically connected to a first electrode of the 21st transistor;
  • a gate of the twenty-first transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the sixth node;
  • the 20th transistor and the 21st transistor are p-type transistors, and the 22nd transistor and the 23rd transistor are n-type transistors.
  • the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;
  • a gate of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fourth transistor is electrically connected to a first electrode of the twenty-fifth transistor;
  • a gate of the twenty-fifth transistor is electrically connected to the sixth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second voltage terminal;
  • the twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;
  • a gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.
  • an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit, and the driving method includes:
  • the driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal;
  • the gating circuit controls, under the control of the gating control signal, to write the gating input signal provided by the gating input terminal into the first node;
  • the output control circuit performs a NAND operation on the Nth stage driving signal and the potential of the second end of the output control circuit to obtain a first output signal
  • the output circuit is used to invert the first output signal to obtain and provide an output drive signal through the output drive terminal.
  • an embodiment of the present disclosure provides a driving module, comprising a plurality of stages of the above-mentioned driving circuits;
  • the Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.
  • an embodiment of the present disclosure provides a display device, comprising the above-mentioned driving module.
  • FIG1 is a structural diagram of a driving circuit according to an embodiment of the present disclosure.
  • FIG2 is a circuit diagram of a related pixel circuit
  • FIG3 is a working timing diagram of the related pixel circuit shown in FIG2 ;
  • FIG4 is a circuit diagram of a related pixel circuit
  • FIG. 5 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 6 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 7 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 8 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 9 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 11 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG. 12 is a circuit diagram of at least one embodiment of a gating circuit in a driving circuit according to an embodiment of the present disclosure
  • FIG13 is a circuit diagram of at least one embodiment of an inverter
  • FIG14 is a circuit diagram of at least one embodiment of an inverter
  • FIG15 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG16 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG17 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG21 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG22 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG23 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG24 is a timing diagram of operation of at least one embodiment of the driving circuit shown in FIG23;
  • FIG25 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure.
  • FIG26 is a structural diagram of a driving module according to at least one embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the electrodes is called the first electrode and the other is called the second electrode.
  • the first electrode when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
  • the driving circuit includes a driving signal generating circuit 10 , a gating circuit 11 , an output control circuit 12 and an output circuit 13 ;
  • the driving signal generating circuit 10 is electrically connected to the N-1-th driving signal output terminal NS(N-1) and the N-th driving signal output terminal NS(N), respectively, and is used to perform a shift operation on the N-1-th driving signal provided by the N-1-th driving signal output terminal NS(N-1), and obtain and output the N-th driving signal through the N-th driving signal output terminal NS(N);
  • the gating circuit 11 is electrically connected to the first node N1, the gating input terminal VCT and the gating control terminal CX respectively, and is used to control the gating input signal provided by the gating input terminal VCT to be written into the first node N1 under the control of the gating control signal provided by the gating control terminal CX;
  • the first end of the output control circuit 12 is electrically connected to the N-th level drive signal output terminal NS(N), and the second end of the output control circuit 12 is electrically connected to the first node N1, for performing a negative AND operation on the N-th level drive signal and the potential of the second end of the output control circuit to obtain a first output signal;
  • the output circuit 13 is electrically connected to the output control circuit 12 and the output drive terminal NO(N) respectively, and is used to invert the first output signal, obtain and provide an output drive signal through the output drive terminal NO(N);
  • N is a positive integer.
  • the driving signal generating circuit 10 shifts the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1) Operation is performed to obtain and output the Nth level driving signal through the Nth level driving signal output terminal NS(N), and the selection circuit 11 writes the selection input signal into the first node N1 under the control of the selection control signal; the output control circuit 12 performs an AND-NOT operation on the Nth level driving signal and the potential of the second end of the output control circuit 12 to obtain the first output signal, and the output circuit 13 inverts the first output signal to obtain and provide the output driving signal through the output driving terminal NO(N).
  • the embodiment of the driving circuit shown in FIG. 1 of the present disclosure may be an N-th stage driving circuit.
  • the gating circuit 11 Before the Nth stage driving signal providing stage, the gating circuit 11 writes the gating input signal provided by the gating input terminal VCT into the first node N1 under the control of the gating control signal;
  • the Nth level drive signal output terminal NS (N) When the selection input signal is a high voltage signal, in the Nth level drive signal providing stage, the Nth level drive signal output terminal NS (N) outputs a high voltage signal, then the first output signal output by the output control circuit 12 is a low voltage signal, and the output circuit 13 provides a high voltage signal through the output drive terminal NO (N), which can control the corresponding row pixel circuit to update the pixel voltage;
  • the Nth level drive signal output terminal NS (N) When the selection input signal is a low voltage signal, in the Nth level drive signal providing stage, the Nth level drive signal output terminal NS (N) outputs a high voltage signal, then the first output signal output by the output control circuit 12 is a high voltage signal, and the output circuit 13 provides a low voltage signal through the output drive terminal NO (N), which can control the corresponding row pixel circuit not to update the pixel voltage.
  • the disclosed embodiment can realize the update of a partial picture of the display screen by controlling the selection input signal provided by the selection input terminal VCT, thereby reducing power consumption, or realize ultra-low power consumption of OLED display products such as wearable products, mobile terminals, NB (notebook computers) by partial update of the display picture.
  • the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst and an organic light emitting diode O1;
  • the gate of M1 is electrically connected to the first reset terminal NR(N), the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the gate of M3;
  • the gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;
  • the gate of M4 is electrically connected to the second scanning terminal PG(N), and the source of M4 is electrically connected to the data line D1. Then, the drain of M4 is electrically connected to the source of M3;
  • the gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;
  • the gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;
  • the gate of M7 is electrically connected to the second scanning terminal PG(N), the source of M7 is electrically connected to the initial voltage terminal I1, and the drain of M7 is electrically connected to the anode of O1.
  • the first reset terminal NR(N) may be the N-1th stage first scan terminal NG(N), but is not limited thereto.
  • M1 and M2 are n-type transistors
  • M3, M4, M5, M6 and M7 are all p-type transistors
  • M1 and M2 are IGZO TFTs with small leakage current
  • M3, M4, M5, M6 and M7 are all LTPS TFTs.
  • M1 and M2 are IGZO TFTs.
  • IGZO TFT can ensure that Cst can maintain the gate voltage of M3 for a longer time.
  • the second scanning terminal PG (N) is responsible for resetting the voltage of the anode of O1 and writing the data voltage on the data line into the source of the driving transistor
  • the first scanning terminal NG (N) is responsible for resetting Cst, extracting Vth (Vth is the threshold voltage of the driving transistor) and writing the data voltage into the gate of the driving transistor.
  • the first scanning signal provided by the first scanning terminal NG(N) and the second scanning signal provided by the second scanning terminal PG(N) may be in opposite phases to each other, but the present invention is not limited thereto.
  • the driving circuit described in at least one embodiment of the present disclosure may provide the first scanning signal to the first scanning terminal NG(N) via the output driving terminal NO(N), but the present invention is not limited thereto.
  • the display cycle may include a first display control stage t1 , a second display control stage t2 and a third display control stage t3 which are successively arranged;
  • E(N) outputs a high voltage signal
  • NR(N) provides a high voltage signal
  • PG(N) provides a high voltage signal
  • NG(N) provides a low voltage signal
  • M5 and M6 are turned off, M1 is turned on, and the potential of the gate of M3 is pulled down to the initial voltage Vinit; the initial voltage terminal I1 is used to provide the initial voltage Vinit;
  • E(N) outputs a high voltage signal
  • NR(N) provides a low voltage signal
  • PG(N) provides a low voltage signal
  • NG(N) provides a high voltage signal
  • M5 and M6 are turned off, M1 is turned off, M2 is turned on, M4 is turned on, M2 and M3 form a diode structure
  • the data voltage Vdata provided by the data line D1 charges Cst until M3 is turned off, at which time the gate voltage of M3 is Vdata+Vth, and Vth is the threshold voltage of M3
  • M7 is turned on to reset the anode voltage of O1;
  • E(N) outputs a low voltage signal
  • NR(N) provides a low voltage signal
  • PG(N) provides a high voltage signal
  • NG(N) provides a low voltage signal
  • M5 and M6 are turned on, M3 drives O1 to emit light; O1 emits light according to the voltage setting of Vdata.
  • NG(N) can control whether the data voltage Vdata (the data voltage Vdata can be the pixel voltage) is written into the gate of M3 in the second display control stage.
  • FIG. 4 is a circuit diagram of a related pixel circuit.
  • the related pixel circuit may include a first display control transistor M1, a second display control transistor M2, a driving transistor M3, a fourth display control transistor M4, a fifth display control transistor M5, a sixth display control transistor M6, a seventh display control transistor M7, a storage capacitor Cst and an organic light emitting diode O1;
  • the gate of M1 is electrically connected to the third reset terminal RST1, the source of M1 is electrically connected to the initial voltage terminal I1, and the drain of M1 is electrically connected to the drain of M3;
  • the gate of M2 is electrically connected to the first scanning terminal NG(N), the source of M2 is electrically connected to the gate of M3, and the drain of M2 is electrically connected to the drain of M3;
  • the gate of M4 is electrically connected to the second scanning terminal PG(N), the source of M4 is electrically connected to the data line D1, and the drain of M4 is electrically connected to the source of M3;
  • the gate of M5 is electrically connected to the light emitting control terminal E(N), the source of M5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of M5 is electrically connected to the source of M3;
  • the gate of M6 is electrically connected to the light emitting control terminal E(N), the source of M6 is electrically connected to the drain of M3, the drain of M6 is electrically connected to the anode of O1; the cathode of O1 is electrically connected to the low level terminal ELVSS;
  • the gate of M7 is electrically connected to the fourth reset terminal RST2 , the source of M7 is electrically connected to the initial voltage terminal I1 , and the drain of M7 is electrically connected to the anode of O1 .
  • NG(N) can control whether the data voltage Vdata on the data line D1 is written into the gate of the driving transistor M3.
  • the first scanning signal provided by NG(N) can be used to control the opening or closing of the second transistor to control whether the data voltage on the data line is written into the gate of the driving transistor, thereby controlling whether the brightness of the pixel circuit of this row is updated; when NG(N) outputs a high voltage signal, the second transistor is turned on, and the brightness of the pixel circuit of this row can be updated; when NG(N) outputs a low voltage signal, the second transistor is always turned off, and the change of the data voltage on the data line will not be written into the gate of the driving transistor, and the luminous brightness of the organic light emitting diode will not change, that is, the display brightness of the pixel circuit of the current row in the current frame remains unchanged.
  • the pixel brightness can be refreshed by controlling the opening or closing of the N-type transistor. Therefore, when you want to achieve non-refresh of some pixels, just ensure that the N-type transistor is turned off.
  • the gating circuit is used to control the writing of the gating input signal provided by the gating input terminal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the gating circuit may write the gating input signal into the first node when the potential of the N-1th level driving signal is the first voltage and the potential of the Nth level driving signal is the second voltage.
  • the first voltage may be a high voltage
  • the second voltage may be a low voltage
  • the present invention is not limited thereto.
  • the first voltage may also be a low voltage
  • the second voltage may be a high voltage
  • the gating circuit includes a first transistor; the gate of the first transistor is electrically connected to the gating control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the gating input terminal.
  • the gating circuit may include a first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the gate control terminal S0, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the gate input terminal VCT;
  • T1 is a p-type transistor.
  • the gating circuit may include a first transistor T1;
  • the gate of the first transistor T1 is electrically connected to the gate control terminal S0.
  • the source of the transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the gate input terminal VCT;
  • T1 is an n-type transistor.
  • the gating control terminal includes a first gating control terminal and a second gating control terminal;
  • the gating circuit includes a first transistor and a second transistor;
  • the gate of the first transistor is electrically connected to the first selection control terminal, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the first electrode of the second transistor;
  • the gate of the second transistor is electrically connected to the second gate control terminal, and the second electrode of the second transistor is electrically connected to the gate input terminal;
  • the first gating control terminal is an N-1th level driving signal output terminal
  • the second gating control terminal is an Nth level driving signal output terminal
  • the first transistor is an n-type transistor
  • the second transistor is a p-type transistor
  • the first gating control terminal is an N-th level driving signal output terminal
  • the second gating control terminal is an N-1-th level driving signal output terminal
  • the first transistor is a p-type transistor
  • the second transistor is an n-type transistor
  • the first gating control terminal is connected to the inverted signal of the N-1th level driving signal
  • the second gating control terminal is the output terminal of the Nth level driving signal
  • the first transistor and the second transistor are both p-type transistors
  • the first gating control terminal is an output terminal of the Nth level driving signal, and the second gating control terminal is connected to the inverted signal of the N-1th level driving signal; the first transistor and the second transistor are both p-type transistors; or,
  • the first gating control terminal is the N-1th level driving signal terminal
  • the second gating control terminal is connected to the inverted signal of the Nth level driving signal
  • the first transistor and the second transistor are both n-type transistors
  • the first gating control terminal is connected to the inverted signal of the Nth level driving signal
  • the second gating control terminal is the N-1th level driving signal terminal
  • the first transistor and the second transistor are both n-type transistors.
  • the gating circuit may include a first transistor T1 and a second transistor T2 ;
  • the gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gate input terminal VCT;
  • T1 is an n-type transistor and T2 is a p-type transistor.
  • the gating circuit may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the Nth stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the source of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the gate input terminal VCT;
  • T1 is a p-type transistor and T2 is an n-type transistor.
  • the gating circuit may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the first inverted driving signal terminal NGI1, the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is inverted with the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1);
  • the gate of the second transistor T2 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gate input terminal VCT;
  • T1 is a p-type transistor
  • T2 is a p-type transistor
  • the gating circuit may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the N-th stage driving signal output terminal NS(N), the drain of the first transistor T1 is electrically connected to the first node N1, and the source of the first transistor T1 is electrically connected to the drain of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the first inverted driving signal terminal NGI1, and the source of the second transistor T2 is electrically connected to the selection input terminal VCT; the first inverted driving signal provided by the first inverted driving signal terminal NGI1 is electrically connected to the first inverted driving signal provided by the N-1 stage driving signal output terminal NS(N-1) The N-1th level driving signal provided is inverted;
  • T1 is a p-type transistor
  • T2 is a p-type transistor
  • the gating circuit may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the second inverted driving signal terminal NGI2, and the drain of the second transistor T2 is electrically connected to the selection input terminal VCT; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-th level driving signal provided by the N-th level driving signal output terminal NS(N);
  • T1 is an n-type transistor
  • T2 is an n-type transistor
  • the gating circuit may include a first transistor T1 and a second transistor T2 ;
  • the gate of the first transistor T1 is electrically connected to the second inverted driving signal terminal NGI2, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the source of the second transistor T2; the second inverted driving signal provided by the second inverted driving signal terminal NGI2 is inverted with the N-th level driving signal provided by the N-th level driving signal output terminal NS(N);
  • the gate of the second transistor T2 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), and the drain of the second transistor T2 is electrically connected to the gate input terminal VCT;
  • T1 is an n-type transistor
  • T2 is an n-type transistor
  • the N-1th level driving signal provided by the N-1th level driving signal output terminal NS(N-1) can be inverted by the first inverting circuit to obtain the first inverted driving signal provided by the first inverted driving signal terminal NGI1;
  • the first inverting circuit includes a first inverting control transistor T01 and a second inverting control transistor T02;
  • T01 is a p-type transistor
  • T02 is an n-type transistor
  • the N-th level driving signal provided by the N-th level driving signal output terminal NS(N) can be inverted by the second inverting circuit to obtain a second inverted driving signal provided by the second inverted driving signal terminal NGI2;
  • the second inverting circuit includes a third inverting control transistor T03 and a fourth inverting control transistor T04;
  • T03 is a p-type transistor
  • T04 is an n-type transistor
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first initialization circuit
  • the first initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the first node respectively, and is used to control the connection between the first node and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the driving circuit may further include a first initialization circuit, and the first initialization circuit controls the connection between the first node and the first voltage terminal under the control of an initial control signal.
  • the first voltage terminal may be a high voltage terminal.
  • the driving circuit described in at least one embodiment of the present disclosure further includes a first voltage maintaining circuit
  • the first end of the first voltage maintaining circuit is electrically connected to the first node, the second end of the first voltage maintaining circuit is electrically connected to a DC voltage terminal second node, and the first voltage maintaining circuit is used to maintain the potential of the first node.
  • the driving circuit may further include a first voltage maintaining circuit, and the first voltage maintaining circuit maintains the potential of the first node.
  • the driving circuit may further include a first initialization circuit 21 ;
  • the first initialization circuit 21 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the first node N1 respectively, and is used to control the connection between the first node N1 and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • NCX provides a valid voltage signal
  • the first initialization circuit 21 controls the first node N1 to be connected to the first voltage terminal V1.
  • the driving circuit may further include a first voltage maintaining circuit 22 ;
  • a first end of the first voltage maintaining circuit 22 is electrically connected to the first node N1 , a second end of the first voltage maintaining circuit 22 is electrically connected to the first voltage terminal V1 , and the first voltage maintaining circuit 22 is used to maintain the potential of the first node N1 .
  • the driving circuit further includes a second voltage maintaining circuit, and the first node is electrically connected to the second end of the output control circuit through the second voltage maintaining circuit;
  • the second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit
  • the input terminal of the first inverter is electrically connected to the first node, the output terminal of the first inverter is electrically connected to the second node, the input terminal of the second inverter is electrically connected to the second node, and the output terminal of the second inverter is electrically connected to a third node and the second terminal of the output control circuit;
  • the first inverter is used to invert the potential of the first node and output the inverted potential of the first node through the output terminal of the first inverter
  • the second inverter is used to invert the potential of its input terminal and output the inverted potential through the output terminal of the second inverter
  • the sustain control circuit is electrically connected to the sustain control terminal, the third node and the first node respectively, and is used to control the connection or disconnection between the third node and the first node under the control of a sustain control signal provided by the sustain control terminal.
  • the driving circuit may further include a second voltage maintaining circuit
  • the first node may be electrically connected to the second end of the output control circuit through the second voltage maintaining circuit
  • the second voltage maintaining circuit may include a first inverter, a second inverter and a maintaining control circuit; the first inverter inverts the potential of the first node, and the second inverter inverts the potential of its input end; the maintaining control circuit controls the connection or disconnection between the third node and the first node under the control of a maintaining control signal provided by the maintaining control end;
  • the sustain control circuit may control the third node to be disconnected from the first node when the gating circuit controls the gating input signal to be written into the first node.
  • the first inverter and the second inverter included in the second voltage maintaining circuit can control the connection between the third node and the high voltage end when the potential of the first node is a high voltage, so that the potential of the third node can be higher than the potential of the first node, and can control the connection between the third node and the low voltage end when the potential of the first node is a low voltage, so that the potential of the third node can be lower than the potential of the first node, so that the third node can better control the transistor whose gate is electrically connected to the third node included in the output control circuit.
  • the driving circuit may further include a second voltage maintaining circuit; the maintaining control terminal includes an N-1 The first stage driving signal output terminal NS(N-1) and the first clock signal terminal GCK;
  • the first node N1 is electrically connected to the second end of the output control circuit 12 through the second voltage maintaining circuit;
  • the second voltage maintaining circuit includes a first inverter F1, a second inverter F2 and a maintaining control circuit W1;
  • the input end of the first inverter F1 is electrically connected to the first node N1, and the output end of the first inverter F1 is electrically connected to the second node N2;
  • the input end of the second inverter F2 is electrically connected to the second node N2, and the output end of the second inverter F2 is electrically connected to the third node N3 and the second end of the output control circuit 12;
  • the first inverter F1 is used to invert the potential of the first node N1, and output the inverted potential of the first node through the output end of the first inverter F1;
  • the second inverter F2 is used to invert the potential at its input terminal and output the inverted potential through the output terminal of the second inverter F2;
  • the maintenance control circuit W1 is electrically connected to the N-1th level drive signal output terminal NS(N-1), the first clock signal terminal GCK, the third node N3 and the first node N1, respectively, and is used to control the connection or disconnection between the third node N3 and the first node N1 under the control of the N-1th level drive signal provided by the N-1th level drive signal output terminal NS(N-1), and to control the connection or disconnection between the third node N3 and the first node N1 under the control of the first clock signal provided by the first clock signal terminal GCK.
  • the N-1th stage driving signal output terminal may be replaced by a second clock signal terminal, but the present invention is not limited thereto.
  • the maintenance control end includes a first maintenance control end and a second maintenance control end;
  • the sustain control circuit includes a third transistor and a fourth transistor
  • the gate of the third transistor is electrically connected to the first sustain control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the third node;
  • the gate of the fourth transistor is electrically connected to the second sustain control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first node;
  • the third transistor is a p-type transistor, and the fourth transistor is an n-type transistor;
  • the first sustain control terminal is the N-1th level driving signal terminal, and the second sustain control terminal is the first clock signal terminal; or,
  • the first sustain control terminal is a second clock signal terminal
  • the second sustain control terminal is a first clock signal terminal
  • the first inverter includes a fifth transistor and a sixth transistor
  • the second inverter includes a seventh transistor and an eighth transistor
  • the gate of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the first voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node;
  • the gate of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the second voltage terminal;
  • the fifth transistor is a p-type transistor, and the sixth transistor is an n-type transistor;
  • the gate of the seventh transistor is electrically connected to the second node, the first electrode of the seventh transistor is electrically connected to the first voltage terminal, and the second electrode of the seventh transistor is electrically connected to the third node;
  • the gate of the eighth transistor is electrically connected to the second node, the first electrode of the eighth transistor is electrically connected to the third node, and the second electrode of the eighth transistor is electrically connected to the second voltage terminal;
  • the seventh transistor is a p-type transistor
  • the eighth transistor is an n-type transistor.
  • the first initialization circuit includes a ninth transistor, and the first voltage maintaining circuit includes a first capacitor;
  • the gate of the ninth transistor is electrically connected to the initial control terminal, the first electrode of the ninth transistor is electrically connected to the first voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first node;
  • the first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the DC voltage end or the second node.
  • the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;
  • the gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;
  • the gate of the eleventh transistor is electrically connected to the first node, and the A first electrode is electrically connected to the first voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the fourth node;
  • the gate of the twelfth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;
  • the gate of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;
  • the tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.
  • the output control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor;
  • the gate of the tenth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the tenth transistor is electrically connected to the first voltage terminal, and the second electrode of the tenth transistor is electrically connected to the fourth node;
  • the gate of the eleventh transistor is electrically connected to the third node, the first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth node;
  • the gate of the twelfth transistor is electrically connected to the Nth stage driving signal output terminal, the first electrode of the twelfth transistor is electrically connected to the fourth node, and the second electrode of the twelfth transistor is electrically connected to the fifth node;
  • the gate of the thirteenth transistor is electrically connected to the third node, the first electrode of the thirteenth transistor is electrically connected to the fifth node, and the second electrode of the thirteenth transistor is electrically connected to the second voltage terminal;
  • the tenth transistor and the eleventh transistor are p-type transistors, and the twelfth transistor and the thirteenth transistor are n-type transistors.
  • the output circuit includes a fourteenth transistor and a fifteenth transistor
  • the gate of the fourteenth transistor is electrically connected to the fourth node, and the first The first electrode of the fourteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourteenth transistor is electrically connected to the output driving terminal;
  • a gate of the fifteenth transistor is electrically connected to the fourth node, a first electrode of the fifteenth transistor is electrically connected to the output driving end, and a second electrode of the fifteenth transistor is electrically connected to the second voltage end.
  • the driving signal generating circuit may include a first control circuit, a second control circuit, a third inverter, and a second initialization circuit;
  • the first control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the N-1th level drive signal output terminal and the sixth node respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal under the control of the first clock signal provided by the first clock signal terminal and the second clock signal provided by the second clock signal terminal, and obtain and output the inverted signal through the sixth node;
  • the second control circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the Nth level driving signal output terminal and the sixth node respectively, and is used to invert the Nth level driving signal provided by the Nth level driving signal output terminal under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node;
  • the third inverter is electrically connected to the sixth node and the Nth stage drive signal output terminal respectively, and is used to invert the potential of the sixth node and output the inverted signal through the Nth stage drive signal output terminal;
  • the second initialization circuit is electrically connected to the initial control terminal, the first voltage terminal and the Nth level drive signal output terminal respectively, and is used to control the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal provided by the initial control terminal.
  • the drive signal generating circuit may include a first control circuit, a second control circuit, a third inverter and a second initialization circuit; the first control circuit shifts and inverts the N-1th drive signal under the control of the first clock signal and the second clock signal, and outputs the inverted signal through the sixth node; the second control circuit inverts the Nth level drive signal under the control of the first clock signal and the second clock signal, and outputs the inverted signal through the sixth node; the third inverter inverts the potential of the sixth node, and outputs the inverted signal through the Nth level drive signal output terminal; the second initialization circuit controls the connection between the Nth level drive signal output terminal and the first voltage terminal under the control of the initial control signal.
  • the driving signal generating circuit may include a first control circuit 31 , a second control circuit 32 , a third inverter F3 , and a second initialization circuit 30 ;
  • the first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th level drive signal output terminal NS(N-1) and the sixth node N6 respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, and obtain and output the inverted signal through the sixth node N6;
  • the second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-th level driving signal output terminal NS(N) and the sixth node N6 respectively, and is used for inverting the N-th level driving signal provided by the N-th level driving signal output terminal NS(N) under the control of the first clock signal and the second clock signal, and obtaining and outputting the inverted signal through the sixth node N6;
  • the third inverter F3 is electrically connected to the sixth node N6 and the N-th stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the sixth node N6 and output the inverted signal through the N-th stage drive signal output terminal NS(N);
  • the second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth level drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • the driving signal generating circuit may include a first control circuit 31 , a second control circuit 32 , a third inverter F3 and a second initialization circuit 30 ;
  • the first control circuit 31 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-1th level drive signal output terminal NS(N-1) and the sixth node N6, respectively, and is used to shift and invert the N-1th drive signal provided by the N-1th level drive signal output terminal NS(N-1) under the control of the first clock signal provided by the first clock signal terminal GCK and the second clock signal provided by the second clock signal terminal GCB, and obtain and output the inverted N-1th drive signal through the sixth node N6. signal;
  • the second control circuit 32 is electrically connected to the first clock signal terminal GCK, the second clock signal terminal GCB, the N-th level driving signal output terminal NS(N) and the sixth node N6 respectively, and is used to invert the N-th level driving signal provided by the N-th level driving signal output terminal NS(N) under the control of the first clock signal and the second clock signal, and obtain and output the inverted signal through the sixth node N6;
  • the third inverter F3 is electrically connected to the sixth node N6 and the N-th stage drive signal output terminal NS(N) respectively, and is used to invert the potential of the sixth node N6 and output the inverted signal through the N-th stage drive signal output terminal NS(N);
  • the second initialization circuit 30 is electrically connected to the initial control terminal NCX, the first voltage terminal V1 and the Nth level drive signal output terminal NS(N), respectively, and is used to control the connection between the Nth level drive signal output terminal NS(N) and the first voltage terminal V1 under the control of the initial control signal provided by the initial control terminal NCX.
  • the first control circuit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor;
  • the gate of the sixteenth transistor is electrically connected to the second clock signal terminal, the first electrode of the sixteenth transistor is electrically connected to the first voltage terminal, and the second electrode of the sixteenth transistor is electrically connected to the first electrode of the seventeenth transistor;
  • the gate of the seventeenth transistor is electrically connected to the N-1th stage driving signal output terminal, and the second electrode of the seventeenth transistor is electrically connected to the sixth node;
  • the gate of the eighteenth transistor is electrically connected to the N-1th stage driving signal output terminal, the first electrode of the eighteenth transistor is electrically connected to the sixth node, and the second electrode of the eighteenth transistor is electrically connected to the first electrode of the nineteenth transistor;
  • the gate of the nineteenth transistor is electrically connected to the first clock signal terminal, and the second electrode of the nineteenth transistor is electrically connected to the second voltage terminal;
  • the sixteenth transistor and the seventeenth transistor are p-type transistors, and the eighteenth transistor and the nineteenth transistor are n-type transistors.
  • the second control circuit includes a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor;
  • a gate of the 20th transistor is electrically connected to the first clock signal terminal, a first electrode of the 20th transistor is electrically connected to the first voltage terminal, and a second electrode of the 20th transistor is electrically connected to a first electrode of the 21st transistor;
  • a gate of the twenty-first transistor is electrically connected to the Nth stage driving signal output terminal, and a second electrode of the twenty-first transistor is electrically connected to the sixth node;
  • a gate of the 22nd transistor is electrically connected to the Nth stage driving signal output terminal, a first electrode of the 22nd transistor is electrically connected to the sixth node, and a second electrode of the 22nd transistor is electrically connected to a first electrode of the 23rd transistor;
  • a gate of the twenty-third transistor is electrically connected to the second clock signal terminal, and a second electrode of the twenty-third transistor is electrically connected to the second voltage terminal;
  • the 20th transistor and the 21st transistor are p-type transistors, and the 22nd transistor and the 23rd transistor are n-type transistors.
  • the third inverter includes a twenty-fourth transistor and a twenty-fifth transistor; the second initialization circuit includes a twenty-sixth transistor;
  • a gate of the twenty-fourth transistor is electrically connected to the sixth node, a first electrode of the twenty-fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-fourth transistor is electrically connected to a first electrode of the twenty-fifth transistor;
  • a gate of the twenty-fifth transistor is electrically connected to the sixth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second voltage terminal;
  • the twenty-fourth transistor is a p-type transistor, and the twenty-fifth transistor is an n-type transistor;
  • a gate of the twenty-sixth transistor is electrically connected to the initial control terminal, a first electrode of the twenty-sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the twenty-sixth transistor is electrically connected to the Nth stage driving signal output terminal.
  • the first voltage terminal may be a high voltage terminal
  • the second voltage terminal may be a low voltage terminal, but is not limited thereto.
  • the difference between at least one embodiment of the driving circuit shown in FIG. 20 and at least one embodiment of the driving circuit shown in FIG. 18 is that at least one embodiment of the driving circuit shown in FIG. 20 does not include a first voltage maintaining circuit.
  • At least one embodiment of the driving circuit shown in FIG. 21 is different from at least one embodiment of the driving circuit shown in FIG. 19 The difference between the embodiments is that at least one embodiment of the driving circuit shown in FIG21 further includes a first voltage maintaining circuit 22;
  • a first end of the first voltage maintaining circuit 22 is electrically connected to the first node N1 , a second end of the first voltage maintaining circuit 22 is electrically connected to the first voltage terminal V1 , and the first voltage maintaining circuit 22 is used to maintain the potential of the first node N1 .
  • the gating circuit may include a first transistor T1 and a second transistor T2;
  • the gate of the first transistor T1 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the drain of the second transistor T2;
  • the gate of the second transistor T2 is electrically connected to the Nth stage driving signal output terminal NS(N), and the source of the second transistor T2 is electrically connected to the gate input terminal VCT;
  • T1 is an n-type transistor and T2 is a p-type transistor;
  • the first initialization circuit includes a ninth transistor T9;
  • the gate of the ninth transistor T9 is electrically connected to the initial control terminal NCX, the source of the ninth transistor T9 is electrically connected to the high voltage terminal VGH, and the drain of the ninth transistor T9 is electrically connected to the first node N1;
  • the output control circuit includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13;
  • the gate of the tenth transistor T10 is electrically connected to the Nth stage driving signal output terminal NS(N), the source of the tenth transistor T10 is electrically connected to the high voltage terminal VGH, and the source of the tenth transistor T10 is electrically connected to the fourth node N4;
  • the gate of the eleventh transistor T11 is electrically connected to the first node N1, the source of the eleventh transistor T11 is electrically connected to the high voltage terminal VGH, and the drain of the eleventh transistor T11 is electrically connected to the fourth node N4;
  • the gate of the twelfth transistor T12 is electrically connected to the N-th stage driving signal output terminal NS(N), the source of the twelfth transistor T12 is electrically connected to the fourth node N4, and the drain of the twelfth transistor T12 is electrically connected to the fifth node N5;
  • the gate of the thirteenth transistor T13 is electrically connected to the first node N1.
  • the source of the transistor T13 is electrically connected to the fifth node N5, and the drain of the thirteenth transistor T13 is electrically connected to the low voltage terminal VGL;
  • the tenth transistor T10 and the eleventh transistor T11 are p-type transistors, and the twelfth transistor T12 and the thirteenth transistor T13 are n-type transistors;
  • the output circuit includes a fourteenth transistor T14 and a fifteenth transistor T15;
  • the gate of the fourteenth transistor T14 is electrically connected to the fourth node N4, the source of the fourteenth transistor T14 is electrically connected to the high voltage terminal VGH, and the drain of the fourteenth transistor T14 is electrically connected to the output driving terminal NO (N);
  • the gate of the fifteenth transistor T15 is electrically connected to the fourth node N4, the source of the fifteenth transistor T15 is electrically connected to the output driving terminal NO(N), and the drain of the fifteenth transistor T15 is electrically connected to the low voltage terminal VGL;
  • the first control circuit includes a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19;
  • the gate of the sixteenth transistor T16 is electrically connected to the second clock signal terminal GCB, the source of the sixteenth transistor T16 is electrically connected to the high voltage terminal VGH, and the drain of the sixteenth transistor T16 is electrically connected to the source of the seventeenth transistor T17;
  • the gate of the nineteenth transistor T19 is electrically connected to the first clock signal terminal GCK, and the source of the nineteenth transistor T19 is electrically connected to the low voltage terminal VGL;
  • the sixteenth transistor T16 and the seventeenth transistor T17 are p-type transistors, and the eighteenth transistor T18 and the nineteenth transistor T19 are n-type transistors;
  • the second control circuit includes a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22 and a twenty-third transistor T23;
  • the gate of the twentieth transistor T20 is electrically connected to the first clock signal terminal GCK
  • the source of the twentieth transistor T20 is electrically connected to the high voltage terminal VGH
  • the twentieth transistor T20 is electrically connected to the first clock signal terminal GCK.
  • the drain of the transistor T21 is electrically connected to the source of the transistor T21;
  • a gate of the twenty-first transistor T21 is electrically connected to the Nth stage driving signal output terminal NS(N), and a drain of the twenty-first transistor T21 is electrically connected to the sixth node N6;
  • a gate of the 22nd transistor T22 is electrically connected to the Nth stage driving signal output terminal NS(N), a source of the 22nd transistor T22 is electrically connected to the sixth node N6, and a source of the 22nd transistor T22 is electrically connected to a drain of the 23rd transistor T23;
  • a gate of the twenty-third transistor T23 is electrically connected to the second clock signal terminal GCB, and a drain of the twenty-third transistor T23 is electrically connected to the low voltage terminal VGL;
  • the 20th transistor T20 and the 21st transistor T21 are p-type transistors, and the 22nd transistor T22 and the 23rd transistor T23 are n-type transistors;
  • the third inverter includes a twenty-fourth transistor T24 and a twenty-fifth transistor T25; the second initialization circuit includes a twenty-sixth transistor T26;
  • a gate of the twenty-fourth transistor T24 is electrically connected to the sixth node N6, a source of the twenty-fourth transistor T24 is electrically connected to the high voltage terminal VGH, and a drain of the twenty-fourth transistor T24 is electrically connected to a source of the twenty-fifth transistor T25;
  • a gate of the twenty-fifth transistor T25 is electrically connected to the sixth node N6, and a drain of the twenty-fifth transistor T25 is electrically connected to the low voltage terminal VGL;
  • the twenty-fourth transistor T24 is a p-type transistor, and the twenty-fifth transistor T25 is an n-type transistor;
  • the gate of the 26th transistor T26 is electrically connected to the initial control terminal NCX, the source of the 26th transistor T26 is electrically connected to the high voltage terminal VGH, and the second electrode of the 26th transistor is electrically connected to the Nth stage driving signal output terminal NS(N);
  • the structure of the drive signal generating circuit is not limited to that shown in FIG. 22 .
  • the drive signal generating circuit may be, for example, a 16T3C circuit, a 13T3C circuit, a 12T3C circuit, a 10T3C circuit, etc., but is not limited thereto.
  • At least one embodiment of the driving circuit described in FIG. 22 of the present disclosure is in operation.
  • NS(N-1) provides a high voltage signal, closes T17, opens T18, the potential of N6 is low voltage, closes T25, and opens T24.
  • NS(N) and NS(N-1) both provide high voltage signals to realize the shift register from NS(N-1) to NS(N);
  • NS(N-1) provides a low voltage signal, turns on T17, turns off T18, the potential of N6 is a high voltage, turns on T25, and turns off T24.
  • NS(N) and NS(N-1) both provide low voltage signals to realize the shift register from NS(N-1) to NS(N).
  • At least one embodiment of the driving circuit described in FIG. 22 of the present disclosure is in operation.
  • T1 When NS(N-1) provides a high voltage signal, T1 is turned on, and when NS(N) provides a low voltage signal, T2 is turned on.
  • VCT By simultaneously selecting the two signals, VCT within a high-low frequency switching cycle H can be obtained.
  • the state of the selection input signal provided is written into the first node N1, and then T1 and T2 will not be turned on at the same time at other times to prevent the potential of N1 from being affected by the potential change of the selection input signal provided by VCT.
  • T10, T11, T12 and T13 form a NAND gate, the input signals of which are respectively the signal provided by NS(N) and the potential of N1, and the output end of the NAND gate is electrically connected to the fourth node N4.
  • T24 and T25 form a third inverter, the input end of which is electrically connected to N4, and the output end of the third inverter is electrically connected to NO(N);
  • VCT provides a high voltage signal when T1 and T2 are turned on, N1 will be written with a high voltage, and the gate state of the NAND gate can ensure that NS(N) is normally passed to NO(N);
  • VCT provides a low voltage signal when T1 and T2 are turned on
  • N1 will be written with a low voltage, and the NAND gate is in a cut-off state, ensuring that NO(N) provides a low voltage signal, thereby achieving low-level maintenance of NO(N).
  • NCX when the display starts (that is, when the display device is turned on), in the power-on stage before the first stage, NCX outputs a low voltage signal, T9 is turned on to control the potential of N1 to be a high voltage, and T26 is turned on so that NS (N) provides a high voltage signal; at this time, T12 and T13 are both turned on, the potential of N4 is a low voltage, T14 is turned on, T15 is turned off, and NO (N) outputs a high voltage signal, so that the second display control transistor M2 included in all pixel circuits in the effective display area can be turned on, and the residual charge in the storage capacitor Cst is cleared, thereby improving the screen flickering problem when the screen is turned on;
  • T1 and T2 are turned on.
  • N1 When VCT provides a low voltage signal, the potential of N1 is a low voltage signal, and C1 maintains the potential of N1; T11 is turned on, T10 is turned on, the potential of N4 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;
  • N1 When VCT provides a high voltage signal, the potential of N1 is a high voltage signal, C1 maintains the potential of N1, T11 is turned off, T10 is turned on, the potential of N4 is a high voltage, T15 is turned on, and NO (N) outputs a low voltage signal;
  • NS(N) outputs a high voltage signal.
  • N1 When the potential of N1 is high, T10 is turned off, T11 is turned off, T12 and T13 are turned on, and N4 The potential is low voltage, T14 is turned on, and NO (N) outputs a high voltage signal;
  • NS(N) After the Nth stage of driving signal supply, NS(N) outputs a low voltage signal.
  • N1 When the potential of N1 is a low voltage signal, T10 is turned on, T11 is turned on, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal;
  • N1 When the potential of N1 is a high voltage signal, T10 is turned on, T11 is turned off, the potential of N4 is a high voltage, and NO(N) outputs a low voltage signal.
  • the node labeled N7 is the seventh node, and the seventh node N7 is electrically connected to the drain of T1 .
  • the seventh node N7 is electrically connected to the drain of T1 .
  • the driving circuit described in at least one embodiment of the present disclosure further includes a second voltage maintaining circuit; the first node N1 is electrically connected to the gate of T11 through the second voltage maintaining circuit;
  • the second voltage maintaining circuit includes a first inverter, a second inverter and a maintaining control circuit
  • the gate of the third transistor T3 is electrically connected to the N-1th stage driving signal output terminal NS(N-1), the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3;
  • the gate of the fourth transistor T4 is electrically connected to the first clock signal terminal GCK, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the first node N1;
  • the first inverter includes a fifth transistor T5 and a sixth transistor T6, and the second inverter includes a seventh transistor T7 and an eighth transistor T8;
  • the gate of the fifth transistor T5 is electrically connected to the first node N1, the source of the fifth transistor T5 is electrically connected to the high voltage terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the second node N2;
  • the gate of the sixth transistor T6 is electrically connected to the first node N1, the source of the sixth transistor T6 is electrically connected to the second node N2, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VGL electrical connection;
  • the gate of the seventh transistor T7 is electrically connected to the second node N2, the source of the seventh transistor T7 is electrically connected to the high voltage terminal VGH, and the drain of the seventh transistor T7 is electrically connected to the third node N3;
  • the gate of the eighth transistor T8 is electrically connected to the second node N2, the source of the eighth transistor T8 is electrically connected to the third node N3, and the drain of the eighth transistor T8 is electrically connected to the low voltage terminal VGL;
  • the third node N3 is electrically connected to the gate of T11 and the gate of T13 respectively.
  • the third transistor T3 is a p-type transistor
  • the fourth transistor T4 is an n-type transistor
  • the fifth transistor T5 is a p-type transistor
  • the sixth transistor T6 is an n-type transistor
  • the seventh transistor T7 is a p-type transistor
  • the eighth transistor T8 is an n-type transistor.
  • the absolute value of the potential of N1 will be lower, and the absolute value of the potential of N1 can be controlled to increase by the first inverter and the second inverter, so as to better control the corresponding transistors in the output circuit to be turned on or off, and maintain the control circuit control when T1 and T2 are turned on, and control the disconnection between N1 and N3 so as not to affect the writing of the potential of N1.
  • FIG. 24 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 23 of the present disclosure.
  • At least one embodiment of the driving circuit shown in FIG25 further includes a first capacitor C1;
  • C1 is used to stabilize the potential of N1.
  • the driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:
  • the driving signal generating circuit performs a shift operation on the N-1th level driving signal to obtain and output the Nth level driving signal through the Nth level driving signal output terminal;
  • the gating circuit controls, under the control of the gating control signal, to write the gating input signal provided by the gating input terminal into the first node;
  • the output control circuit performs a NAND operation on the Nth stage driving signal and the potential of the second end of the output control circuit to obtain a first output signal
  • the driving module described in the embodiment of the present disclosure includes multiple stages of the above-mentioned driving circuits
  • the Nth stage driving circuit is electrically connected to the driving signal output terminal included in the N-1th stage driving circuit; N is a positive integer.
  • the first-stage driving circuit is labeled S1
  • the second-stage driving circuit is labeled S2
  • the third-stage driving circuit is labeled S3
  • the fourth-stage driving circuit is labeled S4
  • the fifth-stage driving circuit is labeled S5
  • the sixth-stage driving circuit is labeled S6
  • the seventh-stage driving circuit is labeled S7
  • the eighth-stage driving circuit is labeled S8
  • the ninth-stage driving circuit is labeled S9
  • the tenth-stage driving circuit is labeled S10
  • the eleventh-stage driving circuit is labeled S11
  • the twelfth-stage driving circuit is labeled S12;
  • the terminal labeled NS(1) is the drive signal output terminal of S1, and the terminal labeled NO(1) is the output drive terminal of S1;
  • the terminal labeled NS(2) is the drive signal output terminal of S2, and the terminal labeled NO(2) is the output drive terminal of S2; S2 is electrically connected to NS(1);
  • the terminal labeled NS (4) is the drive signal output terminal of S4, and the terminal labeled NO (4) is the output drive terminal of S4; S4 is electrically connected to NS (3);
  • the terminal labeled NS (5) is the drive signal output terminal of S5, and the terminal labeled NO (5) is the output drive terminal of S5; S5 is electrically connected to NS (4);
  • the terminal labeled NS (6) is the drive signal output terminal of S6, and the terminal labeled NO (6) is the output drive terminal of S6; S6 is electrically connected to NS (5);
  • the terminal labeled NS (7) is the drive signal output terminal of S7, and the terminal labeled NO (7) is the output drive terminal of S7; S7 is electrically connected to NS (6);
  • the terminal labeled NS (8) is the drive signal output terminal of S8, and the terminal labeled NO (8) is the output drive terminal of S8; S8 is electrically connected to NS (7);
  • the terminal labeled NS (9) is the drive signal output terminal of S9, and the terminal labeled NO (9) is the output drive terminal of S9; S9 is electrically connected to NS (8);
  • the terminal labeled NS (10) is the drive signal output terminal of S10, and the terminal labeled NO (10) is the output drive terminal of S10; S10 is electrically connected to NS (9);
  • the terminal labeled NS (11) is the drive signal output terminal of S11, and the terminal labeled NO (11) is the output drive terminal of S11; S11 is electrically connected to NS (10);
  • the terminal labeled NS (12) is the drive signal output terminal of S12, and the terminal labeled NO (12) is the output drive terminal of S12; S12 is electrically connected to NS (11);
  • S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the selection input terminal VCT;
  • S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the first clock signal terminal GCK;
  • S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 are all electrically connected to the second clock signal terminal GCB.
  • FIG. 27 is a timing diagram of the operation of at least one embodiment of the driving module shown in FIG. 26 .
  • At least one embodiment of the driving module shown in FIG. 26 of the present disclosure is in operation, when NS(N-1) outputs a high voltage signal and NS(N) outputs a low voltage signal, if VCT outputs a low voltage signal, then when NS(N) outputs a high voltage signal, NO(N) outputs a low voltage signal;
  • the display device described in the embodiment of the present disclosure includes the above-mentioned driving module.

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Abstract

一种驱动电路、驱动方法、驱动模组和显示装置。驱动电路包括驱动信号生成电路（10）、选通电路（11）、输出控制电路（12）和输出电路（13）；驱动信号生成电路（10）用于对第N-1级驱动信号进行移位操作，得到第N级驱动信号；选通电路（11）在选通控制信号的控制下，控制选通输入信号写入第一节点（N1）；输出控制电路（12）对第N级驱动信号和输出控制电路（12）的第二端的电位进行与非操作，得到第一输出信号；输出电路（13）用于对第一输出信号进行反相，得到并通过输出驱动端（NO(N)）提供输出驱动信号；N为正整数。通过控制选通输入端（VCT）提供的选通输入信号，实现显示屏幕局部画面的更新，从而降低功耗。

Description

驱动电路、驱动方法、驱动模组和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种驱动电路、驱动方法、驱动模组和显示装置。
背景技术
在相关技术中，在OLED(有机发光二极管)显示器更新画面时，需要在一帧时间内，对所有行像素电路进行像素电压的初始化和写入。而在某些特殊画面下(如息屏AOD显示画面(息屏AOD显示画面为在不点亮整个手机屏幕的情况下，控制屏幕局部点亮的画面)、静态画面或较少更新的画面)，整屏绝大部分像素电路不需要更新像素电压，即绝大部分像素电路可以通过低漏电的LTPO(低温多晶氧化物)TFT(薄膜晶体管)维持在原有的显示亮度，对这些像素电路的反复刷写造成了功耗的浪费。
发明内容
在一个方面中，本公开实施例提供一种驱动电路，包括驱动信号生成电路、选通电路、输出控制电路和输出电路；
所述驱动信号生成电路分别与第N-1级驱动信号输出端和第N级驱动信号输出端电连接，用于对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
所述选通电路分别与第一节点、选通输入端和选通控制端电连接，用于在所述选通控制端提供的选通控制信号的控制下，控制将所述选通输入端提供的选通输入信号写入所述第一节点；
所述输出控制电路的第一端与所述第N级驱动信号输出端电连接，所述输出控制电路的第二端与所述第一节点电连接，用于对所述第N级驱动信号和所述输出控制电路的第二端的电位进行与非操作，得到第一输出信号；
所述输出电路用于对所述第一输出信号进行反相，得到并通过输出驱动端提供输出驱动信号；
N为正整数。
可选的，所述选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述选通输入端提供的选通输入信号写入所述第一节点。
可选的，所述选通电路包括第一晶体管；所述第一晶体管的栅极与所述选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述选通输入端电连接。
可选的，所述选通控制端包括第一选通控制端和第二选通控制端；所述选通电路包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与第一选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与第二选通控制端电连接，所述第二晶体管的第二极与所述选通输入端电连接；
所述第一选通控制端为第N-1级驱动信号输出端，所述第二选通控制端为第N级驱动信号输出端，第一晶体管为n型晶体管，第二晶体管为p型晶体管；或者，
所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端为第N-1级驱动信号输出端，第一晶体管为p型晶体管，第二晶体管为n型晶体管；或者，
所述第一选通控制端接入第N-1级驱动信号的反相信号，所述第二选通控制端为第N级驱动信号输出端，所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端接入第N-1级驱动信号的反相信号；所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
所述第一选通控制端为第N-1级驱动信号端，所述第二选通控制端接入第N级驱动信号的反相信号，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，
所述第一选通控制端接入第N级驱动信号的反相信号，所述第二选通控制端为第N-1级驱动信号端，所述第一晶体管和所述第二晶体管都为n型晶体管。
可选的，本公开至少一实施例所述的驱动电路还包括第一初始化电路；
所述第一初始化电路分别与初始控制端、第一电压端和第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第一节点与所述第一电压端之间连通。
可选的，本公开至少一实施例所述的驱动电路还包括第一电压维持电路；
所述第一电压维持电路的第一端与所述第一节点电连接，所述第一电压维持电路的第二端与直流电压端或第二节点电连接，所述第一电压维持电路用于维持第一节点的电位。
可选的，本公开至少一实施例所述的驱动电路还包括第二电压维持电路，所述第一节点通过所述第二电压维持电路与所述输出控制电路的第二端电连接；
所述第二电压维持电路包括第一反相器、第二反相器和维持控制电路；
所述第一反相器的输入端与所述第一节点电连接，所述第一反相器的输出端与第二节点电连接，所述第二反相器的输入端与所述第二节点电连接，所述第二反相器的输出端与第三节点和所述输出控制电路的第二端电连接；
所述第一反相器用于对所述第一节点的电位进行反相，并通过第一反相器的输出端输出反相后的第一节点的电位，所述第二反相器用于对其输入端的电位进行反相，并通过所述第二反相器的输出端输出反相后的电位；
所述维持控制电路分别与维持控制端、所述第三节点和所述第一节点电连接，用于在所述维持控制端提供的维持控制信号的控制下，控制所述第三节点与所述第一节点之间连通或断开。
可选的，所述维持控制端包括第一维持控制端和第二维持控制端；
所述维持控制电路包括第三晶体管和第四晶体管；
所述第三晶体管的栅极与第一维持控制端电连接，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与所述第三节点电连接；
所述第四晶体管的栅极与第二维持控制端电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第一节点电连接；
所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管；
所述第一维持控制端为第N-1级驱动信号端，所述第二维持控制端为第一时钟信号端；或者，
所述第一维持控制端为第二时钟信号端，所述第二维持控制端为第一时钟信号端。
可选的，所述第一反相器包括第五晶体管和第六晶体管，所述第二反相器包括第七晶体管和第八晶体管；
所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与第一电压端电连接，所述第五晶体管的第二极与第二节点电连接；
所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与所述第二节点电连接，所述第六晶体管的第二极与第二电压端电连接；
所述第五晶体管为p型晶体管，所述第六晶体管为n型晶体管；
所述第七晶体管的栅极与所述第二节点电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与第三节点电连接；
所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第一极与所述第三节点电连接，所述第八晶体管的第二极与第二电压端电连接；
所述第七晶体管为p型晶体管，所述第八晶体管为n型晶体管。
可选的，所述第一初始化电路包括第九晶体管，所述第一电压维持电路包括第一电容；
所述第九晶体管的栅极与所述初始控制端电连接，所述第九晶体管的第一极与第一电压端电连接，所述第九晶体管的第二极与第一节点电连接；
所述第一电容的第一端与所述第一节点电连接，所述第一电容的第二端与所述直流电压端或第二节点电连接。
可选的，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十 晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
所述第十一晶体管的栅极与所述第一节点电连接，所述第十一晶体管的第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
所述第十三晶体管的栅极与所述第一节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
可选的，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
所述第十一晶体管的栅极与所述第三节点电连接，所述第十一晶体管的第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
所述第十三晶体管的栅极与所述第三节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
可选的，所述输出电路包括第十四晶体管和第十五晶体管；
所述第十四晶体管的栅极与第四节点电连接，所述第十四晶体管的第一极与第一电压端电连接，所述第十四晶体管的第二极与输出驱动端电连接；
所述第十五晶体管的栅极与所述第四节点电连接，所述第十五晶体管的第一极与所述输出驱动端电连接，所述第十五晶体管的第二极与第二电压端电连接。
可选的，所述驱动信号生成电路包括第一控制电路、第二控制电路、第三反相器和第二初始化电路；
所述第一控制电路分别与第一时钟信号端、第二时钟信号端、第N-1级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第六节点输出反相后的信号；
所述第二控制电路分别与所述第一时钟信号端、所述第二时钟信号端、第N级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号和所述第二时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第六节点输出反相后的信号；
所述第三反相器分别与所述第六节点和所述第N级驱动信号输出端电连接，用于对所述第六节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
可选的，所述第一控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
所述第十六晶体管的栅极与所述第二时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述 第十七晶体管的第二极与所述第六节点电连接；
所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第六节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
所述第十九晶体管的栅极与所述第一时钟信号端电连接，所述第十九晶体管的第二极与所述第二电压端电连接；
所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
可选的，所述第二控制电路包括第二十晶体管、第二十一晶体管、第二十二晶体管和第二十三晶体管；
所述第二十晶体管的栅极与所述第一时钟信号端电连接，所述第二十晶体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
所述第二十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十一晶体管的第二极与所述第六节点电连接；
所述第二十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十二晶体管的第一极与所述第六节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
所述第二十三晶体管的栅极与所述第二时钟信号端电连接，所述第二十三晶体管的第二极与所述第二电压端电连接；
所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
可选的，所述第三反相器包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
所述第二十四晶体管的栅极与所述第六节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极电连接；
所述第二十五晶体管的栅极与所述第六节点电连接，所述第二十五晶体管的第二极与第二电压端电连接；
所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
在第二个方面中，本公开实施例提供一种驱动方法，应用于上述的驱动电路，所述驱动方法包括：
驱动信号生成电路对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
选通电路在选通控制信号的控制下，控制将选通输入端提供的选通输入信号写入第一节点；
输出控制电路对所述第N级驱动信号和所述输出控制电路的第二端的电位进行与非操作，得到第一输出信号；
输出电路用于对所述第一输出信号进行反相，得到并通过输出驱动端提供输出驱动信号。
在第三个方面中，本公开实施例提供一种驱动模组，包括多级上述的驱动电路；
第N级驱动电路与第N-1级驱动电路包括的驱动信号输出端电连接；N为正整数。
在第三个方面中，本公开实施例一种显示装置，包括上述的驱动模组。
附图说明
图1是本公开实施例所述的驱动电路的结构图；
图2是相关的像素电路的电路图；
图3是图2所示的相关的像素电路的工作时序图；
图4是相关的像素电路的电路图；
图5是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图6是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图7是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图8是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图9是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图10是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图11是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图12是本公开实施例所述的驱动电路中的选通电路的至少一实施例的电路图；
图13是反相器的至少一实施例的电路图；
图14是反相器的至少一实施例的电路图；
图15是本公开至少一实施例所述的驱动电路的结构图；
图16是本公开至少一实施例所述的驱动电路的结构图；
图17是本公开至少一实施例所述的驱动电路的结构图；
图18是本公开至少一实施例所述的驱动电路的结构图；
图19是本公开至少一实施例所述的驱动电路的结构图；
图20是本公开至少一实施例所述的驱动电路的结构图；
图21是本公开至少一实施例所述的驱动电路的结构图；
图22是本公开至少一实施例所述的驱动电路的电路图；
图23是本公开至少一实施例所述的驱动电路的电路图；
图24是图23所示的驱动电路的至少一实施例的工作时序图；
图25是本公开至少一实施例所述的驱动电路的电路图；
图26是本公开至少一实施例所述的驱动模组的结构图；
图27是图26所示的驱动模组的至少一实施例的工作时序图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的驱动电路，包括驱动信号生成电路10、选通电路11、输出控制电路12和输出电路13；
所述驱动信号生成电路10分别与第N-1级驱动信号输出端NS(N-1)和第N级驱动信号输出端NS(N)电连接，用于对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号；
所述选通电路11分别与第一节点N1、选通输入端VCT和选通控制端CX电连接，用于在所述选通控制端CX提供的选通控制信号的控制下，控制将所述选通输入端VCT提供的选通输入信号写入所述第一节点N1；
所述输出控制电路12的第一端与所述第N级驱动信号输出端NS(N)电连接，所述输出控制电路12的第二端与所述第一节点N1电连接，用于对所述第N级驱动信号和所述输出控制电路的第二端的电位进行与非操作，得到第一输出信号；
所述输出电路13分别与所述输出控制电路12和输出驱动端NO(N)电连接，用于对所述第一输出信号进行反相，得到并通过输出驱动端NO(N)提供输出驱动信号；
N为正整数。
本公开图1所示的驱动电路的实施例在工作时，驱动信号生成电路10对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行移位 操作，得到并通过第N级驱动信号输出端NS(N)输出第N级驱动信号，选通电路11在选通控制信号的控制下，将选通输入信号写入第一节点N1；输出控制电路12对第N级驱动信号和所述输出控制电路12的第二端的电位进行与非操作，得到第一输出信号，输出电路13对第一输出信号进行反相，得到并通过输出驱动端NO(N)提供输出驱动信号。
本公开图1所示的驱动电路的实施例可以为第N级驱动电路。
本公开图1所示的驱动电路的实施例在工作时，在一帧时间内，
在第N级驱动信号提供阶段之前，选通电路11在选通控制信号的控制下，将选通输入端VCT提供的选通输入信号写入第一节点N1；
当所述选通输入信号为高电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述输出控制电路12输出的第一输出信号为低电压信号，输出电路13通过输出驱动端NO(N)提供高电压信号，可以控制相应行像素电路更新像素电压；
当所述选通输入信号为低电压信号时，在第N级驱动信号提供阶段，第N级驱动信号输出端NS(N)输出高电压信号，则所述输出控制电路12输出的第一输出信号为高电压信号，输出电路13通过输出驱动端NO(N)提供低电压信号，可以控制相应行像素电路不更新像素电压。
本公开实施例可以通过控制所述选通输入端VCT提供的选通输入信号，实现显示屏幕局部画面的更新，从而降低功耗，或通过显示画面局部更新实现穿戴产品、移动终端、NB(笔记本电脑)等OLED显示产品的超低功耗。
如图2所示，相关的像素电路可以包括第一显示控制晶体管M1、第二显示控制晶体管M2、驱动晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、存储电容Cst和有机发光二极管O1；
M1的栅极与第一复位端NR(N)电连接，M1的源极与初始电压端I1电连接，M1的漏极与M3的栅极电连接；
M2的栅极与第一扫描端NG(N)电连接，M2的源极与M3的栅极电连接，M2的漏极与M3的漏极电连接；
M4的栅极与第二扫描端PG(N)电连接，M4的源极与数据线D1电连 接，M4的漏极与M3的源极电连接；
M5的栅极与发光控制端E(N)电连接，M5的源极与电源电压端ELVDD电连接，M5的漏极与M3的源极电连接；
M6的栅极与发光控制端E(N)电连接，M6的源极与M3的漏极电连接，M6的漏极与O1的阳极电连接；O1的阴极与低电平端ELVSS电连接；
M7的栅极与第二扫描端PG(N)电连接，M7的源极与初始电压端I1电连接，M7的漏极与O1的阳极电连接。
在具体实施时，所述第一复位端NR(N)可以为第N-1级第一扫描端NG(N)，但不以此为限。
在图2所示的相关的像素电路中，M1和M2为n型晶体管，M3、M4、M5、M6和M7都为p型晶体管，M1和M2为漏电流较小的IGZO TFT，M3、M4、M5、M6和M7都为LTPS TFT。
在图2所示的相关的像素电路中，M1和M2为IGZO TFT，在使用低频显示时，IGZO TFT可以保证Cst能够在较长时间内维持M3的栅极的电压。
在图2所示的相关的像素电路中，第二扫描端PG(N)负责O1的阳极的电压的复位和数据线上的数据电压写入驱动晶体管的源极，第一扫描端NG(N)负责实现Cst的复位，Vth(Vth为驱动晶体管的阈值电压)提取和数据电压写入驱动晶体管的栅极。
在具体实施时，所述第一扫描端NG(N)提供的第一扫描信号与所述第二扫描端PG(N)提供的第二扫描信号可以相互反相，但不以此为限。
本公开至少一实施例所述的驱动电路可以通过输出驱动端NO(N)为第一扫描端NG(N)提供第一扫描信号，但不以此为限。
如图3所示，图2所示的相关的像素电路在工作时，显示周期可以包括先后设置的第一显示控制阶段t1、第二显示控制阶段t2和第三显示控制阶段t3；
在第一显示控制阶段t1，E(N)输出高电压信号，NR(N)提供高电压信号，PG(N)提供高电压信号，NG(N)提供低电压信号，M5和M6关断，M1打开，将M3的栅极的电位拉低为初始电压Vinit；所述初始电压端I1用于提供所述初始电压Vinit；
在第二显示控制阶段t2，E(N)输出高电压信号，NR(N)提供低电压信号，PG(N)提供低电压信号，NG(N)提供高电压信号，M5和M6关断，M1关断，M2打开，M4打开，M2与M3形成二极管结构，通过数据线D1提供的数据电压Vdata为Cst充电，直至M3关断，此时M3的栅极电压为Vdata+Vth，Vth为M3的阈值电压；M7打开，以对O1的阳极电压进行复位操作；
在第三显示控制阶段t3，E(N)输出低电压信号，NR(N)提供低电压信号，PG(N)提供高电压信号，NG(N)提供低电压信号，M5和M6打开，M3驱动O1发光；O1依据Vdata的电压设定进行发光。
由以上相关的像素电路的工作过程可知，NG(N)可以在第二显示控制阶段控制数据电压Vdata(所述数据电压Vdata可以为所述像素电压)是否写入M3的栅极。
图4是相关的像素电路的电路图。
如图4所示，相关的像素电路可以包括第一显示控制晶体管M1、第二显示控制晶体管M2、驱动晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、存储电容Cst和有机发光二极管O1；
M1的栅极与第三复位端RST1电连接，M1的源极与初始电压端I1电连接，M1的漏极与M3的漏极电连接；
M2的栅极与第一扫描端NG(N)电连接，M2的源极与M3的栅极电连接，M2的漏极与M3的漏极电连接；
M4的栅极与第二扫描端PG(N)电连接，M4的源极与数据线D1电连接，M4的漏极与M3的源极电连接；
M5的栅极与发光控制端E(N)电连接，M5的源极与电源电压端ELVDD电连接，M5的漏极与M3的源极电连接；
M6的栅极与发光控制端E(N)电连接，M6的源极与M3的漏极电连接，M6的漏极与O1的阳极电连接；O1的阴极与低电平端ELVSS电连接；
M7的栅极与第四复位端RST2电连接，M7的源极与初始电压端I1电连接，M7的漏极与O1的阳极电连接。
图4所示的相关的像素电路在工作时，NG(N)可以控制数据线D1上的数据电压Vdata是否写入驱动晶体管M3的栅极。
在具体实施时，可以通过NG(N)提供的第一扫描信号以控制打开第二晶体管或关断第二晶体管，以控制数据线上的数据电压是否写入驱动晶体管的栅极，从而控制是否对本行像素电路的亮度进行更新；当NG(N)输出高电压信号时，第二晶体管打开，可以对本行像素电路的亮度进行更新；当NG(N)输出低电压信号时，第二晶体管始终关闭，数据线上的数据电压的变化不会写入驱动晶体管的栅极，有机发光二极管的发光亮度不会变化，即当前行像素电路在当前帧的显示亮度维持不变。综上可知，可以通过控制N型晶体管的打开或关闭，即可实现像素亮度的刷新，因此当想实现部分像素不刷新时，保证N型晶体管关闭即可。
在本公开至少一实施例中，所述选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述选通输入端提供的选通输入信号写入所述第一节点。
在具体实施时，所述选通电路可以在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，将选通输入信号写入第一节点。
可选的，所述第一电压可以为高电压，所述第二电压可以为低电压，但不以此为限。在本公开至少一实施例中，所述第一电压也可以为低电压，所述第二电压可以为高电压。
可选的，所述选通电路包括第一晶体管；所述第一晶体管的栅极与所述选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述选通输入端电连接。
如图5所示，所述选通电路可以包括第一晶体管T1；
所述第一晶体管T1的栅极与选通控制端S0电连接，所述第一晶体管T1的漏极与第一节点N1电连接，所述第一晶体管T1的源极与选通输入端VCT电连接；
T1为p型晶体管。
如图6所示，所述选通电路可以包括第一晶体管T1；
所述第一晶体管T1的栅极与选通控制端S0电连接，所述第一晶体管T1 的源极与第一节点N1电连接，所述第一晶体管T1的漏极与选通输入端VCT电连接；
T1为n型晶体管。
在本公开至少一实施例中，所述选通控制端包括第一选通控制端和第二选通控制端；所述选通电路包括第一晶体管和第二晶体管；
所述第一晶体管的栅极与第一选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
所述第二晶体管的栅极与第二选通控制端电连接，所述第二晶体管的第二极与所述选通输入端电连接；
所述第一选通控制端为第N-1级驱动信号输出端，所述第二选通控制端为第N级驱动信号输出端，第一晶体管为n型晶体管，第二晶体管为p型晶体管；或者，
所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端为第N-1级驱动信号输出端，第一晶体管为p型晶体管，第二晶体管为n型晶体管；或者，
所述第一选通控制端接入第N-1级驱动信号的反相信号，所述第二选通控制端为第N级驱动信号输出端，所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端接入第N-1级驱动信号的反相信号；所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
所述第一选通控制端为第N-1级驱动信号端，所述第二选通控制端接入第N级驱动信号的反相信号，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，
所述第一选通控制端接入第N级驱动信号的反相信号，所述第二选通控制端为第N-1级驱动信号端，所述第一晶体管和所述第二晶体管都为n型晶体管。
如图7所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的漏极电连接；
所述第二晶体管T2的栅极与第N级驱动信号输出端NS(N)电连接，所述第二晶体管T2的源极与所述选通输入端VCT电连接；
T1为n型晶体管，T2为p型晶体管。
如图8所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第N级驱动信号输出端NS(N)电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接，所述第一晶体管T1的源极与所述第二晶体管T2的源极电连接；
所述第二晶体管T2的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第二晶体管T2的漏极与所述选通输入端VCT电连接；
T1为p型晶体管，T2为n型晶体管。
如图9所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第一反相驱动信号端NGI1电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接，所述第一晶体管T1的源极与所述第二晶体管T2的漏极电连接；所述第一反相驱动信号端NGI1提供的第一反相驱动信号与第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号反相；
所述第二晶体管T2的栅极与第N级驱动信号输出端NS(N)电连接，所述第二晶体管T2的源极与所述选通输入端VCT电连接；
T1为p型晶体管，T2为p型晶体管。
如图10所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第N级驱动信号输出端NS(N)电连接，所述第一晶体管T1的漏极与所述第一节点N1电连接，所述第一晶体管T1的源极与所述第二晶体管T2的漏极电连接；
所述第二晶体管T2的栅极与第一反相驱动信号端NGI1电连接，所述第二晶体管T2的源极与所述选通输入端VCT电连接；所述第一反相驱动信号端NGI1提供的第一反相驱动信号与第N-1级驱动信号输出端NS(N-1)提 供的第N-1级驱动信号反相；
T1为p型晶体管，T2为p型晶体管。
如图11所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的源极电连接；
所述第二晶体管T2的栅极与第二反相驱动信号端NGI2电连接，所述第二晶体管T2的漏极与所述选通输入端VCT电连接；所述第二反相驱动信号端NGI2提供的第二反相驱动信号与第N级驱动信号输出端NS(N)提供的第N级驱动信号反相；
T1为n型晶体管，T2为n型晶体管。
如图12所示，所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第二反相驱动信号端NGI2电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的源极电连接；所述第二反相驱动信号端NGI2提供的第二反相驱动信号与第N级驱动信号输出端NS(N)提供的第N级驱动信号反相；
所述第二晶体管T2的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第二晶体管T2的漏极与所述选通输入端VCT电连接；
T1为n型晶体管，T2为n型晶体管。
如图13所示，可以通过第一反相电路对第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号进行反相，得到第一反相驱动信号端NGI1提供的第一反相驱动信号；
所述第一反相电路包括第一反相控制晶体管T01和第二反相控制晶体管T02；
T01为p型晶体管，T02为n型晶体管。
如图14所示，可以通过第二反相电路对第N级驱动信号输出端NS(N)提供的第N级驱动信号进行反相，得到第二反相驱动信号端NGI2提供的第二反相驱动信号；
所述第二反相电路包括第三反相控制晶体管T03和第四反相控制晶体管T04；
T03为p型晶体管，T04为n型晶体管。
本公开至少一实施例所述的驱动电路还包括第一初始化电路；
所述第一初始化电路分别与初始控制端、第一电压端和第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第一节点与所述第一电压端之间连通。
在具体实施时，所述驱动电路还可以包括第一初始化电路，第一初始化电路在初始控制信号的控制下，控制第一节点与第一电压端之间连通。
可选的，所述第一电压端可以为高电压端。
本公开至少一实施例所述的驱动电路还包括第一电压维持电路；
所述第一电压维持电路的第一端与所述第一节点电连接，所述第一电压维持电路的第二端与直流电压端第二节点电连接，所述第一电压维持电路用于维持第一节点的电位。
在具体实施时，所述驱动电路还可以包括第一电压维持电路，第一电压维持电路维持第一节点的电位。
如图15所示，在图1所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第一初始化电路21；
所述第一初始化电路21分别与初始控制端NCX、第一电压端V1和第一节点N1电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第一节点N1与所述第一电压端V1之间连通。
图15所示的驱动电路的至少一实施例在工作时，在一帧时间开始时，NCX提供有效电压信号，所述第一初始化电路21控制第一节点N1与第一电压端V1之间连通。
如图16所示，在图15所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还可以包括第一电压维持电路22；
所述第一电压维持电路22的第一端与所述第一节点N1电连接，所述第一电压维持电路22的第二端与第一电压端V1电连接，所述第一电压维持电路22用于维持第一节点N1的电位。
在本公开至少一实施例中，所述驱动电路还包括第二电压维持电路，所述第一节点通过所述第二电压维持电路与所述输出控制电路的第二端电连接；
所述第二电压维持电路包括第一反相器、第二反相器和维持控制电路；
所述第一反相器的输入端与所述第一节点电连接，所述第一反相器的输出端与第二节点电连接，所述第二反相器的输入端与所述第二节点电连接，所述第二反相器的输出端与第三节点和所述输出控制电路的第二端电连接；
所述第一反相器用于对所述第一节点的电位进行反相，并通过第一反相器的输出端输出反相后的第一节点的电位，所述第二反相器用于对其输入端的电位进行反相，并通过所述第二反相器的输出端输出反相后的电位；
所述维持控制电路分别与维持控制端、所述第三节点和所述第一节点电连接，用于在所述维持控制端提供的维持控制信号的控制下，控制所述第三节点与所述第一节点之间连通或断开。
在具体实施时，所述驱动电路还可以包括第二电压维持电路，所述第一节点可以通过所述第二电压维持电路与所述输出控制电路的第二端电连接，所述第二电压维持电路可以包括第一反相器、第二反相器和维持控制电路；第一反相器对所述第一节点的电位进行反相，第二反相器对其输入端的电位进行反相；所述维持控制电路在所述维持控制端提供的维持控制信号的控制下，控制所述第三节点与所述第一节点之间连通或断开；
所述维持控制电路可以在所述选通电路控制将所述选通输入信号写入所述第一节点时，控制第三节点与第一节点之间断开。
本公开至少一实施例所述的驱动电路在工作时，通过增设第二电压维持电路，第二电压维持电路包括的第一反相器和第二反相器可以当第一节点的电位为高电压时，控制第三节点与高电压端之间连通，可以使得第三节点的电位高于第一节点的电位，并可以当第一节点的电位为低电压时，控制第三节点与低电压端之间连通，可以使得第三节点的电位低于第一节点的电位，使得第三节点能够更好的控制输出控制电路包括的栅极与第三节点电连接的晶体管。
如图17所示，在图15所示的驱动电路的至少一实施例的基础上，
所述驱动电路还可以包括第二电压维持电路；所述维持控制端包括第N-1 级驱动信号输出端NS(N-1)和第一时钟信号端GCK；
所述第一节点N1通过所述第二电压维持电路与所述输出控制电路12的第二端电连接；
所述第二电压维持电路包括第一反相器F1、第二反相器F2和维持控制电路W1；
所述第一反相器F1的输入端与所述第一节点N1电连接，所述第一反相器F1的输出端与第二节点N2电连接；
所述第二反相器F2的输入端与所述第二节点N2电连接，所述第二反相器F2的输出端与第三节点N3和所述输出控制电路12的第二端电连接；
所述第一反相器F1用于对所述第一节点N1的电位进行反相，并通过第一反相器F1的输出端输出反相后的第一节点的电位；
所述第二反相器F2用于对其输入端的电位进行反相，并通过所述第二反相器F2的输出端输出反相后的电位；
所述维持控制电路W1分别与第N-1级驱动信号输出端NS(N-1)、第一时钟信号端GCK、所述第三节点N3和所述第一节点N1电连接，用于在第N-1级驱动信号输出端NS(N-1)提供的第N-1级驱动信号的控制下，控制所述第三节点N3与所述第一节点N1之间连通或断开，在所述第一时钟信号端GCK提供的第一时钟信号的控制下，控制所述第三节点N3与所述第一节点N1之间连通或断开。
在图17所示的至少一实施例中，第N-1级驱动信号输出端可以被替换为第二时钟信号端，但不以此为限。
可选的，所述维持控制端包括第一维持控制端和第二维持控制端；
所述维持控制电路包括第三晶体管和第四晶体管；
所述第三晶体管的栅极与第一维持控制端电连接，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与所述第三节点电连接；
所述第四晶体管的栅极与第二维持控制端电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第一节点电连接；
所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管；
所述第一维持控制端为第N-1级驱动信号端，所述第二维持控制端为第一时钟信号端；或者，
所述第一维持控制端为第二时钟信号端，所述第二维持控制端为第一时钟信号端。
可选的，所述第一反相器包括第五晶体管和第六晶体管，所述第二反相器包括第七晶体管和第八晶体管；
所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与第一电压端电连接，所述第五晶体管的第二极与第二节点电连接；
所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一极与所述第二节点电连接，所述第六晶体管的第二极与第二电压端电连接；
所述第五晶体管为p型晶体管，所述第六晶体管为n型晶体管；
所述第七晶体管的栅极与所述第二节点电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与第三节点电连接；
所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第一极与所述第三节点电连接，所述第八晶体管的第二极与第二电压端电连接；
所述第七晶体管为p型晶体管，所述第八晶体管为n型晶体管。
可选的，所述第一初始化电路包括第九晶体管，所述第一电压维持电路包括第一电容；
所述第九晶体管的栅极与所述初始控制端电连接，所述第九晶体管的第一极与第一电压端电连接，所述第九晶体管的第二极与第一节点电连接；
所述第一电容的第一端与所述第一节点电连接，所述第一电容的第二端与所述直流电压端或第二节点电连接。
可选的，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
所述第十一晶体管的栅极与所述第一节点电连接，所述第十一晶体管的 第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
所述第十三晶体管的栅极与所述第一节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
可选的，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
所述第十一晶体管的栅极与所述第三节点电连接，所述第十一晶体管的第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
所述第十三晶体管的栅极与所述第三节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
可选的，所述输出电路包括第十四晶体管和第十五晶体管；
所述第十四晶体管的栅极与第四节点电连接，所述第十四晶体管的第一 极与第一电压端电连接，所述第十四晶体管的第二极与输出驱动端电连接；
所述第十五晶体管的栅极与所述第四节点电连接，所述第十五晶体管的第一极与所述输出驱动端电连接，所述第十五晶体管的第二极与第二电压端电连接。
在本公开至少一实施例中，所述驱动信号生成电路可以包括第一控制电路、第二控制电路、第三反相器和第二初始化电路；
所述第一控制电路分别与第一时钟信号端、第二时钟信号端、第N-1级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第N-1级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第六节点输出反相后的信号；
所述第二控制电路分别与所述第一时钟信号端、所述第二时钟信号端、第N级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号和所述第二时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第六节点输出反相后的信号；
所述第三反相器分别与所述第六节点和所述第N级驱动信号输出端电连接，用于对所述第六节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
在具体实施时，所述驱动信号生成电路可以包括第一控制电路、第二控制电路、第三反相器和第二初始化电路；所述第一控制电路在第一时钟信号和第二时钟信号的控制下，对第N-1驱动信号进行移位并反相操作，通过第六节点输出反相后的信号，第二控制电路在第一时钟信号和第二时钟信号的控制下，对第N级驱动信号进行反相，通过第六节点输出反相后的信号，第三反相器对第六节点的电位进行反相，通过第N级驱动信号输出端输出反相后的信号；第二初始化电路在初始控制信号的控制下，控制第N级驱动信号输出端与第一电压端之间连通。
如图18所示，在图16所示的驱动电路的至少一实施例的基础上，所述驱动信号生成电路可以包括第一控制电路31、第二控制电路32、第三反相器F3和第二初始化电路30；
所述第一控制电路31分别与第一时钟信号端GCK、第二时钟信号端GCB、第N-1级驱动信号输出端NS(N-1)和第六节点N6电连接，用于在所述第一时钟信号端GCK提供的第一时钟信号和所述第二时钟信号端GCB提供的第二时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1驱动信号进行移位并反相，得到并通过所述第六节点N6输出反相后的信号；
所述第二控制电路32分别与所述第一时钟信号端GCK、所述第二时钟信号端GCB、第N级驱动信号输出端NS(N)和第六节点N6电连接，用于在所述第一时钟信号和所述第二时钟信号的控制下，对所述第N级驱动信号输出端NS(N)提供的第N级驱动信号进行反相，得到并通过所述第六节点N6输出反相后的信号；
所述第三反相器F3分别与所述第六节点N6和所述第N级驱动信号输出端NS(N)电连接，用于对所述第六节点N6的电位进行反相，并通过所述第N级驱动信号输出端NS(N)输出反相后的信号；
所述第二初始化电路30分别与初始控制端NCX、第一电压端V1和所述第N级驱动信号输出端NS(N)电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第N级驱动信号输出端NS(N)与所述第一电压端V1之间连通。
如图19所示，在图17所示的驱动电路的至少一实施例的基础上，所述驱动信号生成电路可以包括第一控制电路31、第二控制电路32、第三反相器F3和第二初始化电路30；
所述第一控制电路31分别与第一时钟信号端GCK、第二时钟信号端GCB、第N-1级驱动信号输出端NS(N-1)和第六节点N6电连接，用于在所述第一时钟信号端GCK提供的第一时钟信号和所述第二时钟信号端GCB提供的第二时钟信号的控制下，对所述第N-1级驱动信号输出端NS(N-1)提供的第N-1驱动信号进行移位并反相，得到并通过所述第六节点N6输出反相后 的信号；
所述第二控制电路32分别与所述第一时钟信号端GCK、所述第二时钟信号端GCB、第N级驱动信号输出端NS(N)和第六节点N6电连接，用于在所述第一时钟信号和所述第二时钟信号的控制下，对所述第N级驱动信号输出端NS(N)提供的第N级驱动信号进行反相，得到并通过所述第六节点N6输出反相后的信号；
所述第三反相器F3分别与所述第六节点N6和所述第N级驱动信号输出端NS(N)电连接，用于对所述第六节点N6的电位进行反相，并通过所述第N级驱动信号输出端NS(N)输出反相后的信号；
所述第二初始化电路30分别与初始控制端NCX、第一电压端V1和所述第N级驱动信号输出端NS(N)电连接，用于在所述初始控制端NCX提供的初始控制信号的控制下，控制所述第N级驱动信号输出端NS(N)与所述第一电压端V1之间连通。
可选的，所述第一控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
所述第十六晶体管的栅极与所述第二时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十七晶体管的第二极与所述第六节点电连接；
所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第六节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
所述第十九晶体管的栅极与所述第一时钟信号端电连接，所述第十九晶体管的第二极与所述第二电压端电连接；
所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
可选的，所述第二控制电路包括第二十晶体管、第二十一晶体管、第二十二晶体管和第二十三晶体管；
所述第二十晶体管的栅极与所述第一时钟信号端电连接，所述第二十晶体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
所述第二十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十一晶体管的第二极与所述第六节点电连接；
所述第二十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十二晶体管的第一极与所述第六节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
所述第二十三晶体管的栅极与所述第二时钟信号端电连接，所述第二十三晶体管的第二极与所述第二电压端电连接；
所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
可选的，所述第三反相器包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
所述第二十四晶体管的栅极与所述第六节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极电连接；
所述第二十五晶体管的栅极与所述第六节点电连接，所述第二十五晶体管的第二极与第二电压端电连接；
所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
可选的，所述第一电压端可以为高电压端，所述第二电压端可以为低电压端，但不以此为限。
图20所示的驱动电路的至少一实施例与图18所示的驱动电路的至少一实施例的区别在于：图20所示的驱动电路的至少一实施例不包含第一电压维持电路。
图21所示的驱动电路的至少一实施例与图19所示的驱动电路的至少一 实施例的区别在于：图21所示的驱动电路的至少一实施例还包含第一电压维持电路22；
所述第一电压维持电路22的第一端与所述第一节点N1电连接，所述第一电压维持电路22的第二端与第一电压端V1电连接，所述第一电压维持电路22用于维持第一节点N1的电位。
如图22所示，在图20所示的驱动电路的至少一实施例的基础上，
所述选通电路可以包括第一晶体管T1和第二晶体管T2；
所述第一晶体管T1的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第一晶体管T1的源极与所述第一节点N1电连接，所述第一晶体管T1的漏极与所述第二晶体管T2的漏极电连接；
所述第二晶体管T2的栅极与第N级驱动信号输出端NS(N)电连接，所述第二晶体管T2的源极与所述选通输入端VCT电连接；
T1为n型晶体管，T2为p型晶体管；
所述第一初始化电路包括第九晶体管T9；
所述第九晶体管T9的栅极与所述初始控制端NCX电连接，所述第九晶体管T9的源极与高电压端VGH电连接，所述第九晶体管T9的漏极与第一节点N1电连接；
所述输出控制电路包括第十晶体管T10、第十一晶体管T11、第十二晶体管T12和第十三晶体管T13；
所述第十晶体管T10的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第十晶体管T10的源极与高电压端VGH电连接，所述第十晶体管T10的源极与第四节点N4电连接；
所述第十一晶体管T11的栅极与所述第一节点N1电连接，所述第十一晶体管T11的源极与所述高电压端VGH电连接，所述第十一晶体管T11的漏极所述第四节点N4电连接；
所述第十二晶体管T12的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第十二晶体管T12的源极与所述第四节点N4电连接，所述第十二晶体管T12的漏极与所述第五节点N5电连接；
所述第十三晶体管T13的栅极与所述第一节点N1电连接，所述第十三 晶体管T13的源极与所述第五节点N5电连接，所述第十三晶体管T13的漏极与低电压端VGL电连接；
所述第十晶体管T10和所述第十一晶体管T11为p型晶体管，所述第十二晶体管T12和所述第十三晶体管T13为n型晶体管；
所述输出电路包括第十四晶体管T14和第十五晶体管T15；
所述第十四晶体管T14的栅极与第四节点N4电连接，所述第十四晶体管T14的源极与高电压端VGH电连接，所述第十四晶体管T14的漏极与输出驱动端NO(N)电连接；
所述第十五晶体管T15的栅极与所述第四节点N4电连接，所述第十五晶体管T15的源极与所述输出驱动端NO(N)电连接，所述第十五晶体管T15的漏极与低电压端VGL电连接；
所述第一控制电路包括第十六晶体管T16、第十七晶体管T17、第十八晶体管T18和第十九晶体管T19；
所述第十六晶体管T16的栅极与所述第二时钟信号端GCB电连接，所述第十六晶体管T16的源极与高电压端VGH电连接，所述第十六晶体管T16的漏极与所述第十七晶体管T17的源极电连接；
所述第十七晶体管T17的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十七晶体管T17的漏极与所述第六节点N6电连接；
所述第十八晶体管T18的栅极与所述第N-1级驱动信号输出端NS(N-1)电连接，所述第十八晶体管T18的源极与所述第六节点N6电连接，所述第十八晶体管T18的漏极与所述第十九晶体管T19的源极电连接；
所述第十九晶体管T19的栅极与所述第一时钟信号端GCK电连接，所述第十九晶体管T19的源极与低电压端VGL电连接；
所述第十六晶体管T16和所述第十七晶体管T17为p型晶体管，所述第十八晶体管T18和所述第十九晶体管T19为n型晶体管；
所述第二控制电路包括第二十晶体管T20、第二十一晶体管T21、第二十二晶体管T22和第二十三晶体管T23；
所述第二十晶体管T20的栅极与所述第一时钟信号端GCK电连接，所述第二十晶体管T20的源极与高电压端VGH电连接，所述第二十晶体管T20 的漏极与所述第二十一晶体管T21的源极电连接；
所述第二十一晶体管T21的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十一晶体管T21的漏极与所述第六节点N6电连接；
所述第二十二晶体管T22的栅极与所述第N级驱动信号输出端NS(N)电连接，所述第二十二晶体管T22的源极与所述第六节点N6电连接，所述第二十二晶体管T22的源极与所述第二十三晶体管T23的漏极电连接；
所述第二十三晶体管T23的栅极与所述第二时钟信号端GCB电连接，所述第二十三晶体管T23的漏极与所述低电压端VGL电连接；
所述第二十晶体管T20和所述第二十一晶体管T21为p型晶体管，所述第二十二晶体管T22和所述第二十三晶体管T23为n型晶体管；
所述第三反相器包括第二十四晶体管T24和第二十五晶体管T25；所述第二初始化电路包括第二十六晶体管T26；
所述第二十四晶体管T24的栅极与所述第六节点N6电连接，所述第二十四晶体管T24的源极与所述高电压端VGH电连接，所述第二十四晶体管T24的漏极与所述第二十五晶体管T25的源极电连接；
所述第二十五晶体管T25的栅极与所述第六节点N6电连接，所述第二十五晶体管T25的漏极与低电压端VGL电连接；
所述第二十四晶体管T24为p型晶体管，所述第二十五晶体管T25为n型晶体管；
所述第二十六晶体管T26的栅极与所述初始控制端NCX电连接，所述第二十六晶体管T26的源极与所述高电压端VGH电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端NS(N)电连接；
所述第二十六晶体管T26为p型晶体管。
在本公开至少一实施例中，所述驱动信号生成电路的结构并不限于如图22所示，所述驱动信号生成电路例如可以为16T3C电路、13T3C电路、12T3C电路、10T3C电路等，但不以此为限。
本公开图22所述的驱动电路的至少一实施例在工作时，
1、当GCK提供高电压信号时，T19打开，T20关闭，GCB提供低电压信号，T16打开，T23关闭，此时驱动信号生成电路处于传输状态；
当NS(N)提供低电压信号时，打开T17，关闭T18，N6的电位为高电压，打开T25，关闭T24，NS(N)提供低电压信号，NS(N-1)提供低电压信号；
当NS(N)提供高电压信号时，关闭T17，打开T18，N6的电位为低电压，关闭T25，打开T24，NS(N)和NS(N-1)都提供高电压信号；
2、当GCK提供低电压信号时，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位与NS(N)提供的信号维持之前状态不变；
3、当NS(N-1)提供的信号由低电压信号切换为高电压信号时，GCK提供低电压信号，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位与NS(N)提供的信号维持之前的低电压状态不变，完成移位。在下一个时刻，GCK提供高电压信号，打开T19，关闭T20，GCB提供低电压信号，打开T16，关闭T23，此时电路处于传输状态，NS(N-1)提供高电压信号，关闭T17，打开T18，N6的电位为低电压，关闭T25，打开T24，NS(N)和NS(N-1)都提供高电压信号，实现NS(N-1)向NS(N)的移位寄存；
4、当NS(N-1)从提供高电压信号切换为提供低电压信号时，GCK提供低电压信号，关闭T19，打开T20，GCB提供高电压信号，关闭T16，打开T23，此时电路处于寄存状态，T21、T22、T23和T11组成锁存电路，N6的电位和NS(N)提供的信号维持为之前的高电压状态不变，完成移位；在下一个时刻，GCK提供高电压信号，打开T19，关闭T20，GCB提供低电压信号，打开T16，关闭T23，此时电路处于传输状态，NS(N-1)提供低电压信号，打开T17，关闭T18，N6的电位为高电压，打开T25，关闭T24，NS(N)和NS(N-1)都提供低电压信号，实现NS(N-1)向NS(N)的移位寄存。
本公开图22所述的驱动电路的至少一实施例在工作时，
当NS(N-1)提供高电压信号时，打开T1，NS(N)提供低电压信号时，打开T2，通过两个信号同时选通，可以获取一个高低频切换周期H内的VCT 提供的选通输入信号的状态，并写入第一节点N1，然后T1和T2在其他时间不会同时打开，防止N1的电位被VCT提供的选通输入信号的电位变化影响。T10、T11、T12和T13组成一个与非门，该与非门的输入信号分别为NS(N)提供的信号、N1的电位，该与非门的输出端与第四节点N4电连接。T24和T25组成第三反相器，所述第三反相器的输入端与N4电连接，第三反相器的输出端与NO(N)电连接；
如果VCT在T1和T2打开时提供高电压信号时，N1会被写入高电压，该与非门的选通状态可以保证NS(N)正常传递给NO(N)；
如果VCT在T1和T2打开时提供低电压信号时，N1会被写入低电压，该与非门处于截止状态，保证NO(N)提供低电压信号，从而实现NO(N)的低电平维持。
可选的，在开始显示时(也即在显示装置开机时)，在第一阶段之前的开机阶段，NCX输出低电压信号，T9打开，以控制N1的电位为高电压，T26打开，以使得NS(N)提供高电压信号；此时，T12和T13都打开，N4的电位为低电压，T14导通，T15关断，NO(N)输出高电压信号，可以将有效显示区域中的所有像素电路包括的第二显示控制晶体管M2都打开，清空存储电容Cst中残留的电荷，改善开机屏闪不良；
之后，当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，T1和T2打开，
当VCT提供低电压信号时，N1的电位为低电压信号，C1维持N1的电位；T11导通，T10导通，N4的电位为高电压，T15打开，NO(N)输出低电压信号；
当VCT提供高电压信号时，N1的电位为高电压信号，C1维持N1的电位，T11关断，T10导通，N4的电位为高电压，T15打开，NO(N)输出低电压信号；
之后，在第N级驱动信号提供阶段，NS(N)输出高电压信号，
当N1的电位为低电压时，T10关断，T11打开，N4的电位为高电压，T15打开，NO(N)输出低电压信号；
当N1的电位为高电压时，T10关断，T11关断，T12和T13导通，N4 的电位为低电压，T14打开，NO(N)输出高电压信号；
在第N级驱动信号提供阶段之后，NS(N)输出低电压信号，
当N1的电位为低电压信号时，T10导通，T11导通，N4的电位为高电压，NO(N)输出低电压信号；
当N1的电位为高电压信号时，T10导通，T11关断，N4的电位为高电压，NO(N)输出低电压信号。
本公开图22所示的驱动电路的至少一实施例在工作时，当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，T1和T2打开，通过以上两个信号同时选通，可以获取一个高低频切换周期内的选通输入信号状态。
在图22中，标号为N7的为第七节点，第七节点N7与T1的漏极电连接，第七节点N7与T1的漏极电连接。
如图23所示，在本公开图22所示的驱动电路的至少一实施例的基础上，本公开至少一实施例所述的驱动电路还包括第二电压维持电路；所述第一节点N1通过所述第二电压维持电路与T11的栅极电连接；
所述第二电压维持电路包括第一反相器、第二反相器和维持控制电路；
所述维持控制电路包括第三晶体管T3和第四晶体管T4；
所述第三晶体管T3的栅极与第N-1级驱动信号输出端NS(N-1)电连接，所述第三晶体管T3的源极与所述第一节点N1电连接，所述第三晶体管T3的漏极与所述第三节点N3电连接；
所述第四晶体管T4的栅极与第一时钟信号端GCK电连接，所述第四晶体管T4的源极与所述第三节点N3电连接，所述第四晶体管T4的漏极与所述第一节点N1电连接；
所述第一反相器包括第五晶体管T5和第六晶体管T6，所述第二反相器包括第七晶体管T7和第八晶体管T8；
所述第五晶体管T5的栅极与所述第一节点N1电连接，所述第五晶体管T5的源极与高电压端VGH电连接，所述第五晶体管T5的漏极与第二节点N2电连接；
所述第六晶体管T6的栅极与所述第一节点N1电连接，所述第六晶体管T6的源极与所述第二节点N2电连接，所述第六晶体管T6的漏极与低电压端 VGL电连接；
所述第七晶体管T7的栅极与所述第二节点N2电连接，所述第七晶体管T7的源极与所述高电压端VGH电连接，所述第七晶体管T7的漏极与第三节点N3电连接；
所述第八晶体管T8的栅极与所述第二节点N2电连接，所述第八晶体管T8的源极与所述第三节点N3电连接，所述第八晶体管T8的漏极与低电压端VGL电连接；
所述第三节点N3分别与T11的栅极和T13的栅极电连接。
在图23所示的驱动电路的至少一实施例中，所述第三晶体管T3为p型晶体管，所述第四晶体管T4为n型晶体管；所述第五晶体管T5为p型晶体管，所述第六晶体管T6为n型晶体管；所述第七晶体管T7为p型晶体管，所述第八晶体管T8为n型晶体管。
本公开图23所示的驱动电路的至少一实施例中，由于p型晶体管在传递低电压时有阈值电压损失，n型晶体管在传递高电压时有阈值电压损失，则N1的电位的绝对值会较低，则可以通过第一反相器和第二反相器控制N1的电位的绝对值升高，从而能够更好的控制输出电路中的相应的晶体管导通或关断，维持控制电路控制在T1和T2打开时，控制N1与N3之间断开，以不会影响N1的电位的写入。
图24是本公开图23所示的驱动电路的至少一实施例的工作时序图。
图25所示的驱动电路的至少一实施例与图22所示的驱动电路的至少一实施例的区别在于：图25所示的驱动电路的至少一实施例还包括第一电容C1；
第一电容C1的第一端与第一节点N1电连接，第一电容C1的第二端与低电压端VGL电连接；
C1用于稳定N1的电位。
本公开实施例所述的驱动方法，应用于上述的驱动电路，所述驱动方法包括：
驱动信号生成电路对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
选通电路在选通控制信号的控制下，控制将选通输入端提供的选通输入信号写入第一节点；
输出控制电路对所述第N级驱动信号和所述输出控制电路的第二端的电位进行与非操作，得到第一输出信号；
输出电路用于对所述第一输出信号进行反相，得到并通过输出驱动端提供输出驱动信号。
本公开实施例所述的驱动模组包括多级上述的驱动电路；
第N级驱动电路与第N-1级驱动电路包括的驱动信号输出端电连接；N为正整数。
如图26所示，标号为S1的为第一级驱动电路，标号为S2的为第二级驱动电路，标号为S3的为第三级驱动电路，标号为S4的为第四级驱动电路，标号为S5的为第五级驱动电路，标号为S6的为第六级驱动电路，标号为S7的为第七级驱动电路，标号为S8的为第八级驱动电路，标号为S9的为第九级驱动电路，标号为S10的为第十级驱动电路，标号为S11的为第十一级驱动电路，标号为S12的为第十二级驱动电路；
标号为NS(1)的为S1的驱动信号输出端，标号为NO(1)的为S1的输出驱动端；
标号为NS(2)的为S2的驱动信号输出端，标号为NO(2)的为S2的输出驱动端；S2与NS(1)电连接；
标号为NS(3)的为S3的驱动信号输出端，标号为NO(3)的为S3的输出驱动端；S3与NS(2)电连接；
标号为NS(4)的为S4的驱动信号输出端，标号为NO(4)的为S4的输出驱动端；S4与NS(3)电连接；
标号为NS(5)的为S5的驱动信号输出端，标号为NO(5)的为S5的输出驱动端；S5与NS(4)电连接；
标号为NS(6)的为S6的驱动信号输出端，标号为NO(6)的为S6的输出驱动端；S6与NS(5)电连接；
标号为NS(7)的为S7的驱动信号输出端，标号为NO(7)的为S7的输出驱动端；S7与NS(6)电连接；
标号为NS(8)的为S8的驱动信号输出端，标号为NO(8)的为S8的输出驱动端；S8与NS(7)电连接；
标号为NS(9)的为S9的驱动信号输出端，标号为NO(9)的为S9的输出驱动端；S9与NS(8)电连接；
标号为NS(10)的为S10的驱动信号输出端，标号为NO(10)的为S10的输出驱动端；S10与NS(9)电连接；
标号为NS(11)的为S11的驱动信号输出端，标号为NO(11)的为S11的输出驱动端；S11与NS(10)电连接；
标号为NS(12)的为S12的驱动信号输出端，标号为NO(12)的为S12的输出驱动端；S12与NS(11)电连接；
S1、S2、S3、S4、S5、S6、S7、S8、S9、S10、S11和S12都与选通输入端VCT电连接；
S1、S2、S3、S4、S5、S6、S7、S8、S9、S10、S11和S12都与第一时钟信号端GCK电连接；
S1、S2、S3、S4、S5、S6、S7、S8、S9、S10、S11和S12都与第二时钟信号端GCB电连接。
在图26中，标号为STV的为起始电压端，S1与STV电连接。
图27是图26所示的驱动模组的至少一实施例的工作时序图。
本公开图26所示的驱动模组的至少一实施例在工作时，当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，如若VCT输出低电压信号，则当NS(N)输出高电压信号时，NO(N)输出低电压信号；
当NS(N-1)输出高电压信号，NS(N)输出低电压信号时，如若VCT输出高电压信号，则当NS(N)输出高电压信号时，NO(N)输出高电压信号。
本公开实施例所述的显示装置包括上述的驱动模组。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种驱动电路，包括驱动信号生成电路、选通电路、输出控制电路和输出电路；
    所述驱动信号生成电路分别与第N-1级驱动信号输出端和第N级驱动信号输出端电连接，用于对所述第N-1级驱动信号输出端提供的第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
    所述选通电路分别与第一节点、选通输入端和选通控制端电连接，用于在所述选通控制端提供的选通控制信号的控制下，控制将所述选通输入端提供的选通输入信号写入所述第一节点；
    所述输出控制电路的第一端与所述第N级驱动信号输出端电连接，所述输出控制电路的第二端与所述第一节点电连接，用于对所述第N级驱动信号和所述输出控制电路的第二端的电位进行与非操作，得到第一输出信号；
    所述输出电路用于对所述第一输出信号进行反相，得到并通过输出驱动端提供输出驱动信号；
    N为正整数。
  2. 如权利要求1所述的驱动电路，其中，所述选通电路用于在第N-1级驱动信号的电位为第一电压，并第N级驱动信号的电位为第二电压时，控制将所述选通输入端提供的选通输入信号写入所述第一节点。
  3. 如权利要求1所述的驱动电路，其中，所述选通电路包括第一晶体管；所述第一晶体管的栅极与所述选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述选通输入端电连接。
  4. 如权利要求1所述的驱动电路，其中，所述选通控制端包括第一选通控制端和第二选通控制端；所述选通电路包括第一晶体管和第二晶体管；
    所述第一晶体管的栅极与第一选通控制端电连接，所述第一晶体管的第一极与所述第一节点电连接，所述第一晶体管的第二极与所述第二晶体管的第一极电连接；
    所述第二晶体管的栅极与第二选通控制端电连接，所述第二晶体管的第二极与所述选通输入端电连接；
    所述第一选通控制端为第N-1级驱动信号输出端，所述第二选通控制端为第N级驱动信号输出端，第一晶体管为n型晶体管，第二晶体管为p型晶体管；或者，
    所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端为第N-1级驱动信号输出端，第一晶体管为p型晶体管，第二晶体管为n型晶体管；或者，
    所述第一选通控制端接入第N-1级驱动信号的反相信号，所述第二选通控制端为第N级驱动信号输出端，所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
    所述第一选通控制端为第N级驱动信号输出端，所述第二选通控制端接入第N-1级驱动信号的反相信号；所述第一晶体管和所述第二晶体管都为p型晶体管；或者，
    所述第一选通控制端为第N-1级驱动信号端，所述第二选通控制端接入第N级驱动信号的反相信号，所述第一晶体管和所述第二晶体管都为n型晶体管；或者，
    所述第一选通控制端接入第N级驱动信号的反相信号，所述第二选通控制端为第N-1级驱动信号端，所述第一晶体管和所述第二晶体管都为n型晶体管。
  5. 如权利要求1所述的驱动电路，其中，还包括第一初始化电路；
    所述第一初始化电路分别与初始控制端、第一电压端和第一节点电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第一节点与所述第一电压端之间连通。
  6. 如权利要求5所述的驱动电路，其中，还包括第一电压维持电路；
    所述第一电压维持电路的第一端与所述第一节点电连接，所述第一电压维持电路的第二端与直流电压端或第二节点电连接，所述第一电压维持电路用于维持第一节点的电位。
  7. 如权利要求1至6中任一权利要求所述的驱动电路，其中，还包括第二电压维持电路，所述第一节点通过所述第二电压维持电路与所述输出控制电路的第二端电连接；
    所述第二电压维持电路包括第一反相器、第二反相器和维持控制电路；
    所述第一反相器的输入端与所述第一节点电连接，所述第一反相器的输出端与第二节点电连接，所述第二反相器的输入端与所述第二节点电连接，所述第二反相器的输出端与第三节点和所述输出控制电路的第二端电连接；
    所述第一反相器用于对所述第一节点的电位进行反相，并通过第一反相器的输出端输出反相后的第一节点的电位，所述第二反相器用于对其输入端的电位进行反相，并通过所述第二反相器的输出端输出反相后的电位；
    所述维持控制电路分别与维持控制端、所述第三节点和所述第一节点电连接，用于在所述维持控制端提供的维持控制信号的控制下，控制所述第三节点与所述第一节点之间连通或断开。
  8. 如权利要求7所述的驱动电路，其中，所述维持控制端包括第一维持控制端和第二维持控制端；
    所述维持控制电路包括第三晶体管和第四晶体管；
    所述第三晶体管的栅极与第一维持控制端电连接，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与所述第三节点电连接；
    所述第四晶体管的栅极与第二维持控制端电连接，所述第四晶体管的第一极与所述第三节点电连接，所述第四晶体管的第二极与所述第一节点电连接；
    所述第三晶体管为p型晶体管，所述第四晶体管为n型晶体管；
    所述第一维持控制端为第N-1级驱动信号端，所述第二维持控制端为第一时钟信号端；或者，
    所述第一维持控制端为第二时钟信号端，所述第二维持控制端为第一时钟信号端。
  9. 如权利要求7所述的驱动电路，其中，所述第一反相器包括第五晶体管和第六晶体管，所述第二反相器包括第七晶体管和第八晶体管；
    所述第五晶体管的栅极与所述第一节点电连接，所述第五晶体管的第一极与第一电压端电连接，所述第五晶体管的第二极与第二节点电连接；
    所述第六晶体管的栅极与所述第一节点电连接，所述第六晶体管的第一 极与所述第二节点电连接，所述第六晶体管的第二极与第二电压端电连接；
    所述第五晶体管为p型晶体管，所述第六晶体管为n型晶体管；
    所述第七晶体管的栅极与所述第二节点电连接，所述第七晶体管的第一极与所述第一电压端电连接，所述第七晶体管的第二极与第三节点电连接；
    所述第八晶体管的栅极与所述第二节点电连接，所述第八晶体管的第一极与所述第三节点电连接，所述第八晶体管的第二极与第二电压端电连接；
    所述第七晶体管为p型晶体管，所述第八晶体管为n型晶体管。
  10. 如权利要求6所述的驱动电路，其中，所述第一初始化电路包括第九晶体管，所述第一电压维持电路包括第一电容；
    所述第九晶体管的栅极与所述初始控制端电连接，所述第九晶体管的第一极与第一电压端电连接，所述第九晶体管的第二极与第一节点电连接；
    所述第一电容的第一端与所述第一节点电连接，所述第一电容的第二端与所述直流电压端或第二节点电连接。
  11. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
    所述第十一晶体管的栅极与所述第一节点电连接，所述第十一晶体管的第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
    所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
    所述第十三晶体管的栅极与所述第一节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
    所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
  12. 如权利要求7所述的驱动电路，其中，所述输出控制电路包括第十晶体管、第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十晶体管的第一极与第一电压端电连接，所述第十晶体管的第二极与第四节点电连接；
    所述第十一晶体管的栅极与所述第三节点电连接，所述第十一晶体管的第一极与所述第一电压端电连接，所述第十一晶体管的第二极所述第四节点电连接；
    所述第十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第十二晶体管的第一极与所述第四节点电连接，所述第十二晶体管的第二极与第五节点电连接；
    所述第十三晶体管的栅极与所述第三节点电连接，所述第十三晶体管的第一极与所述第五节点电连接，所述第十三晶体管的第二极与第二电压端电连接；
    所述第十晶体管和所述第十一晶体管为p型晶体管，所述第十二晶体管和所述第十三晶体管为n型晶体管。
  13. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述输出电路包括第十四晶体管和第十五晶体管；
    所述第十四晶体管的栅极与第四节点电连接，所述第十四晶体管的第一极与第一电压端电连接，所述第十四晶体管的第二极与输出驱动端电连接；
    所述第十五晶体管的栅极与所述第四节点电连接，所述第十五晶体管的第一极与所述输出驱动端电连接，所述第十五晶体管的第二极与第二电压端电连接。
  14. 如权利要求1至6中任一权利要求所述的驱动电路，其中，所述驱动信号生成电路包括第一控制电路、第二控制电路、第三反相器和第二初始化电路；
    所述第一控制电路分别与第一时钟信号端、第二时钟信号端、第N-1级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号端提供的第一时钟信号和所述第二时钟信号端提供的第二时钟信号的控制下，对所述第N-1 级驱动信号输出端提供的第N-1驱动信号进行移位并反相，得到并通过所述第六节点输出反相后的信号；
    所述第二控制电路分别与所述第一时钟信号端、所述第二时钟信号端、第N级驱动信号输出端和第六节点电连接，用于在所述第一时钟信号和所述第二时钟信号的控制下，对所述第N级驱动信号输出端提供的第N级驱动信号进行反相，得到并通过所述第六节点输出反相后的信号；
    所述第三反相器分别与所述第六节点和所述第N级驱动信号输出端电连接，用于对所述第六节点的电位进行反相，并通过所述第N级驱动信号输出端输出反相后的信号；
    所述第二初始化电路分别与初始控制端、第一电压端和所述第N级驱动信号输出端电连接，用于在所述初始控制端提供的初始控制信号的控制下，控制所述第N级驱动信号输出端与所述第一电压端之间连通。
  15. 如权利要求14所述的驱动电路，其中，所述第一控制电路包括第十六晶体管、第十七晶体管、第十八晶体管和第十九晶体管；
    所述第十六晶体管的栅极与所述第二时钟信号端电连接，所述第十六晶体管的第一极与所述第一电压端电连接，所述第十六晶体管的第二极与所述第十七晶体管的第一极电连接；
    所述第十七晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十七晶体管的第二极与所述第六节点电连接；
    所述第十八晶体管的栅极与所述第N-1级驱动信号输出端电连接，所述第十八晶体管的第一极与所述第六节点电连接，所述第十八晶体管的第二极与所述第十九晶体管的第一极电连接；
    所述第十九晶体管的栅极与所述第一时钟信号端电连接，所述第十九晶体管的第二极与第二电压端电连接；
    所述第十六晶体管和所述第十七晶体管为p型晶体管，所述第十八晶体管和所述第十九晶体管为n型晶体管。
  16. 如权利要求14所述的驱动电路，其中，所述第二控制电路包括第二十晶体管、第二十一晶体管、第二十二晶体管和第二十三晶体管；
    所述第二十晶体管的栅极与所述第一时钟信号端电连接，所述第二十晶 体管的第一极与第一电压端电连接，所述第二十晶体管的第二极与所述第二十一晶体管的第一极电连接；
    所述第二十一晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十一晶体管的第二极与所述第六节点电连接；
    所述第二十二晶体管的栅极与所述第N级驱动信号输出端电连接，所述第二十二晶体管的第一极与所述第六节点电连接，所述第二十二晶体管的第二极与所述第二十三晶体管的第一极电连接；
    所述第二十三晶体管的栅极与所述第二时钟信号端电连接，所述第二十三晶体管的第二极与第二电压端电连接；
    所述第二十晶体管和所述第二十一晶体管为p型晶体管，所述第二十二晶体管和所述第二十三晶体管为n型晶体管。
  17. 如权利要求14所述的驱动电路，其中，所述第三反相器包括第二十四晶体管和第二十五晶体管；所述第二初始化电路包括第二十六晶体管；
    所述第二十四晶体管的栅极与所述第六节点电连接，所述第二十四晶体管的第一极与所述第一电压端电连接，所述第二十四晶体管的第二极与所述第二十五晶体管的第一极电连接；
    所述第二十五晶体管的栅极与所述第六节点电连接，所述第二十五晶体管的第二极与第二电压端电连接；
    所述第二十四晶体管为p型晶体管，所述第二十五晶体管为n型晶体管；
    所述第二十六晶体管的栅极与所述初始控制端电连接，所述第二十六晶体管的第一极与所述第一电压端电连接，所述第二十六晶体管的第二极与所述第N级驱动信号输出端电连接。
  18. 一种驱动方法，应用于如权利要求1至17中任一权利要求所述的驱动电路，所述驱动方法包括：
    驱动信号生成电路对第N-1级驱动信号进行移位操作，得到并通过第N级驱动信号输出端输出第N级驱动信号；
    选通电路在选通控制信号的控制下，控制将选通输入端提供的选通输入信号写入第一节点；
    输出控制电路对所述第N级驱动信号和所述输出控制电路的第二端的电 位进行与非操作，得到第一输出信号；
    输出电路用于对所述第一输出信号进行反相，得到并通过输出驱动端提供输出驱动信号。
  19. 一种驱动模组，包括多级如权利要求1至17中任一权利要求所述的驱动电路；
    第N级驱动电路与第N-1级驱动电路包括的驱动信号输出端电连接；N为正整数。
  20. 一种显示装置，包括如权利要求19所述的驱动模组。
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