WO2024214131A1 - 電力増幅器 - Google Patents

電力増幅器 Download PDF

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Publication number
WO2024214131A1
WO2024214131A1 PCT/JP2023/014490 JP2023014490W WO2024214131A1 WO 2024214131 A1 WO2024214131 A1 WO 2024214131A1 JP 2023014490 W JP2023014490 W JP 2023014490W WO 2024214131 A1 WO2024214131 A1 WO 2024214131A1
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Prior art keywords
amplifier
terminal
internal
input terminal
output
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PCT/JP2023/014490
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English (en)
French (fr)
Japanese (ja)
Inventor
勝也 嘉藤
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三菱電機株式会社
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Priority to JP2025513503A priority Critical patent/JPWO2024214131A1/ja
Priority to PCT/JP2023/014490 priority patent/WO2024214131A1/ja
Publication of WO2024214131A1 publication Critical patent/WO2024214131A1/ja

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics

Definitions

  • This disclosure relates to a power amplifier for wireless communication that amplifies power at high frequencies.
  • it relates to a power amplifier that employs an LMBA circuit.
  • Figure 5 shows the circuit described in Non-Patent Document 1, and uses this to explain the operation of the LMBA.
  • a signal input from outside to the input terminal 502 is distributed by the distribution circuit 60 to the carrier amplifier 510 and the balance amplifier 520.
  • the carrier amplifier 510 is composed of an input matching circuit 11 , an active element 12 biased to class AB, and an output matching circuit 13 , and its output is connected to a coupling terminal P 1 of a hybrid coupler 41 .
  • the balanced amplifier 520 two amplifiers, namely, an amplifier 20 composed of an input matching circuit 21, an active element 22 biased to class C, and an output matching circuit 33, and an amplifier 30 composed of an input matching circuit 31, an active element 32 biased to class C, and an output matching circuit 33, are combined in parallel by hybrid couplers 40 and 41.
  • the output matching circuits 23 and 33 are designed so that the impedance when looking at the output matching circuits 23 and 33 from the hybrid coupler 41 is open.
  • the hybrid couplers 40 and 41 are designed so that reflections are minimized for a 50 ⁇ load.
  • the passing phase of the path from the input terminal 502 through the balance amplifier 520 to the output terminal 504 is set to ⁇ 1
  • the passing phase of the path from the input terminal 502 through the carrier amplifier 510 to the output terminal 504 is set to ⁇ 2.
  • the electrical length of the phase adjustment circuit 530 connected between the distribution circuit 60 and the balance amplifier 520 is designed so that ⁇ 1 and ⁇ 2 are the same.
  • Ic and Ib respectively indicate the currents supplied to the hybrid coupler 41 from the carrier amplifier and the balanced amplifier.
  • the impedance seen from P1 of the hybrid coupler 41 is 50 ⁇ , the same as when a large signal is input, and the impedance seen from P2 and P3 of the hybrid coupler 41 is both infinity, so the balance amplifier biased to class C does not operate and only the carrier amplifier operates, resulting in high efficiency at low output.
  • power amplifiers for wireless base stations are generally required to be small, they are generally in the form of a module PA in which the circuits are integrated in a single package.
  • this requires the use of an expensive package structure, which increases costs.
  • LMBAs generally have large circuit size, and when modularized, the balance amplifier and carrier amplifier are all integrated on the same PKG, making cost reduction an issue.
  • One possible solution to this problem is to use different packages for the main amplifier and the peak amplifier, as described in prior art 1. Specifically, to reduce costs, a package with low thermal resistance could be used for the carrier amplifier module, and a package with high thermal resistance but low cost could be used for the balanced amplifier module.
  • the amplifier that requires a package with low thermal resistance is a carrier amplifier, so in order to reduce the package area, it is optimal from a cost perspective to divide it into two modules: one that integrates only the carrier amplifier, and one that integrates the other parts, the distribution circuit and balance amplifier.
  • the present disclosure aims to provide a power amplifier using an LMBA circuit that is composed of two module amplifiers, is high performance, low cost, and allows easy connection between modules.
  • the power amplifier disclosed herein is a power amplifier that includes a carrier amplifier module, a balanced amplifier module, a first delay line, and a second delay line.
  • the carrier amplifier module has a first internal output terminal and a second internal output terminal, an input terminal connected to the input of the power amplifier, a distribution circuit, and a first amplifier mounted in a package.
  • the distribution circuit has an input connected to the input terminal, one output connected to the input of the first amplifier, and the other output connected to the first internal output terminal.
  • the first amplifier has a transistor for power amplification mounted in a package, and an output connected to the second internal output terminal.
  • the balanced amplifier module has a first internal input terminal and a second internal input terminal, an output terminal connected to the output of the power amplifier, a second amplifier and a third amplifier mounted in a package, and a first hybrid coupler and a second hybrid coupler.
  • the first hybrid coupler has a first terminal connected to the first internal input terminal, a second terminal connected to the input of the second amplifier, a third terminal connected to the input of the third amplifier, and a fourth terminal that is terminated.
  • the second hybrid coupler has a first terminal connected to the second internal input terminal, a second terminal connected to the output of the second amplifier, a third terminal connected to the output of the third amplifier, and a fourth terminal connected to the output terminal.
  • Each of the second amplifier and the third amplifier includes a power amplifying transistor mounted in a package.
  • the first delay line is connected to the first internal output terminal and the first internal input terminal
  • the second delay line is connected to the second internal output terminal and the second internal input terminal.
  • the power amplifier according to the present disclosure is characterized in that the thermal resistance from the transistor in the first amplifier to the back surface of the package is smaller than the thermal resistance from the transistor in the second amplifier and the third amplifier to the back surface of the package. Moreover, the sum of the electrical length from the input terminal to the first internal output terminal and the electrical length from the first internal input terminal to the output terminal is equal to the sum of the electrical length from the input terminal to the second internal output terminal and the electrical length from the second internal input terminal to the output terminal, and further the electrical lengths of the first delay line and the second delay line are equal.
  • This disclosure makes it possible to provide a power amplifier that uses a LMBA circuit that is high-performance, low-cost, and easy to connect between modules.
  • FIG. 1 is a diagram illustrating a power amplifier 100 according to a first embodiment. 5 is a diagram showing calculation results of the efficiency of the power amplifier 100 according to the first embodiment.
  • FIG. FIG. 10 is a diagram illustrating a power amplifier 200 according to a second embodiment.
  • FIG. 11 is a plan view of a power amplifier 100 according to a third embodiment.
  • FIG. 1 is a diagram showing a circuit described in Non-Patent Document 1.
  • FIG. 6 is a diagram illustrating a power amplifier 600 according to a first comparative example.
  • FIG. 7 is a diagram illustrating a power amplifier 700 according to a second comparative example.
  • FIG. 11 is a diagram illustrating a power amplifier 800 according to a third comparative example.
  • Embodiment 1 A power amplifier according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.
  • the power amplifier 100 is an LMBA including a balanced amplifier module 4, a carrier amplifier module 5, and a first delay line 80 and a second delay line 81 on a printed circuit board (PCB).
  • the power amplifier 100 has an input terminal 102 and an output terminal 104 .
  • the carrier amplifier module 5 has an input terminal 2, a first internal output terminal 90, and a second internal output terminal 92.
  • the carrier amplifier module 5 also includes a first amplifier 10, a distribution circuit 60, and a package 55 (not shown).
  • the first amplifier 10 is a carrier amplifier.
  • the distribution circuit 60 and the first amplifier 10 are integrated and mounted in the package 55.
  • the input terminal 2 is connected to an input terminal 102 of the power amplifier 100.
  • the input of the distribution circuit 60 is connected to the input terminal 2.
  • One output of the distribution circuit 60 is connected to a first internal output terminal 90, and the other output is connected to the input side of the first amplifier 10.
  • the distribution circuit 60 distributes a signal input to the input terminal 2 to the first internal output terminal 90 and the first amplifier 10.
  • the output side of the first amplifier 10 is connected to a second internal output terminal 92.
  • the first amplifier 10 is a microwave power amplifier that includes an active element 12, an input matching circuit 11 connected to the input side of the active element 12, and an output matching circuit 13 connected to the output side of the active element 12.
  • the input matching circuit 11 and the output matching circuit 13 are matching circuits that match the active element 12 with external impedance.
  • the active element 12 is biased to class AB. Note that bias circuits and the like are not shown in FIG. 1.
  • the signal input from the distribution circuit 60 to the first amplifier 10 is transmitted to the active element 12 via the input matching circuit 11, amplified by the active element 12, and output to the second internal output terminal 92 via the output matching circuit 13.
  • the balanced amplifier module 4 includes a package 44 (not shown), a hybrid coupler 40 which is a first hybrid coupler mounted in the package 44 , a hybrid coupler 41 which is a second hybrid coupler, a second amplifier 20 , a third amplifier 30 , and a termination resistor 50 .
  • the balanced amplifier module 4 includes a first internal input terminal 91 and a second internal input terminal 93 to which power is input from the carrier amplifier module 5, and an output terminal 3 to which amplified power is output.
  • the port P1 of the hybrid coupler 40 is connected to the first internal input terminal 91.
  • the port P1 of the hybrid coupler 41 is connected to the second internal input terminal 93.
  • the output terminal 3 is connected to an output terminal 104 of the power amplifier 100.
  • the inputs of the second amplifier 20 and the third amplifier 30 are connected to ports P2 and P3 of the hybrid coupler 40, respectively, and the outputs of the second amplifier 20 and the third amplifier 30 are connected to ports P2 and P3 of the hybrid coupler 41, respectively, and the two amplifiers are combined in parallel.
  • the port P4 of the hybrid coupler 40 is terminated by a terminating resistor 50.
  • the port P4 of the hybrid coupler 41 is connected to the output terminal 3.
  • the output matching circuits 23 and 33 are designed so that the impedance when looking at the output matching circuits 23 and 33 from the hybrid coupler 41 is open.
  • the hybrid couplers 40 and 41 are designed so that reflection is minimized for a 50 ⁇ load.
  • the hybrid couplers 40 and 41 may be constructed of microstrip lines formed on a resin substrate, a GaAs substrate, or a Si substrate, or may be constructed using a lumped constant circuit.
  • Hybrid couplers 40 and 41 are typical 90-degree hybrid circuits with four input/output ports, and are, for example, branch line couplers made up of microstrip lines.
  • These four input/output ports are the first port P1, the second port P2, the third port P3, and the fourth port P4.
  • an input signal is input to port P1
  • the input signal is equally distributed and output to ports P2 and P3, and no signal is output from port P4.
  • the phase of the output signal from port P2 lags behind the input signal by 90°
  • the phase of the output signal from port P3 lags behind the input signal by 180°.
  • the power value of each output signal is half the power value of the input signal.
  • the second amplifier 20 is a microwave power amplifier that includes an active element 22, an input matching circuit 21 connected to the input of the active element 22, and an output matching circuit 23 connected to the output of the active element 22.
  • the input matching circuit 21 and the output matching circuit 23 are matching circuits that match the impedance of the active element 22 with the outside.
  • the active element 22 is biased to class C. Bias circuits and the like are not shown in Figure 1.
  • the signal input to the input matching circuit 21 from port P2 of the hybrid coupler 40 is amplified by the active element 22 and output to port P2 of the hybrid coupler 41 via the output matching circuit 23.
  • the third amplifier 30 is a microwave power amplifier that includes an active element 32, an input matching circuit 31 connected to the input of the active element 32, and an output matching circuit 33 connected to the output of the active element 32.
  • the input matching circuit 31 and the output matching circuit 33 are matching circuits that match the active element 32 with external impedance.
  • the active element 32 is biased to class C.
  • the bias circuit is not shown in Figure 1.
  • the signal input to the input matching circuit 31 from port P3 of the hybrid coupler 40 is amplified by the active element 32 and output to port P3 of the hybrid coupler 41 via the output matching circuit 33.
  • the active elements 12, 22, and 32 are, for example, GaN (Gallium Nitride)-based HEMTs (High Electron Mobility Transistors) formed on a SiC (Silicon Carbide) substrate, but may also be transistors using other compound semiconductors or silicon-based LD-MOSFETs.
  • the input matching circuits 11, 21, 31 and the output matching circuits 13, 23, 33 may be circuits integrated on an inexpensive semiconductor substrate such as gallium arsenide (GaAs) or silicon (Si), or circuits configured with small chip inductors and chip capacitors arranged on a resin substrate, etc.
  • the active elements 22 and 32 may be biased to class B or deep class AB.
  • the package 55 constituting the carrier amplifier module 5 and the package 44 constituting the balanced amplifier module 4 have different structures.
  • the structure of the package 55 is selected so that the thermal resistance from the rear surface of the active element 12 of the carrier amplifier module 5 to the rear surface of the package 55 is lower than the thermal resistance from the rear surface of the active element 22 and active element 32 of the balanced amplifier module 4 to the rear surface of the package 44.
  • the structure of the package 44 of the balanced amplifier module 4 is, for example, a structure using a multi-layer board made of FR4 material and having a board thickness of 200 to 500 ⁇ m.
  • the back sides of the active elements 22 and 32 which are transistor chips, are mounted on the front side of the multi-layer board using solder or conductive adhesive.
  • thermal vias may be provided that penetrate from the front side to the back side of the multi-layer board corresponding to the back sides of the active elements 22 and 32, or that are thermally connected. This structure allows the package to be constructed inexpensively, but it is generally difficult to sufficiently reduce the thermal resistance.
  • the structure of package 55 of carrier amplifier module 5 is, for example, the same as package 44, a multi-layer board with a board thickness of 200 to 500 ⁇ m and made of FR4 material, but the multi-layer board is hollowed out at the location where active element 12, which is a transistor chip, is mounted, and a heat sink made of a thin metal plate is attached to the back surface of package 55, and the back surface of active element 12 is directly die-bonded to the heat sink.
  • the back surface of the heat sink becomes the back surface of package 55.
  • This type of structure is more expensive than package 44, but it can reduce the thermal resistance from the back surface of active element 12 to the back surface of package 55.
  • a first internal output terminal 90 and a first internal input terminal 91 are connected by a first delay line 80.
  • a second internal output terminal 92 and a second internal input terminal 93 are connected by a second delay line 81.
  • the first delay line 80 and the second delay line 81 each have a characteristic impedance of 50 ⁇ , and are provided so that both have the same electrical length.
  • the absolute value of the electrical length may be any value.
  • the first delay line 80 and the second delay line 81 are configured as microstrip lines formed on a PCB, but may be of any other form, such as a coplanar line, a slot line, or a coaxial line.
  • the sum of the electrical length from the input terminal 2 to the first internal output terminal 90 and the electrical length from the first internal input terminal 91 to the output terminal 3 is defined as ⁇ _b.
  • the sum of the electrical length from the input terminal 2 to the second internal output terminal 92 and the electrical length from the second internal input terminal 93 to the output terminal 3 is defined as ⁇ _c.
  • Figure 2 shows the calculation results of the efficiency of the power amplifier 100 according to the first embodiment.
  • Figure 2 shows the calculation results of the efficiency of the power amplifier 100 when the electrical lengths of the delay lines 80 and 81 are the same and are changed in 10 degree steps in the range of 0 to 30 degrees.
  • the horizontal axis of Figure 2 is the output power
  • the vertical axis of Figure 2 is the power added efficiency (PAE). Since the results are almost overlapping, it can be seen that in the power amplifier 100, if the electrical lengths of the two delay lines 80 and 81 are the same, the PAE remains almost unchanged even if the absolute value of the electrical length is changed, and the characteristics do not deteriorate. In addition, since the absolute value of the electrical length does not matter, connection between modules is easy.
  • the power amplifier 100 in the first embodiment of the present disclosure is a power amplifier including a carrier amplifier module 5, a balanced amplifier module 4, a first delay line 80, and a second delay line 81.
  • the power amplifier 100 is configured as follows.
  • the carrier amplifier module 5 has an input terminal 2 , a first internal output terminal 90 and a second internal output terminal 92 , and is provided with a distribution circuit 60 and a first amplifier 10 mounted in a package 55 .
  • the input terminal 2 is connected to the input terminal of the power amplifier 100
  • the distribution circuit 60 has an input connected to the input terminal 2 and an output connected to the input of the first amplifier 10 and a first internal output terminal 90, respectively
  • the first amplifier 10 has an active element 12 for power amplification biased to class AB and an output connected to a second internal output terminal 92.
  • the balanced amplifier module 4 has a first internal input terminal 91, a second internal input terminal 93, and an output terminal 3, and is equipped with a second amplifier 20 and a third amplifier 30 mounted in a package 44, as well as a hybrid coupler 40 which is a first hybrid coupler, and a hybrid coupler 41 which is a second hybrid coupler.
  • the output terminal 3 is connected to the output terminal 3 of the power amplifier 100.
  • the first hybrid coupler 40 has a first terminal P1 connected to the first internal input terminal 91, a second terminal P2 connected to the input of the second amplifier 20, a third terminal P3 connected to the input of the third amplifier 30, and a fourth terminal P4 that is terminated.
  • the second hybrid coupler 41 has a first terminal P1 connected to the second internal input terminal 93, a second terminal P2 connected to the output of the second amplifier 20, a third terminal P3 connected to the output of the third amplifier 30, and a fourth terminal P4 connected to the output terminal 3.
  • the second amplifier 20 and the third amplifier 30 each have an active element 22 and 32 for power amplification biased in class C and mounted in a package 44 .
  • the first delay line 80 is connected to a first internal output terminal 90 and a first internal input terminal 91
  • the second delay line 81 is connected to a second internal output terminal 92 and a second internal input terminal 93 .
  • the thermal resistance from the active element 12 of the first amplifier 10 to the rear surface of the package 55 is smaller than the thermal resistance from the active element 22 of the second amplifier 20 and the active element 32 of the third amplifier 30 to the rear surface of the package 44 .
  • the sum of the electrical length from the input terminal 2 to the first internal output terminal 90 and the electrical length from the first internal input terminal 91 to the output terminal 3 is equal to the sum of the electrical length from the input terminal 2 to the second internal output terminal 92 and the electrical length from the second internal input terminal 93 to the output terminal 3.
  • the electrical lengths of the first delay line 80 and the second delay line 81 are equal.
  • an inexpensive package 44 is used for the balanced amplifier module 4, and the distribution circuit 60 is integrated into the carrier amplifier module 5. This has the effect of reducing costs because the package structure can be optimized for the carrier amplifier and the balanced amplifier, respectively, with respect to cost.
  • the electrical length of the path passing through the first amplifier 10 is set to be the same as the electrical length of the path passing through the second amplifier 20 and the third amplifier 30, and the electrical lengths of the two delay lines 80 and 81 connecting the balanced amplifier module 4 and the carrier amplifier module 5 are set to be the same.
  • the delay in the two delay lines 80 and 81 occurs equally regardless of the absolute value of their electrical lengths, so the delays occurring in the path through the balanced amplifier and the path through the carrier amplifier cancel each other out, and the phase difference between the paths becomes zero, resulting in no degradation of high frequency characteristics.
  • the two modules can be easily connected, there is a degree of freedom in the arrangement of the modules, and even when bypass capacitors or the like are arranged around the modules, there are advantages that they can be used without having to worry about the spacing between the modules.
  • the power amplifier 600 has a configuration in which a carrier amplifier module 5 that integrates only a carrier amplifier and a balanced amplifier module 4 that integrates a distribution circuit 60 and a balanced amplifier are connected by delay lines 85 and 86 on a PCB.
  • a difference occurs between ⁇ 1 and ⁇ 2 because the passing phase ⁇ 2 on the carrier amplifier side is delayed by the sum ( ⁇ m1+ ⁇ m2) of the electrical length ⁇ m1 of the delay line 85 and the electrical length ⁇ m2 of the delay line 86 relative to the passing phase ⁇ 1 on the balance amplifier side.
  • the shift in the passing phase is problematic because it generates a composite loss and significantly deteriorates the high frequency characteristics of the power amplifier.
  • FIG. 7 is a diagram for explaining a power amplifier 700 according to Comparative Example 2. Unlike Comparative Example 1, in the power amplifier 700, a delay line 710 for canceling the phase delay of the delay lines 85 and 86 is provided in the balanced amplifier module 4. However, in this case, there is a problem that the circuit size of the balanced amplifier module 4 becomes large.
  • FIG. 8 is a diagram illustrating a power amplifier 800 according to Comparative Example 3. Unlike Comparative Examples 1 and 2, in the power amplifier 800, the balanced amplifier module 4 and the carrier amplifier module 5 are connected by a phase lead circuit 810 and a delay line 86. Here, the phase lead circuit 810 is designed to have a leading phase so as to cancel out the delay caused by the delay line 86.
  • this method requires the design of a phase-lead circuit according to the length of the delay line, and the frequency band in which the phase can be offset is also limited, making it complicated and raising concerns about degradation of high-frequency characteristics.
  • the characteristic impedance of the hybrid couplers 40 and 41 does not have to be 50 ⁇ , and may be any impedance Zc, Zd. In this case, the same effect as described above can be obtained by setting the characteristic impedance of the hybrid coupler 40 and the delay line 80 to Zc, and the characteristic impedance of the hybrid coupler 41 and the delay line 81 to Zd. Zc and Zd may be the same or different.
  • Embodiment 2. 3 is a diagram for explaining a power amplifier 200 according to embodiment 2.
  • the difference from embodiment 1 is that the output matching circuit 13 of the first amplifier 10 in the power amplifier 100 is divided into an output matching circuit 210 and an output matching circuit 212, and the output matching circuit 210 is arranged in the carrier amplifier module 5 and the output matching circuit 212 is arranged in the balanced amplifier module 4.
  • the impedance seen from the second internal input terminal 93 towards the balanced amplifier module 4 is Zm.
  • the output matching circuit 212 is configured so that Zm has only real components and no imaginary components, or the imaginary components are sufficiently small compared to the real components that in practical terms it can be regarded as having only real components.
  • the characteristic impedance of the delay line 81 is set to Zm. Explanation of other parts will be omitted.
  • the package structure can be optimized for the cost of each of the carrier amplifier module and the balanced amplifier module, resulting in low costs, easy connection between modules, no degradation of high frequency characteristics, and high performance.
  • a part of the output matching circuit of the first amplifier 10 that was implemented in the carrier amplifier module 5 is integrated in the balanced amplifier module 4, which has the effect of reducing the size of the carrier amplifier module 5 that uses an expensive package, thereby achieving further cost reduction.
  • Embodiment 3 the planar layout of the balance amplifier module 4, the carrier amplifier module 5, the first internal output terminal 90, the second internal output terminal 92, the first internal input terminal, the second internal input terminal 93, the first delay line 80, and the second delay line 81 of the power amplifier 100 according to the first embodiment is limited. The rest is the same as in the first embodiment.
  • FIG. 4 is a plan view of the power amplifier 100 according to the third embodiment, showing the arrangement of the balanced amplifier module 4, the carrier amplifier module 5, and the delay lines 80 and 81 as viewed from above.
  • the shapes and arrangement of the electrode pads (terminals) arranged on the backsides of the balanced amplifier module 4 and the carrier amplifier module 5 are shown by dashed lines as seen through from above.
  • the ground terminal 120 of the balance amplifier module 4 and the ground terminal 122 of the carrier amplifier module 5 are indicated by dashed rectangles, and signal terminals including the first internal output terminal 90, the second internal output terminal 92, the first internal input terminal 91, and the second internal input terminal 93 are indicated by dashed squares.
  • the microstrip line 112 connects the input terminal 2 to the input terminal 102 (not shown), and the microstrip line 112 connects the output terminal 3 to the output terminal 104 (not shown).
  • signal terminals including a first internal input terminal 91 and a second internal input terminal 93 are arranged surrounding a ground terminal 120.
  • the first internal input terminal 91 and the second internal input terminal 93 are arranged along the same side 124 of the balanced amplifier module 4, which has a rectangular external shape.
  • signal terminals including a first internal output terminal 90 and a second internal output terminal 92 are arranged surrounding a ground terminal 122.
  • the first internal output terminal 90 and the second internal output terminal 92 are arranged along the same side 126 of the carrier amplifier module 5, which has a rectangular outer shape.
  • the balance amplifier module 4 and the carrier amplifier module 5 are positioned directly opposite each other so that sides 124 and 126 are parallel to each other, and so that the first internal input terminal 91 faces the first internal output terminal 90, and the second internal input terminal 93 faces the second internal output terminal 92.
  • the first internal output terminal 90 and the first internal input terminal 91 are connected linearly by a delay line 80, and the second internal output terminal 92 and the second internal input terminal 93 are connected linearly by a delay line 81, i.e., connected over the shortest distance. It is desirable that the spacing between the first internal input terminal 91 and the first internal output terminal 90 is the same as the spacing between the second internal input terminal 93 and the second internal output terminal 92. Explanation of other parts is omitted.
  • the power amplifier 100 according to the third embodiment thus configured, like the power amplifier 100 according to the first embodiment, naturally has the advantage of being able to reduce costs by optimizing the package structure for the carrier amplifier module and the balanced amplifier module in terms of cost, and also has the advantage of being easy to connect between modules, not deteriorating the high frequency characteristics, and providing high performance.
  • the positions of the balanced amplifier module 4, the carrier amplifier module 5, the first internal output terminal 90, the second internal output terminal 92, the first internal input terminal, and the second internal input terminal 93 are limited as described above.
  • the electrical lengths of the first delay line 80 and the second delay line 81 can be made the same, which has the effect of making it easier to connect modules to each other.
  • the power amplifier 100 has been described as an example, but the shapes and arrangements of the modules, pads (terminals), etc. in the third embodiment may also be applied to the power amplifier 200.
  • the present disclosure is not limited to the above-described embodiments, but includes various modifications.
  • the above-described embodiments are described in detail to clearly explain the present disclosure, and the present disclosure is not necessarily limited to those including all of the described configurations.
  • it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment and it is also possible to add the configuration of another embodiment to the configuration of one embodiment.

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PCT/JP2023/014490 2023-04-10 2023-04-10 電力増幅器 WO2024214131A1 (ja)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019092009A (ja) * 2017-11-13 2019-06-13 住友電気工業株式会社 半導体増幅素子及び半導体増幅装置
WO2022176947A1 (ja) * 2021-02-18 2022-08-25 ヌヴォトンテクノロジージャパン株式会社 高周波電力増幅装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019092009A (ja) * 2017-11-13 2019-06-13 住友電気工業株式会社 半導体増幅素子及び半導体増幅装置
WO2022176947A1 (ja) * 2021-02-18 2022-08-25 ヌヴォトンテクノロジージャパン株式会社 高周波電力増幅装置

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