WO2024212232A1 - 一种基于存算一体架构的用于手写数字识别的全模拟电路系统 - Google Patents

一种基于存算一体架构的用于手写数字识别的全模拟电路系统 Download PDF

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WO2024212232A1
WO2024212232A1 PCT/CN2023/088451 CN2023088451W WO2024212232A1 WO 2024212232 A1 WO2024212232 A1 WO 2024212232A1 CN 2023088451 W CN2023088451 W CN 2023088451W WO 2024212232 A1 WO2024212232 A1 WO 2024212232A1
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circuit
voltage
analog
voltages
current
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陈冰
叶佳宝
崔学成
王万年
赵家艺
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Zhejiang University
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Zhejiang University
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/048—Activation functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means

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  • the present invention relates to the technical field of electronic information, integrated circuits and artificial neural networks, and in particular to a full analog circuit system for handwritten digit recognition based on a storage-computing integrated architecture.
  • Power consumption wall refers to the data transmission involved in the process of CPU executing instructions.
  • the CPU needs to read data from the memory and then write the calculation results back to the memory.
  • the transmission of data consumes a lot of energy.
  • the CPU frequency is getting higher and higher, the amount of data transmission is also increasing, resulting in higher power consumption, thus limiting the performance of the entire computing system.
  • the new neural network hardware circuit systems based on the storage-computing integrated architecture are all based on the combination of digital circuits and analog circuits, with low integration, slow response speed, high power consumption, and it is difficult to further improve the performance of the system. Therefore, it is urgent to research and develop a new generation of fully analog neural network systems based on the storage-computing integrated architecture.
  • the purpose of the present invention is to propose a fully analog circuit system for handwritten digit recognition based on a storage-computing integrated architecture.
  • the system is completely implemented by analog circuits based on a storage-computing integrated architecture, which can eliminate the traditional
  • the von Neumann architecture of the present invention solves the two problems of "storage wall” and "power consumption wall” that seriously limit the performance of neural networks, and does not require the assistance of any digital modules, and can realize ultra-low latency recognition of handwritten digit recognition tasks by the neural network hardware system.
  • the existing scheme based on the combination of digital circuits and analog circuits has an operating speed of about 1 millisecond, an energy consumption of about 4W, low integration, and cannot be fully integrated on a circuit board.
  • the system proposed in the present invention has an operating speed of about 0.01 milliseconds, an energy consumption of about 0.5W, a high integration, and can be fully integrated on a circuit board. Therefore, compared with the existing schemes, the present invention has the advantages of fast running speed, low energy consumption, and high integration.
  • the present invention has a very broad application prospect in the research field of new neural network hardware systems based on a storage and computing integrated architecture, and is expected to provide a feasible non-von Neumann hardware solution for deep neural networks and edge computing, bringing hope to the future scientific and technological revolution.
  • a full analog circuit system for handwritten digit recognition based on a storage-computation integrated architecture includes a first analog circuit and a second analog circuit, wherein the first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of m columns and 2n rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit;
  • the second analog circuit is composed of the following circuit modules: a second resistor array with a scale of n columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit;
  • the input of the full analog circuit system is m analog voltages, which are generated by an external microcontroller with a touch capacitive screen.
  • the input driving circuit inputs the m analog voltages into a first resistor array with a scale of m columns and 2n rows; the conductance of the first resistor array with m columns and 2n rows is multiplied by the input analog voltage, and a corresponding current value is obtained on each resistor.
  • the first activation function circuit performs nonlinear activation on the n analog voltages, and maps them to a voltage range of 0V-1V to generate n voltages;
  • the conductance of the second resistor array with a size of n columns and 20 rows is multiplied by the n-way voltage generated by the first activation function circuit, and a corresponding current value is obtained on each resistor. All current values on each row are accumulated and The output is at the end of the row; the second current-voltage conversion circuit converts the current value outputted in each row into a voltage value, and performs amplification processing to obtain 20 voltage values, which are recorded as U1 , U2 ... U20 ; the second subtraction circuit performs subtraction difference processing on the first 10 voltage values and the last 10 voltage values of the 20 voltage values to generate 10 analog voltages, U1 ', U2 '...
  • the second activation function circuit performs nonlinear activation on the 10 analog voltages, and maps them to the voltage range of 0V-1V to generate 10 voltages;
  • the voltage comparison circuit compares the 10 voltages outputted by the second activation function circuit with the reference voltage 0.5V respectively, and each voltage greater than 0.5V outputs a high level to the corresponding digital tube, and the number of the digital tube is 10, which respectively corresponds to the 10 voltages and the ten digits from 0 to 9, thereby lighting up the corresponding digits of the road to complete the handwritten digit recognition function.
  • the input drive circuit in the circuit module is composed of a non-inverting MOSFET driver chip, which converts m 3.3V voltage signals generated by an external microcontroller with a touch capacitor screen into 5V voltage signals, and increases the driving load capacity of each voltage to 100mA.
  • the current-to-voltage conversion circuit includes a sampling resistor and an integrated operational amplifier.
  • the sampling resistor has a resistance of 1 ⁇ and converts current into voltage.
  • the integrated operational amplifier is used to construct a common-mode amplifier to amplify the voltage obtained by the sampling resistor.
  • the subtraction circuit in the circuit module includes an integrated operational amplifier for amplifying 2n voltage values V 1 , V 2 . . . V 2n .
  • the first activation function circuit and the second activation function circuit are respectively composed of three-stage amplifier circuits in cascade, the first amplifier circuit is composed of a biased in-phase operational amplifier, and the second and third amplifier circuits are composed of inverting operational amplifiers;
  • the voltage comparison circuit includes an integrated operational amplifier, and the voltage comparison circuit is a single-threshold voltage comparison circuit. When the voltage value input to the voltage comparison circuit is greater than 0.5V, the voltage comparison circuit outputs a high level.
  • the high level is 1V.
  • the beneficial effects of the present invention are as follows: compared with the traditional neural network hardware system, the present invention is completely implemented by analog circuits based on the storage-computing integrated architecture, which can eliminate the data handling problems caused by the traditional von Neumann architecture, and does not require the assistance of any digital modules, and can achieve ultra-low latency and accurate recognition.
  • the present invention has a very broad application prospect in the research field of new neural network hardware systems based on the storage-computing integrated architecture, and is expected to provide a feasible non-von Neumann hardware solution for deep neural networks and edge computing.
  • FIG1 is a schematic diagram of the circuit principle of the present invention.
  • FIG2 is a circuit diagram of an input drive circuit according to an example of the present invention.
  • FIG. 3 is a circuit diagram of a first current-to-voltage conversion circuit and a second current-to-voltage conversion circuit according to an embodiment of the present invention
  • FIG. 4 is a circuit diagram of a first subtraction circuit and a second subtraction circuit according to an example of the present invention
  • FIG. 5 is a circuit diagram of a first activation function circuit and a second activation function circuit of an example of the present invention
  • FIG. 6 is a circuit diagram of a voltage comparison circuit according to an example of the present invention.
  • the present invention provides a full analog circuit system for handwritten digit recognition based on a storage-computation integrated architecture.
  • the circuit principle schematic diagram of the system is shown in FIG1 , and includes a first analog circuit and a second analog circuit.
  • the first analog circuit is composed of the following circuit modules: an input drive circuit, a first resistor array with a scale of 49 columns and 20 rows, a first current-voltage conversion circuit, a first subtraction circuit, and a first activation function circuit;
  • the second analog circuit is composed of the following circuit modules: a second resistor array with a scale of 10 columns and 20 rows, a second current-voltage conversion circuit, a second subtraction circuit, a second activation function circuit, and a voltage comparison circuit.
  • the input of the full analog circuit system is 49 analog voltages, which are generated by an external microcontroller with a touch capacitive screen (the microcontroller used in this embodiment is an STM32F103ZET6 single-chip microcomputer, and the single-chip microcomputer is connected to a 4.3-inch capacitive touch screen as an input device for handwritten digits to collect handwritten digits. And converted into 49 analog voltages), the input drive circuit enhances the load capacity of 49 analog voltages to obtain 49 drive voltages.
  • the input drive circuit is composed of a non-inverting MOSFET driver chip, which converts 49 voltages of 3.3V generated by an external microcontroller with a touch capacitor screen into a 5V voltage, and increases the drive load capacity of each voltage to 100mA; it can be implemented using a dual-channel high-speed power MOSFET driver TC4427 chip, which has the advantages of high output current, wide power supply voltage, etc.
  • the circuit schematic is shown in Figure 3.
  • the input driving circuit inputs the driving voltage into the first resistor array with a scale of 49 columns and 20 rows.
  • the conductance of the first resistor array with 49 columns and 20 rows is multiplied by the input driving voltage, and a corresponding current value is obtained on each resistor. All current values on each row are accumulated and output at the end of the row;
  • the first current-voltage conversion circuit converts the current value outputted in each row into a voltage value, and amplifies it to obtain 20 voltage values, which are recorded as V 1 , V 2 ?? V 20 ;
  • the current-voltage conversion circuit is implemented by a sampling resistor and an integrated operational amplifier.
  • the sampling resistor has a resistance of 1 ⁇ .
  • the accumulated current in each row of the resistor array is converted into a voltage.
  • the integrated operational amplifier is used to construct a common-phase configuration amplifier to amplify the voltage obtained by the sampling resistor, and the amplification factor is 40 times; it can be implemented by using TI's OPA4317 series integrated operational amplifier, which has the characteristics of low offset, rail-to-rail output, high speed, and low noise. Its circuit schematic is shown in Figure 5.
  • the first activation function circuit performs nonlinear activation on the 10 analog voltages and maps them to the voltage range of 0V-1V to generate 10 voltages.
  • the first amplifier circuit is composed of an integrated operational amplifier with a single 5V power supply and rail-to-rail output, and the bias voltage is 2.5V and the amplification factor is 1; the OPA4350 series of TI can be used.
  • the first stage is realized by an integrated operational amplifier with single power supply, rail-to-rail output, high speed and low noise.
  • the second amplifier circuit is composed of an integrated operational amplifier with ⁇ 5V dual power supply, and the amplification factor is 0.2 times; it can be realized by TI's OPA2227 series integrated operational amplifier, which has the characteristics of dual power supply, wide power supply voltage range, high precision and low noise.
  • the third stage amplifier circuit is composed of an integrated operational amplifier with ⁇ 5V dual power supply, and the amplification factor is 1 times; it can be realized by TI's OPA2227 series integrated operational amplifier. Its circuit schematic is shown in Figure 7.
  • the conductance of the second resistor array with a scale of 10 columns and 20 rows is multiplied by the 10 voltages generated by the first activation function circuit, and a corresponding current value is obtained on each resistor. All current values on each row are accumulated and output at the end of the row; the second current-voltage conversion circuit converts the current value output from each row into a voltage value, and amplifies it by 50 times to obtain 20 voltage values, which are recorded as U1 , U2 ... U20 ; the second subtraction circuit performs subtraction difference processing on the first 10 voltage values and the last 10 voltage values of the 20 voltage values to generate 10 analog voltages, U1 ', U2 '...
  • the second activation function circuit performs nonlinear activation on the 10 analog voltages, maps them to the voltage range of 0V-1V to generate 10 voltages;
  • the voltage comparison circuit compares the 10 voltages output by the second activation function circuit with the reference voltage 0.5V respectively, and each voltage greater than 0.5V outputs a high level to the corresponding digital tube, the number of which is 10, corresponding to the 10 voltages and the ten digits 0-9, thereby lighting up the corresponding digits of the channel and completing the handwritten digit recognition function.
  • the voltage comparison circuit can be implemented using TI's OPA4317 series integrated operational amplifier, which has the characteristics of low offset, rail-to-rail output, high speed, and low noise. Its circuit schematic is shown in Figure 9.
  • the present invention realizes the recognition of handwritten digits.
  • the system is completely implemented by analog circuits based on the storage-computing integrated architecture, which can eliminate the data handling problems caused by the traditional von Neumann architecture and does not require the assistance of any digital modules. It can achieve ultra-low latency and accurate handwritten digit recognition.
  • the system has a very broad application prospect in the research field of new neural network hardware systems based on the storage-computing integrated architecture, and is expected to provide a feasible non-von Neumann hardware solution for deep neural networks and edge computing.

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Abstract

本发明公开了一种基于存算一体架构的用于手写数字识别的全模拟电路系统，包括第一模拟电路和第二模拟电路，所述第一模拟电路由以下电路模块组成：输入驱动电路、规模为m列2n行的第一电阻阵列、第一电流电压转换电路、第一减法电路、第一激活函数电路；所述第二模拟电路由以下电路模块组成：规模为n列20行的第二电阻阵列、第二电流电压转换电路、第二减法电路、第二激活函数电路、电压比较电路。该系统可以消除传统冯诺依曼架构所带来的数据搬运问题，并且不需要任何数字模块的辅助，实现超低延时的精准识别。该系统在新型神经网络硬件系统研究领域具有非常广阔的应用前景，有望为深度神经网络和边缘计算提供一个可行的非冯诺依曼硬件解决方案。

Description

一种基于存算一体架构的用于手写数字识别的全模拟电路系统 技术领域
本发明涉及电子信息、集成电路及人工神经网络技术领域，具体涉及一种基于存算一体架构的用于手写数字识别的全模拟电路系统。
背景技术
随着计算机与信息技术的迅速发展，人们对信息的传输速度和存储容量、电子器件和电路集成度的要求越来越高。当前，人工神经网络作为应用十分广泛的非线性网络，已经发展得非常成熟并取得了巨大的成功，已经在全世界范围内掀起了一场具有颠覆性质的智能化革命。但当下的人工神经网络大多都是在传统计算机上运行的，而传统计算机又是基于冯诺依曼架构来设计的，其中的计算单元和存储单元是分离的。这就会产生“存储墙”和“功耗墙”两个严重限制神经网络性能的问题。“存储墙”是指CPU和内存之间的速度不匹配，CPU的运算速度比内存读写速度快很多，而且随着CPU的发展，其速度的提升更快，但是内存的速度提升相对较慢，导致CPU在等待内存读写完成时浪费了很多时间，从而限制了整个运算系统的性能。“功耗墙”是指在CPU执行指令的过程中涉及到数据的传输，CPU需要从内存中读取数据，然后将计算结果写回内存。而数据的传输会消耗大量的能量，当CPU频率越来越高时，数据传输量也越来越大，导致功耗也越来越高，从而限制了整个运算系统的性能。
目前，基于存算一体架构的新型神经网络硬件电路系统都是基于数字电路和模拟电路相结合的方案，集成度低、响应速度慢，功耗高，很难进一步提高系统的性能。因此，研究和开发新一代基于存算一体架构的全模拟神经网络系统已经迫在眉睫。
发明内容
本发明的目的是提出一种基于存算一体架构的用于手写数字识别的全模拟电路系统，该系统完全由基于存算一体架构的模拟电路实现，可以消除由传统 的冯诺依曼架构带来的“存储墙”和“功耗墙”两个严重限制神经网络性能的问题，并且不需要任何数字模块的辅助，可以实现神经网络硬件系统对手写数字识别任务的超低延时识别。现有的基于数字电路和模拟电路相结合的方案运行速度大约为1毫秒，能耗大约为4W，集成度低，无法完全集成在一片电路板上。本发明提出的系统运行速度大约为0.01毫秒，能耗大约为0.5W，集成度高，可以完全集成在一片电路板上。因此，本发明与现有的方案相比具有运行速度快、能耗低、集成度高等优点。本发明在基于存算一体架构的新型神经网络硬件系统研究领域具有非常广阔的应用前景，有望为深度神经网络和边缘计算提供一个可行的非冯诺依曼硬件解决方案，给未来科技革命带来曙光。
本发明的目的是通过以下技术方式实现的：
一种基于存算一体架构的用于手写数字识别的全模拟电路系统，如图1，包括第一模拟电路和第二模拟电路，所述第一模拟电路由以下电路模块组成：输入驱动电路、规模为m列2n行的第一电阻阵列、第一电流电压转换电路、第一减法电路、第一激活函数电路；
所述第二模拟电路由以下电路模块组成：规模为n列20行的第二电阻阵列、第二电流电压转换电路、第二减法电路、第二激活函数电路、电压比较电路；
所述全模拟电路系统的输入是m个模拟电压，由外接的带触摸电容屏幕的微控制器产生，输入驱动电路将m个模拟电压输入到规模为m列2n行的第一电阻阵列中；m列2n行的第一电阻阵列的电导与输入的模拟电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在行的末尾输出；第一电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，得到2n个电压值，记为V1、V2……V2n；第一减法电路对2n个电压值的前n个电压值和后n个电压值进行减法差分处理，产生n路模拟电压V1’、V2’……Vn’，Vi’＝Vi-Vi+n，i为1--n；第一激活函数电路将n路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生n路电压；
规模为n列20行的第二电阻阵列的电导与第一激活函数电路产生的n路电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在 行的末尾输出；第二电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，得到20个电压值，记为U1、U2……U20；第二减法电路对20个电压值的前10个电压值和后10个电压值进行减法差分处理，产生10路模拟电压，U1’、U2’……U20’，Ui’＝Ui-Ui+10，i为1--10；第二激活函数电路将10路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生10路电压；电压比较电路将第二激活函数电路输出的10路电压分别与基准电压0.5V进行比较，每一路大于0.5V的电压输出高电平到对应的数码管，所述数码管的数量为10个，分别对应10路电压以及0—9十个数字，从而点亮该路对应的数字，完成手写数字识别功能。
进一步地，所述电路模块中的输入驱动电路由非反相的MOSFET驱动芯片构成，将由外部带触摸电容屏幕的微控制器产生的m路大小为3.3V的电压信号转换为5V的电压信号，并将每一路电压的驱动负载能力提高到100mA。
进一步地，所述电流电压转换电路包括采样电阻和集成运算放大器，所述采样电阻阻值为1Ω，将电流转换为电压，所述集成运算放大器用于构建同相组态放大器，放大采样电阻得到的电压。
进一步地，所述电路模块中的减法电路包括集成运算放大器，用于将V1、V2……V2n这2n个电压值放大。
进一步地，所述第一激活函数电路和第二激活函数电路分别由三级放大电路级联组成，第一放大电路由带偏置的同相组态运算放大器构成，第二和第三级放大电路由反相组态运算放大器构成；所述激活函数为Sigmoid函数，将Sigmoid函数简化为y＝0.2x+0.5，其中x,y分别为自变量和因变量，将激活函数电路输入电压信号分为以下三段：(-∞,-2.5V)、[-2.5V,2.5V]、(2.5V,+∞)，由第一放大电路将三段信号并行映射到0-5V；由第二和第三级放大电路依次进行线性变换，将0-5V最终映射到0-1V，实现Sigmoid函数功能。
进一步地，所述电压比较电路包括集成运算放大器，所述电压比较电路为单门限电压比较电路，输入到电压比较电路中的电压值大于0.5V的，输出高电平。
进一步地，所述高电平为1V。
本发明的有益效果是：与传统的神经网络硬件系统相比，本发明完全由基于存算一体架构的模拟电路实现，可以消除传统冯诺依曼架构所带来的数据搬运问题，并且不需要任何数字模块的辅助，可以实现超低延时的精准识别。本发明在基于存算一体架构的新型神经网络硬件系统研究领域具有非常广阔的应用前景，有望为深度神经网络和边缘计算提供一个可行的非冯诺依曼硬件解决方案。
附图说明
图1是本发明的电路原理示意图；
图2是本发明实例的输入驱动电路的电路原理图；
图3是本发明实例的第一电流电压转换电路和第二电流电压转换电路的电路原理图；
图4是本发明实例的第一减法电路和第二减法电路的电路原理图；
图5是本发明实例的第一激活函数电路和第二激活函数电路的电路原理图；
图6是本发明实例的电压比较电路的电路原理图。
具体实施方式
下面结合附图和实例，对本发明的具体实施方式作进一步详细描述。以下实例用于说明本发明，不用来限制本发明的范围。
本发明提供一种基于存算一体架构的用于手写数字识别的全模拟电路系统，系统的电路原理示意图如图1所示，包括第一模拟电路和第二模拟电路，第一模拟电路由以下电路模块组成：输入驱动电路、规模为49列20行的第一电阻阵列、第一电流电压转换电路、第一减法电路、第一激活函数电路；
第二模拟电路由以下电路模块组成：规模为10列20行的第二电阻阵列、第二电流电压转换电路、第二减法电路、第二激活函数电路、电压比较电路。
所述全模拟电路系统的输入是49个模拟电压，由外接的带触摸电容屏幕的微控制器产生(在本实施例中使用的微控制器是STM32F103ZET6单片机，单片机外接一个4.3英寸电容触摸屏幕作为手写数字的输入设备，采集手写数字， 并转换为49个模拟电压)，输入驱动电路增强49个模拟电压的负载能力，得到49个驱动电压，输入驱动电路由非反相的MOSFET驱动芯片构成，将由外部带触摸电容屏幕的微控制器产生的49路大小为3.3V的电压转换为5V的电压，并将每一路电压的驱动负载能力提高到100mA；可采用双通道高速功率MOSFET驱动器TC4427芯片来实现，其具有高输出电流，宽电源电压等优点，其电路原理图如图3所示。
输入驱动电路将驱动电压输入到规模为49列20行的第一电阻阵列中，49列20行的第一电阻阵列的电导与输入的驱动电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在行的末尾输出；第一电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，得到20个电压值，记为V1、V2……V20；电流电压转换电路由采样电阻和集成运算放大器实现，采样电阻阻值为1Ω，将电阻阵列中每一行累积的电流转换为电压，集成运算放大器用于构建同相组态放大器，放大采样电阻得到的电压，放大倍数为40倍；可采用TI公司的OPA4317系列集成运算放大器实现，其具有低偏移、轨到轨输出、高速、低噪声的特性。其电路原理图如图5所示。第一减法电路对20个电压值的前10个电压值和后10个电压值进行减法差分处理，产生10路模拟电压V1’、V2’……V10’，Vi’＝Vi-Vi+10，i为1--10；减法电路可采用TI公司的OPA2227系列集成运算放大器实现，其具有双电源供电、宽电源电压范围、高精度、低噪声的特性。其电路原理图如图6所示。第一激活函数电路将10路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生10路电压。
激活函数电路由三级放大电路级联组成，用于实现Sigmoid函数，其中第一放大电路由带偏置的同相组态运算放大器构成，第二和第三级放大电路由反相组态运算放大器构成；将Sigmoid函数简化为y＝0.2x+0.5，将模拟电路输入电压信号分为三段：(-∞,-2.5V)、[-2.5V,2.5V]、(2.5V,+∞)，由第一放大电路将三段信号并行映射到0-5V；由第二和第三级放大电路依次进行线性变换，将0-5V最终映射到0-1V。第一放大电路由5V单电源供电、轨到轨输出的集成运算放大器构成，且偏置电压为2.5V，放大倍数为1倍；可采用TI公司的OPA4350系 列集成运算放大器实现，其具有单电源供电、轨到轨输出、高速、低噪声的特性。第二放大电路由±5V双电源供电的集成运算放大器构成，放大倍数为0.2倍；可采用TI公司的OPA2227系列集成运算放大器实现，其具有双电源供电、宽电源电压范围、高精度、低噪声的特性。第三级放大电路由±5V双电源供电的集成运算放大器构成，放大倍数为1倍；可采用TI公司的OPA2227系列集成运算放大器实现。其电路原理图如图7所示。
规模为10列20行的第二电阻阵列的电导与第一激活函数电路产生的10路电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在行的末尾输出；第二电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，放大50倍，得到20个电压值，记为U1、U2……U20；第二减法电路对20个电压值的前10个电压值和后10个电压值进行减法差分处理，产生10路模拟电压，U1’、U2’……U20’，Ui’＝Ui-Ui+10，i为1--10；第二激活函数电路将10路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生10路电压；电压比较电路将第二激活函数电路输出的10路电压分别与基准电压0.5V进行比较，每一路大于0.5V的电压输出高电平到对应的数码管，所述数码管的数量为10个，分别对应10路电压以及0—9十个数字，从而点亮该路对应的数字，完成手写数字识别功能。电压比较电路可以采用TI公司的OPA4317系列集成运算放大器实现，其具有低偏移、轨到轨输出、高速、低噪声的特性。其电路原理图如图9所示。
由以上实施例可以看出，本发明实例实现了手写数字的识别，该系统完全由基于存算一体架构的模拟电路实现，可以消除传统冯诺依曼架构所带来的数据搬运问题，并且不需要任何数字模块的辅助，可以实现超低延时的精准手写数字识别。该系统在基于存算一体架构的新型神经网络硬件系统研究领域具有非常广阔的应用前景，有望为深度神经网络和边缘计算提供一个可行的非冯诺依曼硬件解决方案。
以上所述的实例对本发明的技术方案和有益效果进行了详细说明，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换也应视为本发明的保护范围。

Claims (7)

  1. 基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，包括第一模拟电路和第二模拟电路；
    所述第一模拟电路由以下电路模块组成：输入驱动电路、规模为m列2n行的第一电阻阵列、第一电流电压转换电路、第一减法电路、第一激活函数电路；
    所述第二模拟电路由以下电路模块组成：规模为n列20行的第二电阻阵列、第二电流电压转换电路、第二减法电路、第二激活函数电路、电压比较电路；
    所述全模拟电路系统的输入是m个模拟电压，由外接的带触摸电容屏幕的微控制器产生，输入驱动电路增强m个模拟电压的负载能力，得到m个驱动电压，输入驱动电路将驱动电压输入到规模为m列2n行的第一电阻阵列中；m列2n行的第一电阻阵列的电导与输入的驱动电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在行的末尾输出；第一电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，得到2n个电压值，记为V1、V2……V2n；第一减法电路对2n个电压值的前n个电压值和后n个电压值进行减法差分处理，产生n路模拟电压V1’、V2’……Vn’，Vi’＝Vi-Vi+n，i为1--n；第一激活函数电路将n路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生n路电压；
    规模为n列20行的第二电阻阵列的电导与第一激活函数电路产生的n路电压相乘，每个电阻上得到一个相应的电流值，每一行上的所有电流值累加并在行的末尾输出；第二电流电压转换电路将每一行输出的电流值转换为电压值，并进行放大处理，得到20个电压值，记为U1、U2……U20；第二减法电路对20个电压值的前10个电压值和后10个电压值进行减法差分处理，产生10路模拟电压，U1’、U2’……U20’，Ui’＝Ui-Ui+10，i为1--10；第二激活函数电路将10路模拟电压进行非线性激活，将其映射到0V-1V电压范围之间产生10路电压；电压比较电路将第二激活函数电路输出的10路电压分别与基准电压0.5V进行比较，每一路大于0.5V的电压输出高电平到对应的数码管，所述数码管的数量为10 个，分别对应10路电压以及0—9十个数字，从而点亮该路对应的数字，完成手写数字识别功能。
  2. 根据权利要求1所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述电路模块中的输入驱动电路由非反相的MOSFET驱动芯片构成，将由外部带触摸电容屏幕的微控制器产生的m路大小为3.3V的电压信号转换为5V的电压信号，并将每一路电压的驱动负载能力提高到100mA。
  3. 根据权利要求1所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述电流电压转换电路包括采样电阻和集成运算放大器，所述采样电阻阻值为1Ω，将电流转换为电压，所述集成运算放大器用于构建同相组态放大器，放大采样电阻得到的电压。
  4. 根据权利要求1所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述电路模块中的减法电路包括集成运算放大器，用于将V1、V2……V2n这2n个电压值放大。
  5. 根据权利要求1所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述第一激活函数电路和第二激活函数电路分别由三级放大电路级联组成，第一放大电路由带偏置的同相组态运算放大器构成，第二和第三级放大电路由反相组态运算放大器构成；所述激活函数为Sigmoid函数，将Sigmoid函数简化为y＝0.2x+0.5，其中x,y分别为自变量和因变量，将激活函数电路输入电压信号分为以下三段：(-∞,-2.5V)、[-2.5V,2.5V]、(2.5V,+∞)，由第一放大电路将三段信号并行映射到0-5V；由第二和第三级放大电路依次进行线性变换，将0-5V最终映射到0-1V，实现Sigmoid函数功能。
  6. 根据权利要求1所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述电压比较电路包括集成运算放大器，所述电压比较电路为单门限电压比较电路，输入到电压比较电路中的电压值大于0.5V的，输出高电平。
  7. 根据权利要求6所述的基于存算一体架构的用于手写数字识别的全模拟电路系统，其特征在于，所述高电平为1V。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190392289A1 (en) * 2017-03-22 2019-12-26 Denso Corporation Neural network circuit
US20200380350A1 (en) * 2019-05-28 2020-12-03 Cirrus Logic International Semiconductor Ltd. Analog neural network systems
US20210097379A1 (en) * 2019-09-26 2021-04-01 Qatar Foundation For Education, Science And Community Development Circuit for calculating weight adjustments of an artificial neural network, and a module implementing a long short-term artificial neural network
CN113517009A (zh) * 2021-06-10 2021-10-19 上海新氦类脑智能科技有限公司 存算一体式智能芯片、控制方法及控制器
CN115564019A (zh) * 2022-09-13 2023-01-03 浙江大学 一种神经网络激活函数模拟电路及其设计方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190392289A1 (en) * 2017-03-22 2019-12-26 Denso Corporation Neural network circuit
US20200380350A1 (en) * 2019-05-28 2020-12-03 Cirrus Logic International Semiconductor Ltd. Analog neural network systems
US20210097379A1 (en) * 2019-09-26 2021-04-01 Qatar Foundation For Education, Science And Community Development Circuit for calculating weight adjustments of an artificial neural network, and a module implementing a long short-term artificial neural network
CN113517009A (zh) * 2021-06-10 2021-10-19 上海新氦类脑智能科技有限公司 存算一体式智能芯片、控制方法及控制器
CN115564019A (zh) * 2022-09-13 2023-01-03 浙江大学 一种神经网络激活函数模拟电路及其设计方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ZHOU XUAN; ZHU XIAOLEI; CHEN BING; ZHAO YI; FU CHENGJIE: "An 8-bit RRAM based Multiplier for Hybrid Memory Computing", 2019 IEEE INTERNATIONAL WORKSHOP ON FUTURE COMPUTING (IWOFC, IEEE, 14 December 2019 (2019-12-14), pages 1 - 3, XP033763911, DOI: 10.1109/IWOFC48002.2019.9078444 *
ZHU JIANGHAN; CHEN BINGZHEN; YANG ZHITAO; MENG LINGXIAO; YE TERRY TAO: "Analog Circuit Implementation of Neural Networks for In-Sensor Computing", 2021 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI), IEEE, 7 July 2021 (2021-07-07), pages 150 - 156, XP033963446, DOI: 10.1109/ISVLSI51109.2021.00037 *

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