Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/851—Complementary IGFETs, e.g. CMOS comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D88/00—Three-dimensional [3D] integrated devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/427—Power or ground buses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/435—Cross-sectional shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D88/00—Three-dimensional [3D] integrated devices
  • H10D88/01—Manufacture or treatment

Definitions

• This disclosure relates to a semiconductor integrated circuit device, and in particular to the layout structure of an output circuit.
• Semiconductor integrated circuit devices are equipped with input/output circuits that input and output signals from and to the outside world via input/output pads. As the output circuit in the input/output circuit passes a large current, careful attention must be paid to its layout structure.
• Patent Document 1 proposes a configuration in which transistors are stacked and wiring is provided directly below the transistors in order to increase the integration density of semiconductor integrated circuit devices.
• Patent Document 1 does not disclose a specific layout structure for a circuit that passes a large current, such as an output circuit in an input/output circuit, in a configuration in which transistors are stacked and wiring is provided directly below the transistors.
• the objective of this disclosure is to realize an output circuit capable of passing a large current to an output terminal in a semiconductor integrated circuit device having a configuration in which transistors are stacked and wiring is provided directly below the transistors.
• an output circuit for outputting a signal from a semiconductor integrated circuit includes a first output transistor section including a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and an output terminal, a first power supply wiring that supplies the first power supply voltage, and an output wiring connected to the output terminal, the first output transistor section including a first active region that constitutes the channel, source, and drain of the first transistor, and a second active region that constitutes the channel, source, and drain of the first transistor, that is formed in an upper layer of the first active region, and that overlaps with the first active region in a planar view, the first power supply wiring is disposed on the back side of the first transistor so as to overlap with the first and second active regions in a planar view, and is connected to the underside of the portion of the first active region that becomes the source of the first transistor through a via, and the output wiring is disposed in the same wiring layer as the first power supply wiring so as to overlap with the first and second active regions
• a first output transistor section including a first transistor connected between a first power supply and an output terminal includes first and second active areas.
• the first and second active areas overlap in a planar view to form a first transistor.
• the first power supply wiring and the output wiring are arranged in a wiring layer on the back side of the first transistor so as to overlap with the first and second active areas in a planar view.
• the first power supply wiring is connected via a via to the underside of a portion of the first active area that serves as the source of the first transistor, and the output wiring is connected via a via to the underside of a portion of the first active area that serves as the drain of the first transistor.
• an output circuit for outputting a signal from a semiconductor integrated circuit includes a first output transistor section including first and second transistors of a first conductivity type connected in series between a first power supply that supplies a first power supply voltage and an output terminal, a first power supply wiring that supplies the first power supply voltage, and an output wiring that is connected to the output terminal, the first output transistor section including a first active region and a second active region that is formed in an upper layer of the first active region and overlaps the first active region in a planar view, at least one of the first and second active regions constitutes the channel, source, and drain of the first and second transistors, the first power supply wiring is disposed on the back side of the first and second transistors so as to overlap the first and second active regions in a planar view, and is connected to the underside of the portion of the first active region that serves as the source of the first transistor through a via, and the output wiring is disposed in the same wiring layer as the first power supply wiring so as to overlap the first and second active
• a first output transistor section including first and second transistors connected in series between a first power supply and an output terminal includes first and second active areas.
• the first and second active areas overlap in a planar view, and at least one of them constitutes the first and second transistors.
• the first power supply wiring and the first output wiring are arranged in a wiring layer on the rear side of the first and second transistors so as to overlap the first and second active areas in a planar view.
• the first power supply wiring is connected via a via to the underside of a portion of the first active area that serves as the source of the first transistor, and the output wiring is connected via a via to the underside of a portion of the first active area that serves as the drain of the second transistor.
• FIG. 1 is a plan view showing a layout of an IO cell according to a first embodiment
• FIG. 1 is a plan view showing a layout of an IO cell according to a first embodiment
• FIG. 1 is a plan view showing a layout of an IO cell according to a first embodiment
• 4(a) and 4(b) are cross-sectional views of the layouts shown in FIGS. 1A is another example of the configuration of a semiconductor integrated circuit device
• FIG. 1B is a cross-sectional view of the device.
• FIG. 11 is a plan view showing a layout of an IO cell according to a second embodiment
• FIG. 11 is a plan view showing a layout of an IO cell according to a second embodiment
• FIG. 11 is a plan view showing a layout of an IO cell according to a second embodiment
• VSS and VDDIO
• OUT refers to both the output terminal and the output signal.
• FIG. 1 is a plan view showing a schematic overall configuration of a semiconductor integrated circuit device (semiconductor chip) according to an embodiment.
• the semiconductor integrated circuit device 1 shown in FIG. 1 includes a core region 2 in which an internal core circuit is formed, and an IO region 3 provided around the core region 2 and in which an interface circuit (IO circuit) is formed.
• an IO cell row 5 is provided so as to surround the core region 2 in the peripheral portion of the semiconductor integrated circuit device 1.
• a plurality of IO cells 10 constituting an interface circuit are arranged in the IO cell row 5.
• the IO cells 10 include signal IO cells that input, output, or input/output signals, power IO cells for supplying a ground potential (power supply voltage VSS), and power IO cells for supplying power (power supply voltage VDDIO) mainly to the IO region 3.
• VSS power supply voltage
• VDDIO power supply voltage
• the IO cell 10A for signal input/output is arranged on the upper side of the core region 2.
• the IO region 3 is provided with power supply wiring 6, 7 extending in the direction in which the IO cells 10 are arranged.
• the power supply wiring 6, 7 are formed in a ring shape on the periphery of the semiconductor integrated circuit device 1 (also called ring power supply wiring).
• the power supply wiring 6 supplies VDDIO, and the power supply wiring 7 supplies VSS.
• the power supply wiring 6, 7 are formed in a wiring layer on the back side of the semiconductor chip in which the transistors are formed.
• the semiconductor integrated circuit device 1 has multiple external connection pads arranged thereon. In this embodiment, the multiple external connection pads are provided on the back side of the semiconductor chip.
• FIG. 2 is a simplified diagram of the configuration of IO cell 10A.
• IO cell 10A has power supply wiring 6, 7 arranged extending in the X direction.
• an N-conductivity type output transistor section 11 is provided on power supply wiring 7, and a P-conductivity type output transistor section 12 is provided on power supply wiring 6.
• the N-conductivity type output transistor section 11 and the P-conductivity type output transistor section 12 are provided in positions closer to the outside of the chip.
• FIG. 3 is a circuit diagram of the output circuit in this embodiment.
• the IO cell 10A in FIG. 2 has the output circuit shown in FIG. 3.
• a P-conductivity type (hereinafter, referred to as P-type as appropriate) transistor P1 is provided between the power supply VDDIO and the output terminal OUT (outputs the output signal OUT), and an N-conductivity type (hereinafter, referred to as N-type as appropriate) transistor N1 is provided between the power supply VSS and the output terminal OUT.
• the output control circuit 20 outputs output control signals INP and INN.
• the transistor P1 receives the output control signal INP at its gate
• the transistor N1 receives the output control signal INN at its gate.
• the output signal OUT is supplied to an external connection pad.
• the output signal OUT becomes a high level (VDDIO)
• the output control signals INP and INN are at a high level
• the output signal OUT becomes a low level (VSS).
• the transistors that make up the output circuit are realized by CFETs (Complementary Field Effect Transistors), which are transistors stacked together.
• a wiring layer is provided on the back of the CFET.
• FIGS. 4, 5, and 6 are plan views showing the layout of the output transistor section of IO cell 10A shown in FIG. 2 in this embodiment.
• FIGS. 4, 5, and 6 show the layout divided into layers.
• FIG. 4 shows the configuration of the back wiring
• FIG. 5 shows the configuration of the lower transistor (labeled "lower Tr.” in the figure)
• FIG. 6 shows the configuration of the upper transistor (labeled "upper Tr.” in the figure).
• FIG. 7 is a cross-sectional view showing the cross-sectional structure of the layout of FIGS. 4 to 6, where (a) shows the cross-sectional structure along line X1-X1' and (b) shows the cross-sectional structure along line Y1-Y1'. The direction perpendicular to the substrate surface is taken as the Z direction.
• the upper part of the drawing corresponds to the N-conductivity type output transistor section 11 that constitutes transistor N1
• the lower part of the drawing corresponds to the P-conductivity type output transistor section 12 that constitutes transistor P1.
• Nanosheet FETs Field Effect Transistors are formed in the N-conductivity type output transistor section 11 and the P-conductivity type output transistor section 12.
• the N-conductivity type output transistor section 11 comprises a lower active region 31 constituting the lower transistor, and an upper active region 51 constituting the upper transistor.
• the P-conductivity type output transistor section 12 comprises a lower active region 35 constituting the lower transistor, and an upper active region 55 constituting the upper transistor.
• the active region constitutes the channel, source, and drain of a transistor.
• the active region constituting a nanosheet FET has a nanosheet as a channel. The portions of the active region that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.
• a number of pad electrodes are provided on the back surface of the semiconductor chip. Power supply voltages VDDIO and VSS are supplied from outside the semiconductor chip via the pad electrodes. In addition, the output signal OUT is connected to the outside of the semiconductor chip via the pad electrodes.
• the BM0 (Backside Metal 0) layer and the BM1 (Backside Metal 1) layer are provided as wiring layers.
• the BM1 layer is located below the BM0 layer, i.e., farther from the transistors.
• the power supply wiring 6, 7 shown in FIG. 2 are formed in the BM1 layer.
• the power supply wiring 6 (two in FIG. 4) that supplies VDDIO is provided under the P-conductivity type output transistor section 12, and the power supply wiring 7 (two in FIG. 4) that supplies VSS is provided under the N-conductivity type output transistor section 11.
• the output wiring 8 (three in FIG. 4) that transmits the output signal OUT is arranged to extend in the X direction.
• the power supply wiring 6, 7 and the output wiring 8 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• the power supply wiring 21 that supplies VSS is provided under the N-conductivity type output transistor section 11, and overlaps with the power supply wiring 7 in the BM1 layer in a planar view.
• the power supply wiring 21 and the power supply wiring 7 are connected through a via.
• the power supply wiring 22 that supplies VDDIO is provided under the P-conductivity type output transistor section 12, and overlaps with the power supply wiring 6 in the BM1 layer in a planar view.
• the power supply wiring 22 and the power supply wiring 6 are connected through a via.
• the output wiring 23 that transmits the output signal OUT is provided under the N-conductivity type output transistor section 11 and the P-conductivity type output transistor section 12, and overlaps with the output wiring 8 in the BM1 layer in a planar view.
• the output wiring 23 and the output wiring 8 are connected through a via.
• an active region 31 that constitutes the channel, source, and drain of transistor N1 is formed in the component portion of the lower transistor.
• three active regions 31 are formed, and each active region 31 has six nanosheets 32.
• the portion that becomes the source of transistor N1 is connected through a via to the power supply wiring 21 that supplies VSS.
• the portion that becomes the drain of transistor N1 is connected through a via to the output wiring 23.
• an active region 35 that constitutes the channel, source, and drain of transistor P1 is formed in the lower transistor component.
• three active regions 35 are formed, and each active region 35 has six nanosheets 36.
• the part that becomes the source of transistor P1 is connected through a via to the power supply wiring 22 that supplies VDDIO.
• the part that becomes the drain of transistor P1 is connected through a via to the output wiring 23.
• a local wiring 41 extending in the Y direction is arranged on the upper surface of the portion that will become the source of transistor N1 in the active region 31.
• a local wiring 42 extending in the Y direction is arranged on the upper surface of the portion that will become the source of transistor P1 in the active region 35.
• a local wiring 43 extending in the Y direction is arranged on the upper surface of the portion that will become the drain of transistor N1 in the active region 31 and the portion that will become the drain of transistor P1 in the active region 35.
• an active region 51 that constitutes the channel, source, and drain of the transistor N1 is formed in the upper transistor component.
• three active regions 51 are formed, and each active region 51 has six nanosheets 52.
• active regions 55 that form the channel, source, and drain of transistor P1 are formed in the upper transistor component.
• active regions 55 are formed, and each active region 55 has six nanosheets 56.
• a gate wiring 61 is formed extending in the Y and Z directions.
• the gate wiring 61 surrounds the outer periphery in the Y and Z directions of the nanosheet 32 in the active region 31 and the nanosheet 52 in the active region 51 via a gate insulating film (not shown).
• the gate wiring 61 corresponds to the gate of transistor N1.
• a gate wiring 65 is formed extending in the Y and Z directions.
• the gate wiring 65 surrounds the outer periphery in the Y and Z directions of the nanosheet 36 of the active region 35 and the nanosheet 56 of the active region 55 via a gate insulating film (not shown).
• the gate wiring 65 corresponds to the gate of the transistor P1.
• a local wiring 44 extending in the Y direction is arranged on the upper surface of the portion of the active region 51 that serves as the source of transistor N1.
• a local wiring 45 extending in the Y direction is arranged on the upper surface of the portion of the active region 55 that serves as the source of transistor P1.
• a local wiring 46 extending in the Y direction is arranged on the upper surface of the portion of the active region 51 that serves as the drain of transistor N1 and the portion of the active region 55 that serves as the drain of transistor P1.
• Local wiring 41 and local wiring 44 which overlap in plan view, are connected through a via. That is, the portions that become the source of transistor N1 in active regions 31 and 51 are connected.
• Local wiring 42 and local wiring 45 which overlap in plan view, are connected through a via. That is, the portions that become the source of transistor P1 in active regions 35 and 55 are connected.
• Local wiring 43 and local wiring 46 which overlap in plan view, are connected through a via. That is, the portions that become the drain of transistor N1 in active regions 31 and 51 are connected to the portions that become the drain of transistor P1 in active regions 35 and 55.
• Metal wires 71 and 72 extending in the X direction are formed in the M0 wiring layer, which is a metal wiring layer above the local wiring layer.
• Metal wires 71 (two wires in FIG. 6) are connected to gate wire 61 through a via.
• Metal wires 72 (two wires in FIG. 6) are connected to gate wire 65 through a via.
• Metal wire 71 is a wire that transmits an output control signal INN
• metal wire 72 is a wire that transmits an output control signal INP.
• the only wiring formed on the back surface of the semiconductor chip is the power supply wiring 6, 22 that supplies VDDIO, the power supply wiring 7, 21 that supplies VSS, and the output wiring 8, 23 that transmits the output signal OUT.
• the power supply wiring 6, 7 and the output wiring 8 are laid out to the maximum extent. This allows the output circuit to pass a large current.
• the active regions 31 and 35 of the lower transistors are connected to the back wiring only through vias. This reduces the resistance value, allowing the output circuit to pass a large current.
• both the upper and lower transistors are N-type transistors.
• both the upper and lower transistors are P-type transistors. This allows the current flowing from the output circuit to be increased.
• the N-conductivity type output transistor section 11 which includes the transistor N1 connected between the power supply VSS and the output terminal OUT, includes active regions 31 and 51.
• the active regions 31 and 51 overlap in a planar view to form the transistor N1.
• the power supply wiring 21 and the output wiring 23 are arranged in the wiring layer on the back side of the transistor N1 so as to overlap the active regions 31 and 51 in a planar view.
• the power supply wiring 21 is connected via a via to the underside of the portion of the active region 31 that serves as the source of the transistor N1
• the output wiring 23 is connected via a via to the underside of the portion of the active region 31 that serves as the drain of the transistor N1.
• the P-conductivity type output transistor section 12 which includes a transistor P1 connected between a power supply VDD and an output terminal OUT, includes active regions 35 and 55.
• the active regions 35 and 55 overlap in a plan view to form the transistor P1.
• the power supply wiring 22 and the output wiring 23 are arranged in the wiring layer on the rear side of the transistor P1 so as to overlap the active regions 35 and 55 in a plan view.
• the power supply wiring 22 is connected via a via to the underside of the portion of the active region 35 that serves as the source of the transistor P1
• the output wiring 23 is connected via a via to the underside of the portion of the active region 35 that serves as the drain of the transistor P1.
• This configuration makes it possible to realize an output circuit that can pass a large current through the output terminal without increasing the layout area.
• the power supply wiring 6, 7, 21, 22 and the output wiring 8, 23 are formed in a wiring layer provided on the back surface of the semiconductor chip, this is not limited to the present invention.
• the power supply wiring and the output wiring may be formed on the back surface of the transistor.
• the back surface of the transistor refers to the side opposite to the side on which the local wiring, metal wiring, etc. connected to the transistor are stacked.
• the power supply wiring 6, 7, 21, 22 and the output wiring 8, 23 may also be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM1 layer to form the back wiring.
• the power supply wiring and output wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.
• FIG. 8(a) is another configuration example of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 100 shown in FIG. 8(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B).
• the above-mentioned IO cells, standard cells, etc. are arranged on chip A.
• Chip B has power wiring and output wiring formed in a wiring layer provided on the surface.
• Chip B is attached to the back side of chip A using bumps, etc.
• FIG. 8(b) shows a cross section of the output circuit shown in FIGS. 4 to 6 along line Y1-Y1' in this configuration example.
• the power supply wiring and output wiring formed in the BM0 layer and BM1 layer in the above-described embodiment are formed in a wiring layer provided on the surface of chip B.
• the power supply wiring and output wiring may also be formed in multiple wiring layers.
• the power supply wiring further below the BM1 layer is also formed in chip B.
• (Modification) 9 shows the cross-sectional configuration of the output circuit according to the modified example taken along line Y1-Y1'.
• the lower portions of the active regions 51 and 55 of the upper transistor are connected to local wiring 43 formed on the upper surfaces of the active regions 31 and 35 of the lower transistor through vias.
• the local wiring 41 formed on the upper surface of the active region 31 of the lower transistor is similarly connected to the lower portion of the active region 51 of the upper transistor through a via.
• the local wiring 42 formed on the upper surface of the active region 35 of the lower transistor is connected to the lower portion of the active region 55 of the upper transistor through a via.
• no local wiring is formed on the upper surfaces of the active regions 51 and 55 of the upper transistor.
• local wiring may be formed on the upper surfaces of the active regions 51 and 55.
• This configuration reduces the resistance in the path to the upper transistor, allowing the output circuit to pass a larger current.
• the upper surface of active region 31 and the lower surface of active region 51 may be connected through vias, and the upper surface of active region 35 and the lower surface of active region 55 may be connected through vias.
• FIG. 10 is a circuit diagram of an output circuit in the second embodiment.
• the IO cell 10A shown in FIG. 2 includes an output circuit shown in FIG. 10.
• P-type transistors P21 and P22 are provided in series between a power supply VDDIO and an output terminal OUT
• N-type transistors N21 and N22 are arranged in series between a power supply VSS and an output terminal OUT.
• the output control circuit 20A outputs output control signals INP1, INP2, INN1, and INN2.
• the transistor P21 receives the output control signal INP1 at its gate
• the transistor P22 receives the output control signal INP2 at its gate.
• the transistor N21 receives the output control signal INN1 at its gate, and the transistor N22 receives the output control signal INN2 at its gate.
• the output signal OUT is then supplied to an external connection pad.
• the output control signals INP1, INP2, INN1, and INN2 are at a low level, the output signal OUT is at a high level (VDDIO), and when the output control signals INP1, INP2, INN1, and INN2 are at a high level, the output signal OUT is at a low level (VSS).
• VDDIO high level
• VSS low level
• one of the output control signals INP1 and INP2 may be at a fixed potential (VSS)
• the other of the output control signals INN1 and INN2 may be at a fixed potential (VDDIO).
• FIGS. 11, 12, and 13 are plan views showing the layout of the output transistor portion of IO cell 10A shown in FIG. 2 in this embodiment.
• FIGS. 11, 12, and 13 show the layout divided by layer.
• FIG. 11 shows the configuration of the back wiring
• FIG. 12 shows the configuration of the lower transistor
• FIG. 13 shows the configuration of the upper transistor. Note that the cross-sectional structure is similar to that of the first embodiment and can be easily understood from the first embodiment, so it is not shown here.
• the upper part of the drawing corresponds to the N-conductivity type output transistor section 11 that constitutes the transistors N21 and N22, and the lower part of the drawing corresponds to the P-conductivity type output transistor section 12 that constitutes the transistors P21 and P22.
• Nanosheet FETs are formed in the N-conductivity type output transistor section 11 and the P-conductivity type output transistor section 12.
• the layouts of Figures 11 to 13 have two transistors in series, so two nanosheets are formed between the power supplies VSS, VDDIO and the output terminal OUT, and two gate wirings are arranged.
• the basic configuration is the same as in the first embodiment, and detailed explanations of the configuration that can be easily understood from the explanation of the first embodiment will be omitted.
• the power supply wiring 121a, 121b that supplies VSS is provided under the N-conductivity type output transistor section 11, and overlaps with the power supply wiring 7 in the BM1 layer in a planar view.
• the power supply wiring 121a, 121b and the power supply wiring 7 are connected through vias.
• the power supply wiring 122a, 122b that supplies VDDIO is provided under the P-conductivity type output transistor section 12, and overlaps with the power supply wiring 6 in the BM1 layer in a planar view.
• the power supply wiring 122a, 122b and the power supply wiring 6 are connected through vias.
• the output wiring 123a, 123b is provided under the N-conductivity type output transistor section 11 and the P-conductivity type output transistor section 12, and overlaps with the output wiring 8 in the BM1 layer in a planar view.
• the output wiring 123a, 123b and the output wiring 8 are connected through vias.
• an active region 31 that forms the channels, sources, and drains of transistors N21 and N22 is formed in the lower transistor component.
• the part that becomes the source of transistor N21 is connected through a via to power supply wiring 121a, 121b that supplies VSS.
• the part that becomes the drain of transistor N22 is connected through a via to output wiring 123a, 123b.
• an active region 35 that forms the channel, source, and drain of transistors P21 and P22 is formed in the lower transistor component.
• the part that becomes the source of transistor P21 is connected through a via to power supply wiring 122a and 122b that supplies VDDIO.
• the part that becomes the drain of transistor P22 is connected through a via to output wiring 123a and 123b.
• a local wiring 141 extending in the Y direction is arranged on the upper surface of the portion that serves as the source of transistor N21 in the active region 31, and on the upper surface of the portion that serves as the drain of transistor N21 and the source of transistor N22.
• a local wiring 142 extending in the Y direction is arranged on the upper surface of the portion that serves as the source of transistor P21 in the active region 35, and on the upper surface of the portion that serves as the drain of transistor P21 and the source of transistor P22.
• a local wiring 143 extending in the Y direction is arranged on the upper surface of the portion that serves as the drain of transistor N22 in the active region 31, and on the upper surface of the portion that serves as the drain of transistor P22 in the active region 35.
• active regions 51 that form the channels, sources, and drains of transistors N21 and N22 are formed in the upper transistor component.
• active regions 55 that form the channels, sources, and drains of transistors P21 and P22 are formed in the upper transistor component.
• gate wirings 161, 162 are formed extending in the Y and Z directions.
• the gate wirings 161, 162 surround the outer periphery in the Y and Z directions of the nanosheet 32 in the active region 31 and the nanosheet 52 in the active region 51 via a gate insulating film (not shown).
• the gate wiring 161 corresponds to the gate of transistor N21
• the gate wiring 162 corresponds to the gate of transistor N22.
• gate wirings 165, 166 are formed extending in the Y and Z directions.
• the gate wirings 165, 166 surround the outer periphery in the Y and Z directions of the nanosheet 36 of the active region 35 and the nanosheet 56 of the active region 55 via a gate insulating film (not shown).
• the gate wiring 165 corresponds to the gate of transistor P21
• the gate wiring 166 corresponds to the gate of transistor P22.
• a local wiring 144 extending in the Y direction is arranged on the upper surface of the portion of the active region 51 that serves as the source of transistor N21, and on the upper surface of the portion of the active region 51 that serves as the drain of transistor N21 and the source of transistor N22.
• a local wiring 145 extending in the Y direction is arranged on the upper surface of the portion of the active region 55 that serves as the source of transistor P21, and on the upper surface of the portion of the active region 55 that serves as the drain of transistor P21 and the source of transistor P22.
• a local wiring 146 extending in the Y direction is arranged on the upper surface of the portion of the active region 51 that serves as the drain of transistor N22, and on the upper surface of the portion of the active region 55 that serves as the drain of transistor P22.
• Local wiring 141 and local wiring 144 which overlap in plan view, are connected through a via. That is, the part that becomes the source of transistor N21 in active regions 31 and 51 is connected. Also, the part that becomes the drain of transistor N21 and the source of transistor N22 in active regions 31 and 51 is connected. Local wiring 142 and local wiring 145, which overlap in plan view, are connected through a via. That is, the part that becomes the source of transistor P21 in active regions 35 and 55 is connected. Also, the part that becomes the drain of transistor P21 and the source of transistor P22 in active regions 35 and 55 is connected. Local wiring 143 and local wiring 146, which overlap in plan view, are connected through a via. That is, the part that becomes the drain of transistor N22 in active regions 31 and 51 is connected to the part that becomes the drain of transistor P22 in active regions 35 and 55.
• metal wirings 171, 172, 173, and 174 extending in the X direction are formed.
• Metal wiring 171 is connected to gate wiring 161 through a via.
• Metal wiring 172 is connected to gate wiring 162 through a via.
• Metal wiring 173 is connected to gate wiring 165 through a via.
• Metal wiring 174 is connected to gate wiring 166 through a via.
• Metal wiring 171 is a wiring that transmits the output control signal INN1
• metal wiring 172 is a wiring that transmits the output control signal INN2.
• Metal wiring 173 is a wiring that transmits the output control signal INP1, and metal wiring 174 is a wiring that transmits the output control signal INP2.
• the only wiring formed on the back surface of the semiconductor chip is the power supply wiring 6, 122a, 122b that supplies VDDIO, the power supply wiring 7, 121a, 121b that supplies VSS, and the output wiring 8, 123a, 123b that transmits the output signal OUT.
• the power supply wiring 6, 7 and the output wiring 8 are laid out to the maximum extent. This allows the output circuit to pass a large current.
• the active regions 31 and 35 of the lower transistors are connected to the back wiring only through vias. This reduces the resistance value, allowing the output circuit to pass a large current.
• both the upper and lower transistors are N-type transistors.
• both the upper and lower transistors are P-type transistors. This allows the current flowing from the output circuit to be increased.
• the N-conductivity type output transistor section 11 which includes transistors N21 and N22 connected in series between the power supply VSS and the output terminal OUT, includes active regions 31 and 51.
• the active regions 31 and 51 overlap in a plan view to form the transistors N21 and N22.
• the power supply wiring 121a and 121b and the output wiring 123a and 123b are arranged in the wiring layer on the back side of the transistors N21 and N22 so as to overlap the active regions 31 and 51 in a plan view.
• the power supply wiring 121a and 121b are connected via a via to the underside of the part of the active region 31 that serves as the source of the transistor N21, and the output wiring 123a and 123b are connected via a via to the underside of the part of the active region 31 that serves as the drain of the transistor N22.
• the P-conductivity type output transistor section 12 which includes transistors P21 and P22 connected in series between the power supply VDDIO and the output terminal OUT, includes active regions 35 and 55.
• the active regions 35 and 55 overlap in a plan view to form the transistors P21 and P22.
• the power supply wiring 122a and 122b and the output wiring 123a and 123b are arranged in the wiring layer on the back side of the transistors P21 and P22 so as to overlap the active regions 35 and 55 in a plan view.
• the power supply wiring 122a and 122b are connected via a via to the underside of the part of the active region 35 that serves as the source of the transistor P21, and the output wiring 123a and 123b are connected via a via to the underside of the part of the active region 35 that serves as the drain of the transistor P22.
• This configuration makes it possible to realize an output circuit that can pass a large current through the output terminal without increasing the layout area.
• the power supply wiring 6, 7, 121a, 121b, 122a, 122b and the output wiring 8, 123a, 123b may be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM1 layer to form the back wiring.
• the power supply wiring and output wiring formed on the back side of the transistor may be configured using a semiconductor chip separate from the semiconductor chip on which the transistor is configured.
• the active area of the upper transistor and the active area of the lower transistor may be electrically connected, as in the modified example of the first embodiment.
• the upper and lower transistors are of the same conductivity type. That is, in the N-conductivity type output transistor section 11, both the upper and lower active regions are N-type, and in the P-conductivity type output transistor section 12, both the upper and lower active regions are P-type.
• the conductivity type of the upper and lower active regions may be different in the entire output transistor section.
• the upper active region may be N-type and the lower active region may be P-type.
• the upper active region may be P-type and the lower active region may be N-type. This simplifies the manufacturing process of the entire output circuit, making it easier to manufacture the semiconductor integrated circuit device.
• a nanosheet FET is formed in the transistor portion, but the transistor formed in the transistor portion is not limited to a nanosheet FET.
• the transistor formed in the transistor portion may be a finFET.
• This disclosure makes it possible to realize an output circuit that can pass a large current through an output terminal without increasing the layout area, which is useful for improving the performance of semiconductor chips, for example.

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• 2024
  • 2024-03-27 JP JP2025512516A patent/JPWO2024210011A1/ja active Pending
  • 2024-03-27 WO PCT/JP2024/012187 patent/WO2024210011A1/ja not_active Ceased
• 2025
  • 2025-09-11 US US19/326,227 patent/US20260011643A1/en active Pending

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