WO2024183455A1 - 单总线系统的通信方法 - Google Patents

单总线系统的通信方法 Download PDF

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Publication number
WO2024183455A1
WO2024183455A1 PCT/CN2024/071417 CN2024071417W WO2024183455A1 WO 2024183455 A1 WO2024183455 A1 WO 2024183455A1 CN 2024071417 W CN2024071417 W CN 2024071417W WO 2024183455 A1 WO2024183455 A1 WO 2024183455A1
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single bus
slave
time slot
module
host
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PCT/CN2024/071417
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English (en)
French (fr)
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张夕勇
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张夕勇
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of integrated circuit design, and more particularly to a communication method of a single bus system.
  • the single bus is a peripheral serial expansion bus technology introduced by DALLAS in the United States. Different from the SPI and I2C serial data communication methods, it uses a single signal line to transmit both clock and data, and the data transmission is bidirectional. It has many advantages such as saving I/O port lines, simple resource structure, low cost, and convenient bus expansion and maintenance.
  • This protocol consists of a bus master node or multiple slave nodes to form a system, and reads data from the slave chip through a single signal line.
  • Each slave chip that complies with the single bus protocol has a unique address, including a 48-bit serial number, an 8-bit family code, and an 8-bit CRC code.
  • the master chip communicates with each chip in a bidirectional manner based on 64-bit addressing, so its protocol has strict timing requirements, and initialization, writing bits, or reading bits have strict timing requirements.
  • the host when there are multiple slaves on a single bus, the host mainly confirms the communication object through the unique identity information of the slave, that is, identity verification is required before actual communication. This process limits the speed of single bus communication.
  • the identity information of the slave is mainly the transmission of digital signals. There is a possibility of reverse cracking in the slave that needs encryption protection, which reduces information security.
  • the object of the present invention is to provide a communication method for a single bus system in order to overcome the deficiencies of the above-mentioned technology.
  • a communication method of a single bus system includes a host and multiple slaves, the host communicates with the multiple slaves through the single bus, and the multiple slaves each include an interface module, a power management module, a microprocessor module, a clock module and a storage module;
  • the communication method of the single bus system includes the following steps:
  • the host sends a reset signal in a specific time slot through the single bus for selecting the corresponding slave and querying the status of the corresponding slave;
  • the host After receiving the response signal, the host sends serial signals such as instructions/addresses/data through the single bus;
  • the slave receives serial signals such as instructions/addresses/data through the single bus, and the microprocessor module decodes the serial signals such as instructions/addresses/data to generate corresponding internal signals for controlling the operation of other modules in the slave.
  • the interface module is electrically connected to the host via the single bus for exchanging input data and output data;
  • the microprocessor module is electrically connected to other modules in the slave respectively, and is used to receive instruction information and data information, and convert them into corresponding internal signals to control the operation of other modules in the slave;
  • the power management module is electrically connected to other modules in the slave respectively for power supply;
  • the clock module is electrically connected to the microprocessor module to provide a clock signal
  • the storage module is electrically connected to the microprocessor module for storing and reading data.
  • a parasitic power supply circuit is arranged inside the power management module.
  • the power management module supplies power to other modules in the slave machine on the one hand, and charges the internal parasitic power supply circuit on the other hand.
  • the parasitic power supply circuit supplies power to other modules in the slave machine.
  • the clock frequency of the clock module can be changed through configuration information.
  • different time slots of the reset signal and the response signal correspond one-to-one to the plurality of slaves, and the slave only responds to the reset signal of the corresponding time slot.
  • the write-0 time slot of the host is greater than the maximum value of the slave sampling signal, and the write-1 time slot of the host is less than the minimum value of the slave sampling signal.
  • the signal time slot sent by the slave on the single bus, the write 0 time slot of the slave is greater than the maximum value of the host sampling signal, and the write 1 time slot of the slave is less than the minimum value of the host sampling signal.
  • the present invention utilizes reset and response signals of different time slots to realize the selection and inquiry of any slave by the host in the single bus system. Compared with the selection and inquiry method of identity information verification in the existing single bus system communication technology, it not only reduces the communication time and complexity, but also the physical encryption method with one-to-one correspondence between the reset time slot and the response time slot further improves information security.
  • FIG1 is a schematic diagram of a single bus system connection according to an embodiment of the present invention.
  • FIG2 is a schematic diagram of the internal connection of a slave device in a single bus system according to an embodiment of the present invention
  • FIG. 3 is a step diagram of a communication method for a single bus system according to an embodiment of the present invention.
  • FIG4 is a timing diagram of a communication method of a single bus system according to an embodiment of the present invention.
  • FIG. 5 is a communication reset/response signal time slot diagram of a single bus system according to an embodiment of the present invention
  • FIG. 6 is a time slot diagram of a host communication reset/response signal of a single bus system according to an embodiment of the present invention
  • FIG. 7 is a time slot diagram of a slave communication reset/response signal in a single bus system according to an embodiment of the present invention.
  • the communication method of the single bus system proposed in the present invention utilizes reset and response signals of different time slots to realize the selection and inquiry of any slave by the host in the single bus system. Compared with the selection and inquiry method of identity information verification in the existing single bus system communication technology, it not only reduces the communication time and complexity, but also the physical encryption method with one-to-one correspondence between the reset time slot and the response time slot further improves information security.
  • the single bus system includes a host and N slaves, the host is connected to and communicates with the N slaves simultaneously through the single bus, and each slave includes an electrically connected interface module, a power management module, a microprocessor module, a clock module and a storage module.
  • the interface module is electrically connected to the host via a single bus for exchanging input data and output data;
  • the microprocessor module is electrically connected to other modules in the slave machine respectively, and is used to receive instruction information and data information, and convert them into corresponding internal signals to control the work of other modules in the slave machine;
  • the power management module is electrically connected to other modules in the slave respectively to supply power to other modules;
  • the clock module is electrically connected to the microprocessor module for providing a clock signal
  • the storage module is electrically connected to the microprocessor module for storing and reading data.
  • the power management module is equipped with a parasitic power supply circuit.
  • the power management module supplies power to other modules in the slave and charges the internal parasitic power supply circuit.
  • the parasitic power supply circuit supplies power to other modules in the slave. This ensures that the power management module can supply power to other modules regardless of whether the single bus level is high or low, thus ensuring the normal operation of the single bus system.
  • the clock frequency of the clock module can be changed through configuration information.
  • a communication method of a single bus system of the present invention comprises the following steps:
  • the host sends a reset signal in a specific time slot through a single bus to select the corresponding slave and inquire about the status of the corresponding slave;
  • the slave After the slave receives the reset signal of a specific time slot, it sends a response signal of a specific time slot through a single bus;
  • the host After receiving the response signal, the host sends serial signals such as command/address/data through the single bus;
  • the slave receives serial signals such as instructions/addresses/data through a single bus.
  • the microprocessor decodes the serial signals such as instructions/addresses/data and generates corresponding internal signals to control the operation of other modules in the slave.
  • the timing sequence of the communication method of the single bus system in this embodiment is:
  • the host sends a reset signal #1 in a specific time slot via the single bus; the single bus does not reply with an acknowledge signal, which means that the slave selected/queried by the host does not exist or is busy.
  • the host sends a reset signal #2 at a specific time slot via the single bus;
  • the slave After receiving the reset signal #2 of the specific time slot, the slave sends the response signal #2 of the specific time slot through the single bus;
  • the host After receiving the response signal #2, the host sends the serial signal "11001100" of the read ID command through the single bus;
  • the slave receives the ID read instruction serial signal through the single bus, and the microprocessor decodes the ID read instruction serial signal to generate a corresponding internal signal to control the slave to send the local ID data "01100011" through the single bus.
  • the host sends a reset signal #3 at a specific time slot via the single bus;
  • the slave After receiving the reset signal #3 of the specific time slot, the slave sends the response signal #3 of the specific time slot through the single bus;
  • the host After receiving the response signal #3, the host sends the serial signal "10011001" of the write ID command and the serial signal "01100100" of the write data through the single bus;
  • the slave receives the serial signal of the write ID instruction and the serial signal of the write data through the single bus.
  • the microprocessor decodes the serial signal of the write ID instruction and generates a corresponding internal signal to control the slave to update the local ID register data to "01100100” and write the ID data "01100100" at the same time.
  • different time slots of the reset signal and the response signal of the single bus of the present invention correspond one-to-one to multiple slaves, and the slaves only respond to the reset signal of the corresponding time slot.
  • the signal time slots sent by the host on the single bus of the present invention are such that the write-0 time slot of the host is greater than the maximum value of the slave sampling signal, and the write-1 time slot of the host is less than the minimum value of the slave sampling signal.
  • the signal timing of the slave device on the single bus of the present invention is that the write 0 time slot of the slave device is greater than the maximum value of the host sampling signal, and the write 1 time slot of the slave device is less than the minimum value of the host sampling signal.

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Abstract

本发明公开了一种单总线系统的通信方法，单总线系统包括主机和多个从机，主机通过单总线与多个从机通信，多个从机均包括接口模块、电源管理模块、微处理器模块、时钟模块和存储模块；单总线系统的通信方法包括以下步骤：S1.主机通过单总线发送特定时隙的复位信号，用于选择对应的从机和询问对应从机的状态；S2.从机接到特定时隙的复位信号后，通过单总线发送特定时隙的应答信号；S3.主机在接收应答信号后，通过单总线发送指令/地址/数据等串行信号；S4.从机通过单总线接收指令/地址/数据等串行信号，微处理器模块对指令/地址/数据等串行信号译码后产生对应的内部信号用以控制从机中其他模块的工作。其有益之处在于减少了通信时间和复杂度，且提高了信息安全度。

Description

单总线系统的通信方法 技术领域
本发明涉及集成电路设计的技术领域，更具体的说，本发明涉及一种单总线系统的通信方法。
 背景技术
单总线是美国DALLAS公司推出的外围串行扩展总线技术，与SPI、I²C串行数据通信方式不同，它采用单根信号线，既传输时钟又传输数据，而且数据传输是双向的，具有节省I/O口线、资源结构简单、成本低廉、便于总线扩展和维护等诸多优点。这种协议由一个总线主节点、或多个从节点组成系统，通过单根信号线对从芯片进行数据的读取。每一个符合单总线协议的从芯片都有一个唯一的地址，包括48位的序列号、8位的家族代码和8位的CRC代码。主芯片根据64位寻址对各个芯片进行双向通信，因此其协议对时序的要求较严格，初始化、写比特或读比特都有严格的时序要求。
在现有技术中，当单总线上挂有多个从机时，主机主要通过从机独有的身份信息来确认通信对象，即在实际通信前需要进行身份验证，这个过程限制了单总线通信的速度，此外，从机的身份信息主要是数字信号的传输，在需要加密保护的从机中存在被反向破解的可能性，降低了信息安全性。
 技术问题
本发明的目的在于为克服上述技术的不足而提供一种单总线系统的通信方法。
 技术解决方案
本发明的技术方案是这样实现的：一种单总线系统的通信方法，所述单总线系统包括主机和多个从机，所述主机通过单总线与多个所述从机通信，多个所述从机均包括接口模块、电源管理模块、微处理器模块、时钟模块和存储模块；所述单总线系统的通信方法包括以下步骤：
S1.所述主机通过所述单总线发送特定时隙的复位信号，用于选择对应的从机和询问对应从机的状态；
S2.所述从机接到特定时隙的复位信号后，通过所述单总线发送特定时隙的应答信号；
S3.所述主机在接收应答信号后，通过所述单总线发送指令/地址/数据等串行信号；
S4.所述从机通过所述单总线接收指令/地址/数据等串行信号，所述微处理器模块对指令/地址/数据等串行信号译码后产生对应的内部信号用以控制所述从机中其他模块的工作。
优选地，所述接口模块通过所述单总线与所述主机电连接用于输入数据和输出数据的交换；
所述微处理器模块分别与所述从机内的其他模块电连接，用于接收指令信息和数据信息，并转换为相应的内部信号来控制所述从机中其他模块的工作；
所述电源管理模块分别与所述从机内的其他模块电连接用于供电；
所述时钟模块与所述微处理器模块电连接用于提供时钟信号；
所述存储模块与所述微处理器模块电连接用于数据的存储和读取。
优选地，所述电源管理模块的内部设置有寄生供电电路，当所述单总线处于高电平时，所述电源管理模块一方面向所述从机中其他模块供电，另一方面对内部所述寄生供电电路充电，当所述单总线处于低电平时，所述寄生供电电路向所述从机中其他模块供电。
优选地，所述时钟模块的时钟频率可以通过配置信息改变。
优选地，所述复位信号和所述应答信号的不同时隙与多个所述从机一一对应，所述从机仅对相应时隙的复位信号做出应答。
优选地，所述主机在所述单总线上发送的信号时隙，所述主机的写0时隙大于所述从机采样信号的最大值，所述主机的写1时隙小于所述从机采样信号的最小值。
优选地，所述从机在所述单总线上发送的信号时隙，所述从机的写0时隙大于所述主机采样信号的最大值，所述从机的写1时隙小于所述主机采样信号的最小值。
 有益效果
本发明利用不同时隙的复位和应答信号来实现单总线系统中主机对任一从机的选择和询问，相比现有单总线系统通信技术中身份信息验证的选择和询问方式，不仅减少了通信时间和复杂度，而且这种复位时隙和应答时隙一一对应的物理加密方法，进一步提高了信息安全。
 附图说明
图1为本发明实施例的单总线系统连接示意图；
图2为本发明实施例的单总线系统的从机内部连接示意图；
图3为本发明实施例的单总线系统的通信方法步骤图；
图4为本发明实施例的单总线系统的通信方法的时序图；
图5为本发明实施例的单总线系统的通信复位/应答信号时隙图；
图6为本发明实施例的单总线系统的主机通信复位/应答信号时隙图；
图7为本发明实施例的单总线系统的从机通信复位/应答信号时隙图。
 本发明的最佳实施方式
本发明提出的单总线系统的通信方法，利用不同时隙的复位和应答信号来实现单总线系统中主机对任一从机的选择和询问，相比现有单总线系统通信技术中身份信息验证的选择和询问方式，不仅减少了通信时间和复杂度，而且这种复位时隙和应答时隙一一对应的物理加密方法，进一步提高了信息安全。
本发明的实施方式
下面将通过具体实施例对本发明进行详细说明。
如图1、图2所示，本发明的一种单总线系统的通信方法，单总线系统包括主机和N个从机，主机通过单总线同时与N个从机连接并通信，各个从机均包括电连接的接口模块、电源管理模块、微处理器模块、时钟模块和存储模块。
其中，接口模块通过单总线与主机电连接用于输入数据和输出数据的交换；
微处理器模块分别与从机内的其他模块电连接，用于接收指令信息和数据信息，并转换为相应的内部信号来控制从机中其他模块的工作；
电源管理模块分别与从机内的其他模块电连接用于供电给其他模块；
时钟模块与微处理器模块电连接用于提供时钟信号；
存储模块与微处理器模块电连接用于数据的存储和读取。
电源管理模块的内部设置有寄生供电电路，当单总线处于高电平时，电源管理模块一方面向从机中其他模块供电，另一方面对内部寄生供电电路充电，当单总线处于低电平时，寄生供电电路向从机中其他模块供电。这样可确保电源管理模块无论单总线的电平高与低时，均可为其他模块供电，保证单总线系统的正常工作。
时钟模块的时钟频率可以通过配置信息改变。
如图3所示，本发明一种单总线系统的通信方法，包括以下步骤：
S1.主机通过单总线发送特定时隙的复位信号，用于选择对应的从机和询问对应从机的状态；
S2.从机接到特定时隙的复位信号后，通过单总线发送特定时隙的应答信号；
S3.主机在接收应答信号后，通过单总线发送指令/地址/数据等串行信号；
S4.从机通过单总线接收指令/地址/数据等串行信号，微处理器对指令/地址/数据等串行信号译码后产生对应的内部信号控制从机中其他模块的工作。
如图4所示，本实施例中单总线系统的通信方法的时序为：
1、主机通过单总线发送特定时隙的复位信号#1；单总线无应答信号回复，即主机选择/询问的从机不存在或者忙碌。
2、主机通过单总线发送特定时隙的复位信号#2；
从机接到特定时隙的复位信号#2后，通过单总线发送特定时隙的应答信号#2；
主机在接收应答信号#2后，通过单总线发送读ID指令的串行信号“11001100”；
从机通过单总线接收读ID指令串行信号，微处理器对读ID指令串行信号译码后产生对应的内部信号控制从机通过单总线发送本机ID数据“01100011”。
3、主机通过单总线发送特定时隙的复位信号#3；
从机接到特定时隙的复位信号#3后，通过单总线发送特定时隙的应答信号#3；
主机在接收应答信号#3后，通过单总线发送写ID指令的串行信号“10011001”和写入数据的串行信号“01100100”；
从机通过单总线接收写ID指令的串行信号和写入数据的串行信号，微处理器对写ID指令串行信号译码后产生对应的内部信号控制从机更新本机ID寄存器数据为“01100100”，同时写入ID数据“01100100”。
如图5所示，本发明单总线的复位信号和应答信号的不同时隙与多个从机一一对应，从机仅对相应时隙的复位信号做出应答。
如图6所示，本发明主机在单总线上发送的信号时隙，主机的写0时隙大于从机采样信号的最大值，主机的写1时隙小于从机采样信号的最小值。
如图7所示，本发明从机在单总线上发送的信号时序，从机的写0时隙大于主机采样信号的最大值，从机的写1时隙小于主机采样信号的最小值。
 工业实用性
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，皆应属本发明权利要求的涵盖范围。

Claims (7)

  1. 一种单总线系统的通信方法，其特征在于，所述单总线系统包括主机和多个从机，所述主机通过单总线与多个所述从机通信，多个所述从机均包括接口模块、电源管理模块、微处理器模块、时钟模块和存储模块；所述单总线系统的通信方法包括以下步骤：
    S1.所述主机通过所述单总线发送特定时隙的复位信号，用于选择对应的从机和询问对应从机的状态；
    S2.所述从机接到特定时隙的复位信号后，通过所述单总线发送特定时隙的应答信号；
    S3.所述主机在接收应答信号后，通过所述单总线发送指令/地址/数据等串行信号；
    S4.所述从机通过所述单总线接收指令/地址/数据等串行信号，所述微处理器模块对指令/地址/数据等串行信号译码后产生对应的内部信号用以控制所述从机中其他模块的工作。
  2. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述接口模块通过所述单总线与所述主机电连接用于输入数据和输出数据的交换；
    所述微处理器模块分别与所述从机内的其他模块电连接，用于接收指令信息和数据信息，并转换为相应的内部信号来控制所述从机中其他模块的工作；
    所述电源管理模块分别与所述从机内的其他模块电连接用于供电；
    所述时钟模块与所述微处理器模块电连接用于提供时钟信号；
    所述存储模块与所述微处理器模块电连接用于数据的存储和读取。
  3. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述电源管理模块的内部设置有寄生供电电路，当所述单总线处于高电平时，所述电源管理模块一方面向所述从机中其他模块供电，另一方面对内部所述寄生供电电路充电，当所述单总线处于低电平时，所述寄生供电电路向所述从机中其他模块供电。
  4. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述时钟模块的时钟频率可以通过配置信息改变。
  5. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述复位信号和所述应答信号的不同时隙与多个所述从机一一对应，所述从机仅对相应时隙的复位信号做出应答。
  6. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述主机在所述单总线上发送的信号时隙，所述主机的写0时隙大于所述从机采样信号的最大值，所述主机的写1时隙小于所述从机采样信号的最小值。
  7. 根据权利要求1所述单总线系统的通信方法，其特征在于，所述从机在所述单总线上发送的信号时隙，所述从机的写0时隙大于所述主机采样信号的最大值，所述从机的写1时隙小于所述主机采样信号的最小值。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276678A (en) * 1990-06-18 1994-01-04 Intelect, Inc. Distributed switching and telephone conferencing system
CN104657303A (zh) * 2014-10-13 2015-05-27 江苏瑞微电子有限公司 单总线数据通信方法
CN112564882A (zh) * 2020-11-26 2021-03-26 北京工业大学 一种基于ahb总线的单线数字通讯接口
CN116303204A (zh) * 2023-03-07 2023-06-23 张夕勇 单总线系统的通信方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276678A (en) * 1990-06-18 1994-01-04 Intelect, Inc. Distributed switching and telephone conferencing system
CN104657303A (zh) * 2014-10-13 2015-05-27 江苏瑞微电子有限公司 单总线数据通信方法
CN112564882A (zh) * 2020-11-26 2021-03-26 北京工业大学 一种基于ahb总线的单线数字通讯接口
CN116303204A (zh) * 2023-03-07 2023-06-23 张夕勇 单总线系统的通信方法

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