WO2024180908A1 - Élément d'imagerie à semi-conducteurs, dispositif de photodétection, et procédé de fabrication d'élément d'imagerie à semi-conducteurs - Google Patents

Élément d'imagerie à semi-conducteurs, dispositif de photodétection, et procédé de fabrication d'élément d'imagerie à semi-conducteurs Download PDF

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WO2024180908A1
WO2024180908A1 PCT/JP2024/000159 JP2024000159W WO2024180908A1 WO 2024180908 A1 WO2024180908 A1 WO 2024180908A1 JP 2024000159 W JP2024000159 W JP 2024000159W WO 2024180908 A1 WO2024180908 A1 WO 2024180908A1
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transistor
source
current
circuit
sample
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PCT/JP2024/000159
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English (en)
Japanese (ja)
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健一郎 安城
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ソニーセミコンダクタソリューションズ株式会社
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

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  • This technology relates to solid-state imaging devices. More specifically, it relates to a solid-state imaging device provided with a current source transistor, a photodetector, and a method for manufacturing a solid-state imaging device.
  • CMOS Image Sensors have used a global shutter method in which all pixels are exposed simultaneously in order to suppress rolling shutter distortion.
  • a solid-state imaging element has been proposed in which a capacitive element is provided for each pixel and a voltage is sampled and held in the capacitive element (see, for example, Non-Patent Document 1).
  • an nMOS (n-channel Metal Oxide Semiconductor) transistor with its source grounded and its gate to which a bias voltage is applied is arranged for each pixel as a current source.
  • a capacitive element is provided for each pixel, and the voltage is sampled and held to achieve the global shutter method.
  • the gate-source voltage of the nMOS transistor of the current source can vary from pixel to pixel due to factors such as ground bounce when the pixel is driven. As a result, there is a problem in that the current flowing through the nMOS transistor of the current source varies from pixel to pixel.
  • This technology was developed in light of these circumstances, and aims to suppress current variations in solid-state imaging devices that have a current source transistor for each pixel.
  • This technology has been made to solve the problems mentioned above, and its first aspect is a solid-state imaging device having a plurality of pixels, each of which is provided with a current source transistor whose source is connected to a ground node and which supplies a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the ground node, and a sample-and-hold switch which samples and holds a predetermined bias voltage in the capacitance element during a period in which the drain-source current is not supplied, and a control method thereof.
  • This has the effect of suppressing current variations.
  • the device may further include an amplifier transistor that amplifies the voltage of the floating diffusion layer and outputs it from a source, and a switch circuit that opens and closes a path between the amplifier transistor and the current source transistor, and the sample-and-hold switch may sample and hold the bias voltage in the capacitive element while the switch circuit is in an open state. This provides the effect of holding the bias voltage.
  • a sample-and-hold circuit may be further provided that holds both a signal level corresponding to the amount of exposure and a predetermined reset level. This provides the effect of realizing a global shutter.
  • the switch circuit may include at least one of a switch transistor that opens and closes a path between the source of the amplifier transistor and a previous-stage node connected to the sample-and-hold circuit, and a precharge transistor that opens and closes a path between the previous-stage node and the drain of the current source transistor. This provides the effect of cutting off the current by controlling the transistor.
  • a mirror source transistor through which a predetermined reference current flows may be further provided, and the sample-and-hold switch may open and close a path between the gate and drain of the mirror source transistor and the gate of the current source transistor. This provides the effect of supplying a current according to the reference current.
  • the current source transistor, the capacitance element, and the sample-and-hold switch may be arranged in any one of a plurality of stacked semiconductor chips. This has the effect of facilitating miniaturization of pixels.
  • each of the plurality of pixels may detect the presence or absence of an address event. This has the effect of suppressing the variation in the current of the pixel that detects the address event.
  • the second aspect of the present technology is a photodetector device comprising a plurality of pixels, each of which is provided with a current source transistor whose source is connected to a ground node and which supplies a predetermined drain-source current, a capacitance element inserted between the gate of the current source transistor and the ground node, and a sample-and-hold switch which samples and holds a predetermined bias voltage in the capacitance element during a period in which the drain-source current is not being supplied, and a signal processing circuit which processes pixel signals from each of the plurality of pixels.
  • 1 is a block diagram showing a configuration example of an imaging device according to a first embodiment of the present technology
  • 1 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology
  • 1 is a circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology
  • 1 is a circuit diagram showing a configuration example of an accessory according to a first embodiment of the present technology
  • 4 is a timing chart showing an example of an operation of the solid-state imaging element according to the first embodiment of the present technology.
  • FIG. 4 is a graph showing an example of characteristics of a current source transistor according to the first embodiment of the present technology
  • FIG. 11 is a circuit diagram showing an example of a state of a solid-state imaging element in a comparative example.
  • 4A to 4C are diagrams illustrating an example of a state of a solid-state imaging element during sample-and-hold in the first embodiment of the present technology;
  • 1A to 1C are diagrams illustrating an example of a state of a solid-state imaging element after a pixel is sampled and held according to a first embodiment of the present technology.
  • 3 is a diagram showing an example of a layout of a sample-and-hold switch, a capacitance element, and a current source transistor according to the first embodiment of the present technology;
  • FIG. 4 is a flowchart showing an example of an operation of the solid-state imaging element according to the first embodiment of the present technology.
  • 1 is a circuit diagram showing a configuration example of a pixel according to a first modified example of the first embodiment of the present technology
  • 13 is a circuit diagram showing another example of a pixel in the first modified example of the first embodiment of the present technology.
  • FIG. 11 is a circuit diagram showing a configuration example of a pixel in which the number of transistors is reduced according to a first modified example of the first embodiment of the present technology.
  • FIG. 13 is a diagram showing an example of a layered structure of a solid-state imaging element according to a second embodiment of the present technology;
  • FIG. 11 is a circuit diagram showing a configuration example of a pixel according to a second embodiment of the present technology.
  • FIG. 13 is a block diagram showing a configuration example of a solid-state imaging element according to a third embodiment of the present technology.
  • FIG. 13 is a circuit diagram showing a configuration example of a pixel according to a third embodiment of the present technology.
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system;
  • FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit.
  • First embodiment example of sampling and holding in a capacitive element while current is stopped
  • Second embodiment example of sampling and holding in a capacitive element while current is stopped in a stacked structure
  • Third embodiment example of detecting an address event by sampling and holding in a capacitive element while the current is stopped
  • First embodiment [Configuration example of imaging device] 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology.
  • the imaging device 100 is a device that captures image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130.
  • the imaging device 100 is assumed to be a digital camera or an electronic device having an imaging function (such as a smartphone or a personal computer).
  • the imaging device 100 is an example of a light detection device described in the claims.
  • the solid-state imaging element 200 captures image data under the control of the imaging control unit 130.
  • the solid-state imaging element 200 supplies the image data to the recording unit 120 via a signal line 209.
  • the imaging lens 110 collects light and guides it to the solid-state imaging element 200.
  • the imaging control unit 130 controls the solid-state imaging element 200 to capture image data.
  • the imaging control unit 130 supplies imaging control signals including, for example, a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139.
  • the recording unit 120 records the image data.
  • the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.
  • the imaging device 100 records image data
  • the image data may also be transmitted to the outside of the imaging device 100.
  • an external interface for transmitting the image data is further provided.
  • the imaging device 100 may further display the image data.
  • a display unit is further provided.
  • FIG. 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to the first embodiment of the present technology.
  • the solid-state imaging element 200 is a CIS, and includes a vertical scanning circuit 211, an accessory 220, and a pixel array section 230.
  • the solid-state imaging element 200 further includes a timing control circuit 212, a digital to analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260.
  • a plurality of pixels 300 are arranged in a two-dimensional lattice in the pixel array section 230.
  • Each circuit in the solid-state imaging element 200 is provided, for example, on a single semiconductor chip.
  • a set of pixels 300 arranged in the horizontal direction will be referred to as a "row,” and a set of pixels 300 arranged in a direction perpendicular to the rows will be referred to as a "column.”
  • the timing control circuit 212 controls the operation timing of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control unit 130.
  • the DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion.
  • the DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.
  • the vertical scanning circuit 211 sequentially selects and drives the rows to output analog pixel signals.
  • the pixels 300 perform photoelectric conversion of incident light to generate analog pixel signals.
  • the pixels 300 supply pixel signals to the column signal processing circuit 260 via the load MOS circuit block 250.
  • the accessory 220 is provided with a mirror source transistor that forms a current mirror circuit with a current source transistor (not shown) in the pixel.
  • MOS transistors that supply a constant current are provided for each column.
  • the column signal processing circuit 260 performs signal processing such as AD (Analog to Digital) conversion processing and CDS (Correlated Double Sampling) processing on pixel signals for each column.
  • This column signal processing circuit 260 supplies image data consisting of the processed signals to the recording unit 120.
  • Note that the column signal processing circuit 260 is an example of a signal processing circuit as described in the claims.
  • FIG. 3 is a circuit diagram showing a configuration example of a pixel 300 in the first embodiment of the present technology.
  • the pixel 300 includes a front-stage circuit 310, a sample-and-hold circuit 350, and a rear-stage circuit 360.
  • the front-stage circuit 310 includes a photoelectric conversion element 311, a transfer transistor 312, a front-stage reset transistor 313, a floating diffusion (FD) 314, and a front-stage amplification transistor 315.
  • the front-stage circuit 310 further includes a switch circuit 330, a current source transistor 317, a capacitance element 318, and a sample-and-hold switch 319.
  • the switch circuit 330 includes a switch transistor 331.
  • the pixel 300 further includes a conversion efficiency control transistor 320, a capacitance element 321, and a precharge transistor 332.
  • a selector 308 is added for each column.
  • an nMOS transistor is used as each transistor in the front-stage circuit 310.
  • the photoelectric conversion element 311 converts incident light into an electric charge and generates an electric charge.
  • the transfer transistor 312 transfers the electric charge from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal TRG from the vertical scanning circuit 211.
  • the previous stage reset transistor 313 initializes the FD 314 in accordance with a reset signal RST from the vertical scanning circuit 211.
  • FD314 accumulates electric charge and generates a voltage according to the amount of charge.
  • the voltage when FD314 is initialized is referred to as the "reset level,” and the voltage when electric charge is transferred to FD314 is referred to as the “signal level.”
  • the pre-amplification transistor 315 amplifies the voltage of the FD 314 and outputs it from the source. Note that the pre-amplification transistor 315 is an example of an amplification transistor as described in the claims.
  • the switch transistor 331 opens and closes the path between the source of the pre-amplification transistor 315 and the drain of the current source transistor 317 in accordance with a control signal SW from the vertical scanning circuit 211.
  • the connection node between the switch transistor 331 and the current source transistor 317 is referred to as the pre-stage node 316.
  • the current source transistor 317 supplies a constant drain-source current I ds according to the voltage applied to the gate, and the source of the current source transistor 317 is connected to the ground node.
  • the capacitive element 318 is inserted between the gate and source (in other words, the ground node) of the current source transistor 317.
  • the sample-and-hold switch 319 opens and closes the path between the accessory 220 and the gate of the current source transistor 317 according to a control signal SH from the vertical scanning circuit 211.
  • the vertical scanning circuit 211 turns on the switch transistors 331 of all pixels using the control signal SW. This causes the drain-source current I ds to flow through the current source transistors 317 of all pixels.
  • the gate-source voltage V gs of the current source transistors 317 may vary from pixel to pixel. This variation in the gate-source voltage V gs is caused by the following two factors.
  • the first is ground bounce on the pixel side, which occurs due to IR drop caused by the DC current itself within the pixel.
  • a bounce of about several tens of millivolts (mV) is still unavoidable.
  • the second is variation in the bias voltage VB due to ground bounce on the accessory 220 side.
  • the accessory 220 is placed outside the pixel array unit 230, it is easy to take measures against the ground bounce for the second reason. For this reason, the impact of the first factor is large.
  • a capacitive element 318 and a sample-and-hold switch 319 are provided, and while the switch transistor 331 is in the off state, the vertical scanning circuit 211 switches the sample-and-hold switch 319 from a closed state to an open state using a control signal SH. This causes the bias voltage VB to be sampled and held by the capacitive element 318.
  • Cs should be about 10 femtofarads (fF). With a capacitance value of this order, it is possible to appropriately balance the area of the capacitive element 318 and the ability of the power supply side potential to follow the bounce.
  • the sample-and-hold circuit 350 holds both a signal level corresponding to the amount of exposure and a predetermined reset level.
  • This sample-and-hold circuit 350 includes capacitance elements 351 and 352, selection transistors 353 and 354, and a rear-stage reset transistor 355.
  • an nMOS transistor is used as each transistor in the sample-and-hold circuit 350.
  • Capacitive elements 351 and 352 hold the voltage (reset level or signal level) output from previous stage circuit 310.
  • capacitive element 351 holds the reset level
  • capacitive element 352 holds the signal level.
  • elements having a MIM (Metal Insulator Metal) structure are used as these capacitive elements.
  • one end of each of these capacitive elements 351 and 352 is commonly connected to previous stage node 316.
  • the selection transistor 353 opens and closes the path between the other end of the capacitance element 351 and the subsequent node 356 in accordance with a selection signal S1 from the vertical scanning circuit 211.
  • the selection transistor 354 opens and closes the path between the other end of the capacitance element 352 and the subsequent node 356 in accordance with a selection signal S2 from the vertical scanning circuit 211.
  • the rear-stage reset transistor 355 initializes the voltage of the rear-stage node 356 to a predetermined potential VREG in accordance with a rear-stage reset signal RB from the vertical scanning circuit 211.
  • the potential VREG is set to a potential different from the power supply voltage VDD (for example, a potential lower than VDD).
  • the rear circuit 360 includes a rear amplifier transistor 361 and a rear selection transistor 362. These transistors may be, for example, nMOS transistors.
  • the rear-stage amplification transistor 361 amplifies the voltage of the rear-stage node 356.
  • the rear-stage selection transistor 362 outputs the voltage signal amplified by the rear-stage amplification transistor 361 to the vertical signal line 309 as a pixel signal in accordance with a selection signal SEL from the vertical scanning circuit 211.
  • the conversion efficiency control transistor 320 controls the conversion efficiency of converting electric charge into voltage in accordance with a control signal FDG from the vertical scanning circuit 211.
  • the conversion efficiency control transistor 320 is in the on state, the capacitance element 321 is connected to the FD 314, and the conversion efficiency is low.
  • the conversion efficiency control transistor 320 is in the off state, the electric charge is converted into voltage only by the FD 314, and the conversion efficiency is high.
  • an element with an MIM structure is used as the capacitance element 321.
  • the selector 308 selects either the power supply voltage VDD or the voltage Vread according to a selection signal sel from the vertical scanning circuit 211, and supplies it to the drain of the pre-amplification transistor 315 as a drain voltage VAMD.
  • the sample-and-hold circuit 350 samples and holds a voltage
  • the power supply voltage VDD is selected.
  • the voltage Vread is selected.
  • Vread is set to a value shown in the following formula.
  • Vread VDD-Vgs-Vft...Formula 2
  • Vgs is the gate-source voltage of the pre-stage amplifying transistor 315.
  • Vft is the amount of fluctuation in the potential of the FD 314 due to the reset feedthrough of the pre-stage reset transistor 313.
  • the preamplification transistor 315 is turned off, reducing noise generated by that transistor.
  • the precharge transistor 332 is disposed within the switch circuit 330 and opens and closes the path between the previous node 316 and the current source transistor 317 in accordance with a control signal PC from the vertical scanning circuit 211.
  • both the switch transistor 331 and the precharge transistor 332 are arranged in the switch circuit 330, it is also possible to arrange only one of them.
  • the sample-and-hold switch 319 samples and holds the bias voltage VB while at least one of the two transistors in the switch circuit 330 is in the off state.
  • pMOS p-channel Metal Oxide Semiconductor
  • the vertical scanning circuit 211 can also control the transfer signal TRG, reset signal RST, and control signal FDG to any of high level, middle level, and low level.
  • the high level is set to a value higher than "0" volts (V).
  • the middle level is set to a value lower than the high level, for example, "0" volts (V).
  • the low level is set to a value lower than the middle level, for example, "-1" volts (V).
  • the transfer transistor 312, previous stage reset transistor 313, and conversion efficiency control transistor 320 corresponding to these signals are driven in three values.
  • the vertical scanning circuit 211 When the vertical scanning circuit 211 holds the reset level in the capacitive element 351, it can soft-reset the pre-amplification transistor 315 by changing the transfer signal TRG, the reset signal RST, and the control signal FDG from a middle level to a low level. This reduces kTC noise.
  • the conversion efficiency control transistor 320, the capacitance element 321, the selector 308, and the precharge transistor 332 are all arranged, this is not limiting and some of these may be omitted.
  • the vertical scanning circuit 211 drives some of the transistors in three-value driving, if soft reset is not required, these transistors may also be driven in two-value driving.
  • three pMOS transistors are arranged in the sample hold circuit 350, some or all of these may be nMOS transistors.
  • [Accessories configuration example] 4 is a circuit diagram showing a configuration example of the accessory 220 according to the first embodiment of the present technology.
  • the accessory 220 includes a reference current source 221 and a plurality of mirror source transistors 222. If the mirror source transistors 222 are arranged for each row and the number of rows is N (N is an integer), the number of mirror source transistors 222 is N. For example, nMOS transistors are used as the mirror source transistors 222.
  • the reference current source 221 supplies a predetermined reference current I ref .
  • the gate and drain of each mirror source transistor 222 are connected to the reference current source 221, and the source is connected to a ground node.
  • the sample-and-hold switch 319 opens and closes a path between the gate and drain of the mirror source transistor 222 in the corresponding row and the gate of the current source transistor 317. Note that in the figure, elements other than the current source transistor 317, the capacitance element 318, and the sample-and-hold switch 319 are omitted in each pixel 300.
  • a current mirror circuit is formed by the mirror source transistor 222 and the corresponding current source transistor 317. If the switch transistor 331 (not shown) is in an on state when the sample-and-hold switch 319 is in a closed state, a drain-source current I ds corresponding to the reference current I ref flows through the current source transistor 317.
  • the vertical scanning circuit 211 uses the control signal SH to transition the sample-and-hold switch 319 from the on state to the off state. This causes the gate voltage of the mirror source transistor 222 to be sampled and held in the capacitive element 318 as the bias voltage VB.
  • the vertical scanning circuit 211 turns on the switch transistor 331. At this time, since the bias voltage VB is held in the capacitance element 318, a drain-source current Ids corresponding to the mirror source reference current Iref flows through the current source transistor 317.
  • FIG. 5 is a block diagram showing an example of the configuration of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.
  • a vertical signal line 309 is wired to the load MOS circuit block 250 for each column. If the number of columns is I (I is an integer), then I vertical signal lines 309 are wired. In addition, a load MOS transistor 251 that supplies a constant current is connected to each vertical signal line 309.
  • the column signal processing circuit 260 has a plurality of ADCs (Analog to Digital Converters) 261 and a digital signal processing unit 262.
  • the ADCs 261 are arranged for each column. If the number of columns is I, then I ADCs 261 are arranged.
  • the ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213.
  • This ADC 261 supplies the digital signal to the digital signal processor 262.
  • a single-slope ADC equipped with a comparator and a counter is disposed as the ADC 261.
  • the digital signal processing unit 262 performs predetermined signal processing, such as CDS processing, on each digital signal for each column.
  • the digital signal processing unit 262 supplies image data consisting of the processed digital signals to the recording unit 120.
  • FIG. 6 is a timing chart showing an example of the operation of the solid-state imaging device 200 in the first embodiment of the present technology.
  • the vertical scanning circuit 211 drives all pixels to start exposure at the same time. That is, exposure is performed by a global shutter method.
  • the vertical scanning circuit 211 drives all pixels to hold voltages (reset level and signal level).
  • the vertical scanning circuit 211 drives the rows in sequence to read out the voltages and perform AD (Analog to Digital) conversion.
  • AD Analog to Digital
  • the control signal SW is at a low level, and the control signal SH is at a high level.
  • the vertical scanning circuit 211 changes the control signal SH from a high level to a low level. This causes the bias voltage to be sampled and held in the capacitive element 318 in the pixel.
  • the vertical scanning circuit 211 sets the control signal FDG, the reset signal RST, the control signal SW, and the control signal PC to high level. This initializes the FD 314 and the subsequent nodes.
  • the vertical scanning circuit 211 sets the control signal FDG and the reset signal RST to a middle level. This determines the reset level state, and the previous node is in a potential state buffered by the previous stage amplification transistor 315.
  • the vertical scanning circuit 211 sets the selection signals S1 and S2 to a low level, and immediately thereafter at timing T5, returns the selection signal S2 to a high level. This causes the reset level to be sampled in the capacitive element 351.
  • the vertical scanning circuit 211 changes the transfer signal TRG, the reset signal RST, and the control signal FDG from the middle level to the low level, and changes the control signal PC from the high level to the low level.
  • the vertical scanning circuit 211 sets the rear-stage reset signal RB to a high level. This also turns off the rear-stage reset transistor 355 on the right side of the capacitive element 351.
  • the vertical scanning circuit 211 sets the selection signal S1 to a high level. This also turns off the selection transistor 353.
  • the vertical scanning circuit 211 returns the transfer signal TRG, the reset signal RST, and the control signal FDG to the middle level, and returns the control signal PC to the high level. This makes it possible to recover the charge lost at timing T6 and prevent the loss of information at the reset level.
  • the vertical scanning circuit 211 sets the transfer signal TRG to a high level and the selection signal S2 to a low level. This causes charge to be transferred to the FD 314.
  • the vertical scanning circuit 211 sets the transfer signal TRG to a middle level. This causes the signal level to be sampled by the capacitive element 352.
  • the vertical scanning circuit 211 sets the subsequent reset signal RB to low level, and immediately thereafter sets the transfer signal TRG, the reset signal RST, and the control signal FDG to low level.
  • the vertical scanning circuit 211 returns the subsequent reset signal RB to high level. This initializes the subsequent node.
  • the vertical scanning circuit 211 sets the selection signal S2 to a high level and returns the transfer signal TRG, the reset signal RST, and the control signal FDG to the middle level. This causes the selection transistor 354 to be turned off, and the signal level is held in the capacitance element 352.
  • control signal SW is controlled to a middle level. Also, the selection signals S1 and S2 are controlled to a high level in turn, and the reset level and the signal level are read out in turn.
  • the vertical scanning circuit 211 keeps the switch transistor 331 on during the sample and hold period, this control is not limited to this.
  • the vertical scanning circuit 211 can also alternately turn on and off the switch transistor 331 and the precharge transistor 332 during the sample and hold period. This makes it possible to speed up the settling of the previous node from a high level to a low level, improving responsiveness.
  • the control signal SH is controlled to change from a high level to a low level, whereby the bias voltage is sampled and held in the capacitance element 318 in the pixel.
  • FIG. 7 is a graph showing an example of the characteristics of the current source transistor 317 according to the first embodiment of the present technology.
  • the vertical axis in the figure represents the drain-source current I ds of the current source transistor 317, and the horizontal axis represents the gate-source voltage V gs .
  • the current value per pixel must be set to a few nanoamperes (nA) in order to suppress power consumption, and this inevitably results in a current in a weak inversion region (in other words, a subthreshold region) below the threshold voltage Vth .
  • the drain-source current I ds is a power of the natural logarithm with a value according to the gate-source voltage V gs as the exponent.
  • the variation ⁇ I ds in the drain-source current I ds caused by the variation ⁇ V gs in the gate-source voltage V gs is much larger than when the same level of ⁇ V gs occurs in the strong inversion region.
  • FIG. 8 is a circuit diagram showing an example of the state of the solid-state imaging device 200 in a comparative example.
  • the capacitive element 318 and the sample-and-hold switch 319 are not provided in each pixel 300, and the gate and source of the mirror source transistor 222 are directly connected to the gate of the mirror destination current source transistor 317.
  • the current causes ground bounce, resulting in variations in ground voltage for each pixel.
  • the pixel at the top left of the figure has a ground voltage of 80 millivolts (mV)
  • the pixel at the top right has a ground voltage of 100 millivolts (mV).
  • bias voltage VB may vary due to ground bounce on the accessory side, but for the sake of convenience, we will assume that there is no variation in the bias voltage VB.
  • the gate-source voltage of the current source transistor 317 varies due to the variation in the ground voltage for each pixel.
  • the bias voltage VB is 180 millivolts (mV) and the ground voltage is 80 millivolts (mB), so the gate-source voltage is 100 millivolts (mV).
  • the bias voltage VB is 180 millivolts (mV) and the ground voltage is 100 millivolts (mB), so the gate-source voltage is 80 millivolts (mV).
  • This variation in the gate-source voltage causes the drain-source current I ds of the current source transistor 317 to vary for each pixel.
  • FIG. 9 is a diagram showing an example of the state of the solid-state imaging element when a pixel is sampled and held in the first embodiment of the present technology.
  • a shows the state of the solid-state imaging element when sampled by the sample-and-hold switch 319
  • b shows the state when held.
  • the switch transistor 331 (not shown) is in the off state in all pixels, and the supply of the drain-source current Ids of the current source transistor 317 is stopped.
  • the dotted arrow indicates that the supply of the drain-source current Ids is stopped.
  • no ground bounce occurs in each pixel, and the ground voltage of all pixels is, for example, 0 millivolts (mV).
  • bias voltage VB may vary due to ground bounce on the accessory side, but for the sake of convenience, we will assume that there is no variation in the bias voltage VB.
  • the vertical scanning circuit 211 closes the sample and hold switches 319 of all pixels. This causes the bias voltage VB to be sampled in the capacitive element 318.
  • the vertical scanning circuit 211 closes the sample hold switches 319 of all pixels. This causes the bias voltage VB of the capacitance element 318 to be held.
  • the vertical scanning circuit 211 turns on the switch transistors 331 (not shown) of all pixels, causing a drain-source current I ds to flow.
  • This current causes ground bounce, causing the ground voltage to vary from pixel to pixel.
  • the ground voltage in the upper left pixel of the figure is 80 millivolts (mV)
  • the ground voltage in the upper right pixel is 100 millivolts (mV).
  • the voltage on the voltage side of the capacitance element 318 rises by the amount of ground bounce.
  • the voltage on the power supply side rises from 140 millivolts (mV) to 220 millivolts (mV)
  • the voltage on the power supply side rises from 140 millivolts (mV) to 240 millivolts (mV).
  • FIG. 11 is a diagram showing an example of the layout of the sample-and-hold switch 319, the capacitance element 318, and the current source transistor 317 in the first embodiment of the present technology.
  • a MOS transistor is used as the sample-and-hold switch 319.
  • the gate of the transistor is connected to a signal line that supplies a control signal SH, and the source is connected to a signal line that supplies a bias voltage VB.
  • G", “D”, and “S” in the figure represent the gate, drain, and source of the MOS transistor.
  • the capacitance element 318 is, for example, the gate capacitance of a MOS transistor.
  • the drain and source of this transistor are connected to a node of the ground voltage VSS, and the gate is connected to a signal line that supplies the bias voltage VB.
  • the gate of the current source transistor 317 is connected to the connection node between the sample-and-hold switch 319 and the capacitance element 318, and the source is connected to the node of the ground voltage VSS.
  • FIG. 12 is a flowchart showing an example of the operation of the solid-state imaging device 200 in the first embodiment of the present technology. This operation is started, for example, when a specific application for capturing image data is executed.
  • the vertical scanning circuit 211 starts exposure of all pixels with the control signals SW of all pixels at low level (step S901). Then, while keeping the control signals SW at low level, the vertical scanning circuit 211 controls the sample and hold switches 319 of all pixels to sample and hold the bias voltage VB (step S902). Then, the vertical scanning circuit 211 sets the control signals SW of all pixels to high level, ending exposure of all pixels (step S903). Next, the solid-state imaging element 200 sequentially reads out all rows (step S904). After step S904, the solid-state imaging element 200 ends the operation for imaging.
  • the sample-and-hold switch 319 samples and holds the bias voltage VB in the capacitive element 318 while the drain-source current is stopped, so that the variation in the gate-source voltage can be suppressed. This makes it possible to suppress the variation in the drain-source current for each pixel.
  • the pixels 300 having the circuit configuration illustrated in Fig. 3 are arranged, but the circuit configuration of the pixels 300 is not limited to that illustrated in Fig. 3.
  • the solid-state imaging element 200 in this modified example of the first embodiment differs from the first embodiment in that it uses a circuit configuration different from that in Fig. 3.
  • FIG. 13 is a circuit diagram showing an example of the configuration of a pixel 300 in a modified example of the first embodiment of the present technology.
  • the pixel 300 in this modified example of the first embodiment differs from the first embodiment in that the downstream circuit has two systems.
  • Subsequent circuits 360-1 and 360-2 are arranged in pixel 300, subsequent stage amplification transistor 361-1 and subsequent stage selection transistor 362-1 are arranged in subsequent stage circuit 360-1, and subsequent stage selection transistor 362-1 is connected to vertical signal line 309-1.
  • Subsequent stage amplification transistor 361-2 and subsequent stage selection transistor 362-2 are arranged in subsequent stage circuit 360-2, and subsequent stage selection transistor 362-2 is connected to vertical signal line 309-2.
  • the circuit configuration illustrated in the figure makes it possible to suppress fluctuations in the level of the subsequent node.
  • the selection transistors 354 and 353 can be connected in series between the front-stage circuit 310 and the rear-stage circuit 360.
  • the capacitance element 351 is inserted between the rear-stage node 356 and the ground node.
  • the capacitance element 352 is inserted between the connection node of the selection transistors 354 and 353 and the ground node.
  • a sampling transistor 357 can be placed in place of the selection transistors 353 and 354 in the sample-and-hold circuit 350.
  • the sampling transistor 357 and the capacitance element 351 are connected in series between the front-stage circuit 310 and the rear-stage circuit 360.
  • the capacitance element 352 is inserted between the connection node of the sampling transistor 357 and the capacitance element 351 and the ground node.
  • the downstream circuit is divided into two systems, so that fluctuations in the level of the downstream node can be suppressed.
  • the circuits in the solid-state imaging element 200 are arranged on a single semiconductor chip, but this configuration may make it difficult to miniaturize the pixels.
  • the solid-state imaging element 200 in the second embodiment differs from the first embodiment in that the solid-state imaging element 200 has a layered structure.
  • the solid-state imaging element 200 of the second embodiment includes a lower chip 202 and an upper chip 201 stacked on the lower chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, they can also be connected by vias or bumps.
  • the upper chip 201 has an upper pixel array section 231 arranged thereon.
  • the lower chip 202 has a lower pixel array section 232 and a column signal processing circuit 260 arranged thereon. For each pixel in the pixel array section 230, a portion of the pixel is arranged in the upper pixel array section 231, and the remainder is arranged in the lower pixel array section 232.
  • the upper chip 201 and the lower chip 202 are examples of the multiple semiconductor chips described in the claims.
  • a vertical scanning circuit 211 Also arranged on the lower chip 202 are a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are omitted in the figure.
  • FIG. 17 is a circuit diagram showing an example of a configuration of a pixel 300 in the second embodiment of the present technology.
  • the elements in the front-stage circuit 310 other than the precharge transistor 332, the current source transistor 317, the capacitance element 318, and the sample and hold switch 319 are arranged on the upper chip 201.
  • the precharge transistor 332, the current source transistor 317, the capacitance element 318, the sample and hold switch 319, and the circuits following the sample and hold circuit 350 are arranged on the lower chip 202.
  • the area of the pixel can be reduced, making it easier to miniaturize the pixel.
  • elements and circuits can be distributed across three or more stacked semiconductor chips.
  • the circuits and elements within pixel 300 are distributed and arranged across two semiconductor chips, making it easier to miniaturize the pixel.
  • the capacitive element 318 and the sample-and-hold switch 319 are disposed in the CIS, but these circuits may be disposed in a sensor other than the CIS.
  • the third embodiment differs from the first embodiment in that the capacitive element 318 and the sample-and-hold switch 319 are disposed in an EVS (Event-based Vision Sensor).
  • FIG. 18 is a block diagram showing an example of the configuration of a solid-state imaging element 200 in the third embodiment of the present technology.
  • This solid-state imaging element 200 is an EVS, and includes a column arbiter 271, a column AER (Address Event Representation) circuit 272, a column address encoder 273, a pixel array section 400, and a state machine 277.
  • the solid-state imaging element 200 also includes a row address encoder 274, a row AER circuit 275, and a row arbiter 276.
  • a plurality of pixels 410 are arranged in a two-dimensional lattice in the pixel array section 400.
  • Each pixel in the pixel array unit 400 generates a differential signal indicating the amount of change in voltage corresponding to the photocurrent, and compares the level of the signal with a predetermined threshold. This comparison result indicates the detection result of an address event.
  • the threshold for comparison with the differential signal includes two different thresholds, the larger of which is set as the upper threshold, and the smaller of which is set as the lower threshold.
  • the address event includes an on event and an off event
  • the detection result includes the detection result of a 1-bit on event and the detection result of a 1-bit off event. An on event is detected when the differential signal exceeds the upper threshold, and an off event is detected when the differential signal falls below the lower threshold.
  • the pixel 410 When the pixel 410 detects an address event, it transmits and receives a request and a response (hereinafter referred to as a "handshake") between the row AER circuit 275 and the pixel 410 in order to output the address event detection result to the outside. Next, the pixel 410 performs a handshake with the column AER circuit 272.
  • a handshake a request and a response
  • the column arbiter 271 arbitrates requests from the column AER circuit 272 and transmits a response to the column AER circuit 272 based on the arbitration results.
  • the column AER circuit 272 transmits and receives (handshakes) requests and responses requesting external output of the address event detection results between each column, the column arbiter 271, and the state machine 277.
  • the column address encoder 273 encodes the address of the column in which the address event occurred and transmits it to the state machine 277.
  • the row address encoder 274 encodes the address of the row where the address event occurred and transmits it to the state machine 277.
  • the row arbiter 276 arbitrates requests from the row AER circuit 275 and transmits a response to the row AER circuit 275 based on the arbitration results.
  • the row AER circuit 275 transmits and receives (handshakes) requests and responses requesting external output of the address event detection results between each row, the row arbiter 276, and the state machine 277.
  • the state machine 277 performs handshake between the column AER circuit 272 and the row AER circuit 275.
  • the state machine 277 receives a request from the column AER circuit 272 and the row AER circuit 275, it decodes the data from the column address encoder 273 and the row address encoder 274 to identify the address where the address event was detected.
  • Image data is generated by arranging the address event detection results for each pixel in a two-dimensional grid.
  • the state machine 277 supplies the image data to the recording unit 120.
  • FIG. 19 is a circuit diagram showing an example of a configuration of a pixel 410 in the third embodiment of the present technology.
  • This pixel 410 includes a logarithmic response unit 420, a buffer 430, a differentiation circuit 440, a comparator 450, and an AER logic circuit 460.
  • the logarithmic response unit 420 includes a photoelectric conversion element 421, nMOS transistors 422 and 423, and a pMOS transistor 424.
  • the photoelectric conversion element 421 generates a photocurrent Ip as an electrical signal by photoelectric conversion of the incident light.
  • the pMOS transistor 424 and the nMOS transistor 423 are connected in series between the power supply and the ground terminal.
  • the gate of the nMOS transistor 422 is connected to the connection node of the pMOS transistor 424 and the nMOS transistor 423, the source is connected to the photoelectric conversion element 421, and the drain is connected to the power supply.
  • a bias voltage Vblog is applied to the gate of the pMOS transistor 424.
  • the gate of the nMOS transistor 423 is connected to the connection node of the nMOS transistor 422 and the photoelectric conversion element 421.
  • the logarithmic response unit 420 performs current-voltage conversion on the photocurrent Ip to generate the pixel voltage Vp.
  • the solid-state imaging element 200 has a structure in which an upper chip 201 and a lower chip 202 are stacked, and the photoelectric conversion element 421 and the nMOS transistors 422 and 423 are arranged on the upper chip 201.
  • the circuitry from the pMOS transistor 424 onwards is arranged on the lower chip 202.
  • the solid-state imaging element 200 has a layered structure, it can also be a single semiconductor chip instead of a layered structure.
  • the buffer 430 also includes pMOS transistors 431 and 432 connected in series between the power supply and the ground node.
  • the gate of the pMOS transistor 432 on the ground side is connected to the logarithmic response unit 420, and a bias voltage Vbsf is applied to the gate of the pMOS transistor 431 on the power supply side.
  • the connection point of the pMOS transistors 431 and 432 is connected to the differentiation circuit 440. This connection performs impedance conversion on the pixel voltage Vp, and the converted voltage signal is output to the differentiation circuit 440 as the output signal Vp'.
  • Differential circuit 440 includes capacitive elements 318, 441, and 444, pMOS transistors 442, 443, and 446, nMOS transistor 445, and sample-and-hold switch 319.
  • One end of the capacitance element 441 is connected to the buffer 430, and the other end is connected to one end of the capacitance element 444 and the gate of the pMOS transistor 443.
  • a reset signal xrst is input to the gate of the pMOS transistor 442, and the source and drain are connected to both ends of the capacitance element 444.
  • the pMOS transistor 443 and the nMOS transistor 445 are connected in series between the power supply and the ground terminal.
  • the other end of the capacitance element 444 is connected to the connection point of the pMOS transistor 443 and the nMOS transistor 445. This connection point is also connected to the comparator 450.
  • the nMOS transistor 445 is an example of a current source transistor as defined in the claims.
  • Capacitive element 318 is inserted between the gate and source of nMOS transistor 445.
  • pMOS transistor 446 supplies power supply voltage to the gate of pMOS transistor 443 in accordance with the initialization signal INI, turning pMOS transistor 443 off.
  • the reset signal xrst is at a high level
  • pMOS transistor 446 is periodically controlled to the off state by the initialization signal INI.
  • Sample-and-hold switch 319 samples and holds bias voltage VB in capacitive element 318, for example, when pMOS transistor 446 is turned off by the initialization signal INI and the current is cut off.
  • a differential signal indicating the amount of change in the output signal Vp' is generated and output to the comparator 450.
  • the differential signal is initialized by the reset signal xrst.
  • Comparator 450 includes pMOS transistors 451 and 453 and nMOS transistors 452 and 454.
  • pMOS transistor 451 and nMOS transistor 452 are connected in series between the power supply and the ground terminal, and pMOS transistor 453 and nMOS transistor 454 are also connected in series between the power supply and the ground terminal.
  • the gates of pMOS transistors 451 and 453 are connected to differentiation circuit 440.
  • a predetermined upper threshold Von is applied to the gate of nMOS transistor 452, and a predetermined lower threshold Voff is applied to the gate of nMOS transistor 454.
  • connection point between pMOS transistor 451 and nMOS transistor 452 is connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCH.
  • the connection point between pMOS transistor 453 and nMOS transistor 454 is also connected to AER logic circuit 460, and the voltage at this connection point is output as comparison result VCL.
  • comparator 450 outputs a high-level comparison result VCH when the differentiated signal exceeds the upper threshold Von, and outputs a low-level comparison result VCL when the differentiated signal falls below the lower threshold Voff.
  • This comparison result VCH indicates the detection result of an on-event
  • comparison result VCL indicates the detection result of an off-event.
  • the comparator 450 detects both on-events and off-events, it may detect only one of them. For example, when detecting only on-events, only the corresponding pMOS transistor 451 and nMOS transistor 452 are arranged.
  • the AER logic circuit 460 performs a handshake based on the comparison results VCH and VCL. When an address event occurs, the AER logic circuit 460 performs a handshake with the column arbiter 271. Next, the AER logic circuit 460 performs a handshake with the row arbiter 276, and resets the differentiation circuit 440 with the reset signal xrst.
  • the capacitive element 318 and the sample-and-hold switch 319 can also be arranged in sensors other than EVS and CIS, as long as the sensor has a current source transistor for each pixel.
  • the capacitive element 318 and the sample-and-hold switch 319 can also be arranged in a sensor that performs photon counting using a SPAD.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.
  • FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the body system control unit 12020 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 12020.
  • the body system control unit 12020 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle, and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface, based on the received images.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received.
  • the imaging unit 12031 can output the electrical signal as an image, or as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared light.
  • the in-vehicle information detection unit 12040 detects information inside the vehicle.
  • a driver state detection unit 12041 that detects the state of the driver is connected.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's degree of fatigue or concentration based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.
  • the microcomputer 12051 can calculate control target values for the driving force generating device, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040, and output control commands to the drive system control unit 12010.
  • the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an Advanced Driver Assistance System (ADAS), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 can also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching high beams to low beams.
  • the audio/image output unit 12052 transmits at least one output signal of audio and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the outside of the vehicle of information.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an on-board display and a head-up display.
  • FIG. 23 shows an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 12100.
  • the imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100.
  • the imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100.
  • the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.
  • FIG. 23 shows an example of the imaging ranges of the imaging units 12101 to 12104.
  • Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
  • imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively
  • imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door.
  • an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple imaging elements, or an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects, such as two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, based on the distance information obtained from the imaging units 12101 to 12104, and can use the data to automatically avoid obstacles.
  • the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or exceeds a set value and there is a possibility of a collision, it can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by forcibly decelerating or steering the vehicle to avoid a collision via the drive system control unit 12010.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured image of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian.
  • the audio/image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian.
  • the audio/image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology disclosed herein can be applied to, for example, the imaging unit 12031.
  • the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031.
  • the present technology can also be configured as follows. (1) a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current; a capacitance element inserted between the gate of the current source transistor and the ground node; and a sample-and-hold switch for sampling and holding a predetermined bias voltage in the capacitance element during a period in which the drain-source current is not supplied. (2) an amplifying transistor that amplifies the voltage of the floating diffusion layer and outputs it from its source; a switch circuit that opens and closes a path between the amplification transistor and the current source transistor,
  • the solid-state imaging device further comprising a sample-and-hold circuit for holding a signal level according to the amount of exposure and a predetermined reset level.
  • the switch circuit comprises: a switch transistor that opens and closes a path between a source of the amplifier transistor and a previous-stage node connected to the sample-and-hold circuit; and a precharge transistor that opens and closes a path between the previous node and a drain of the current source transistor.
  • (5) further comprising a mirror source transistor through which a predetermined reference current flows;
  • the solid-state imaging device according to any one of (1) to (4), wherein the sample-and-hold switch opens and closes a path between the gate and drain of the mirror source transistor and the gate of the current source transistor.
  • a plurality of pixels each of which is provided with a current source transistor having a source connected to a ground node and supplying a predetermined drain-source current, a capacitance element inserted between a gate of the current source transistor and the ground node, and a sample-and-hold switch that samples and holds a predetermined bias voltage in the capacitance element during a period in which the drain-source current is not being supplied; and a signal processing circuit that processes pixel signals from each of the plurality of pixels.
  • a current source transistor having a source connected to a ground node, supplying a predetermined drain-source current; and a sample and hold step of sampling and holding a predetermined bias voltage in a capacitance element inserted between the gate of the current source transistor and the ground node during a period in which the drain-source current is not flowing.
  • Imaging device 110 Imaging lens 120 Recording unit 130 Imaging control unit 200 Solid-state imaging element 201 Upper chip 202 Lower chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Accessory 221 Reference current source 222 Mirror source transistor 230, 400 Pixel array section 231 Upper pixel array section 232 Lower pixel array section 250 Load MOS circuit block 251 Load MOS transistor 260 Column signal processing circuit 261 ADC 262 Digital signal processing unit 271 Column arbiter 272 Column AER circuit 273 Column address encoder 274 Row address encoder 275 Row AER circuit 276 Row arbiter 277 State machine 300, 410 Pixel 308 Selector 310 Pre-stage circuit 311, 421 Photoelectric conversion element 312 Transfer transistor 313 Pre-stage reset transistor 314 FD 315 Pre-stage amplification transistor 316 Pre-stage node 317 Current source transistor 318, 321, 351, 352, 441, 444 Capacitive element 319 Sample hold switch 320 Conversion efficiency control transistor 330 Switch circuit 331 Switch transistor

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Abstract

La présente invention supprime les variations de courant dans un élément d'imagerie à semi-conducteurs dans lequel un transistor servant de source de courant est disposé dans chaque pixel.　Un transistor de source de courant, un élément capacitif, et un commutateur échantillonneur-bloqueur sont disposés dans chaque pixel d'une pluralité de pixels. Le transistor source de courant comprend une source connectée à un nœud de masse, et fournit un courant source-drain prédéterminé. L'élément capacitif est inséré entre une grille du transistor de source de courant et le nœud de masse. Le commutateur échantillonneur-bloqueur échantillonne et bloque une tension de polarisation prédéterminée dans l'élément capacitif pendant une période dans laquelle le courant drain-source n'est pas fourni.
PCT/JP2024/000159 2023-03-02 2024-01-09 Élément d'imagerie à semi-conducteurs, dispositif de photodétection, et procédé de fabrication d'élément d'imagerie à semi-conducteurs WO2024180908A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021197632A (ja) * 2020-06-15 2021-12-27 キヤノン株式会社 光電変換装置、光電変換システム及び移動体
WO2022074940A1 (fr) * 2020-10-08 2022-04-14 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et dispositif d'imagerie
WO2022196057A1 (fr) * 2021-03-19 2022-09-22 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021197632A (ja) * 2020-06-15 2021-12-27 キヤノン株式会社 光電変換装置、光電変換システム及び移動体
WO2022074940A1 (fr) * 2020-10-08 2022-04-14 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs et dispositif d'imagerie
WO2022196057A1 (fr) * 2021-03-19 2022-09-22 ソニーセミコンダクタソリューションズ株式会社 Élément d'imagerie à semi-conducteurs

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