WO2024180584A1

WO2024180584A1 - Display device

Info

Publication number: WO2024180584A1
Application number: PCT/JP2023/006973
Authority: WO
Inventors: 史幸小林
Original assignee: シャープディスプレイテクノロジー株式会社
Priority date: 2023-02-27
Filing date: 2023-02-27
Publication date: 2024-09-06

Abstract

A display device (1) comprising a high-potential-side first power source line (14), a low-potential-side second power source line (15), a data signal line (11), a drive transistor (T4), a first capacitance electrode (21) that is electrically connected to the first power source line (14) and that forms capacitance with a gate electrode (23) of the drive transistor (T4), and a second capacitance electrode (22) that is electrically connected to the second power source line (15) and that forms capacitance with the first capacitance electrode (21).

Description

Display device

This disclosure relates to a display device.

Patent Document 1 discloses that in a display device in which power supply lines and source signal lines are arranged in parallel, display unevenness occurs due to potential variations in the power supply lines.

Japanese Patent Application Publication No. 2021-152669

In display devices that have a high-potential power line and a data signal line, display abnormalities can occur due to fluctuations in the potential of the high-potential power line.

The display device according to the present disclosure includes a first power line on the high potential side and a second power line on the low potential side, a data signal line, a drive transistor, a first capacitance electrode electrically connected to the first power line and forming a capacitance with the gate electrode of the drive transistor, and a second capacitance electrode electrically connected to the second power line and forming a capacitance with the first capacitance electrode.

A display device according to another aspect of the present disclosure includes a first power line on the high potential side and a second power line on the low potential side, a data signal line, a drive transistor, a third capacitance electrode electrically connected to the second power line and forming a capacitance with the gate electrode of the drive transistor, and a fourth capacitance electrode electrically connected to the gate electrode and forming a capacitance with the third capacitance electrode.

This disclosure makes it possible to suppress display abnormalities.

FIG. 1 is a plan view showing a configuration example of a display device according to an embodiment of the present invention. 1A and 1B are a plan view and a cross-sectional view showing a configuration example of a display device according to an embodiment of the present invention. 11A to 11C are explanatory diagrams showing a display example in the present embodiment and a display example in a comparative example. 1A and 1B are a plan view and a cross-sectional view showing another configuration example of the display device of the present embodiment. FIG. 1 is a plan view illustrating a display device according to a first embodiment of the present disclosure. FIG. 1 is a plan view illustrating an example of a display device according to a first embodiment of the present disclosure. 2 is a circuit diagram of a pixel circuit included in the display device according to the first embodiment of the present disclosure. This is a cross-sectional view taken along line A1-A1 of FIG. 10 is a timing chart showing an example of a potential fluctuation of a first power supply line in accordance with a potential fluctuation of a data signal. FIG. 11 is a plan view illustrating an example of a display device according to a second embodiment of the present disclosure. This is a cross-sectional view taken along line A2-A2 of FIG. FIG. 11 is a circuit diagram of a pixel circuit included in a display device according to a second embodiment of the present disclosure.

FIG. 1 is a plan view showing an example of the configuration of the display device of this embodiment. FIG. 2 is a plan view and a cross-sectional view showing an example of the configuration of the display device of this embodiment. As shown in FIGS. 1 and 2, the display device 1 includes a plurality of light-emitting elements 5, a first power supply line 14 on the high potential side (e.g., ELVDD) and a second power supply line 15 on the low potential side (e.g., ELVSS), a data signal line 11, a scanning signal line 12, a driving transistor T4, a first capacitance electrode 21 electrically connected to the first power supply line 14 and forming a capacitance C1 (control capacitance) with the gate electrode 23 of the driving transistor T4, and a second capacitance electrode 22 electrically connected to the second power supply line 15 and forming a capacitance C2 (storage capacitance) with the first capacitance electrode 21. The first power supply line 14 and the data signal line 11 may be adjacent to each other (formed adjacent to each other in the same layer). The driving transistor T4 is formed in the pixel circuit 13. The light-emitting element 5A connected to pixel circuit 13A, the light-emitting element 5B connected to pixel circuit 13B, and the light-emitting element 5C connected to pixel circuit 13C may emit light of different colors. The light-emitting element 5 may be a light-emitting diode (e.g., an OLED).

A first capacitance electrode 21 is disposed on the gate electrode 23 via a first inorganic insulating film 71, and a second capacitance electrode 22 is disposed on the first capacitance electrode 21 via a second inorganic insulating film 72. A first power supply line 14 is disposed on the second capacitance electrode 22 via an organic insulating film 73. The first power supply line 14, the second power supply line 15, and the data signal line 11 are located in the same layer. The second power supply line 15 and the second capacitance electrode 22 are connected via a contact hole H1.
2, the display device 1 includes, from the bottom up, a semiconductor layer SC (e.g., polysilicon), a metal layer GM including a gate electrode 23, a metal layer M3 including a first capacitance electrode 21, a metal layer SE including a second capacitance electrode 22, and a metal layer M4 including a first power line 14, a second power line 15, and a data signal line 11. The overlapping portion of the semiconductor layer SC with the gate electrode 23 becomes the channel of the driving transistor T4. The portion of the semiconductor layer SC that does not overlap with the metal layer GM may function as a conductor (electrode, wiring).

The display device 1 includes a third power line 16 on the high potential side (e.g., ELVDD) that extends in a direction (second direction) perpendicular to the extension direction (first direction) of the data signal line 11, and the third power line 16 and the second capacitance electrode 22 are located in the same layer (metal layer SE). The third power line 16 and the first capacitance electrode 21 are connected via a contact hole H2, and the third power line 16 and the first power line 14 are connected via a contact hole H3. A capacitance CX (storage capacitance) may be formed between the first power line 14 and the second capacitance electrode 22. The distance between the data signal line 11 and the second power line 15 may be greater than the distance between the data signal line 11 and the first power line 14.
3 is an explanatory diagram showing a display example in this embodiment and a display example in a comparative example. Since the display device 1 includes the first capacitance electrode 21 and the second capacitance electrode 22 forming the capacitance C2 (storage capacitance), the potential of the first power line 14 is unlikely to fluctuate even if the potential of the data signal line 11 fluctuates. For example, even if the potential of the data signal line 11 changes from middle to high (High: black potential) or from high (High: black potential) to middle, the potential of the first power line 14 hardly fluctuates, and the gate potential (potential of the gate electrode 23) of the driving transistor T4 is appropriately set (maintained at a potential according to the grayscale data), so that display abnormalities are suppressed even when a black block is displayed on a gray background.

On the other hand, in a comparative display device that does not include a second capacitive electrode, the potential of the ELVDD power line is likely to fluctuate due to fluctuations in the potential of the data signal line. For example, when the potential of the data signal line changes from medium to high (high: black potential), the gate potential of the drive transistor is pulled in and the boundary line shifts to the high brightness side, and when the potential of the data signal line changes from high (high: black potential) to medium, the gate potential of the drive transistor is pushed up and the boundary line shifts to the low brightness side, so that a white line extending the upper edge of a black block and a black line extending the lower edge of a black block are likely to be displayed (abnormal display) on a gray background.

4 is a plan view and a cross-sectional view showing another example of the configuration of the display device of this embodiment. As shown in FIG. 4, the display device 1 includes a first power line 14 on the high potential side and a second power line 15 on the low potential side, a data signal line 11, a driving transistor T4, a third capacitance electrode 121 electrically connected to the second power line 15 and forming a capacitance C3 (storage capacitance) with the gate electrode 23 of the driving transistor T4, and a fourth capacitance electrode 122 electrically connected to the gate electrode 23 and forming a capacitance C4 (storage capacitance) with the third capacitance electrode 121. A capacitance C1 (control capacitance) is formed between the first power line 14 and the fourth capacitance electrode 122. The third capacitance electrode 121 is disposed on the gate electrode 23 via the first inorganic insulating film 71, and the fourth capacitance electrode 122 is disposed on the third capacitance electrode 121 via the second inorganic insulating film 72. The first power line 14 is disposed on the fourth capacitance electrode 122 via the organic insulating film 73.

The third capacitance electrode 121 is formed on metal layer M3, and the fourth capacitance electrode 122 is formed on metal layer SE. The gate electrode 23 and the fourth capacitance electrode 122 are connected via a contact hole H4. An opening K is formed in the third capacitance electrode 121, and the contact hole H4 is formed so as to be located within the opening in a plan view (so as not to contact the third capacitance electrode 121). The second power line 15 and the third capacitance electrode 121 are connected via a contact hole H5.

The display device 1 in FIG. 4 includes a third capacitance electrode 121 that forms a storage capacitance with the gate electrode 23 and the fourth capacitance electrode 122, so that even if the potential of the first power line 14 fluctuates, the gate potential of the drive transistor T4 (the potential of the gate electrode 23) is less likely to fluctuate, making it possible to suppress display abnormalities such as those in the comparative example (FIG. 3).

As shown in FIG. 1, a first power supply line 14 may be provided for each of the pixel circuits 13A to 13C, and second power supply lines 15 may be provided corresponding to the pixel circuits 13A to 13C. In other words, the number of second power supply lines 15 may be less than the number of first power supply lines 14.

1, the anode (e.g., a light-reflecting electrode) of the light-emitting element 5A may overlap the data signal line 11A in a planar view, the anode of the light-emitting element 5B may overlap the data signal line 11B in a planar view, and the anode of the light-emitting element 5C may overlap the data signal line 11C in a planar view. This makes it possible to suppress the effect of potential fluctuations in the data signal lines 11A to 11C on the common electrode (e.g., a cathode at the same potential as the second power line 15) of the light-emitting elements 5A to 5C.

Below, examples of the present disclosure will be described with reference to the drawings. Note that the drawings are schematic, and the correlation between the size and position of images shown in different drawings is not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals.

[First embodiment]
5 is a plan view showing a display device 1 according to a first embodiment of the present disclosure. As shown in FIG. 5, the display device 1 includes a plurality of pixel circuits 13, a plurality of data signal lines 11, and a plurality of scanning signal lines 12. The plurality of data signal lines 11 extend in a first direction Y. The plurality of scanning signal lines 12 extend in a second direction X perpendicular to the first direction Y. In a plan view, three data signal lines 11 and one scanning signal line 12 are formed in each of the plurality of pixel circuits 13. In a plan view, the data signal line 11 is formed so as to overlap the plurality of pixel circuits 13 arranged in parallel in the first direction Y. In a plan view, the scanning signal line 12 is formed so as to overlap the plurality of pixel circuits 13 arranged in parallel in the second direction X.

FIG. 6 is a plan view showing an example of a pixel circuit 13 provided in a display device 1 according to a first embodiment of the present disclosure. The pixel circuit 13 includes a pixel circuit 13R corresponding to red, a pixel circuit 13G corresponding to green, and a pixel circuit 13B corresponding to blue. The

pixel circuits

13R, 13G, and 13B are formed along the second direction X. The three data signal lines 11 formed in the pixel circuit 13 are formed one for each of the

pixel circuits

13R, 13G, and 13B. A data signal data is input to the data signal line 11.

The scanning signal line 12 is formed so as to straddle the

pixel circuits

13R, 13G, and 13B. The scanning signal line 12 straddling the

pixel circuits

13R, 13G, and 13B means that the scanning signal line 12 overlaps the

pixel circuits

13R, 13G, and 13B in a plan view. In FIG. 5, a scanning signal scan[n] is input to the scanning signal line 12 in the nth row.

The pixel circuit 13 is supplied with a high-level potential ELVDD and a low-level potential ELVSS, as well as initialization potentials Vini1 and Vini2. A first power supply line 14 extending in the first direction Y is formed in each of the

pixel circuits

13R, 13G, and 13B. The first power supply line 14 is a high-potential side wiring, and supplies the high-level potential ELVDD to the pixel circuit 13. A second power supply line 15 extending in the first direction Y is formed in the pixel circuit 13. The second power supply line 15 is a low-potential side wiring, and supplies the low-level potential ELVSS to the pixel circuit 13.

A third power supply line 16 is formed in the pixel circuit 13, extending in the second direction X so as to straddle the

pixel circuits

13R, 13G, and 13B. The third power supply line 16 straddling the

pixel circuits

13R, 13G, and 13B means that the third power supply line 16 overlaps the

pixel circuits

13R, 13G, and 13B in a planar view. The third power supply line 16 is a high-potential wiring and supplies a high-level potential ELVDD to the pixel circuit 13. The third power supply line 16 is formed in a layer lower than the first power supply line 14 and the second power supply line 15. In the

pixel circuits

13R, 13G, and 13B, the third power supply line 16 is electrically connected to the first power supply line 14 via a third contact hole 41. In FIG. 6, the contact holes formed in common to

pixel circuits

13R, 13G, and 13B, such as the third contact hole 41, are represented by the reference symbol for pixel circuit 13B.

The pixel circuit 13 includes a wiring 17 used to supply an initialization potential Vini1, and a wiring 18 used to supply an initialization potential Vini2. The pixel circuit 13 also includes a wiring 19 to which a light emission control signal dis[n-1] is input, and a wiring 20 to which a light emission control signal em[n] is input. The

wirings

17, 18, 19, and 20 extend in the second direction X.

The display device 1 includes a first capacitance electrode 21 for each of the

pixel circuits

13R, 13G, and 13B. The first capacitance electrode 21 is electrically connected to the third power supply line 16 via the second contact hole 42. The first capacitance electrode 21 is electrically connected to the first power supply line 14 via the third power supply line 16.

The display device 1 includes a second capacitance electrode 22. The second capacitance electrode 22 is electrically connected to the second power line 15 via a first contact hole 43. The first contact hole 43 is formed at a position where the second power line 15 and the second capacitance electrode 22 overlap in a plan view. The second capacitance electrode 22 extends in the second direction X from a position where it is connected to the first contact hole 43 in a plan view. The second capacitance electrode 22 has a wide portion 22A whose size in the first direction Y is locally large. In a plan view, the wide portion 22A of the second capacitance electrode 22 overlaps with the first capacitance electrodes 21 of the

pixel circuits

13R, 13G, and 13B.

Hereinafter,

pixel circuits

13R, 13G, and 13B may be referred to as pixel circuit 13.

FIG. 7 is a circuit diagram of a pixel circuit 13 provided in a display device 1 according to a first embodiment of the present disclosure. As shown in FIG. 7, each of the pixel circuits 13 has a 7T2C configuration. Each of the pixel circuits 13 includes seven thin-film transistors T1-T7, an organic light-emitting diode OLED, a first capacitance C1, and a second capacitance C2.

FIG. 6 shows the positions where the thin-film transistors T1-T7 are formed in the pixel circuit 13. In FIG. 6, the positions corresponding to the gate electrodes of the thin-film transistors T1-T7 in the pixel circuit 13R are denoted with reference symbols.

The thin-film transistor T4 is a drive transistor for the organic light-emitting diode OLED. That is, the display device 1 includes a thin-film transistor T4 that is a drive transistor for the organic light-emitting diode OLED. Hereinafter, the thin-film transistor T4 will be referred to as the drive transistor T4. The first capacitance C1 is formed between the gate electrode 23 of the drive transistor T4 and the first capacitance electrode 21. The second capacitance C2 is formed between the first capacitance electrode 21 and the second capacitance electrode 22.

The light emission control signal dis[n-1] input to wiring 19 is input to the gate electrode of thin-film transistor T1. The scan signal scan[n] is input to the gate electrodes of thin-film transistors T2 and T3. The light emission control signal em[n] is input to the gate electrodes of thin-film transistors T5 and T6. The light emission control signal dis[n] is input to the gate electrode of thin-film transistor T7.

As shown in FIG. 6, one of the drain and source of the thin-film transistor T1 is electrically connected to the wiring 17 via the fourth contact hole 44, and the other is electrically connected to the gate electrode 23 of the drive transistor T4 via the fifth contact hole 45 and the sixth contact hole 46.

One of the drain and source of the thin-film transistor T2 is electrically connected to the gate electrode 23 of the drive transistor T4 via the fifth contact hole 45 and the sixth contact hole 46, and the other is connected to the source (drain) of the drive transistor T4 via a wiring 61. One of the drain and source of the thin-film transistor T3 is electrically connected to the data signal line 11 via the seventh contact hole 47 and the eighth contact hole 48, and the other is connected to the drain (source) of the drive transistor T4 via a wiring 60.

One of the drain and source of the thin-film transistor T5 is electrically connected to the third power line 16 via the ninth contact hole 49, and the other is connected to the drain (source) of the drive transistor T4. One of the drain and source of the thin-film transistor T6 is connected to the organic light-emitting diode OLED via the tenth contact hole 50, and the other is connected to the source (drain) of the drive transistor T4.

One of the drain and source of the thin-film transistor T7 is electrically connected to the wiring 18 via the 11th contact hole 51, and the other is connected to the organic light-emitting diode OLED via the 12th contact hole 52.

FIG. 8 is a cross-sectional view taken along the line A1-A1 in FIG. 6. As shown in FIG. 8, a first capacitance electrode 21 is disposed on the gate electrode 23 of the driving transistor T4 via a first inorganic insulating film 71. The first capacitance electrode 21 forms a first capacitance C1 together with the gate electrode 23.

A wide portion 22A of the second capacitance electrode 22 is disposed on the first capacitance electrode 21 via a second inorganic insulating film 72. A first power supply line 14 is disposed on the wide portion 22A of the second capacitance electrode 22 via an organic insulating film 73. The wide portion 22A of the second capacitance electrode 22 forms a second capacitance C2 with the first capacitance electrode 21 and the first power supply line 14.

A light-reflecting electrode 80 is disposed on the first power line 14 via a planarization film 74. A light-emitting layer 81 and a common electrode 82 are disposed above the light-reflecting electrode 80. The common electrode 82 has the same potential as the second power line 15. In other words, the potential of the common electrode 82 is the low-level potential ELVSS. The end of the light-reflecting electrode 80 is covered with an edge cover 83. In FIG. 6, the outline of the light-reflecting electrode 80 disposed on the first power line 14 is shown. The light-reflecting electrode 80 is formed of, for example, silver or the like.

As shown in FIG. 8, the first power supply line 14, the second power supply line 15, and the data signal line 11 are located in the same layer. In addition, the third power supply line 16, which is not shown in FIG. 8, is located in the same layer as the second capacitance electrode 22. The first power supply line 14, the second power supply line 15, the data signal line 11, the third power supply line 16, and the second capacitance electrode 22 are formed of the same material containing aluminum. The gate electrode 23 and the first capacitance electrode 21 of the driving transistor T4 are formed of molybdenum.

In FIG. 8, the data signal line 11 is adjacent to the first power supply line 14. The data signal line 11 being adjacent to the first power supply line 14 may mean that the data signal line 11 is located in the same layer as the first power supply line 14, the data signal line 11 extends in parallel with the first power supply line 14, and the voltage fluctuation of the data signal line 11 affects the first power supply line 14. At this time, the data signal line 11 forms a parasitic capacitance C _elvdd-data with the first power supply line 14. A power supply line such as the first power supply line 14 is designed to have a wiring width as large as possible in order to reduce a voltage drop (IR drop) of an IR product occurring on the power supply line. When the wiring width of the first power supply line 14 increases, the distance between the data signal line 11 and the first power supply line 14 becomes closer, and the parasitic capacitance C _elvdd-data increases. The effect of the parasitic capacitance C _elvdd-data on the first power supply line 14 will be described with reference to FIG. 9.

9 is a timing chart showing an example of the potential fluctuation of the first power supply line 14 accompanying the potential fluctuation of the data signal data. In the example of FIG. 9, the data signal data changes from a low level potential to a high level potential at timing TM1. The potential of the first power supply line 14 changes by ΔV _elvdd1 following the fluctuation of the data signal data. Thereafter, the potential of the first power supply line 14 gradually returns to the value before the fluctuation. The amount of fluctuation ΔV _elvdd1 is the value of formula (1) and is proportional to the magnitude of the parasitic capacitance C _elvdd-data .
ΔV _elvdd1 = (V _DataH - V _DataL ) x C _elvdd-data / ΣC _elvdd ...(1)
Here, V _DataH is the high level potential of the data signal data, V _DataL is the low level potential of the data signal data, and ΣC _elvdd is the total capacitance of ELVDD, which is the combined capacitance of the first capacitance C1, the second capacitance C2, and the parasitic capacitance C _T4 of the driving transistor T4.

The potential _{Vn_g} of the gate electrode of the driving transistor T4 becomes equal to the data signal "data" minus the magnitude | _Vth | of the threshold voltage _Vth of the driving transistor T4 while data is being written.

However, when the data writing is completed, the potential _{Vn_g} of the gate electrode of the driving transistor T4 fluctuates following the potential fluctuation of the first power supply line 14. In the example of Fig. 9, the data writing is completed at timing TM2, and the potential _{Vn_g} of the gate electrode 23 of the driving transistor T4 after timing TM2 drops by _{ΔVn_g} following the drop in the first power supply line 14. The potential fluctuation amount _{ΔVn_g} is the value of formula (2) and is based on the potential fluctuation amount _ΔVelvdd2 of the first power supply line 14 at timing TM2 and the first capacitance C1.
ΔV _{n_g} = ΔV _elvdd2 ×C1/ΣC _{n_g} …(2)
Here, C1/ΣC _{n_g} is the capacitive coupling coefficient between the first power line 14 and the gate electrode 23 of the driving transistor T4, and is 1 in the case of the circuit diagram of FIG.

9, the amount of potential fluctuation of the first power supply line 14 returns to 0 at timing TM3, but the potential _{Vn_g} of the gate electrode of the driving transistor T4 remains in a state where it has decreased by _{ΔVn_g} . In this manner, if the potential _{Vn_g} of the gate electrode of the driving transistor T4 remains in a state where it fluctuates in response to fluctuations in the data signal data, display unevenness in which bright lines and dark lines appear on the display device 1 may occur.

In the display device 1 according to the first embodiment of the present disclosure, the second capacitance electrode 22 electrically connected to the second power line 15 extends in the second direction X and is formed so as to overlap the first capacitance electrode 21 in a plan view. As a result, a second capacitance C2 is formed between the first capacitance electrode 21 and the second capacitance electrode 22 and between the first power line 14 and the second capacitance electrode 22, and the ELVDD total capacitance ΣC _elvdd increases. Then, the potential electric charge ΔV _elvdd1 of the first power line 14 accompanying the change in the data signal data and the potential fluctuation amount ΔV _elvdd2 of the first power line 14 at the end of writing data become small, so that the potential fluctuation amount ΔV _{n_g} of the potential V _{n_g} of the gate electrode 23 of the driving transistor T4 becomes small. Therefore, it is possible to reduce display unevenness that causes bright lines and dark lines in the display device 1 according to the first embodiment of the present disclosure.

Second Example
A display device 1 according to a second embodiment of the present disclosure will be described. Fig. 10 is a plan view showing an example of a pixel circuit 13A in the display device 1 according to the second embodiment of the present disclosure. The pixel circuit 13A includes a pixel circuit 113R corresponding to red, a pixel circuit 113G corresponding to green, and a pixel circuit 113B corresponding to blue. The

pixel circuits

113R, 113G, and 113B are formed along the second direction X. The three data signal lines 11 formed in the pixel circuit 13A are formed in each of the

pixel circuits

113R, 113G, and 113B, respectively.

The pixel circuit 13A in the display device 1 according to the second embodiment of the present disclosure does not include a first capacitance electrode 21 and a second capacitance electrode 22, but includes a third capacitance electrode 121 and a fourth capacitance electrode 122. The third capacitance electrode 121 is electrically connected to the second power line 15 via a first contact hole 43 and a thirteenth contact hole 53. The third capacitance electrode 121 extends in the second direction X in a plan view. The fourth capacitance electrode 122 is electrically connected to the gate electrode 23 of the drive transistor T4 via a fourteenth contact hole 54.

Hereinafter,

pixel circuits

113R, 113G, and 113B may be referred to as pixel circuit 113.

11 is a cross-sectional view taken along line A2-A2 of FIG. 10. As shown in FIG. 11, a third capacitance electrode 121 is arranged on the gate electrode 23 of the driving transistor T4 (driving transistor) via a first inorganic insulating film 71. A fourth capacitance electrode 122 is arranged on the third capacitance electrode 121 via a second inorganic insulating film 72. A first power supply line 14 is arranged on the fourth capacitance electrode 122 via an organic insulating film 73. The fourth capacitance electrode 122 is located in the same layer as the third power supply line 16. The first power supply line 14, the second power supply line 15, the data signal line 11, the third power supply line 16, and the fourth capacitance electrode 122 are made of the same material containing aluminum. The gate electrode 23 and the third capacitance electrode 121 of the driving transistor T4 are made of molybdenum. The third capacitance electrode 121 forms a third capacitance C3 together with the gate electrode 23 and the fourth capacitance electrode 122. The fourth capacitance electrode 122 forms a first capacitance C1 with the first power line 14.

In addition, a relay electrode 91 is disposed on the third capacitance electrode 121 via the second inorganic insulating film 72. The first contact hole 43 and the thirteenth contact hole 53 are electrically connected via the relay electrode 91. The relay electrode 91 is formed in the same layer and made of the same material as the fourth capacitance electrode 122. The second power line 15 is electrically connected to the third capacitance electrode 121 via the first contact hole 43, the thirteenth contact hole 53, and the relay electrode 91.

A light-reflecting electrode 80A is disposed on the first power supply line 14 via a planarization film 74. In the pixel circuit 13A in the display device 1 according to the second embodiment of the present disclosure, the light-reflecting electrode 80A is disposed so as to overlap with the data signal line 11 in a planar view. This prevents parasitic capacitance from being formed between the data signal line 11 and the common electrode 82. The parasitic capacitance C _elvdd-data between the data signal line 11 and the first power supply line 14 is larger than the parasitic capacitance C _elvss-data between the data signal line 11 and a power supply line to which a low-level potential ELVSS is supplied, such as the second power supply line 15.

Above the light-reflecting electrode 80A, a light-emitting layer 81 and a common electrode 82 are arranged. The common electrode 82 has the same potential as the second power line 15.

An insulating film 90 is formed around the periphery of the 14th contact hole 54 to prevent a short circuit between the third capacitance electrode and 121.

FIG. 12 is a circuit diagram of a pixel circuit 113 provided in a display device 1 according to a second embodiment of the present disclosure. The pixel circuit 113 provided in a display device 1 according to a second embodiment of the present disclosure has a 7T2C configuration. Seven thin film transistors T1-T7, an organic light emitting diode OLED, a first capacitance C1, and a third capacitance C3 are formed in the pixel circuit 113. By connecting the third capacitance C3 to the gate electrode of the driving transistor T4, the capacitive coupling coefficient C1/ΣC _{n_g} between the first power line 14 and the gate electrode 23 of the driving transistor T4 becomes small. As a result, the potential fluctuation amount ΔV _{n_g} of the potential V _{n_g} of the gate electrode 23 of the driving transistor T4 becomes small. Therefore, it is possible to reduce display unevenness that causes bright lines and dark lines in the display device 1 according to the second embodiment of the present disclosure.

The above disclosure is intended to be illustrative and explanatory, and not limiting. Based on these examples and explanations, many variations will be obvious to those skilled in the art, and it should be noted that these variations are also included in the embodiments.

1 Display device 11 Data signal line 14 First power line 15 Second power line 16 Third power line 21 First capacitance electrode 22 Second capacitance electrode 22A Wide portion 23 Gate electrode 71 First inorganic insulating film 72 Second inorganic insulating film 73 Organic insulating film 74

Planarization film

80, 80A Light-reflecting electrode 81 Light-emitting layer 82 Common electrode 121 Third capacitance electrode 122 Fourth capacitance electrode T4 Thin film transistor (driving transistor)
Y 1st direction X 2nd direction

Claims

a first power line on a high potential side and a second power line on a low potential side;
A data signal line;
A drive transistor;
a first capacitance electrode electrically connected to the first power supply line and forming a capacitance together with a gate electrode of the driving transistor;
a second capacitance electrode electrically connected to the second power supply line and forming a capacitance with the first capacitance electrode.
the first capacitance electrode is disposed on the gate electrode via a first inorganic insulating film;
The display device according to claim 1 , wherein the second capacitance electrode is disposed on the first capacitance electrode via a second inorganic insulating film.
The display device according to claim 2, wherein the first power line is disposed on the second capacitance electrode via an organic insulating film.
The display device according to claim 3, wherein the first power supply line, the second power supply line, and the data signal line are located on the same layer.
The display device of claim 4, wherein the data signal line and the first power supply line are adjacent to each other.
The display device according to claim 4, wherein the distance between the first power line and the second power line is greater than the distance between the data signal line and the first power line.
the first power supply line and the data signal line extend in a first direction;
The display device according to claim 2 , wherein the second capacitance electrode extends in a second direction perpendicular to the first direction.
the second capacitance electrode has a wide portion whose size in a first direction in which the first power line extends is locally large;
The display device according to claim 6 , wherein the wide portion and the first capacitance electrode overlap with each other via the second inorganic insulating film.
a third power line on a high potential side extending in the second direction;
The display device according to claim 7 , wherein the third power supply line and the second capacitance electrode are located in the same layer.
the second power supply line and the second capacitance electrode are connected via a first contact hole; the first capacitance electrode and the third power supply line are connected via a second contact hole;
10. The display device according to claim 9, wherein the first power supply line and the third power supply line are connected via a third contact hole.
a light-reflection electrode is disposed on the first power line via a planarization film;
The display device according to claim 3 , further comprising a light-emitting layer and a common electrode having the same potential as the second power line, disposed above the light-reflecting electrode.
12. The display device according to claim 1, wherein the first power supply line, the data signal line, and the second capacitance electrode are made of the same material containing aluminum.
a first power line on a high potential side and a second power line on a low potential side;
A data signal line;
A drive transistor;
a third capacitance electrode electrically connected to the second power line and forming a capacitance together with a gate electrode of the driving transistor;
a fourth capacitance electrode electrically connected to the gate electrode and forming a capacitance together with the third capacitance electrode.
The display device according to claim 13, wherein the first power supply line and the data signal line are located in the same layer and are adjacent to each other.
the third capacitance electrode is disposed on the gate electrode via a first inorganic insulating film;
15. The display device according to claim 13, wherein the fourth capacitance electrode is disposed on the third capacitance electrode via a second inorganic insulating film.
the first power supply line is disposed on the fourth capacitance electrode via an organic insulating film;
The display device according to claim 15 , wherein a capacitance is formed between the fourth capacitance electrode and the first power supply line.
a light-reflection electrode overlapping the data signal line in a plan view is disposed above the first power supply line;
17. The display device according to claim 13, further comprising a light-emitting layer and a common electrode having the same potential as the second power line, disposed above the light-reflecting electrode.
the first power supply line and the data signal line extend in a first direction;
18. The display device according to claim 13, wherein the third capacitance electrode extends in a second direction perpendicular to the first direction.
a third power line on a high potential side extending in the second direction;
The display device according to claim 18 , wherein the third power supply line and the fourth capacitance electrode are located in the same layer.
the third capacitance electrode has an opening;
the gate electrode and the fourth capacitance electrode are connected via a fourth contact hole;
20. The display device according to claim 13, wherein the fourth contact hole is located within the opening in a plan view.
The display device according to any one of claims 13 to 20, wherein the first power supply line, the data signal line, and the fourth capacitance electrode are made of the same material containing aluminum.
a plurality of pixel circuits each including the drive transistor;
the first power supply line is provided for each of the plurality of pixel circuits;
22. The display device according to claim 1, wherein the second power supply lines are provided corresponding to the plurality of pixel circuits.