Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/8311—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different channel structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/832—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/851—Complementary IGFETs, e.g. CMOS comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/90—Masterslice integrated circuits
  • H10D84/903—Masterslice integrated circuits comprising field effect technology
  • H10D84/907—CMOS gate arrays
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/10—Integrated device layouts
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/427—Power or ground buses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Definitions

• This disclosure relates to a semiconductor integrated circuit device.
• the standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate.
• the standard cell method is a method for designing an LSI chip by preparing basic units with specific logical functions (e.g. inverters, latches, flip-flops, full adders, etc.) as standard cells in advance, placing multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.
• basic units with specific logical functions e.g. inverters, latches, flip-flops, full adders, etc.
• transistors which are the basic building blocks of LSIs, have achieved increased integration density, lower operating voltages, and faster operating speeds through the reduction of gate length (scaling). In recent years, however, excessive scaling has caused problems with off-current and the resulting dramatic increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type.
• One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).
• Patent Document 1 discloses the structure of a termination cell used to terminate a circuit block composed of standard cells using CFETs (Complementary FETs).
• a "termination cell” refers to a cell that does not contribute to the logical function of the circuit block and is used to terminate the circuit block.
• Patent document 2 discloses a semiconductor integrated circuit device in which standard cell rows of different heights are arranged alternately and standard cells span multiple standard cell rows.
• Patent document 3 discloses a technique for achieving even higher integration by providing wiring on the back surface of the substrate directly below the transistor and connecting the source/drain of the transistor to this wiring.
• Patent Document 2 does not disclose a layout structure that includes standard cells that do not have a logical function, such as termination cells, in a semiconductor integrated circuit device that has rows of standard cells of different heights.
• This disclosure provides a layout structure for a semiconductor integrated circuit device having rows of standard cells of different heights, the layout structure including standard cells that do not have a logic function.
• a semiconductor integrated circuit device comprises a first cell row including a plurality of standard cells aligned in a first direction, and a second cell row including a plurality of standard cells aligned in the first direction, the first cell row including a first standard cell having a first nanosheet extending in the first direction and having a logic function, and a second standard cell adjacent to the first standard cell and including a second nanosheet extending in the first direction and not having a logic function, the first nanosheet and the second nanosheet having the same width and position in a second direction perpendicular to the first direction, the second cell row including a third nanosheet extending in the first direction and having a logic function, and a third standard cell adjacent to the third standard cell and not having a logic function, and a fourth standard cell having no logic function, the third nanosheet and the fourth nanosheet have the same width and position in the second direction, the first cell row is formed on the back side of the transistor included in the first standard cell, extends in the first direction, overlaps
• the semiconductor integrated circuit device includes a first cell row and a second cell row.
• the first nanosheet included in the first standard cell having a logic function and the second nanosheet included in the second standard cell having no logic function have the same width and position in the second direction.
• the third nanosheet included in the third standard cell having a logic function and the fourth nanosheet included in the fourth standard cell having no logic function have the same width and position in the second direction. This improves the performance predictability of the transistor included in the standard cell having a logic function, and can suppress manufacturing variations and improve yield.
• the third and fourth nanosheets have a width in the second direction larger than the first and second nanosheets. This allows standard cells with high drive capacity to be configured in the second cell row and standard cells with low power consumption to be configured in the first cell row, thereby optimizing the performance of the semiconductor integrated circuit device.
• a semiconductor integrated circuit device includes a plurality of cell rows each including a plurality of standard cells arranged in a first direction, the plurality of cell rows including a first cell row including a first standard cell having a first nanosheet extending in the first direction and having a logic function, a second cell row adjacent to the first cell row in a second direction perpendicular to the first direction, having a different height from the first cell row, and including a second nanosheet extending in the first direction, and a third cell row at one end of the plurality of cell rows in the second direction, adjacent to the opposite side of the second cell row with respect to the first cell row, including a third nanosheet extending in the first direction, and including a third standard cell not having a logic function, the first cell row including a first standard cell having a first nanosheet extending in the first direction, the second standard cell having a second nanosheet extending in the first direction, and the third standard cell having a third nanosheet extending in the first direction, the third standard
• the second cell row is formed on the back side of the transistor, extends in the first direction, overlaps with the first nanosheet in a planar view, and includes a first power supply wiring that supplies a first power supply voltage;
• the second cell row is formed in the same wiring layer as the first power supply wiring, extends in the first direction, overlaps with the second nanosheet in a planar view, and includes a second power supply wiring that supplies the first power supply voltage;
• the third cell row is formed in the same wiring layer as the first and second power supply wirings, extends in the first direction, overlaps with the third nanosheet in a planar view, and includes a third power supply wiring that supplies the first power supply voltage;
• the first nanosheet and the second nanosheet have different widths in the second direction, and the third nanosheet and the second nanosheet have the same width in the second direction.
• the semiconductor integrated circuit device includes a first cell row, a second cell row adjacent to the first cell row in the second direction and having a different height from the first cell row, and a third cell row at one end of the multiple cell rows in the second direction and adjacent to the opposite side of the first cell row to the second cell row.
• a first nanosheet included in a first standard cell having a logical function included in the first cell row has a different width in the second direction from a second nanosheet included in a second standard cell included in the second cell row.
• a third nanosheet included in a third standard cell not having a logical function included in the third cell row has the same width in the second direction as the second nanosheet. This improves the performance predictability of the transistor included in the standard cell having a logical function, and also suppresses manufacturing variations, thereby improving yield.
• FIG. 2 is a plan view showing an example of the layout of a circuit block in the semiconductor integrated circuit device according to the embodiment;
• FIG. 2 is an enlarged view of a portion W1 of FIG. 1, showing a layout structure of a standard cell according to the first embodiment;
• 3A and 3B are cross-sectional views of the configuration of FIG. 2.
• (a) and (b) are other configuration examples.
• 4A to 4C are plan views showing a layout structure of a termination cell according to a first modification of the first embodiment;
• FIG. 2 is an enlarged view of a portion W2 of FIG.
• FIG. 1 shows an example of a layout structure of a double-height cell, where (a) is a termination cell and (b) is a filler cell.
• FIG. 2 is an enlarged view of a portion W3 of FIG. 1, showing a layout structure of a standard cell according to a second embodiment;
• FIG. 2 is an enlarged view of a portion W4 of FIG. 1, showing a layout structure of a standard cell according to a second embodiment;
• FIG. 9 is a plan view showing a modification of the layout structure of FIG. 8 .
• FIG. 10 is a plan view showing a modification of the layout structure of FIG.
• a semiconductor integrated circuit device includes a plurality of standard cells (in this specification, simply referred to as cells, as appropriate), and at least some of the plurality of standard cells include nanosheet FETs (Field Effect Transistors).
• a nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows.
• the nanosheet is formed of, for example, silicon. Note that in this disclosure, the transistors included in the standard cells are not limited to nanosheet FETs.
• VDD voltage
• VSS voltage or the power supply itself.
• expressions such as “same wiring width” that mean that the width, etc., is the same are considered to include the range of manufacturing variation.
• Fig. 1 is a plan view showing an example of the layout of a circuit block included in a semiconductor integrated circuit device according to an embodiment.
• the block layout in Fig. 1 is configured by arranging standard cells.
• Fig. 1 shows only the cell frames and power supply wiring of the standard cells, and does not show the internal structure of the standard cells, wiring between the standard cells, etc.
• the horizontal direction of the drawing is the X direction (corresponding to the first direction)
• the vertical direction of the drawing is the Y direction (corresponding to the second direction)
• the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction).
• the same symbols refer to the same things, and explanations may be omitted.
• a number of cells arranged in the X direction constitute cell rows CR1 and CR2.
• the height of cell row CR1 is H1
• the height of cell row CR2 is H2.
• the height H2 is greater than the height H1 (H2>H1).
• a number of cell rows CR1 and CR2 (six rows in FIG. 1) are arranged in the Y direction.
• the cell rows CR1 and CR2 are arranged alternately in the Y direction.
• Power wiring is formed on both ends of each cell in the Y direction, and each cell receives power supply potentials VDD and VSS from the outside via this power wiring.
• the power wiring is formed in the BM0 (Backside Metal 0) layer, which is a wiring layer provided on the back side of the semiconductor chip on which the transistors are formed.
• the width of the power wiring in cell row CR1 is WP1
• the width of the power wiring in cell row CR2 is WP2.
• the power wiring width WP2 is greater than the power wiring width WP1 (WP2>WP1).
• the cell rows CR1 and CR2 are arranged in a mirrored manner in the Y direction, so that the power wiring between the cell rows is shared.
• the width of the power wiring shared by the cell rows CR1 and CR2 is (WP1 + WP2).
• the multiple cells include cells with logic functions such as NAND gates and NOR gates (including inverter cells CI1 and CI2, which have the logic function of an inverter, as described below), as well as termination cells and filler cells that do not have a logic function.
• logic functions such as NAND gates and NOR gates (including inverter cells CI1 and CI2, which have the logic function of an inverter, as described below), as well as termination cells and filler cells that do not have a logic function.
• termination cells refer to cells that do not contribute to the logical function of a circuit block and are placed at the end of the circuit block.
• Ends of a circuit block refers to both ends of the cell rows that make up a circuit block (here, both ends in the X direction), as well as the top and bottom rows of the circuit block (here, both ends of the cell rows in the Y direction).
• termination cells are placed at both ends of the cell rows in the X direction or both ends of the cell rows in the Y direction, which are the ends of a circuit block.
• Filler cells are cells that do not contribute to the logical function of a circuit block and are placed in the gaps between cells that have logical functions.
• a rectangular logic unit LC that includes logic cells having logic functions and realizes the circuit functions is placed in the center of the circuit block.
• a termination cell portion is formed along the outer edge of the circuit block so as to surround this logic unit LC.
• filler cells are placed within the logic unit LC.
• dummy gate wiring is arranged in the terminal cell.
• dummy gate wiring refers to gate wiring that does not form a transistor, and gate wiring that forms a transistor that does not contribute to the logical function of the circuit.
• inverter cells CI1, CI2 and filler cells CF1, CF2 are arranged in the logic section LC, and termination cells C11, C12, C31, C32 are arranged in the termination cell section.
• Inverter cell CI1, filler cell CF1, and termination cells C11, C31 are arranged in cell row CR1, and the cell height is H1.
• Inverter cell CI2, filler cell CF2, and termination cells C12, C32 are arranged in cell row CR2, and the cell height is H2.
• end cells are arranged as follows.
• end cell C11 is arranged at the left end of the drawing, and an end cell that is a left-right mirror image of end cell C11 is arranged at the right end of the drawing.
• end cell C12 is arranged at the right end of the drawing, and an end cell that is a left-right mirror image of end cell C12 is arranged at the left end of the drawing.
• end cell C31 is arranged side by side in the X direction between the end cells at both ends of the drawing.
• end cell C32 is arranged side by side in the X direction between the end cells at both ends of the drawing.
• Fig. 2 is an enlarged view of a portion W1 in Fig. 1, and is a plan view showing a layout structure of a standard cell in this embodiment.
• Fig. 3 is a cross-sectional view of Fig. 2.
• Fig. 3(a) is a cross-sectional view taken along line X1-X1' in Fig. 2
• Fig. 3(b) is a cross-sectional view taken along line Y1-Y1' in Fig. 2.
• Fig. 2 shows the portion W1 of Fig. 1 upside down.
• part W1 is a part of cell string CR1.
• inverter cell CI1 is located at the left end of logic section LC in the drawing, with termination cell C11 located adjacent to it on the left side.
• filler cell CF1 is located adjacent to inverter cell CI1 on the right side.
• the inverter cell CI1 is provided with power supply wirings 11 and 12 extending in the X direction at both ends in the Y direction.
• the power supply wirings 11 and 12 are formed in a BM0 layer, which is a wiring layer provided on the back surface of a semiconductor chip in which transistors are formed.
• the power supply wirings 11 and 12 have a wiring width of WP1.
• the power supply wiring 11 supplies a power supply voltage VDD
• the power supply wiring 12 supplies a power supply voltage VSS.
• the power supply wirings 11 and 12 are shared with other cells in the cell string CR1 including the inverter cell CI1, and become power supply wirings extending in the X direction.
• the power supply wirings 11 and 12 are also shared between cell strings adjacent to each other in the Y direction.
• An active region 2P that constitutes the channel, source, and drain of the P-type transistor is formed in the P-type transistor region on the N-type well (NWell).
• the active region 2P overlaps with the power supply wiring 11 in a plan view.
• Transistor P1 has a nanosheet 21 as a channel, which is made up of three overlapping sheets in a plan view and extends in the X direction. In other words, transistor P1 is a nanosheet FET.
• the part that serves as the source of transistor P1 is connected to power supply wiring 11 through a via 61.
• An active region 2N that constitutes the channel, source, and drain of the N-type transistor is formed in an N-type transistor region on a P-type substrate (PSub). In a plan view, the active region 2N overlaps with the power supply wiring 12.
• the N-type transistor region may be formed on a P-type well.
• Transistor N1 has a nanosheet 26 as a channel, which is made up of three overlapping sheets in a plan view and extends in the X-direction. In other words, transistor N1 is a nanosheet FET.
• the part that serves as the source of transistor N1 is connected to power supply wiring 12 through a via 62.
• the active region which is the source and drain on both sides of the nanosheet, is formed, for example, by epitaxial growth from the nanosheet.
• a gate wiring 31 is formed extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the gate wiring 31 surrounds the outer periphery in the Y direction and Z direction of the nanosheet 21 of transistor P1 and the nanosheet 26 of transistor N1 via a gate insulating film (not shown).
• the gate wiring 31 corresponds to the gates of transistors P1 and N1.
• dummy gate wirings 32a, 33a are formed on both sides of the cell frame in the X direction.
• dummy gate wirings 32b, 33b are formed on both sides of the cell frame in the X direction.
• the dummy gate wirings 32a, 32b are shared with another cell arranged on the left side of the drawing (terminal cell C11 in FIG. 2).
• the dummy gate wirings 33a, 33b are shared with another cell arranged on the right side of the drawing (filler cell CF1 in FIG. 2).
• the dummy gate wirings 32a and 32b, the gate wiring 31, and the dummy gate wirings 33a and 33b are arranged at the same pitch in the X direction.
• the gate wiring 31 and the dummy gate wirings 32a, 32b, 33a, and 33b are formed with the same width in the X direction.
• Local wiring 41a, 41b, and 41c extending in the Y direction are formed in the local wiring layer.
• the local wiring is denoted as LI.
• Local wiring 41a is connected to a portion in active region 2P that serves as the source of transistor P1.
• Local wiring 41b is connected to a portion in active region 2N that serves as the source of transistor N1.
• Local wiring 41c extends from the P-type transistor region to the N-type transistor region, and is connected to a portion in active region 2P that serves as the drain of transistor P1, and a portion in active region 2N that serves as the drain of transistor N1.
• Metal wires 71 and 72 extending in the X direction are formed in the M0 wiring layer, which is a metal wiring layer above the local wiring layer.
• Metal wire 71 is connected to gate wiring 31 through a via.
• Metal wire 72 is connected to local wiring 41c through a via.
• Metal wire 71 corresponds to input node A, and metal wire 72 corresponds to output node Y.
• inverter cell CI1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with input A and output Y.
• inverter cell CI1 is a standard cell with a logic function.
• the terminal cell C11 is disposed at the left end in the X direction in the cell row CR1.
• terminal cell C11 is provided with power supply wiring 111, 112 extending in the X direction at both ends in the Y direction.
• Power supply wiring 111, 112 are formed in the BM0 layer, which is a wiring layer provided on the back surface of a semiconductor chip in which transistors are formed.
• Power supply wiring 111 supplies the same power supply voltage VDD as power supply wiring 11, and power supply wiring 112 supplies the same power supply voltage VSS as power supply wiring 12.
• Power supply wiring 111 is formed at the same position in the Y direction as power supply wiring 11 and is formed to the same width.
• Power supply wiring 112 is formed at the same position in the Y direction as power supply wiring 12 and is formed to the same width.
• an active region 2P1 that constitutes the channel, source, and drain of the P-type transistor is formed.
• the active region 2P1 overlaps with the power supply wiring 111.
• a P-type transistor PD1 which is a dummy transistor, is formed.
• Transistor PD1 has a nanosheet 121 as a channel, which is made up of three overlapping sheet structures in a plan view and extends in the X direction. Nanosheet 121 has the same width and position in the Y direction as nanosheet 21 in inverter cell CI1.
• an active region 2N1 that constitutes the channel, source, and drain of the N-type transistor is formed.
• the active region 2N1 overlaps with the power supply wiring 112.
• an N-type transistor ND1 that is a dummy transistor is formed.
• Transistor ND1 has a nanosheet 126 as a channel, which is made up of three overlapping sheets in a plan view and extends in the X direction. Nanosheet 126 has the same width and position in the Y direction as nanosheet 26 in inverter cell CI1.
• a dummy gate wiring 131 is formed extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the dummy gate wiring 131 surrounds the outer periphery in the Y direction and Z direction of the nanosheet 121 of the transistor PD1 and the nanosheet 126 of the transistor ND1 via a gate insulating film (not shown).
• Two dummy gate wirings 132 and 133 are formed on the left side of the dummy gate wiring 131 in the drawing, extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the dummy gate wiring 133 is disposed at the left end of the terminal cell C11.
• Local wiring 141, 142 extending in the Y direction are formed in the local wiring layer.
• Local wiring 141 extends from the P-type transistor region to the N-type transistor region, and is connected to the portion that becomes the drain of transistor PD1 in active region 2P1 and the portion that becomes the drain of transistor ND1 in active region 2N1.
• Local wiring 142 extends from the P-type transistor region to the N-type transistor region, and is connected to the portion that becomes the source of transistor PD1 in active region 2P1 and the portion that becomes the source of transistor ND1 in active region 2N1.
• dummy gate wiring 131, 132, 133 and local wiring 141, 142 are not connected to any other wiring.
• the termination cell C11 does not have an operating transistor.
• the termination cell C11 is a standard cell that does not have a logic function.
• the filler cell CF1 is provided with power supply wirings 13 and 14 extending in the X direction at both ends in the Y direction.
• the power supply wirings 13 and 14 are formed in the BM0 wiring layer.
• the power supply wiring 13 supplies the same power supply voltage VDD as the power supply wiring 11, and the power supply wiring 14 supplies the same power supply voltage VSS as the power supply wiring 12.
• the power supply wiring 13 is formed at the same position in the Y direction as the power supply wiring 11 and has the same width.
• the power supply wiring 14 is formed at the same position in the Y direction as the power supply wiring 12 and has the same width.
• an active region 2P2 that constitutes the channel, source, and drain of the P-type transistor is formed.
• the active region 2P2 overlaps with the power supply wiring 13.
• Transistors PD2 and PD3 have nanosheets 22 and 23 as channels, which are made of three sheet structures that overlap in a plan view and extend in the X direction. Nanosheets 22 and 23 have the same width and position in the Y direction as nanosheet 21 in inverter cell CI1.
• an active region 2N2 is formed that constitutes the channel, source, and drain of the N-type transistor. In plan view, the active region 2N2 overlaps with the power supply wiring 14.
• Transistors ND2 and ND3 have nanosheets 27 and 28, which are made up of three overlapping sheets in plan view and extend in the X direction, as channels. Nanosheets 27 and 28 have the same width and position in the Y direction as nanosheet 26 in inverter cell CI1.
• Dummy gate wiring 34, 35 are formed extending in the Y direction from the P-type transistor region to the N-type transistor region.
• Dummy gate wiring 34 surrounds the outer periphery in the Y direction and Z direction of nanosheet 22 of transistor PD2 and nanosheet 27 of transistor ND2 via a gate insulating film (not shown).
• Dummy gate wiring 35 surrounds the outer periphery in the Y direction and Z direction of nanosheet 23 of transistor PD3 and nanosheet 28 of transistor ND3 via a gate insulating film (not shown).
• a dummy gate wiring 36a is formed in the P-type transistor region, and a dummy gate wiring 36b is formed in the N-type transistor region.
• Local wiring 42, 43, 44 are formed in the local wiring layer, extending in the Y direction from the P-type transistor region to the N-type transistor region.
• Local wiring 42 is connected to the portion that becomes the drain of transistor PD2 in active region 2P2, and the portion that becomes the drain of transistor ND2 in active region 2N2.
• Local wiring 43 is connected to the portion that becomes the source of transistor PD2 and the drain of transistor PD3 in active region 2P2, and to the portion that becomes the source of transistor ND2 and the drain of transistor ND3 in active region 2N2.
• Local wiring 44 is connected to the portion that becomes the source of transistor PD3 in active region 2P2, and the portion that becomes the source of transistor ND3 in active region 2N2.
• dummy gate wirings 34, 35, 36a, and 36b and local wirings 42, 43, and 44 are not connected to any other wiring.
• filler cell CF1 does not have an operating transistor.
• filler cell CF1 is a standard cell that does not have a logic function.
• the active area 2P of the inverter cell CI1, the active area 2P1 of the terminal cell C11, and the active area 2P2 of the filler cell CF1 have the same width in the Y direction (WA1) and are located at the same position in the Y direction. That is, the nanosheet 21 of the inverter cell CI1, the nanosheet 121 of the terminal cell C11, and the nanosheets 22 and 23 of the filler cell CF1 have the same width and position in the Y direction, and are located at the same distance from the cell frame at the top of the drawing (SA1).
• the active area 2N of the inverter cell CI1, the active area 2N1 of the terminal cell C11, and the active area 2N2 of the filler cell CF1 have the same width in the Y direction (WA1) and are located at the same position in the Y direction. That is, the nanosheet 26 of the inverter cell CI1, the nanosheet 126 of the terminal cell C11, and the nanosheets 27 and 28 of the filler cell CF1 have the same width and position in the Y direction, and are the same distance from the cell frame at the bottom of the drawing (SA1).
• the dummy gate wirings 131, 132, and 133 in the terminal cell C11 and the dummy gate wirings 34 and 35 in the filler cell CF1 are formed at the same position in the Y direction as the gate wiring 31 of the inverter cell CI1 and are formed to the same length.
• the dummy gate wiring 133, dummy gate wiring 132, dummy gate wiring 131, dummy gate wirings 32a and 32b, gate wiring 31, dummy gate wirings 33a and 33b, dummy gate wiring 34, dummy gate wiring 35, and dummy gate wirings 36a and 36b are arranged at the same pitch in the X direction and have the same positions at both ends in the Y direction.
• the local wirings 141 and 142 in the termination cell C11 and the local wirings 42, 43, and 44 in the filler cell CF1 have the same positions at both ends in the Y direction as the local wirings 41a, 41b, and local wiring 41c in the inverter cell CI1. Furthermore, the local wirings 141, 142, local wirings 41a and 41b, local wiring 41c, local wiring 42, local wiring 43, and local wiring 44 are arranged at the same pitch in the X direction.
• the gate wiring and local wiring including the dummy gate wiring are arranged in a regular pattern. This makes it possible to suppress variation in the finished shape of the layout pattern of the cells arranged inside the circuit block from the terminal cell, thereby suppressing manufacturing variation in the semiconductor integrated circuit device, improving yield and reliability.
• the dummy gate wiring 131-133 in the termination cell C11 is formed with the same length in the Y direction as the gate wiring 31 in the inverter cell CI1. This makes it possible to suppress variations in the finished shape of the layout pattern, and thus suppress manufacturing variations in the semiconductor integrated circuit device.
• the local wirings 141 and 142 in the terminal cell C11 are arranged so that the positions of both ends in the Y direction are the same as the local wirings 41a, 41b and local wiring 41c in the inverter cell CI1. This makes it possible to make the distance from the logic unit LC to the nearest local wiring constant, thereby improving the performance predictability of the cells arranged in the logic unit LC. In addition, it is possible to suppress variations in the finished shape of the layout pattern, thereby suppressing manufacturing variations in the semiconductor integrated circuit device.
• the number of dummy gate wirings and local wirings arranged in the terminal cell C11 is not limited to this.
• the number of dummy gate wirings and local wirings arranged in the terminal cell C11 is required to suppress variation in the finished dimensions of the end of the logic section.
• the cell width (size in the X direction) of the terminal cell C11 may be changed depending on the number of dummy gate wirings and local wirings arranged in the terminal cell C11.
• the dummy gate wirings 131-133 in the terminal cell C11 are formed to have the same length in the Y direction as the gate wiring 31 in the inverter cell CI1, but this is not limited to the above. However, forming them to have the same length in the Y direction can better suppress manufacturing variations in the circuit blocks.
• the local wirings 141 and 142 in the terminal cell C11 are arranged so that both ends in the Y direction are in the same position as the local wirings 41a, 41b and local wiring 41c in the inverter cell CI1, but this is not limited to the above. However, by arranging the both ends in the Y direction in the same position, manufacturing variations in the circuit blocks can be further suppressed.
• a terminal cell that is the inverted terminal cell C11 described above in the X direction is placed at the right end of cell row CR1.
• power supply wiring 11, 12, 13, 14, 111, and 112 are formed in a wiring layer provided on the back surface of the semiconductor chip, this is not limited to this.
• the power supply wiring may be formed on the back surface side of the transistor.
• the back surface side of the transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked.
• the power supply wiring 11, 12, 13, 14, 111, and 112 may be formed in multiple wiring layers.
• the power supply wiring formed on the back surface side of the transistor may be formed using a semiconductor chip separate from the semiconductor chip on which the transistor is formed.
• FIG. 4(a) is another configuration example of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 100 shown in FIG. 4(a) is configured by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B).
• Chip A has power wiring formed in a wiring layer provided on its surface.
• Chip B is attached to the back side of chip A using bumps or the like.
• FIG. 4(b) shows a cross section of the line Y1-Y1' in the inverter cell CI1 of FIG. 2 in this configuration example.
• a power supply wiring 11 that supplies VDD and a power supply wiring 12 that supplies VSS are formed in a wiring layer provided on the surface of chip B.
• the power supply wiring 11 is connected to the active region 2P of chip A through a via 61.
• the power supply wiring 12 is connected to the active region 2N of chip A through a via 62.
• the power supply wirings 111, 112 of the termination cell C11 and the power supply wirings 13, 14 of the filler cell CF1 are also formed in a wiring layer provided on the surface of chip B.
• the power supply wiring 11, 12, 13, 14, 111, and 112 may be formed in multiple wiring layers.
• FIG. 5A and 5B are plan views showing layout structures of modified examples of the termination cell.
• the active regions 2P1 and 2N1 are further extended to the left in the drawing, and in addition, a local wiring 143 is added.
• the active regions 2P1 and 2N1 are not extended, and a local wiring 143 is added.
• the dummy gate wiring 133 in the configuration of Fig. 5B is deleted.
• a termination cell having the configuration shown in FIGS. 5(a) to (c) may be arranged. Also, in the configuration shown in FIGS. 5(a) to (c), the active regions 2P1 and 2N1 may be omitted.
• (Layout of part W2) 6 is an enlarged view of portion W2 in FIG. 1, and is a plan view showing the layout structure of a standard cell in this embodiment.
• portion W2 is a part of cell string CR2.
• inverter cell CI2 is arranged at the right end of logic section LC in the drawing, and termination cell C12 is arranged adjacent to it on the right side.
• filler cell CF2 is arranged adjacent to inverter cell CI2 on the left side.
• the layout in FIG. 6 is almost the same as the layout in FIG. 2, flipped left to right.
• the cell height H2 is higher than the cell height H1 in FIG. 2, the size of each component differs from that in the layout in FIG. 2.
• the wiring width of the power supply wiring is WP2, which is larger than the wiring width WP1 of the power supply wiring shown in FIG. 2 (WP2>WP1). Details of the layout can be easily inferred from the above content, so a description will be omitted here.
• the active areas of inverter cell CI2, termination cell C12, and filler cell CF2 have the same width in the Y direction (WA2) and the same position in the Y direction. That is, the nanosheets in the P-type transistor region of portion W2 have the same width and position in the Y direction. Width WA2 is greater than width WA1 in the layout of FIG. 2. In addition, the nanosheets in the P-type transistor region of portion W2 have the same distance from the cell frame at the top of the drawing (SA1), which is the same as distance SA1 in portion W1 shown in FIG. 2.
• the active areas of inverter cell CI2, termination cell C12, and filler cell CF2 have the same width in the Y direction (WA2) and the same position in the Y direction.
• the nanosheets in the N-type transistor region of portion W2 have the same width and position in the Y direction.
• the nanosheets in the N-type transistor region of portion W2 have the same distance from the cell frame at the bottom of the drawing (SA1), which is the same as the distance SA1 in portion W1 shown in Figure 2.
• the width WA1 in the Y direction of the nanosheet in portion W1 of cell row CR1 is smaller than the width WA2 in the Y direction of the nanosheet in portion W2 of cell row CR2 (WA1 ⁇ WA2).
• the active region and nanosheet of the terminal cell C11 and filler cell CF1 have the same width and position in the Y direction relative to the active region and nanosheet of the inverter cell CI1.
• the active region and nanosheet of the terminal cell C12 and filler cell CF2 have the same width and position in the Y direction relative to the active region and nanosheet of the inverter cell CI2. This makes it possible to always keep constant the width and position in the Y direction of the active region adjacent to the active region of the inverter cell.This improves the performance predictability of the transistors that make up the inverter, and also makes it possible to suppress manufacturing variations in semiconductor integrated circuit devices, thereby improving yields.
• inverter cells have been used as an example of logic cells, but logic cells other than inverters, such as NAND cells, NOR cells, and FF cells, may also be arranged. Even in this case, the same effect can be obtained by making the width and position in the Y direction of the active region and nanosheet the same for the logic cells and the adjacent termination cells and filler cells.
• the termination cells and filler cells may be double-height cells arranged from a cell row CR1 of height H1 to a cell row CR2 of height H2.
• FIG. 7 shows an example of a layout structure for a double-height cell, where (a) is a terminal cell and (b) is a filler cell.
• the configuration of the terminal cell in FIG. 7(a) corresponds to a configuration in which the configuration of terminal cell C12 shown in FIG. 6 is inverted vertically and horizontally and connected to the upper side of terminal cell C11 shown in FIG. 2.
• the configuration of the filler cell in FIG. 7(b) corresponds to a configuration in which the configuration of filler cell CF2 shown in FIG. 6 is inverted vertically and connected to the upper side of filler cell CF1 shown in FIG. 2. Details of the configuration can be easily understood from the above explanation, so a description will be omitted here.
• the amount of design data can be reduced by preparing and using a double-height cell such as that shown in Figure 7.
• Second Embodiment 8 is an enlarged view of a portion W3 in FIG. 1, and is a plan view showing a layout structure of a standard cell according to the second embodiment.
• the terminal cell C31 is arranged in a cell row CR1 arranged in the top row in the Y direction of the circuit block.
• the terminal cell C31 is also arranged adjacent to the upper side of the inverter cell CI2 in the cell row CR2 arranged at the upper end of the logic unit LC in the drawing.
• the terminal cell C31 is provided with power supply wiring 211, 212 extending in the X direction at both ends in the Y direction.
• the power supply wiring 211, 212 are formed in the BM0 layer, which is a wiring layer provided on the back surface of the semiconductor chip in which the transistors are formed.
• the power supply wiring 211, 212 have a wiring width of WP1.
• the power supply wiring 211 is formed integrally with the power supply wiring 11 of the inverter cell CI2, and supplies the same power supply voltage VDD as the power supply wiring 11.
• the power supply wiring 212 supplies the same power supply voltage VSS as the power supply wiring 12.
• an active region 2P3 that constitutes the channel, source, and drain of the P-type transistor is formed in a P-type transistor region on an N-type well (NWell).
• the active region 2P3 overlaps with the power supply wiring 211 in a planar view.
• the active region 2P3 includes nanosheets 221a and 221b that constitute a dummy transistor.
• the nanosheets 221a and 221b are made up of three overlapping sheets in a planar view, and extend in the X direction.
• an active region 2N3 that constitutes the channel, source, and drain of an N-type transistor is formed.
• the active region 2N3 overlaps with the power supply wiring 212.
• the active region 2N3 includes nanosheets 226a and 226b that constitute a dummy transistor.
• the nanosheets 226a and 226b are made up of three overlapping sheets in a plan view, and extend in the X direction.
• Dummy gate wiring 231, 232 are formed extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the dummy gate wiring 231 surrounds the outer periphery in the Y direction and Z direction of the nanosheet 221a included in the active region 2P3 and the nanosheet 226a included in the active region 2N3 via a gate insulating film (not shown).
• the dummy gate wiring 232 surrounds the outer periphery in the Y direction and Z direction of the nanosheet 221b included in the active region 2P3 and the nanosheet 226b included in the active region 2N3 via a gate insulating film (not shown).
• a dummy gate wiring 233 is formed, extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the dummy gate wiring 233 is located at the left end of the termination cell C31 in the drawing.
• a dummy gate wiring 234 is formed, extending in the Y direction from the P-type transistor region to the N-type transistor region.
• the dummy gate wiring 234 is located at the right end of the termination cell C31 in the drawing.
• Local wiring 241, 242, and 243 extending in the Y direction are formed in the local wiring layer.
• the local wiring 241 extends from the P-type transistor region to the N-type transistor region, and is connected to the portion between the dummy gate wirings 231 and 233 in the active region 2P3 and the portion between the dummy gate wirings 231 and 233 in the active region 2N3.
• the local wiring 242 extends from the P-type transistor region to the N-type transistor region, and is connected to the portion between the dummy gate wirings 231 and 232 in the active region 2P3 and the portion between the dummy gate wirings 231 and 232 in the active region 2N3.
• the local wiring 243 extends from the P-type transistor region to the N-type transistor region, and is connected to the portion between the dummy gate wirings 232 and 234 in the active region 2P3 and the portion between the dummy gate wirings 232 and 234 in the active region 2N3.
• dummy gate wiring 231, 232, 233, 234 and local wiring 241, 242, 243 are not connected to any other wiring.
• termination cell C31 does not have an operating transistor.
• termination cell C31 is a standard cell that does not have a logic function.
• the width in the Y direction of the active areas 2P3, 2N3 and the nanosheets 221a, 221b, 226a, 226b in the terminal cell C31 is WA1, which is the same as the active areas and nanosheets in the cells of the cell row CR1 adjacent to the inverter cell CI2 on the lower side of the drawing.
• the nanosheets 221a, 226a in the terminal cell C31 are formed in the same position in the X direction as the nanosheets 21, 26 in the inverter cell CI2.
• the dummy gate wirings 231, 232, 233, and 234 in the terminal cell C31 are arranged at the same pitch in the X direction, and the positions of both ends in the Y direction are the same.
• the dummy gate wiring 231 in the terminal cell C31 is arranged in the same position in the X direction as the gate wiring 31 in the inverter cell CI2.
• the dummy gate wiring 232 in the terminal cell C31 is arranged in the same position in the X direction as the dummy gate wirings 32a and 32b in the inverter cell CI2.
• the dummy gate wiring 233 in the terminal cell C31 is arranged in the same position in the X direction as the dummy gate wirings 33a and 33b in the inverter cell CI2.
• the local wirings 241, 242, and 243 in the terminal cell C31 are arranged at the same pitch in the X direction, and the positions of both ends in the Y direction are the same.
• the local wiring 241 in the terminal cell C31 is arranged in the same position in the X direction as the local wiring 41c in the inverter cell CI2.
• the local wiring 242 in the terminal cell C31 is arranged in the same position in the X direction as the local wirings 41a and 41b in the inverter cell CI2.
• the terminal cell C31 with height H1 is arranged adjacent to the upper side of the inverter cell CI2 located in the top row of the logic unit LC. Therefore, for the P-type transistor P1 of the inverter cell CI2, the position and width of the nanosheet adjacent in the Y direction (nanosheet 221a of the terminal cell C31) is the same as when a cell with height H1 other than the terminal cell (e.g., inverter cell CI1 or filler cell CF1) is adjacent to the inverter cell CI2 in the Y direction. This improves the performance predictability of the transistors that make up the inverter cell, suppresses manufacturing variations in semiconductor integrated circuit devices, and improves yield.
• a cell with height H1 other than the terminal cell e.g., inverter cell CI1 or filler cell CF1
• the nanosheets 221a and 221b of the terminal cell C31 are located at the same distance from the boundary between the inverter cell CI2 and the terminal cell C31 as the nanosheet 21 of the inverter cell CI2. This makes it possible to suppress the variation in the finished shape of the layout pattern of the cells arranged inside the circuit block from the terminal cell, thereby suppressing the manufacturing variation of the semiconductor integrated circuit device, improving the yield, and improving the reliability.
• the terminal cell C31 is provided with a dummy transistor, a dummy gate wiring, and a local wiring.
• a nanosheet is formed at the same position in the X direction as the nanosheet of the inverter cell CI2.
• a dummy gate wiring is arranged at the same position in the X direction as the gate wiring of the inverter cell CI2.
• a local wiring is arranged at the same position in the X direction as the local wiring of the inverter cell CI2.
• the transistors including the dummy transistors, the gate wiring including the dummy gate wiring, and the local wiring are arranged regularly. Therefore, in the circuit block, it is possible to suppress the variation in the finished shape of the layout pattern of the cells arranged inside the terminal cell, and it is possible to suppress the manufacturing variation of the semiconductor integrated circuit device, improve the yield, and improve the reliability.
• the cell width of the terminal cell C31 is not limited to that shown in FIG. 8.
• FIG. 9 is an enlarged view of portion W4 in FIG. 1, and is a plan view showing the layout structure of a standard cell according to this embodiment.
• the terminal cell C32 is arranged in cell row CR2, which is arranged in the bottom row in the Y direction of the circuit block. Furthermore, the terminal cell C32 is arranged adjacent to the lower side of the inverter cell CI1 in cell row CR1, which is arranged at the bottom end of the logic unit LC in the drawing.
• FIG. 9 corresponds to the configuration in FIG. 8 flipped upside down and with the heights of the termination cells and inverter cells swapped. Details of the layout structure can be easily understood from the above description, so a detailed explanation is omitted here.
• a terminal cell C32 of height H2 is arranged adjacent to the inverter cell CI1 located in the bottom row of the logic unit LC on the lower side of the drawing. Therefore, for the P-type transistor P1 of the inverter cell CI1, the position and width of the nanosheet adjacent in the Y direction (the nanosheet of the terminal cell C32) is the same as when a cell of height H2 other than the terminal cell (e.g., inverter cell CI2 or filler cell CF2) is adjacent to the inverter cell CI1 in the Y direction. This improves the performance predictability of the transistors that make up the inverter cell, suppresses manufacturing variations in semiconductor integrated circuit devices, and improves yield.
• the configuration of FIG. 9 has the same characteristics as the configuration of FIG. 8, so it is possible to suppress variation in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variation in semiconductor integrated circuit devices, improving yields, and improving reliability.
• the cell width of the terminal cell C32 is not limited to that shown in FIG. 9.
• (Modification) 10 is a plan view showing a layout structure of a termination cell according to a modified example of this embodiment.
• the configuration of the termination cell C31 in FIG. 8 on the VSS side at the upper side of the drawing is omitted. That is, the power supply wiring 212 and the active region 2N3 are omitted, the dummy gate wirings 231-234 are replaced with short dummy gate wirings 235-238, and the local wirings 241-243 are replaced with short local wirings 244-246.
• the termination cell C31 in FIG. 10 is smaller in size in the Y direction than the cell with the cell height H1 in the cell row CR1 in the logic unit LC. Also, the termination cell C31 in FIG. 10 does not include an N-type transistor, but only includes a P-type transistor.
• the power supply wiring 211, active region 2P3, dummy gate wiring 235-238, and local wiring 244-246 are also arranged on the side of the logic unit LC facing inverter cell CI2. This makes it possible to suppress variation in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variation in semiconductor integrated circuit devices, improving yields, and improving reliability.
• FIG. 11 is a plan view showing the layout structure of a termination cell according to a modified example of this embodiment.
• the configuration of the VSS side at the bottom of the drawing is omitted from the configuration of termination cell C32 in FIG. 9.
• the size of termination cell C32 in FIG. 11 is smaller in the Y direction than the cell with cell height H2 in cell row CR2 in logic unit LC.
• termination cell C32 in FIG. 11 does not have an N-type transistor, but only a P-type transistor.
• the configuration of FIG. 11 also makes it possible to suppress variation in the finished shape of the layout pattern of cells arranged inside the terminal cell in the circuit block, thereby suppressing manufacturing variation in semiconductor integrated circuit devices, improving yields, and improving reliability.
• the VSS side configuration is omitted, but part of the VSS side configuration may be omitted. Also, if the termination cell has a VSS side configuration adjacent to the cells that make up the logic unit LC, the VDD side configuration may be omitted. In this case, the termination cell does not have a P-type transistor, but only an N-type transistor.
• the circuit block is rectangular, but this is not limited to this. Also, in FIG. 1, six rows of cells are arranged in the circuit block, but the number of rows of cells arranged in the circuit block is not limited to this.
• the nanosheet is illustrated as having three overlapping sheet structures in a plan view, and the cross-sectional shape of the sheet structure is rectangular, but the number of sheet structures of the nanosheet and the cross-sectional shape are not limited to this.
• the transistors are nanosheet FETs, but this is not limited to this.
• they may be fin FETs or other types of transistors.
• the present disclosure makes it possible to suppress manufacturing variability, improve yields, and increase reliability for semiconductor integrated circuit devices that include standard cells of different heights, thereby making it possible to, for example, reduce the size of semiconductor integrated circuit devices and improve their performance.

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  • 2024-01-19 JP JP2024574440A patent/JPWO2024162047A1/ja active Pending
  • 2024-01-19 WO PCT/JP2024/001518 patent/WO2024162047A1/ja not_active Ceased
• 2025
  • 2025-06-18 US US19/242,640 patent/US20250318272A1/en active Pending

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