WO2024159997A1 - 栅极驱动电路、显示面板、显示装置以及显示驱动方法 - Google Patents

栅极驱动电路、显示面板、显示装置以及显示驱动方法 Download PDF

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Publication number
WO2024159997A1
WO2024159997A1 PCT/CN2024/070025 CN2024070025W WO2024159997A1 WO 2024159997 A1 WO2024159997 A1 WO 2024159997A1 CN 2024070025 W CN2024070025 W CN 2024070025W WO 2024159997 A1 WO2024159997 A1 WO 2024159997A1
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WIPO (PCT)
Prior art keywords
signal
data
display
node
frame start
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Ceased
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PCT/CN2024/070025
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English (en)
French (fr)
Inventor
贺雪英
王明强
包征
张家祥
傅晓亮
罗赞
张斌
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to US18/859,293 priority Critical patent/US12651577B2/en
Publication of WO2024159997A1 publication Critical patent/WO2024159997A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a gate driving circuit, a display panel, a display device, and a display driving method.
  • the display devices In display devices equipped with Organic Light-Emitting Diode (OLED) screens, due to the influence of driving circuits and device structures, the display devices generally have a problem of low brightness in the first frame when switching display images, which seriously affects the user experience.
  • OLED Organic Light-Emitting Diode
  • the present disclosure provides a gate driving circuit, comprising: a first frame start signal line and a cascade circuit;
  • the first frame start signal line is connected to the first input terminal of the cascade circuit and is configured to: transmit a first frame start signal to the cascade circuit in a first display phase;
  • the cascade circuit includes a plurality of shift registers cascaded to each other, each of the shift registers is connected to a clock signal line, an output end of the shift register is connected to a writing module in a pixel driving circuit, and the cascade circuit is configured to output a first scanning signal step by step according to the first frame start signal and a clock signal input by the clock signal line;
  • the effective level of the first frame start signal within one cycle overlaps with multiple pulse signals of the clock signal
  • the first scanning signal includes multiple scanning pulse signals within one cycle
  • the writing module is used to write the data signal into the pixel driving circuit under the control of the first scanning signal.
  • the gate drive circuit further includes:
  • a second frame start signal line is connected to the second input terminal of the cascade circuit and is configured to: transmit a second frame start signal to the cascade circuit in a second display phase;
  • the cascade circuit is further configured to: output a second scanning signal step by step according to the second frame start signal and the clock signal;
  • the number of pulse signals whose effective level of the second frame start signal overlaps with the clock signal in one cycle is less than the number of pulse signals whose effective level of the first frame start signal overlaps with the clock signal in one cycle, and the number of scan pulse signals included in the second scan signal in one cycle is greater than or equal to 1, and less than the number of scan pulse signals included in the first scan signal in one cycle.
  • the first frame start signal line and the second frame start signal line are independently configured, or share the same signal line.
  • the number of pulse signals whose effective level of the first frame start signal overlaps with the clock signal within one cycle is greater than or equal to 2 and less than or equal to 5.
  • an effective level of the second frame start signal in one period overlaps with a pulse signal of the clock signal.
  • the effective level of the first frame start signal is a low level.
  • the second frame start signal has the same active level voltage as the first frame start signal.
  • the signal input end of the first-stage shift register is connected to the first input end and the second input end
  • the output end of the E-stage shift register is connected to the signal input end of the E+F-stage shift register
  • the output end of the M-stage shift register is connected to the reset signal input end of the M-N-stage shift register, wherein 1 ⁇ E ⁇ H, F ⁇ 1, E+F ⁇ H, 1 ⁇ M ⁇ H, 1 ⁇ N ⁇ M, and E, F, H, M and N are all positive integers
  • H is the total number of shift registers in the cascade circuit.
  • the present disclosure provides a display panel, comprising:
  • a plurality of pixel driving circuits arranged in an array
  • a plurality of light emitting devices wherein the light emitting devices are connected to a pixel driving circuit located in the same pixel;
  • a plurality of scanning signal lines wherein the scanning signal lines are connected to scanning signal terminals of pixel driving circuits located in the same row;
  • a plurality of data signal lines wherein the data signal lines are connected to the data of the pixel driving circuit in the same column Signal terminal connections;
  • output ends of the plurality of shift registers in the cascade circuit are respectively connected to different scanning signal lines;
  • the pixel driving circuit is configured to: write the data signal at the data signal end into the pixel driving circuit according to the signal at the scanning signal end, so as to drive the light emitting device to emit light.
  • the plurality of data signal lines include a first data signal line and a second data signal line
  • the display panel further includes: a signal terminal, a first data selection circuit and a second data selection circuit, the first data signal line is connected to the signal terminal through the first data selection circuit, and the second data signal line is connected to the signal terminal through the second data selection circuit.
  • the pixel driving circuit includes:
  • a writing module connected to the data signal terminal, the first node and the scanning signal terminal, and configured to: in a compensation phase, write the data signal into the first node in response to a signal at the scanning signal terminal;
  • a driving module connected to the first node, the second node and the third node, and configured to: write the signal of the first node into the second node under the potential control of the third node;
  • a compensation module connected to the second node, the third node and the scanning signal terminal, and configured to: in a compensation phase, write the signal of the second node into the third node according to the signal of the scanning signal terminal;
  • a light-emitting control module is connected to the first voltage terminal, the enable signal terminal, the first node, the second node and the light-emitting device, and is configured to: in a light-emitting stage, cooperate with the driving module according to the enable signal of the enable signal terminal to drive the light-emitting device to emit light;
  • a storage module connected to the first voltage terminal and the third node, and configured to store a signal of the third node
  • a first reset module is connected to the third node, the first reset signal terminal and the reset control signal terminal, and is configured to: write the signal of the first reset signal terminal into the third node according to the signal of the reset control signal terminal;
  • the second reset module is connected to the anode of the light emitting device, the second reset signal terminal and the scan signal terminal, and is configured to write the signal of the second reset signal terminal into the anode of the light emitting device according to the signal of the scan signal terminal.
  • the ratio of the brightness of the first frame to the preset frame is the first frame brightness ratio
  • the first frame brightness ratio is greater than or equal to 85%
  • the preset frame is any frame after the same picture is stably displayed.
  • the present disclosure provides a display device, comprising:
  • the display driver chip is connected to the display panel and is used to provide a driving signal to the display panel.
  • the driving signal includes: the first frame start signal, the clock signal and the data signal.
  • the present disclosure provides a display driving method, which is applied to a display panel as described in any embodiment, and the display driving method includes:
  • a first frame start signal is provided to the first frame start signal line so that the first frame start signal line transmits the first frame start signal to the cascade circuit, and the cascade circuit outputs a first scanning signal step by step according to the first frame start signal and the clock signal.
  • the gate driving circuit further includes a second frame start signal line
  • the second frame start signal line is connected to the second input terminal of the cascade circuit
  • a second frame start signal is provided to the second frame start signal line so that the second frame start signal line transmits the second frame start signal to the cascade circuit, and the cascade circuit outputs a second scanning signal step by step according to the second frame start signal and the clock signal.
  • the method before the steps of providing a first frame start signal to the first frame start signal line and providing a second frame start signal to the second frame start signal line, the method further includes:
  • the display data includes a previous frame of display data and a next frame of display data, wherein the previous frame of display data and the next frame of display data are display data of two adjacent frames;
  • the previous frame display data is compared with the next frame display data, and according to the comparison result, the steps in the first display stage or the steps in the second display stage are executed.
  • executing the steps in the first display stage or the steps in the second display stage according to the comparison result includes:
  • the first scan signal includes a plurality of scan pulse signals
  • the plurality of scan signal lines include a first scan signal line
  • the plurality of data signal lines include a first data signal line
  • the pixel driving circuit connected to the first scan signal line and the first data signal line is a first pixel driving circuit.
  • a plurality of compensation stages are separated from each other, each of which comprises: inputting the scanning pulse signal to the scanning signal end of the first pixel driving circuit, providing a data signal to the data signal end of the first pixel driving circuit, so that the data signal is written into the first pixel driving circuit.
  • the plurality of data signal lines further include a second data signal line
  • the display panel further includes a signal terminal, a first data selection circuit, and a second data selection circuit
  • the first data signal line is connected to the signal terminal through the first data selection circuit
  • the second data signal line is connected to the signal terminal through the second data selection circuit
  • the data signal is provided to the signal terminal, the first data selection circuit is controlled to be turned on, and the second data selection circuit is controlled to be turned off, so that the data signal is written into a first data storage capacitor, and one plate of the first data storage capacitor is connected to the first data signal line.
  • the first pixel driving circuit when the first pixel driving circuit includes a writing module, a driving module, a compensation module, a light emitting control module and a first reset module, and the writing module is connected to the data signal terminal, the first node and the scanning signal terminal, the driving module is connected to the first node, the second node and the third node, the compensation module is connected to the second node, the third node and the scanning signal terminal, the light emitting control module is connected to the first voltage terminal, the enable signal terminal, the first node, the second node and the light emitting device, and the first reset module is connected to the third node, the first reset signal terminal and the reset control signal terminal, the compensation stage is used to write the data signal into the first node, the second node and the third node in sequence, Before each of the compensation stages, it also includes:
  • a first reset signal is provided to the first reset signal terminal, and a reset control signal is provided to the reset control signal terminal, so that the first reset signal is written into the third node;
  • the method further includes:
  • an enable signal is provided to the enable signal terminal so that the light-emitting control module cooperates with the drive module to drive the light-emitting device to emit light.
  • FIG1 shows a schematic structural diagram of a gate driving circuit provided by the present disclosure
  • FIG2a shows a driving signal timing diagram of a gate driving circuit
  • FIG2 b shows a schematic diagram of a circuit structure of a shift register
  • FIG3 shows a brightness-time curve of the first display panel
  • FIG4 shows a brightness-time curve of a second display panel
  • FIG5 shows a schematic structural diagram of a display panel provided by the present disclosure
  • FIG6 shows a "virtual edge" defect of a display panel
  • FIG7 shows a timing diagram of a driving signal of a display panel
  • FIG8 shows a schematic structural diagram of a pixel driving circuit provided by the present disclosure
  • FIG9 shows a schematic structural diagram of a display device provided by the present disclosure
  • FIG10 shows a first driving signal timing diagram of a pixel driving circuit
  • FIG. 11 shows a second driving signal timing diagram of a pixel driving circuit.
  • OLED displays are often in a state of looping video playback. Due to the influence of the drive circuit and device structure, when the display switches the display screen, the brightness of the first frame is usually only 60% of the required brightness. For the more sensitive human eye, the phenomenon seen is that there will be a ghost image in the first frame after the screen is switched.
  • the first frame response or first frame brightness ratio (First Frame Ratio, FFR) is usually used to characterize this phenomenon. The higher the FFR value, the less obvious the ghost image.
  • the gate drive circuit includes: a first frame start signal line 11 and a cascade circuit 12.
  • the first frame start signal line 11 is connected to the first input terminal Input1 of the cascade circuit 12, and the first frame start signal line 11 is configured to: in the first display stage, transmit the first frame start signal GSTV1 to the cascade circuit 12.
  • the cascade circuit 12 includes a plurality of shift registers 13 cascaded to each other, each shift register 13 is connected to a clock signal line 14, and the cascade circuit 12 is configured to: output the first scan signal G1 step by step according to the first frame start signal GSTV1 and the clock signal GCK input by the clock signal line 14.
  • the effective level of the first frame start signal GSTV1 in one cycle overlaps with a plurality of pulse signals of the clock signal GCK, and the first scan signal G1 includes a plurality of scan pulse signals in one cycle.
  • one cycle refers to one frame cycle (1Frame as shown in FIG. 2a ), that is, when the display panel displays multiple frames, the display cycle of each frame is the inverse of the refresh rate of the display panel.
  • the output terminal Output of the shift register 13 and the writing module 81 in the pixel driving circuit 51 can be connected through a scanning signal line gate, and the scanning signal line gate is connected to the scanning signal terminal Vgate of the writing module 81.
  • the writing module 81 is used to write the data signal into the pixel driving circuit 51 under the control of the first scanning signal G1.
  • the effective level of the first frame start signal GSTV1 in one cycle overlaps with three pulse signals of the clock signal GCK.
  • the effective level of the first frame start signal GSTV1 in one cycle is The number of pulse signals overlapped by the clock signal GCK is greater than or equal to 2 and less than or equal to 5. As shown in FIG2a , the number of pulse signals overlapped by the active level of the first frame start signal GSTV1 and the clock signal GCK in one cycle is 3.
  • the effective level of the first frame start signal GSTV1 is a low level.
  • the input terminal Input of the first stage shift register GOA1 is connected to the first input terminal Input1 of the cascade circuit 12 , or is multiplexed as the first input terminal Input1 of the cascade circuit 12 (as shown in FIG. 1 ).
  • the output terminal Output of the E-th stage shift register 13 is connected to the input terminal Input of the E+F-th stage shift register 13, and the output terminal Output of the M-th stage shift register 13 is connected to the reset terminal Rst of the M-N-th stage shift register 13, wherein 1 ⁇ E ⁇ H, F ⁇ 1, E+F ⁇ H, 1 ⁇ M ⁇ H, 1 ⁇ N ⁇ M, and E, F, H, M and N are all positive integers, and H is the total number of shift registers 13 in the cascade circuit 12.
  • the first scan signal G1 outputted therefrom can be outputted to the scan signal line gate, and can also be used as the start signal of the next stage of the shift register 13 and the reset signal of the previous stage of the shift register 13.
  • the start signal of the first stage of the shift register GOA1 is the first frame start signal GSTV1
  • the first stage of the shift register GOA1 may not output a reset signal
  • the last stage of the shift register 13 may be connected to a row of redundant shift registers 13 to achieve the reset of the last stage of the shift register 13.
  • the shift register 13 may include a charging module 21, an output module 22, a storage capacitor C and a reset module 23.
  • the charging module 21 is respectively connected to the input terminal Input and the pull-up node PU of the shift register 13, and is used to write the signal of the input terminal Input into the pull-up node PU according to the signal of the input terminal Input;
  • the output module 22 is respectively connected to the clock signal input terminal GCK, the pull-up node PU and the output terminal Output, and is used to write the clock signal of the clock signal input terminal GCK into the output terminal Output according to the potential of the pull-up node PU;
  • the storage capacitor C is connected between the pull-up node PU and the output terminal Output, and is used to store the voltage of the pull-up node PU;
  • the reset module 23 is respectively connected to the reset terminal Rst, the reset signal terminal VSS, the pull-up node PU and the output terminal Output, and is used to write the signal of the reset signal terminal VSS into the
  • the charging module 21 includes a transistor M1, a control electrode of the transistor M1 and a first The first electrode of transistor M1 is connected to the input terminal Input of shift register 13, and the second electrode of transistor M1 is connected to the pull-up node PU.
  • Output module 22 includes transistor M3, the control electrode of transistor M3 is connected to the pull-up node PU, the first electrode of transistor M3 is connected to the clock signal input terminal GCK, and the second electrode of transistor M3 is connected to the output terminal Output of shift register 13.
  • Reset module 23 includes transistor M2 and transistor M4, the control electrode of transistor M2 is connected to the pull-down node PD, the first electrode of transistor M2 is connected to the reset signal terminal VSS, the second electrode of transistor M2 is connected to the pull-up node PU, the control electrode of transistor M4 is connected to the pull-down node PD, the first electrode of transistor M4 is connected to the reset signal terminal VSS, and the second electrode of transistor M4 is connected to the output terminal Output.
  • transistors M1 to M4 are all P-type transistors.
  • the first frame start signal line 11 provides the first frame start signal GSTV1 to the input end of the first-stage shift register GOA1.
  • the transistor M1 when the input end Input of the first-stage shift register GOA1 is connected to the low-level first frame start signal GSTV1, the transistor M1 is turned on, the potential of the pull-up node PU is low, and the transistor M3 is also in the on state, so that the signal of the clock signal input end GCK is written to the output end Output, and then the first scan signal is output.
  • the first scan signal output by the output end Output includes three scan pulse signals in one cycle.
  • the cascade circuit 12 generates a multi-pulse first scanning signal G1 step by step under the action of the first frame start signal GSTV1 and the clock signal GCK.
  • the working process of the shift registers 13 at each stage after the first stage shift register GOA1 is similar to that of the first stage shift register GOA1, and will not be repeated here. It can be understood that the number of pulse signals whose effective level of the first frame start signal GSTV1 overlaps with the clock signal GCK in one cycle is the same as the number of scanning pulse signals included in the first scanning signal G1 in one cycle.
  • the display panel may include: a pixel driving circuit 51, a light-emitting device 52 (as shown in FIG8 ), a scanning signal line gate, and a data signal line data.
  • An output terminal Output of a shift register 13 is connected to a scanning signal line gate, and a signal output by the output terminal Output is transmitted to the pixel driving circuit 51 through the scanning signal line gate.
  • the pixel driving circuit 51 writes the data signal input by the data signal line data into the pixel driving circuit 51 (the gate of the driving transistor T3 shown in FIG8 , i.e., the third node N3) according to the signal of the scanning signal line gate, so as to drive the light-emitting device 52 to emit light.
  • the pixel driving circuit 51 can perform multiple voltage biases on the gate of the driving transistor T3 before the light-emitting device 52 emits light, thereby compensating the threshold voltage of the driving transistor T3 multiple times, so that the threshold voltage of the driving transistor T3 shifts toward the negative direction, thereby reducing the difference between the threshold voltages in the compensation stage and the light-emitting stage, thereby improving the brightness of the display screen.
  • the first display panel adopts the gate drive circuit provided by the present disclosure, and the test results are shown in Figure 3.
  • the second display panel adopts the gate drive circuit in the related art (the output scanning signal includes a scanning pulse signal in one cycle), and the test results are shown in Figure 4.
  • the ratio of the brightness of the first frame to the preset frame is the FFR value.
  • the preset frame can be any frame after the above-mentioned same picture is stably displayed.
  • the fourth frame is used as the preset frame.
  • the gate drive circuit 10 provided by the present disclosure can significantly improve the FFR value of the display panel and improve the problem of ghosting in the first frame after switching the screen.
  • the first display stage may include the first frame display stage after the screen is switched, and may also include any frame display stage after the switched screen is stably displayed. As shown in FIG. 3 , the first display stage includes the first to fifth frame display stages after the screen is switched.
  • the first display stage may be the entire display stage of the display panel, that is, each frame display in the entire display stage uses the first frame start signal GSTV1 as the start signal of the cascade circuit 12 .
  • the inventor discovered that when the first frame start signal GSTV1 is used as the start signal of the cascade circuit 12 during the entire display process, a "virtual edge" defect will be generated at the edge of the display screen, as shown in FIG6 .
  • the inventor analyzed the defect.
  • the display panel shown in FIG5 multiple pixel driving circuits 51 are arranged along rows and columns. Assuming that the (n+5)th row is the last row of pixel driving circuits 51, the gate driving circuit 10 is driven by the first frame start signal GSTV1 shown in FIG2a during the entire display process. Referring to FIG7 , a driving signal timing diagram for displaying the display panel shown in FIG5 is shown.
  • the data signal line data When the pixel driving circuits 51 of the (n+1)th row and the rows before it write data signals, the data signal line data will simultaneously write signals to the pixel driving circuits 51 of the three rows; and the pixel driving circuits 51 of the (n+2)th row to the (n+5)th row are driven by the first frame start signal GSTV1 shown in FIG2a .
  • the data signal line data When the circuit 51 is writing data signals, the data signal line data will write signals to 2 or 1 row of pixel driving circuits 51 at the same time.
  • the gate drive circuit further includes: a second frame start signal line 15, the second frame start signal line 15 is connected to the second input terminal Input2 of the cascade circuit 12, and the second frame start signal line 15 is configured to: transmit the second frame start signal GSTV2 to the cascade circuit 12 in the second display stage.
  • the cascade circuit 12 is also configured to: output the second scan signal G2 step by step according to the second frame start signal GSTV2 and the clock signal GCK.
  • the number of pulse signals whose effective level of the second frame start signal GSTV2 overlaps with the clock signal GCK in one cycle is less than the number of pulse signals whose effective level of the first frame start signal GSTV1 overlaps with the clock signal GCK in one cycle
  • the number of scan pulse signals included in the second scan signal G2 in one cycle is greater than or equal to 1, and is less than the number of scan pulse signals included in the first scan signal G1 in one cycle.
  • the effective level of the second frame start signal GSTV2 in one cycle overlaps with one pulse signal of the clock signal GCK. That is, the number of pulse signals of the second frame start signal GSTV2 overlapping with the clock signal GCK in one cycle is 1.
  • the input terminal Input of the first stage shift register GOA1 is connected to the second input terminal Input2 of the cascade circuit 12, or is multiplexed as the second input terminal Input2 of the cascade circuit 12 (as shown in FIG. 1).
  • the start signal of the first-stage shift register GOA1 is the second frame start signal GSTV2.
  • the cascade circuit 12 generates the second scan signal G2 step by step under the action of the second frame start signal GSTV2 and the clock signal GCK. It can be understood that the number of pulse signals whose effective level of the second frame start signal GSTV2 overlaps with the clock signal GCK in one cycle is the same as the number of scan pulse signals included in the second scan signal G2 in one cycle.
  • the cascade circuit 12 When the number of pulse signals whose effective level of the second frame start signal GSTV2 overlaps with the clock signal GCK in one cycle is 1, under the triggering of the second frame start signal GSTV2, the cascade circuit 12 outputs the second scan signal G2 having one scan pulse signal in one cycle.
  • the second frame start signal GSTV2 has the same voltage as the active level of the first frame start signal GSTV1.
  • the first display stage may be the first frame display stage after the screen is switched, and the second display stage may be any frame display stage after the switched screen is stably displayed, such as the second frame display stage, the third frame display stage, etc.
  • the display device includes a display driver chip (Display Driver Integrated Circuit, DDIC) and a display panel (Panel).
  • the DDIC is connected to the application processor (Application Processor, AP) through the mobile industry processor interface (Mobile Industry Processor Interface, MIPI).
  • AP Application Processor
  • MIPI Mobile Industry Processor Interface
  • the DDIC can start the judgment mechanism according to the display data sent by the AP end, for example, the display data of two adjacent frames, such as the display data of the previous frame and the display data of the next frame, can be compared. If the display data of the previous frame is different from the display data of the next frame (as shown in FIG.
  • the display data of the previous frame is data a
  • the display data of the next frame is data b)
  • the first frame start signal GSTV1 is used as the start signal of the first-stage shift register GOA1
  • the second frame start signal GSTV2 in the second frame start signal line 15 is automatically Hized (i.e., in a high impedance state).
  • the steps in the second display stage can be executed, and the second frame start signal GSTV2 is used as the start signal of the first-stage shift register GOA1, and at the same time, the first frame start signal GSTV1 in the first frame start signal line 11 will automatically Hiz off (that is, it is in a high-impedance state).
  • first frame start signal line 11 and the second frame start signal line 15 are independently provided, as shown in Fig. 1.
  • first frame start signal line 11 and the second frame start signal line 15 may also share the same signal line, which is not limited in the present disclosure.
  • the display panel includes: a plurality of pixel driving circuits 51 arranged in an array; a plurality of light emitting devices 52, the light emitting devices 52 are connected to the pixel driving circuit 51 located in the same pixel; a plurality of scanning signal lines gate, the scanning signal lines gate are connected to the scanning signal terminals Vgate of the pixel driving circuit 51 located in the same row; a plurality of data signal lines data, The data signal line data is connected to the data signal terminal Vdata of the pixel driving circuit 51 located in the same column; and in the gate driving circuit 10 provided in any embodiment, the output terminals Output of the plurality of shift registers 13 in the cascade circuit 12 are respectively connected to different scanning signal lines gate.
  • the pixel driving circuit 51 is configured to write the data signal of the data signal terminal Vdata into the pixel driving circuit 51 according to the signal of the scanning signal terminal Vgate, so as to drive the light emitting device 52 to emit light.
  • the display panel provided by the present disclosure has the advantages of the above-mentioned gate driving circuit 10, which will not be described in detail here.
  • the plurality of data signal lines data include a first data signal line data1 and a second data signal line data2
  • the display panel further includes: a signal terminal Source, a first data selection circuit Mux1 and a second data selection circuit Mux2, the first data signal line data1 is connected to the signal terminal Source through the first data selection circuit Mux1, and the second data signal line data2 is connected to the signal terminal Source through the second data selection circuit Mux2.
  • the first data selection circuit Mux1 is a switch transistor, which is turned on or off under the action of the control signal Mux1
  • the second data selection circuit Mux2 is a switch transistor, which is turned on or off under the action of the control signal Mux2.
  • the switch transistor in the first data selection circuit Mux1 and the switch transistor in the second data selection circuit Mux2 are both P-type transistors.
  • the first data selection circuit Mux1 can be first controlled to be turned on (such as the low level of Mux1 in FIG7 ), and the second data selection circuit Mux2 can be controlled to be turned off (such as the high level of Mux2 in FIG7 ), so that the data signal input from the signal terminal Source is written into the first data storage capacitor Cdata1 through the first data selection circuit Mux1 and the first data signal line data1, and one plate of the first data storage capacitor Cdata1 is connected to the first data signal line data1, and then the second data selection circuit Mux2 can be controlled to be turned on (such as the low level of Mux2 in FIG7 ), and the first data selection circuit Mux1 can be controlled to be turned off (such as the high level of Mux1 in FIG7 ), so that the data signal input from the signal terminal Source is written into the second data storage capacitor Cdata2 through the second data selection circuit Mux2 and the second data signal line
  • two data signal lines data share the same signal terminal Source.
  • three or more data signal lines data may share the same signal terminal Source.
  • a signal terminal Source which is not limited in the present disclosure.
  • the pixel driving circuit 51 includes: a writing module 81, the writing module 81 is connected to the data signal terminal Vdata, the first node N1 and the scanning signal terminal Vgate, and the writing module 81 is configured to: in the compensation stage, write the data signal to the first node N1 according to the signal of the scanning signal terminal Vgate.
  • the writing module 81 may include a fourth transistor T4 , a control electrode of which is connected to the scan signal terminal Vgate, a first electrode of which is connected to the data signal terminal Vdata, and a second electrode of which is connected to the first node N1 .
  • the pixel driving circuit 51 includes: a driving module 82, the driving module 82 is connected to the first node N1, the second node N2 and the third node N3, and the driving module 82 is configured to: write the signal of the first node N1 to the second node N2 under the potential control of the third node N3.
  • the driving module 82 may include a driving transistor T3 , a control electrode of which is connected to the third node N3 , a first electrode of which is connected to the first node N1 , and a second electrode of which is connected to the second node N2 .
  • the pixel driving circuit 51 includes: a compensation module 83, the compensation module 83 is connected to the second node N2, the third node N3 and the scanning signal terminal Vgate, and the compensation module 83 is configured to: in the compensation stage, write the signal of the second node N2 into the third node N3 according to the signal of the scanning signal terminal Vgate.
  • the compensation module 83 may include a second transistor T2 , a control electrode of which is connected to the scan signal terminal Vgate, a first electrode of which is connected to the second node N2 , and a second electrode of which is connected to the third node N3 .
  • the pixel driving circuit 51 includes: a light-emitting control module 84, the light-emitting control module 84 is connected to the first voltage terminal ELVDD, the enable signal terminal EM, the first node N1, the second node N2 and the light-emitting device 52, and the light-emitting control module 84 is configured to: in the light-emitting stage, cooperate with the driving module 82 according to the enable signal of the enable signal terminal EM to drive the light-emitting device 52 to emit light.
  • the light control module 84 may include a fifth transistor T5 and a sixth transistor T6, the control electrode of the fifth transistor T5 is connected to the enable signal terminal EM, the first electrode of the fifth transistor T5 is connected to the first voltage terminal ELVDD, the second electrode of the fifth transistor T5 is connected to the first node N1, the control electrode of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the sixth transistor T6 is connected to the second node N2, and the second electrode of the sixth transistor T6 is connected to the anode of the light emitting device 52.
  • the pixel driving circuit 51 includes a storage module 85 , the storage module 85 is connected to the first voltage terminal ELVDD and the third node N3 , and the storage module 85 is configured to store a signal of the third node N3 .
  • the storage module 85 includes a first capacitor Cst, a first electrode of which is connected to the first voltage terminal ELVDD, and a second electrode of which is connected to the third node N3 .
  • the pixel driving circuit 51 includes: a first reset module 86, the first reset module 86 is connected to the third node N3, the first reset signal terminal Vint1 and the reset control signal terminal Reset, and the first reset module 86 is configured to: write the signal of the first reset signal terminal Vint1 into the third node N3 according to the signal of the reset control signal terminal Reset.
  • the first reset module 86 includes a first transistor T1 , a control electrode connected to the reset control signal terminal Reset, a first electrode connected to the first reset signal terminal Vint1 , and a second electrode connected to the third node N3 .
  • the pixel driving circuit 51 includes: a second reset module 87, the second reset module 87 is connected to the anode of the light-emitting device 52, the second reset signal terminal Vint2 and the scanning signal terminal Vgate, and the second reset module 87 is configured to: write the signal of the second reset signal terminal Vint2 into the anode of the light-emitting device 52 according to the signal of the scanning signal terminal Vgate.
  • the second reset module 87 includes a seventh transistor T7 , a control electrode connected to the scan signal terminal Vgate, a first electrode connected to the second reset signal terminal Vint2 , and a second electrode connected to the anode of the light emitting device 52 .
  • the first transistor T1 to the seventh transistor T7 are all P-type transistors.
  • the first transistor T1 to the seventh transistor T7 may also be N-type transistors, which is not limited in the present disclosure.
  • the brightness ratio of the first frame to the preset frame is the first frame brightness ratio FFR, the first frame brightness ratio is greater than or equal to 85%, and the preset frame is any frame after the same screen is stably displayed.
  • the present disclosure provides a display device, as shown in FIG9 , comprising: a display panel Panel as provided in any embodiment; and a display driver chip DDIC.
  • the display driver chip DDIC is connected to the display panel Panel and is used to provide a driving signal to the display panel Panel.
  • the driving signal includes: First frame start signal, clock signal and data signal.
  • the display device provided by the present disclosure has the advantages of the above-mentioned gate driving circuit 10, which will not be described in detail here.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame or a navigator.
  • the DDIC is connected to the application processor AP via the mobile industry processor interface MIPI.
  • the driving signal may further include a second frame start signal and the like.
  • the present disclosure provides a display driving method, which is applied to a display panel provided in any embodiment (as shown in FIG5 ), and the display driving method includes:
  • Step S01 providing a clock signal GCK to the clock signal line 14 , so that the clock signal line 14 transmits the clock signal GCK to the shift register 13 .
  • Step S02 In the first display stage, a first frame start signal GSTV1 is provided to the first frame start signal line 11, so that the first frame start signal line 11 transmits the first frame start signal GSTV1 to the cascade circuit 12, and the cascade circuit 12 outputs the first scanning signal G1 step by step according to the first frame start signal GSTV1 and the clock signal GCK.
  • the display driving method provided by the present disclosure can be executed by a display driving chip DDIC in a display device.
  • the gate driving circuit further includes a second frame start signal line 15 , and the second frame start signal line 15 is connected to the second input terminal Input2 of the cascade circuit 12 , after step S01 , the following further includes:
  • Step S11 In the second display stage, a second frame start signal GSTV2 is provided to the second frame start signal line 15, so that the second frame start signal line 15 transmits the second frame start signal GSTV2 to the cascade circuit 12, and the cascade circuit 12 outputs the second scanning signal G2 step by step according to the second frame start signal GSTV2 and the clock signal GCK.
  • the method before step S02 and step S11, the method further includes:
  • Step S21 acquiring display data, the display data including a previous frame of display data and a next frame of display data, the previous frame of display data and the next frame of display data being display data of two adjacent frames.
  • Step S22 Compare the previous frame display data with the next frame display data, and according to the comparison result, The steps in the first display stage or the steps in the second display stage are performed.
  • step S22 according to the comparison result, the steps in the first display stage or the steps in the second display stage are performed, including:
  • Step S31 If the previous frame display data is different from the next frame display data, then the steps in the first display stage are executed.
  • Step S32 If the previous frame display data is the same as the next frame display data, then execute the steps in the second display stage.
  • the first scan signal G1 includes a plurality of scan pulse signals
  • the plurality of scan signal lines gate include a first scan signal G1 line
  • the plurality of data signal lines data include a first data signal line data1
  • the pixel driving circuit 51 connected to the first scan signal G1 line and the first data signal line data1 is the first pixel driving circuit 51.
  • Step S41 multiple compensation stages separated from each other, each compensation stage includes: inputting a scan pulse signal to the scan signal terminal Vgate of the first pixel driving circuit 51, and providing a data signal to the data signal terminal Vdata of the first pixel driving circuit 51, so that the data signal is written into the first pixel driving circuit 51.
  • the gate of the driving transistor T3 can be biased once with a voltage, and the threshold voltage of the driving transistor T3 can be compensated multiple times in multiple compensation stages, so that the threshold voltage of the driving transistor T3 shifts toward a negative direction.
  • the second scanning signal G2 includes a scanning pulse signal
  • multiple scanning signal lines gate include a first scanning signal G1 line
  • multiple data signal lines data include a first data signal line data1
  • the pixel driving circuit 51 connected to the first scanning signal G1 line and the first data signal line data1 is the first pixel driving circuit 51.
  • step S11 it also includes: a compensation stage, inputting a scanning pulse signal to the scanning signal terminal Vgate of the first pixel driving circuit 51, and providing a data signal to the data signal terminal Vdata of the first pixel driving circuit 51, so that the data signal is written into the first pixel driving circuit 51.
  • the plurality of data signal lines data further include a second data signal line data2
  • the display panel further includes a signal terminal Source, a first data selection circuit Mux1, and a second data selection circuit Mux2
  • the first data signal line data1 is connected to the signal terminal Source through the first data selection circuit Mux1
  • the second data signal line data2 is connected to the signal terminal Source through the second data selection circuit Mux2.
  • step S41 before each compensation stage, it further includes:
  • Step S51 providing a data signal to the signal terminal Source, controlling the first data selection circuit Mux1 to open, and controlling the second data selection circuit Mux2 to close, so that the data signal is written into the first data storage capacitor Cdata1, and one plate of the first data storage capacitor Cdata1 is connected to the first data signal line data1.
  • step S41 before each compensation stage, it can also include: providing a data signal to the signal terminal Source, controlling the second data selection circuit Mux2 to open, and controlling the first data selection circuit Mux1 to close, so that the data signal is written into the second data storage capacitor Cdata2, and one electrode of the second data storage capacitor Cdata2 is connected to the second data signal line data2.
  • the first pixel driving circuit 51 includes a writing module 81, a driving module 82, a compensation module 83, a light emitting control module 84 and a first reset module 86
  • the writing module 81 is connected to the data signal terminal Vdata
  • the driving module 82 is connected to the first node N1, the second node N2 and the third node N3
  • the compensation module 83 is connected to the second node N2, the third node N3 and the scanning signal terminal Vgate
  • the light emitting control module 84 is connected to the first voltage terminal ELVDD
  • the enable signal terminal EM the first node N1, the second node N2 and the light emitting device 52
  • the first reset module 86 is connected to the third node N3, the first reset signal terminal Vint1 and the reset control signal terminal Reset
  • the compensation stage t2 is used to write the data signal into the first node N1, the second node N2 and the third node
  • Step S61 Reset stage t1, providing a first reset signal to the first reset signal terminal Vint1, and providing a reset control signal (such as Reset in FIG. 10 and FIG. 11 ) to the reset control signal terminal Reset, so that the first reset signal is written into the third node N3.
  • a reset control signal such as Reset in FIG. 10 and FIG. 11
  • step S41 after the multiple compensation stages t2 in step S41, or as shown in FIG. 11 , after the single compensation stage t2, the following may also be included:
  • Step S71 light-emitting stage t3, providing an enable signal (such as EM in FIG. 10 and FIG. 11 ) to the enable signal terminal EM, so that the light-emitting control module 84 cooperates with the driving module 82 to drive the light-emitting device 52 to emit light.
  • an enable signal such as EM in FIG. 10 and FIG. 11
  • the display driving method may also include more steps, which may be determined according to actual needs, and the present disclosure does not limit this.
  • the detailed description and technical effects of the display driving method can refer to the above description of the gate driving circuit and the display panel, which will not be repeated here.
  • plurality means two or more, and “at least one” means one or more, unless otherwise clearly and specifically defined.
  • orientation or positional relationship indicated by the terms “upper” and “lower” are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.
  • the terms "comprises,” “comprising,” or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, product, or device.
  • an element defined by the phrase “comprising a " does not exclude the presence of additional identical elements in the process, method, commodity, or device that includes the element.
  • references herein to "one embodiment,” “some embodiments,” “exemplary embodiments,” “one or more embodiments,” “example,” “an example,” “some examples,” etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
  • the expressions “coupled” and “connected” may be used.
  • the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C", and both include the following combinations of A, B and C: only A, only B, only C, the combination of A and B, A and C The combination of A, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • a process, step, calculation or other action based on one or more of the conditions or values may, in practice, be based on other conditions or exceed the values described.
  • a process, step, calculation or other action based on one or more of the conditions or values may, in practice, be based on other conditions or exceed the values described.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity may also be, for example, a deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, wherein the acceptable deviation range for approximate equality may be, for example, that the difference between the two being equal is less than or equal to 5% of either one.
  • “Flush” includes absolute flushness and approximate flushness, wherein the acceptable deviation range for approximate flushness may be, for example, that the distance between the two being flush is less than or equal to 5% of the size of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

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Abstract

公开了一种栅极驱动电路、显示面板、显示装置以及显示驱动方法。栅极驱动电路包括：第一帧起始信号线（11）和级联电路（12）；第一帧起始信号线（11），与级联电路（12）的第一输入端（Input1）连接，被配置为：在第一显示阶段，向级联电路（12）传输第一帧起始信号（GSTV1）；级联电路（12），包括相互级联的多个移位寄存器（13），各移位寄存器（13）与时钟信号线（14）连接，移位寄存器（13）的输出端（Output）与像素驱动电路（51）中的写入模块（81）连接，级联电路（12）被配置为：根据第一帧起始信号（GSTV1）以及时钟信号线（14）输入的时钟信号（GCK），逐级输出第一扫描信号（G1）；第一帧起始信号（GSTV1）在一个周期内的有效电平与时钟信号（GCK）的多个脉冲信号交叠，第一扫描信号（G1）在一个周期内包括多个扫描脉冲信号。

Description

栅极驱动电路、显示面板、显示装置以及显示驱动方法
相关申请的交叉引用
本公开要求在2023年1月30日提交中国专利局、申请号为202310103731.8、名称为“栅极驱动电路、显示面板、显示装置以及显示驱动方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别是涉及一种栅极驱动电路、显示面板、显示装置以及显示驱动方法。
背景技术
目前搭载有机发光二极管(Organic Light-Emitting Diode,OLED)屏幕的显示装置中，由于驱动电路和器件结构的影响，显示装置在切换显示画面时，普遍存在第一帧的亮度较低的问题，严重影响了用户体验。
概述
本公开提供了一种栅极驱动电路，包括：第一帧起始信号线和级联电路；
所述第一帧起始信号线，与所述级联电路的第一输入端连接，被配置为：在第一显示阶段，向所述级联电路传输第一帧起始信号；
所述级联电路，包括相互级联的多个移位寄存器，各所述移位寄存器与时钟信号线连接，所述移位寄存器的输出端与像素驱动电路中的写入模块连接，所述级联电路被配置为：根据所述第一帧起始信号以及所述时钟信号线输入的时钟信号，逐级输出第一扫描信号；
其中，所述第一帧起始信号在一个周期内的有效电平与所述时钟信号的多个脉冲信号交叠，所述第一扫描信号在一个周期内包括多个扫描脉冲信号，所述写入模块用于在所述第一扫描信号的控制下，将数据信号写入所述像素驱动电路。
在一些实施方式中，所述栅极驱动电路还包括：
第二帧起始信号线，与所述级联电路的第二输入端连接，被配置为：在第二显示阶段，向所述级联电路传输第二帧起始信号；
所述级联电路还被配置为：根据所述第二帧起始信号以及所述时钟信号，逐级输出第二扫描信号；
其中，所述第二帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量，小于所述第一帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量，所述第二扫描信号在一个周期内包括的扫描脉冲信号数量大于或等于1，且小于所述第一扫描信号在一个周期内包括的扫描脉冲信号数量。
在一些实施方式中，所述第一帧起始信号线与所述第二帧起始信号线各自独立设置，或者共用同一条信号线。
在一些实施方式中，所述第一帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量大于或等于2，且小于或等于5。
在一些实施方式中，所述第二帧起始信号在一个周期内的有效电平与所述时钟信号的一个脉冲信号交叠。
在一些实施方式中，所述第一帧起始信号的有效电平为低电平。
在一些实施方式中，所述第二帧起始信号与所述第一帧起始信号的有效电平的电压相同。
在一些实施方式中，所述级联电路中，第一级移位寄存器的信号输入端连接所述第一输入端以及所述第二输入端，第E级移位寄存器的输出端与第E+F级移位寄存器的信号输入端连接，第M级移位寄存器的输出端与第M-N级移位寄存器的复位信号输入端连接，其中，1≤E＜H，F≥1，E+F≤H，1＜M≤H，1≤N＜M，且E、F、H、M和N均为正整数，所述H为所述级联电路中的移位寄存器总数量。
本公开提供了一种显示面板，包括：
阵列排布的多个像素驱动电路；
多个发光器件，所述发光器件与位于同一像素的像素驱动电路连接；
多条扫描信号线，所述扫描信号线与位于同一行的像素驱动电路的扫描信号端连接；
多条数据信号线，所述数据信号线与位于同一列的像素驱动电路的数据 信号端连接；以及
如任一实施方式所述的栅极驱动电路，所述级联电路中的多个移位寄存器的输出端分别连接不同的扫描信号线；
其中，所述像素驱动电路被配置为：根据所述扫描信号端的信号，将所述数据信号端的数据信号写入所述像素驱动电路中，以驱动所述发光器件发光。
在一些实施方式中，所述多条数据信号线包括第一数据信号线和第二数据信号线，所述显示面板还包括：信号端子、第一数据选择电路和第二数据选择电路，所述第一数据信号线与所述信号端子通过所述第一数据选择电路连接，所述第二数据信号线与所述信号端子通过所述第二数据选择电路连接。
在一些实施方式中，所述像素驱动电路包括：
写入模块，与所述数据信号端、第一节点以及所述扫描信号端连接，被配置为：在补偿阶段，响应于所述扫描信号端的信号，将所述数据信号写入所述第一节点；
驱动模块，与所述第一节点、第二节点以及第三节点连接，被配置为：在所述第三节点的电位控制下，将所述第一节点的信号写入所述第二节点；
补偿模块，与所述第二节点、所述第三节点以及所述扫描信号端连接，被配置为：在补偿阶段，根据所述扫描信号端的信号，将所述第二节点的信号写入所述第三节点；
发光控制模块，与第一电压端、使能信号端、所述第一节点、所述第二节点以及所述发光器件连接，被配置为：在发光阶段，根据所述使能信号端的使能信号，与所述驱动模块配合，驱动所述发光器件发光；
存储模块，与所述第一电压端以及所述第三节点连接，被配置为存储所述第三节点的信号；
第一复位模块，与所述第三节点、第一复位信号端以及复位控制信号端连接，被配置为：根据所述复位控制信号端的信号，将所述第一复位信号端的信号写入所述第三节点；以及
第二复位模块，与所述发光器件的阳极、第二复位信号端和所述扫描信号端连接，被配置为：根据所述扫描信号端的信号，将所述第二复位信号端的信号写入所述发光器件的阳极。
在一些实施方式中，在所述显示装置显示同一画面的连续多帧画面中，第一帧画面与预设帧画面的亮度之比为首帧亮度占比，所述首帧亮度占比大于或等于85％，所述预设帧画面为稳定显示所述同一画面后的任一帧画面。
本公开提供了一种显示装置，包括：
如任一实施方式所述的显示面板；以及
显示驱动芯片，与所述显示面板连接，用于向所述显示面板提供驱动信号，所述驱动信号包括：所述第一帧起始信号、所述时钟信号以及所述数据信号。
本公开提供了一种显示驱动方法，应用于如任一实施方式所述的显示面板，所述显示驱动方法包括：
向所述时钟信号线提供时钟信号，以使所述时钟信号线向所述移位寄存器传输所述时钟信号；
在第一显示阶段，向所述第一帧起始信号线提供第一帧起始信号，以使所述第一帧起始信号线向所述级联电路传输所述第一帧起始信号，所述级联电路根据所述第一帧起始信号以及所述时钟信号，逐级输出第一扫描信号。
在一些实施方式中，当所述栅极驱动电路还包括第二帧起始信号线，所述第二帧起始信号线与所述级联电路的第二输入端连接时，在所述向所述时钟信号线提供时钟信号的步骤之后，还包括：
在第二显示阶段，向所述第二帧起始信号线提供第二帧起始信号，以使所述第二帧起始信号线向所述级联电路传输所述第二帧起始信号，所述级联电路根据所述第二帧起始信号以及所述时钟信号，逐级输出第二扫描信号。
在一些实施方式中，在所述向所述第一帧起始信号线提供第一帧起始信号，以及所述向所述第二帧起始信号线提供第二帧起始信号的步骤之前，还包括：
获取显示数据，所述显示数据包括前一帧显示数据和后一帧显示数据，所述前一帧显示数据与所述后一帧显示数据为相邻两帧画面的显示数据；
将所述前一帧显示数据与所述后一帧显示数据进行比较，根据比较结果，执行在所述第一显示阶段的步骤或者在所述第二显示阶段的步骤。
在一些实施方式中，所述根据比较结果，执行在所述第一显示阶段的步骤或者在所述第二显示阶段的步骤，包括：
若所述前一帧显示数据与所述后一帧显示数据不同，则执行在所述第一显示阶段的步骤；
若所述前一帧显示数据与所述后一帧显示数据相同，则执行在所述第二显示阶段的步骤。
在一些实施方式中，所述第一扫描信号包括多个扫描脉冲信号，所述多条扫描信号线包括第一扫描信号线，所述多条数据信号线包括第一数据信号线，与所述第一扫描信号线以及所述第一数据信号线连接的像素驱动电路为第一像素驱动电路，在所述向所述第一帧起始信号线提供第一帧起始信号，以使所述第一帧起始信号线向所述级联电路传输所述第一帧起始信号，所述级联电路根据所述第一帧起始信号以及所述时钟信号，逐级输出第一扫描信号的步骤之后，还包括：
相互分隔开的多个补偿阶段，各所述补偿阶段包括：向所述第一像素驱动电路的扫描信号端输入所述扫描脉冲信号，向所述第一像素驱动电路的数据信号端提供数据信号，以使所述数据信号写入所述第一像素驱动电路。
在一些实施方式中，所述多条数据信号线还包括第二数据信号线，所述显示面板还包括信号端子、第一数据选择电路和第二数据选择电路，且所述第一数据信号线与所述信号端子通过所述第一数据选择电路连接，所述第二数据信号线与所述信号端子通过所述第二数据选择电路连接，在各所述补偿阶段之前，还包括：
向所述信号端子提供所述数据信号，控制所述第一数据选择电路打开，控制所述第二数据选择电路关闭，以使所述数据信号写入第一数据存储电容中，所述第一数据存储电容的一个极板与所述第一数据信号线连接。
在一些实施方式中，当所述第一像素驱动电路包括写入模块、驱动模块、补偿模块、发光控制模块以及第一复位模块，且所述写入模块与所述数据信号端、第一节点以及所述扫描信号端连接，所述驱动模块与所述第一节点、第二节点以及第三节点连接，所述补偿模块与所述第二节点、所述第三节点以及所述扫描信号端连接，所述发光控制模块与第一电压端、使能信号端、所述第一节点、所述第二节点以及所述发光器件连接，所述第一复位模块与所述第三节点、第一复位信号端和复位控制信号端连接时，所述补偿阶段用于将所述数据信号依次写入所述第一节点、所述第二节点和所述第三节点， 在各所述补偿阶段之前，还包括：
复位阶段，向所述第一复位信号端提供第一复位信号，向复位控制信号端提供复位控制信号，以使所述第一复位信号写入所述第三节点；
在所述多个补偿阶段之后，还包括：
发光阶段，向所述使能信号端提供使能信号，以使所述发光控制模块与所述驱动模块配合，驱动所述发光器件发光。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。需要说明的是，附图中的比例仅作为示意并不代表实际比例。
图1示出了本公开提供的一种栅极驱动电路的结构示意图；
图2a示出了一种栅极驱动电路的驱动信号时序图；
图2b示出了一种移位寄存器的电路结构示意图；
图3示出了第一种显示面板的亮度-时间曲线；
图4示出了第二种显示面板的亮度-时间曲线；
图5示出了本公开提供的一种显示面板的结构示意图；
图6示出了一种显示面板的“虚边”不良；
图7示出了一种显示面板的驱动信号时序图；
图8示出了本公开提供的一种像素驱动电路的结构示意图；
图9示出了本公开提供的一种显示装置的结构示意图；
图10示出了一种像素驱动电路的第一种驱动信号时序图；
图11示出了一种像素驱动电路的第二种驱动信号时序图。
详细描述
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
在实际使用过程中，OLED显示屏常常处于循环播放视频的状态，由于驱动电路和器件结构的影响，显示屏在切换显示画面时，第一帧的亮度通常只有所需亮度的60％。对于较为敏感的人眼来说，看到的现象即为切换画面后的第一帧会出现拖影。通常采用首帧响应或首帧亮度占比(First Frame Ratio，FFR)来表征这一现象，FFR值越高拖影越不明显。
本公开提供了一种栅极驱动电路，如图1和图2a所示，该栅极驱动电路包括：第一帧起始信号线11和级联电路12。第一帧起始信号线11与级联电路12的第一输入端Input1连接，第一帧起始信号线11被配置为：在第一显示阶段，向级联电路12传输第一帧起始信号GSTV1。级联电路12包括相互级联的多个移位寄存器13，各移位寄存器13与时钟信号线14连接，级联电路12被配置为：根据第一帧起始信号GSTV1以及时钟信号线14输入的时钟信号GCK，逐级输出第一扫描信号G1。
如图2a所示，第一帧起始信号GSTV1在一个周期内的有效电平与时钟信号GCK的多个脉冲信号交叠，第一扫描信号G1在一个周期内包括多个扫描脉冲信号。
本公开中，“一个周期”指的是一个帧周期(如图2a所示的1Frame)，也就是显示面板进行多帧显示时，每一帧的显示周期，为该显示面板刷新频率的倒数。
参照图5和图8，移位寄存器13的输出端Output与像素驱动电路51中的写入模块81可以通过扫描信号线gate连接，扫描信号线gate连接写入模块81的扫描信号端Vgate，写入模块81用于在第一扫描信号G1的控制下，将数据信号写入像素驱动电路51。
示例性地，在图2a中，第一帧起始信号GSTV1在一个周期内的有效电平与时钟信号GCK的三个脉冲信号交叠。
在一些实施方式中，第一帧起始信号GSTV1在一个周期内的有效电平与 时钟信号GCK交叠的脉冲信号数量大于或等于2，且小于或等于5。如图2a所示，第一帧起始信号GSTV1在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量为3。
在一些实施方式中，如图2a所示，第一帧起始信号GSTV1的有效电平为低电平。
示例性地，在级联电路12中，第一级移位寄存器GOA1的输入端Input连接级联电路12的第一输入端Input1，或者复用为级联电路12的第一输入端Input1(如图1所示出的)。
在一些实施方式中，级联电路12中，第E级移位寄存器13的输出端Output与第E+F级移位寄存器13的输入端Input连接，第M级移位寄存器13的输出端Output与第M-N级移位寄存器13的复位端Rst连接，其中，1≤E＜H，F≥1，E+F≤H，1＜M≤H，1≤N＜M，且E、F、H、M和N均为正整数，H为级联电路12中的移位寄存器13总数量。
示例性地，如图1所示，F＝N＝1。在图1中，对于每一级移位寄存器13，其输出的第一扫描信号G1可以输出至扫描信号线gate，还可以作为下一级移位寄存器13的起始信号以及上一级移位寄存器13的复位信号。在第一显示阶段，第一级移位寄存器GOA1的起始信号为第一帧起始信号GSTV1，第一级移位寄存器GOA1可以不输出复位信号，最后一级移位寄存器13可以连接一行冗余移位寄存器13实现最后一级移位寄存器13的复位。
示例性地，如图2b所示，移位寄存器13可以包括充电模块21、输出模块22、存储电容C和复位模块23。其中，充电模块21分别与移位寄存器13的输入端Input以及上拉节点PU连接，用于根据输入端Input的信号，将输入端Input的信号写入上拉节点PU；输出模块22分别与时钟信号输入端GCK、上拉节点PU以及输出端Output连接，用于根据上拉节点PU的电位，将时钟信号输入端GCK的时钟信号写入输出端Output；存储电容C连接上拉节点PU与输出端Output之间，用于存储上拉节点PU的电压；复位模块23分别与复位端Rst、复位信号端VSS、上拉节点PU以及输出端Output连接，用于根据复位端Rst的信号，将复位信号端VSS的信号写入上拉节点PU和输出端Output。
如图2b所示，充电模块21包括晶体管M1，晶体管M1的控制极和第一 极连接移位寄存器13的输入端Input，晶体管M1的第二极连接上拉节点PU。输出模块22包括晶体管M3，晶体管M3的控制极连接上拉节点PU，晶体管M3的第一极连接时钟信号输入端GCK，晶体管M3的第二极连接移位寄存器13的输出端Output。复位模块23包括晶体管M2和晶体管M4，晶体管M2的控制极连接下拉节点PD，晶体管M2的第一极连接复位信号端VSS，晶体管M2的第二极连接上拉节点PU，晶体管M4的控制极连接下拉节点PD，晶体管M4的第一极连接复位信号端VSS，晶体管M4的第二极连接输出端Output。在图2b中，晶体管M1至M4均为P型晶体管。
如图2a所示，在第一显示阶段，第一帧起始信号线11向第一级移位寄存器GOA1的输入端提供第一帧起始信号GSTV1。如图2b所示，当第一级移位寄存器GOA1的输入端Input接入低电平的第一帧起始信号GSTV1时，晶体管M1开启，上拉节点PU点电位为低电平，晶体管M 3也处于开启状态，从而将时钟信号输入端GCK的信号写入输出端Output，进而输出第一扫描信号。如图2a所示，由于第一帧起始信号GSTV1在一个周期内的有效电平阶段(如图2a所示的低电平阶段)与时钟信号GCK的三个脉冲信号交叠，因此，输出端Output输出的第一扫描信号在一个周期内包括三个扫描脉冲信号。
这样，级联电路12在第一帧起始信号GSTV1和时钟信号GCK的作用下，逐级产生多脉冲的第一扫描信号G1。在级联电路12中，第一级移位寄存器GOA1之后各级移位寄存器13的工作过程与第一级移位寄存器GOA1类似，这里不再赘述。可以理解，第一帧起始信号GSTV1在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量，与第一扫描信号G1在一个周期内包括的扫描脉冲信号数量相同。
当本公开提供的栅极驱动电路10应用于显示面板时，参照图5，该显示面板可以包括：像素驱动电路51、发光器件52(如图8所示)、扫描信号线gate以及数据信号线data，一个移位寄存器13的输出端Output与一条扫描信号线gate连接，输出端Output输出的信号通过扫描信号线gate传输至像素驱动电路51，进而像素驱动电路51根据扫描信号线gate的信号，将数据信号线data输入的数据信号写入像素驱动电路51中(如图8所示出的驱动晶体管T3的栅极，即第三节点N3)，以驱动发光器件52发光。
由于第一扫描信号G1在一个周期内具有多个扫描脉冲信号，当本公开提供的栅极驱动电路10应用于显示面板时，像素驱动电路51在第一扫描信号G1的控制下，能够在发光器件52发光之前对驱动晶体管T3的栅极进行多次电压偏置，从而对驱动晶体管T3的阈值电压进行多次补偿，使得驱动晶体管T3的阈值电压向负向偏移，这样就减小了补偿阶段和发光阶段阈值电压的差值，因此可以提升显示画面亮度。
发明人测试了两种显示面板连续多帧显示同一画面的亮度随时间的变化，第一种显示面板采用本公开提供的栅极驱动电路，测试结果如图3所示，第二种显示面板采用相关技术中的栅极驱动电路(输出的扫描信号在一个周期内包括一个扫描脉冲信号)，测试结果如图4所示。在显示面板显示同一画面的连续多帧画面中，第一帧画面与预设帧画面的亮度之比为FFR值，预设帧画面可以为稳定显示上述同一画面后的任一帧画面，这里将第四帧画面作为预设帧画面。对比图3和图4可以发现，第一种显示面板的第一帧起始亮度和结束亮度都有很大的提高，两种显示面板的第四帧亮度基本没有差别。因此，采用本公开提供的栅极驱动电路10，可以显著提升显示面板的FFR值，改善切换画面后第一帧显示的拖影问题。
需要说明的是，第一显示阶段可以包括切换画面后的第一帧显示阶段，还可以包括切换画面稳定显示后的任一帧显示阶段，如图3所示，第一显示阶段包括切换画面后的第一帧至第五帧显示阶段。
在一些实施方式中，第一显示阶段可以为显示面板的整个显示阶段，也就是，整个显示阶段的每一帧显示都是采用第一帧起始信号GSTV1作为级联电路12的起始信号。
发明人发现，在整个显示过程中都采用第一帧起始信号GSTV1作为级联电路12的起始信号时，会在显示画面的边缘产生“虚边”不良，如图6所示。发明人对该不良进行了分析，在图5所示的显示面板中，多个像素驱动电路51沿行列排布，假设第(n+5)行是最后一行像素驱动电路51，整个显示过程中栅极驱动电路10都采用图2a所示的第一帧起始信号GSTV1驱动，参照图7示出了图5所示显示面板进行显示的驱动信号时序图，第(n+1)行及其前面行的像素驱动电路51在进行数据信号写入时，数据信号线data会同时对3行像素驱动电路51进行信号写入；而第(n+2)行至(n+5)行的像素驱动 电路51在进行数据信号写入时，数据信号线data会同时对2行或1行像素驱动电路51进行信号写入，这就导致靠近边缘的第(n+2)行至第(n+5)行像素驱动电路51中第三节点N3(即驱动晶体管T3的栅极)的电压较大，在亮画面时会出现发暗现象，进而出现图6中边框附近发暗的“虚边”现象。
为了避免这种显示的异常现象，在一些实施方式中，如图1所示，栅极驱动电路还包括：第二帧起始信号线15，第二帧起始信号线15与级联电路12的第二输入端Input2连接，第二帧起始信号线15被配置为：在第二显示阶段，向级联电路12传输第二帧起始信号GSTV2。相应地，级联电路12还被配置为：根据第二帧起始信号GSTV2以及时钟信号GCK，逐级输出第二扫描信号G2。其中，第二帧起始信号GSTV2在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量，小于第一帧起始信号GSTV1在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量，第二扫描信号G2在一个周期内包括的扫描脉冲信号数量大于或等于1，且小于第一扫描信号G1在一个周期内包括的扫描脉冲信号数量。
示例性地，在图2a中，第二帧起始信号GSTV2在一个周期内的有效电平与时钟信号GCK的一个脉冲信号交叠。也就是，第二帧起始信号GSTV2在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量为1。
示例性地，在级联电路12中，第一级移位寄存器GOA1的输入端Input连接级联电路12的第二输入端Input2，或者复用为级联电路12的第二输入端Input2(如图1所示出的)。
在第二显示阶段，第一级移位寄存器GOA1的起始信号为第二帧起始信号GSTV2。这样，在第二显示阶段，级联电路12在第二帧起始信号GSTV2和时钟信号GCK的作用下，逐级产生第二扫描信号G2。可以理解，第二帧起始信号GSTV2在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量，与第二扫描信号G2在一个周期内包括的扫描脉冲信号数量相同。当第二帧起始信号GSTV2在一个周期内的有效电平与时钟信号GCK交叠的脉冲信号数量为1时，在第二帧起始信号GSTV2的触发下，级联电路12输出在一个周期内具有一个扫描脉冲信号的第二扫描信号G2。
在一些实施方式中，第二帧起始信号GSTV2与第一帧起始信号GSTV1的有效电平的电压相同。
在一些实施方式中，第一显示阶段可以为切换画面后的第一帧显示阶段，第二显示阶段可以为切换画面稳定显示后的任一帧显示阶段，如第二帧显示阶段、第三帧显示阶段等。
参照图9示出了一种显示装置的结构示意图，如图9所示，该显示装置包括显示驱动芯片(Display Driver Integrated Circuit，DDIC)和显示面板(Panel)，DDIC与应用处理器(Application Processor，AP)通过移动产业处理器接口(Mobile Industry Processor Interface，MIPI)连接。当其中的显示面板采用图5所示的显示面板时，DDIC可以根据AP端送来的显示数据启动判断机制，例如可以对相邻两帧画面的显示数据，如前一帧显示数据与后一帧显示数据进行比较，如果前一帧显示数据与后一帧显示数据不同(如图2a所示，前一帧显示数据为data a，后一帧显示数据为data b)，即后一帧显示数据有更新，对应切换画面的第一帧显示，这种情况下执行在第一显示阶段的步骤，第一帧起始信号GSTV1作为第一级移位寄存器GOA1的起始信号，同时第二帧起始信号线15中的第二帧起始信号GSTV2会自动Hiz掉(即处于高阻状态)。如果前一帧显示数据与后一帧显示数据相同，即后一帧显示数据未更新，与前一帧显示数据显示相同的画面，这种情况下可以执行在第二显示阶段的步骤，第二帧起始信号GSTV2作为第一级移位寄存器GOA1的起始信号，同时第一帧起始信号线11中的第一帧起始信号GSTV1会自动Hiz掉(即处于高阻状态)。
这样，通过分阶段对级联电路12进行不同的驱动，可以解决“虚边”不良，同时也可以提升切换画面第一帧的显示亮度，提升FFR值，解决拖影不良。
在一些实施方式中，第一帧起始信号线11与第二帧起始信号线15各自独立设置，如图1所示出的。当然，第一帧起始信号线11与第二帧起始信号线15还可以共用同一条信号线，本公开对此不作限定。
本公开提供了一种显示面板，如图5和图8所示，该显示面板包括：阵列排布的多个像素驱动电路51；多个发光器件52，发光器件52与位于同一像素的像素驱动电路51连接；多条扫描信号线gate，扫描信号线gate与位于同一行的像素驱动电路51的扫描信号端Vgate连接；多条数据信号线data， 数据信号线data与位于同一列的像素驱动电路51的数据信号端Vdata连接；以及如任一实施方式提供的栅极驱动电路10，级联电路12中的多个移位寄存器13的输出端Output分别连接不同的扫描信号线gate。
其中，像素驱动电路51被配置为：根据扫描信号端Vgate的信号，将数据信号端Vdata的数据信号写入像素驱动电路51中，以驱动发光器件52发光。
可以理解，本公开提供的显示面板具有上述栅极驱动电路10的优点，这里不再赘述。
在一些实施方式中，如图5所示，多条数据信号线data包括第一数据信号线data1和第二数据信号线data2，显示面板还包括：信号端子Source、第一数据选择电路Mux1和第二数据选择电路Mux2，第一数据信号线data1与信号端子Source通过第一数据选择电路Mux1连接，第二数据信号线data2与信号端子Source通过第二数据选择电路Mux2连接。
示例性地，如图5所示，第一数据选择电路Mux1为一个开关晶体管，该开关晶体管在控制信号Mux1的作用下打开或关闭，第二数据选择电路Mux2为一个开关晶体管，该开关晶体管在控制信号Mux2的作用下打开或关闭。示例性地，在图5中，第一数据选择电路Mux1中的开关晶体管以及第二数据选择电路Mux2中的开关晶体管均为P型晶体管。
在具体实施时，如图7所示，可以在第一扫描信号G1和第二扫描信号G2中的各扫描脉冲信号之前，首先控制第一数据选择电路Mux1打开(如图7中Mux1的低电平)，控制第二数据选择电路Mux2关闭(如图7中Mux2的高电平)，以使信号端子Source输入的数据信号通过第一数据选择电路Mux1以及第一数据信号线data1写入第一数据存储电容Cdata1中，第一数据存储电容Cdata1的一个极板与第一数据信号线data1连接，然后控制第二数据选择电路Mux2打开(如图7中Mux2的低电平)，控制第一数据选择电路Mux1关闭(如图7中Mux1的高电平)，以使信号端子Source输入的数据信号通过第二数据选择电路Mux2以及第二数据信号线data2写入第二数据存储电容Cdata2中，第二数据存储电容Cdata2的一个极板与第二数据信号线data2连接。
需要说明的是，在图5中示出的是两条数据信号线data共用同一个信号端子Source，在具体实施时，还可以三条或更多条数据信号线data共用同一 个信号端子Source，本公开对此不作限定。
在一些实施方式中，如图8所示，像素驱动电路51包括：写入模块81，写入模块81与数据信号端Vdata、第一节点N1以及扫描信号端Vgate连接，写入模块81被配置为：在补偿阶段，根据扫描信号端Vgate的信号，将数据信号写入第一节点N1。
示例性地，如图8所示，写入模块81可以包括第四晶体管T4，控制极与扫描信号端Vgate连接，第一极与数据信号端Vdata连接，第二极与第一节点N1连接。
在一些实施方式中，像素驱动电路51包括：驱动模块82，驱动模块82与第一节点N1、第二节点N2以及第三节点N3连接，驱动模块82被配置为：在第三节点N3的电位控制下，将第一节点N1的信号写入第二节点N2。
示例性地，如图8所示，驱动模块82可以包括驱动晶体管T3，控制极与第三节点N3连接，第一极与第一节点N1连接，第二极与第二节点N2连接。
在一些实施方式中，像素驱动电路51包括：补偿模块83，补偿模块83与第二节点N2、第三节点N3以及扫描信号端Vgate连接，补偿模块83被配置为：在补偿阶段，根据扫描信号端Vgate的信号，将第二节点N2的信号写入第三节点N3。
示例性地，如图8所示，补偿模块83可以包括第二晶体管T2，控制极与扫描信号端Vgate连接，第一极与第二节点N2连接，第二极与第三节点N3连接。
在一些实施方式中，像素驱动电路51包括：发光控制模块84，发光控制模块84与第一电压端ELVDD、使能信号端EM、第一节点N1、第二节点N2以及发光器件52连接，发光控制模块84被配置为：在发光阶段，根据使能信号端EM的使能信号，与驱动模块82配合，驱动发光器件52发光。
示例性地，如图8所示，发光控制模块84可以包括第五晶体管T5和第六晶体管T6，第五晶体管T5的控制极与使能信号端EM连接，第五晶体管T5的第一极与第一电压端ELVDD连接，第五晶体管T5的第二极与第一节点N1连接，第六晶体管T6的控制极与使能信号端EM连接，第六晶体管T6的第一极与第二节点N2连接，第六晶体管T6的第二极与发光器件52的阳极连接。
在一些实施方式中，像素驱动电路51包括：存储模块85，存储模块85与第一电压端ELVDD以及第三节点N3连接，存储模块85被配置为：存储第三节点N3的信号。
示例性地，如图8所示，存储模块85包括第一电容Cst，第一极与第一电压端ELVDD连接，第二极以及第三节点N3连接。
在一些实施方式中，像素驱动电路51包括：第一复位模块86，第一复位模块86与第三节点N3、第一复位信号端Vint1以及复位控制信号端Reset连接，第一复位模块86被配置为：根据复位控制信号端Reset的信号，将第一复位信号端Vint1的信号写入第三节点N3。
示例性地，如图8所示，第一复位模块86包括第一晶体管T1，控制极与复位控制信号端Reset连接，第一极与第一复位信号端Vint1连接，第二极与第三节点N3连接。
在一些实施方式中，像素驱动电路51包括：第二复位模块87，第二复位模块87与发光器件52的阳极、第二复位信号端Vint2和扫描信号端Vgate连接，第二复位模块87被配置为：根据扫描信号端Vgate的信号，将第二复位信号端Vint2的信号写入发光器件52的阳极。
示例性地，如图8所示，第二复位模块87包括第七晶体管T7，控制极与扫描信号端Vgate连接，第一极与第二复位信号端Vint2连接，第二极与发光器件52的阳极连接。
示例性地，在图8中，第一晶体管T1至第七晶体管T7均为P型晶体管。当然，第一晶体管T1至第七晶体管T7还可以为N型晶体管，本公开对此不作限定。
为了确保人眼无法察觉到切换画面第一帧的拖影现象，在一些实施方式中，在显示面板显示同一画面的连续多帧画面中，第一帧画面与预设帧画面的亮度之比为首帧亮度占比FFR，首帧亮度占比大于或等于85％，预设帧画面为稳定显示同一画面后的任一帧画面。
本公开提供了一种显示装置，如图9所示，包括：如任一实施方式提供的显示面板Panel；以及显示驱动芯片DDIC。其中，显示驱动芯片DDIC与显示面板Panel连接，用于向显示面板Panel提供驱动信号，驱动信号包括： 第一帧起始信号、时钟信号以及数据信号。
可以理解，本公开提供的显示装置具有上述栅极驱动电路10的优点，这里不再赘述。
本公开提供的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
如图9所示，DDIC与应用处理器AP通过移动产业处理器接口MIPI连接。
在一些实施方式中，驱动信号还可以包括第二帧起始信号等。
本公开提供了一种显示驱动方法，应用于如任一实施方式提供的显示面板(如图5所示)，显示驱动方法包括：
步骤S01：向时钟信号线14提供时钟信号GCK，以使时钟信号线14向移位寄存器13传输时钟信号GCK。
步骤S02：在第一显示阶段，向第一帧起始信号线11提供第一帧起始信号GSTV1，以使第一帧起始信号线11向级联电路12传输第一帧起始信号GSTV1，级联电路12根据第一帧起始信号GSTV1以及时钟信号GCK，逐级输出第一扫描信号G1。
本公开提供的显示驱动方法，可以由显示装置中的显示驱动芯片DDIC执行。
在一些实施方式中，如图5所示，当栅极驱动电路还包括第二帧起始信号线15，第二帧起始信号线15与级联电路12的第二输入端Input2连接时，在步骤S01之后，还包括：
步骤S11：在第二显示阶段，向第二帧起始信号线15提供第二帧起始信号GSTV2，以使第二帧起始信号线15向级联电路12传输第二帧起始信号GSTV2，级联电路12根据第二帧起始信号GSTV2以及时钟信号GCK，逐级输出第二扫描信号G2。
在一些实施方式中，在步骤S02和步骤S11之前，还包括：
步骤S21：获取显示数据，显示数据包括前一帧显示数据和后一帧显示数据，前一帧显示数据与后一帧显示数据为相邻两帧画面的显示数据。
步骤S22：将前一帧显示数据与后一帧显示数据进行比较，根据比较结果， 执行在第一显示阶段的步骤或者在第二显示阶段的步骤。
在一些实施方式中，在步骤S22中，根据比较结果，执行在第一显示阶段的步骤或者在第二显示阶段的步骤，包括：
步骤S31：若前一帧显示数据与后一帧显示数据不同，则执行在第一显示阶段的步骤。
步骤S32：若前一帧显示数据与后一帧显示数据相同，则执行在第二显示阶段的步骤。
在一些实施方式中，如图10所示，第一扫描信号G1包括多个扫描脉冲信号，多条扫描信号线gate包括第一扫描信号G1线，多条数据信号线data包括第一数据信号线data1，与第一扫描信号G1线以及第一数据信号线data1连接的像素驱动电路51为第一像素驱动电路51，在步骤S02之后，还包括：
步骤S41：相互分隔开的多个补偿阶段，各补偿阶段包括：向第一像素驱动电路51的扫描信号端Vgate输入扫描脉冲信号，向第一像素驱动电路51的数据信号端Vdata提供数据信号，以使数据信号写入第一像素驱动电路51。
在每个补偿阶段，都能够对驱动晶体管T3的栅极进行一次电压偏置，多个补偿阶段可以对驱动晶体管T3的阈值电压进行多次补偿，使得驱动晶体管T3的阈值电压向负向偏移。
在一些实施方式中，如图11所示，第二扫描信号G2包括一个扫描脉冲信号，多条扫描信号线gate包括第一扫描信号G1线，多条数据信号线data包括第一数据信号线data1，与第一扫描信号G1线以及第一数据信号线data1连接的像素驱动电路51为第一像素驱动电路51，在步骤S11之后，还包括：一个补偿阶段，向第一像素驱动电路51的扫描信号端Vgate输入扫描脉冲信号，向第一像素驱动电路51的数据信号端Vdata提供数据信号，以使数据信号写入第一像素驱动电路51。
在一些实施方式中，如图5所示，多条数据信号线data还包括第二数据信号线data2，显示面板还包括信号端子Source、第一数据选择电路Mux1和第二数据选择电路Mux2，且第一数据信号线data1与信号端子Source通过第一数据选择电路Mux1连接，第二数据信号线data2与信号端子Source通过第二数据选择电路Mux2连接，如图7所示，在步骤S41中，在各补偿阶段之前，还包括：
步骤S51：向信号端子Source提供数据信号，控制第一数据选择电路Mux1打开，控制第二数据选择电路Mux2关闭，以使数据信号写入第一数据存储电容Cdata1中，第一数据存储电容Cdata1的一个极板与第一数据信号线data1连接。
在具体实施时，如图10图7所示，在步骤S41中，在各补偿阶段之前，还可以包括：向信号端子Source提供数据信号，控制第二数据选择电路Mux2打开，控制第一数据选择电路Mux1关闭，以使数据信号写入第二数据存储电容Cdata2中，第二数据存储电容Cdata2的一个极板与第二数据信号线data2连接。
在一些实施方式中，如图8所示，当第一像素驱动电路51包括写入模块81、驱动模块82、补偿模块83、发光控制模块84以及第一复位模块86，且写入模块81与数据信号端Vdata、第一节点N1以及扫描信号端Vgate连接，驱动模块82与第一节点N1、第二节点N2以及第三节点N3连接，补偿模块83与第二节点N2、第三节点N3以及扫描信号端Vgate连接，发光控制模块84与第一电压端ELVDD、使能信号端EM、第一节点N1、第二节点N2以及发光器件52连接，第一复位模块86与第三节点N3、第一复位信号端Vint1和复位控制信号端Reset连接时，补偿阶段t2用于将数据信号依次写入第一节点N1、第二节点N2和第三节点N3，如图10和图11所示，在步骤S41中，在各补偿阶段t2之前，还包括：
步骤S61：复位阶段t1，向第一复位信号端Vint1提供第一复位信号，向复位控制信号端Reset提供复位控制信号(如图10和图11中的Reset)，以使第一复位信号写入第三节点N3。
如图10所示，在步骤S41中的多个补偿阶段t2之后，或者如图11所示，在单个补偿阶段t2之后，还可以包括：
步骤S71：发光阶段t3，向使能信号端EM提供使能信号(如图10和图11中的EM)，以使发光控制模块84与驱动模块82配合，驱动发光器件52发光。
需要说明的是，该显示驱动方法还可以包括更多的步骤，这可以根据实际需求而定，本公开对此不作限制。关于显示驱动方法的详细说明和技术效果可以参考上文中关于栅极驱动电路以及显示面板的描述，此处不再赘述。
本公开中，“多个”的含义是两个或两个以上，“至少一个”的含义是一个或一个以上，除非另有明确具体的限定。
本公开中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、产品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本文中所称的“一个实施例”、“一些实施例”、“示例性实施例”、“一个或者多个实施例”、“示例”、“一个示例”、“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。
在描述一些实施例时，可能使用了“耦接”和“连接”的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C 的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本文中“基于”或“根据”的使用意味着开放和包容性。基于一个或多个所述条件或值的过程、步骤、计算或其他动作，在实践中可以基于其它条件或超出所述的值。根据一个或多个所述条件或值的过程、步骤、计算或其他动作，在实践中可以根据其它条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”、“齐平”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。“齐平”包括绝对齐平和近似齐平，其中近似齐平的可接受偏差范围内例如可以是齐平的两者之间的距离小于或等于其中任一者尺寸的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间 存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (20)

  1. 一种栅极驱动电路，包括：第一帧起始信号线和级联电路；
    所述第一帧起始信号线，与所述级联电路的第一输入端连接，被配置为：在第一显示阶段，向所述级联电路传输第一帧起始信号；
    所述级联电路，包括相互级联的多个移位寄存器，各所述移位寄存器与时钟信号线连接，所述移位寄存器的输出端与像素驱动电路中的写入模块连接，所述级联电路被配置为：根据所述第一帧起始信号以及所述时钟信号线输入的时钟信号，逐级输出第一扫描信号；
    其中，所述第一帧起始信号在一个周期内的有效电平与所述时钟信号的多个脉冲信号交叠，所述第一扫描信号在一个周期内包括多个扫描脉冲信号，所述写入模块用于在所述第一扫描信号的控制下，将数据信号写入所述像素驱动电路。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述栅极驱动电路还包括：
    第二帧起始信号线，与所述级联电路的第二输入端连接，被配置为：在第二显示阶段，向所述级联电路传输第二帧起始信号；
    所述级联电路还被配置为：根据所述第二帧起始信号以及所述时钟信号，逐级输出第二扫描信号；
    其中，所述第二帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量，小于所述第一帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量，所述第二扫描信号在一个周期内包括的扫描脉冲信号数量大于或等于1，且小于所述第一扫描信号在一个周期内包括的扫描脉冲信号数量。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述第一帧起始信号线与所述第二帧起始信号线各自独立设置，或者共用同一条信号线。
  4. 根据权利要求1至3任一项所述的栅极驱动电路，其中，所述第一帧起始信号在一个周期内的有效电平与所述时钟信号交叠的脉冲信号数量大于或等于2，且小于或等于5。
  5. 根据权利要求2至4任一项所述的栅极驱动电路，其中，所述第二帧 起始信号在一个周期内的有效电平与所述时钟信号的一个脉冲信号交叠。
  6. 根据权利要求1至5任一项所述的栅极驱动电路，其中，所述第一帧起始信号的有效电平为低电平。
  7. 根据权利要求2至6任一项所述的栅极驱动电路，其中，所述第二帧起始信号与所述第一帧起始信号的有效电平的电压相同。
  8. 根据权利要求1至7任一项所述的栅极驱动电路，其中，所述级联电路中，第一级移位寄存器的信号输入端连接所述第一输入端以及所述第二输入端，第E级移位寄存器的输出端与第E+F级移位寄存器的信号输入端连接，第M级移位寄存器的输出端与第M-N级移位寄存器的复位信号输入端连接，其中，1≤E＜H，F≥1，E+F≤H，1＜M≤H，1≤N＜M，且E、F、H、M和N均为正整数，所述H为所述级联电路中的移位寄存器总数量。
  9. 一种显示面板，包括：
    阵列排布的多个像素驱动电路；
    多个发光器件，所述发光器件与位于同一像素的像素驱动电路连接；
    多条扫描信号线，所述扫描信号线与位于同一行的像素驱动电路的扫描信号端连接；
    多条数据信号线，所述数据信号线与位于同一列的像素驱动电路的数据信号端连接；以及
    如权利要求1至8任一项所述的栅极驱动电路，所述级联电路中的多个移位寄存器的输出端分别连接不同的扫描信号线；
    其中，所述像素驱动电路被配置为：根据所述扫描信号端的信号，将所述数据信号端的数据信号写入所述像素驱动电路中，以驱动所述发光器件发光。
  10. 根据权利要求9所述的显示面板，其中，所述多条数据信号线包括第一数据信号线和第二数据信号线，所述显示面板还包括：信号端子、第一数据选择电路和第二数据选择电路，所述第一数据信号线与所述信号端子通过所述第一数据选择电路连接，所述第二数据信号线与所述信号端子通过所述第二数据选择电路连接。
  11. 根据权利要求9或10所述的显示面板，其中，所述像素驱动电路包括：
    写入模块，与所述数据信号端、第一节点以及所述扫描信号端连接，被配置为：在补偿阶段，响应于所述扫描信号端的信号，将所述数据信号写入所述第一节点；
    驱动模块，与所述第一节点、第二节点以及第三节点连接，被配置为：在所述第三节点的电位控制下，将所述第一节点的信号写入所述第二节点；
    补偿模块，与所述第二节点、所述第三节点以及所述扫描信号端连接，被配置为：在补偿阶段，根据所述扫描信号端的信号，将所述第二节点的信号写入所述第三节点；
    发光控制模块，与第一电压端、使能信号端、所述第一节点、所述第二节点以及所述发光器件连接，被配置为：在发光阶段，根据所述使能信号端的使能信号，与所述驱动模块配合，驱动所述发光器件发光；
    存储模块，与所述第一电压端以及所述第三节点连接，被配置为存储所述第三节点的信号；
    第一复位模块，与所述第三节点、第一复位信号端以及复位控制信号端连接，被配置为：根据所述复位控制信号端的信号，将所述第一复位信号端的信号写入所述第三节点；以及
    第二复位模块，与所述发光器件的阳极、第二复位信号端和所述扫描信号端连接，被配置为：根据所述扫描信号端的信号，将所述第二复位信号端的信号写入所述发光器件的阳极。
  12. 根据权利要求9至11任一项所述的显示面板，其中，在所述显示装置显示同一画面的连续多帧画面中，第一帧画面与预设帧画面的亮度之比为首帧亮度占比，所述首帧亮度占比大于或等于85％，所述预设帧画面为稳定显示所述同一画面后的任一帧画面。
  13. 一种显示装置，包括：
    如权利要求9至12任一项所述的显示面板；以及
    显示驱动芯片，与所述显示面板连接，用于向所述显示面板提供驱动信号，所述驱动信号包括：所述第一帧起始信号、所述时钟信号以及所述数据信号。
  14. 一种显示驱动方法，应用于如权利要求9至12任一项所述的显示面板，所述显示驱动方法包括：
    向所述时钟信号线提供时钟信号，以使所述时钟信号线向所述移位寄存器传输所述时钟信号；
    在第一显示阶段，向所述第一帧起始信号线提供第一帧起始信号，以使所述第一帧起始信号线向所述级联电路传输所述第一帧起始信号，所述级联电路根据所述第一帧起始信号以及所述时钟信号，逐级输出第一扫描信号。
  15. 根据权利要求14所述的显示驱动方法，其中，当所述栅极驱动电路还包括第二帧起始信号线，所述第二帧起始信号线与所述级联电路的第二输入端连接时，在所述向所述时钟信号线提供时钟信号的步骤之后，还包括：
    在第二显示阶段，向所述第二帧起始信号线提供第二帧起始信号，以使所述第二帧起始信号线向所述级联电路传输所述第二帧起始信号，所述级联电路根据所述第二帧起始信号以及所述时钟信号，逐级输出第二扫描信号。
  16. 根据权利要求15所述的显示驱动方法，其中，在所述向所述第一帧起始信号线提供第一帧起始信号，以及所述向所述第二帧起始信号线提供第二帧起始信号的步骤之前，还包括：
    获取显示数据，所述显示数据包括前一帧显示数据和后一帧显示数据，所述前一帧显示数据与所述后一帧显示数据为相邻两帧画面的显示数据；
    将所述前一帧显示数据与所述后一帧显示数据进行比较，根据比较结果，执行在所述第一显示阶段的步骤或者在所述第二显示阶段的步骤。
  17. 根据权利要求16所述的显示驱动方法，其中，所述根据比较结果，执行在所述第一显示阶段的步骤或者在所述第二显示阶段的步骤，包括：
    若所述前一帧显示数据与所述后一帧显示数据不同，则执行在所述第一显示阶段的步骤；
    若所述前一帧显示数据与所述后一帧显示数据相同，则执行在所述第二显示阶段的步骤。
  18. 根据权利要求14至17任一项所述的显示驱动方法，其中，所述第一扫描信号包括多个扫描脉冲信号，所述多条扫描信号线包括第一扫描信号线，所述多条数据信号线包括第一数据信号线，与所述第一扫描信号线以及所述第一数据信号线连接的像素驱动电路为第一像素驱动电路，在所述向所述第一帧起始信号线提供第一帧起始信号，以使所述第一帧起始信号线向所述级联电路传输所述第一帧起始信号，所述级联电路根据所述第一帧起始信 号以及所述时钟信号，逐级输出第一扫描信号的步骤之后，还包括：
    相互分隔开的多个补偿阶段，各所述补偿阶段包括：向所述第一像素驱动电路的扫描信号端输入所述扫描脉冲信号，向所述第一像素驱动电路的数据信号端提供数据信号，以使所述数据信号写入所述第一像素驱动电路。
  19. 根据权利要求18所述的显示驱动方法，其中，所述多条数据信号线还包括第二数据信号线，所述显示面板还包括信号端子、第一数据选择电路和第二数据选择电路，且所述第一数据信号线与所述信号端子通过所述第一数据选择电路连接，所述第二数据信号线与所述信号端子通过所述第二数据选择电路连接，在各所述补偿阶段之前，还包括：
    向所述信号端子提供所述数据信号，控制所述第一数据选择电路打开，控制所述第二数据选择电路关闭，以使所述数据信号写入第一数据存储电容中，所述第一数据存储电容的一个极板与所述第一数据信号线连接。
  20. 根据权利要求18或19所述的显示驱动方法，其中，当所述第一像素驱动电路包括写入模块、驱动模块、补偿模块、发光控制模块以及第一复位模块，且所述写入模块与所述数据信号端、第一节点以及所述扫描信号端连接，所述驱动模块与所述第一节点、第二节点以及第三节点连接，所述补偿模块与所述第二节点、所述第三节点以及所述扫描信号端连接，所述发光控制模块与第一电压端、使能信号端、所述第一节点、所述第二节点以及所述发光器件连接，所述第一复位模块与所述第三节点、第一复位信号端和复位控制信号端连接时，所述补偿阶段用于将所述数据信号依次写入所述第一节点、所述第二节点和所述第三节点，在各所述补偿阶段之前，还包括：
    复位阶段，向所述第一复位信号端提供第一复位信号，向复位控制信号端提供复位控制信号，以使所述第一复位信号写入所述第三节点；
    在所述多个补偿阶段之后，还包括：
    发光阶段，向所述使能信号端提供使能信号，以使所述发光控制模块与所述驱动模块配合，驱动所述发光器件发光。
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