WO2024155895A1

WO2024155895A1 - Fabrication of supercapacitors with inkjet printed manufacturing

Info

Publication number: WO2024155895A1
Application number: PCT/US2024/012169
Authority: WO
Inventors: Bashir Iqbal MORSHED; Mst Moriom MOMOTA
Original assignee: Texas Tech University System
Priority date: 2023-01-19
Filing date: 2024-01-19
Publication date: 2024-07-25

Abstract

Embodiments described herein provide for metal-insulator-metal (MIM) capacitors, supercapacitors of MIM capacitors, and a method of forming MIM capacitors and supercapacitors. The MIM capacitors and supercapacitors include a plurality of capacitors disposed over each other, each capacitor includes a first conductive layer disposed over a substrate, a dielectric layer disposed on the first conductive layer, and a second conductive layer disposed on the dielectric layer.

Description

FABRICATION OF SUPERCAPACITORS WITH INKJET PRINTED MANUFACTURING

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

[0001] This application claims priority to US Provisional Patent Application Ser. No. 63/439,906, filed on January 19, 2023, which is herein incorporated by reference.

STATEMENT OF FEDERALLY FUNDED RESEARCH

[0002] This disclosure was made with government support under Grant No. CNS- 2105766 awarded by the National Science Foundation. The government has certain rights in the disclosure.

BACKGROUND

Field

[0003] Embodiments of the present disclosure generally relate to capacitors and supercapacitors. More specifically, embodiments described herein provide metal- insulator-metal (MIM) capacitors, supercapacitors of MIM capacitors, and a method of forming MIM capacitors and supercapacitors.

Description of the Related Art

[0004] Ever increasing energy demand in many next generation technologies, such as electric vehicles, renewable energies, smart homes, smart cities, wearables, and internet-of-things (loT), urges to impelled extensive research in the development of new eco-friendly, high-energy density, lightweight, solid-state energy storage technologies. Currently, high-energy-density batteries are based on electrochemical processes that contain rare materials and toxic chemicals. For instance, Lithium Ion (Lil) batteries are the most popular rechargeable batteries with high energy density, large current capacity, and light weight. Lithium-iodide polymer batteries (LiPo) are commonly used in many commercial applications including electric vehicles, drones, wearables, and battery-operated Internet-of- Things (loT).

[0005] For electric vehicles, large capacity lightweight solid-state batteries without fire hazards can be transformative. For wearables and implantables, solid-state flexible batteries can be safer as currently used LiPo batteries might leak hazardous chemicals causing bodily injury. For renewables, safe storage of large energy in low volume will allow consistent energy outputs from unpredictable energy sources such as wind and sun. Prosthetics and robotics also suffer from the high weight and low power density of current battery technologies. Supercapacitors can be one of the approaches to develop solid state batteries. However, current techniques are relatively expensive, are not fully solid-state, are not robust, have a large volume, and have a high weight per capacitance.

[0006] According what is needed in the art are metal-insulator-metal (MIM) capacitors, supercapacitors of MIM capacitors, and and a method of forming MIM capacitors and supercapacitors.

SUMMARY

[0007] In one embodiment, a metal-insulator-metal (MIM) supercapacitor is provided. The supercapacitor includes a plurality of capacitors disposed over each other, each capacitor includes a first conductive layer disposed over a substrate, a dielectric layer disposed on the first conductive layer, and a second conductive layer disposed on the dielectric layer.

[0008] In another embodiment, a supercapacitor is provided. The supercapacitor includes a plurality of metal-insulator-metal (MIM) capacitors disposed over a substrate, each MIM capacitor includes a plurality of capacitors disposed over each other, each capacitor including a first conductive layer disposed over a substrate, a dielectric layer disposed on the first conductive layer, and a second conductive layer disposed on the dielectric layer.

[0009] In another embodiment, a metal-insulator-metal (MIM) supercapacitor is provided. The supercapacitor includes a capacitor stack including a plurality of conductive layers alternating with a plurality of dielectric layers, where a first conductive layer of the plurality of conductive layers is disposed over a substrate, and the plurality of dielectric layers includes one more layer than the plurality of dielectric layers, the MIM supercapacitor capacitor is made by a process of depositing a conductive layer (cl) solution, curing the cl solution to form a conductive layer, forming a dielectric layer, and repeating the depositing the cl solution, the curing the cl solution to form a respective conductive layer of the plurality of conductive layers, and the forming the dielectric layer to form a respective dielectric layer of the plurality of dielectric layers.

[0010] In yet embodiment, a method of fabricating a metal-insulator-metal (MIM) supercapacitor stack is provided. The method includes forming a plurality of capacitors, the forming each capacitor includes depositing a conductive layer (cl) solution, curing the cl solution to form a conductive layer, forming a dielectric layer, and repeating the depositing the cl solution, the curing the cl solution to form a respective conductive layer of a plurality of conductive layers, and the forming of the dielectric layer to form a respective dielectric layer of a plurality of dielectric layers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of its scope, and may admit to other equally effective embodiments.

[0012] Figures 1A and 1 B are schematic, cross-sectional views of a metal-insulator- metal (MIM) capacitor according to embodiments.

[0013] Figure 1 C is a schematic, top view of a conductive layer according to embodiments.

[0014] Figure 1 D is a schematic, top view of a dielectric layer according to embodiments.

[0015] Figure 1 E is a schematic, top view of a capacitor according to embodiments.

[0016] Figure 2 is a schematic, cross-sectional view of a supercapacitor array according to embodiments. [0017] Figures 3A-3F are schematic, cross-sectional views of a substrate during a method of forming a MIM capacitor according to embodiments.

[0018] Figures 4A-4C are schematic, cross-sectional views of a substrate during a sub-method of forming a dielectric layer according to embodiments.

[0019] Figure 5 depicts charging and discharging across a MIM capacitor.

[0020] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure generally relate to capacitors and supercapacitors. More specifically, embodiments described herein provide for metal-insulator-metal (MIM) capacitors, supercapacitors of MIM capacitors, and a method of forming MIM capacitors and supercapacitors.

[0022] Figures 1A and 1 B are schematic, cross-sectional views of a MIM capacitor 100. The MIM capacitor 100 includes a plurality of conductive layers 102 alternating with a plurality of dielectric layers 104. In some embodiments described herein, which can be combined with other embodiments described herein, the dielectric layers 104 include sublayers. In these embodiments further described herein, each dielectric layer 104 two or more sublayers (e.g., three sublayers). The plurality of conductive layers 102 includes one more layer than the plurality of dielectric layers 104. The conductive layers 102 alternate connections to either positive terminal or negative terminals. For example, odd-number conductive layers 102 are connected to a positive terminal, and even-number conductive layers 102 are connected to a negative terminal as further described herein. Capacitors 106 of the MIM capacitor 100 include a dielectric layer 104 disposed between adjacent conductive layers 102. The dielectric layer 104 contacts each of the adjacent conductive layers 102. The MIM capacitor 100 is a supercapacitor with high capacity (1 mF or more, such as to several F capacity). The supercapacitor of the MIM capacitor 100 includes at least 10 (n) capacitors 106, and in some embodiments 100 (n) capacitors 106 (n+1 conductive layers 102 and n dielectric layers 104). In some embodiments, the surface area (i.e. , footprint corresponding to the area of the cl body 110 having the cl body length 119 and the cl body width 113 as further described herein) of the MIM capacitors 100 with multiple conductive layers 102 and dielectric layers 104 is about 1 cm² to about 10 cm². In other embodiments, footprints of the MIM capacitors 100 may be 10,000 cm² or less, 0.001 mm² or greater, or about 0.001 mm² to about 10,000 cm² as required for optimal mechanical and electrical characteristics. The MIM capacitor 100 may include any number of capacitors 106.

[0023] In some embodiments described herein, which can be combined with other embodiments described herein, the MIM capacitor 100 includes a substrate 108 with a first conductive layer 102A disposed thereon. Figure 2 is a schematic, cross- sectional view of a supercapacitor array according to embodiments. As shown in Figure 2, in one embodiment, a plurality of MIM capacitors 100 described herein are arranged in an array formation to form a large area supercapacitor array 200. The supercapacitor array 200 with the plurality of MIM capacitors 100 has an increased capacity. In one embodiment, the MIM capacitors 100 are connected by connecting each of the positive terminals and each of the negative terminals. In another embodiment, the MIM capacitors 100 are not connected with each other. Each MIM capacitor 100 may be individually tested for proper functionality. In other embodiments, multiple supercapacitor arrays 200 are connected or combined to form a very high capacity supercapacitor for a large amount of energy storage. The MIM capacitors 100 of the supercapacitor array 200 have a surface area 202.

[0024] The MIM capacitor 100 of Figure 1A includes a first arrangement 101 A. The first arrangement 101 A includes four capacitors 106. The MIM capacitor 100 of Figure 1 B includes a second arrangement 101 B. The second arrangement 101 B includes two capacitors 106. The first arrangement 101 A of the MIM capacitor 100 includes first, second, third, and fourth capacitors 106A, 106B, 106C, 106D. The second arrangement 101 B of the MIM capacitor 100 includes first and second capacitors 106A, 106B. The first capacitor 106A includes a first dielectric layer 104A between the first conductive layer 102A and a second conductive layer 102B. The second capacitor 106B includes a second dielectric layer 104B between the second conductive layer 102B and a third conductive layer 102C. The third capacitor 106B includes a third dielectric layer 104C between the third conductive layer 102C and a fourth conductive layer 102D. The fourth capacitor 106D includes a fourth dielectric layer 104D between the fourth conductive layer 102D and a fifth conductive layer 102E.

[0025] The conductive layers 102 include a metal containing material or other electrically conductive material. The metal containing material is electrically conductive material. The metal containing material includes, but is not limited to, silver (Ag), copper (Cu), carbon (C), graphene indium tin oxide, or combinations thereof. The carbon material may include carbon nanotubes. The conductive layers 102 include nanoparticles of the metal containing material. In addition to nanoparticles, the metal containing material may include a solvent, such as a glycol and/or ether. The solvent may evaporate after curing. In one embodiment of conductive layers 102 including a metal containing material with silver, the metal containing material includes about 20% to about 50% silver nanoparticle by weight with a silver concentration of about 25% to about 50%, ethylene glycol at a concentration of about 10 to about 15%, and polyethylene glycol 4-(tert-octylphenyl) ether at a concentration of about 0.2 to about 1 %. In other embodiments, different compositions of the metal containing material are utilized.

[0026] The dielectric layers 104 include a dielectric material. In some embodiments, the dielectric constant K is 1.0 or greater. In other embodiments, the dielectric constant K is 1.13 or less. The dielectric material includes an oxide containing material, a polymer material, or a non-conductive material. The polymer material includes, but is not limited to, polyvinylpyrrolidone (PVP), polypyrrole (PPy), polystyrene (PS), polypropylene (PP), polyvinyl chloride (PVC), polyethylene (PE), polyurethane (PU), polycarbonate (PC), polyethylene terephthalate (PET), polyetheretherketone (PEEK), poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS),, or combinations thereof. The oxide containing material includes, but is not limited to, copper(ll) oxide (CuO), silver oxide (Ag2O), or other oxide containing materials. The dielectric material may include a solvent, such as hexanol. In one embodiment of the dielectric layers 104 including PVP, the dielectric material includes about 0.5% to about 20% of PVP by weight and about 0.1 % to about 10% by weight of Poly (melamineco-formaldehyde) in hexanol. In some embodiments, the dielectric material of the dielectric layers 104 is deposited by inkjet printing. In other embodiments, the dielectric material of the dielectric layers 104 is deposited by other process, such as sputtering (e.g., PVD) or deposition (e.g., CVD, ALD, and the like).

[0027] In embodiments including the substrate 108, the substrate 108 includes polyimide, PET, silicone, silicon (Si), polydimethylsiloxane (PDMS), plastic, paper, glass, or combinations thereof. The substrate 108 may be flexible. The conductive layers 102 have a conductive layer (cl) thickness 103. The cl thickness 103 is less than 10 pm. In some embodiments, the cl thickness 103 is about 7 pm. The dielectric layers 104 have a dielectric layer (dl) thickness 105. The dl thickness 105 is less than 1 pm. In some embodiments, the dl thickness 105 is about 0.9 pm. The MIM capacitor 100 has a capacitor thickness 107 of conductive layers 102 and the dielectric layers 104. In some embodiments, the capacitor thickness 107 of the second arrangement 101 B, i.e., two capacitors 106, is about 23 pm. The substrate

108 has a substrate thickness 109. In some embodiments, the substrate thickness

109 is about 25 pm. The MIM capacitor 100 has a thickness 111 including the capacitor thickness 107 and substrate thickness 109. In some embodiments, the thickness 111 of the second arrangement 101 B, i.e., two capacitors 106 and the substrate 108, is about 48 pm.

[0028] Figure 1 C is a schematic, top view of a conductive layer 102. The conductive layers 102 have a cl body 110. In some embodiments, which can be combined with other embodiments described herein, the conductive layers 102 include a trace 112 coupled to the cl body 110. In embodiments including the trace 112, the trace 112 of odd-number (i.e., the first conductive layer 102A, the third conductive layer 102C, in the fifth conductive layer 102E) conductive layers 102 are connected to a positive terminal, and the trace 112 of even-number (i.e., the second conductive layer 102B and fourth conductive layer 102D) conductive layers 102 are connected to a negative terminal. The cl body 110 has a cl body length 119 and a cl body width 113. The trace 112 has a trace length 115 and a trace width 117. The cl body length 119 and the cl body width 113 are about 5 mm to about 10 mm. In one embodiment, the cl body length 119 and the cl body width 113 are about 10 mm. In another embodiment, the cl body length 119 and the cl body width 113 are about 6 mm. In yet embodiment, the cl body length 119 and the cl body width 113 are about 5 mm. In some embodiments, the trace length 115 is about 3 mm and trace width 117 is about 8mm. Figure 1 D is a schematic, top view of a dielectric layer 104. The dielectric layer 104 has a dl length 114 and a dl width 116. The dl length 114 and the dl width 116 are about 9 mm to 16 mm. In one embodiment, the dl length 114 and the dl width 116 are 16 mm. In another embodiment, the dl length 114 and the dl width 116 are 10 mm. In yet another embodiment, the dl length 114 and the dl width 116 are 9 mm. Figure 1 E, is a schematic view, top view of a capacitor 106. The dielectric layer 104 is a body distance 118 from the cl body 110.

[0029] Figures 3A-3F are schematic, cross-sectional views of a substrate 108 during a method of forming a MIM capacitor 100. In an optional operation of the method, the substrate 108 is cleaned. The substrate 108 is cleaned to remove particles and/or other contaminants. A cleaning solution of isopropyl alcohol may be used.

[0030] As shown in Figure 3A, a first conductive layer 102A is formed via a conductive layer (cl) inkjet printing process. The cl inkjet printing process includes depositing droplets of cl solution. The cl solution includes nanoparticles and a solvent. In one example, the cl solution includes about 20% to about 50% silver nanoparticle by weight with a silver concentration of about 25% to about 50%, ethylene glycol at a concentration of about 10 to about 15%, and polyethylene glycol 4-(tert-octylphenyl) ether at a concentration of about 0.2 to about 1 %. The cl solution has a viscosity, surface, tension, and specific gravity. In this example, at 25° C the viscosity of the cl solution is about 8 to about 12 cP, the surface tension is about 28 to about 32 dyne/cm, the specific gravity is 1.6, the Z-average particle size is about 30 to about 50 nm. During the deposition step of the cl inkjet printing process, the ink is ejected from the nozzle drop by drop in a printing direction (e.g. left to right). The deposition angle, deposition temperature, volume and speed of ink droplets of the cl solution, and droplet spacing are controlled by the inkjet printer. In this example, multiple nozzles were used with a head angle setting at 2.5°, which resulted in 15 pm drop spacing at 1693 dots per inch (dpi) printing resolution. The layouts of the conductive layers 102, as shown in Figures 1 C and 1 E, are saved in a file that is provided to the inkjet printer. The software inkjet printer converts the files into a format for the conductive layers 102 to be printed at a dpi resolution. In this example, the resolution is 1693. In a second operation, the printed first conductive layer 102A is cured. The curing temperature and curing time are controlled. The curing temperature is about 120 °C to about 250 °C. In one embodiment, the curing temperature is about 180° C. The curing time is about 2 seconds to about 60 minutes. In one embodiment, the curing time is about 30 minutes. In other embodiments, instead of thermal curing, the conductive layer 102 is cured by via a laser curing process or a sintering process.

[0031] As shown in Figure 3B, a first dielectric layer 104A is formed via a dielectric layer (dl) inkjet printing process. In one example, the dl solution includes 0.5% to about 20% of PVP by weight and about 0.1 % to about 10% by weight of Poly (melamineco-formaldehyde) in hexanol. The PVP in the dl solution was then dispersed by subjecting the mixture to sonication until the dl solution turns transparent. The dl solution has a viscosity, surface, tension, and specific gravity. During the deposition the ink is ejected from the nozzle drop by drop in a printing direction (e.g. left to right). The deposition angle, deposition temperature, volume and speed of ink droplets of the dl solution, and droplet spacing are controlled by the inkjet printer. In this example, multiple nozzles were used with a head angle setting at 2.5°, which resulted in 15 pm drop spacing at 1693 dots per inch (dpi) printing resolution. The layouts of the dielectric layers 104, as shown in Figures 1 D and 1 E, are saved in a file that is provided to the inkjet printer. The software inkjet printer converts the files into a format for the conductive layers 102 to be printed at a dpi resolution. In this example, the resolution is 1693. In a second operation, the printed first dielectric layer 104A is cured. The curing temperature and curing time are controlled. The curing temperature is about 120 °C to about 250 °C. In one embodiment, the curing temperature is about 180° C. The curing time is about 2 seconds to about 60 minutes. In one embodiment, the curing time is about 30 minutes. In other embodiments, instead of thermal curing, the conductive layer 102 is cured by via laser process or sintering process. In some embodiments, the dielectric material of the dielectric layers 104 is deposited by inkjet printing. In other embodiments, the dielectric material of the dielectric layers 104 is deposited by other process, such as sputtering (e.g., PVD) or deposition (e.g., CVD, ALD, and the like).

[0032] In some embodiments, as shown in Figures 4A-4C, the dl inkjet printing process forms three sublayers 120. Figures 4A-4C are schematic, cross-sectional views of a substrate 108 during a sub-method of forming a dielectric layer 104. At a first operation of the sub-method, as shown in Figure 4A, a first sublayer 120A is formed via the dl inkjet printing process. The dl solution is deposited twice, i.e, two coatings of the solution dl solution are deposited. At a second operation of the submethod, the two coatings are cured to form the first sublayer 120A of two coatings. The curing temperature is about 120 °C to about 250 °C. The curing time is about 2 second to about 60 minutes. The first operation and second operation are repeated twice to form the second sublayer 120B, as shown in Figure 4B, and the third the second sublayer 120C, as shown in Figure 4C.

[0033] As shown in Figure 3C, a second conductive layer 102B is formed via the cl inkjet printing process. The second dielectric layer 104B is then formed via the cl inkjet printing process as show in Figure 3D. The sub-method may be utilized to form the second dielectric layer 104B with three sublayers 120. As shown in Figure 3E, a third conductive layer 102C is formed via the cl inkjet printing process to form the second arrangement 101 B of the MIM capacitor 100. The method is repeated to for the first arrangement 101 A of the MIM capacitor 100 including the third dielectric layer 104C, the fourth conductive layer 102D, the fourth dielectric layer 104D, and the fifth conductive layer 102E as shown in Figure 3F.

[0034] The MIM capacitors 100 and the method of forming the MIM capacitors 100 described herein with alterative formation of conductive layers 102 and dielectric layers 104 as shown in Figures 1A and 1 B result in high capacitance per unit footprint with capacity for a small volume leading to high energy density. The capacitance of metal-insulator-metal (MIM) type supercapacitors is be expressed as:

C= _{0 r}A_e/d where A_e is the geometric surface area of the conductive layers 102 (i.e., the area of the cl body 110 having the cl body length 119 and the cl body width 113), so is the permittivity of free space, s_r is the relative permittivity of the dielectric material (also known as dielectric constant K), and d is the distance between the two opposite biased conductive layers 102 (i.e., the dl thickness 105).

[0035] This MIM capacitors 100 achieve a high n*C capacitance due to parallel arrangement of n capacitors 106. The total capacitance (ideal) is expressed as where C is the capacitance for a single MIM capacitor. Thus,

capacitance per unit area is C_perarea=C_stack/A_e=n(^^L). The cl thickness 103 corresponds to m and the dl thickness 105 corresponds to d, and the substrate thickness 109 corresponds to s. The thickness 111 of n stacked capacitors 106 is n+1)m+nd+s. The volume of this supercapacitor is ((n+7)m+nc/+s)*A_e. Therefore,’ the cap ^racitance p ^rer unit volume i

The stored charge per unit volume or charge density of MIM capacitor 100 is:

Here, t_m, td, and t_s are cl thickness 103, dl thickness 105, and substrate thickness 109 respectively. Watt (joules) stored in capacitors \NJ-~₂ CV² , Watt-energy per second is l/l/_Ws=^ CV², and Watt-hour (3600 sec) is W_wh=y^ C'/²=-^ Q '. Ampere-hour (

[0036] One embodiment of the, MIM capacitor 100 has the second arrangement 101 B having the cl thickness 103 of 7 pm, dl thickness of 1 pm, substrate thickness 109 of 25 pm, capacitor thickness 107 of 23 pm, a surface area of about 100 mm² has a capacitance about 2 nF. Figure 5 depicts the charging and discharging with 20 V across the MIM capacitor 100. For the 2 nF MIM capacitor 100, the stored charge is 40 nC. As the volume of this MIM capacitor 100 is 23x1 O’¹⁰ m³ (ignoring the substrate 108), the charge density for this capacitor is 17.4 C/m³ With the substrate 108, the charge density becomes 8.3 C/m³. In another embodiment, a MIM capacitor 100 having a surface area of about 25 mm² with four conductive layers 102 and three dielectric layers 104 has a capacitance of about 0.607 nF. In yet another embodiment, a MIM capacitor 100 having a surface area of about 36 mm² with four conductive layers 102 and three dielectric layers 104 has a capacitance of about 0.778 nF. By stacking more conductive layers 102 and dielectric layers 104, such as an n of 100, it is possible for the change density to be about 1000 C/m³.

[0037] In summation, embodiments of MIM capacitors, supercapacitors, and a method of forming the MIM capacitors and supercapacitors of MIM capacitors are described herein. The MIM capacitors described herein are supercapacitors with high capacity. The supercapacitor of the MIM capacitor 100 includes at least 10, and in some embodiments, 100 capacitors (n) 106 (n+1 conductive layers and n dielectric layers) in a stack. In some embodiments, the surface area (i.e. , footprint) of the MIM capacitors with multiple conductive layers 102 and dielectric layers 104 is about 1 cm² to about 10 cm². In other embodiments, footprints of the MIM capacitors 100 may be 10,000 cm² or less, or 0.001 mm² or more as required for optimal mechanical and electrical characteristics. A plurality of MIM capacitors described herein are arranged in an array formation to form a large area supercapacitor array. The supercapacitor array with the plurality of MIM capacitors has an increased capacity. In one embodiment, the MIM capacitors are connected by connecting each of the positive terminals and each of the negative terminals. In another embodiment, the MIM capacitors are not connected with each other. Each MIM capacitor 100 may be individually tested for proper functionality. In other embodiments, multiple supercapacitor arrays are connected or combined to form a very high capacity supercapacitor for a large amount of energy storage.

[0038] The embodiments of MIM capacitors and supercapacitor formed by the method provided have reduced peeling or cracking while maintaining flexibility resulting from the cured conductive layers and dielectric layers in a solid state. The MIM capacitor described herein has an increased capacitance per volume, density per area, and sheet resistance while reducing recharge time. The MIM capacitor described herein can be used for various applications of electronic devices such as wearables, implantables, robotics, and electric vehicles, or other energy storage solutions. [0039] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. The examples discussed herein are not limiting of the scope, applicability, or aspects set forth in the claims. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. For example, changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as appropriate. For instance, the methods described may be performed in an order different from that described, and various actions may be added, omitted, or combined. Also, features described with respect to some examples may be combined in some other examples. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method that is practiced using other structure, functionality, or structure and functionality in addition to, or other than, the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0040] The use of the term “or” in the claims is used to mean “and/or” unless explicitly indicated to refer to alternatives only or the alternatives are mutually exclusive, although the disclosure supports a definition that refers to only alternatives and “and/or.” Throughout this application, the term “about” is used to indicate that a value includes the inherent variation of error for the device, the method being employed to determine the value, or the variation that exists among the study subjects.

[0041] The methods disclosed herein comprise one or more operations or actions for achieving the methods. The method operations and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of operations or actions is specified, the order and/or use of specific operations and/or actions may be modified without departing from the scope of the claims. Further, the various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor.

[0042] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:

1 . A metal-insulator-metal (MIM) supercapacitor comprising: a plurality of capacitors disposed over each other, each capacitor comprising: a first conductive layer disposed over a substrate; a dielectric layer disposed on the first conductive layer; and a second conductive layer disposed on the dielectric layer.

2. The supercapacitor of claim 1 , wherein the plurality of capacitors include at least 10 capacitors.

3. The supercapacitor of claim 1 , wherein the plurality of capacitors include at least 100 capacitors.

4. The supercapacitor of claim 1 , wherein conductive layers of the capacitors include a metal containing material or other electrically conductive material.

5. The supercapacitor of claim 4, wherein the metal containing material includes silver (Ag), copper (Cu), carbon (C), graphene, indium tin oxide, or combinations thereof.

6. The supercapacitor of claim 4, wherein the conductive layers include nanoparticles of the metal containing material.

7. The supercapacitor of claim 1 , wherein the dielectric layer includes an oxide containing material, a polymer material, or a non-conductive material.

8. The supercapacitor of claim 1 , wherein the substrate includes polyimide, PET, silicone, silicon (Si), polydimethylsiloxane (PDMS), plastic, paper, glass, or combinations thereof.

9. The supercapacitor of claim 1 , wherein the first conductive layer has a surface area of 10,000 cm² or less.

10. The supercapacitor of claim 1 , wherein the first conductive layer has a surface area of 0.001 mm² or more.

11 . The supercapacitor of claim 1 , wherein the first conductive layer has a surface area of about 0.001 mm² to about 10,000 cm².

12. A supercapacitor comprising a plurality of metal-insulator-metal (MIM) capacitors disposed over a substrate, each MIM capacitor comprising: a plurality of capacitors disposed over each other, each capacitor comprising: a first conductive layer disposed over a substrate; a dielectric layer disposed on the first conductive layer; and a second conductive layer disposed on the dielectric layer.

12. The supercapacitor of claim 12, wherein the plurality of capacitors include at least 10 capacitors.

13. The supercapacitor of claim 12, wherein the plurality of capacitors include at least 100 capacitors.

14. The supercapacitor of claim 12, wherein the MIM capacitors are connected to each other.

15. The supercapacitor of claim 12, wherein the MIM capacitors are connected to each other.

16. The supercapacitor of claim 12, wherein multiple supercapacitors are connected.

17. A metal-insulator-metal (MIM) supercapacitor comprising a capacitor stack including a plurality of conductive layers alternating with a plurality of dielectric layers, wherein a first conductive layer of the plurality of conductive layers is disposed over a substrate, and the plurality of dielectric layers includes one more layer than the plurality of dielectric layers, the MIM supercapacitor capacitor is made by a process of: depositing a conductive layer (cl) solution; curing the cl solution to form a conductive layer; forming a dielectric layer; and repeating the depositing the cl solution, the curing the cl solution to form a respective conductive layer of the plurality of conductive layers, and the forming the dielectric layer to form a respective dielectric layer of the plurality of dielectric layers.

18. The supercapacitor of claim 17, wherein the dielectric layer is formed by inkjet printing a dielectric layer (dl) solution and curing the dl solution to form the dielectric layer.

19. The supercapacitor of claim 17, wherein the dielectric layer is formed by sputtering or deposition.

20. The supercapacitor of claim 17, wherein the conductive layer is formed by thermal curing, laser curing, or sintering.

21. A method of fabricating a metal-insulator-metal (MIM) supercapacitor stack, comprising: forming a plurality of capacitors, the forming each capacitor comprising: depositing a conductive layer (cl) solution; curing the cl solution to form a conductive layer; forming a dielectric layer; and repeating the depositing the cl solution, the curing the cl solution to form a respective conductive layer of a plurality of conductive layers, and the forming of the dielectric layer to form a respective dielectric layer of a plurality of dielectric layers.

22. The method of claim 21 , wherein the MIM supercapacitor stack includes three or more capacitors.

23. The method of claim 21 , wherein the cl solution includes nanoparticles and a solvent.

24. The method of claim 21 , wherein the dielectric layer is formed by inkjet printing a dielectric layer (dl) solution and curing the dl solution to form the dielectric layer.

25. The method of claim 21 , wherein the dielectric layer includes multiple sublayers.

26. The method of claim 25, wherein each sublayer is formed by inkjet printing a dielectric layer (dl) solution twice to deposit two coatings and curing the two coatings.

27. The method of claim 21 , wherein the conductive layer includes silver (Ag), copper (Cu), carbon (C), graphene, indium tin oxide, or combinations thereof.

28. The method of claim 21 , wherein the dielectric layer includes an oxide containing material, a polymer material, or a non-conductive material.

29. The method of claim 21 , wherein the plurality of capacitors include at least 10 capacitors.

30. The method of claim 21 , wherein the plurality of capacitors include at least 100 capacitors.