WO2024152581A1

WO2024152581A1 - Pdcch monitoring

Info

Publication number: WO2024152581A1
Application number: PCT/CN2023/118101
Authority: WO
Inventors: Ruixiang MA; Haipeng Lei
Original assignee: Lenovo (Beijing) Limited
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2024-07-25

Abstract

Various aspects of the present disclosure relate to user equipment, base station, processors, and methods for PDCCH monitoring. In an aspect, a user equipment (UE) transmits, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission. The UE monitors, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

Description

PDCCH MONITORING

TECHNICAL FIELD

The present disclosure relates to wireless communications, and more specifically to user equipment, base station, processors, and methods for physical downlink control channel (PDCCH) monitoring, for example, PDCCH monitoring for configured grant (CG) physical uplink shared channel (PUSCH) re-transmission.

BACKGROUND

A wireless communications system may include one or multiple network communication devices, such as base stations, which may be otherwise known as an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. Each network communication devices, such as a base station may support wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE) , or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) . Additionally, the wireless communications system may support wireless communications across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G) ) .

CG PUSCH transmission is widely used in communication between the UE and the base station. After each CG PUSCH transmission or after all the CG PUSCH transmission, the UE may monitor PDCCH to determine whether the CG PUSCH transmission is correctly received by a base station. However, keeping the monitoring of all PDCCH candidates in all the search space sets would waste UE’s power, thus there are still some open problems related to PDCCH monitoring that need to be studied in the future.

SUMMARY

The present disclosure relates to methods, apparatuses, and systems that support PDCCH monitoring.

In a first aspect of the solution, a user equipment (UE) may comprise: a processor; and a transceiver coupled to the processor, wherein the processor is configured to:transmit, via the transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and monitor, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

In some implementations of the method and apparatuses described herein, in the case that the second DCI is received by the UE before the CG PUSCH transmission, the processor may be configured to: monitor, in the case that the CG PUSCH transmission is transmitted before the end of the first duration, the PDCCH in a first monitoring mode after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to terminate the skipping of the PDCCH monitoring and monitor the PDCCH after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to terminate the skipping of the PDCCH monitoring in at least one preset search space (SS) set, and monitor the PDCCH in the at least one preset SS set in a first preset timer after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, the at least one preset SS set may include at least one of the following: at least one SS set configured for monitoring a downlink feedback information (DFI) ; at least one SS set configured for monitoring a DCI format for CG retransmission scheduling; at least one SS set indicated by the base station via radio resource control (RRC) signalling for monitoring PDCCH in the first duration; and at least one predefined SS set for monitoring PDCCH in the first duration.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to terminate the skipping of the PDCCH monitoring and monitor the PDCCH in a second preset timer after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, the processor may be further configured to: in the case that an end time of the first duration is later than an end time of the second preset timer, continue to skip the PDCCH monitoring in the first duration after the end of the second preset timer.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to monitor the PDCCH in a third preset timer starting from the end of the first duration after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to monitor the PDCCH in a third preset timer, the third preset timer starts after the CG PUSCH transmission is transmitted, stops in the first duration, and re-starts after the end of the first duration.

In some implementations of the method and apparatuses described herein, the processor may be configured to monitor the PDCCH in a fourth preset timer after the CG PUSCH transmission is transmitted, and in the case that the second DCI is received before the fourth preset timer expires, the processor may be configured to: monitor the PDCCH in a second monitoring mode after the second DCI is received.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to skip the PDCCH monitoring for the first duration from the end of the second DCI.

In some implementations of the method and apparatuses described herein, the second DCI further may include an information regarding whether the CG PUSCH transmission is correctly received by the base station.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to monitor the PDCCH until the first DCI is received from the base station before the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the first DCI is received.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to monitor the PDCCH until the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the fourth preset timer expires.

In some implementations of the method and apparatuses described herein, a length of the second duration may be equal to a length of the first duration, or the length of the second duration may be equal to a part of the first duration remaining when the skipping of the PDCCH monitoring is started.

In some implementations of the method and apparatuses described herein, the processor may be configured to monitor the PDCCH by further switching to a first preset search space set (SSS) group from a second preset SSS group after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, the first preset SSS group and the second preset SSS group may be preconfigured by the base station or predefined.

In some implementations of the method and apparatuses described herein, a fifth preset timer may be started after the switching to the first preset SSS group from the second preset SSS group, and the processor is further configured to: switch to the second preset SSS group from the first preset SSS group to monitor the PDCCH after the fifth preset timer expires.

In a second aspect of the solution, a user equipment (UE) , may comprise: a processor; and a transceiver coupled to the processor, wherein the processor is configured to:transmit, via the transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and switch to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.

In some implementations of the method and apparatuses described herein, a fifth preset timer may be started after the switching to the first preset SSS group from the second preset SSS group, and the processor may be further configured to: switch to the second preset SSS group from the first preset SSS group to monitor the PDCCH after the fifth preset timer expires.

In a third aspect of the solution, a base station may comprise: a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and transmit, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.

In some implementations of the method and apparatuses described herein, in the case that the second DCI is transmitted by the base station before the CG PUSCH transmission is received, the processor may be configured to: transmit, in the case that the CG PUSCH transmission is received before the end of the first duration, the PDCCH in a first monitoring mode after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to transmit the PDCCH after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to transmit the PDCCH in at least one preset SS set in a first preset timer after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to transmit the PDCCH in a second preset timer after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, the processor may be further configured to: in the case that an end time of the first duration is later than an end time of the second preset timer, stop transmitting the PDCCH in the first duration after the end of the second preset timer.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to transmit the PDCCH in a third preset timer starting from the end of the first duration after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, in the first monitoring mode, the processor may be configured to transmit the PDCCH in a third preset timer, the third preset timer starts after the CG PUSCH transmission is received, stops in the first duration, and re-starts after the end of the first duration.

In some implementations of the method and apparatuses described herein, the processor may be configured to transmit the PDCCH in a fourth preset timer after the CG PUSCH transmission is received, and in the case that the second DCI is transmitted before the fourth preset timer expires, the processor may be configured to: transmit the PDCCH in a second monitoring mode after the second DCI is transmitted.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to stop transmitting the PDCCH for the first duration from the end of the second DCI.

In some implementations of the method and apparatuses described herein, the second DCI may further include an information regarding whether the CG PUSCH transmission is correctly received by the base station.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to transmit the PDCCH until the first DCI is transmitted before the fourth preset timer expires, and stop transmitting the PDCCH for a second duration after the first DCI is transmitted.

In some implementations of the method and apparatuses described herein, in the second monitoring mode, the processor may be configured to transmit the PDCCH until the fourth preset timer expires, and stop transmitting the PDCCH for a second duration after the fourth preset timer expires.

In some implementations of the method and apparatuses described herein, a length of the second duration may be equal to a length of the first duration, or the length of the second duration ma be equal to a part of the first duration remaining when the transmitting of the PDCCH is stopped.

In some implementations of the method and apparatuses described herein, the processor may be configured to transmit the PDCCH by further switching to a first preset search space set (SSS) group from a second preset SSS group after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, the first preset SSS group and the second preset SSS group are preconfigured by the base station or predefined.

In some implementations of the method and apparatuses described herein, a fifth preset timer may be started after the switching to the first preset SSS group from the second preset SSS group, and the processor may be further configured to: switch to the second preset SSS group from the first preset SSS group to transmit the PDCCH after the fifth preset timer expires.

In a fourth aspect of the solution, a base station may comprise: a processor; and a transceiver coupled to the processor, wherein the processor is configured to: receive, via the transceiver and from a user equipment, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and switch to a first preset search space set (SSS) group from a second preset SSS group to transmit a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received.

In some implementations of the method and apparatuses described herein, a fifth preset timer may be started after the switching to the first preset SSS group from the second preset SSS group, and the processor may be further configured to: switch to the second preset SSS group from the first preset SSS group to transmit the PDCCH after the fifth preset timer expires

In a fifth aspect of the solution, a processor for wireless communication may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the processor to: transmit, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and monitor, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

In a sixth aspect of the solution, a method performed by a user equipment (UE) , the method may comprise: transmitting, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and monitoring, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

In a seventh aspect of the solution, a processor for wireless communication, may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the processor to: transmit, via a transceiver and to a base station, configured grant (CG) physical uplink shared channel (PUSCH) transmission; and switch to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.

In an eighth aspect of the solution, a method performed by a user equipment (UE) , the method may comprise: transmitting, via a transceiver and to a base station, configured grant (CG) physical uplink shared channel (PUSCH) transmission; switching to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.

In a ninth aspect of the solution, a processor for wireless communication may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the processor to: receive, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and transmit, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.

In a tenth aspect of the solution, a method performed by a base station, the method may comprise: receiving, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and transmitting, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.

In an eleventh aspect of the solution, a processor for wireless communication, may comprise: at least one memory; and a controller coupled with the at least one memory and configured to cause the processor to: receive, via the transceiver and from a user equipment, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and transmit, in a first preset search space set (SSS) group and not in a second preset SSS group, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received.

In a twelfth aspect of the solution, a method performed by a base station, the method may comprise: receiving, via the transceiver and from a user equipment, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and switching to a first preset search space set (SSS) group from a second preset SSS group to transmit a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received.

It is to be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure. Other features of the present disclosure will become easily comprehensible through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an example of a wireless communications system that supports PDCCH monitoring in accordance with aspects of the present disclosure.

FIG. 2 illustrates an example of PDCCH monitoring associated with aspects of the present disclosure.

FIG. 3 illustrates an example of PDCCH monitoring occasions associated with aspects of the present disclosure.

FIG. 4 illustrates an example of PDCCH monitoring associated with aspects of the present disclosure.

FIG. 5 illustrates an example of PDCCH skipping associated with aspects of the present disclosure.

FIG. 6 illustrates an example of CG PUSCH transmission occasions (TOs) in a CG period associated with aspects of the present disclosure.

FIG. 7 illustrates an example of PDCCH monitoring in the case that a DCI providing PDCCH monitoring adaption filed is detected associated with aspects of the present disclosure.

FIG. 8 illustrates an example of signalling procedure of PDCCH monitoring in accordance with aspects of the present disclosure.

FIGS. 9A to 9D illustrate examples of monitoring PDCCH in accordance with aspects of the present disclosure.

FIGS. 10A to 10D illustrate examples of monitoring PDCCH in accordance with aspects of the present disclosure.

FIG. 11 illustrates another example of signalling procedure of PDCCH monitoring in accordance with aspects of the present disclosure.

FIG. 12 illustrates an example of monitoring PDCCH in accordance with aspects of the present disclosure.

FIGS. 13 to 16 illustrate examples of devices that support PDCCH monitoring in accordance with aspects of the present disclosure.

FIGS. 17 to 20 illustrate examples of processors that support PDCCH monitoring in accordance with aspects of the present disclosure.

FIGS. 21 to 24 illustrate flowcharts of methods that support PDCCH monitoring in accordance with aspects of the present disclosure.

DETAILED DESCRIPTION

Principles of the present disclosure will now be described with reference to some embodiments. It is to be understood that these embodiments are described only for the purpose of illustration and help those skilled in the art to understand and implement the present disclosure, without suggesting any limitation as to the scope of the disclosure. The disclosure described herein may be implemented in various manners other than the ones described below.

In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

References in the present disclosure to “one embodiment, ” “an example embodiment, ” “an embodiment, ” “some embodiments, ” and the like indicate that the embodiment (s) described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment (s) . Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms “first” and “second” or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could also be termed as a second element, and similarly, a second element could also be termed as a first element, without departing from the scope of embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a” , “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” , “comprising” , “has” , “having” , “includes” and/or “including” , when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof.

As used herein, the term “communication network” refers to a network following any suitable communication standards, such as, 5G new radio (NR) , long term evolution (LTE) , LTE-advanced (LTE-A) , wideband code division multiple access (WCDMA) , high-speed packet access (HSPA) , narrow band internet of things (NB-IoT) , and so on. Further, the communications between a terminal device and a network device in the communication network may be performed according to any suitable generation communication protocols, including but not limited to, the first generation (1G) , the second generation (2G) , 2.5G, 2.75G, the third generation (3G) , the fourth generation (4G) , 4.5G, the fifth generation (5G) communication protocols, and/or any other protocols either currently known or to be developed in the future. Embodiments of the present disclosure may be applied in various communication systems. Given the rapid development in communications, there will also be future type communication technologies and systems in which the present disclosure may be embodied. It should not be seen as limiting the scope of the present disclosure to only the aforementioned systems.

As used herein, the term “network device” generally refers to a node in a communication network via which a terminal device can access the communication network and receive services therefrom. The network device may refer to a base station (BS) or an access point (AP) , for example, a node B (NodeB or NB) , a radio access network (RAN) node, an evolved NodeB (eNodeB or eNB) , a NR NB (also referred to as a gNB) , a remote radio unit (RRU) , a radio header (RH) , an infrastructure device for a V2X (vehicle-to-everything) communication, a transmission and reception point (TRP) , a reception point (RP) , a remote radio head (RRH) , a relay, an integrated access and backhaul (IAB) node, a low power node such as a femto BS, a pico BS, and so forth, depending on the applied terminology and technology.

As used herein, the term “terminal device” generally refers to any end device that may be capable of wireless communications. By way of example rather than a limitation, a terminal device may also be referred to as a communication device, a user equipment (UE) , an end user device, a subscriber station (SS) , an unmanned aerial vehicle (UAV) , a portable subscriber station, a mobile station (MS) , or an access terminal (AT) . The terminal device may include, but is not limited to, a mobile phone, a cellular phone, a smart phone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet, a wearable terminal device, a personal digital assistant (PDA) , a portable computer, a desktop computer, an image capture terminal device such as a digital camera, a gaming terminal device, a music storage and playback appliance, a vehicle-mounted wireless terminal device, a wireless endpoint, a mobile station, laptop-embedded equipment (LEE) , laptop-mounted equipment (LME) , a USB dongle, a smart device, wireless customer-premises equipment (CPE) , an internet of things (loT) device, a watch or other wearable, a head-mounted display (HMD) , a vehicle, a drone, a medical device (for example, a remote surgery device) , an industrial device (for example, a robot and/or other wireless devices operating in an industrial and/or an automated processing chain contexts) , a consumer electronics device, a device operating on commercial and/or industrial wireless networks, and the like. In the following description, the terms: “terminal device, ” “communication device, ” “terminal, ” “user equipment” and “UE, ” may be used interchangeably.

For a PUSCH transmission, when PUSCH resource allocation is semi-statically configured by a higher layer parameter configuredGrantConfig in BWP-UplinkDedicated information element, and the PUSCH transmission corresponds to a configured grant (CG) , the PUSCH transmission may correspond to a CG Type 1 or CG Type 2. The CG Type 1 PUSCH transmission is semi-statically configured to operate upon the reception of the higher layer parameter configuredGrantConfig including rrc-ConfiguredUplinkGrant without detection of an UL grant in a DCI. The CG Type 2 PUSCH transmission is semi-persistently scheduled by an UL grant in a valid activation DCI after reception of the higher layer parameter configuredGrantConfig not including rrc-ConfiguredUplinkGrant. UE could be configured with one or multiple CG configurations for CG PUSCH transmission, and for each CG configuration, a period P and a CG type are provided.

After a CG PUSCH transmission, UE should determine whether the CG PUSCH transmission is correctly received by a corresponding network device, e.g., base station or gNB. To this end, the UE may monitor PDCCH to detect a DCI indicating whether the CG PUSCH transmission is correctly received by the network device. There are two monitoring manners including: (1) the UE should monitors PDCCH in a timer 1(for example, may be configured by the base station via RRC signalling, configuredGrantTimer) and may assume that the CG PUSCH transmission is acknowledge (ACK) (which means that the CG PUSCH transmission is correctly received) if there is no DCI scheduling a PUSCH retransmission is received in the timer 1; and (2) the UE receives a DCI carrying CG-downlink feedback information (DFI) that provides hybrid automatic repeat request (HARQ) -ACK information for a transport block corresponding to the CG PUSCH transmission in a timer 2 (for example, may be configured by the base station via RRC signalling, cg-RetransmissionTimer) , and may assume that the transport block was correctly decoded (which means that the CG PUSCH transmission is correctly received) if a corresponding HARQ-ACK information value is ACK; otherwise, for example, if the corresponding HARQ-ACK information value is Negative Acknowledgement (NACK) or the DCI carrying CG-DFI is not received, the UE assumes that the transport block was not correctly decoded (which means that the CG PUSCH transmission is not correctly received) , an example for manner (2) is shown in FIG. 2.

As shown in FIG. 2, a DFI 201 carried by a DCI is received after the CG PUSCH transmission 202 is transmitted and it has 8 bits to indicate HARQ-ACK information of 8 HARQ processes (i.e., “ANANAAAN” in FIG. 2) , each HARQ process corresponds to a CG PUSCH transmission. The CG PUSCH transmission 202 corresponds to HARQ processes number (HPN) 7 (i.e. the last bit in the HARQ-ACK information) , and the corresponding HARQ-ACK is N (i.e., NACK, thus the UE would retransmit the CG PUSCH transmission 202. In other word, the UE may judge whether the CG PUSCH transmission 202 is ACK or NACK to determine whether the CG PUSCH transmission 202 is correctly received by the base station.

If UE knows the PUSCH is ACK, then the corresponding buffer would be flushed, and the corresponding HARQ process could be used for new transmission; and if UE knows the PUSCH is NACK, UE would retransmit the PUSCH or wait the scheduling of the PUSCH retransmission.

As discussed above, No matter which monitoring manner is used, the UE should monitor PDCCH after a CG PUSCH transmission 202 is transmitted. A set of PDCCH candidates for a UE to monitor is defined in terms of PDCCH search space sets. A search space set can be a common search space (CSS) set or a UE-specific search space (USS) set. The UE monitors PDCCH candidates in one or more search spaces sets. For example, UE could be provided by higher layers with S≤40 search space sets, and for each search space set from the S search space sets, the UE could be provided by SearchSpace at least the following parameters: a search space set index s, 0<s≤40, indicated by searchSpaceId; an association between the search space set s and a CORESET p indicated by controlResourceSetId or by controlResourceSetId-v1610; a PDCCH monitoring periodicity of k_s slots and a PDCCH monitoring offset of o_s slots, indicated by monitoringSlotPeriodicityAndOffset or by monitoringSlotPeriodicityAndOffset-r17; and a PDCCH monitoring pattern within a slot, indicating first symbol (s) of the CORESET for PDCCH monitoring within each slot where the UE monitors PDCCH, indicated by monitoringSymbolsWithinSlot.

The UE may determine a PDCCH monitoring occasion on an active down link (DL) bandwidth part (BWP) based on the PDCCH monitoring periodicity, the PDCCH monitoring offset, and the PDCCH monitoring pattern within a slot.

For example, SS set 1 is associated with CORESET 1, for CORESET 1, duration=2 symbols is configured. For SS set 1, the configured periodicity is k_s =2 slots, and offset o_s=1 slot, and PDCCH monitoring pattern within a slot is 10001000000000, then the PDCCH monitoring occasions are determined as FIG. 3 (indicated by gray blocks 301-304 in FIG. 3) . The frequency domain resource of each occasion is the frequency domain resource configured in the CORESET.

However, keeping the monitoring of all PDCCH candidates in all the Search space sets would waste UE power. Considering that there could be some case where no PDCCH is sent by base station, some PDCCH monitoring occasions could be skipped. For example, all the SS sets could be grouped into two groups, for example, SS set group 0 and SS set group 1, and UE could be indicated to monitor PDCCH only in SS set group 0 or 1. The UE could also be indicated to skip PDCCH monitoring in a duration. Details regarding such PDCCH skipping in the specification is described below.

When a UE is provided searchSpaceGroupIdList, the UE resets PDCCH monitoring according to search space sets with group index 0, if provided by searchSpaceGroupIdList.

A UE can be provided by searchSpaceSwitchDelay a number of symbols P_switch where a minimum value of P_switch is provided in Table 1 for UE processing capability 1 and UE processing capability 2 and SCS configuration μ. UE processing capability 1 for SCS configuration μ applies unless the UE indicates support for UE processing capability 2.

Table 1: Minimum value of P_switch [symbols]

A UE can be provided, by searchSpaceSwitchTimer, a timer value for a serving cell that the UE is provided searchSpaceGroupIdList or, if provided, for a set of serving cells provided by cellGroupsForSwitchList. The UE decrements the timer value by one after each slot based on a reference SCS configuration that is the smallest SCS configuration μ among all configured DL BWPs in the serving cell, or in the set of serving cells. The UE maintains the reference SCS configuration during the timer decrement procedure.

If a UE is provided by SearchSpaceSwitchTrigger a location of a search space set group switching flag field in a DCI format 2_0, for a serving cell where the UE has active DL BWP with SCS configuration μ, the UE may start or stop monitoring PDCCH as following: (1) if the UE detects a DCI format 2_0 and a value of the search space set group switching flag field in the DCI format 2_0 is 0, the UE starts monitoring PDCCH according to search space sets with group index 0, and stops monitoring PDCCH according to search space sets with group index 1, for the serving cell, at the beginning of the first slot that is at least P_switch symbols after the last symbol of the PDCCH with the DCI format 2_0 when μ∈ {0, 1, 2, 3} , and the UE sets the timer value to the value provided by searchSpaceSwitchTimer; (2) if the UE detects a DCI format 2_0 and a value of the search space set group switching flag field in the DCI format 2_0 is 1, the UE starts monitoring PDCCH according to search space sets with group index 1, and stops monitoring PDCCH according to search space sets with group index 0, for the serving cell, at the beginning of the first slot that is at least P_switch symbols after the last symbol of the PDCCH with the DCI format 2_0 when μ∈ {0, 1, 2, 3} . After that, if the UE monitors PDCCH for a serving cell according to search space sets with group index 1, the UE starts monitoring PDCCH for the serving cell according to search space sets with group index 0, and stops monitoring PDCCH according to search space sets with group index 1, for the serving cell, at the beginning of the first slot that is at least P_switch symbols after a slot where the timer expires or after a last symbol of a remaining channel occupancy duration for the serving cell if indicated by DCI format 2_0 when μ∈ {0, 1, 2, 3} .

An example of PDCCH monitoring related to above process is shown in FIG. 4.

If a UE is not provided SearchSpaceSwitchTrigger for a serving cell, and if the UE detects a DCI format by monitoring PDCCH according to a search space set with group index 0, the UE starts monitoring PDCCH according to search space sets with group index 1, and stops monitoring PDCCH according to search space sets with group index 0, for the serving cell, at the beginning of the first slot that is at least P_switch symbols after the last symbol of the PDCCH with the DCI format when μ∈ {0, 1, 2, 3} . The UE sets the timer value to the value provided by searchSpaceSwitchTimer if the UE detects a DCI format by monitoring PDCCH in any search space set. In this case, if the UE monitors PDCCH for a serving cell according to search space sets with group index 1, the UE starts monitoring PDCCH for the serving cell according to search space sets with group index 0, and stops monitoring PDCCH according to search space sets with group index 1, for the serving cell, at the beginning of the first slot that is at least P_switch symbols after a slot where the timer expires or, if the UE is provided a search space set to monitor PDCCH for detecting a DCI format 2_0, after a last symbol of a remaining channel occupancy duration for the serving cell if indicated by DCI format 2_0 when μ∈ {0, 1, 2, 3} .

The UE determines a slot and a symbol in the slot to start or stop PDCCH monitoring according to search space sets for a serving cell that the UE is provided searchSpaceGroupIdList or, if cellGroupsForSwitchList is provided, for a set of serving cells, based on the smallest SCS configuration μ among all configured DL BWPs in the serving cell or in the set of serving cells and, if any, in the serving cell where the UE receives a PDCCH and detects a corresponding DCI format 2_0 triggering the start or stop of PDCCH monitoring according to search space sets.

A UE can be provided a set of durations by PDCCHSkippingDurationList for PDCCH monitoring on an active DL BWP of a serving cell and, if the UE is not provided searchSpaceGroupIdList-r17 on the active DL BWP of the serving cell, a DCI format 0_1 and a DCI format 0_2 that schedule PUSCH transmission, and a DCI format 1_1 and a DCI format 1_2 that schedule PDSCH receptions can include a PDCCH monitoring adaptation field of 1 bit or of 2 bits.

If the PDCCH monitoring adaptation field has 1 bit and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on the active DL BWP of the serving cell, then a '0' value for the bit indicates no skipping in PDCCH monitoring, and a '1' value for the bit indicates skipping PDCCH monitoring for a duration provided by the first value in the set of durations.

If the PDCCH monitoring adaptation field has 2 bits and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on the active DL BWP of the serving cell, the a '00' value for the bits indicates no skipping in PDCCH monitoring, a '01' value for the bits indicates skipping PDCCH monitoring for a duration provided by the first value in the set of durations, a '10' value for the bits indicates skipping PDCCH monitoring for a duration provided by the second value in the set of durations, and a '11' value for the bits indicates skipping PDCCH monitoring for a duration provided by the third value in the set of durations, if any; otherwise, if the set of durations includes two values, a use of the '11' value is reserved.

A UE can be provided group indexes for a Type3-PDCCH CSS set or USS set by searchSpaceGroupIdList-r17 for PDCCH monitoring on an active DL BWP of a serving cell and, if the UE is not provided PDCCHSkippingDurationList for the active DL BWP of the serving cell, a DCI format 0_1 and a DCI format 0_2 that schedule PUSCH transmissions and a DCI format 1_1 and a DCI format 1_2 that schedule PDSCH receptions can include a PDCCH monitoring adaptation field of 1 bit or of 2 bits for the serving cell.

If the field has 1 bit and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on the active DL BWP of the serving cell, then a '0' value for the bit indicates start of PDCCH monitoring according to search space sets with group index 0 and stop of PDCCH monitoring according to search space sets with other group indexes, if any, and a '1' value for the bit indicates start of PDCCH monitoring according to search space sets with group index 1 and stop of PDCCH monitoring according to search space sets with other group indexes, if any, and the UE sets the timer value to the one provided by searchSpaceSwitchTimer-r17.

If the field has 2 bits and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on the active DL BWP of the serving cell, then a '00' value for the bit indicates start of PDCCH monitoring according to search space sets with group index 0 and stop of PDCCH monitoring according to search space sets with other group indexes, if any; a '01' value for the bit indicates start of PDCCH monitoring according to search space sets with group index 1 and stop of PDCCH monitoring according to search space sets with other group indexes, if any, and the UE sets the timer value to the one provided by searchSpaceSwitchTimer-r17; a '10' value for the bit indicates start of PDCCH monitoring according to search space sets with group index 2 and stop of PDCCH monitoring according to search space sets with other group indexes, if any, and the UE sets the timer value to the one provided by searchSpaceSwitchTimer-r17; and a '11' value is reserved.

A UE can be provided a set of durations by PDCCHSkippingDurationList and group indexes for a Type3-PDCCH CSS set or USS set by searchSpaceGroupIdList-r17 for PDCCH monitoring on an active DL BWP of a serving cell and, a DCI format 0_1 and a DCI format 0_2 that schedule PUSCH transmissions, and a DCI format 1_1 and a DCI format 1_2 that schedule PDSCH receptions can include a PDCCH monitoring adaptation field of 2 bits.

If the set of durations includes one value and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on the active DL BWP of the serving cell, then a '00' value for the bits indicates start of PDCCH monitoring according to search space sets with group index 0 and stop of PDCCH monitoring according to search space sets with group index 1, if any; a '01' value for the bits indicates start of PDCCH monitoring according to search space sets with group index 1 and stop of PDCCH monitoring according to search space sets with group index 0, if any, and the UE sets the timer value to the one provided by searchSpaceSwitchTimer-r17; a '10' value for the bits indicates skipping PDCCH monitoring for a duration provided by the value in the set of durations; and a '11' value is reserved.

If the set of durations includes two values and for PDCCH monitoring by the UE according to Type3-PDCCH CSS sets or USS sets on active DL BWP of the serving cell, then a '00' value for the bits indicates start of PDCCH monitoring according to search space sets with group index 0 and stop of PDCCH monitoring according to search space sets with group index 1, if any; a '01' value for the bits indicates start of PDCCH monitoring according to search space sets with group index 1 and stop of PDCCH monitoring according to search space sets with group index 0, if any, and the UE sets the timer value to the one provided by searchSpaceSwitchTimer-r17; a '10' value for the bits indicates skipping PDCCH monitoring for a duration provided by the first value in the set of durations; and a '11' value for the bits indicates skipping PDCCH monitoring for a duration provided by the second value in the set of durations.

When the PDCCH monitoring adaptation field indicates a UE to start PDCCH monitoring according to search space sets with a first group index and stop PDCCH monitoring according to search space sets with a second group index, the UE applies the indication at the beginning of a first slot that is at least P_switch symbols after the last symbol of the PDCCH reception providing the DCI format with the PDCCH monitoring adaptation field when μ∈ {0, 1, 2, 3} .

When the PDCCH monitoring adaptation field indicates a UE to skip PDCCH monitoring for a duration on the active DL BWP of a serving cell, the UE starts skipping of PDCCH monitoring at the beginning of a first slot that is after the last symbol of the PDCCH reception providing the DCI format with the PDCCH monitoring adaptation field.

If a UE is provided group indexes for a Type3-PDCCH CSS set or a USS set by searchSpaceGroupIdList-r17 and a timer value by searchSpaceSwitchTimer-r17 for PDCCH monitoring an active DL BWP of on a serving cell and the timer is running, the UE resets the timer after a slot of the active DL BWP of the serving cell if the UE detects a DCI format in a PDCCH reception in the slot for with CRC scrambled by C-RNTI/CS-RNTI/MCS-C-RNTI, otherwise, the UE decrements the timer value by one after a slot of the active DL BWP of the serving cell.

When the timer expires in a first slot, the UE monitors PDCCH on the serving cell according to search space sets with group index 0 starting in a second slot that is not earlier than P_switch symbols after the first slot when μ∈ {0, 1, 2, 3} , and/or is not earlier than a slot where a PDCCH skipping duration expires, if applicable.

FIG. 5 illustrates an example of PDCCH skipping associated with aspects of the present disclosure. In particular, FIG. 5 illustrates an example of PDCCH skipping with a DCI including a PDCCH monitoring adaptation field of 1 bit or of 2 bits.

As shown in FIG. 5, the DCI including a PDCCH monitoring adaptation field of 1 bit or of 2 bits may indicate the UE to skip PDCCH monitoring in a duration, the duration may be determined using the method mentioned before, for example, the duration may be one in the set of durations provided by PDCCHSkippingDurationList.

Related content about PDCCH monitoring and PDCCH skipping in the specification is described as above. However, with the development of communication technology, a need for improvement of PDCCH monitoring is increasing. For example, Xtended Reality (XR) is a broad term covering Augmented Reality (AR) , Mixed Reality (MR) and Virtual Reality (VR) . Along with Cloud Computing, XR applications typically requires high throughput and low latency, and have a big packet size and variable data packet size. To realize the low latency requirement and the big packet size, it has been decided in 3GPP to configure multiple CG PUSCH transmission occasions (TOs) in a period of a single CG PUSCH configuration. gNB could configure a parameter N and indicate a single start and length indicator value (SLIV) from a configured time domain resource allocation (TDRA) table, and UE could determine N resource in in each of N consecutive slots per CG period, and each resource has same SLIV in the slot.

As shown in FIG. 6, for example, assuming that the period of a CG is 6 slots, and N=4, and a SLIV is indicated, then the determined N TOs in a CG period could be shown in FIG. 6 by grey squares 601, 602, 603, and 604.

After each CG PUSCH transmission or all the CG PUSCH transmission, there are two manners for the UE to monitor PDCCH, that is, as mentioned above: (1) the UE should monitors PDCCH in a timer 1 and may assume that the CG PUSCH transmission is ACK (which means that the CG PUSCH transmission is correctly received) if there is no DCI scheduling a PUSCH retransmission is received in the timer 1; and (2) the UE receives a DCI carrying CG-DFI that provides HARQ-ACK information for a transport block corresponding to the CG PUSCH transmission in a timer 2, and may assume that the transport block was correctly decoded (which means that the CG PUSCH transmission is correctly received) if a corresponding HARQ-ACK information value is ACK; otherwise, for example, if the corresponding HARQ-ACK information value is NACK or the DCI carrying CG-DFI is not received, the UE assumes that the transport block was not correctly decoded (which means that the CG PUSCH transmission is not correctly received) .

However, for above manner (1) , if the PDCCH is skipped after the UE detects a DCI format providing the PDCCH monitoring adaptation field indicating to the UE to skip PDCCH monitoring for the duration, the UE could not receive the DCI scheduling retransmission when the timer 1 is running, which makes UE decide the CG PUSCH transmission is ACK, and which would have effect on the reliability of the PUSCH. And for manner (2) , if the PDCCH is skipped after the UE detects a DCI format providing the PDCCH monitoring adaptation field indicating to the UE to skip PDCCH monitoring for the duration, the UE could not receive the DFI when the timer 2 is running, which makes UE decide the CG PUSCH transmission is NACK, and then UE would retransmit the PUSCH, which would have effect on the system capacity. In addition, for bother manner (1) and manner (2) , if the PDCCH monitoring occasions in the timer (e.g., timer 1 or timer 2) are less, the UE could not receive the DCI (i.e., a DCI scheduling retransmission or a DCI carry the DFI) timely, thus the latency requirement of XR cannot be guaranteed, if all the PDCCH monitoring occasions are monitored by the UE, UE power would be wasted.

FIG. 7 illustrates an example of PDCCH monitoring in the case that a DCI providing PDCCH monitoring adaption filed is detected in accordance with aspects of the present disclosure.

As shown in FIG. 7, the timer for monitoring PDCCH (for example, timer 1 or timer 2) is within the duration for skipping PDCCH monitoring, thus even the timer runs after the CG PUSCH transmission 702 is transmitted, UE do not monitor PDCCH due to the DCI 701, and could not receive a DCI indicating whether the CG PUSCH transmission 702 is correctly received by the corresponding base station in the timer.

Thus, it needs a solution to solve above issues to guarantee the latency, reliability, power and capacity requirement of CG PUSCH transmission.

The present disclosure proposed a solution to support PDCCH monitoring, for example, for PDCCH monitoring for CG PUSCH transmission. In this solution, after a CG PUSCH transmission is transmitted, the UE may monitor PDCCH timely in a power-saving way. By implementing the example embodiments of the present disclosure, the latency, reliability, and capacity requirement of CG PUSCH transmission could be guaranteed while the power of the UE is saved. For example, by implementing the example embodiments of the present disclosure, for above monitoring manner (1) , UE could detect the DCI scheduling retransmission in a timely manner, and the UE could retransmit the PUSCH timely and then reduce latency and for monitoring manner (2) , UE may receive the DCI to indicate ACK and do not need to retransmit the CG PUSCH transmission, the capacity could be guarantee, or the UE may receive the DCI to indicate NACK and retransmit the CG PUSCH transmission timely and then the reliability and latency could be guarantee.

Aspects of the present disclosure are described in the context of a wireless communications system.

FIG. 1 illustrates an example of a wireless communications system 100 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more network entities 102 (also referred to as network equipment (NE) ) , one or more UEs 104, a core network 106, and a packet data network 108. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, such as an LTE network or an LTE-advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including institute of electrical and electronics engineers (IEEE) 802.11 (Wi-Fi) , IEEE 802.16 (WiMAX) , IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA) , frequency division multiple access (FDMA) , or code division multiple access (CDMA) , etc.

The one or more network entities 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the network entities 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a radio access network (RAN) , a base transceiver station, an access point, a NodeB, an eNodeB (eNB) , a next-generation NodeB (gNB) , or other suitable terminology. A network entity 102 and a UE 104 may communicate via a communication link 110, which may be a wireless or wired connection. For example, a network entity 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

A network entity 102 may provide a geographic coverage area 112 for which the network entity 102 may support services (e.g., voice, video, packet data, messaging, broadcast, etc. ) for one or more UEs 104 within the geographic coverage area 112. For example, a network entity 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc. ) according to one or multiple radio access technologies. In some implementations, a network entity 102 may be moveable, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but the different geographic coverage areas 112 may be associated with different network entities 102. Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The one or more UEs 104 may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a mobile device, a wireless device, a remote device, a remote unit, a handheld device, or a subscriber device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an internet-of-things (IoT) device, an internet-of-everything (IoE) device, or machine-type communication (MTC) device, among other examples. In some implementations, a UE 104 may be stationary in the wireless communications system 100. In some other implementations, a UE 104 may be mobile in the wireless communications system 100.

The one or more UEs 104 may be devices in different forms or having different capabilities. Some examples of UEs 104 are illustrated in FIG. 1. A UE 104 may be capable of communicating with various types of devices, such as the network entities 102, other UEs 104, or network equipment (e.g., the core network 106, the packet data network 108, a relay device, an integrated access and backhaul (IAB) node, or another network equipment) , as shown in FIG. 1. Additionally, or alternatively, a UE 104 may support communication with other network entities 102 or UEs 104, which may act as relays in the wireless communications system 100.

A UE 104 may also be able to support wireless communication directly with other UEs 104 over a communication link 114. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link 114 may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

A network entity 102 may support communications with the core network 106, or with another network entity 102, or both. For example, a network entity 102 may interface with the core network 106 through one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The network entities 102 may communicate with each other over the backhaul links 116 (e.g., via an X2, Xn, or another network interface) . In some implementations, the network entities 102 may communicate with each other directly (e.g., between the network entities 102) . In some other implementations, the network entities 102 may communicate with each other or indirectly (e.g., via the core network 106) . In some implementations, one or more network entities 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC) . An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmission-reception points (TRPs) .

In some implementations, a network entity 102 may be configured in a disaggregated architecture, which may be configured to utilize a protocol stack physically or logically distributed among two or more network entities 102, such as an integrated access backhaul (IAB) network, an open radio access network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance) , or a virtualized RAN (vRAN) (e.g., a cloud RAN (C-RAN) ) . For example, a network entity 102 may include one or more of a CU, a DU, a radio unit (RU) , a RAN intelligent controller (RIC) (e.g., a near-real time RIC (Near-RT RIC) , a non-real time RIC (Non-RT RIC) ) , a service management and orchestration (SMO) system, or any combination thereof.

An RU may also be referred to as a radio head, a smart radio head, a remote radio head (RRH) , a remote radio unit (RRU) , or a transmission reception point (TRP) . One or more components of the network entities 102 in a disaggregated RAN architecture may be co-located, or one or more components of the network entities 102 may be located in distributed locations (e.g., separate physical locations) . In some implementations, one or more network entities 102 of a disaggregated RAN architecture may be implemented as virtual units (e.g., a virtual CU (VCU) , a virtual DU (VDU) , a virtual RU (VRU) ) .

Split of functionality between a CU, a DU, and an RU may be flexible and may support different functionalities depending upon which functions (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combinations thereof) are performed at a CU, a DU, or an RU. For example, a functional split of a protocol stack may be employed between a CU and a DU such that the CU may support one or more layers of the protocol stack and the DU may support one or more different layers of the protocol stack. In some implementations, the CU may host upper protocol layer (e.g., a layer 3 (L3) , a layer 2 (L2) ) functionality and signaling (e.g., radio resource control (RRC) , service data adaption protocol (SDAP) , packet data convergence protocol (PDCP) ) . The CU may be connected to one or more DUs or RUs, and the one or more DUs or RUs may host lower protocol layers, such as a layer 1 (L1) (e.g., physical (PHY) layer) or an L2 (e.g., radio link control (RLC) layer, medium access control (MAC) layer) functionality and signaling, and may each be at least partially controlled by the CU 160.

Additionally, or alternatively, a functional split of the protocol stack may be employed between a DU and an RU such that the DU may support one or more layers of the protocol stack and the RU may support one or more different layers of the protocol stack. The DU may support one or multiple different cells (e.g., via one or more RUs) . In some implementations, a functional split between a CU and a DU, or between a DU and an RU may be within a protocol layer (e.g., some functions for a protocol layer may be performed by one of a CU, a DU, or an RU, while other functions of the protocol layer are performed by a different one of the CU, the DU, or the RU) .

A CU may be functionally split further into CU control plane (CU-CP) and CU user plane (CU-UP) functions. A CU may be connected to one or more DUs via a midhaul communication link (e.g., F1, F1-c, F1-u) , and a DU may be connected to one or more RUs via a fronthaul communication link (e.g., open fronthaul (FH) interface) . In some implementations, a midhaul communication link or a fronthaul communication link may be implemented in accordance with an interface (e.g., a channel) between layers of a protocol stack supported by respective network entities 102 that are in communication via such communication links.

The core network 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The core network 106 may be an evolved packet core (EPC) , or a 5G core (5GC) , which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME) , an access and mobility management functions (AMF) ) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW) , a packet data network (PDN) gateway (P-GW) , or a user plane function (UPF) ) . In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc. ) for the one or more UEs 104 served by the one or more network entities 102 associated with the core network 106.

The core network 106 may communicate with the packet data network 108 over one or more backhaul links 116 (e.g., via an S1, N2, N2, or another network interface) . The packet data network 108 may include an application server 118. In some implementations, one or more UEs 104 may communicate with the application server 118. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the core network 106 via a network entity 102. The core network 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server 118 using the established session (e.g., the established PDU session) . The PDU session may be an example of a logical connection between the UE 104 and the core network 106 (e.g., one or more network functions of the core network 106) .

In the wireless communications system 100, the network entities 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers) ) to perform various operations (e.g., wireless communications) . In some implementations, the network entities 102 and the UEs 104 may support different resource structures. For example, the network entities 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the network entities 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the network entities 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures) . The network entities 102 and the UEs 104 may support various frame structures based on one or more numerologies.

One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., μ=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., μ=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., μ=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., μ=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., μ=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., μ=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames) . Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., μ=0, μ=1, μ=2, μ=3, μ=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) of symbols (e.g., OFDM symbols) . In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing) , a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., μ=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz –7.125 GHz) , FR2 (24.25 GHz –52.6 GHz) , FR3 (7.125 GHz –24.25 GHz) , FR4 (52.6 GHz –114.25 GHz) , FR4a or FR4-1 (52.6 GHz –71 GHz) , and FR5 (114.25 GHz –300 GHz) . In some implementations, the network entities 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the network entities 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., control information, data) . In some implementations, FR2 may be used by the network entities 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies) . For example, FR1 may be associated with a first numerology (e.g., μ=0) , which includes 15 kHz subcarrier spacing; a second numerology (e.g., μ=1) , which includes 30 kHz subcarrier spacing; and a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies) . For example, FR2 may be associated with a third numerology (e.g., μ=2) , which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., μ=3) , which includes 120 kHz subcarrier spacing.

FIG. 8 illustrates an example of signalling procedure 800 for PDCCH monitoring in accordance with aspects of the present disclosure.

As shown in FIG. 8, at step 802, a UE 104 transmits, to a base station 102, a CG PUSCH transmission.

The base station 102 may receive the CG PUSCH transmission at step 804 and transmit, to the UE 104, a PDCCH carrying a first DCI indicating whether the CG PUSCH transmission is correctly received by the base station at step 808 based on a transmitting time of a second DCI transmitted by the base station 102 if necessary.

For the UE 104, after the CG PUSCH transmission is transmitted at step 802, the UE 104 may monitor, at step 806, the PDCCH carrying the first DCI indicating whether the CG PUSCH transmission is correctly received, based on a receiving time of a second DCI from the base station 102. Herein, the first DCI may be a DCI scheduling PUSCH retransmission (which means that the CG PUSCH transmission is not correctly received, and needs to be retransmitted) , or a DCI carrying CG-DFI that provides HARQ-ACK information for a transport block of the PUSCH transmission. Furthermore, the second DCI may indicate the UE to skip PDCCH monitoring for a first duration, for example, the second DCI may be the DCI format providing the PDCCH monitoring adaptation field indicating to the UE to skip PDCCH monitoring for the first duration as mentioned before, and the first duration may be a duration in a set of durations indicated by PDCCHSkippingDurationList as mentioned before. The second DCI may be transmitted from the base station 102 and received by the UE 104 before the CG PUSCH transmission, however, for some reasons, sometimes the second DCI may be transmitted from the base station 102 and received by the UE 104 after the CG PUSCH transmission, the transmitting/monitoring of PDCCH based on the transmitting/receiving time of a second DCI will be described in details with reference to FIGS. 9A to 9D and FIGS. 10A to 10D.

FIGS. 9A to 9D illustrate examples of monitoring PDCCH in accordance with aspects of the present disclosure. In particular, FIGS. 9A to 9D illustrate examples of monitoring/transmitting PDCCH in the case that the second DCI 901 is transmitted from the base station 102 and received by the UE 104 before the CG PUSCH transmission 902. In this case, the UE 104 may skip PDCCH monitoring as indicated by the second DCI 901 after receiving the second DCI, and then, monitor PDCCH after the CG PUSCH transmission 902 is transmitted. While for the base station 102, the second DCI is transmitted by the base station 102 before the CG PUSCH transmission is received, and in this case, the base station 102 may not transmit PDCCH after transmitting the second DCI 901, and then, transmit PDCCH after the CG PUSCH transmission 902 is received.

In some example embodiments, the UE 104 may monitor, in the case that the CG PUSCH transmission 902 is transmitted before the end of the first duration, the PDCCH in a first monitoring mode after the CG PUSCH transmission 902 is transmitted. Accordingly, the base station 102 may transmit, in the case that the CG PUSCH transmission is received before the end of the first duration, the PDCCH in the first monitoring mode after the CG PUSCH transmission is received. Herein, the statement of the CG PUSCH transmission 902 being transmitted means that the last symbol of the CG PUSCH transmission 902 is transmitted. In the first monitoring mode, the duration for skipping the PDCCH monitoring and/or the timer (e.g. time 1 or timer 2) set for monitoring the PDCCH may be adjusted such that the PDCCH can be monitored.

In some example embodiments, in the first monitoring mode, for example, as shown in FIG. 9A, the UE may terminate the skipping of the PDCCH monitoring and monitor the PDCCH after the CG PUSCH transmission 902 is transmitted. For example, the UE 104 may terminate PDCCH skipping from the beginning of a first slot that is after a last symbol of the CG PUSCH transmission 902. In FIG. 9A, the skipping of the PDCCH monitoring is stopped and the UE may keep monitoring PDCCH after the CG PUSCH transmission 902 is transmitted. While for the base station 102, the base station 102 may transmit the PDCCH after the CG PUSCH transmission is received, for example, transmit the PDCCH from the beginning of a first slot that is after a last symbol of the CG PUSCH transmission 902.

In some example embodiments, in the first monitoring mode, the UE may terminate the skipping of the PDCCH monitoring in at least one preset search space (SS) set, and monitor the PDCCH in the at least one preset SS set in a first preset timer after the CG PUSCH transmission 902 is transmitted. That is to say, in the first monitoring mode, the base station 102 may transmit the PDCCH in the at least one preset SS set in the first preset timer after the CG PUSCH transmission 902 is received. The at least one preset SS set includes at least one of the following: at least one SS set configured for monitoring DFI (for manner (2) mentioned above) ; at least one SS set configured for monitoring a DCI format for scheduling CG PUSCH retransmission (for manner (1) mentioned above) ; at least one SS set indicated by the base station via radio resource control (RRC) signalling for monitoring PDCCH in the first duration; and at least one predefined SS set for monitoring PDCCH in the first duration. Since the UE only monitors PDCCH in preset SS set, the UE power waste will be improved.

In some example embodiments, in the first monitoring mode, for example, as shown in FIG. 9B, the UE may terminate the skipping of the PDCCH monitoring and monitor the PDCCH in a second preset timer (for example, the timer 1 or timer 2 as mentioned before ) after the CG PUSCH transmission 902 is transmitted. While for the base station 102, the base station 102 may transmit the PDCCH in the second preset timer after the CG PUSCH transmission 902 is received. The second preset timer may be the timer 1 or the time 2 as mention before, or may be any other preconfigured or predefined timer. In such case, if the end time of the first duration is later than the end time of the second preset timer, the UE may continue to skip the PDCCH monitoring in the first duration after the end of the second preset timer, and the base station 102 may stop transmitting the PDCCH in the first duration after the end of the second preset timer, as illustrated in FIG. 9B. In present disclosure, the term “end time” may refer to the last time unit or a ending time unit (such as the last/ending symbol, last/ending slot, last/ending subframe, and the like) , and “start time/beginning time” may refer to the first time unit or a beginning time unit (such as the first/beginning symbol, first/beginning slot, first /beginning subframe, and the like) . Since the UE could skip PDCCH monitoring after the timer, the UE power waste will be improved.

As an example, during the second preset timer runs, the first duration is still decreased, and after the end of the second preset timer, the UE may continue to skip the PDCCH monitoring and the base station 102 may stop transmitting the PDCCH for a remaining part of the first duration, the length of the remaining part is equal to a difference between a length of the first duration and a length of a duration from a beginning of the first duration to the end of the second preset timer. Alternatively, during the second preset timer runs, the first duration may be hold or paused (which means the first duration is not decreased) , and after the end of the second preset timer, the UE may continue to skip the PDCCH monitoring and the base station 102 may stop transmitting the PDCCH for a remaining part of the first duration, and the length of the remaining part is equal to a difference between a length of the first duration and a length of a duration from a beginning of the first duration to the beginning of the second preset timer. Since PDCCH skipping could be continued after the timer, the UE power waste will be improved.

In some example embodiments, in FIG. 9B, the UE may only terminate the skipping of the PDCCH monitoring and the base station 102 may only transmit the PDCCH in some preset SS sets as listed above.

In some example embodiments, in the first monitoring mode, for example, as shown in FIG. 9C, the UE may monitor the PDCCH in a third preset timer starting from the end of the first duration after the PUSCH transmission 902 is transmitted (for example starting from the first symbol after the first duration) , and the base station 102 may transmit the PDCCH in the third preset timer starting from the end of the first duration after the CG PUSCH transmission 902 is received. The third preset timer may be the timer 1 or timer 2 as mentioned before. As another example, as shown in FIG. 9D, the third preset timer may start after the CG PUSCH transmission is transmitted (for example start from the first symbol after CG PUSCH transmission) , stops in the first duration, and re-starts after the end of the first duration. In other words, in FIG. 9D, the third preset timer may be a timer obtained by extending the timer 1 or timer 2, and the extended value may configured or determined based on the first duration and the timer 1 or timer 2. For example, the extended value may be equal to a duration from the end of the CG PUSCH transmission to the end of the first duration. Since the first duration is not changed, the UE power waste will be improved.

In some example embodiments, if the UE 104 does not receive the second DCI before transmits the CG PUSCH transmission, the UE 104 may monitor the PDCCH in a fourth preset timer after the PUSCH transmission is transmitted, and the base station 102 may transmit the PDCCH in a fourth preset timer after the CG PUSCH transmission is received. After UE transmits the CG PUSCH transmission, UE does not expect to detect/receive the second DCI before the UE detects the first DCI. To this end, the base station 102 transmits the second DCI before it received the CG PUSCH transmission, and should not transmit the second DCI after it received the CG PUSCH transmission.

However, for some reasons, the base station 102 may transmit the second DCI after the CG PUSCH transmission is received, and the second DCI may be received by the UE 104 after the CG PUSCH transmission, the monitoring/transmitting of PDCCH in such situation is described in detail with reference to FIGS. 10A to 10D below.

FIGS. 10A to 10D illustrate examples of monitoring PDCCH in accordance with aspects of the present disclosure. In particular, FIGS. 10A to 10D illustrate examples of monitoring/transmitting PDCCH in the case that the second DCI 1001 is transmitted from the base station 102 and received by the UE 104 after the CG PUSCH transmission 1002 is transmitted. In this case, the UE 104 may monitor the PDCCH in a fourth preset timer after the CG PUSCH transmission1002 is transmitted and the base station 102 may transmit the PDCCH in the fourth preset timer after the CG PUSCH transmission1002 is received, and in the case that the second DCI 1001 is transmitted before the fourth preset timer expires, the UE 104 may monitor the PDCCH in a second monitoring mode different from the first monitoring mode after the second DCI 1001 is received, and the base station 102 may transmit the PDCCH in a second monitoring mode after the second DCI is transmitted. In the second monitoring mode, similar as the first monitoring mode, the duration for skipping the PDCCH monitoring and/or the timer (e.g. time 1 or timer 2) set for monitoring the PDCCH may be adjusted such that the PDCCH may be monitored.

As an example, as shown in FIG. 10A and FIG. 10B, in the second monitoring mode, the base station 102 may transmit the PDCCH until it transmits the first DCI to the UE 104 before the fourth preset timer expires, and stop transmitting the PDCCH for a second duration after the first DCI is transmitted, and the UE 104 may monitor the PDCCH until the first DCI (for example, a DCI carrying the DFI) is received from the base station 102 before the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the first DCI is received. In other word, when the first DCI is received by the UE 104, whether the CG PUSCH transmission is correctly received by the base station can be determined, and thus there is no need to continue to monitor the PDCCH. In such situation, the length of the second duration may be equal to a length of a first duration as indicated in the second DCI 1001, or may be equal to a part of the first duration remaining when the skipping of the PDCCH monitoring is started (that is, a part of the first duration remaining after the first DCI is received) . That is to say, the beginning of the first duration may be set differently in FIG. 10A (from the beginning of a first slot after the last symbol of the first DCI) and FIG. 10B (from the beginning of a first slot after the last symbol of the second DCI) , but the actual skipping of the PDCCH monitoring is only performed in a part of the first duration after the first DCI is received.

Alternatively, as another example, as shown in FIG. 10C and FIG. 10D, in the second monitoring mode, the base station 102 may transmit the PDCCH until the fourth preset timer expires, and stop transmitting the PDCCH for a second duration after the fourth preset timer expires, and accordingly, the UE 104 may monitor the PDCCH until the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the fourth preset timer expires. In such situation, the length of the second duration may be equal to a length of a first duration as indicated in the second DCI 1001, or may be equal to a part of the first duration remaining when the skipping of the PDCCH monitoring is started (that is, a part of the first duration remaining after the four preset timer expires) . That is to say, the beginning of the first duration indicated in the second DCI may be set differently in FIG. 10C (for example, after the end of the four preset timer) and FIG. 10D (from the beginning of a first slot after the last symbol of the second DCI) , but the actual skipping of the PDCCH monitoring is only performed in a part of the first duration after the four preset timer expires.

As another example, in the second monitoring mode, after the base station 102 transmits the second DCI, the base station 102 may stop transmitting the PDCCH for the first duration from the end of the second DCI (for example, from the beginning of a first slot after the last symbol of the second DCI) . Accordingly, when the second DCI is received by the UE 104, the UE 104 may skip the PDCCH monitoring for the first duration directly after the second DCI is received (for example, from the beginning of a first slot after the last symbol of the second DCI) . In such case, the UE 104 may assumes that the CG PUSCH transmission is correctly received by the base station 102 if the UE 104 receives the second DCI. Alternatively, the second DCI may include an information regarding whether the CG PUSCH transmission is correctly received by the base station, e.g., a new bit field may be set in the second DCI to indicate whether the CG PUSCH transmission is correctly received by the base station (e.g., the HARQ-ACK information for the CG PUSCH transmission) , and thus the UE 104 may know that whether the CG PUSCH transmission is correctly received by the base station and do not need to monitor PDCCH anymore. The new bit field may be designed to be the same as the DFI mentioned before.

FIG. 11 illustrates another example of signalling procedure 1100 of PDCCH monitoring in accordance with aspects of the present disclosure.

As shown in FIG. 11, at step 102, a UE 104 transmits, to a base station 102, a CG PUSCH transmission.

The base station 102 may receive the CG PUSCH transmission at step1104 and switch to a first preset search space set (SSS) group from a second preset SSS group to transmit a PDCCH carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station 102 after the CG PUSCH transmission is received at step 1108 if necessary.

For the UE 104, at step 1106, the UE 104 may switch to a first preset search space set (SSS) group from a second preset SSS group to monitor the PDCCH carrying the first DCI indicating whether the CG PUSCH transmission is correctly received. Herein, the first DCI may be a DCI scheduling the PUSCH retransmission (which means that the CG PUSCH transmission is not correctly received, and needs to be retransmitted) , or a DCI carrying CG-DFI that provides HARQ-ACK information for a transport block of the PUSCH transmission.

In some example implementations, the first preset SSS group and the second preset SSS group may be preconfigured by the base station or predefined. For example, they may include SS Set configured with more PDCCH monitoring occasions by the base station 102 to guarantee the first DCI could be transmitted as soon as possible, or could be configured by the base station or could be predefined as: e.g., SSS group 1 or SSS group 2. Furthermore, these preset SSS group may be preconfigured or predefined for different CG configurations. For example, if CG PUSCH transmission corresponds to CG configuration 1, then the UE could begin or switch to monitor PDCCH in a preset SSS group corresponding to the CG configuration 1; if CG PUSCH transmission correspond to CG configuration 2, then the UE could begin or switch to monitor PDCCH in a preset SSS group corresponding to the CG configuration 2, and so on.

For example, if the UE 104 is monitoring PDCCH in a SS group, and after the UE transmit a CG PUSCH transmission, the UE may start monitoring PDCCH according to a preset SSS group (e.g. SSS group 1) , and stops monitoring PDCCH according to another SSS group. And for example, from the beginning of the first slot that is at least P_switch symbols after the last symbol of the CG PUSCH transmission. In some example implementations, both the UE 104 and the base station 102 may set a fifth preset timer (e.g. timer 1 or timer 2) and the fifth preset timer is started after the switching to the preset SSS group, and when the fifth preset timer expires, the UE 104 may switch to another preset SSS group (e.g. SSS group 0) from the preset SSS group (e.g. SSS group 1) to monitor PDCCH, and also, the base station 102 may switch to the other preset SSS group (e.g. SSS group 0) to transmit PDCCH, such procedure will be described with reference to FIG. 12.

FIG. 12 illustrates an example of monitoring PDCCH in accordance with aspects of the present disclosure. In particular, FIG. 12 illustrates an example of monitoring PDCCH related to the process 1100 in accordance with aspects of the present disclosure.

As shown in the FIG. 12, after the CG PUSCH transmission 1201 is transmitted, the UE 104 may begin or switch to monitor the PDCCH in SSS group 1 in the fifth preset timer, and after the fifth preset timer expires, switch to SSS group 0. Also, after the CG PUSCH transmission 1201 is received, the base station 102 may begin or switch to transmit the PDCCH in SSS group 1 in the fifth preset timer, and after the fifth preset timer expires, switch to SSS group 0.

In some implementations, the way of monitoring/transmitting PDCCH as shown in FIG. 11 may be used in conjunction with those shown in FIGS. 8 to FIG. 10D. That is to say, when the UE 104 monitors PDCCH after the PUSCH transmission is transmitted as shown in FIGS. 8 to FIG. 10D, the UE 104 may switch to a preset SSS group and only monitor the PDCCH in the preset SSS group. And similarly, when the base station 102 transmits PDCCH after the PUSCH transmission is received as shown in FIGS. 8 to FIG. 10D, the base station 102 may switch to a preset SSS group and only transmit the PDCCH in the preset SSS group.

FIG. 13 illustrates an example of a device 1300 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The device 1300 may be an example of a UE 104 as described herein. The device 1300 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1300 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1302, a memory 1304, a transceiver 1306, and, optionally, an I/O controller 1308. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1302, the memory 1304, the transceiver 1306, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1302, the memory 1304, the transceiver 1306, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1302, the memory 1304, the transceiver 1306, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1302 and the memory 1304 coupled with the processor 1302 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1302, instructions stored in the memory 1304) .

For example, the processor 1302 may support wireless communication at the device 1300 in accordance with examples as disclosed herein. The processor 1302 may be configured to operable to support a means for transmitting, via the transceiver 1306 and to a base station 102, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for monitoring, via the transceiver1306 and from the base station 102, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

The processor 1302 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 602 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 602. The processor 602 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 604) to cause the device 600 to perform various functions of the present disclosure.

The memory 1304 may include random access memory (RAM) and read-only memory (ROM) . The memory 1304 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1302 cause the device 600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1302 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1304 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1308 may manage input and output signals for the device 1300. The I/O controller 1308 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1308 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1308 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1308 may be implemented as part of a processor, such as the processor 1306. In some implementations, a user may interact with the device 1300 via the I/O controller 1308 or via hardware components controlled by the I/O controller 608.

In some implementations, the device 1300 may include a single antenna 1310. However, in some other implementations, the device 1300 may have more than one antenna 1310 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1306 may communicate bi-directionally, via the one or more antennas 1310, wired, or wireless links as described herein. For example, the transceiver 1306 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1306 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1310 for transmission, and to demodulate packets received from the one or more antennas 1310. The transceiver 1306 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1310 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1310 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 14 illustrates an example of a device 1400 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The device 1400 may be an example of a UE 104 as described herein. The device 1400 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1400 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1402, a memory 1404, a transceiver 1406, and, optionally, an I/O controller 1408. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1402, the memory 1404, the transceiver 1406, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1402, the memory 1404, the transceiver 1406, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1402, the memory 1404, the transceiver 1406, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1402 and the memory 1404 coupled with the processor 1402 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1402, instructions stored in the memory 1404) .

For example, the processor 1402 may support wireless communication at the device 1400 in accordance with examples as disclosed herein. The processor 1402 may be configured to operable to support a means for transmitting, via the transceiver 1406 and to a base station 102, configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for switching to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.

The processor 1402 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1402 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1402. The processor 1402 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1404) to cause the device 1400 to perform various functions of the present disclosure.

The memory 1404 may include random access memory (RAM) and read-only memory (ROM) . The memory 1404 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1402 cause the device 1400 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1402 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1404 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1408 may manage input and output signals for the device 1400. The I/O controller 1408 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1408 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1408 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1408 may be implemented as part of a processor, such as the processor 1406. In some implementations, a user may interact with the device 1400 via the I/O controller 1408 or via hardware components controlled by the I/O controller 1408.

In some implementations, the device 1400 may include a single antenna 1410. However, in some other implementations, the device 1400 may have more than one antenna 1410 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1406 may communicate bi-directionally, via the one or more antennas 1410, wired, or wireless links as described herein. For example, the transceiver 1406 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1406 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1410 for transmission, and to demodulate packets received from the one or more antennas 1410. The transceiver 1406 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1410 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1410 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 15 illustrates an example of a device 1500 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The device 1500 may be an example of a base stations 102 as described herein. The device 1500 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1500 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1502, a memory 1504, a transceiver 1506, and, optionally, an I/O controller 1508. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1502, the memory 1504, the transceiver 1506, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1502, the memory 1504, the transceiver 1506, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1502, the memory 1504, the transceiver 1506, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1502 and the memory 1504 coupled with the processor 1502 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1502, instructions stored in the memory 1504) .

For example, the processor 1502 may support wireless communication at the device 1500 in accordance with examples as disclosed herein. The processor 1502 may be configured to operable to support a means for receiving, via the transceiver 1506 and from a UE 104, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for transmitting, via the transceiver 1506 and to the UE 104, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.

The processor 1502 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1502 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1502. The processor 1502 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1504) to cause the device 1500 to perform various functions of the present disclosure.

The memory 1504 may include random access memory (RAM) and read-only memory (ROM) . The memory 1504 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1502 cause the device 1500 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1502 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1504 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1508 may manage input and output signals for the device 1500. The I/O controller 1508 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1508 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1508 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1508 may be implemented as part of a processor, such as the processor 1506. In some implementations, a user may interact with the device 1500 via the I/O controller 1508 or via hardware components controlled by the I/O controller 1508.

In some implementations, the device 1500 may include a single antenna 1510. However, in some other implementations, the device 1500 may have more than one antenna 1510 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1506 may communicate bi-directionally, via the one or more antennas 1510, wired, or wireless links as described herein. For example, the transceiver 1506 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1506 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1510 for transmission, and to demodulate packets received from the one or more antennas 1510. The transceiver 1506 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1510 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1510 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 16 illustrates an example of a device 1600 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The device 1600 may be an example of a base stations 102 as described herein. The device 1600 may support wireless communication with one or more network entities 102, UEs 104, or any combination thereof. The device 1600 may include components for bi-directional communications including components for transmitting and receiving communications, such as a processor 1602, a memory 1604, a transceiver 1606, and, optionally, an I/O controller 1608. These components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1602, the memory 1604, the transceiver 1606, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. For example, the processor 1602, the memory 1604, the transceiver 1606, or various combinations or components thereof may support a method for performing one or more of the operations described herein.

In some implementations, the processor 1602, the memory 1604, the transceiver 1606, or various combinations or components thereof may be implemented in hardware (e.g., in communications management circuitry) . The hardware may include a processor, a digital signal processor (DSP) , an application-specific integrated circuit (ASIC) , a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, discrete hardware components, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure. In some implementations, the processor 1602 and the memory 1604 coupled with the processor 1602 may be configured to perform one or more of the functions described herein (e.g., executing, by the processor 1602, instructions stored in the memory 1604) .

For example, the processor 1602 may support wireless communication at the device 1600 in accordance with examples as disclosed herein. The processor 1602 may be configured to operable to support a means for receiving, via the transceiver 1606 and from a UE 104, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for switching to a first preset search space set (SSS) group from a second preset SSS group to transmit a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received.

The processor 1602 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, a microcontroller, an ASIC, an FPGA, a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof) . In some implementations, the processor 1602 may be configured to operate a memory array using a memory controller. In some other implementations, a memory controller may be integrated into the processor 1602. The processor 1602 may be configured to execute computer-readable instructions stored in a memory (e.g., the memory 1604) to cause the device 1600 to perform various functions of the present disclosure.

The memory 1604 may include random access memory (RAM) and read-only memory (ROM) . The memory 1604 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1602 cause the device 1600 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. In some implementations, the code may not be directly executable by the processor 1602 but may cause a computer (e.g., when compiled and executed) to perform functions described herein. In some implementations, the memory 1604 may include, among other things, a basic I/O system (BIOS) which may control basic hardware or software operation such as the interaction with peripheral components or devices.

The I/O controller 1608 may manage input and output signals for the device 1600. The I/O controller 1608 may also manage peripherals not integrated into the device M02. In some implementations, the I/O controller 1608 may represent a physical connection or port to an external peripheral. In some implementations, the I/O controller 1608 may utilize an operating system such as or another known operating system. In some implementations, the I/O controller 1608 may be implemented as part of a processor, such as the processor 1606. In some implementations, a user may interact with the device 1600 via the I/O controller 1608 or via hardware components controlled by the I/O controller 1608.

In some implementations, the device 1600 may include a single antenna 1610. However, in some other implementations, the device 1600 may have more than one antenna 1610 (i.e., multiple antennas) , including multiple antenna panels or antenna arrays, which may be capable of concurrently transmitting or receiving multiple wireless transmissions. The transceiver 1606 may communicate bi-directionally, via the one or more antennas 1610, wired, or wireless links as described herein. For example, the transceiver 1606 may represent a wireless transceiver and may communicate bi-directionally with another wireless transceiver. The transceiver 1606 may also include a modem to modulate the packets, to provide the modulated packets to one or more antennas 1610 for transmission, and to demodulate packets received from the one or more antennas 1610. The transceiver 1606 may include one or more transmit chains, one or more receive chains, or a combination thereof.

A transmit chain may be configured to generate and transmit signals (e.g., control information, data, packets) . The transmit chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM) , frequency modulation (FM) , or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM) . The transmit chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmit chain may also include one or more antennas 1610 for transmitting the amplified signal into the air or wireless medium.

A receive chain may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receive chain may include one or more antennas 1610 for receive the signal over the air or wireless medium. The receive chain may include at least one amplifier (e.g., a low-noise amplifier (LNA) ) configured to amplify the received signal. The receive chain may include at least one demodulator configured to demodulate the receive signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receive chain may include at least one decoder for decoding the processing the demodulated signal to receive the transmitted data.

FIG. 17 illustrates an example of a processor 1700 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The processor 1700 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1700 may include a controller 1702 configured to perform various operations in accordance with examples as described herein. The processor 1700 may optionally include at least one memory 1704, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1700 may optionally include one or more arithmetic-logic units (ALUs) 1700. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1700 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1700) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1702 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1700 to cause the processor 1700 to support various operations of a base station in accordance with examples as described herein. For example, the controller 1702 may operate as a control unit of the processor 1700, generating control signals that manage the operation of various components of the processor 1700. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1702 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1704 and determine subsequent instruction (s) to be executed to cause the processor 1700 to support various operations in accordance with examples as described herein. The controller 1702 may be configured to track memory address of instructions associated with the memory 1704. The controller 1702 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1702 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1700 to cause the processor 1700 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1702 may be configured to manage flow of data within the processor 1700. The controller 1702 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1700.

The memory 1704 may include one or more caches (e.g., memory local to or included in the processor 1700 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1704 may reside within or on a processor chipset (e.g., local to the processor 1700) . In some other implementations, the memory 1704 may reside external to the processor chipset (e.g., remote to the processor 1700) .

The memory 1704 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1700, cause the processor 1700 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1702 and/or the processor 1700 may be configured to execute computer-readable instructions stored in the memory 1704 to cause the processor 1700 to perform various functions. For example, the processor 1700 and/or the controller 1702 may be coupled with or to the memory 1704, and the processor 1700, the controller 1702, and the memory 1704 may be configured to perform various functions described herein. In some examples, the processor 1700 may include multiple processors and the memory 1704 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1700 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1700 may reside within or on a processor chipset (e.g., the processor 1700) . In some other implementations, the one or more ALUs 1700 may reside external to the processor chipset (e.g., the processor 1700) . One or more ALUs 1700 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1700 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1700 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1700 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1700 to handle conditional operations, comparisons, and bitwise operations.

The processor 1700 may support wireless communication in accordance with examples as disclosed herein. The processor 1700 may be configured to or operable to support a means for transmitting, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for monitoring, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, and the second DCI indicates the UE to skip PDCCH monitoring for a first duration.

FIG. 18 illustrates an example of a processor 1800 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The processor 1800 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1800 may include a controller 1802 configured to perform various operations in accordance with examples as described herein. The processor 1800 may optionally include at least one memory 1804, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1800 may optionally include one or more arithmetic-logic units (ALUs) 1800. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1800 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1800) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1802 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1800 to cause the processor 1800 to support various operations of a UE in accordance with examples as described herein. For example, the controller 1802 may operate as a control unit of the processor 1800, generating control signals that manage the operation of various components of the processor 1800. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1802 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1804 and determine subsequent instruction (s) to be executed to cause the processor 1800 to support various operations in accordance with examples as described herein. The controller 1802 may be configured to track memory address of instructions associated with the memory 1804. The controller 1802 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1802 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1800 to cause the processor 1800 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1802 may be configured to manage flow of data within the processor 1800. The controller 1802 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1800.

The memory 1804 may include one or more caches (e.g., memory local to or included in the processor 1800 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1804 may reside within or on a processor chipset (e.g., local to the processor 1800) . In some other implementations, the memory 1804 may reside external to the processor chipset (e.g., remote to the processor 1800) .

The memory 1804 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1800, cause the processor 1800 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1802 and/or the processor 1800 may be configured to execute computer-readable instructions stored in the memory 1804 to cause the processor 1800 to perform various functions. For example, the processor 1800 and/or the controller 1802 may be coupled with or to the memory 1804, and the processor 1800, the controller 1802, and the memory 1804 may be configured to perform various functions described herein. In some examples, the processor 1800 may include multiple processors and the memory 1804 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1800 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1800 may reside within or on a processor chipset (e.g., the processor 1800) . In some other implementations, the one or more ALUs 1800 may reside external to the processor chipset (e.g., the processor 1800) . One or more ALUs 1800 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1800 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1800 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1800 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1800 to handle conditional operations, comparisons, and bitwise operations.

The processor 1800 may support wireless communication in accordance with examples as disclosed herein. The processor 1800 may be configured to or operable to support means for transmitting, via a transceiver and to a base station, configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for switching to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.

FIG. 19 illustrates an example of a processor 1900 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The processor 1900 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1900 may include a controller 1902 configured to perform various operations in accordance with examples as described herein. The processor 1900 may optionally include at least one memory 1904, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 1900 may optionally include one or more arithmetic-logic units (ALUs) 1900. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 1900 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1900) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 1902 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1900 to cause the processor 1900 to support various operations of a UE in accordance with examples as described herein. For example, the controller 1902 may operate as a control unit of the processor 1900, generating control signals that manage the operation of various components of the processor 1900. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 1902 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1904 and determine subsequent instruction (s) to be executed to cause the processor 1900 to support various operations in accordance with examples as described herein. The controller 1902 may be configured to track memory address of instructions associated with the memory 1904. The controller 1902 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1902 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1900 to cause the processor 1900 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1902 may be configured to manage flow of data within the processor 1900. The controller 1902 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 1900.

The memory 1904 may include one or more caches (e.g., memory local to or included in the processor 1900 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 1904 may reside within or on a processor chipset (e.g., local to the processor 1900) . In some other implementations, the memory 1904 may reside external to the processor chipset (e.g., remote to the processor 1900) .

The memory 1904 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1900, cause the processor 1900 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 1902 and/or the processor 1900 may be configured to execute computer-readable instructions stored in the memory 1904 to cause the processor 1900 to perform various functions. For example, the processor 1900 and/or the controller 1902 may be coupled with or to the memory 1904, and the processor 1900, the controller 1902, and the memory 1904 may be configured to perform various functions described herein. In some examples, the processor 1900 may include multiple processors and the memory 1904 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 1900 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 1900 may reside within or on a processor chipset (e.g., the processor 1900) . In some other implementations, the one or more ALUs 1900 may reside external to the processor chipset (e.g., the processor 1900) . One or more ALUs 1900 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1900 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1900 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1900 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 1900 to handle conditional operations, comparisons, and bitwise operations.

The processor 1900 may support wireless communication in accordance with examples as disclosed herein. The processor 1900 may be configured to or operable to support means for receiving, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for transmitting, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.

FIG. 20 illustrates an example of a processor 2000 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The processor 2000 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 2000 may include a controller 2002 configured to perform various operations in accordance with examples as described herein. The processor 2000 may optionally include at least one memory 2004, such as L1/L2/L3 cache. Additionally, or alternatively, the processor 2000 may optionally include one or more arithmetic-logic units (ALUs) 2000. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses) .

The processor 2000 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 2000) or other memory (e.g., random access memory (RAM) , read-only memory (ROM) , dynamic RAM (DRAM) , synchronous dynamic RAM (SDRAM) , static RAM (SRAM) , ferroelectric RAM (FeRAM) , magnetic RAM (MRAM) , resistive RAM (RRAM) , flash memory, phase change memory (PCM) , and others) .

The controller 2002 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 2000 to cause the processor 2000 to support various operations of a UE in accordance with examples as described herein. For example, the controller 2002 may operate as a control unit of the processor 2000, generating control signals that manage the operation of various components of the processor 2000. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

The controller 2002 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 2004 and determine subsequent instruction (s) to be executed to cause the processor 2000 to support various operations in accordance with examples as described herein. The controller 2002 may be configured to track memory address of instructions associated with the memory 2004. The controller 2002 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 2002 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 2000 to cause the processor 2000 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 2002 may be configured to manage flow of data within the processor 2000. The controller 2002 may be configured to control transfer of data between registers, arithmetic logic units (ALUs) , and other functional units of the processor 2000.

The memory 2004 may include one or more caches (e.g., memory local to or included in the processor 2000 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementation, the memory 2004 may reside within or on a processor chipset (e.g., local to the processor 2000) . In some other implementations, the memory 2004 may reside external to the processor chipset (e.g., remote to the processor 2000) .

The memory 2004 may store computer-readable, computer-executable code including instructions that, when executed by the processor 2000, cause the processor 2000 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such as system memory or another type of memory. The controller 2002 and/or the processor 2000 may be configured to execute computer-readable instructions stored in the memory 2004 to cause the processor 2000 to perform various functions. For example, the processor 2000 and/or the controller 2002 may be coupled with or to the memory 2004, and the processor 2000, the controller 2002, and the memory 2004 may be configured to perform various functions described herein. In some examples, the processor 2000 may include multiple processors and the memory 2004 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

The one or more ALUs 2000 may be configured to support various operations in accordance with examples as described herein. In some implementation, the one or more ALUs 2000 may reside within or on a processor chipset (e.g., the processor 2000) . In some other implementations, the one or more ALUs 2000 may reside external to the processor chipset (e.g., the processor 2000) . One or more ALUs 2000 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 2000 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 2000 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 2000 may support logical operations such as AND, OR, exclusive-OR (XOR) , not-OR (NOR) , and not-AND (NAND) , enabling the one or more ALUs 2000 to handle conditional operations, comparisons, and bitwise operations.

The processor 2000 may support wireless communication in accordance with examples as disclosed herein. The processor 2000 may be configured to or operable to support means for receiving, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and means for switching to a first preset search space set (SSS) group from a second preset SSS group to transmit a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received.

FIG. 21 illustrates a flowchart of a method 2100 that supports the PDCCH monitoring in accordance with aspects of the present disclosure. The operations of the method 2100 may be implemented by a device or its components as described herein. For example, the operations of the method 2100 may be performed by the UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 2105, the method may include transmitting, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission. The operations of 2105 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2105 may be performed by a device as described with reference to FIG. 1.

At 2110, the method may include monitoring, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, the second DCI indicates the UE to skip PDCCH monitoring for a first duration. The operations of 2110 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2110 may be performed by a device as described with reference to FIG. 1.

FIG. 22 illustrates a flowchart of a method 2200 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The operations of the method 2200 may be implemented by a device or its components as described herein. For example, the operations of the method 2200 may be performed by the UE 104 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 2205, the method may include transmitting, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission. The operations of 2205 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2205 may be performed by a device as described with reference to FIG. 1.

At 2210, the method may include switching to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted. The operations of 2210 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2210 may be performed by a device as described with reference to FIG. 1.

It should be noted that the methods described herein describes possible implementations, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible. Further, aspects from two or more of the methods may be combined.

FIG. 23 illustrates a flowchart of a method 2300 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The operations of the method 2300 may be implemented by a device or its components as described herein. For example, the operations of the method 2300 may be performed by a base stations 102 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 2305, the method may include receiving, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission. The operations of 2305 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2305 may be performed by a device as described with reference to FIG. 1.

At 2310, the method may include transmitting, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration. The operations of 2310 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2310 may be performed by a device as described with reference to FIG. 1.

FIG. 24 illustrates a flowchart of a method 2400 that supports PDCCH monitoring in accordance with aspects of the present disclosure. The operations of the method 2400 may be implemented by a device or its components as described herein. For example, the operations of the method 2400 may be performed by a base stations 102 as described herein. In some implementations, the device may execute a set of instructions to control the function elements of the device to perform the described functions. Additionally, or alternatively, the device may perform aspects of the described functions using special-purpose hardware.

At 2405, the method may include receiving, via a transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission. The operations of 2405 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2405 may be performed by a device as described with reference to FIG. 1.

At 2410, the method may include switching to a first preset search space set (SSS) group from a second preset SSS group to transmit a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is received. The operations of 2410 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 2410 may be performed by a device as described with reference to FIG. 1.

The various illustrative blocks and components described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a DSP, an ASIC, a CPU, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions may also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer. By way of example, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM) , flash memory, compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

As used herein, including in the claims, an article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a, ” “at least one, ” “one or more, ” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of” ) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C) . Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on. Further, as used herein, including in the claims, a “set” may include one or more elements.

The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

A user equipment (UE) , comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

transmit, via the transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and

monitor, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, wherein the second DCI indicates the UE to skip PDCCH monitoring for a first duration.
The UE of claim 1, wherein in the case that the second DCI is received by the UE before the CG PUSCH transmission, the processor is configured to:

monitor, in the case that the CG PUSCH transmission is transmitted before the end of the first duration, the PDCCH in a first monitoring mode after the CG PUSCH transmission is transmitted.
The UE of claim 2, wherein in the first monitoring mode, the processor is configured to terminate the skipping of the PDCCH monitoring and monitor the PDCCH after the CG PUSCH transmission is transmitted.
The UE of claim 2, wherein in the first monitoring mode, the processor is configured to terminate the skipping of the PDCCH monitoring in at least one preset search space (SS) set, and monitor the PDCCH in the at least one preset SS set in a first preset timer after the CG PUSCH transmission is transmitted.
The UE of claim 4, wherein the at least one preset SS set includes at least one of the following:

at least one SS set configured for monitoring a downlink feedback information (DFI) ;

at least one SS set configured for monitoring a DCI format for CG retransmission scheduling;

at least one SS set indicated by the base station via radio resource control (RRC) signalling for monitoring PDCCH in the first duration; and

at least one predefined SS set for monitoring PDCCH in the first duration.
The UE of claim 2, wherein in the first monitoring mode, the processor is configured to terminate the skipping of the PDCCH monitoring and monitor the PDCCH in a second preset timer after the CG PUSCH transmission is transmitted.
The UE of claim 6, wherein the processor is further configured to:

in the case that an end time of the first duration is later than an end time of the second preset timer, continue to skip the PDCCH monitoring in the first duration after the end of the second preset timer.
The UE of claim 2, wherein in the first monitoring mode, the processor is configured to monitor the PDCCH in a third preset timer starting from the end of the first duration after the CG PUSCH transmission is transmitted.
The UE of claim 2, wherein in the first monitoring mode, the processor is configured to monitor the PDCCH in a third preset timer, the third preset timer starts after the CG PUSCH transmission is transmitted, stops in the first duration, and re-starts after the end of the first duration.
The UE of claim 1, wherein the processor is configured to monitor the PDCCH in a fourth preset timer after the CG PUSCH transmission is transmitted, and in the case that the second DCI is received before the fourth preset timer expires, the processor is configured to:

monitor the PDCCH in a second monitoring mode after the second DCI is received.
The UE of claim 10, wherein in the second monitoring mode, the processor is configured to skip the PDCCH monitoring for the first duration from the end of the second DCI.
The UE of claim 11, wherein the second DCI further includes an information regarding whether the CG PUSCH transmission is correctly received by the base station.
The UE of claim 10, wherein in the second monitoring mode, the processor is configured to monitor the PDCCH until the first DCI is received from the base station before the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the first DCI is received.
The UE of claim 10, wherein in the second monitoring mode, the processor is configured to monitor the PDCCH until the fourth preset timer expires, and skip the PDCCH monitoring for a second duration after the fourth preset timer expires.
The UE of claim 1, wherein the processor is configured to monitor the PDCCH by further switching to a first preset search space set (SSS) group from a second preset SSS group after the CG PUSCH transmission is transmitted.
The UE of claim 15, wherein the first preset SSS group and the second preset SSS group are preconfigured by the base station or predefined.
The UE of claim 15, wherein a fifth preset timer is started after the switching to the first preset SSS group from the second preset SSS group, and the processor is further configured to: switch to the second preset SSS group from the first preset SSS group to monitor the PDCCH after the fifth preset timer expires.
A base station, comprising:

a processor; and

a transceiver coupled to the processor,

wherein the processor is configured to:

receive, via the transceiver and from a user equipment (UE) , a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and

transmit, via the transceiver and to the UE, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a transmitting time of a second DCI transmitted by the base station, wherein the second DCI indicates the UE to skip the PDCCH monitoring for a first duration.
A method performed by a user equipment (UE) , the method comprising:

transmitting, via a transceiver and to a base station, a configured grant (CG) physical uplink shared channel (PUSCH) transmission; and

monitoring, via the transceiver and from the base station, a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station, based on a receiving time of a second DCI from the base station, whereinthe second DCI indicates the UE to skip PDCCH monitoring for a first duration.
A method performed by a user equipment (UE) , the method comprising:

transmitting, via a transceiver and to a base station, configured grant (CG) physical uplink shared channel (PUSCH) transmission;

switching to a first preset search space set (SSS) group from a second preset SSS group to monitor a physical downlink control channel (PDCCH) carrying a first downlink control information (DCI) indicating whether the CG PUSCH transmission is correctly received by the base station after the CG PUSCH transmission is transmitted.