WO2024150742A1 - Display device and electronic apparatus - Google Patents

Display device and electronic apparatus Download PDF

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Publication number
WO2024150742A1
WO2024150742A1 PCT/JP2024/000190 JP2024000190W WO2024150742A1 WO 2024150742 A1 WO2024150742 A1 WO 2024150742A1 JP 2024000190 W JP2024000190 W JP 2024000190W WO 2024150742 A1 WO2024150742 A1 WO 2024150742A1
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Prior art keywords
transistor
display device
semiconductor substrate
pixel
light
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PCT/JP2024/000190
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French (fr)
Japanese (ja)
Inventor
寛 西川
昌志 内田
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2024150742A1 publication Critical patent/WO2024150742A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates

Definitions

  • This disclosure relates to display devices and electronic devices.
  • Such display devices have multiple light-emitting elements, each configured with, for example, a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer.
  • the display devices also have a drive circuit for driving the light-emitting elements.
  • a display device is the display device disclosed in Patent Document 1 below.
  • display devices are required to reduce the layout size of the drive circuits while taking into consideration the withstand voltage and characteristics required of the various transistors included in the drive circuits. Furthermore, even when light-emitting elements are miniaturized and the number of pixels is increased, display devices are required to further reduce power consumption during standby.
  • This disclosure therefore proposes a display device and electronic device that can reduce the layout size of the drive circuit and reduce power consumption during standby while satisfying the required characteristics for the transistors included in the drive circuit.
  • a display device comprising a plurality of pixels arranged two-dimensionally in a matrix on a semiconductor substrate, each of the pixels having a light-emitting element whose luminance changes in response to a current supplied thereto, and a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light-emitting element, the first transistor having a first channel formation region in the semiconductor substrate, and the second transistor having a first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate, and a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate and in contact with the first gate electrode via an insulating film.
  • an electronic device equipped with a display device, the display device comprising a plurality of pixels arranged two-dimensionally in a matrix on a semiconductor substrate, each of the pixels comprising a light-emitting element whose luminance changes in response to a current supplied thereto, and a plurality of transistors including at least a first transistor and a second transistor, electrically connected to the light-emitting element, the first transistor comprising a first channel-forming region in the semiconductor substrate, the second transistor comprising a first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate, and a second channel-forming region in an oxide semiconductor layer stacked above the semiconductor substrate and in contact with the first gate electrode via an insulating film.
  • FIG. 1 is a schematic diagram illustrating an example of an overall configuration of a display device according to an embodiment of the present disclosure.
  • 1 is a circuit diagram illustrating an example of a pixel of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a comparative example.
  • FIG. 2 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to the first embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram showing an example of a planar configuration of a pixel according to the first embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the first embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the first embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a second embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the second embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the second embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the second embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram showing an example of a planar configuration of a pixel according to a third embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fourth embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fifth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a sixth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a sixth embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view (part 1) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure.
  • FIG. 23 is a cross-sectional view (part 2) for explaining a pixel manufacturing method according to the seventh embodiment of the present disclosure.
  • FIG. 23 is a cross-sectional view (part 3) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view (part 4) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram showing an example of a cross-sectional configuration of a main part of a pixel according to an eighth embodiment of the present disclosure.
  • FIG. FIG. 23 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to an eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 4) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fifth modified example of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 1) illustrating an example of a planar configuration of a pixel according to a sixth modified example of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 2) showing an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 3) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 4) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure.
  • FIG. 23 is a schematic diagram (part 5) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view (part 1) for explaining a pixel manufacturing method according to an eighth embodiment of the present disclosure.
  • FIG. 23 is a cross-sectional view (part 2) for explaining a manufacturing method of a pixel according to an eighth embodiment of the present disclosure.
  • FIG. 1 is a front view showing an example of the appearance of a digital still camera.
  • FIG. 2 is a rear view showing an example of the appearance of a digital still camera.
  • FIG. 1 is an external view of a head mounted display.
  • FIG. 1 is an external view of a see-through head-mounted display.
  • FIG. 1 is an external view of a television device.
  • FIG. 1 is an external view of a smartphone.
  • FIG. 1 is a diagram showing the internal structure of a vehicle.
  • FIG. 2 is a diagram showing the internal structure of a vehicle (part 2).
  • circuits electrical connections
  • electrically connected means connecting multiple elements so that electricity (signals) is conducted between them.
  • electrically connected includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.
  • sharing refers to mutual use of one other element (e.g., a diffusion region) between different elements (e.g., transistors, etc.).
  • Fig. 1 is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure.
  • the display device 10 is a device in which light-emitting elements such as OLEDs (Organic Light Emitting Diodes) or Micro-OLEDs are formed in an array.
  • a display device 10 can be used, for example, as a display device for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), an electronic viewfinder (EVF), or a small projector.
  • the light-emitting element may be a self-luminous element and a current-driven electro-optical element.
  • examples of current-driven electro-optical elements include inorganic EL elements, LED elements, and semiconductor laser elements.
  • an organic EL display device using OLEDs as the light-emitting elements has the following features.
  • OLEDs are self-luminous elements
  • the organic EL display device has higher image visibility than a liquid crystal display device, which is also a flat display device, and can be easily made lighter and thinner because it does not require lighting components such as a backlight.
  • the response speed of OLEDs is very fast, on the order of several microseconds, the organic EL display device does not produce afterimages when displaying moving images.
  • an active matrix organic EL display device that uses, as a light emitting element, an OLED, which is a current-driven light emitting element whose light emission brightness changes according to the value of the current flowing through the device.
  • an “active matrix organic EL display device” will be simply referred to as a "display device.”
  • the display device 10 has a pixel array section 30 in which a plurality of pixels 20, each including a light-emitting element, are two-dimensionally arranged in a matrix on a semiconductor substrate (not shown), and a drive circuit section arranged around the pixel array section 30.
  • the drive circuit section includes, for example, a write scan section 40, a first drive scan section 50, a second drive scan section 60, and a signal output section 70 mounted on the same display panel 80 as the pixel array section 30, and drives each pixel 20 of the pixel array section 30.
  • one pixel which is a unit for forming a color image is composed of multiple sub-pixels.
  • each of the sub-pixels corresponds to the pixel 20 in FIG. 1.
  • one pixel 20 may be composed of three sub-pixels, for example, a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light, and may be composed of one, two, or more sub-pixels, and is not particularly limited.
  • one pixel 20 is not limited to a combination of sub-pixels of the three primary colors, for example, red, green, and blue, and one pixel 20 may be composed by adding sub-pixels of one or more colors to the sub-pixels of the three primary colors. More specifically, the display device 10 can be configured to configure one pixel 20 by adding a sub-pixel that emits white light to improve brightness, or by adding at least one sub-pixel that emits complementary color light to expand the color reproduction range.
  • scanning lines 31 (31 1 to 31 m ) and drive lines 32 (32 1 to 32 m ) are wired for each pixel row along the row direction (arrangement direction of the pixels 20 in the pixel row/horizontal direction) for the arrangement of the pixels 20 in m rows and n columns.
  • signal lines 34 ( 34 1 to 34 n ) are wired for each pixel column along the column direction (arrangement direction of the pixels 20 in the pixel column/vertical direction) for the arrangement of the pixels 20 in m rows and n columns.
  • the scanning lines 31 1 to 31 m are each electrically connected to an output terminal of a corresponding row of the write scanning section 40.
  • the driving lines 32 1 to 32 m are each electrically connected to an output terminal of a corresponding row of the driving scanning section 50.
  • the signal lines 34 1 to 34 n are each electrically connected to an output terminal of a corresponding column of the signal output section 70.
  • the write scanning section 40 is configured with a shift register circuit etc. When writing a signal voltage of a video signal to each pixel 20 of the pixel array section 30, the write scanning section 40 sequentially supplies write scanning signals WS (WS 1 to WS m ) to the scanning lines 31 (31 1 to 31 m ) to sequentially scan each pixel 20 of the pixel array section 30 in row units.
  • the first drive scanning section 50 is configured with a shift register circuit and the like, similar to the write scanning section 40.
  • This drive scanning section 50 can control the emission/non-emission (extinction) of the pixels 20 by supplying light emission control signals DS (DS 1 to DS m ) to the drive lines 32 (32 1 to 32 m ) in synchronization with the line sequential scanning by the write scanning section 40.
  • the signal output unit 70 selectively outputs a signal voltage (hereinafter simply referred to as "signal voltage") Vsig of a video signal corresponding to luminance information supplied from a signal supply source (not shown) and a reference voltage Vofs.
  • the reference voltage Vofs is a voltage equivalent to the reference voltage of the signal voltage Vsig of the video signal, or a voltage close to it.
  • the signal voltage Vsig/reference voltage Vofs alternatively output from the signal output unit 70 is written to each pixel 20 of the pixel array unit 30 via signal lines 34 (34 1 to 34 n ) in units of pixel rows selected by line-sequential scanning by the write scanning unit 40. That is, the signal output unit 70 can write the signal voltage Vsig in units of pixel rows (lines).
  • the display device 10 by switching off the driving transistor Tr1 (see FIG. 2 ) included in the pixel 20 described later, the current supply to the light-emitting element EL (see FIG. 2 ) included in the pixel 20 is cut off, and as a result, the light emission of the light-emitting element EL is suppressed, so that the black gradation can be displayed.
  • the driving transistor Tr1 when the driving transistor Tr1 is switched to the off state, a current leaks between the source and drain of the driving transistor Tr1, which may reduce the contrast when displaying the black gradation.
  • the driving section of the display device 10 has a second driving scanning section 60, and further, second driving lines 33 (33 1 to 33 m ) are wired for each pixel row along the row direction.
  • the second driving lines 33 1 to 33 m are respectively connected to the output terminals of the corresponding rows of the second driving scanning section 60.
  • the second drive scanning section 60 is configured with a shift register circuit and the like, similar to the write scanning section 40.
  • This second drive scanning section 60 supplies drive signals AZ (AZ 1 to AZ m ) to the second drive lines 33 (33 1 to 33 m ) in synchronization with the line sequential scanning by the write scanning section 40, thereby controlling the pixels 20 not to emit light during the non-light emitting period.
  • FIG. 1 is an example of the configuration of the display device 10 according to the embodiment of the present disclosure, and the path configuration of the display device 10 according to the embodiment of the present disclosure is not limited to the configuration shown in FIG. 1.
  • Fig. 2 is a circuit diagram showing an example of the pixel 20 of the display device 10 according to the embodiment of the present disclosure.
  • a pixel 20 is composed of a light-emitting element EL and a drive circuit that drives the light-emitting element EL.
  • the light-emitting element EL is an example of a current-driven electro-optical element whose light emission luminance changes according to the value of the current flowing through the device, and is, for example, an OLED.
  • the cathode of the light-emitting element EL is electrically connected to, for example, a node Vss for outputting a current.
  • the drive circuit is composed of multiple transistors (drive transistor Tr1, write transistor Tr2, light emission control transistor Tr3, switching transistor Tr4) electrically connected to the light emitting element EL, and capacitance units C1 and C2.
  • the anode of the light emitting element EL is electrically connected to the drive transistor Tr1, and when a current flows through the drive transistor Tr1, the light emitting element EL can emit light.
  • the driving transistor (also called a light-emitting transistor) (first transistor) Tr1 and the writing transistor (also called a data writing control transistor) (fourth transistor) Tr2 are, for example, field effect transistors (FETs). More specifically, the driving transistor Tr1 is a P-channel transistor, and the writing transistor Tr2 is an N-channel transistor.
  • the light-emitting control transistor (also called a power supply control transistor) Tr3 (third transistor) and the switching transistor (also called a light-extinction control transistor) (second transistor) Tr4 are, for example, field effect transistors. More specifically, the light-emitting control transistor Tr3 is a P-channel transistor, and the switching transistor Tr4 is an N-channel transistor.
  • the source and drain of the driving transistor Tr1 are electrically connected to a power supply node (current source) of the power supply voltage V DD and an anode electrode of the light-emitting element EL via the drain of the light-emitting control transistor Tr3 described later.
  • the source and drain of the writing transistor Tr2 are electrically connected to a signal line (Vsig) and the gate of the driving transistor Tr1, respectively, and the gate of the writing transistor Tr2 is electrically connected to a scanning line (WS).
  • the light-emitting control transistor Tr3 is electrically connected between the power supply node of the power supply voltage V DD and the source of the driving transistor Tr1.
  • the switching transistor Tr4 is electrically connected between the drain of the driving transistor Tr1 and a current drain node Vss.
  • the driving transistor Tr1 can drive the light-emitting element EL by supplying a driving current to the light-emitting element EL that corresponds to the holding voltage (signal voltage) of the capacitance section C1, which will be described later.
  • the write transistor Tr2 can write to the gate of the drive transistor Tr1 by sampling the signal voltage Vsig supplied from the signal output unit 70.
  • write here means that a signal voltage is applied to the gate node, and the potential of the gate node is held at a potential based on the signal voltage.
  • the light emission control transistor Tr3 controls whether the light emitting element EL emits light or not when driven by the light emission control signal DS.
  • the switching transistor Tr4 under the drive signal AZ, controls the light-emitting element EL so that it does not emit light during the non-light-emitting period of the light-emitting element EL. That is, the switching transistor Tr4 becomes conductive, and serves to form a path that detours (i.e., bypasses) the light-emitting element EL so that no current is supplied to the light-emitting element EL. In this way, even if a current leaks between the source and drain of the driving transistor Tr1 when the driving transistor Tr1 is switched to the off state, the switching transistor Tr4 becomes conductive, and therefore no current is supplied to the light-emitting element EL. As a result, with this configuration, it is possible to suppress a decrease in contrast when displaying black gradations.
  • the capacitance unit C1 is connected between the gate and source of the drive transistor Tr1 and holds the signal voltage Vsig written by sampling by the write transistor Tr2.
  • the drive transistor Tr1 drives the light-emitting element EL by passing a drive current corresponding to the voltage held by the capacitance unit C1 through the light-emitting element EL.
  • the capacitance unit C2 is connected between the source of the driving transistor Tr1 and a node of a fixed potential (for example, a power supply node of the power supply voltage V DD ).
  • the capacitance unit C2 suppresses fluctuations in the source voltage of the driving transistor Tr1 when the signal voltage Vsig is written, and has the effect of setting the gate-source voltage Vgs of the driving transistor Tr1 to the threshold voltage Vth of the driving transistor Tr1.
  • circuit configuration example shown in FIG. 2 is an example of the circuit configuration of the pixel 20 of this embodiment, and the circuit configuration of the pixel 20 of this embodiment is not limited to the circuit configuration shown in FIG. 2.
  • FIG. 3 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20a according to a comparative example. Note that the comparative example here refers to the pixel 20a that the present inventors had been studying extensively before creating the embodiment of the present disclosure.
  • the inventor has previously considered the configuration of pixel 20a as shown in FIG. 3.
  • multiple transistors included in the drive circuit of pixel 20a such as drive transistor Tr1 are provided on a semiconductor substrate 100.
  • these multiple transistors have channel formation regions within the semiconductor substrate 100.
  • a light-emitting element EL is provided above these transistors.
  • the multiple transistors have gate electrodes 102 provided via an insulating film 202 on a region having n-type conductivity that functions as a channel provided in the semiconductor substrate 100. Furthermore, these transistors have source/drains formed of diffusion regions 104 containing impurities having p-type conductivity provided in the semiconductor substrate 100 on either side of the channel region. Furthermore, these transistors are isolated from other elements by element isolation portions (Shallow Trench Isolation: STI) 106 provided in the semiconductor substrate 100.
  • element isolation portions Shallow Trench Isolation: STI
  • a wiring layer 200 is provided on the semiconductor substrate 100 on which a plurality of transistors are provided.
  • the wiring layer 200 includes an insulating film 202, wiring 204, and vias 206.
  • a light-emitting portion 300 which is a light-emitting element EL, is provided on the wiring layer 200.
  • the light-emitting element EL has an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 that emits light and is stacked on the anode electrode 310, and a cathode electrode 312 that is stacked on the light-emitting layer 314 and transmits light from the light-emitting layer 314.
  • the layout size of the drive circuit taking into consideration the withstand voltage and characteristics required of various transistors in the drive circuit of pixel 20a.
  • the layout size of the drive circuit it is possible to reduce the size of the elements such as the source and drain that constitute each transistor.
  • the area of the source and drain becomes smaller, and therefore the contacts that electrically connect to them also become smaller, making it easier for misalignment to occur between the source and drain and the contacts during mass production.
  • the embodiment of the present disclosure created by the present inventors can reduce the layout size of the drive circuit and reduce power consumption during standby while still satisfying the required characteristics for the transistors included in the drive circuit.
  • Figure 4A is a schematic diagram showing an example of a cross-sectional configuration of the pixel 20 according to the first embodiment of the present disclosure, and corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side.
  • Figure 4B is a schematic diagram showing an example of a planar configuration of the pixel 20 according to the first embodiment of the present disclosure, and corresponds to a cross section when the pixel 20 is cut along the line A-A' shown in Figure 4A. Note that the pixel 20 having the configuration shown in Figures 4A and 4B has the circuit configuration shown in Figure 2 described above.
  • the pixel 20 has a laminated structure including a semiconductor substrate 100 made of silicon having an n-type conductivity, a wiring layer 200 laminated on the semiconductor substrate 100, and a light-emitting element EL provided on the wiring layer 200.
  • the light-emitting element EL is a current-driven electro-optical element whose light emission luminance changes according to the current value flowing through the device.
  • the semiconductor substrate 100 and the wiring layer 200 include a driving circuit for driving the light-emitting element EL.
  • the wiring layer 200 includes, in addition to the elements described below, an insulating film 202 (formed, for example, of a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 )), a wiring 204 (formed, for example, of a metal film such as tungsten (W)), and a via 206 (formed, for example, of a metal film such as tungsten).
  • an insulating film 202 formed, for example, of a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 )
  • a wiring 204 formed, for example, of a metal film such as tungsten (W)
  • a via 206 formed, for example, of a metal film such as tungsten.
  • the drive circuit includes a drive transistor Tr1 (labeled “Drv” in FIG. 4A), a write transistor Tr2 (labeled “WS” in FIG. 4A), a light-emission control transistor Tr3 (labeled “DS” in FIG. 4A), a switching transistor Tr4 (labeled "AZ” in FIG. 4A), and capacitance units C1 and C2.
  • Tr1 drive transistor
  • Tr2 write transistor
  • Tr3 light-emission control transistor
  • Tr4 labeleled "AZ” in FIG. 4A
  • capacitance units C1 and C2 are not shown in FIG. 4A.
  • the driving transistor Tr1 is a field effect transistor provided on the semiconductor substrate 100, and more specifically, a P-channel transistor.
  • the driving transistor Tr1 has a gate electrode 102 provided via an insulating film 202 on a region (first channel formation region) having n-type conductivity that functions as a channel of the driving transistor Tr1 provided in the semiconductor substrate 100.
  • the driving transistor Tr1 has a source/drain formed of a diffusion region 104 containing an impurity having p-type conductivity provided in the semiconductor substrate 100 so as to sandwich the channel formation region.
  • the driving transistor Tr1 by providing the driving transistor Tr1 on the semiconductor substrate 100, the characteristics of the driving transistor Tr1 can be stabilized and the driving transistor Tr1 can be made a high-voltage transistor.
  • the driving transistor Tr1 may be an N-channel transistor.
  • the source and drain of the driving transistor Tr1 are electrically connected to a wiring 204 connected to a power supply (V DD ) provided in the wiring layer 200 and to an anode electrode 310 of the light-emitting element EL by vias 206 that penetrate the wiring layer 200. Furthermore, the gate electrode 102 of the driving transistor Tr1 is electrically connected to an electrode (not shown) of a capacitance section C1 (described later) and the source or drain of the writing transistor Tr2 by the vias 206.
  • the capacitance unit C1 may also be provided in the wiring layer 200 stacked above the drive transistor Tr1.
  • one electrode (not shown) of the capacitance unit C1 may be electrically connected to the source or drain of the drive transistor Tr1 described above through a via 206.
  • the other electrode (not shown) of the capacitance unit C1 may also be electrically connected to the source or drain of the drive transistor Tr1 described above and the source or drain of the write transistor Tr2 described below through a via 206.
  • the driving transistor Tr1 is isolated from other elements by an element isolation section 106 provided in the semiconductor substrate 100.
  • the source or drain of the drive transistor Tr1 shares a diffusion region 104 provided in the semiconductor substrate 100 with the source or drain of the light emission control transistor Tr3 provided on the semiconductor substrate 100. That is, the drive transistor Tr1 and the light emission control transistor Tr3 have a series gate structure in which the source or drain of one transistor shares a single diffusion region 104 with the source or drain of the other transistor. In this embodiment, it is preferable to select a series gate structure to prevent an increase in the layout area of the drive transistor Tr1 and the light emission control transistor Tr3, but this embodiment is not limited to this.
  • the light emission control transistor Tr3 like the drive transistor Tr1, has a gate electrode 102 provided via an insulating film 202 on a region (third channel formation region) having n-type conductivity that functions as a channel of the light emission control transistor Tr3 provided in the semiconductor substrate 100. Furthermore, the light emission control transistor Tr3 has a source/drain formed of diffusion regions 104 containing p-type conductivity impurities that sandwich the channel formation region. In this way, in this embodiment, by providing the light emission control transistor Tr3 on the semiconductor substrate 100, it is possible to stabilize the characteristics and make it a high-voltage transistor with high driving force. Furthermore, the light emission control transistor Tr3 is separated from the drive transistor Tr1 by an element isolation portion 106 provided in the semiconductor substrate 100.
  • the source or drain of the light emission control transistor Tr3 is electrically connected to an electrode (not shown) of a capacitance unit C2 provided in the wiring layer 200 and to a wiring 204 connected to a power supply (V DD ) by a via 206. Furthermore, the gate electrode 102 of the light emission control transistor Tr3 is electrically connected to a signal source of a light emission control signal DS by a via 206.
  • the capacitance portion C2 may be provided in the wiring layer 200 laminated above the driving transistor Tr1 and the emission control transistor Tr3.
  • one side of the capacitance portion C2 may be electrically connected to the source/drain shared by the driving transistor Tr1 and the emission control transistor Tr3 described above through a via 206, and the other side of the capacitance portion C2 may be electrically connected through the via 206 to the wiring 204 that is connected to the power supply (V DD ).
  • the write transistor Tr2 and the switching transistor Tr4 are provided in the wiring layer 200 laminated on the semiconductor substrate 100 on which the drive transistor Tr1 and the emission control transistor Tr3 are provided.
  • the drive transistor Tr1 and the emission control transistor Tr3 included in the drive circuit and for which a high breakdown voltage is desired are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided in the wiring layer 200.
  • the write transistor Tr2 may be provided on the semiconductor substrate 100, like the drive transistor Tr1 and the emission control transistor Tr3.
  • the write transistor Tr2 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and can be an N-channel transistor in detail.
  • the write transistor Tr2 may be a P-channel transistor. More specifically, the write transistor Tr2 has an oxide semiconductor layer 210 provided in the wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202.
  • the oxide semiconductor layer 210 can be formed from, for example, an oxide film containing at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), tin (Sn), and zinc (Zn). More specifically, the oxide semiconductor layer 210 can be formed from indium oxide (In 2 O 3 ), tin-indium oxide (In 2 O 3 with Sn added as a dopant, for example, ITO), indium-gallium-zinc oxide (ZnO 4 with In and Ga added as dopants, for example, IGZO), aluminum-zinc oxide (ZnO with Al added as a dopant, for example, AZO), indium-zinc oxide (ZnO with In added as a dopant, for example, IZO), indium-tin-zinc oxide (ZnO with In and Sn added as dopants, for example, ITZO), indium-aluminum-zinc oxide (ZnO with In and Al added as dopants, for
  • these oxide semiconductors have an extremely small leakage current, and therefore leakage in the write transistor Tr2 can be suppressed.
  • the leakage is low and a signal can be retained for a long period of time, the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increased number of pixels can be suppressed.
  • the write transistor Tr2 is also configured as a top gate structure in which the gate electrode (second gate electrode) 212 is located above the oxide semiconductor layer 210.
  • this embodiment is not limited to this, and as described later, the write transistor Tr2 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
  • the gate electrode 212 of the write transistor Tr2 has a vertical gate portion (second vertical gate portion) 212a extending along the film thickness direction of the semiconductor substrate 100.
  • the gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202.
  • the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 4A in accordance with the write transistor Tr2 having a top gate structure and a vertical gate structure.
  • the write transistor Tr2 has a channel formation region (fourth channel formation region) in the region 210a that is a convex portion that is in contact with the gate electrode 212 and its vertical gate portion 212a via the insulating film 202 within the oxide semiconductor layer 210. Furthermore, in this embodiment, the source and drain of the write transistor Tr2 are located in a pair of regions 210b that sandwich the region 210a, which is a convex portion of the oxide semiconductor layer 210.
  • the gate electrode 212 of the write transistor Tr2 a vertical gate structure
  • the gate length can be easily increased without expanding the layout area (footprint).
  • hydrogen can diffuse into the channel formation region and bond with dangling bonds in the channel formation region, causing fluctuations in the characteristics of the channel formation region.
  • the vertical gate portion 212a longer (increasing the aspect ratio)
  • the source and drain can be separated further from the channel formation region of the write transistor Tr2, thereby suppressing the above-mentioned characteristic fluctuations.
  • the gate electrode 212 and vertical gate portion 212a of the write transistor Tr2 can be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo).
  • the source or drain of the write transistor Tr2 is electrically connected to a wiring 204 (signal voltage Vsig) provided in the wiring layer 200 through a via (contact hole) 206.
  • the via 206 is in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
  • the gate electrode 212 of the write transistor Tr2 is electrically connected to the wiring 204, which is connected to the scanning line (WS), through the via 206.
  • the switching transistor Tr4 is configured as a thin film transistor (TFT) provided in the wiring layer 200, similar to the write transistor Tr2, and can be, for example, an N-channel transistor. Note that this embodiment is not limited to this structure, and the switching transistor Tr4 may be provided on the semiconductor substrate 100, similar to the drive transistor Tr1 and the light emission control transistor Tr3.
  • TFT thin film transistor
  • the switching transistor Tr4 has an oxide semiconductor layer 210 provided in the wiring layer 200 and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202.
  • the oxide semiconductor layer 210 can be formed of, for example, an oxide film containing at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.
  • the oxide semiconductor layer 210 can be formed of indium oxide (In 2 O 3 ), tin-indium oxide (ITO), indium-gallium-zinc oxide (IGZO), aluminum-zinc oxide (AZO), indium-zinc oxide (IZO), indium-tin-zinc oxide (ITZO), indium-aluminum-zinc oxide (IAZO), or the like.
  • these oxide semiconductors have an extremely small leakage current, so that leakage in the switching transistor Tr4 can be suppressed. In this way, according to this embodiment, leakage current during a transient response is suppressed, so that black floating is reduced and contrast is improved. Furthermore, it is easy to form the switching transistor Tr4 as an N-channel transistor.
  • the switching transistor Tr4 which is an N-channel transistor, can stably control the cathode-anode voltage of the light-emitting element EL to 0 V, so that no current is supplied to the light-emitting element EL.
  • the switching transistor Tr4 which is an N-channel transistor, can stably control the cathode-anode voltage of the light-emitting element EL to 0 V, so that no current is supplied to the light-emitting element EL.
  • the switching transistor Tr4 is also configured as a top gate structure in which the gate electrode (first gate electrode) 212 is located above the oxide semiconductor layer 210.
  • this embodiment is not limited to this, and as described later, the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
  • the gate electrode 212 of the switching transistor Tr4 has a vertical gate portion (first vertical gate portion) 212a extending along the film thickness direction of the semiconductor substrate 100.
  • the gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202.
  • the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 4A in accordance with the switching transistor Tr4 having a top gate structure and a vertical gate structure.
  • the switching transistor Tr4 has a channel formation region (second channel formation region) in the region 210a that is a convex portion in the oxide semiconductor layer 210 and that is in contact with the gate electrode 212 and its vertical gate portion 212a via the insulating film 202.
  • the source and drain of the switching transistor Tr4 are located in a pair of regions 210b that sandwich the region 210a that is a convex portion in the oxide semiconductor layer 210.
  • the gate electrode 212 of the switching transistor Tr4 a vertical gate structure
  • the gate length can be easily increased without expanding the layout area.
  • hydrogen can diffuse into the channel formation region and bond with dangling bonds in the channel formation region, causing the characteristics of the channel formation region to fluctuate.
  • the vertical gate portion 212a longer, the source and drain can be separated further from the channel formation region of the switching transistor Tr4, thereby suppressing the above-mentioned characteristic fluctuations.
  • the gate electrode 212 and vertical gate portion 212a of the switching transistor Tr4 can be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo).
  • the source or drain of the switching transistor Tr4 is electrically connected to the anode electrode 310 of the light-emitting element EL provided on the wiring layer 200 through a via 206.
  • the via 206 is in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
  • the gate electrode 212 of the switching transistor Tr4 is electrically connected to the wiring 204 that is connected to the drive signal source (AZ) through the via 206.
  • the switching transistor Tr4 and the writing transistor Tr2 are provided at the same height, i.e., in the same layer, in the stacked structure of the pixel 20.
  • this is not limited to this in the present embodiment, and for example, the switching transistor Tr4 and the writing transistor Tr2 may be provided at different heights, i.e., in different layers, and stacked on top of each other in the stacked structure of the pixel 20.
  • a light-emitting unit 300 which is a light-emitting element EL, is provided on the wiring layer 200.
  • the light-emitting element EL mainly comprises an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 that is laminated on the anode electrode 310 and emits light, and a cathode electrode 312 that is laminated on the light-emitting layer 314 and transmits light from the light-emitting layer 314.
  • the anode electrode 310 may also function as a reflective layer, and is preferably made of a metal film with as high a reflectivity and a large work function as possible in order to increase the light extraction efficiency.
  • metal films include metal films containing at least one of the simple substances and alloys of metal elements such as chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum, titanium, tantalum (Ta), aluminum, magnesium (Mg), iron (Fe), tungsten, and silver (Ag).
  • the light-emitting layer 314 provided on the anode electrode 310 is made of an organic material or an inorganic material, and is a layer capable of emitting, for example, white light.
  • the light-emitting layer 314 may have a hole injection layer (not shown) and a hole transport layer (not shown) provided adjacent to the anode electrode 310, and an electron transport layer (not shown) provided adjacent to the cathode electrode 312.
  • the light-emitting layer 314 may have a structure in which a hole injection layer, a hole transport layer, the light-emitting layer 314, and an electron transport layer (not shown) are stacked from the anode electrode 310 side.
  • the hole injection layer functions as a layer that increases the efficiency of hole injection into the light-emitting layer 314, and also functions as a buffer layer for suppressing leakage.
  • the hole transport layer functions as a layer that increases the efficiency of hole transport into the light-emitting layer 314.
  • the light-emitting layer 314 can generate light by recombining electrons and holes due to the generation of an electric field.
  • the electron transport layer functions as a layer that increases the efficiency of transporting electrons to the light-emitting layer 314.
  • the light-emitting layer 314 may have an electron injection layer (not shown) between the electron transport layer and the cathode electrode 312.
  • the electron injection layer functions as a layer that increases the efficiency of electron injection.
  • the configuration of the light-emitting layer 314 is not limited to the configuration described above, and layers other than the hole injection layer and the light-emitting layer 314 can be provided as necessary.
  • the light-emitting layer 314 is not limited to a layer that emits white light, but may be a layer that emits red light (for example, visible light having a wavelength of about 640 nm to 770 nm), blue light (for example, visible light having a wavelength of about 430 nm to 490 nm), or green light (for example, visible light having a wavelength of about 490 nm to 550 nm).
  • red light for example, visible light having a wavelength of about 640 nm to 770 nm
  • blue light for example, visible light having a wavelength of about 430 nm to 490 nm
  • green light for example, visible light having a wavelength of about 490 nm to 550 nm.
  • the cathode electrode 312 provided on the light-emitting layer 314 is a transparent electrode that is transparent to the light generated in the light-emitting layer 314, and in the following description, the transparent electrode also includes a semi-transparent electrode.
  • the cathode electrode 312 can be formed from a metal film or an oxide film containing at least one of the simple substances and alloys of metal elements such as aluminum, magnesium, calcium (Ca), sodium (Na), silver, indium, and zinc.
  • a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 4B) is provided on the strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor are provided to sandwich the gate electrode 212. Furthermore, in this plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are aligned on a single line.
  • the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 laminated on the semiconductor substrate 100.
  • TFTs thin film transistors
  • the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs), are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4.
  • leakage from the write transistor Tr2 can be suppressed, and therefore a signal can be held for a long time, and the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increase in the number of pixels can be suppressed.
  • leakage from the switching transistor Tr4 can be suppressed, and therefore black floating can be reduced, the contrast can be improved, and the increase in power consumption of the display device 10 can be suppressed.
  • the switching transistor Tr4 it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode of the light-emitting element EL to 0 V, and it is possible to prevent current from being supplied to the light-emitting element EL. As a result, according to this embodiment, it is possible to suppress a decrease in contrast when displaying black gradations.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure, the gate length can be easily increased without expanding the layout area. Furthermore, by lengthening the vertical gate portion 212a, the source and drain can be further away from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause the characteristics of the channel formation region to fluctuate.
  • the pixel 20 is not limited to the configuration shown in FIG. 4A and FIG. 4B.
  • the transistors provided in the semiconductor substrate 100 and the transistors provided in the oxide semiconductor layer 210 in the wiring layer 200 are not limited to the configuration shown in FIG. 4A, and can be freely combined as long as at least one transistor is provided in the semiconductor substrate 100 and at least one other transistor is provided in the oxide semiconductor layer 210.
  • the number of transistors included in the drive circuit of the pixel 20 is not limited to four, and is not particularly limited as long as it is two or more.
  • FIGS. 5 and 6 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a modified example of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 shown to be located on the lower side. Note that in these figures, the capacitance sections C1 and C2 are omitted from illustration.
  • a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
  • the conductive layer 220 when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, and therefore a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
  • the conductive layer 220 may be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium (Ti), tantalum (Ta), and molybdenum (Mo). More specifically, the conductive layer 220 may be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, aluminum-titanium alloy, silicon-titanium alloy, molybdenum, etc.
  • a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
  • the conductive layer 222 functions as a heat sink to generate a temperature gradient during the formation of the oxide semiconductor layer 210, and a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
  • the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when contacts are formed at the source and drain.
  • hydrogen or oxygen diffuses when contacts are formed at the source and drain, these may cause oxidation and reduction, resulting in a change in carrier concentration.
  • the conductive layer 222 can suppress the diffusion of hydrogen and oxygen when the contacts are formed.
  • the conductive layer 222 may be formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum. More specifically, the conductive layer 222 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, aluminum-titanium alloy, silicon-titanium alloy, molybdenum, etc.
  • the pixel 20 is not limited to the configuration shown in Figures 5 and 6.
  • Fig. 7 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 7, the capacitance parts C1 and C2 are omitted from the illustration.
  • the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, but as shown in FIG. 7, the gate electrode 212 of the write transistor Tr2 has a flat gate electrode structure having a flat gate electrode 232 on the oxide semiconductor layer 230.
  • the layout size of the drive circuit can be reduced while satisfying the required characteristics of the transistors included in the drive circuit, and the power consumption during standby can also be reduced.
  • the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 stacked on the semiconductor substrate 100.
  • the layout size of the drive circuit can be reduced while ensuring a high withstand voltage for a certain transistor, and the display device 10 can be made smaller and finer.
  • the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs) are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4.
  • the gate electrode 212 of the switching transistor Tr4 a vertical gate structure
  • the gate length can be easily increased without expanding the layout area.
  • the source and drain can be separated further from the channel formation region of the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause fluctuations in the characteristics of the channel formation region.
  • the pixel 20 is not limited to the configuration shown in FIG. 7.
  • the gate electrode 212 of the writing transistor Tr2 may have a vertical gate structure
  • the gate electrode 212 of the switching transistor Tr4 may have a flat gate electrode structure.
  • FIGS. 8 and 9 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a modified example of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 shown to be located on the lower side. Note that in these figures, the capacitance sections C1 and C2 are omitted from illustration.
  • a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the switching transistor Tr4.
  • the conductive layer 220 when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, and therefore a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
  • a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that becomes the source or drain of the switching transistor Tr4.
  • the conductive layer 222 when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, so that a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
  • the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when contacts are formed at the source and drain.
  • the conductive layer 222 can suppress the diffusion of hydrogen and oxygen when the contacts are formed.
  • the pixel 20 is not limited to the configuration shown in Figures 8 and 9.
  • Fig. 10 is a schematic diagram showing an example of a planar configuration of a pixel 20 according to this embodiment, and corresponds to Fig. 4B.
  • a gate electrode 212 is provided on a strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor are provided to sandwich the gate electrode 212. Furthermore, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged on a single line. However, the embodiments of the present disclosure are not limited to such a structure.
  • a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) is provided at the center of an L-shaped oxide semiconductor layer 210. Furthermore, a pair of vias (contact holes) 214 electrically connected to the source and drain of the transistor are provided on the ends of the L-shaped oxide semiconductor layer 210. In other words, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged in an L shape.
  • a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) is provided at the center of a U-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor are provided on the ends of the U-shaped oxide semiconductor layer 210. In other words, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged in a U-shape.
  • a part of the writing transistor Tr2 and the switching transistor Tr4 may be structured to share a part of the region with these transistors of the adjacent pixel 20.
  • a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) of a transistor of one pixel 20 is provided on the center of a Y-shaped oxide semiconductor layer 210.
  • a pair of vias 214 electrically connected to the source and drain of the transistor of one pixel 20 and a via 214 electrically connected to the source or drain of the transistor of the other pixel 20 are provided on three ends of the Y-shaped oxide semiconductor layer 210.
  • the center of the gate electrode 212 of the transistor of one pixel 20, the center of the pair of vias 214 of the transistor of one pixel 20, and the center of one of the pair of vias 214 of the transistor of the other pixel 20 are arranged in a Y shape.
  • the layout size of the drive circuit can be made smaller, and the display device 10 can be made smaller and finer.
  • the writing transistor Tr2 and the switching transistor Tr4 of the pixel 20 are not limited to the configuration shown in FIG. 10.
  • Fig. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 11, the capacitance units C1 and C2 are omitted from the illustration.
  • the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
  • this embodiment is not limited to this, and as shown in FIG. 11, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
  • the cross-sectional structures of the write transistor Tr2 and the switching transistor Tr4 i.e., the structures of the source and drain contacts of these transistors, it is possible to reduce the size of the drive circuit in the film thickness direction of the semiconductor substrate 100. As a result, according to this embodiment, it is possible to make the display device 10 smaller and more miniaturized.
  • the pixel 20 is not limited to the configuration shown in FIG. 11.
  • Fig. 12 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 12, the capacitance units C1 and C2 are omitted from the illustration.
  • the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure with one vertical gate portion 212a, but in this embodiment, they may have a vertical gate structure with multiple vertical gate portions 212b.
  • the write transistor Tr2 and the switching transistor Tr4 have two vertical gate portions 212b. Note that this embodiment is not limited to having two vertical gate portions 212b, and it is sufficient to have two or more vertical gate portions 212b.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have multiple vertical gate portions 212b, so that the gate length can be increased without increasing the layout area. Furthermore, in this embodiment, the source and drain can be separated from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be more effectively prevented from diffusing from the source and drain into the channel formation region, which would cause fluctuations in the characteristics of the channel formation region.
  • the pixel 20 is not limited to the configuration shown in FIG. 12.
  • Fig. 13 and Fig. 14 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail correspond to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance parts C1 and C2 are omitted from the illustration.
  • the write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210.
  • this embodiment is not limited to this, and the write transistor Tr2 and the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have vertical gate portions 212a extending along the film thickness direction of the semiconductor substrate 100.
  • the gate electrodes 212 and their vertical gate portions 212a are in contact with the lower surface of the oxide semiconductor layer 210 via the insulating film 202.
  • the oxide semiconductor layer 210 has a region 210a that is a convex portion that protrudes upward along the vertical gate portion 212a in the cross section shown in FIG. 13 in accordance with the write transistor Tr2 having a bottom gate structure and a vertical gate structure.
  • the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
  • the write transistor Tr2 and the switching transistor Tr4 may have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210. Furthermore, in the example of FIG. 14, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
  • the size of the drive circuit in the film thickness direction of the semiconductor substrate 100 can be reduced, and the display device 10 can be made smaller and finer.
  • the pixel 20 is not limited to the configuration shown in Figures 13 and 14.
  • Figures 15A to 15D are cross-sectional views for explaining the method for manufacturing the pixel (pixel circuit) 20 according to this embodiment, and correspond to the cross section shown in Figure 4A in detail.
  • a drive transistor Tr1 and a light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed thereon, and an insulating film 202 is then formed. Then, as shown in the center of FIG. 15A, a trench 400 is formed in the insulating film 202 by etching or the like. Furthermore, as shown on the right side of FIG. 15A, an oxide semiconductor layer 210 that will become the channel formation region of the write transistor Tr2 and the switching transistor Tr4 is formed by sputtering or the like so as to cover the insulating film 202.
  • an insulating film 202 that will become the gate insulating film of the write transistor Tr2 and the switching transistor Tr4 is formed so as to cover the oxide semiconductor layer 210 and fill the trench 400.
  • a trench 402 is formed in the region of the insulating film 202 that is filled in the trench 400.
  • a metal film or the like that will become the vertical gate portion 212a of the gate electrode 212 of the write transistor Tr2 and the switching transistor Tr4 is formed so as to fill the trench 402.
  • an insulating film 202 that will become the gate insulating film of the write transistor Tr2 and the switching transistor Tr4 is formed on the insulating film 202 and the vertical gate portion 212a. Furthermore, using CMP (Chemical Mechanical Polishing) or the like, the insulating film 202 is planarized and the upper surface of the vertical gate portion 212a is exposed, and the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 are formed on the upper surface of the vertical gate portion 212a.
  • CMP Chemical Mechanical Polishing
  • an insulating film 202 that will become an interlayer insulating film is formed so as to cover the upper surfaces of the gate electrode 212 and the insulating film 202.
  • holes are formed in the insulating film 202 to expose part of the upper surface of the region 210b of the oxide semiconductor layer 210 that will become the source and drain of the writing transistor Tr2 and the switching transistor Tr4, and a metal film that will become the via 214 is formed in the insulating film 202 in the hole.
  • wiring 204 is formed on the upper surface of the via 214.
  • the pixel 20 according to the embodiment of the present disclosure can be manufactured using methods, devices, and conditions that are used in the manufacture of general semiconductor devices. In other words, the pixel 20 according to the embodiment can be manufactured using existing semiconductor device manufacturing methods.
  • Fig. 16 is a schematic diagram showing an example of a cross-sectional configuration of a main part of a pixel 20 according to the eighth embodiment of the present disclosure.
  • the channel formation regions of the write transistor Tr2 and the switching transistor Tr4 are formed in the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure, which makes it easy to increase the gate length without increasing the layout area.
  • the vertical gate portion 212a is lengthened, which makes it possible to separate the source and drain from the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, thereby suppressing the diffusion of hydrogen from the source and drain into the channel formation region and the change in the characteristics of the channel formation region when contacts are formed at the source and drain.
  • the oxide semiconductor layer 210 made of indium gallium zinc oxide (IGZO) or the like has a property of being easily oxidized and reduced by the influence of the surrounding films.
  • IGZO indium gallium zinc oxide
  • the oxide semiconductor layer 210 is easily oxidized and its resistance is likely to increase.
  • the region 210a of the oxide semiconductor layer 210 that serves as the channel may have a high resistance, but the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain are required to have a low resistance in order to prevent parasitic resistance from occurring in the source and drain.
  • an eighth embodiment of the present disclosure which makes it easy to separately create a region 210a of the oxide semiconductor layer 210 that serves as a channel, and a pair of regions 210b of the oxide semiconductor layer 210 that serve as a source and drain.
  • the region 210a of the oxide semiconductor layer 210 that becomes the channel is formed so as to be in contact with an insulating film (first insulating layer) 202 made of an oxidation film that takes electrons from the surroundings, thereby increasing the resistance of the region 210a of the oxide semiconductor layer 210 that becomes the channel.
  • the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain are formed so as to be in contact with an insulating film (second insulating layer) 450 made of a reduction film that gives electrons to the surroundings, thereby decreasing the resistance of the region 210b.
  • the oxidizing film that takes electrons from the surroundings refers to a film that has the effect of taking electrons from the surrounding film and oxidizing the film, and more specifically, it is a film that can take electrons from the region 210a of the oxide semiconductor layer 210 that becomes the channel and oxidize the film.
  • the oxidizing film is an oxygen supplying film that supplies oxygen to the region 210a of the oxide semiconductor layer 210 that becomes the channel, and can be, for example, silicon oxide, silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), etc.
  • the oxygen supplying film is preferably silicon oxide (SiOx (x>2)) containing an excess of oxygen, etc.
  • the reduction action film that provides electrons to the surroundings refers to a film that has the effect of providing electrons to the surrounding film and reducing the film, and in particular, it is a film that can provide electrons to the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain, thereby reducing the film.
  • the reduction action film is a hydrogen supply film that provides hydrogen to the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain, or a film that can extract oxygen from the pair of regions 210b.
  • the hydrogen supply film can be, for example, silicon nitride, silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxynitride (AlON), or the like that contains hydrogen. Furthermore, the hydrogen supply film can adjust its hydrogen content by, for example, the film formation conditions, film thickness, etc., so that the reduction action to the region 210b can be freely adjusted. In this embodiment, it is preferable to set the film thickness of the hydrogen supply film to, for example, 20 nm or more in order to provide sufficient hydrogen to the region 210b and to block the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b. In addition, in this embodiment, an example of a film that can extract oxygen is an insulating film that has a greater compressive stress than the oxide semiconductor layer 210.
  • the region 210a of the oxide semiconductor layer 210 that serves as the channel is formed so as to be in contact with the insulating film 202 made of an oxidation film that takes electrons from the surroundings, so that the region 210a is oxidized and the resistance value can be increased.
  • the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain are formed so as to be in contact with the insulating film (second insulating layer) 450 made of a reduction film that gives electrons to the surroundings, so that the pair of regions 210b are reduced and the resistance value can be reduced.
  • the regions 210a and 210b of the oxide semiconductor layer 210 can be easily made to have desired characteristics.
  • FIG. 17 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment.
  • the stacked structure of the pixel 20 is shown in a cross section taken along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 positioned below. Sections C1 and C2 are omitted from the illustration.
  • the write transistor Tr2 and the switching transistor Tr4 have an oxide semiconductor layer 210 provided in a wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202.
  • the write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210.
  • the oxide semiconductor layer 210 has a thickness of, for example, 20 nm or less.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate portion 212a extending along the film thickness direction of the semiconductor substrate 100.
  • the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 17 in accordance with the write transistor Tr2 and the switching transistor Tr4 having a top gate structure and a vertical gate structure.
  • the write transistor Tr2 and the switching transistor Tr4 have a channel formation region in the region 210a that is a convex portion in contact with the gate electrode 212 and its vertical gate portion 212a through the insulating film 202 in the oxide semiconductor layer 210.
  • the gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 through the insulating film 202 made of the above-mentioned oxidation film.
  • the side of the region 210a, which is the convex portion that is the channel formation region, opposite the vertical gate portion 212a is also in contact with the insulating film 202, which is an oxidation film.
  • the source and drain of the writing transistor Tr2 and the switching transistor Tr4 are located in a pair of regions 210b that sandwich the region 210a, which is a convex-shaped portion in the oxide semiconductor layer 210. Furthermore, in this embodiment, unlike each of the embodiments described so far, an insulating film 450 made of the above-mentioned reduction action film is provided so as to contact the lower surface of the pair of regions 210b, as shown in FIG. 17.
  • the region 210a that becomes the channel is formed so as to be in contact with the insulating film 202, which is an oxidizing film that takes electrons from the surroundings, so that the region 210a is oxidized and the resistance value can be increased.
  • the pair of regions 210b that become the source and drain are formed so as to be in contact with the insulating film (second insulating layer) 450, which is a reducing film that gives electrons to the surroundings, so that the pair of regions 210b is reduced and the resistance value can be decreased.
  • the cross section of the pixel 20 taken along line A-A' in FIG. 17 can have the same shape as the first embodiment shown in FIG. 4B.
  • a gate electrode 212 may be provided on the strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor may be provided to sandwich the gate electrode 212.
  • the center of the gate electrode 212 and the center of the pair of vias 214 may be arranged on a single line.
  • the plan view of the write transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210 can also have the same form as that of the third embodiment shown in FIG. 10.
  • the write transistor Tr2 and the switching transistor Tr4 may have a gate electrode 212 provided at the center of the L-shaped oxide semiconductor layer 210.
  • a pair of vias (contact holes) 214 electrically connected to the source and drain of the transistor may be provided at the ends of the L-shaped oxide semiconductor layer 210.
  • the gate electrode 212 may be provided, for example, at the center of the U-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor may be provided at the ends of the U-shaped oxide semiconductor layer 210.
  • a part of the writing transistor Tr2 and the switching transistor Tr4 may share a part of the region with these transistors of an adjacent pixel 20.
  • the gate electrode 212 of the transistor of one pixel 20 may be provided on the center of the Y-shaped oxide semiconductor layer 210.
  • a pair of vias 214 electrically connected to the source and drain of the transistor of one pixel 20, and a via 214 electrically connected to the source or drain of the transistor of the other pixel 20 may be provided on the three ends of the Y-shaped oxide semiconductor layer 210.
  • the pixel 20 is not limited to the configuration shown in FIG. 17.
  • Fig. 18A to Fig. 18C are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to Modification 1 of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from illustration.
  • a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
  • the conductive layer 220 is preferably a reducing film that provides electrons to the surroundings, that is, a conductive film that has a high ionization tendency and is easily oxidized.
  • the conductive layer 220 is formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, and tantalum. More specifically, the conductive layer 220 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, etc.
  • the region 210b can be further reduced, and the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modified example, the region 210b that becomes the source and drain can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of the transistor Tr2 and the switching transistor Tr4.
  • a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
  • the conductive layer 222 is also preferably a reducing film that provides electrons to the surroundings, that is, a conductive film that has a high ionization tendency and is easily oxidized.
  • the conductive layer 222 is also formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, and tantalum. More specifically, the conductive layer 222 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, etc.
  • the region 210b can be further reduced, and the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modified example, the region 210b that becomes the source and drain can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of the transistor Tr2 and the switching transistor Tr4.
  • a conductive layer 220 that contacts the lower surface of the oxide semiconductor layer 210 and a conductive layer 222 that contacts the upper surface of the oxide semiconductor layer 210 are provided. That is, in the example of FIG. 18C, the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4 is sandwiched between the conductive layer 220 and the conductive layer 222.
  • region 210b can be further reduced, and oxygen can be prevented from diffusing from the surroundings (e.g., insulating film 202) to region 210b. Therefore, according to this modified example, region 210b, which serves as the source and drain, can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of transistor Tr2 and switching transistor Tr4.
  • pixel 20 is not limited to the configuration shown in FIGS. 18A to 18C.
  • Figures 19A to 19D are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a second modification of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
  • This modified example 2 can be said to be an embodiment in which the second embodiment is applied to the eighth embodiment. That is, as shown in FIG. 19A, the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, but the gate electrode 212 of the write transistor Tr2 has a planar gate electrode structure having a planar gate electrode 232 on the oxide semiconductor layer 230.
  • conductive layers 220 and 222 can be applied to the configuration shown in Figure 19A, similar to modified example 1 above.
  • pixel 20 is not limited to the configuration shown in Figures 19A to 19D.
  • Figures 20A to 20C are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a second modification of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
  • the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
  • this modified example is not limited to this, and as shown in FIG. 20A, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
  • the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller.
  • the display device 10 can be made smaller and finer.
  • the write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210.
  • this modified example is not limited to this, and similar to the sixth embodiment, as shown in FIG. 20B, the write transistor Tr2 and the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
  • the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller.
  • the display device 10 can be made smaller and finer.
  • the write transistor Tr2 and the switching transistor Tr4 have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210, but the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
  • the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller.
  • the display device 10 can be made smaller and finer.
  • the pixel 20 is not limited to the configuration shown in Figures 20A to 20C.
  • Fig. 21A and Fig. 21B are schematic diagrams showing an example of a cross-sectional configuration of a main part of a pixel 20 according to the fourth modification of the present embodiment.
  • the write transistor Tr2 and the switching transistor Tr4 may have a dual gate structure.
  • the write transistor Tr2 and the switching transistor Tr4 have a vertical gate portion (first vertical gate portion) 212a and a gate electrode (third gate electrode) 212c that faces each other across a region 210a that is a convex portion of the oxide semiconductor layer 210 that is a channel formation region.
  • the same potential or different potentials may be applied to the vertical gate portion 212a and the gate electrode 212c.
  • the vertical gate portions of the write transistor Tr2 and the switching transistor Tr4 may have a structure in which metal is not completely embedded.
  • the vertical gate portion 212d may have a cylindrical structure in which the surface facing the region 210a, which is the convex portion of the oxide semiconductor layer 210 that is the channel formation region, is closed and the inside is hollow.
  • the vertical gate portions of this modification may have a structure in which metal is not completely embedded, it can be said that this structure is highly suitable for mass production.
  • Fig. 22 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to the fifth modification of this embodiment, and in detail corresponds to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
  • the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure with one vertical gate portion 212a, but in this modified example, they may have a vertical gate structure with multiple vertical gate portions 212b.
  • the write transistor Tr2 and the switching transistor Tr4 have two vertical gate portions 212b.
  • the transistors are not limited to having two vertical gate portions 212b, and may have two or more vertical gate portions 212b.
  • the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have multiple vertical gate portions 212b, so that the gate length can be increased without increasing the layout area. Furthermore, in this modification 5, the source and drain can be separated further from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be more effectively prevented from diffusing from the source and drain into the channel formation region, which would cause fluctuations in the characteristics of the channel formation region.
  • Fig. 23A to Fig. 23E are schematic diagrams showing an example of a planar configuration of a pixel 20 according to the sixth modification of this embodiment.
  • the write transistor Tr2 and the switching transistor Tr4 may be spaced apart from each other in a plan view of the write transistor Tr2 and the switching transistor Tr4.
  • the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may be connected in a U shape (the Japanese katakana character "KOU") in a plan view of the write transistor Tr2 and the switching transistor Tr4.
  • the write transistor Tr2 and the switching transistor Tr4 may be arranged vertically in a plan view. Furthermore, as shown in FIG. 23C, in this modification, the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may extend vertically and be connected to each other.
  • the write transistor Tr2 and the switching transistor Tr4 may be provided so as to share the source and drain in a plan view. This can reduce the area occupied by the write transistor Tr2 and the switching transistor Tr4.
  • the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may be connected, for example, in a U shape in a plan view of the write transistor Tr2 and the switching transistor Tr4.
  • FIG. 24A and Fig. 24B is a cross-sectional view for explaining the manufacturing method of the device 20.
  • a drive transistor Tr1 and a light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed thereon, and then an insulating film 202 made of an oxidation film (e.g., silicon oxide) is formed. Furthermore, an insulating film 450 made of a reduction film (e.g., silicon nitride) is formed on the insulating film 202.
  • a trench 400 is formed in the insulating films 202, 450 by etching or the like.
  • an oxide semiconductor layer 210 that will become the channel formation region of the write transistor Tr2 and the switching transistor Tr4 is formed so as to cover the insulating films 202 and 450, using a process technology with high coverage such as ALD (Atomic Layer Deposition).
  • ALD Atomic Layer Deposition
  • an insulating film 202 made of, for example, silicon oxide that will become a gate insulating film is formed so as to cover the oxide semiconductor layer 210.
  • a process technology with high coverage such as ALD.
  • an electrode material that will become a vertical gate portion 212a is embedded in the trench.
  • the buried electrodes may be processed.
  • n-type impurities may be ion-implanted into the oxide semiconductor layer 210 located on both sides of the vertical gate portion 212a to form the impurity diffusion region 460.
  • the insulating film 202 located on both sides of the vertical gate portion 212a may be removed, and then ions may be implanted into the exposed oxide semiconductor layer 210 located on both sides of the vertical gate portion 212a to form the impurity diffusion region 460.
  • an insulating film 202 is laminated. Furthermore, as shown in the third from the left in FIG. 24B, vias 214 are formed to connect to the portions that will become the source and drain of the oxide semiconductor layer 210, and wiring 204 is formed on the vias 214 as shown in the right in FIG. 24B.
  • a trench 400 is formed on the laminate of insulating films 202 and 450 to form an oxide semiconductor layer 210, and a gate (vertical gate portion 212a) is formed in contact with the oxide semiconductor layer 210 via the insulating film 202. That is, according to this embodiment, by utilizing the laminate of the insulating film 202 made of an oxidation film and the insulating film 450 made of a reduction film, the region 210a that becomes the channel and the region 210b that becomes the source and drain can be easily and separately formed so as to have the desired characteristics without significantly increasing the number of processes. In addition, in this embodiment, the reduction action in region 210b can be freely adjusted by adjusting the film thickness of the insulating film 450, etc.
  • the pixel 20 according to the eighth embodiment of the present disclosure can be manufactured using methods, devices, and conditions that are used in the manufacture of general semiconductor devices. In other words, the pixel 20 according to this embodiment can be manufactured using existing semiconductor device manufacturing methods.
  • PVD Physical Vapor Deposition
  • CVD Physical Vapor Deposition
  • ALD ALD
  • PVD methods include vacuum deposition, EB (Electron Beam) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) combined bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer.
  • the CVD method include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD.
  • Other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater.
  • the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light, laser, and the like.
  • planarization techniques include CMP, laser planarization, and reflow.
  • the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 laminated on the semiconductor substrate 100.
  • TFTs thin film transistors
  • the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs), are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4.
  • leakage from the write transistor Tr2 can be suppressed, and therefore a signal can be held for a long time, and the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increase in the number of pixels can be suppressed.
  • leakage from the switching transistor Tr4 can be suppressed, and therefore black floating can be reduced, the contrast can be improved, and the increase in power consumption of the display device 10 can be suppressed.
  • the switching transistor Tr4 it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode of the light-emitting element EL to 0 V, and it is possible to prevent current from being supplied to the light-emitting element EL. As a result, according to this embodiment, it is possible to suppress a decrease in contrast when displaying black gradations.
  • the gate electrode 212 of the switching transistor Tr4 a vertical gate structure
  • the gate length can be easily increased without expanding the layout area.
  • the source and drain can be separated further from the channel formation region of the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause fluctuations in the characteristics of the channel formation region.
  • the technology disclosed herein may be applied not only to the display device 10 but also to lighting devices, etc.
  • the semiconductor substrate 100 does not necessarily have to be a silicon substrate, but may be another substrate (e.g., an SOI (Silicon On Insulator) substrate, a SiGe substrate, etc.).
  • SOI Silicon On Insulator
  • Fig. 25A is a front view showing an example of the external appearance of digital still camera 500
  • Fig. 25B is a rear view showing an example of the external appearance of digital still camera 500.
  • This digital still camera 500 is a lens-interchangeable single-lens reflex type, and has an interchangeable photographing lens unit (interchangeable lens) 512 approximately in the center of the front of a camera main body section (camera body) 511, and a grip section 513 for the photographer to hold on the left side of the front.
  • interchangeable photographing lens unit interchangeable lens
  • a monitor 514 is provided at a position shifted to the left from the center of the back of the camera body 511.
  • An electronic viewfinder (eyepiece window) 515 is provided at the top of the monitor 514. By looking through the electronic viewfinder 515, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 512 and determine the composition.
  • the display device 10 according to an embodiment of the present disclosure can be used as the monitor 514 or the electronic viewfinder 515.
  • (Specific Example 2) 26 is an external view of a head mounted display 600.
  • the head mounted display 600 has, for example, ear hooks 612 for mounting on the user's head on both sides of a glasses-shaped display unit 611.
  • the display device 10 according to the embodiment of the present disclosure can be used as the display unit 611.
  • the see-through head mounted display 634 is composed of a main body 632, an arm 633, and a lens barrel 631.
  • Main body 632 is connected to arm 643 and glasses 630. Specifically, the end of the long side of main body 632 is connected to arm 633, and one side of main body 632 is connected to glasses 630 via a connecting member. Note that main body 632 may also be worn directly on the head of the human body.
  • the main body 632 incorporates a control board for controlling the operation of the see-through head mounted display 634, and a display unit.
  • the arm 633 connects the main body 632 to the telescope tube 631, and supports the telescope tube 631. Specifically, the arm 633 is coupled to an end of the main body 632 and an end of the telescope tube 631, respectively, and fixes the telescope tube 631.
  • the arm 633 also incorporates a signal line for communicating data related to images provided from the main body 632 to the telescope tube 631.
  • the lens barrel 631 projects image light provided from the main body 632 via the arm 633 through an eyepiece lens toward the eyes of a user wearing the see-through head mounted display 634.
  • the display unit of the main body 632 can use the display device 10 according to an embodiment of the present disclosure.
  • This television device 710 has, for example, an image display screen unit 711 including a front panel 712 and a filter glass 713, and this image display screen unit 711 is configured by the display device 10 according to the embodiment of the present disclosure.
  • the smartphone 800 has a display unit 802 that displays various information, an operation unit that includes buttons that accept operation inputs by a user, and the like.
  • the display unit 802 can be the display device 10 according to this embodiment.
  • FIGS. 30A and 30B are diagrams showing the internal configuration of a vehicle having the display device 10 according to an embodiment of the present disclosure as a display device.
  • Fig. 30A is a diagram showing the state of the interior of the vehicle from the rear to the front
  • Fig. 30B is a diagram showing the state of the interior of the vehicle from the diagonally rear to the diagonally front.
  • the automobile shown in Figures 30A and 30B has a center display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916. Some or all of these displays can be implemented using the display device 10 according to an embodiment of the present disclosure.
  • the center display 911 is disposed on the center console 907 in a position facing the driver's seat 901 and the passenger seat 902.
  • Fig. 30A and Fig. 30B show an example of a horizontally elongated center display 911 extending from the driver's seat 901 side to the passenger seat 902 side
  • the screen size and the location of the center display 911 are arbitrary.
  • the center display 911 can display information detected by various sensors (not shown).
  • the center display 911 can display an image captured by an image sensor, a distance image to an obstacle in front of or to the side of the vehicle measured by a ToF (Time of Flight) sensor, and a passenger's body temperature detected by an infrared sensor.
  • the center display 911 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information.
  • the safety-related information includes information such as detection of drowsiness, detection of distraction, detection of tampering by children in the car, whether or not a seat belt is fastened, and detection of an occupant being left behind, and is information detected, for example, by a sensor (not shown) arranged on the back side of the center display 911.
  • the operation-related information is obtained by detecting gestures related to the operation of the occupant using a sensor.
  • the detected gestures may include operations of various equipment in the car. For example, operations of the air conditioning equipment, navigation device, AV (Audio/Visual) device, lighting device, etc. are detected.
  • the life log includes the life log of all occupants. For example, the life log includes a record of the actions of each occupant while in the car.
  • the health-related information is obtained by detecting the body temperature of the occupant using a temperature sensor, and inferring the health condition of the occupant based on the detected body temperature.
  • the face of the occupant may be captured using an image sensor, and the health condition of the occupant may be inferred from the facial expression captured in the image.
  • the occupant may be spoken to by an automated voice and the occupant's health condition may be inferred based on the occupant's responses.
  • Authentication/identification related information includes a keyless entry function that uses a sensor to perform face authentication, and a function for automatically adjusting seat height and position using face recognition.
  • Entertainment related information includes a function for detecting operation information of an AV device by an occupant using a sensor, and a function for recognizing the occupant's face using a sensor and providing content suitable for the occupant via the AV device.
  • the console display 912 can be used, for example, to display life log information.
  • the console display 912 is disposed near the shift lever 908 on the center console 907 between the driver's seat 901 and the passenger seat 902.
  • the console display 912 can also display information detected by various sensors (not shown).
  • the console display 912 may also display an image of the surroundings of the vehicle captured by an image sensor, or an image showing the distance to obstacles around the vehicle.
  • the head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901.
  • the head-up display 913 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information. Since the head-up display 913 is often virtually positioned in front of the driver's seat 901, it is suitable for displaying information directly related to the operation of the vehicle, such as the vehicle's speed and remaining fuel (battery) level.
  • the digital rear-view mirror 914 can not only display the rear of the vehicle, but also the state of passengers in the back seats. For example, by placing a sensor (not shown) on the back side of the digital rear-view mirror 914, it can be used to display life log information.
  • the steering wheel display 915 is disposed near the center of the steering wheel 906 of the vehicle.
  • the steering wheel display 915 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information.
  • the steering wheel display 915 since the steering wheel display 915 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.
  • the rear entertainment display 916 is attached to the back of the driver's seat 901 and passenger seat 902, and is intended for viewing by rear seat passengers.
  • the rear entertainment display 916 can be used to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information, for example.
  • information related to the rear seat passengers is displayed on the rear entertainment display 916.
  • the rear entertainment display 916 may display information related to the operation of AV equipment or air conditioning equipment, or may display the results of measuring the body temperature of the rear seat passengers using a temperature sensor (not shown).
  • a plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate, Each pixel is A light-emitting element whose luminance changes in response to a current supplied thereto; a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element; having The first transistor is a first channel forming region in the semiconductor substrate; The second transistor is a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate; a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film; having Display device.
  • the display device according to any one of (1) to (4), wherein the first gate electrode has a plurality of the first vertical gate portions.
  • the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.
  • the second transistor has a source and a drain sandwiching the convex portion of the oxide semiconductor layer.
  • the display device wherein the source and the drain of the second transistor include a conductive layer provided over the oxide semiconductor layer.
  • the display device according to (7), wherein the source and the drain of the second transistor include a conductive layer provided under the oxide semiconductor layer.
  • the conductive layer is made of a metal or an alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum.
  • the second channel formation region is in contact with a first insulating layer made of an oxidation film that removes electrons from the surroundings.
  • the oxidation film is an oxygen supply film that supplies oxygen to the second channel formation region.
  • the display device according to any one of (7) to (13) above, wherein the source and the drain of the second transistor are in contact with a second insulating layer made of a reduction-reactive film that provides electrons to the surroundings.
  • the reduction film is a hydrogen supply film that supplies hydrogen to the source and the drain.
  • the reduction film has a thickness of 20 nm or more.
  • the first vertical gate portion has a cylindrical structure with a surface facing the second channel formation region closed.
  • the second transistor further includes a third gate electrode that faces the first vertical gate portion with the second channel formation region interposed therebetween;
  • the display device according to any one of (1) to (17) above.
  • the pair of contact holes and the first gate electrode of the second transistor of the pixel, and one of the pair of contact holes of the second transistor of another pixel adjacent to the pixel, are arranged in a Y shape;
  • the plurality of transistors includes a third transistor and a fourth transistor,
  • the third transistor is a third channel forming region in the semiconductor substrate;
  • the fourth transistor is a fourth channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate;
  • the first transistor is a drive transistor electrically connected to a current source and the light-emitting element, and supplies a current corresponding to a signal voltage to the light-emitting element;
  • the second transistor is a switching transistor that is electrically connected to the light-emitting element and controls the light-emitting element not to emit light during a non-light-emitting period;
  • the third transistor is an emission control transistor that is electrically connected to the drive transistor and controls emission of the light-emitting element;
  • the fourth transistor is a write transistor that is electrically connected to the drive transistor and supplies the signal voltage to the drive transistor via a capacitance section;
  • the display device according to any one of (1) to (27) above, wherein the light-emitting element is an OLED.
  • An electronic device equipped with a display device The display device includes: A plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate, Each pixel is A light-emitting element whose luminance changes in response to a current supplied thereto; a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element; having The first transistor is a first channel forming region in the semiconductor substrate; The second transistor is a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate; a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film; having Electronics.
  • Display device 20a Pixel 30 Pixel array section 31 Scanning line 32, 33 Drive line 34 Signal line 40 Write scanning section 50, 60 Drive scanning section 70 Signal output section 80 Display panel 100 Semiconductor substrate 102, 212, 212c, 232 Gate electrode 104 Diffusion region 106 Element isolation section 200 Wiring layer 202, 450 Insulating film 204 Wiring 206, 214 Via 212a, 212b, 212d Vertical gate section 310, 312 Electrode 210, 230 Oxide semiconductor layer 210a, 210b Region 220, 222 Conductive layer 300 Light-emitting section 314 Light-emitting layer 400, 402 Trench 460 Diffusion region 500 Digital still camera 511 Camera body 512 Shooting lens unit 513 Grip 514 Monitor 515 Electronic viewfinder 600 Head mounted display 611, 802 Display 612 Ear hook 630 Glasses 631 Lens barrel 632 Body 633, 643 Arm 634 See-through head mounted display 710 Television device 711 Video display screen 712 Front panel 713 Filter glass 800

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Abstract

Provided is a display device comprising a plurality of pixels that are two-dimensionally arranged in a matrix on a semiconductor substrate, wherein each of the pixels comprises a light-emitting element the brightness of which changes in accordance with supplied current, and a plurality of transistors including at least a first transistor and a second transistor and electrically connected to the light-emitting element, the first transistor has a first channel formation region in the semiconductor substrate, and the second transistor has a first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate, and a second channel formation region that is located within an oxide semiconductor layer stacked above the semiconductor substrate and is in contact with the first gate electrode via an insulating film.

Description

表示装置及び電子機器Display device and electronic device
　本開示は、表示装置及び電子機器に関する。 This disclosure relates to display devices and electronic devices.
　近年、発光素子として電界発光（ＥＬ：Ｅｌｅｃｔｒｏ　Ｌｕｍｉｎｅｓｃｅｎｃｅ）素子を用いた表示装置の開発が進んでいる。当該表示装置は、例えば、下部電極と、下部電極上に積層された発光層と、発光層上に積層された上部電極とによって構成された複数の発光素子を有する。そして、上記表示装置は、上述した発光素子のほかに、発光素子を駆動するために駆動回路を有する。例えば、表示装置の一例としては、下記特許文献１に開示の表示装置を挙げることができる。 In recent years, development of display devices using electroluminescence (EL) elements as light-emitting elements has progressed. Such display devices have multiple light-emitting elements, each configured with, for example, a lower electrode, a light-emitting layer stacked on the lower electrode, and an upper electrode stacked on the light-emitting layer. In addition to the light-emitting elements described above, the display devices also have a drive circuit for driving the light-emitting elements. For example, one example of a display device is the display device disclosed in Patent Document 1 below.
特開２０２１－９４０１号公報JP 2021-9401 A
　表示装置に対しては、発光素子の微細化等に伴い、上記駆動回路に含まれる各種トランジスタに求められる耐圧や特性を考慮した上で、駆動回路のレイアウトサイズを小さくすることが求められている。さらに、表示装置に対しては、発光素子の微細化及び多画素化を行った場合であっても、待機時の消費電力をより下げることが求められている。 With the miniaturization of light-emitting elements, display devices are required to reduce the layout size of the drive circuits while taking into consideration the withstand voltage and characteristics required of the various transistors included in the drive circuits. Furthermore, even when light-emitting elements are miniaturized and the number of pixels is increased, display devices are required to further reduce power consumption during standby.
　そこで、本開示では、駆動回路に含まれるトランジスタに対する要求特性を満たしつつ、駆動回路のレイアウトサイズを小さくし、待機時の消費電力も下げることができる、表示装置及び電子機器を提案する。 This disclosure therefore proposes a display device and electronic device that can reduce the layout size of the drive circuit and reduce power consumption during standby while satisfying the required characteristics for the transistors included in the drive circuit.
　本開示によれば、半導体基板上にマトリックス状に２次元配列する複数の画素を備え、前記各画素は、供給される電流に応じて輝度が変化する発光素子と、前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタとを有し、前記第１のトランジスタは、前記半導体基板内に第１のチャネル形成領域を有し、前記第２のトランジスタは、前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域とを有する、表示装置が提供される。 According to the present disclosure, there is provided a display device comprising a plurality of pixels arranged two-dimensionally in a matrix on a semiconductor substrate, each of the pixels having a light-emitting element whose luminance changes in response to a current supplied thereto, and a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light-emitting element, the first transistor having a first channel formation region in the semiconductor substrate, and the second transistor having a first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate, and a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate and in contact with the first gate electrode via an insulating film.
　さらに、本開示によれば、表示装置を搭載する電子機器であって、前記表示装置は、半導体基板上にマトリックス状に２次元配列する複数の画素を備え、前記各画素は、供給される電流に応じて輝度が変化する発光素子と、前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタとを有し、前記第１のトランジスタは、前記半導体基板内に第１のチャネル形成領域を有し、前記第２のトランジスタは、前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域とを有する、電子機器が提供される。 Furthermore, according to the present disclosure, there is provided an electronic device equipped with a display device, the display device comprising a plurality of pixels arranged two-dimensionally in a matrix on a semiconductor substrate, each of the pixels comprising a light-emitting element whose luminance changes in response to a current supplied thereto, and a plurality of transistors including at least a first transistor and a second transistor, electrically connected to the light-emitting element, the first transistor comprising a first channel-forming region in the semiconductor substrate, the second transistor comprising a first gate electrode including a first vertical gate portion extending along the film thickness direction of the semiconductor substrate, and a second channel-forming region in an oxide semiconductor layer stacked above the semiconductor substrate and in contact with the first gate electrode via an insulating film.
本開示の実施形態に係る表示装置の全体構成の一例を示す概略図である。1 is a schematic diagram illustrating an example of an overall configuration of a display device according to an embodiment of the present disclosure. 本開示の実施形態に係る表示装置の画素の一例を示した回路図である。1 is a circuit diagram illustrating an example of a pixel of a display device according to an embodiment of the present disclosure. 比較例に係る画素の断面構成の一例を示した模式図である。FIG. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a comparative example. 本開示の第１の実施形態に係る画素の断面構成の一例を示した模式図である。FIG. 2 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to the first embodiment of the present disclosure. 本開示の第１の実施形態に係る画素の平面構成の一例を示した模式図である。FIG. 2 is a schematic diagram showing an example of a planar configuration of a pixel according to the first embodiment of the present disclosure. 本開示の第１の実施形態の変形例に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 1 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the first embodiment of the present disclosure. 本開示の第１の実施形態の変形例に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 2 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the first embodiment of the present disclosure. 本開示の第２の実施形態に係る画素の断面構成の一例を示した模式図である。FIG. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a second embodiment of the present disclosure. 本開示の第２の実施形態の変形例に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 11 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the second embodiment of the present disclosure. 本開示の第２の実施形態の変形例に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 13 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a modified example of the second embodiment of the present disclosure. 本開示の第３の実施形態に係る画素の平面構成の一例を示した模式図である。FIG. 13 is a schematic diagram showing an example of a planar configuration of a pixel according to a third embodiment of the present disclosure. 本開示の第４の実施形態に係る画素の断面構成の一例を示した模式図である。FIG. 13 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fourth embodiment of the present disclosure. 本開示の第５の実施形態に係る画素の断面構成の一例を示した模式図である。FIG. 13 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fifth embodiment of the present disclosure. 本開示の第６の実施形態に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to a sixth embodiment of the present disclosure. 本開示の第６の実施形態に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to a sixth embodiment of the present disclosure. 本開示の第７の実施形態に係る画素の製造方法を説明するための断面図（その１）である。FIG. 13 is a cross-sectional view (part 1) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure. 本開示の第７の実施形態に係る画素の製造方法を説明するための断面図（その２）である。FIG. 23 is a cross-sectional view (part 2) for explaining a pixel manufacturing method according to the seventh embodiment of the present disclosure. 本開示の第７の実施形態に係る画素の製造方法を説明するための断面図（その３）である。FIG. 23 is a cross-sectional view (part 3) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure. 本開示の第７の実施形態に係る画素の製造方法を説明するための断面図（その４）である。FIG. 13 is a cross-sectional view (part 4) for explaining a pixel manufacturing method according to a seventh embodiment of the present disclosure. 本開示の第８の実施形態に係る画素の要部の断面構成の一例を示した模式図である。13 is a schematic diagram showing an example of a cross-sectional configuration of a main part of a pixel according to an eighth embodiment of the present disclosure. FIG. 本開示の第８の実施形態に係る画素の断面構成の一例を示した模式図である。FIG. 23 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to an eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例１に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例１に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例１に係る画素の断面構成の一例を示した模式図（その３）である。FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 1 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例２に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例２に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例２に係る画素の断面構成の一例を示した模式図（その３）である。FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例２に係る画素の断面構成の一例を示した模式図（その４）である。FIG. 23 is a schematic diagram (part 4) illustrating an example of a cross-sectional configuration of a pixel according to Modification 2 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例３に係る画素の断面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例３に係る画素の断面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例３に係る画素の断面構成の一例を示した模式図（その３）である。FIG. 23 is a schematic diagram (part 3) illustrating an example of a cross-sectional configuration of a pixel according to Modification 3 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例４に係る画素の要部の断面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例４に係る画素の要部の断面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) illustrating an example of a cross-sectional configuration of a main part of a pixel according to Modification 4 of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例５に係る画素の断面構成の一例を示した模式図である。FIG. 23 is a schematic diagram showing an example of a cross-sectional configuration of a pixel according to a fifth modified example of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例６に係る画素の平面構成の一例を示した模式図（その１）である。FIG. 23 is a schematic diagram (part 1) illustrating an example of a planar configuration of a pixel according to a sixth modified example of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例６に係る画素の平面構成の一例を示した模式図（その２）である。FIG. 23 is a schematic diagram (part 2) showing an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例６に係る画素の平面構成の一例を示した模式図（その３）である。FIG. 23 is a schematic diagram (part 3) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例６に係る画素の平面構成の一例を示した模式図（その４）である。FIG. 23 is a schematic diagram (part 4) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure. 本開示の第８の実施形態の変形例６に係る画素の平面構成の一例を示した模式図（その５）である。FIG. 23 is a schematic diagram (part 5) illustrating an example of a planar configuration of a pixel according to the sixth modification of the eighth embodiment of the present disclosure. 本開示の第８の実施形態に係る画素の製造方法を説明するための断面図（その１）である。FIG. 13 is a cross-sectional view (part 1) for explaining a pixel manufacturing method according to an eighth embodiment of the present disclosure. 本開示の第８の実施形態に係る画素の製造方法を説明するための断面図（その２）である。FIG. 23 is a cross-sectional view (part 2) for explaining a manufacturing method of a pixel according to an eighth embodiment of the present disclosure. デジタルスチルカメラの外観の一例を示す正面図である。FIG. 1 is a front view showing an example of the appearance of a digital still camera. デジタルスチルカメラの外観の一例を示す背面図である。FIG. 2 is a rear view showing an example of the appearance of a digital still camera. ヘッドマウントディスプレイの外観図である。FIG. 1 is an external view of a head mounted display. シースルーヘッドマウントディスプレイの外観図である。FIG. 1 is an external view of a see-through head-mounted display. テレビジョン装置の外観図である。FIG. 1 is an external view of a television device. スマートフォンの外観図である。FIG. 1 is an external view of a smartphone. 自動車の内部の構成を示す図（その１）である。FIG. 1 is a diagram showing the internal structure of a vehicle. 自動車の内部の構成を示す図（その２）である。FIG. 2 is a diagram showing the internal structure of a vehicle (part 2).
　以下に、添付図面を参照しながら、本開示の好適な実施の形態について詳細に説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。また、本明細書及び図面において、実質的に同一又は類似の機能構成を有する複数の構成要素を、同一の符号の後に異なるアルファベットを付して区別する場合がある。ただし、実質的に同一又は類似の機能構成を有する複数の構成要素の各々を特に区別する必要がない場合、同一符号のみを付する。 Below, a preferred embodiment of the present disclosure will be described in detail with reference to the attached drawings. Note that in this specification and drawings, components having substantially the same functional configuration will be given the same reference numerals to avoid repeated explanation. Also, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different alphabets after the same reference numerals. However, if there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.
　また、以下の説明で参照される図面は、本開示の一実施形態の説明とその理解を促すための図面であり、わかりやすくするために、図中に示される形状や寸法、比などは実際と異なる場合がある。さらに、図中に示される表示装置は、以下の説明と公知の技術を参酌して適宜、設計変更することができる。 In addition, the drawings referred to in the following description are intended to facilitate the explanation and understanding of one embodiment of the present disclosure, and for ease of understanding, the shapes, dimensions, ratios, etc. shown in the drawings may differ from the actual ones. Furthermore, the display devices shown in the drawings can be modified in design as appropriate, taking into consideration the following explanation and known technologies.
　以下の説明における具体的な長さや形状についての記載は、数学的に定義される数値と同一の値や幾何学的に定義される形状だけを意味するものではない。詳細には、以下の説明における具体的な長さや形状についての記載は、発光素子、表示装置、及び、これらの製造工程、及び、その使用・動作において許容される程度の違い（誤差・ひずみ）がある場合やその形状に類似する形状をも含むものとする。 The descriptions of specific lengths and shapes in the following explanations do not necessarily mean the same values as mathematically defined numerical values or geometrically defined shapes. In more detail, the descriptions of specific lengths and shapes in the following explanations also include shapes that have an allowable degree of difference (error/distortion) in light-emitting elements, display devices, and their manufacturing processes, as well as their use and operation, and shapes that are similar to those shapes.
　また、以下の回路（電気的な接続）の説明においては、特段の断りがない限りは、「電気的に接続」とは、複数の要素の間を電気（信号）が導通するように接続することを意味する。加えて、以下の説明における「電気的に接続」には、複数の要素を直接的に、且つ、電気的に接続する場合だけでなく、他の要素を介して間接的に、且つ、電気的に接続する場合も含むものとする。 In addition, in the following explanation of circuits (electrical connections), unless otherwise specified, "electrically connected" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, in the following explanation, "electrically connected" includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.
　また、以下の説明においては、「共有」とは、互いに異なる要素（例えば、トランジスタ等）間で１つの他の要素（例えば、拡散領域等）を共に利用することである。 In the following description, "sharing" refers to mutual use of one other element (e.g., a diffusion region) between different elements (e.g., transistors, etc.).
　なお、説明は以下の順序で行うものとする。
１．　本開示の実施形態に係る表示装置
　　　１．１　表示装置
　　　１．２　画素
２．　本開示の実施形態を創作するに至る背景
３．　第１の実施形態
　　　３．１　詳細構成
　　　３．２　変形例
４．　第２の実施形態
　　　４．１　詳細構成
　　　４．２　変形例
５．　第３の実施形態
６．　第４の実施形態
７．　第５の実施形態
８．　第６の実施形態
９．　第７の実施形態
１０．　第８の実施形態
　　　１０．１　背景
　　　１０．２　詳細構成
　　　１０．３　変形例１
　　　１０．４　変形例２
　　　１０．５　変形例３
　　　１０．６　変形例４
　　　１０．７　変形例５
　　　１０．８　変形例６
　　　１０．９　製造方法
１１．　まとめ
１２．　適用例
１３．　補足 The explanation will be given in the following order.
1. Display device according to an embodiment of the present disclosure 1.1 Display device 1.2 Pixel 2. Background leading to creation of an embodiment of the present disclosure 3. First embodiment 3.1 Detailed configuration 3.2 Modification 4. Second embodiment 4.1 Detailed configuration 4.2 Modification 5. Third embodiment 6. Fourth embodiment 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Eighth embodiment 10.1 Background 10.2 Detailed configuration 10.3 Modification 1
10.4 Modification 2
10.5 Variation 3
10.6 Variation 4
10.7 Variation 5
10.8 Variation 6
10.9 Manufacturing method 11. Summary 12. Application examples 13. Supplementary information
　＜＜１．　本開示の実施形態に係る表示装置＞＞
　＜１．１　表示装置＞
　まず、図１を参照して、表示装置や照明装置として使用される本開示の実施形態に係る表示装置１０の全体構成の一例を説明する。図１は、本開示の実施形態に係る表示装置１０の全体構成の一例を示す概略図である。 <<1. Display device according to an embodiment of the present disclosure>>
<1.1 Display Device>
First, an example of the overall configuration of a display device 10 according to an embodiment of the present disclosure that is used as a display device or a lighting device will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing an example of the overall configuration of the display device 10 according to an embodiment of the present disclosure.
　表示装置１０は、例えば、ＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、又は、Ｍｉｃｒｏ－ＯＬＥＤ等の発光素子をアレイ状に形成した装置である。このような表示装置１０は、例えば、ＶＲ（Ｖｉｒｔｕａｌ　Ｒｅａｌｉｔｙ）用、ＭＲ（Ｍｉｘｅｄ　Ｒｅａｌｉｔｙ）用、又は、ＡＲ（Ａｕｇｍｅｎｔｅｄ　Ｒｅａｌｉｔｙ）用の表示装置、電子ビューファインダ（Ｅｌｅｃｔｒｏｎｉｃ　Ｖｉｅｗ　Ｆｉｎｄｅｒ：ＥＶＦ）、又は、小型プロジェクタ等に適用することができる。 The display device 10 is a device in which light-emitting elements such as OLEDs (Organic Light Emitting Diodes) or Micro-OLEDs are formed in an array. Such a display device 10 can be used, for example, as a display device for VR (Virtual Reality), MR (Mixed Reality), or AR (Augmented Reality), an electronic viewfinder (EVF), or a small projector.
　また、本開示の実施形態においては、上記発光素子は、自発光型の素子であるとともに、電流駆動型の電気光学素子であればよい。例えば、電流駆動型の電気光学素子としては、ＯＬＥＤの他に、無機ＥＬ素子、ＬＥＤ素子、半導体レーザ素子等を挙げることができる。また、上記発光素子としてＯＬＥＤを用いた有機ＥＬ表示装置は、次のような特長を持つ。詳細には、有機ＥＬ表示装置は、ＯＬＥＤが自発光型の素子であるために、有機ＥＬ表示装置は、同じ平面型の表示装置である液晶表示装置に比べて、画像の視認性が高く、しかも、バックライト等の照明部材を必要としないために軽量化及び薄型化が容易である。更に、ＯＬＥＤの応答速度が数マイクロ秒程度と非常に高速であるために、有機ＥＬ表示装置は、動画表示時の残像が発生しない。 Furthermore, in the embodiment of the present disclosure, the light-emitting element may be a self-luminous element and a current-driven electro-optical element. For example, in addition to OLEDs, examples of current-driven electro-optical elements include inorganic EL elements, LED elements, and semiconductor laser elements. Furthermore, an organic EL display device using OLEDs as the light-emitting elements has the following features. In detail, since OLEDs are self-luminous elements, the organic EL display device has higher image visibility than a liquid crystal display device, which is also a flat display device, and can be easily made lighter and thinner because it does not require lighting components such as a backlight. Furthermore, since the response speed of OLEDs is very fast, on the order of several microseconds, the organic EL display device does not produce afterimages when displaying moving images.
　ここでは、一例として、デバイスに流れる電流値に応じて発光輝度が変化する電流駆動型の発光素子である例えばＯＬＥＤを、発光素子として用いるアクティブマトリクス型有機ＥＬ表示装置の場合を例に挙げて説明するものとする。なお、以下、「アクティブマトリクス型有機ＥＬ表示装置」を単に「表示装置」と称する。 Here, as an example, we will explain the case of an active matrix organic EL display device that uses, as a light emitting element, an OLED, which is a current-driven light emitting element whose light emission brightness changes according to the value of the current flowing through the device. Note that hereinafter, an "active matrix organic EL display device" will be simply referred to as a "display device."
　図１に示すように、表示装置１０は、発光素子を含む複数の画素２０が半導体基板（図示省略）上に行列状（マトリックス状）に２次元配列された画素アレイ部３０と、当該画素アレイ部３０の周辺に配置される駆動回路部とを有する構成となっている。駆動回路部は、例えば、画素アレイ部３０と同じ表示パネル８０上に搭載された書き込み走査部４０、第１駆動走査部５０、第２駆動走査部６０、及び、信号出力部７０を含み、画素アレイ部３０の各画素２０を駆動する。 As shown in FIG. 1, the display device 10 has a pixel array section 30 in which a plurality of pixels 20, each including a light-emitting element, are two-dimensionally arranged in a matrix on a semiconductor substrate (not shown), and a drive circuit section arranged around the pixel array section 30. The drive circuit section includes, for example, a write scan section 40, a first drive scan section 50, a second drive scan section 60, and a signal output section 70 mounted on the same display panel 80 as the pixel array section 30, and drives each pixel 20 of the pixel array section 30.
　ここで、表示装置１０がカラー表示対応の場合は、カラー画像を形成する単位となる１つの画素（単位画素／ピクセル）は複数の副画素（サブピクセル）から構成される。このとき、副画素の各々が図１の画素２０に相当することになる。より具体的には、カラー表示対応の表示装置１０では、１つの画素２０は、例えば、赤色光を発光する副画素、緑色光を発光する副画素、青色光を発光する副画素の３つの副画素から構成されてもよく、例えば、１つ、２つ、またはそれ以上の数の副画素から構成されてもよく、特に限定されるものではない。また、１つの画素２０としては、例えば、赤色、緑色及び青色の３原色の副画素の組み合わせに限られるものではなく、３原色の副画素に、さらに１色あるいは複数色の副画素を加えて１つの画素２０を構成してもよい。より具体的には、表示装置１０は、例えば、輝度向上のために白色光を発光する副画素を加えて１つの画素２０を構成したり、色再現範囲を拡大するために補色光を発光する少なくとも１つの副画素を加えて１つの画素２０を構成したりすることも可能である。 Here, when the display device 10 is capable of color display, one pixel (unit pixel/pixel) which is a unit for forming a color image is composed of multiple sub-pixels. In this case, each of the sub-pixels corresponds to the pixel 20 in FIG. 1. More specifically, in the display device 10 capable of color display, one pixel 20 may be composed of three sub-pixels, for example, a sub-pixel that emits red light, a sub-pixel that emits green light, and a sub-pixel that emits blue light, and may be composed of one, two, or more sub-pixels, and is not particularly limited. In addition, one pixel 20 is not limited to a combination of sub-pixels of the three primary colors, for example, red, green, and blue, and one pixel 20 may be composed by adding sub-pixels of one or more colors to the sub-pixels of the three primary colors. More specifically, the display device 10 can be configured to configure one pixel 20 by adding a sub-pixel that emits white light to improve brightness, or by adding at least one sub-pixel that emits complementary color light to expand the color reproduction range.
　画素アレイ部３０には、ｍ行ｎ列の画素２０の配列に対して、行方向（画素行の画素２０の配列方向／水平方向）に沿って走査線３１（３１１～３１ｍ）、及び、駆動線３２（３２１～３２ｍ）が画素行毎に配線されている。さらに、ｍ行ｎ列の画素２０の配列に対して、列方向（画素列の画素２０の配列方向／垂直方向）に沿って信号線３４（３４１～３４ｎ）が画素列毎に配線されている。 In the pixel array section 30, scanning lines 31 (31 1 to 31 m ) and drive lines 32 (32 1 to 32 m ) are wired for each pixel row along the row direction (arrangement direction of the pixels 20 in the pixel row/horizontal direction) for the arrangement of the pixels 20 in m rows and n columns. Furthermore, signal lines 34 ( 34 1 to 34 n ) are wired for each pixel column along the column direction (arrangement direction of the pixels 20 in the pixel column/vertical direction) for the arrangement of the pixels 20 in m rows and n columns.
　走査線３１１～３１ｍは、書き込み走査部４０の対応する行の出力端にそれぞれ電気的に接続されている。駆動線３２１～３２ｍは、駆動走査部５０の対応する行の出力端にそれぞれ電気的に接続されている。信号線３４１～３４ｎは、信号出力部７０の対応する列の出力端にそれぞれ電気的に接続されている。 The scanning lines 31 1 to 31 m are each electrically connected to an output terminal of a corresponding row of the write scanning section 40. The driving lines 32 1 to 32 m are each electrically connected to an output terminal of a corresponding row of the driving scanning section 50. The signal lines 34 1 to 34 n are each electrically connected to an output terminal of a corresponding column of the signal output section 70.
　書き込み走査部４０は、シフトレジスタ回路等によって構成される。この書き込み走査部４０は、画素アレイ部３０の各画素２０への映像信号の信号電圧の書き込みに際して、走査線３１（３１１～３１ｍ）に対して書き込み走査信号ＷＳ（ＷＳ１～ＷＳｍ）を順次供給することによって画素アレイ部３０の各画素２０を行単位で順番に走査することができる。 The write scanning section 40 is configured with a shift register circuit etc. When writing a signal voltage of a video signal to each pixel 20 of the pixel array section 30, the write scanning section 40 sequentially supplies write scanning signals WS (WS 1 to WS m ) to the scanning lines 31 (31 1 to 31 m ) to sequentially scan each pixel 20 of the pixel array section 30 in row units.
　第１駆動走査部５０は、書き込み走査部４０と同様に、シフトレジスタ回路等によって構成される。この駆動走査部５０は、書き込み走査部４０による線順次走査に同期して、駆動線３２（３２１～３２ｍ）に対して発光制御信号ＤＳ（ＤＳ１～ＤＳｍ）を供給することによって画素２０の発光／非発光（消光）の制御を行うことができる。 The first drive scanning section 50 is configured with a shift register circuit and the like, similar to the write scanning section 40. This drive scanning section 50 can control the emission/non-emission (extinction) of the pixels 20 by supplying light emission control signals DS (DS 1 to DS m ) to the drive lines 32 (32 1 to 32 m ) in synchronization with the line sequential scanning by the write scanning section 40.
　信号出力部７０は、信号供給源（図示省略）から供給される輝度情報に応じた映像信号の信号電圧（以下、単に「信号電圧」と称する）Ｖｓｉｇと基準電圧Ｖｏｆｓとを選択的に出力する。ここで、基準電圧Ｖｏｆｓは、映像信号の信号電圧Ｖｓｉｇの基準となる電圧に相当する電圧、あるいは、その近傍の電圧である。 The signal output unit 70 selectively outputs a signal voltage (hereinafter simply referred to as "signal voltage") Vsig of a video signal corresponding to luminance information supplied from a signal supply source (not shown) and a reference voltage Vofs. Here, the reference voltage Vofs is a voltage equivalent to the reference voltage of the signal voltage Vsig of the video signal, or a voltage close to it.
　信号出力部７０から択一的に出力される信号電圧Ｖｓｉｇ／基準電圧Ｖｏｆｓは、信号線３４（３４１～３４ｎ）を介して画素アレイ部３０の各画素２０に対して、書き込み走査部４０による線順次走査によって選択された画素行の単位で書き込まれる。すなわち、信号出力部７０は、信号電圧Ｖｓｉｇを画素行（ライン）単位で書き込むことができる。 The signal voltage Vsig/reference voltage Vofs alternatively output from the signal output unit 70 is written to each pixel 20 of the pixel array unit 30 via signal lines 34 (34 1 to 34 n ) in units of pixel rows selected by line-sequential scanning by the write scanning unit 40. That is, the signal output unit 70 can write the signal voltage Vsig in units of pixel rows (lines).
　表示装置１０においては、後述する画素２０に含まれる駆動トランジスタＴｒ１（図２　参照）をオフに切り替えることで、画素２０に含まれる発光素子ＥＬ（図２　参照）への電流供給を遮断し、結果として当該発光素子ＥＬの発光が抑制されるため黒階調を表示することができる。しかしながら、駆動トランジスタＴｒ１をオフ状態に切り替えた場合に、当該駆動トランジスタＴｒ１のソース－ドレイン間において電流がリークし、黒階調表示時のコントラストを低下させる場合がある。そこで、黒階調表示時のコントラストの低下を避けるために、表示装置１０の駆動部は、第２駆動走査部６０を有し、さらに、行方向に沿って第２駆動線３３（３３１～３３ｍ）が画素行毎に配線されている。第２駆動線３３１～３３ｍは、第２駆動走査部６０の対応する行の出力端にそれぞれ接続されている。 In the display device 10, by switching off the driving transistor Tr1 (see FIG. 2 ) included in the pixel 20 described later, the current supply to the light-emitting element EL (see FIG. 2 ) included in the pixel 20 is cut off, and as a result, the light emission of the light-emitting element EL is suppressed, so that the black gradation can be displayed. However, when the driving transistor Tr1 is switched to the off state, a current leaks between the source and drain of the driving transistor Tr1, which may reduce the contrast when displaying the black gradation. Therefore, in order to avoid the reduction in contrast when displaying the black gradation, the driving section of the display device 10 has a second driving scanning section 60, and further, second driving lines 33 (33 1 to 33 m ) are wired for each pixel row along the row direction. The second driving lines 33 1 to 33 m are respectively connected to the output terminals of the corresponding rows of the second driving scanning section 60.
　詳細には、第２駆動走査部６０は、書き込み走査部４０と同様に、シフトレジスタ回路等によって構成されている。この第２駆動走査部６０は、書き込み走査部４０による線順次走査に同期して、第２駆動線３３（３３１～３３ｍ）に対して駆動信号ＡＺ（ＡＺ１～ＡＺｍ）を供給することによって非発光期間において画素２０を発光しないようにする制御を行うことができる。 In detail, the second drive scanning section 60 is configured with a shift register circuit and the like, similar to the write scanning section 40. This second drive scanning section 60 supplies drive signals AZ (AZ 1 to AZ m ) to the second drive lines 33 (33 1 to 33 m ) in synchronization with the line sequential scanning by the write scanning section 40, thereby controlling the pixels 20 not to emit light during the non-light emitting period.
　なお、図１に示す全体構成例は、本開示の実施形態の表示装置１０の構成の一例であり、本開示の実施形態に係る表示装置１０の路構成は、図１に示す構成に限定されるものではない。 Note that the overall configuration example shown in FIG. 1 is an example of the configuration of the display device 10 according to the embodiment of the present disclosure, and the path configuration of the display device 10 according to the embodiment of the present disclosure is not limited to the configuration shown in FIG. 1.
　＜１．２　画素＞
　次に、図１に示した本開示の実施形態に係る表示装置１０の画素（画素回路）２０の回路構成について説明する。図２は、本開示の実施形態に係る表示装置１０の画素２０の一例を示した回路図である。 <1.2 Pixels>
Next, a description will be given of a circuit configuration of the pixel (pixel circuit) 20 of the display device 10 according to the embodiment of the present disclosure shown in Fig. 1. Fig. 2 is a circuit diagram showing an example of the pixel 20 of the display device 10 according to the embodiment of the present disclosure.
　本開示の実施形態においては、図２に示すように、画素２０は、発光素子ＥＬとこれを駆動する駆動回路とから構成される。発光素子ＥＬは、デバイスに流れる電流値に応じて発光輝度が変化する電流駆動型の電気光学素子の一例であり、例えば、ＯＬＥＤからなる。発光素子ＥＬのカソードは、例えば電流を輩出するためのノードＶｓｓに電気的に接続されている。 In an embodiment of the present disclosure, as shown in FIG. 2, a pixel 20 is composed of a light-emitting element EL and a drive circuit that drives the light-emitting element EL. The light-emitting element EL is an example of a current-driven electro-optical element whose light emission luminance changes according to the value of the current flowing through the device, and is, for example, an OLED. The cathode of the light-emitting element EL is electrically connected to, for example, a node Vss for outputting a current.
　また、駆動回路は、発光素子ＥＬと電気的に接続される複数のトランジスタ（駆動トランジスタＴｒ１、書込みトランジスタＴｒ２、発光制御トランジスタＴｒ３、スイッチングトランジスタＴｒ４）、及び、容量部Ｃ１、Ｃ２から構成される。発光素子ＥＬのアノードは、駆動トランジスタＴｒ１に電気的に接続され、駆動トランジスタＴｒ１を介して電流が流れると、発光することができる。 The drive circuit is composed of multiple transistors (drive transistor Tr1, write transistor Tr2, light emission control transistor Tr3, switching transistor Tr4) electrically connected to the light emitting element EL, and capacitance units C1 and C2. The anode of the light emitting element EL is electrically connected to the drive transistor Tr1, and when a current flows through the drive transistor Tr1, the light emitting element EL can emit light.
　また、駆動トランジスタ（発光トランジスタとも称される）（第１のトランジスタ）Ｔｒ１及び書込みトランジスタ（データ書き込み制御トランジスタとも称される）（第４のトランジスタ）Ｔｒ２は、例えば、電界効果型トランジスタ（Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ：ＦＥＴ）である。さらに詳細には、駆動トランジスタＴｒ１は、Ｐチャネル型のトランジスタからなり、書込みトランジスタＴｒ２は、Ｎチャネル型のトランジスタからなる。また、発光制御トランジスタ（電源制御トランジスタとも称される）Ｔｒ３（第３のトランジスタ）及びスイッチングトランジスタ（消光制御トランジスタとも称される）（第２のトランジスタ）Ｔｒ４は、例えば、電界効果型トランジスタである。さらに詳細には、発光制御トランジスタＴｒ３は、Ｐチャネル型のトランジスタであり、スイッチングトランジスタＴｒ４は、Ｎチャネル型のトランジスタである。 The driving transistor (also called a light-emitting transistor) (first transistor) Tr1 and the writing transistor (also called a data writing control transistor) (fourth transistor) Tr2 are, for example, field effect transistors (FETs). More specifically, the driving transistor Tr1 is a P-channel transistor, and the writing transistor Tr2 is an N-channel transistor. The light-emitting control transistor (also called a power supply control transistor) Tr3 (third transistor) and the switching transistor (also called a light-extinction control transistor) (second transistor) Tr4 are, for example, field effect transistors. More specifically, the light-emitting control transistor Tr3 is a P-channel transistor, and the switching transistor Tr4 is an N-channel transistor.
　より具体的には、図２に示すように、駆動トランジスタＴｒ１のソース及びドレインは、後述する発光制御トランジスタＴｒ３のドレインを介して電源電圧ＶＤＤの電源ノード（電流源）と発光素子ＥＬのアノード電極とにそれぞれ電気的に接続されている。また、書込みトランジスタＴｒ２のソース及びドレインは、信号線（Ｖｓｉｇ）と駆動トランジスタＴｒ１のゲートとにそれぞれ電気的に接続され、書込みトランジスタＴｒ２のゲートは、走査線（ＷＳ）に電気的に接続されている。また、発光制御トランジスタＴｒ３は、電源電圧ＶＤＤの電源ノードと駆動トランジスタＴｒ１のソースとの間に電気的に接続されている。また、スイッチングトランジスタＴｒ４は、駆動トランジスタＴｒ１のドレインと電流排出先ノードＶｓｓとの間に電気的に接続されている。 More specifically, as shown in Fig. 2, the source and drain of the driving transistor Tr1 are electrically connected to a power supply node (current source) of the power supply voltage V DD and an anode electrode of the light-emitting element EL via the drain of the light-emitting control transistor Tr3 described later. The source and drain of the writing transistor Tr2 are electrically connected to a signal line (Vsig) and the gate of the driving transistor Tr1, respectively, and the gate of the writing transistor Tr2 is electrically connected to a scanning line (WS). The light-emitting control transistor Tr3 is electrically connected between the power supply node of the power supply voltage V DD and the source of the driving transistor Tr1. The switching transistor Tr4 is electrically connected between the drain of the driving transistor Tr1 and a current drain node Vss.
　駆動トランジスタＴｒ１は、後述する容量部Ｃ１の保持電圧（信号電圧）に応じた駆動電流を発光素子ＥＬに供給することによって発光素子ＥＬを駆動することができる。 The driving transistor Tr1 can drive the light-emitting element EL by supplying a driving current to the light-emitting element EL that corresponds to the holding voltage (signal voltage) of the capacitance section C1, which will be described later.
　書込みトランジスタＴｒ２は、信号出力部７０から供給される信号電圧Ｖｓｉｇをサンプリングすることによって駆動トランジスタＴｒ１のゲートに書き込むことができる。なお、ここでの「書き込む」という表現は、ゲートノードに対して信号電圧を印加し、当該ゲートノードの電位が、当該信号電圧に基づく電位に保持されることを意味するものとする。 The write transistor Tr2 can write to the gate of the drive transistor Tr1 by sampling the signal voltage Vsig supplied from the signal output unit 70. Note that the expression "write" here means that a signal voltage is applied to the gate node, and the potential of the gate node is held at a potential based on the signal voltage.
　また、発光制御トランジスタＴｒ３は、発光制御信号ＤＳによる駆動の下で、発光素子ＥＬの発光／非発光を制御する。 In addition, the light emission control transistor Tr3 controls whether the light emitting element EL emits light or not when driven by the light emission control signal DS.
　スイッチングトランジスタＴｒ４は、駆動信号ＡＺによる駆動の下で、発光素子ＥＬの非発光期間に発光素子ＥＬが発光しないように制御する。すなわち、スイッチングトランジスタＴｒ４は、導通状態となることで、発光素子ＥＬに電流が供給されないように、発光素子ＥＬを迂回する経路を形成する（即ち、バイパスする）役目を果たす。このようにすることで、駆動トランジスタＴｒ１をオフ状態に切り替えた際に、当該駆動トランジスタＴｒ１のソース－ドレイン間において電流がリークした場合であっても、スイッチングトランジスタＴｒ４が導通状態となることで、発光素子ＥＬに電流が供給されないようにすることができる。その結果、本構成によれば、黒階調表示時のコントラストの低下を抑制することができる。 The switching transistor Tr4, under the drive signal AZ, controls the light-emitting element EL so that it does not emit light during the non-light-emitting period of the light-emitting element EL. That is, the switching transistor Tr4 becomes conductive, and serves to form a path that detours (i.e., bypasses) the light-emitting element EL so that no current is supplied to the light-emitting element EL. In this way, even if a current leaks between the source and drain of the driving transistor Tr1 when the driving transistor Tr1 is switched to the off state, the switching transistor Tr4 becomes conductive, and therefore no current is supplied to the light-emitting element EL. As a result, with this configuration, it is possible to suppress a decrease in contrast when displaying black gradations.
　また、容量部Ｃ１は、駆動トランジスタＴｒ１のゲートとソースとの間に接続されており、書込みトランジスタＴｒ２によるサンプリングによって書き込まれた信号電圧Ｖｓｉｇを保持する。駆動トランジスタＴｒ１は、容量部Ｃ１の保持電圧に応じた駆動電流を発光素子ＥＬに流すことによって発光素子ＥＬを駆動する。 The capacitance unit C1 is connected between the gate and source of the drive transistor Tr1 and holds the signal voltage Vsig written by sampling by the write transistor Tr2. The drive transistor Tr1 drives the light-emitting element EL by passing a drive current corresponding to the voltage held by the capacitance unit C1 through the light-emitting element EL.
　また、容量部Ｃ２は、駆動トランジスタＴｒ１のソースと、固定電位のノード（例えば、電源電圧ＶＤＤの電源ノード）との間に接続されている。当該容量部Ｃ２は、信号電圧Ｖｓｉｇを書き込んだときに駆動トランジスタＴｒ１のソース電圧が変動するのを抑制するとともに、駆動トランジスタＴｒ１のゲート－ソース間電圧Ｖｇｓを駆動トランジスタＴｒ１の閾値電圧Ｖｔｈにする作用を持つ。 The capacitance unit C2 is connected between the source of the driving transistor Tr1 and a node of a fixed potential (for example, a power supply node of the power supply voltage V DD ). The capacitance unit C2 suppresses fluctuations in the source voltage of the driving transistor Tr1 when the signal voltage Vsig is written, and has the effect of setting the gate-source voltage Vgs of the driving transistor Tr1 to the threshold voltage Vth of the driving transistor Tr1.
　なお、図２に示す回路構成例は、本実施形態の画素２０の回路構成の一例であり、本実施形態に係る画素２０の回路構成は、図２に示す回路構成に限定されるものではない。 Note that the circuit configuration example shown in FIG. 2 is an example of the circuit configuration of the pixel 20 of this embodiment, and the circuit configuration of the pixel 20 of this embodiment is not limited to the circuit configuration shown in FIG. 2.
　＜＜２．　本開示の実施形態を創作するに至る背景＞＞
　次に、本開示の実施形態の詳細を説明する前に、図３を参照して、本発明者らが本開示の実施形態を創作するに至る背景について説明する。図３は、比較例に係る画素２０ａの断面構成の一例を示した模式図である。なお、ここで、比較例とは、本発明者らが本開示の実施形態をなす前に検討を重ねていた画素２０ａのことを意味するものとする。 <<2. Background leading to the creation of the embodiments of the present disclosure>>
Next, before describing the details of the embodiment of the present disclosure, the background that led the present inventors to create the embodiment of the present disclosure will be described with reference to Fig. 3. Fig. 3 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20a according to a comparative example. Note that the comparative example here refers to the pixel 20a that the present inventors had been studying extensively before creating the embodiment of the present disclosure.
　これまで発明者は、図３に示すような画素２０ａの構成を検討してきた。図３に示す比較例では、駆動トランジスタＴｒ１等の画素２０ａの駆動回路に含まれる複数のトランジスタは、半導体基板１００に設けられている。言い換えると、これら複数のトランジスタは、半導体基板１００内にチャネル形成領域を持っている。さらに、これらトランジスタの上方に、発光素子ＥＬが設けられている。 The inventor has previously considered the configuration of pixel 20a as shown in FIG. 3. In the comparative example shown in FIG. 3, multiple transistors included in the drive circuit of pixel 20a, such as drive transistor Tr1, are provided on a semiconductor substrate 100. In other words, these multiple transistors have channel formation regions within the semiconductor substrate 100. Furthermore, a light-emitting element EL is provided above these transistors.
　詳細には、複数のトランジスタは、半導体基板１００内に設けられたチャネルとして機能するｎ型の導電型を持つ領域上に、絶縁膜２０２を介して設けられたゲート電極１０２を有する。さらに、これらトランジスタは、チャネル領域を挟むように半導体基板１００内に設けられ、ｐ型の導電型を持つ不純物を含む拡散領域１０４からなるソース／ドレインを持つ。また、これらトランジスタは、半導体基板１００内に設けられた素子分離部（Ｓｈａｌｌｏｗ　Ｔｒｅｎｃｈ　Ｉｓｏｌａｔｉｏｎ：ＳＴＩ）１０６により、他の素子と分離されている。 In detail, the multiple transistors have gate electrodes 102 provided via an insulating film 202 on a region having n-type conductivity that functions as a channel provided in the semiconductor substrate 100. Furthermore, these transistors have source/drains formed of diffusion regions 104 containing impurities having p-type conductivity provided in the semiconductor substrate 100 on either side of the channel region. Furthermore, these transistors are isolated from other elements by element isolation portions (Shallow Trench Isolation: STI) 106 provided in the semiconductor substrate 100.
　また、図３に示すように、複数のトランジスタが設けられた半導体基板１００上には配線層２００が設けされている。配線層２００は、絶縁膜２０２、配線２０４及びビア２０６が含まれている。さらに、配線層２００上には、発光素子ＥＬである発光部３００が設けられている。発光素子ＥＬは、配線層２００上に設けられたアノード電極３１０と、アノード電極３１０上に積層された光を放射する発光層３１４と、発光層３１４上に積層され、発光層３１４からの光を透過するカソード電極３１２とを有する。 Also, as shown in FIG. 3, a wiring layer 200 is provided on the semiconductor substrate 100 on which a plurality of transistors are provided. The wiring layer 200 includes an insulating film 202, wiring 204, and vias 206. Furthermore, a light-emitting portion 300, which is a light-emitting element EL, is provided on the wiring layer 200. The light-emitting element EL has an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 that emits light and is stacked on the anode electrode 310, and a cathode electrode 312 that is stacked on the light-emitting layer 314 and transmits light from the light-emitting layer 314.
　ところで、上記表示装置１０に対しては、発光素子ＥＬの微細化や多画素化に伴い、画素２０ａの駆動回路における各種トランジスタに求められる耐圧や特性を考慮した上で、駆動回路のレイアウトサイズを小さくすることが求められている。しかしながら、図３からわかるように、複数のトランジスタを半導体基板１００に設けた場合には、駆動回路のレイアウトサイズを小さくすることは難しい。例えば、駆動回路のレイアウトサイズを小さくするために、各トランジスタを構成するソース、ドレイン等の要素を小さくすることが考えられる。しかしながら、このようにした場合、ソース、ドレインの面積が小さくなり、それに伴い、これらと電気的に接続するコンタクトも小さくなることから、量産時に、ソース、ドレインとコンタクトとの間の位置ずれが生じやすくなる。 In the above display device 10, as the light-emitting element EL becomes finer and the number of pixels increases, it is required to reduce the layout size of the drive circuit, taking into consideration the withstand voltage and characteristics required of various transistors in the drive circuit of pixel 20a. However, as can be seen from FIG. 3, it is difficult to reduce the layout size of the drive circuit when multiple transistors are provided on the semiconductor substrate 100. For example, in order to reduce the layout size of the drive circuit, it is possible to reduce the size of the elements such as the source and drain that constitute each transistor. However, in this case, the area of the source and drain becomes smaller, and therefore the contacts that electrically connect to them also become smaller, making it easier for misalignment to occur between the source and drain and the contacts during mass production.
　また、所望の耐圧を満たしつつ、駆動回路に含まれるトランジスタのサイズを小さくすることには限界があり、そのため、駆動回路のレイアウトサイズを小さくすることにも限界がある。特に、発光素子ＥＬとしてＯＬＥＤを使用している場合、ＯＬＥＤの駆動には高電圧を印加することから、例えば駆動トランジスタＴｒ１には高い耐圧が求められることから、駆動トランジスタＴｒ１のレイアウトサイズを小さくすることに限界がある。 In addition, there is a limit to how small the size of the transistors included in the drive circuit can be while still satisfying the desired breakdown voltage, and therefore there is also a limit to how small the layout size of the drive circuit can be. In particular, when an OLED is used as the light-emitting element EL, a high voltage is applied to drive the OLED, and therefore the drive transistor Tr1, for example, is required to have a high breakdown voltage, and therefore there is a limit to how small the layout size of the drive transistor Tr1 can be.
　また、駆動回路に含まれるトランジスタのサイズを小さくすることにより、製造条件が少しでも変化すると、トランジスタの特性が変化することから、より精度よく製造条件を制御することが求められる。すなわち、駆動回路に含まれるトランジスタのサイズを小さくすることにより、所望の特性を持つトランジスタを得ることが難しくなっていた。 In addition, by reducing the size of the transistors included in the drive circuit, even the slightest change in the manufacturing conditions will cause the transistor characteristics to change, so there is a need to control the manufacturing conditions with greater precision. In other words, by reducing the size of the transistors included in the drive circuit, it has become difficult to obtain transistors with the desired characteristics.
　加えて、上記表示装置１０に対しては、発光素子ＥＬの微細化及び多画素化を行った場合であっても、待機時の消費電力をより下げることが求められている。しかしながら、画素２０ａが多くなることにより、駆動回路に含まれるトランジスタの数も多くなることから、消費電力を下げることに限界があった。 In addition, for the display device 10, even when the light-emitting element EL is miniaturized and the number of pixels is increased, there is a demand for further reduction in standby power consumption. However, as the number of pixels 20a increases, the number of transistors included in the drive circuit also increases, so there is a limit to how much power consumption can be reduced.
　そこで、本発明者らは、このような状況を鑑みて、以下に説明する本開示の実施形態を創作するに至った。本発明者らが創作した本開示の実施形態によれば、駆動回路に含まれるトランジスタに対する要求特性を満たしつつ、駆動回路のレイアウトサイズを小さくし、待機時の消費電力も下げることができる。 In light of this situation, the present inventors have come up with the embodiment of the present disclosure described below. The embodiment of the present disclosure created by the present inventors can reduce the layout size of the drive circuit and reduce power consumption during standby while still satisfying the required characteristics for the transistors included in the drive circuit.
　＜＜３．　第１の実施形態＞＞
　＜３．１　詳細構成＞
　まずは、図４Ａ及び図４Ｂを参照して、本開示の第１の実施形態に係る画素２０の詳細構造を説明する。図４Ａは、本開示の第１の実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。また、図４Ｂは、本開示の第１の実施形態に係る画素２０の平面構成の一例を示した模式図であり、詳細には、図４Ａに示されるＡ－Ａ´線で画素２０を切断した際の断面にそれぞれ対応する。なお、図４Ａ及び図４Ｂで示す構成を持つ画素２０は、先に説明した図２に示す回路構成を持つものとする。 <<3. First embodiment>>
3.1 Detailed configuration
First, a detailed structure of the pixel 20 according to the first embodiment of the present disclosure will be described with reference to Figures 4A and 4B. Figure 4A is a schematic diagram showing an example of a cross-sectional configuration of the pixel 20 according to the first embodiment of the present disclosure, and corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Also, Figure 4B is a schematic diagram showing an example of a planar configuration of the pixel 20 according to the first embodiment of the present disclosure, and corresponds to a cross section when the pixel 20 is cut along the line A-A' shown in Figure 4A. Note that the pixel 20 having the configuration shown in Figures 4A and 4B has the circuit configuration shown in Figure 2 described above.
　図４Ａに示すように、本実施形態に係る画素２０は、例えばｎ型の導電型を持つシリコン等からなる半導体基板１００と、当該半導体基板１００上に積層された配線層２００と、当該配線層２００上に設けられた発光素子ＥＬとからなる積層構造を持つ。発光素子ＥＬは、先に説明したように、デバイスに流れる電流値に応じて発光輝度が変化する電流駆動型の電気光学素子である。また、本実施形態においては、半導体基板１００と配線層２００とに、上記発光素子ＥＬを駆動する駆動回路が含まれる。さらに、当該配線層２００は、以下に説明する素子のほかに、絶縁膜２０２（例えば、酸化シリコン膜（ＳｉＯ２）や窒化シリコン膜（Ｓｉ３Ｎ４）等から形成される）、配線２０４（例えば、タングステン（Ｗ）等の金属膜等から形成される）及びビア２０６（例えば、タングステン等の金属膜等から形成される）が含まれる。 As shown in FIG. 4A, the pixel 20 according to the present embodiment has a laminated structure including a semiconductor substrate 100 made of silicon having an n-type conductivity, a wiring layer 200 laminated on the semiconductor substrate 100, and a light-emitting element EL provided on the wiring layer 200. As described above, the light-emitting element EL is a current-driven electro-optical element whose light emission luminance changes according to the current value flowing through the device. In addition, in this embodiment, the semiconductor substrate 100 and the wiring layer 200 include a driving circuit for driving the light-emitting element EL. Furthermore, the wiring layer 200 includes, in addition to the elements described below, an insulating film 202 (formed, for example, of a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 )), a wiring 204 (formed, for example, of a metal film such as tungsten (W)), and a via 206 (formed, for example, of a metal film such as tungsten).
　また、上記駆動回路は、図２を用いて説明したように、駆動トランジスタＴｒ１（図４Ａ中「Ｄｒｖ」と付している）、書込みトランジスタＴｒ２（図４Ａ中「ＷＳ」と付している）、発光制御トランジスタＴｒ３（図４Ａ中「ＤＳ」と付している）、スイッチングトランジスタＴｒ４（図４Ａ中「ＡＺ」と付している）、及び、容量部Ｃ１、Ｃ２を含む。以下、画素２０の積層構造を説明するが、図４Ａの下方に位置する半導体基板１００から説明を開始する。なお、図４Ａにおいては、容量部Ｃ１、Ｃ２については、図示を省略している。 As described with reference to FIG. 2, the drive circuit includes a drive transistor Tr1 (labeled "Drv" in FIG. 4A), a write transistor Tr2 (labeled "WS" in FIG. 4A), a light-emission control transistor Tr3 (labeled "DS" in FIG. 4A), a switching transistor Tr4 (labeled "AZ" in FIG. 4A), and capacitance units C1 and C2. The layered structure of pixel 20 will be described below, starting with the semiconductor substrate 100 located at the bottom in FIG. 4A. Note that the capacitance units C1 and C2 are not shown in FIG. 4A.
　駆動トランジスタＴｒ１は、半導体基板１００に設けられた電界効果型トランジスタであり、詳細には、Ｐチャネル型トランジスタである。詳細には、駆動トランジスタＴｒ１は、図４Ａに示すように、半導体基板１００内に設けられた駆動トランジスタＴｒ１のチャネルとして機能するｎ型の導電型を持つ領域（第１のチャネル形成領域）上に、絶縁膜２０２を介して設けられたゲート電極１０２を有する。さらに、駆動トランジスタＴｒ１は、チャネル形成領域を挟むように半導体基板１００内に設けられ、ｐ型の導電型を持つ不純物を含む拡散領域１０４からなるソース／ドレインを持つ。このように、本実施形態においては、駆動トランジスタＴｒ１を半導体基板１００に設けることにより、駆動トランジスタＴｒ１の特性を安定化させつつ、且つ、高耐圧のトランジスタとすることができる。なお、本実施形態においては、駆動トランジスタＴｒ１は、Ｎチャネル型トランジスタであってもよい。 The driving transistor Tr1 is a field effect transistor provided on the semiconductor substrate 100, and more specifically, a P-channel transistor. In detail, as shown in FIG. 4A, the driving transistor Tr1 has a gate electrode 102 provided via an insulating film 202 on a region (first channel formation region) having n-type conductivity that functions as a channel of the driving transistor Tr1 provided in the semiconductor substrate 100. Furthermore, the driving transistor Tr1 has a source/drain formed of a diffusion region 104 containing an impurity having p-type conductivity provided in the semiconductor substrate 100 so as to sandwich the channel formation region. Thus, in this embodiment, by providing the driving transistor Tr1 on the semiconductor substrate 100, the characteristics of the driving transistor Tr1 can be stabilized and the driving transistor Tr1 can be made a high-voltage transistor. Note that in this embodiment, the driving transistor Tr1 may be an N-channel transistor.
　駆動トランジスタＴｒ１のソース及びドレインは、配線層２００を貫通するビア２０６により、配線層２００内に設けられた電源（ＶＤＤ）と接続する配線２０４と、発光素子ＥＬのアノード電極３１０とに電気的にそれぞれ接続する。さらに、駆動トランジスタＴｒ１のゲート電極１０２は、ビア２０６により、後述する容量部Ｃ１の電極（図示省略）と、書込みトランジスタＴｒ２のソース又はドレインとに、電気的に接続する。 The source and drain of the driving transistor Tr1 are electrically connected to a wiring 204 connected to a power supply (V DD ) provided in the wiring layer 200 and to an anode electrode 310 of the light-emitting element EL by vias 206 that penetrate the wiring layer 200. Furthermore, the gate electrode 102 of the driving transistor Tr1 is electrically connected to an electrode (not shown) of a capacitance section C1 (described later) and the source or drain of the writing transistor Tr2 by the vias 206.
　また、容量部Ｃ１は、駆動トランジスタＴｒ１の上方に積層された配線層２００内に設けてもよい。詳細には、容量部Ｃ１の一方の電極（図示省略）は、先に説明した駆動トランジスタＴｒ１のソース又はドレインに、ビア２０６を介して電気的に接続してもよい。また、容量部Ｃ１の他方の電極（図示省略）は、先に説明した駆動トランジスタＴｒ１のソース又はドレイン、及び、後述する書込みトランジスタＴｒ２のソース又はドレインに、ビア２０６を介して電気的に接続してもよい。 The capacitance unit C1 may also be provided in the wiring layer 200 stacked above the drive transistor Tr1. In particular, one electrode (not shown) of the capacitance unit C1 may be electrically connected to the source or drain of the drive transistor Tr1 described above through a via 206. The other electrode (not shown) of the capacitance unit C1 may also be electrically connected to the source or drain of the drive transistor Tr1 described above and the source or drain of the write transistor Tr2 described below through a via 206.
　さらに、当該駆動トランジスタＴｒ１は、半導体基板１００内に設けられた素子分離部１０６により、他の素子と分離されている。 Furthermore, the driving transistor Tr1 is isolated from other elements by an element isolation section 106 provided in the semiconductor substrate 100.
　また、駆動トランジスタＴｒ１のソース又はドレインは、半導体基板１００内に設けられた拡散領域１０４を、半導体基板１００に設けられた発光制御トランジスタＴｒ３のソース又はドレインと共有する。すなわち、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３は、一方のトランジスタのソース又はドレインと他方のトランジスタのソース又はドレインとして１つの拡散領域１０４を共有するシリーズゲート構造を持つ。なお、本実施形態においては、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３のレイアウト面積の増加を抑えるために、シリーズゲート構造を選択することが好ましいが、本実施形態は、これに限定されるものではない。 The source or drain of the drive transistor Tr1 shares a diffusion region 104 provided in the semiconductor substrate 100 with the source or drain of the light emission control transistor Tr3 provided on the semiconductor substrate 100. That is, the drive transistor Tr1 and the light emission control transistor Tr3 have a series gate structure in which the source or drain of one transistor shares a single diffusion region 104 with the source or drain of the other transistor. In this embodiment, it is preferable to select a series gate structure to prevent an increase in the layout area of the drive transistor Tr1 and the light emission control transistor Tr3, but this embodiment is not limited to this.
　発光制御トランジスタＴｒ３は、駆動トランジスタＴｒ１と同様に、図４Ａに示すように、半導体基板１００内に設けられた発光制御トランジスタＴｒ３のチャネルとして機能するｎ型の導電型を持つ領域（第３のチャネル形成領域）上に、絶縁膜２０２を介して設けられたゲート電極１０２を有する。さらに、発光制御トランジスタＴｒ３は、チャネル形成領域を挟む、ｐ型の導電型を持つ不純物を含む拡散領域１０４からなるソース／ドレインを持つ。このように、本実施形態においては、発光制御トランジスタＴｒ３を半導体基板１００に設けることにより、特性を安定化させつつ、且つ、高駆動力持つ高耐圧のトランジスタとすることができる。さらに、発光制御トランジスタＴｒ３は、半導体基板１００内に設けられた素子分離部１０６により、駆動トランジスタＴｒ１と分離される。 As shown in FIG. 4A, the light emission control transistor Tr3, like the drive transistor Tr1, has a gate electrode 102 provided via an insulating film 202 on a region (third channel formation region) having n-type conductivity that functions as a channel of the light emission control transistor Tr3 provided in the semiconductor substrate 100. Furthermore, the light emission control transistor Tr3 has a source/drain formed of diffusion regions 104 containing p-type conductivity impurities that sandwich the channel formation region. In this way, in this embodiment, by providing the light emission control transistor Tr3 on the semiconductor substrate 100, it is possible to stabilize the characteristics and make it a high-voltage transistor with high driving force. Furthermore, the light emission control transistor Tr3 is separated from the drive transistor Tr1 by an element isolation portion 106 provided in the semiconductor substrate 100.
　また、発光制御トランジスタＴｒ３のソース又はドレインは、ビア２０６により、配線層２００内に設けられた容量部Ｃ２の電極（図示省略）と、電源（ＶＤＤ）と接続する配線２０４とに電気的にそれぞれ接続する。さらに、発光制御トランジスタＴｒ３のゲート電極１０２は、ビア２０６により、発光制御信号ＤＳの信号源と電気的に接続する。 The source or drain of the light emission control transistor Tr3 is electrically connected to an electrode (not shown) of a capacitance unit C2 provided in the wiring layer 200 and to a wiring 204 connected to a power supply (V DD ) by a via 206. Furthermore, the gate electrode 102 of the light emission control transistor Tr3 is electrically connected to a signal source of a light emission control signal DS by a via 206.
　また、容量部Ｃ２は、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３の上方に積層された配線層２００内に設けられていてもよい。詳細には、容量部Ｃ２の一方は、ビア２０６により、先に説明した駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３が共有するソース／ドレインに電気的に接続してもよく、容量部Ｃ２の他方は、ビア２０６を介して、電源（ＶＤＤ）と接続する配線２０４に電気的に接続してもよい。 Furthermore, the capacitance portion C2 may be provided in the wiring layer 200 laminated above the driving transistor Tr1 and the emission control transistor Tr3. In detail, one side of the capacitance portion C2 may be electrically connected to the source/drain shared by the driving transistor Tr1 and the emission control transistor Tr3 described above through a via 206, and the other side of the capacitance portion C2 may be electrically connected through the via 206 to the wiring 204 that is connected to the power supply (V DD ).
　さらに、図４Ａに示す構造においては、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３が設けられた半導体基板１００上に積層された配線層２００内に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４が設けられている。本実施形態においては、駆動回路に含まれる、高い耐圧が所望される駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を半導体基板１００に設け、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４を配線層２００内に設けている。このようにすることで、本実施形態によれば、所定のトランジスタについては高い耐圧を確保しつつ、駆動回路のレイアウトサイズを小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。なお、本実施形態においては、このような構造に限定されるものではなく、書込みトランジスタＴｒ２は、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３と同様に、半導体基板１００に設けられていてもよい。 Furthermore, in the structure shown in FIG. 4A, the write transistor Tr2 and the switching transistor Tr4 are provided in the wiring layer 200 laminated on the semiconductor substrate 100 on which the drive transistor Tr1 and the emission control transistor Tr3 are provided. In this embodiment, the drive transistor Tr1 and the emission control transistor Tr3 included in the drive circuit and for which a high breakdown voltage is desired are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided in the wiring layer 200. In this way, according to this embodiment, it is possible to reduce the layout size of the drive circuit while ensuring a high breakdown voltage for a specified transistor, and thus to reduce the size and miniaturization of the display device 10. Note that this embodiment is not limited to such a structure, and the write transistor Tr2 may be provided on the semiconductor substrate 100, like the drive transistor Tr1 and the emission control transistor Tr3.
　詳細には、本実施形態においては、図４Ａに示すように、書込みトランジスタＴｒ２は、配線層２００内に設けられた薄膜トランジスタ（ＴＦＴ）として構成され、詳細には、Ｎチャネル型トランジスタであることができる。なお、本実施形態においては、書込みトランジスタＴｒ２は、Ｐチャネル型トランジスタであってもよい。より具体的には、書込みトランジスタＴｒ２は、半導体基板１００の上に積層された配線層２００内に設けられた酸化物半導体層２１０と、当該酸化物半導体層２１０と絶縁膜２０２を介して接するゲート電極２１２とを有する。 In detail, in this embodiment, as shown in FIG. 4A, the write transistor Tr2 is configured as a thin film transistor (TFT) provided in the wiring layer 200, and can be an N-channel transistor in detail. Note that in this embodiment, the write transistor Tr2 may be a P-channel transistor. More specifically, the write transistor Tr2 has an oxide semiconductor layer 210 provided in the wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202.
　酸化物半導体層２１０は、例えば、アルミニウム（Ａｌ）、インジウム（Ｉｎ）、ガリウム（Ｇａ）、スズ（Ｓｎ）、及び、亜鉛（Ｚｎ）からなる群から選択される少なくとも１つの元素を含む酸化膜等から形成することができる。より具体的には、酸化物半導体層２１０は、酸化インジウム（Ｉｎ２Ｏ３）、スズ－インジウム酸化物（Ｉｎ２Ｏ３にＳｎをドーパントとして添加、例えば、ＩＴＯ）、インジウム－ガリウム－亜鉛酸化物（ＺｎＯ４にＩｎ及びＧａをドーパントとして添加、例えば、ＩＧＺＯ）、アルミニウム－亜鉛酸化物（ＺｎＯにＡｌをドーパントとして添加、例えばＡＺＯ）、インジウム－亜鉛酸化物（ＺｎＯにＩｎをドーパントとして添加、例えばＩＺＯ）、インジウム－スズ－亜鉛酸化物（ＺｎＯにＩｎ及びＳｎをドーパントとして添加、例えば、ＩＴＺＯ）インジウム－アルミニウム－亜鉛酸化物（ＺｎＯにＩｎ及びＡｌをドーパントとして添加、例えば、ＩＡＺＯ）等から形成することができる。本実施形態においては、これらの酸化物半導体はきわめて小さいリーク電流を持つことから、書込みトランジスタＴｒ２におけるリークを抑制することができる。このようにすることで、本実施形態によれば、低リークのため、長時間の信号保持が可能となることから、待機時のフレームレートを下げて、多画素化に伴う表示装置１０の消費電力の増加を抑えることができる。 The oxide semiconductor layer 210 can be formed from, for example, an oxide film containing at least one element selected from the group consisting of aluminum (Al), indium (In), gallium (Ga), tin (Sn), and zinc (Zn). More specifically, the oxide semiconductor layer 210 can be formed from indium oxide (In 2 O 3 ), tin-indium oxide (In 2 O 3 with Sn added as a dopant, for example, ITO), indium-gallium-zinc oxide (ZnO 4 with In and Ga added as dopants, for example, IGZO), aluminum-zinc oxide (ZnO with Al added as a dopant, for example, AZO), indium-zinc oxide (ZnO with In added as a dopant, for example, IZO), indium-tin-zinc oxide (ZnO with In and Sn added as dopants, for example, ITZO), indium-aluminum-zinc oxide (ZnO with In and Al added as dopants, for example, IAZO), or the like. In this embodiment, these oxide semiconductors have an extremely small leakage current, and therefore leakage in the write transistor Tr2 can be suppressed. By doing this, according to this embodiment, since the leakage is low and a signal can be retained for a long period of time, the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increased number of pixels can be suppressed.
　また、書込みトランジスタＴｒ２は、酸化物半導体層２１０に対して上方にゲート電極（第２のゲート電極）２１２が位置するトップゲート構造として構成されている。しかしながら、本実施形態においては、これに限定されるものではなく、後述するように、書込みトランジスタＴｒ２は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であってもよい。 The write transistor Tr2 is also configured as a top gate structure in which the gate electrode (second gate electrode) 212 is located above the oxide semiconductor layer 210. However, this embodiment is not limited to this, and as described later, the write transistor Tr2 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
　さらに、書込みトランジスタＴｒ２のゲート電極２１２は、半導体基板１００の膜厚方向に沿って延伸する垂直ゲート部（第２の垂直ゲート部）２１２ａを有する。ゲート電極２１２及びその垂直ゲート部２１２ａは、絶縁膜２０２を介して酸化物半導体層２１０と接している。詳細には、酸化物半導体層２１０は、トップゲート構造及び垂直ゲート構造を持つ書込みトランジスタＴｒ２にあわせて、図４Ａに示す断面において、垂直ゲート部２１２ａに沿って下方に突出した凸形状部である領域２１０ａを持っている。そして、書込みトランジスタＴｒ２は、酸化物半導体層２１０内であって、ゲート電極２１２及びその垂直ゲート部２１２ａと絶縁膜２０２を介して接している凸形状部である領域２１０ａにチャネル形成領域（第４のチャネル形成領域）を持つ。さらに、本実施形態においては、書込みトランジスタＴｒ２のソース及びドレインは、酸化物半導体層２１０における凸形状部である領域２１０ａを挟み込む一対の領域２１０ｂに位置することとなる。 Furthermore, the gate electrode 212 of the write transistor Tr2 has a vertical gate portion (second vertical gate portion) 212a extending along the film thickness direction of the semiconductor substrate 100. The gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202. In detail, the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 4A in accordance with the write transistor Tr2 having a top gate structure and a vertical gate structure. The write transistor Tr2 has a channel formation region (fourth channel formation region) in the region 210a that is a convex portion that is in contact with the gate electrode 212 and its vertical gate portion 212a via the insulating film 202 within the oxide semiconductor layer 210. Furthermore, in this embodiment, the source and drain of the write transistor Tr2 are located in a pair of regions 210b that sandwich the region 210a, which is a convex portion of the oxide semiconductor layer 210.
　本実施形態においては、書込みトランジスタＴｒ２のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積（フットプリント）を拡大することなく、ゲート長を容易に長くすることができる。また、ソース、ドレインにコンタクトを形成する際に、水素がチャネル形成領域へ拡散し、チャネル形成領域内のダングリングボンドと結合しチャネル形成領域の特性が変動することがある。それに対して、本実施形態においては、垂直ゲート部２１２ａを長くすること（アスペクト比を大きくする）により、書込みトランジスタＴｒ２のチャネル形成領域からソース、ドレインをより離すことができることから、上記特性変動を抑制することができる。 In this embodiment, by making the gate electrode 212 of the write transistor Tr2 a vertical gate structure, the gate length can be easily increased without expanding the layout area (footprint). In addition, when forming contacts at the source and drain, hydrogen can diffuse into the channel formation region and bond with dangling bonds in the channel formation region, causing fluctuations in the characteristics of the channel formation region. In contrast, in this embodiment, by making the vertical gate portion 212a longer (increasing the aspect ratio), the source and drain can be separated further from the channel formation region of the write transistor Tr2, thereby suppressing the above-mentioned characteristic fluctuations.
　書込みトランジスタＴｒ２のゲート電極２１２及び垂直ゲート部２１２ａは、例えば、シリコン、アルミニウム、チタン（Ｔｉ）、及び、モリブデン（Ｍｏ）からなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成することができる。 The gate electrode 212 and vertical gate portion 212a of the write transistor Tr2 can be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo).
　また、書込みトランジスタＴｒ２のソース又はドレインは、ビア（コンタクトホール）２０６により、配線層２００内に設けられた配線２０４（信号電圧Ｖｓｉｇ）に電気的に接続する。上記ビア２０６は、酸化物半導体層２１０の領域２１０ｂの上面と接している。さらに、書込みトランジスタＴｒ２のゲート電極２１２は、ビア２０６により、走査線（ＷＳ）と接続する配線２０４に電気的に接続する。 The source or drain of the write transistor Tr2 is electrically connected to a wiring 204 (signal voltage Vsig) provided in the wiring layer 200 through a via (contact hole) 206. The via 206 is in contact with the upper surface of the region 210b of the oxide semiconductor layer 210. The gate electrode 212 of the write transistor Tr2 is electrically connected to the wiring 204, which is connected to the scanning line (WS), through the via 206.
　また、本実施形態においては、図４Ａに示すように、スイッチングトランジスタＴｒ４は、書込みトランジスタＴｒ２と同様に、配線層２００内に設けられた薄膜トランジスタ（ＴＦＴ）として構成され、例えば、Ｎチャネル型トランジスタであることができる。なお、本実施形態においては、このような構造に限定されるものではなく、スイッチングトランジスタＴｒ４は、駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３と同様に、半導体基板１００に設けられていてもよい。 In addition, in this embodiment, as shown in FIG. 4A, the switching transistor Tr4 is configured as a thin film transistor (TFT) provided in the wiring layer 200, similar to the write transistor Tr2, and can be, for example, an N-channel transistor. Note that this embodiment is not limited to this structure, and the switching transistor Tr4 may be provided on the semiconductor substrate 100, similar to the drive transistor Tr1 and the light emission control transistor Tr3.
　詳細には、スイッチングトランジスタＴｒ４は、配線層２００内に設けられた酸化物半導体層２１０と、当該酸化物半導体層２１０と絶縁膜２０２を介して接するゲート電極２１２とを有する。酸化物半導体層２１０は、上述したように、例えば、アルミニウム、インジウム、ガリウム、スズ、及び、亜鉛からなる群から選択される少なくとも１つの元素を含む酸化膜等から形成することができる。より具体的には、酸化物半導体層２１０は、酸化インジウム（Ｉｎ２Ｏ３）、スズ－インジウム酸化物（ＩＴＯ）、インジウム－ガリウム－亜鉛酸化物（ＩＧＺＯ）、アルミニウム－亜鉛酸化物（ＡＺＯ）、インジウム－亜鉛酸化物（ＩＺＯ）、インジウム－スズ－亜鉛酸化物（ＩＴＺＯ）インジウム－アルミニウム－亜鉛酸化物（ＩＡＺＯ）等から形成することができる。本実施形態においては、これらの酸化物半導体はきわめて小さいリーク電流を持つことから、スイッチングトランジスタＴｒ４におけるリークを抑制することができる。このようにすることで、本実施形態によれば、過渡応答時のリーク電流が抑制されるため、黒浮きが低減され、コントラストが向上する。さらに、スイッチングトランジスタＴｒ４をＮチャネル型トランジスタとして形成することが容易である。そのため、Ｎチャネル型トランジスタであるスイッチングトランジスタＴｒ４により、発光素子ＥＬのカソード－アノード間を０Ｖに安定的に制御することが可能となり、発光素子ＥＬに電流が供給されないようにすることができる。その結果、本実施形態によれば、黒階調表示時のコントラストの低下を抑制することができる。 In detail, the switching transistor Tr4 has an oxide semiconductor layer 210 provided in the wiring layer 200 and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202. As described above, the oxide semiconductor layer 210 can be formed of, for example, an oxide film containing at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc. More specifically, the oxide semiconductor layer 210 can be formed of indium oxide (In 2 O 3 ), tin-indium oxide (ITO), indium-gallium-zinc oxide (IGZO), aluminum-zinc oxide (AZO), indium-zinc oxide (IZO), indium-tin-zinc oxide (ITZO), indium-aluminum-zinc oxide (IAZO), or the like. In this embodiment, these oxide semiconductors have an extremely small leakage current, so that leakage in the switching transistor Tr4 can be suppressed. In this way, according to this embodiment, leakage current during a transient response is suppressed, so that black floating is reduced and contrast is improved. Furthermore, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode voltage of the light-emitting element EL to 0 V, so that no current is supplied to the light-emitting element EL. As a result, according to this embodiment, it is possible to suppress a decrease in contrast when displaying black gradations.
　また、スイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して上方にゲート電極（第１のゲート電極）２１２が位置するトップゲート構造として構成されている。しかしながら、本実施形態においては、これに限定されるものではなく、後述するように、スイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であってもよい。 The switching transistor Tr4 is also configured as a top gate structure in which the gate electrode (first gate electrode) 212 is located above the oxide semiconductor layer 210. However, this embodiment is not limited to this, and as described later, the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
　さらに、スイッチングトランジスタＴｒ４のゲート電極２１２は、半導体基板１００の膜厚方向に沿って延伸する垂直ゲート部（第１の垂直ゲート部）２１２ａを有する。ゲート電極２１２及びその垂直ゲート部２１２ａは、絶縁膜２０２を介して酸化物半導体層２１０と接している。詳細には、酸化物半導体層２１０は、トップゲート構造及び垂直ゲート構造を持つスイッチングトランジスタＴｒ４にあわせて、図４Ａに示す断面において、垂直ゲート部２１２ａに沿って下方に突出した凸形状部である領域２１０ａを持っている。そして、スイッチングトランジスタＴｒ４は、酸化物半導体層２１０内であって、ゲート電極２１２及びその垂直ゲート部２１２ａと絶縁膜２０２を介して接している凸形状部である領域２１０ａにチャネル形成領域（第２のチャネル形成領域）を持つ。また、本実施形態においては、スイッチングトランジスタＴｒ４のソース及びドレインは、酸化物半導体層２１０における凸形状部である領域２１０ａを挟み込む一対の領域２１０ｂに位置することとなる。 Furthermore, the gate electrode 212 of the switching transistor Tr4 has a vertical gate portion (first vertical gate portion) 212a extending along the film thickness direction of the semiconductor substrate 100. The gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 via the insulating film 202. In detail, the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 4A in accordance with the switching transistor Tr4 having a top gate structure and a vertical gate structure. The switching transistor Tr4 has a channel formation region (second channel formation region) in the region 210a that is a convex portion in the oxide semiconductor layer 210 and that is in contact with the gate electrode 212 and its vertical gate portion 212a via the insulating film 202. In this embodiment, the source and drain of the switching transistor Tr4 are located in a pair of regions 210b that sandwich the region 210a that is a convex portion in the oxide semiconductor layer 210.
　本実施形態においては、スイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積を拡大することなく、ゲート長を容易に長くすることができる。また、ソース、ドレインにコンタクトを形成する際に、水素がチャネル形成領域へ拡散し、チャネル形成領域内のダングリングボンドと結合しチャネル形成領域の特性が変動することがある。それに対して、本実施形態においては、垂直ゲート部２１２ａを長くすることにより、スイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、上記特性変動を抑制することができる。 In this embodiment, by making the gate electrode 212 of the switching transistor Tr4 a vertical gate structure, the gate length can be easily increased without expanding the layout area. In addition, when forming contacts at the source and drain, hydrogen can diffuse into the channel formation region and bond with dangling bonds in the channel formation region, causing the characteristics of the channel formation region to fluctuate. In contrast, in this embodiment, by making the vertical gate portion 212a longer, the source and drain can be separated further from the channel formation region of the switching transistor Tr4, thereby suppressing the above-mentioned characteristic fluctuations.
　スイッチングトランジスタＴｒ４のゲート電極２１２及び垂直ゲート部２１２ａは、例えば、シリコン、アルミニウム、チタン（Ｔｉ）、及び、モリブデン（Ｍｏ）からなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成することができる。 The gate electrode 212 and vertical gate portion 212a of the switching transistor Tr4 can be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of silicon, aluminum, titanium (Ti), and molybdenum (Mo).
　また、スイッチングトランジスタＴｒ４のソース又はドレインは、ビア２０６により、配線層２００上に設けられた発光素子ＥＬのアノード電極３１０と電気的に接続する。上記ビア２０６は、酸化物半導体層２１０の領域２１０ｂの上面と接している。さらに、スイッチングトランジスタＴｒ４のゲート電極２１２は、ビア２０６により、駆動信号源（ＡＺ）と接続する配線２０４に電気的に接続する。 The source or drain of the switching transistor Tr4 is electrically connected to the anode electrode 310 of the light-emitting element EL provided on the wiring layer 200 through a via 206. The via 206 is in contact with the upper surface of the region 210b of the oxide semiconductor layer 210. Furthermore, the gate electrode 212 of the switching transistor Tr4 is electrically connected to the wiring 204 that is connected to the drive signal source (AZ) through the via 206.
　さらに、図４Ａに示す構造においては、スイッチングトランジスタＴｒ４及び書込みトランジスタＴｒ２は、画素２０の積層構造において、同一高さ、すなわち、同一層に設けられている。しかしながら、本実施形態においては、これに限定されるものではなく、例えば、スイッチングトランジスタＴｒ４及び書込みトランジスタＴｒ２は、画素２０の積層構造において、異なる高さ、すなわち、異なる層に設けられ、互いに積層されていてもよい。 Furthermore, in the structure shown in FIG. 4A, the switching transistor Tr4 and the writing transistor Tr2 are provided at the same height, i.e., in the same layer, in the stacked structure of the pixel 20. However, this is not limited to this in the present embodiment, and for example, the switching transistor Tr4 and the writing transistor Tr2 may be provided at different heights, i.e., in different layers, and stacked on top of each other in the stacked structure of the pixel 20.
　また、図４Ａに示すように、配線層２００上には、発光素子ＥＬである発光部３００が設けられている。発光素子ＥＬは、配線層２００上に設けられたアノード電極３１０と、アノード電極３１０上に積層された光を放射する発光層３１４と、発光層３１４上に積層され、発光層３１４からの光を透過するカソード電極３１２と主に有する。 Also, as shown in FIG. 4A, a light-emitting unit 300, which is a light-emitting element EL, is provided on the wiring layer 200. The light-emitting element EL mainly comprises an anode electrode 310 provided on the wiring layer 200, a light-emitting layer 314 that is laminated on the anode electrode 310 and emits light, and a cathode electrode 312 that is laminated on the light-emitting layer 314 and transmits light from the light-emitting layer 314.
　アノード電極３１０は、反射層としての機能を兼ね備えてもよく、できるだけ反射率が高く、かつ仕事関数が大きい金属膜によって構成されることが光の取り出し効率を高める上で好ましい。このような金属膜としては、例えば、クロム（Ｃｒ）、金（Ａｕ）、白金（Ｐｔ）、ニッケル（Ｎｉ）、銅（Ｃｕ）、モリブデン、チタン、タンタル（Ｔａ）、アルミニウム、マグネシウム（Ｍｇ）、鉄（Ｆｅ）、タングステン、銀（Ａｇ）等の金属元素の単体及び合金のうちの少なくとも１種を含む金属膜を挙げることができる。 The anode electrode 310 may also function as a reflective layer, and is preferably made of a metal film with as high a reflectivity and a large work function as possible in order to increase the light extraction efficiency. Examples of such metal films include metal films containing at least one of the simple substances and alloys of metal elements such as chromium (Cr), gold (Au), platinum (Pt), nickel (Ni), copper (Cu), molybdenum, titanium, tantalum (Ta), aluminum, magnesium (Mg), iron (Fe), tungsten, and silver (Ag).
　また、アノード電極３１０上に設けられた発光層３１４は、有機材料又は無機材料からなり、例えば白色光を放射することができる層である。また、発光層３１４は、アノード電極３１０に隣接して設けられた正孔注入層（図示省略）及び正孔輸送層（図示省略）と、カソード電極３１２に隣接して設けられた電子輸送層（図示省略）とを有していてもよい。言い換えると、発光層３１４は、アノード電極３１０側から、正孔注入層と、正孔輸送層と、発光層３１４と、電子輸送層（図示省略）とが積層された構造を有することができる。なお、正孔注入層は、発光層３１４への正孔注入効率を高める層として機能するとともに、リークを抑制するためのバッファ層として機能する。正孔輸送層は、発光層３１４への正孔輸送効率を高める層として機能する。また、発光層３１４は、電界が発生することにより、電子と正孔との再結合が起こり、光を発生することができる。電子輸送層は、発光層３１４への電子輸送効率を高める層として機能する。さらに、発光層３１４は、電子輸送層とカソード電極３１２との間に、電子注入層（図示省略）を有していてもよい。当該電子注入層は、電子注入効率を高める層として機能する。なお、本実施形態においては、発光層３１４の構成は上述したような構成に限定されるものではなく、正孔注入層及び発光層３１４以外の層は必要に応じて設けることができる。 The light-emitting layer 314 provided on the anode electrode 310 is made of an organic material or an inorganic material, and is a layer capable of emitting, for example, white light. The light-emitting layer 314 may have a hole injection layer (not shown) and a hole transport layer (not shown) provided adjacent to the anode electrode 310, and an electron transport layer (not shown) provided adjacent to the cathode electrode 312. In other words, the light-emitting layer 314 may have a structure in which a hole injection layer, a hole transport layer, the light-emitting layer 314, and an electron transport layer (not shown) are stacked from the anode electrode 310 side. The hole injection layer functions as a layer that increases the efficiency of hole injection into the light-emitting layer 314, and also functions as a buffer layer for suppressing leakage. The hole transport layer functions as a layer that increases the efficiency of hole transport into the light-emitting layer 314. The light-emitting layer 314 can generate light by recombining electrons and holes due to the generation of an electric field. The electron transport layer functions as a layer that increases the efficiency of transporting electrons to the light-emitting layer 314. Furthermore, the light-emitting layer 314 may have an electron injection layer (not shown) between the electron transport layer and the cathode electrode 312. The electron injection layer functions as a layer that increases the efficiency of electron injection. In this embodiment, the configuration of the light-emitting layer 314 is not limited to the configuration described above, and layers other than the hole injection layer and the light-emitting layer 314 can be provided as necessary.
　また、本実施形態においては、発光層３１４は、白色光を放射する層に限定されるものではなく、赤色光（例えば、６４０ｎｍ～７７０ｎｍ程度の波長を持つ可視光）、青色光（例えば、４３０ｎｍ～４９０ｎｍ程度の波長を持つ可視光）、緑色光（例えば、４９０ｎｍ～５５０ｎｍ程度の波長を持つ可視光）を放射する層であってもよい。 In addition, in this embodiment, the light-emitting layer 314 is not limited to a layer that emits white light, but may be a layer that emits red light (for example, visible light having a wavelength of about 640 nm to 770 nm), blue light (for example, visible light having a wavelength of about 430 nm to 490 nm), or green light (for example, visible light having a wavelength of about 490 nm to 550 nm).
　また、発光層３１４上に設けられたカソード電極３１２は、発光層３１４で発生した光に対して透過性を有する透明電極であり、以下の説明において、透明電極には、半透過性電極も含まれるものとする。カソード電極３１２は、アルミニウム、マグネシウム、カルシウム（Ｃａ）、ナトリウム（Ｎａ）、銀、インジウム、亜鉛等の金属元素の単体及び合金のうちの少なくとも１種を含む金属膜又は酸化膜等から形成することができる。 The cathode electrode 312 provided on the light-emitting layer 314 is a transparent electrode that is transparent to the light generated in the light-emitting layer 314, and in the following description, the transparent electrode also includes a semi-transparent electrode. The cathode electrode 312 can be formed from a metal film or an oxide film containing at least one of the simple substances and alloys of metal elements such as aluminum, magnesium, calcium (Ca), sodium (Na), silver, indium, and zinc.
　さらに、図４Ｂに示すように、酸化物半導体層２１０に設けられる書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視においては、帯状の酸化物半導体層２１０上にゲート電極２１２（詳細には、図４Ｂ中では、垂直ゲート部２１２ａが図示）が設けられ、ゲート電極２１２を挟みこむように、トランジスタのソース、ドレインと電気的に接続される一対のビア２１４が設けられている。さらに、当該平面視においては、ゲート電極２１２の中心と、一対のビア２１４との中心とが１つの線上に配列する。 Furthermore, as shown in FIG. 4B, in a plan view of the write transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210, a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 4B) is provided on the strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor are provided to sandwich the gate electrode 212. Furthermore, in this plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are aligned on a single line.
　以上のように、本実施形態によれば、駆動回路に含まれるトランジスタに対する要求特性を満たしつつ、駆動回路のレイアウトサイズを小さくし、且つ、待機時の消費電力も下げることができる。 As described above, according to this embodiment, it is possible to reduce the layout size of the drive circuit and reduce power consumption during standby while satisfying the required characteristics of the transistors included in the drive circuit.
　詳細には、本実施形態においては、駆動回路に含まれる駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を半導体基板１００に設け、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４を、薄膜トランジスタ（ＴＦＴ）として、半導体基板１００上に積層された配線層２００内に設けている。このようにすることで、本実施形態によれば、所定のトランジスタについては高い耐圧を確保しつつ、駆動回路のレイアウトサイズを小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。 In detail, in this embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 laminated on the semiconductor substrate 100. In this way, according to this embodiment, it is possible to reduce the layout size of the drive circuit while ensuring a high withstand voltage for certain transistors, and ultimately to make the display device 10 smaller and finer.
　また、本実施形態においては、薄膜トランジスタ（ＴＦＴ）である書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域を酸化物半導体層２１０で形成することにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のリークを抑えることができる。詳細には、本実施形態によれば、書込みトランジスタＴｒ２におけるリークを抑制することができることから、長時間の信号保持が可能となることから、待機時のフレームレートを下げて、多画素化に伴う表示装置１０の消費電力の増加を抑えることができる。また、本実施形態によれば、スイッチングトランジスタＴｒ４におけるリークを抑制することができることから、黒浮きが低減され、コントラストが向上し、表示装置１０の消費電力の増加を抑えることができる。さらに、本実施形態によれば、スイッチングトランジスタＴｒ４をＮチャネル型トランジスタとして形成することが容易である。そのため、Ｎチャネル型トランジスタであるスイッチングトランジスタＴｒ４により、発光素子ＥＬのカソード－アノード間を０Ｖに安定的に制御することが可能となり、発光素子ＥＬに電流が供給されないようにすることができる。その結果、本実施形態によれば、黒階調表示時のコントラストの低下を抑制することができる。 In addition, in this embodiment, the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs), are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4. In detail, according to this embodiment, leakage from the write transistor Tr2 can be suppressed, and therefore a signal can be held for a long time, and the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increase in the number of pixels can be suppressed. In addition, according to this embodiment, leakage from the switching transistor Tr4 can be suppressed, and therefore black floating can be reduced, the contrast can be improved, and the increase in power consumption of the display device 10 can be suppressed. Furthermore, according to this embodiment, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode of the light-emitting element EL to 0 V, and it is possible to prevent current from being supplied to the light-emitting element EL. As a result, according to this embodiment, it is possible to suppress a decrease in contrast when displaying black gradations.
　さらに、本実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積を拡大することなく、ゲート長を容易に長くすることができる。さらに、垂直ゲート部２１２ａを長くすることにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することを抑制することができる。 Furthermore, in this embodiment, by making the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure, the gate length can be easily increased without expanding the layout area. Furthermore, by lengthening the vertical gate portion 212a, the source and drain can be further away from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause the characteristics of the channel formation region to fluctuate.
　なお、本実施形態においては、画素２０は、図４Ａ及び図４Ｂに示すような構成に限定されるものではない。例えば、半導体基板１００に設けられるトランジスタ、及び、配線層２００内の酸化物半導体層２１０に設けられるトランジスタは、図４Ａに示す構成に限定されるものではなく、少なくとも１つのトランジスタが半導体基板１００に設けられ、少なくとも他の１つのトランジスタが酸化物半導体層２１０に設けられている限り、自由に組み合わせることができる。また、本実施形態においては、画素２０の駆動回路に含まれるトランジスタの数も４つであることに限定されるものではなく、２つ以上であれば特に限定されるものではない。 In this embodiment, the pixel 20 is not limited to the configuration shown in FIG. 4A and FIG. 4B. For example, the transistors provided in the semiconductor substrate 100 and the transistors provided in the oxide semiconductor layer 210 in the wiring layer 200 are not limited to the configuration shown in FIG. 4A, and can be freely combined as long as at least one transistor is provided in the semiconductor substrate 100 and at least one other transistor is provided in the oxide semiconductor layer 210. In this embodiment, the number of transistors included in the drive circuit of the pixel 20 is not limited to four, and is not particularly limited as long as it is two or more.
　＜３．２　変形例＞
　また、本実施形態は以下のように変形することもできる。そこで、図５及び図６を参照して、本実施形態の変形例を説明する。図５及び図６は、本実施形態の変形例に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 3.2 Modifications
This embodiment can also be modified as follows. A modified example of this embodiment will now be described with reference to Figs. 5 and 6. Figs. 5 and 6 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a modified example of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 shown to be located on the lower side. Note that in these figures, the capacitance sections C1 and C2 are omitted from illustration.
　本変形例においては、図５に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の下面に接する導電層２２０が設けられている。本変形例においては、導電層２２０を設けることにより、酸化物半導体層２１０の形成時に、導電層２２０がヒートシンクのように機能して温度勾配を生じさせることから、酸化物半導体層２１０の結晶性に勾配を生じさせることができる。 In this modification, as shown in FIG. 5, a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4. In this modification, by providing the conductive layer 220, when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, and therefore a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
　導電層２２０は、例えば、アルミニウム、チタン（Ｔｉ）、タンタル（Ｔａ）及び、モリブデン（Ｍｏ）からなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成されてもよい。より具体的には、導電層２２０は、アルミニウム、チタン、タンタル、窒化チタン、窒化タンタル、アルミニウム－チタン合金、シリコン－チタン合金、モリブデン等から形成することができる。 The conductive layer 220 may be formed from, for example, a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium (Ti), tantalum (Ta), and molybdenum (Mo). More specifically, the conductive layer 220 may be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, aluminum-titanium alloy, silicon-titanium alloy, molybdenum, etc.
　本変形例においては、図６に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の上面に接する導電層２２２が設けられている。本変形例においては、導電層２２２を設けることにより、酸化物半導体層２１０の形成時に、導電層２２０がヒートシンクのように機能して温度勾配を生じさせることから、酸化物半導体層２１０の結晶性に勾配を生じさせることができる。さらに、本変形例によれば、導電層２２２により、ソース、ドレインにコンタクトを形成する際に、酸化物半導体層２１０にダメージを生じることを抑制することができる。加えて、ソース、ドレインにコンタクトを形成する際に水素、酸素が拡散した場合には、これらが酸化還元を行いキャリア濃度が変動することがあるが、本変形例においては、導電層２２２により、コンタクトを形成する際の水素、酸素の拡散を抑制することができる。 In this modification, as shown in FIG. 6, a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4. In this modification, the conductive layer 222 functions as a heat sink to generate a temperature gradient during the formation of the oxide semiconductor layer 210, and a gradient can be generated in the crystallinity of the oxide semiconductor layer 210. Furthermore, according to this modification, the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when contacts are formed at the source and drain. In addition, if hydrogen or oxygen diffuses when contacts are formed at the source and drain, these may cause oxidation and reduction, resulting in a change in carrier concentration. However, in this modification, the conductive layer 222 can suppress the diffusion of hydrogen and oxygen when the contacts are formed.
　導電層２２２は、導電層２２０と同様に、例えば、アルミニウム、チタン、タンタル及び、モリブデンからなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成されてもよい。より具体的には、導電層２２２は、アルミニウム、チタン、タンタル、窒化チタン、窒化タンタル、アルミニウム－チタン合金、シリコン－チタン合金、モリブデン等から形成することができる。 Similar to the conductive layer 220, the conductive layer 222 may be formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum. More specifically, the conductive layer 222 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, aluminum-titanium alloy, silicon-titanium alloy, molybdenum, etc.
　なお、本変形例においては、画素２０は、図５及び図６に示すような構成に限定されるものではない。 In this modified example, the pixel 20 is not limited to the configuration shown in Figures 5 and 6.
　＜＜４．　第２の実施形態＞＞
　＜４．１　詳細構成＞
　次に、図７を参照して、本開示の第２の実施形態を説明する。図７は、本実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、図７においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <<4. Second embodiment>>
4.1 Detailed configuration
Next, a second embodiment of the present disclosure will be described with reference to Fig. 7. Fig. 7 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 7, the capacitance parts C1 and C2 are omitted from the illustration.
　本実施形態においては、第１の実施形態と同様に、スイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にしているものの、図７に示すように、書込みトランジスタＴｒ２のゲート電極２１２は、酸化物半導体層２３０上に平板状のゲート電極２３２を持つ、平板ゲート電極構造としている。 In this embodiment, as in the first embodiment, the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, but as shown in FIG. 7, the gate electrode 212 of the write transistor Tr2 has a flat gate electrode structure having a flat gate electrode 232 on the oxide semiconductor layer 230.
　以上のように、本実施形態によれば、駆動回路に含まれるトランジスタに対する要求特性を満たしつつ、駆動回路のレイアウトサイズを小さくし、且つ、待機時の消費電力も下げることができる。詳細には、本実施形態においては、駆動回路に含まれる駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を半導体基板１００に設け、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４を、薄膜トランジスタ（ＴＦＴ）として、半導体基板１００上に積層された配線層２００内に設けている。このようにすることで、本実施形態によれば、所定のトランジスタについては高い耐圧を確保しつつ、駆動回路のレイアウトサイズを小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。さらに、本実施形態においても、薄膜トランジスタ（ＴＦＴ）である書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域を酸化物半導体層２１０で形成することにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のリークを抑えることができる。 As described above, according to this embodiment, the layout size of the drive circuit can be reduced while satisfying the required characteristics of the transistors included in the drive circuit, and the power consumption during standby can also be reduced. In detail, in this embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 stacked on the semiconductor substrate 100. In this way, according to this embodiment, the layout size of the drive circuit can be reduced while ensuring a high withstand voltage for a certain transistor, and the display device 10 can be made smaller and finer. Furthermore, in this embodiment, the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs), are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4.
　さらに、本実施形態においては、スイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積を拡大することなく、ゲート長を容易に長くすることができる。さらに、垂直ゲート部２１２ａを長くすることにより、スイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することを抑制することができる。 Furthermore, in this embodiment, by making the gate electrode 212 of the switching transistor Tr4 a vertical gate structure, the gate length can be easily increased without expanding the layout area. Furthermore, by lengthening the vertical gate portion 212a, the source and drain can be separated further from the channel formation region of the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause fluctuations in the characteristics of the channel formation region.
　なお、本実施形態においては、画素２０は、図７に示すような構成に限定されるものではない。例えば、書込みトランジスタＴｒ２のゲート電極２１２を、垂直ゲート構造にして、スイッチングトランジスタＴｒ４のゲート電極２１２を、平板ゲート電極構造としてもよい。 In this embodiment, the pixel 20 is not limited to the configuration shown in FIG. 7. For example, the gate electrode 212 of the writing transistor Tr2 may have a vertical gate structure, and the gate electrode 212 of the switching transistor Tr4 may have a flat gate electrode structure.
　＜４．２　変形例＞
　また、本実施形態は以下のように変形することもできる。そこで、図８及び図９を参照して、本実施形態の変形例を説明する。図８及び図９は、本実施形態の変形例に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 4.2 Modifications
This embodiment can also be modified as follows. A modified example of this embodiment will now be described with reference to Figs. 8 and 9. Figs. 8 and 9 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a modified example of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 shown to be located on the lower side. Note that in these figures, the capacitance sections C1 and C2 are omitted from illustration.
　本変形例においても、図８に示すように、スイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の下面に接する導電層２２０が設けられている。本変形例においては、導電層２２０を設けることにより、酸化物半導体層２１０の形成時に、導電層２２０がヒートシンクのように機能して温度勾配を生じさせることから、酸化物半導体層２１０の結晶性に勾配を生じさせることができる。 Also in this modification, as shown in FIG. 8, a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the switching transistor Tr4. In this modification, by providing the conductive layer 220, when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, and therefore a gradient can be generated in the crystallinity of the oxide semiconductor layer 210.
　また、本変形例においては、図９に示すように、スイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の上面に接する導電層２２２が設けられている。本変形例においては、導電層２２２を設けることにより、酸化物半導体層２１０の形成時に、導電層２２０がヒートシンクのように機能して温度勾配を生じさせることから、酸化物半導体層２１０の結晶性に勾配を生じさせることができる。さらに、本変形例によれば、導電層２２２により、ソース、ドレインにコンタクトを形成する際に、酸化物半導体層２１０にダメージを生じることを抑制することができる。加えて、本変形例によれば、導電層２２２により、コンタクトを形成する際の水素、酸素の拡散を抑制することができる。 In addition, in this modification, as shown in FIG. 9, a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that becomes the source or drain of the switching transistor Tr4. In this modification, by providing the conductive layer 222, when the oxide semiconductor layer 210 is formed, the conductive layer 220 functions as a heat sink to generate a temperature gradient, so that a gradient can be generated in the crystallinity of the oxide semiconductor layer 210. Furthermore, according to this modification, the conductive layer 222 can suppress damage to the oxide semiconductor layer 210 when contacts are formed at the source and drain. In addition, according to this modification, the conductive layer 222 can suppress the diffusion of hydrogen and oxygen when the contacts are formed.
　なお、本変形例においては、画素２０は、図８及び図９に示すような構成に限定されるものではない。 In this modified example, the pixel 20 is not limited to the configuration shown in Figures 8 and 9.
　＜＜５．　第３の実施形態＞＞
　次に、図１０を参照して、本開示の第３の実施形態を説明する。図１０は、本実施形態に係る画素２０の平面構成の一例を示した模式図であり、図４Ｂに対応する。 <<5. Third embodiment>>
Next, a third embodiment of the present disclosure will be described with reference to Fig. 10. Fig. 10 is a schematic diagram showing an example of a planar configuration of a pixel 20 according to this embodiment, and corresponds to Fig. 4B.
　第１の実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４については、帯状の酸化物半導体層２１０上にゲート電極２１２が設けられ、ゲート電極２１２を挟みこむように、トランジスタのソース、ドレインと電気的に接続される一対のビア２１４が設けられている。さらに、平面視においては、ゲート電極２１２の中心と、一対のビア２１４との中心とが１つの線上に配列していた。しかしながら、本開示の実施形態は、このような構造に限定されるものではない。 In the first embodiment, for the write transistor Tr2 and the switching transistor Tr4, a gate electrode 212 is provided on a strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor are provided to sandwich the gate electrode 212. Furthermore, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged on a single line. However, the embodiments of the present disclosure are not limited to such a structure.
　例えば、図１０の左側に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４については、Ｌ字状の酸化物半導体層２１０の中心上にゲート電極２１２（詳細には、図１０中では、垂直ゲート部２１２ａが図示）が設けられている。さらに、Ｌ字状の酸化物半導体層２１０の端上に、トランジスタのソース、ドレインと電気的に接続される一対のビア（コンタクトホール）２１４が設けられている。言い換えると、平面視において、ゲート電極２１２の中心と、一対のビア２１４との中心とは、Ｌ字状に配列する。 For example, as shown on the left side of FIG. 10, for the write transistor Tr2 and the switching transistor Tr4, a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) is provided at the center of an L-shaped oxide semiconductor layer 210. Furthermore, a pair of vias (contact holes) 214 electrically connected to the source and drain of the transistor are provided on the ends of the L-shaped oxide semiconductor layer 210. In other words, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged in an L shape.
　例えば、図１０の中央に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４については、コ(日本語のカタカナの「コ」)字状の酸化物半導体層２１０の中心上にゲート電極２１２（詳細には、図１０中では、垂直ゲート部２１２ａが図示）が設けられている。さらに、コ字状の酸化物半導体層２１０の端上に、トランジスタのソース、ドレインと電気的に接続される一対のビア２１４が設けられている。言い換えると、平面視において、ゲート電極２１２の中心と、一対のビア２１４との中心とがコ字状に配列する。 For example, as shown in the center of FIG. 10, for the write transistor Tr2 and the switching transistor Tr4, a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) is provided at the center of a U-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor are provided on the ends of the U-shaped oxide semiconductor layer 210. In other words, in a plan view, the center of the gate electrode 212 and the center of the pair of vias 214 are arranged in a U-shape.
　また、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の一部は、隣接する画素２０のこれらトランジスタと領域の一部を共有する構造であってもよい。例えば、図１０の右側に示すように、Ｙ（アルファベットの「Ｙ」)字状の酸化物半導体層２１０の中心上に、一方の画素２０のトランジスタのゲート電極２１２（詳細には、図１０中では、垂直ゲート部２１２ａが図示）が設けられている。さらに、Ｙ字状の酸化物半導体層２１０の３つの端上に、一方の画素２０のトランジスタのソース、ドレインと電気的に接続される一対のビア２１４と、他方の画素２０のトランジスタのソース又はドレインと電気的に接続されるビア２１４が設けられている。言い換えると、平面視において、一方の画素２０のトランジスタのゲート電極２１２の中心と、一方の画素２０のトランジスタの一対のビア２１４の中心と、他方の画素２０のトランジスタの一対のビア２１４のうちの１つビアの中心とが、Ｙ字状に配列する。 Also, a part of the writing transistor Tr2 and the switching transistor Tr4 may be structured to share a part of the region with these transistors of the adjacent pixel 20. For example, as shown on the right side of FIG. 10, a gate electrode 212 (more specifically, a vertical gate portion 212a is shown in FIG. 10) of a transistor of one pixel 20 is provided on the center of a Y-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor of one pixel 20 and a via 214 electrically connected to the source or drain of the transistor of the other pixel 20 are provided on three ends of the Y-shaped oxide semiconductor layer 210. In other words, in a plan view, the center of the gate electrode 212 of the transistor of one pixel 20, the center of the pair of vias 214 of the transistor of one pixel 20, and the center of one of the pair of vias 214 of the transistor of the other pixel 20 are arranged in a Y shape.
　以上のように、本実施形態によれば、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面構造を様々に変形することにより、駆動回路のレイアウトサイズをより小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。 As described above, according to this embodiment, by modifying the planar structures of the writing transistor Tr2 and the switching transistor Tr4 in various ways, the layout size of the drive circuit can be made smaller, and the display device 10 can be made smaller and finer.
　なお、本実施形態においては、画素２０の書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、図１０に示すような構成に限定されるものではない。 In this embodiment, the writing transistor Tr2 and the switching transistor Tr4 of the pixel 20 are not limited to the configuration shown in FIG. 10.
　＜＜６．　第４の実施形態＞＞
　次に、図１１を参照して、本開示の第４の実施形態を説明する。図１１は、本実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、図１１においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <<6. Fourth embodiment>>
Next, a fourth embodiment of the present disclosure will be described with reference to Fig. 11. Fig. 11 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 11, the capacitance units C1 and C2 are omitted from the illustration.
　これまで説明した実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの上面と接していた。しかしながら、本実施形態においてはこれに限定されるものではなく、図１１に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの下面と接していてもよい。 In the embodiments described so far, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210. However, this embodiment is not limited to this, and as shown in FIG. 11, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
　以上のように、本実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の断面構造、すなわち、これらのトランジスタのソース、ドレインのコンタクトの構造を変形することにより、駆動回路の半導体基板１００の膜厚方向におけるサイズをより小さくすることができる。その結果、本実施形態によれば、表示装置１０を小型化、微細化することができる。 As described above, in this embodiment, by modifying the cross-sectional structures of the write transistor Tr2 and the switching transistor Tr4, i.e., the structures of the source and drain contacts of these transistors, it is possible to reduce the size of the drive circuit in the film thickness direction of the semiconductor substrate 100. As a result, according to this embodiment, it is possible to make the display device 10 smaller and more miniaturized.
　なお、本実施形態においては、画素２０は、図１１に示すような構成に限定されるものではない。 In this embodiment, the pixel 20 is not limited to the configuration shown in FIG. 11.
　＜＜７．　第５の実施形態＞＞
　次に、図１２を参照して、本開示の第５の実施形態を説明する。図１２は、本実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、図１２においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <<7. Fifth embodiment>>
Next, a fifth embodiment of the present disclosure will be described with reference to Fig. 12. Fig. 12 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail corresponds to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in Fig. 12, the capacitance units C1 and C2 are omitted from the illustration.
　これまで説明した実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、１つの垂直ゲート部２１２ａを持つ垂直ゲート構造であったが、本実施形態においては、複数の垂直ゲート部２１２ｂを持つ垂直ゲート構造であってもよい。例えば、図１２においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、２つの垂直ゲート部２１２ｂを持つ。なお、本実施形態においては、２つの垂直ゲート部２１２ｂを持つことに限定されるものではなく、２つ以上の垂直ゲート部２１２ｂを持っていればよい。 In the embodiments described so far, the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure with one vertical gate portion 212a, but in this embodiment, they may have a vertical gate structure with multiple vertical gate portions 212b. For example, in FIG. 12, the write transistor Tr2 and the switching transistor Tr4 have two vertical gate portions 212b. Note that this embodiment is not limited to having two vertical gate portions 212b, and it is sufficient to have two or more vertical gate portions 212b.
　以上のように、本実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２が複数の垂直ゲート部２１２ｂを持つことにより、レイアウト面積を拡大することなく、ゲート長をより長くすることができる。さらに、本実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することをより効果的に抑制することができる。 As described above, in this embodiment, the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have multiple vertical gate portions 212b, so that the gate length can be increased without increasing the layout area. Furthermore, in this embodiment, the source and drain can be separated from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be more effectively prevented from diffusing from the source and drain into the channel formation region, which would cause fluctuations in the characteristics of the channel formation region.
　なお、本実施形態においては、画素２０は、図１２に示すような構成に限定されるものではない。 In this embodiment, the pixel 20 is not limited to the configuration shown in FIG. 12.
　＜＜８．　第６の実施形態＞＞
　次に、図１３及び図１４を参照して、本開示の第６の実施形態を説明する。図１３及び図１４は、本実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <<8. Sixth embodiment>>
Next, a sixth embodiment of the present disclosure will be described with reference to Fig. 13 and Fig. 14. Fig. 13 and Fig. 14 are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment, and in detail correspond to a cross section when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance parts C1 and C2 are omitted from the illustration.
　これまで説明した実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して上方にゲート電極２１２が位置するトップゲート構造として構成されていた。しかしながら、本実施形態においては、これに限定されるものではなく、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であってもよい。 In the embodiments described so far, the write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210. However, this embodiment is not limited to this, and the write transistor Tr2 and the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
　詳細には、図１３に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２は、半導体基板１００の膜厚方向に沿って延伸する垂直ゲート部２１２ａを有する。ゲート電極２１２及びその垂直ゲート部２１２ａは、絶縁膜２０２を介して酸化物半導体層２１０の下面と接している。詳細には、酸化物半導体層２１０は、ボトムゲート構造及び垂直ゲート構造を持つ書込みトランジスタＴｒ２にあわせて、図１３に示す断面において、垂直ゲート部２１２ａに沿って上方に突出した凸形状部である領域２１０ａを持っている。 In detail, as shown in FIG. 13, the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have vertical gate portions 212a extending along the film thickness direction of the semiconductor substrate 100. The gate electrodes 212 and their vertical gate portions 212a are in contact with the lower surface of the oxide semiconductor layer 210 via the insulating film 202. In detail, the oxide semiconductor layer 210 has a region 210a that is a convex portion that protrudes upward along the vertical gate portion 212a in the cross section shown in FIG. 13 in accordance with the write transistor Tr2 having a bottom gate structure and a vertical gate structure.
　さらに、図１３に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの上面と接している。 Furthermore, as shown in FIG. 13, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210.
　もしくは、本実施形態においては、図１４に示すように、図１３と同様に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であってもよい。さらに、図１４の例では、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの下面と接している。 Alternatively, in this embodiment, as shown in FIG. 14, similar to FIG. 13, the write transistor Tr2 and the switching transistor Tr4 may have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210. Furthermore, in the example of FIG. 14, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
　以上のように、本実施形態によれば、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の断面構造を変形することにより、駆動回路の半導体基板１００の膜厚方向におけるサイズをより小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。 As described above, according to this embodiment, by modifying the cross-sectional structures of the write transistor Tr2 and the switching transistor Tr4, the size of the drive circuit in the film thickness direction of the semiconductor substrate 100 can be reduced, and the display device 10 can be made smaller and finer.
　また、本実施形態においては、画素２０は、図１３及び図１４に示すような構成に限定されるものではない。 In addition, in this embodiment, the pixel 20 is not limited to the configuration shown in Figures 13 and 14.
　＜＜９．　第７の実施形態＞＞
　次に、図１５Ａから図１５Ｄを参照して、本開示の第７の実施形態として、上述の第１の実施形態に係る画素２０の製造方法の一例を説明する。図１５Ａから図１５Ｄは、本実施形態に係る画素（画素回路）２０の製造方法を説明するための断面図であり、詳細には、図４Ａに示す断面に対応する。 <<9. Seventh embodiment>>
Next, an example of a method for manufacturing the pixel 20 according to the first embodiment will be described as a seventh embodiment of the present disclosure with reference to Figures 15A to 15D. Figures 15A to 15D are cross-sectional views for explaining the method for manufacturing the pixel (pixel circuit) 20 according to this embodiment, and correspond to the cross section shown in Figure 4A in detail.
　まずは、図１５Ａの左側に示すように、半導体基板１００に駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を形成し、その上に配線層２００の一部を形成し、さらに、絶縁膜２０２を形成する。そして、図１５Ａの中央に示すように、絶縁膜２０２に、エッチング等を用いてトレンチ４００を形成する。さらに、図１５Ａの右側に示すように、絶縁膜２０２を覆うように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域となる酸化物半導体層２１０を、スパッタリング等を用いて形成する。 First, as shown on the left side of FIG. 15A, a drive transistor Tr1 and a light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed thereon, and an insulating film 202 is then formed. Then, as shown in the center of FIG. 15A, a trench 400 is formed in the insulating film 202 by etching or the like. Furthermore, as shown on the right side of FIG. 15A, an oxide semiconductor layer 210 that will become the channel formation region of the write transistor Tr2 and the switching transistor Tr4 is formed by sputtering or the like so as to cover the insulating film 202.
　次に、図１５Ｂの左側に示すように、酸化物半導体層２１０を覆い、且つ、トレンチ４００を埋め込むように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート絶縁膜となる絶縁膜２０２を形成する。そして、図１５Ｂの中央に示すように、トレンチ４００内に埋め込まれた絶縁膜２０２の領域に、トレンチ４０２を形成する。さらに、図１５Ｂの右側に示すように、トレンチ４０２を埋め込むように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２の垂直ゲート部２１２ａとなる金属膜等を形成する。 Next, as shown on the left side of FIG. 15B, an insulating film 202 that will become the gate insulating film of the write transistor Tr2 and the switching transistor Tr4 is formed so as to cover the oxide semiconductor layer 210 and fill the trench 400. Then, as shown in the center of FIG. 15B, a trench 402 is formed in the region of the insulating film 202 that is filled in the trench 400. Furthermore, as shown on the right side of FIG. 15B, a metal film or the like that will become the vertical gate portion 212a of the gate electrode 212 of the write transistor Tr2 and the switching transistor Tr4 is formed so as to fill the trench 402.
　次に、図１５Ｃの左側に示すように、絶縁膜２０２及び垂直ゲート部２１２ａ上に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート絶縁膜となる絶縁膜２０２を形成する。さらに、ＣＭＰ（Ｃｈｅｍｉｃａｌ　Ｍｅｃｈａｎｉｃａｌ　Ｐｏｌｉｓｈｉｎｇ）等を用いて、絶縁膜２０２の平坦化、及び、垂直ゲート部２１２ａの上面を露出させ、垂直ゲート部２１２ａの上面の上に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２を形成する。 Next, as shown on the left side of FIG. 15C, an insulating film 202 that will become the gate insulating film of the write transistor Tr2 and the switching transistor Tr4 is formed on the insulating film 202 and the vertical gate portion 212a. Furthermore, using CMP (Chemical Mechanical Polishing) or the like, the insulating film 202 is planarized and the upper surface of the vertical gate portion 212a is exposed, and the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 are formed on the upper surface of the vertical gate portion 212a.
　そして、図１５Ｃの右側に示すように、ゲート電極２１２や絶縁膜２０２の上面を覆うように、層間絶縁膜となる絶縁膜２０２を形成する。 Then, as shown on the right side of FIG. 15C, an insulating film 202 that will become an interlayer insulating film is formed so as to cover the upper surfaces of the gate electrode 212 and the insulating film 202.
　次に、図１５Ｄの左側に示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース、ドレインとなる酸化物半導体層２１０の領域２１０ｂの上面の一部を露出するホールを絶縁膜２０２に形成し、絶縁膜２０２に、ビア２１４となる金属膜をホールに形成する。そして、図１５Ｄの右側に示すように、ビア２１４の上面の上に、配線２０４を形成する。 Next, as shown on the left side of FIG. 15D, holes are formed in the insulating film 202 to expose part of the upper surface of the region 210b of the oxide semiconductor layer 210 that will become the source and drain of the writing transistor Tr2 and the switching transistor Tr4, and a metal film that will become the via 214 is formed in the insulating film 202 in the hole. Then, as shown on the right side of FIG. 15D, wiring 204 is formed on the upper surface of the via 214.
　すなわち、本開示の実施形態に係る画素２０は、一般的な半導体装置の製造に用いられる、方法、装置、及び条件を用いることで製造することが可能である。すなわち、本実施形態に係る画素２０は、既存の半導体装置の製造方法を用いて製造することが可能である。 In other words, the pixel 20 according to the embodiment of the present disclosure can be manufactured using methods, devices, and conditions that are used in the manufacture of general semiconductor devices. In other words, the pixel 20 according to the embodiment can be manufactured using existing semiconductor device manufacturing methods.
　＜＜１０．第８の実施形態＞＞
　＜１０．１　背景＞
　まずは、本開示の第８の実施形態の詳細を説明する前に、図１６を参照して、本発明者らが本開示の第８の実施形態を創作するに至る背景について説明する。図１６は、本開示の第８の実施形態に係る画素２０の要部の断面構成の一例を示した模式図である。 <<10. Eighth embodiment>>
10.1 Background
First, before describing the details of the eighth embodiment of the present disclosure, the background that led the inventors to create the eighth embodiment of the present disclosure will be described with reference to Fig. 16. Fig. 16 is a schematic diagram showing an example of a cross-sectional configuration of a main part of a pixel 20 according to the eighth embodiment of the present disclosure.
　これまで説明した本開示の各実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域を酸化物半導体層２１０内に形成することにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のリークを抑えていた。さらに、これら実施形態においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積を拡大することなく、ゲート長を容易に長くしていた。加えて、これら実施形態においては、垂直ゲート部２１２ａを長くすることにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することを抑制していた。 In each embodiment of the present disclosure described so far, the channel formation regions of the write transistor Tr2 and the switching transistor Tr4 are formed in the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4. Furthermore, in these embodiments, the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure, which makes it easy to increase the gate length without increasing the layout area. In addition, in these embodiments, the vertical gate portion 212a is lengthened, which makes it possible to separate the source and drain from the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, thereby suppressing the diffusion of hydrogen from the source and drain into the channel formation region and the change in the characteristics of the channel formation region when contacts are formed at the source and drain.
　しかしながら、インジウム－ガリウム－亜鉛酸化物（ＩＧＺＯ）等からなる酸化物半導体層２１０は、周囲の膜からの影響で酸化還元されやすい性質を持つ。例えば、酸化物半導体層２１０に、酸化シリコン膜（ＳｉＯ２）からなる絶縁膜２０２から酸素が拡散すると、酸化物半導体層２１０は、容易に酸化され、その抵抗が大きくなりやすい。 However, the oxide semiconductor layer 210 made of indium gallium zinc oxide (IGZO) or the like has a property of being easily oxidized and reduced by the influence of the surrounding films. For example, when oxygen diffuses from the insulating film 202 made of a silicon oxide (SiO 2 ) film into the oxide semiconductor layer 210, the oxide semiconductor layer 210 is easily oxidized and its resistance is likely to increase.
　これまで説明した本開示の実施形態に係る書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４においては、チャネルとなる酸化物半導体層２１０の領域２１０ａは、高抵抗であってもよいものの、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂは、ソース及びドレインに寄生抵抗が生じることを抑制するために、低抵抗であることが求められる。 In the write transistor Tr2 and the switching transistor Tr4 according to the embodiments of the present disclosure described above, the region 210a of the oxide semiconductor layer 210 that serves as the channel may have a high resistance, but the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain are required to have a low resistance in order to prevent parasitic resistance from occurring in the source and drain.
　そこで、チャネルとなる酸化物半導体層２１０の領域２１０ａと、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂとを、別々に作り分けることが考えられる。しかしながら、領域２１０ａと領域２１０ｂと別々に作り分けることは、画素２０自体が微細であることもあって、それ自体が難しく、さらに、表示装置１０の製造工程数が増加することにもつながることから、好ましい選択肢とは言い難い。 Therefore, it is conceivable to separately create the region 210a of the oxide semiconductor layer 210 that serves as the channel, and the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain. However, creating the regions 210a and 210b separately is difficult in itself, partly because the pixels 20 themselves are very fine, and furthermore, it would increase the number of manufacturing steps for the display device 10, so this is hardly a desirable option.
　そこで、本発明者らは、このような状況を鑑みて、チャネルとなる酸化物半導体層２１０の領域２１０ａと、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂとを容易に作り分けることができる、本開示の第８の実施形態を創作するに至った。 In light of this situation, the inventors have come up with an eighth embodiment of the present disclosure, which makes it easy to separately create a region 210a of the oxide semiconductor layer 210 that serves as a channel, and a pair of regions 210b of the oxide semiconductor layer 210 that serve as a source and drain.
　第８の実施形態においては、図１６に示すように、チャネルとなる酸化物半導体層２１０の領域２１０ａについては、周囲から電子を奪う酸化作用膜からなる絶縁膜（第１の絶縁層）２０２と接するように形成することで、チャネルとなる酸化物半導体層２１０の領域２１０ａを高抵抗化する。一方、本実施形態においては、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂについては、周囲に電子を与える還元作用膜からなる絶縁膜（第２の絶縁層）４５０と接するように形成することで、領域２１０ｂを低抵抗化する。 In the eighth embodiment, as shown in FIG. 16, the region 210a of the oxide semiconductor layer 210 that becomes the channel is formed so as to be in contact with an insulating film (first insulating layer) 202 made of an oxidation film that takes electrons from the surroundings, thereby increasing the resistance of the region 210a of the oxide semiconductor layer 210 that becomes the channel. On the other hand, in this embodiment, the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain are formed so as to be in contact with an insulating film (second insulating layer) 450 made of a reduction film that gives electrons to the surroundings, thereby decreasing the resistance of the region 210b.
　ここで、周囲から電子を奪う酸化作用膜とは、周囲の膜から電子を奪って当該膜を酸化する作用がある膜のことをいい、詳細には、チャネルとなる酸化物半導体層２１０の領域２１０ａから電子を奪って酸化することができる膜である。酸化作用膜は、具体的には、チャネルとなる酸化物半導体層２１０の領域２１０ａに酸素を供給する酸素供給膜であり、例えば、酸化シリコン、酸窒化シリコン（ＳｉＯＮ）、酸化アルミニウム（Ａｌ２Ｏ３）等であることができる。さらに、当該酸素供給膜は、酸素が過剰に含まれる酸化シリコン（ＳｉＯｘ（ｘ＞２））等であることが好ましい。 Here, the oxidizing film that takes electrons from the surroundings refers to a film that has the effect of taking electrons from the surrounding film and oxidizing the film, and more specifically, it is a film that can take electrons from the region 210a of the oxide semiconductor layer 210 that becomes the channel and oxidize the film. Specifically, the oxidizing film is an oxygen supplying film that supplies oxygen to the region 210a of the oxide semiconductor layer 210 that becomes the channel, and can be, for example, silicon oxide, silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), etc. Furthermore, the oxygen supplying film is preferably silicon oxide (SiOx (x>2)) containing an excess of oxygen, etc.
　また、ここで、周囲に電子を与える還元作用膜とは、周囲の膜に電子を与えて当該膜を還元する作用がある膜のことをいい、詳細には、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂに電子を与えて還元することができる膜である。還元作用膜は、具体的には、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂに水素を与える水素供給膜、もしくは、一対の領域２１０ｂから酸素を引き抜くことができる膜である。水素供給膜は、例えば、水素を含む、窒化シリコン、酸窒化シリコン（ＳｉＯＮ）、窒化アルミニウム（ＡｌＮ）、酸窒化アルミニウム（ＡｌＯＮ）等であることができる。さらに、水素供給膜は、例えば、成膜条件や膜厚等によりその水素含有量を調整することができるため、領域２１０ｂへの還元作用を自由に調整することができる。本実施形態においては、領域２１０ｂに水素を十分に与えることができるように、且つ、周囲（例えば、絶縁膜２０２）から領域２１０ｂへ酸素が拡散することを遮断するために、水素供給膜の膜厚を、例えば２０ｎｍ以上とすることが好ましい。また、本実施形態においては、酸素を引き抜くことができる膜としては、例えば、酸化物半導体層２１０よりも圧縮応力が大きい絶縁膜を挙げることができる。 Here, the reduction action film that provides electrons to the surroundings refers to a film that has the effect of providing electrons to the surrounding film and reducing the film, and in particular, it is a film that can provide electrons to the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain, thereby reducing the film. Specifically, the reduction action film is a hydrogen supply film that provides hydrogen to the pair of regions 210b of the oxide semiconductor layer 210 that become the source and drain, or a film that can extract oxygen from the pair of regions 210b. The hydrogen supply film can be, for example, silicon nitride, silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxynitride (AlON), or the like that contains hydrogen. Furthermore, the hydrogen supply film can adjust its hydrogen content by, for example, the film formation conditions, film thickness, etc., so that the reduction action to the region 210b can be freely adjusted. In this embodiment, it is preferable to set the film thickness of the hydrogen supply film to, for example, 20 nm or more in order to provide sufficient hydrogen to the region 210b and to block the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b. In addition, in this embodiment, an example of a film that can extract oxygen is an insulating film that has a greater compressive stress than the oxide semiconductor layer 210.
　本実施形態によれば、チャネルとなる酸化物半導体層２１０の領域２１０ａを、周囲から電子を奪う酸化作用膜からなる絶縁膜２０２と接するように形成することにより、領域２１０ａは酸化され、抵抗値を高くすることができる。一方、本実施形態によれば、ソース及びドレインとなる酸化物半導体層２１０の一対の領域２１０ｂについては、周囲に電子を与える還元作用膜からなる絶縁膜（第２の絶縁層）４５０と接するように形成することにより、一対の領域２１０ｂは還元され、抵抗値を低くすることができる。さらに、本実施形態によれば、酸化物半導体層２１０の領域２１０ａ、２１０ｂを所望の特性を持つように、容易に作り分けることができる。以下、このような本開示の第８の実施形態の詳細を説明する。 According to this embodiment, the region 210a of the oxide semiconductor layer 210 that serves as the channel is formed so as to be in contact with the insulating film 202 made of an oxidation film that takes electrons from the surroundings, so that the region 210a is oxidized and the resistance value can be increased. On the other hand, according to this embodiment, the pair of regions 210b of the oxide semiconductor layer 210 that serve as the source and drain are formed so as to be in contact with the insulating film (second insulating layer) 450 made of a reduction film that gives electrons to the surroundings, so that the pair of regions 210b are reduced and the resistance value can be reduced. Furthermore, according to this embodiment, the regions 210a and 210b of the oxide semiconductor layer 210 can be easily made to have desired characteristics. Hereinafter, the details of the eighth embodiment of the present disclosure will be described.
　＜１０．２　詳細構成＞
　次に、図１７を参照して、本開示の第８の実施形態を説明する。図１７は、本実施形態に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <10.2 Detailed configuration>
Next, an eighth embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to this embodiment. The stacked structure of the pixel 20 is shown in a cross section taken along the film thickness direction of the semiconductor substrate 100, with the semiconductor substrate 100 positioned below. Sections C1 and C2 are omitted from the illustration.
　詳細には、本実施形態においては、図１７に示すように、これまで説明した各実施形態と同様に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、半導体基板１００の上に積層された配線層２００内に設けられた酸化物半導体層２１０と、当該酸化物半導体層２１０と絶縁膜２０２を介して接するゲート電極２１２とを有する。また、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して上方にゲート電極２１２が位置するトップゲート構造として構成されている。酸化物半導体層２１０は、その膜厚は、例えば２０ｎｍ以下とする。 In detail, in this embodiment, as shown in FIG. 17, similar to each of the embodiments described so far, the write transistor Tr2 and the switching transistor Tr4 have an oxide semiconductor layer 210 provided in a wiring layer 200 stacked on the semiconductor substrate 100, and a gate electrode 212 that contacts the oxide semiconductor layer 210 via an insulating film 202. The write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210. The oxide semiconductor layer 210 has a thickness of, for example, 20 nm or less.
　さらに、本実施形態においても、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２は、半導体基板１００の膜厚方向に沿って延伸する垂直ゲート部２１２ａを有する。詳細には、酸化物半導体層２１０は、トップゲート構造及び垂直ゲート構造を持つ書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４にあわせて、図１７に示す断面において、垂直ゲート部２１２ａに沿って下方に突出した凸形状部である領域２１０ａを持っている。そして、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０内であって、ゲート電極２１２及びその垂直ゲート部２１２ａと絶縁膜２０２を介して接している凸形状部である領域２１０ａにチャネル形成領域を持つ。さらに、本実施形態においては、ゲート電極２１２及びその垂直ゲート部２１２ａは、上述した酸化作用膜からなる絶縁膜２０２を介して酸化物半導体層２１０と接している。また、本実施形態においては、チャネル形成領域である凸形状部である領域２１０ａの垂直ゲート部２１２ａと反対に位置する側も、酸化作用膜からなる絶縁膜２０２と接している。 Furthermore, in this embodiment, the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have a vertical gate portion 212a extending along the film thickness direction of the semiconductor substrate 100. In detail, the oxide semiconductor layer 210 has a region 210a that is a convex portion protruding downward along the vertical gate portion 212a in the cross section shown in FIG. 17 in accordance with the write transistor Tr2 and the switching transistor Tr4 having a top gate structure and a vertical gate structure. The write transistor Tr2 and the switching transistor Tr4 have a channel formation region in the region 210a that is a convex portion in contact with the gate electrode 212 and its vertical gate portion 212a through the insulating film 202 in the oxide semiconductor layer 210. Furthermore, in this embodiment, the gate electrode 212 and its vertical gate portion 212a are in contact with the oxide semiconductor layer 210 through the insulating film 202 made of the above-mentioned oxidation film. In this embodiment, the side of the region 210a, which is the convex portion that is the channel formation region, opposite the vertical gate portion 212a is also in contact with the insulating film 202, which is an oxidation film.
　また、本実施形態においては、これまで説明した各実施形態と同様に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース及びドレインは、酸化物半導体層２１０における凸形状部である領域２１０ａを挟み込む一対の領域２１０ｂに位置することとなる。さらに、本実施形態においては、これまで説明した各実施形態と異なり、図１７に示すように、一対の領域２１０ｂの下面と接するように、上述の還元作用膜からなる絶縁膜４５０が設けられている。 In addition, in this embodiment, as in each of the embodiments described so far, the source and drain of the writing transistor Tr2 and the switching transistor Tr4 are located in a pair of regions 210b that sandwich the region 210a, which is a convex-shaped portion in the oxide semiconductor layer 210. Furthermore, in this embodiment, unlike each of the embodiments described so far, an insulating film 450 made of the above-mentioned reduction action film is provided so as to contact the lower surface of the pair of regions 210b, as shown in FIG. 17.
　以上のように、本実施形態によれば、チャネルとなる領域２１０ａを、周囲から電子を奪う酸化作用膜からなる絶縁膜２０２と接するように形成することにより、領域２１０ａは酸化され、抵抗値を高くすることができる。一方、本実施形態によれば、ソース及びドレインとなる一対の領域２１０ｂについては、周囲に電子を与える還元作用膜からなる絶縁膜（第２の絶縁層）４５０と接するように形成することにより、一対の領域２１０ｂは還元され、抵抗値を低くすることができる。 As described above, according to this embodiment, the region 210a that becomes the channel is formed so as to be in contact with the insulating film 202, which is an oxidizing film that takes electrons from the surroundings, so that the region 210a is oxidized and the resistance value can be increased. On the other hand, according to this embodiment, the pair of regions 210b that become the source and drain are formed so as to be in contact with the insulating film (second insulating layer) 450, which is a reducing film that gives electrons to the surroundings, so that the pair of regions 210b is reduced and the resistance value can be decreased.
　また、本実施形態においても、図１７に示すＡ－Ａ´線で画素２０を切断した際の断面は、図４Ｂに示される第１の実施形態と同様の形態を持つことができる。詳細には、酸化物半導体層２１０に設けられる書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視においては、帯状の酸化物半導体層２１０上にゲート電極２１２が設けられ、ゲート電極２１２を挟みこむように、トランジスタのソース、ドレインと電気的に接続される一対のビア２１４が設けられていてもよい。さらに、当該平面視においては、ゲート電極２１２の中心と、一対のビア２１４との中心とが１つの線上に配列していてもよい。 Also, in this embodiment, the cross section of the pixel 20 taken along line A-A' in FIG. 17 can have the same shape as the first embodiment shown in FIG. 4B. In detail, in a plan view of the writing transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210, a gate electrode 212 may be provided on the strip-shaped oxide semiconductor layer 210, and a pair of vias 214 electrically connected to the source and drain of the transistor may be provided to sandwich the gate electrode 212. Furthermore, in this plan view, the center of the gate electrode 212 and the center of the pair of vias 214 may be arranged on a single line.
　もしくは、本実施形態においても、酸化物半導体層２１０に設けられる書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視は、図１０に示される第３の実施形態と同様の形態を持つこともできる。詳細には、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４については、例えば、Ｌ字状の酸化物半導体層２１０の中心上にゲート電極２１２が設けられていてもよい。さらに、Ｌ字状の酸化物半導体層２１０の端上に、トランジスタのソース、ドレインと電気的に接続される一対のビア（コンタクトホール）２１４が設けられていてもよい。 Alternatively, in this embodiment, the plan view of the write transistor Tr2 and the switching transistor Tr4 provided in the oxide semiconductor layer 210 can also have the same form as that of the third embodiment shown in FIG. 10. In detail, for example, the write transistor Tr2 and the switching transistor Tr4 may have a gate electrode 212 provided at the center of the L-shaped oxide semiconductor layer 210. Furthermore, a pair of vias (contact holes) 214 electrically connected to the source and drain of the transistor may be provided at the ends of the L-shaped oxide semiconductor layer 210.
　もしくは、本実施形態においても、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４については、例えば、コ(日本語のカタカナの「コ」)字状の酸化物半導体層２１０の中心上にゲート電極２１２が設けられていてもよい。さらに、コ字状の酸化物半導体層２１０の端上に、トランジスタのソース、ドレインと電気的に接続される一対のビア２１４が設けられていてもよい。 Alternatively, in this embodiment, for the write transistor Tr2 and the switching transistor Tr4, the gate electrode 212 may be provided, for example, at the center of the U-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor may be provided at the ends of the U-shaped oxide semiconductor layer 210.
　もしくは、本実施形態においても、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の一部は、隣接する画素２０のこれらトランジスタと領域の一部を共有する構造であってもよい。例えば、Ｙ（アルファベットの「Ｙ」)字状の酸化物半導体層２１０の中心上に、一方の画素２０のトランジスタのゲート電極２１２が設けられていてもよい。さらに、Ｙ字状の酸化物半導体層２１０の３つの端上に、一方の画素２０のトランジスタのソース、ドレインと電気的に接続される一対のビア２１４と、他方の画素２０のトランジスタのソース又はドレインと電気的に接続されるビア２１４が設けられていてもよい。 Alternatively, in this embodiment, a part of the writing transistor Tr2 and the switching transistor Tr4 may share a part of the region with these transistors of an adjacent pixel 20. For example, the gate electrode 212 of the transistor of one pixel 20 may be provided on the center of the Y-shaped oxide semiconductor layer 210. Furthermore, a pair of vias 214 electrically connected to the source and drain of the transistor of one pixel 20, and a via 214 electrically connected to the source or drain of the transistor of the other pixel 20 may be provided on the three ends of the Y-shaped oxide semiconductor layer 210.
　なお、本実施形態においては、画素２０は、図１７に示すような構成に限定されるものではない。 In this embodiment, the pixel 20 is not limited to the configuration shown in FIG. 17.
　＜１０．３　変形例１＞
　また、本実施形態は以下のように変形することもできる。そこで、図１８Ａから図１８Ｃを参照して、本実施形態の変形例１を説明する。図１８Ａから図１８Ｃは、本実施形態の変形例１に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <10.3 Modification 1>
This embodiment can also be modified as follows. Modification 1 of this embodiment will be described with reference to Fig. 18A to Fig. 18C. Fig. 18A to Fig. 18C are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to Modification 1 of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from illustration.
　図１８Ａの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の下面に接する導電層２２０が設けられている。 In the example of FIG. 18A, a conductive layer 220 is provided in contact with the lower surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
　導電層２２０は、周囲に電子を与える還元作用膜であることが好ましく、すなわち、イオン化傾向が大きく自身が酸化しやすい導電性膜であることが好ましい。具体的には、導電層２２０は、例えば、アルミニウム、チタン及び、タンタルからなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成される。より詳細には、導電層２２０は、アルミニウム、チタン、タンタル、窒化チタン、窒化タンタル等から形成することができる。 The conductive layer 220 is preferably a reducing film that provides electrons to the surroundings, that is, a conductive film that has a high ionization tendency and is easily oxidized. Specifically, the conductive layer 220 is formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, and tantalum. More specifically, the conductive layer 220 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, etc.
　以上のように、図１８Ａの例においては、導電層２２０を設けることにより、領域２１０ｂをより還元することができ、且つ、周囲（例えば、絶縁膜２０２）から領域２１０ｂへ酸素が拡散することを遮断することができる。従って、本変形例によれば、ソース及びドレインとなる領域２１０ｂが高抵抗となることをより抑制することができ、その結果、トランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース及びドレインに寄生抵抗が生じないようにすることができる。 As described above, in the example of FIG. 18A, by providing the conductive layer 220, the region 210b can be further reduced, and the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modified example, the region 210b that becomes the source and drain can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of the transistor Tr2 and the switching transistor Tr4.
　また、図１８Ｂの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の上面に接する導電層２２２が設けられている。 In the example of FIG. 18B, a conductive layer 222 is provided in contact with the upper surface of the oxide semiconductor layer 210 in a region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4.
　導電層２２２も、周囲に電子を与える還元作用膜であることが好ましく、すなわち、イオン化傾向が大きく自身が酸化しやすい導電性膜であることが好ましい。具体的には、導電層２２２も、例えば、アルミニウム、チタン及び、タンタルからなる群から選択される少なくとも１つの元素を含む金属又は合金等から形成される。より詳細には、導電層２２２は、アルミニウム、チタン、タンタル、窒化チタン、窒化タンタル等から形成することができる。 The conductive layer 222 is also preferably a reducing film that provides electrons to the surroundings, that is, a conductive film that has a high ionization tendency and is easily oxidized. Specifically, the conductive layer 222 is also formed from a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, and tantalum. More specifically, the conductive layer 222 can be formed from aluminum, titanium, tantalum, titanium nitride, tantalum nitride, etc.
　以上のように、図１８Ｂの例においても、導電層２２２を設けることにより、領域２１０ｂをより還元することができ、且つ、周囲（例えば、絶縁膜２０２）から領域２１０ｂへ酸素が拡散することを遮断することができる。従って、本変形例によれば、ソース及びドレインとなる領域２１０ｂが高抵抗となることをより抑制することができ、その結果、トランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース及びドレインに寄生抵抗が生じないようにすることができる。 As described above, even in the example of FIG. 18B, by providing the conductive layer 222, the region 210b can be further reduced, and the diffusion of oxygen from the surroundings (e.g., the insulating film 202) to the region 210b can be blocked. Therefore, according to this modified example, the region 210b that becomes the source and drain can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of the transistor Tr2 and the switching transistor Tr4.
　さらに、図１８Ｃの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂにおいて、酸化物半導体層２１０の下面に接する導電層２２０と、酸化物半導体層２１０の上面に接する導電層２２２とが設けられている。すなわち、図１８Ｃの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース又はドレインとなる酸化物半導体層２１０の領域２１０ｂは、導電層２２０と導電層２２２とに挟まれている。 Furthermore, in the example of FIG. 18C, in the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4, a conductive layer 220 that contacts the lower surface of the oxide semiconductor layer 210 and a conductive layer 222 that contacts the upper surface of the oxide semiconductor layer 210 are provided. That is, in the example of FIG. 18C, the region 210b of the oxide semiconductor layer 210 that serves as the source or drain of the write transistor Tr2 and the switching transistor Tr4 is sandwiched between the conductive layer 220 and the conductive layer 222.
　以上のように、図１８Ｃの例においても、導電層２２０及び導電層２２２を設けることにより、領域２１０ｂをより還元することができ、且つ、周囲（例えば、絶縁膜２０２）から領域２１０ｂへ酸素が拡散することを遮断することができる。従って、本変形例によれば、ソース及びドレインとなる領域２１０ｂが高抵抗となることをより抑制することができ、その結果、トランジスタＴｒ２及びスイッチングトランジスタＴｒ４のソース及びドレインに寄生抵抗が生じないようにすることができる。 As described above, even in the example of FIG. 18C, by providing conductive layer 220 and conductive layer 222, region 210b can be further reduced, and oxygen can be prevented from diffusing from the surroundings (e.g., insulating film 202) to region 210b. Therefore, according to this modified example, region 210b, which serves as the source and drain, can be further prevented from becoming highly resistive, and as a result, parasitic resistance can be prevented from occurring in the source and drain of transistor Tr2 and switching transistor Tr4.
　なお、図１８Ｃに示す構成は、これまで説明した本開示の各実施形態及び変形例に適用してもよい。さらに、本変形例１においては、画素２０は、図１８Ａから図１８Ｃに示すような構成に限定されるものではない。 The configuration shown in FIG. 18C may be applied to each of the embodiments and modifications of the present disclosure described thus far. Furthermore, in this modification 1, pixel 20 is not limited to the configuration shown in FIGS. 18A to 18C.
　＜１０．４　変形例２＞
　次に、図１９Ａから図１９Ｄを参照して、本実施形態の変形例２を説明する。図１９Ａから図１９Ｄは、本実施形態の変形例２に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <10.4 Modification 2>
Next, a second modification of this embodiment will be described with reference to Figures 19A to 19D. Figures 19A to 19D are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a second modification of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
　本変形例２は、第８の実施形態に第２の実施形態を適用した実施形態であるといえる。すなわち、図１９Ａに示すように、スイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にしているものの、書込みトランジスタＴｒ２のゲート電極２１２は、酸化物半導体層２３０上に平板状のゲート電極２３２を持つ、平板ゲート電極構造としている。 This modified example 2 can be said to be an embodiment in which the second embodiment is applied to the eighth embodiment. That is, as shown in FIG. 19A, the gate electrode 212 of the switching transistor Tr4 has a vertical gate structure, but the gate electrode 212 of the write transistor Tr2 has a planar gate electrode structure having a planar gate electrode 232 on the oxide semiconductor layer 230.
　さらに、本変形例２においても、図１９Ｂから図１９Ｄに示すように、上記変形例１と同様に、図１９Ａに示す形態に、導電層２２０及び導電層２２２を適用することができる。 Furthermore, in this modified example 2, as shown in Figures 19B to 19D, conductive layers 220 and 222 can be applied to the configuration shown in Figure 19A, similar to modified example 1 above.
　なお、本変形例２においては、画素２０は、図１９Ａから図１９Ｄに示すような構成に限定されるものではない。 Note that in this modification 2, pixel 20 is not limited to the configuration shown in Figures 19A to 19D.
　＜１０．５　変形例３＞
　次に、図２０Ａから図２０Ｃを参照して、本実施形態の変形例３を説明する。図２０Ａから図２０Ｃは、本実施形態の変形例２に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <10.5 Modification 3>
Next, a third modification of this embodiment will be described with reference to Figures 20A to 20C. Figures 20A to 20C are schematic diagrams showing an example of a cross-sectional configuration of a pixel 20 according to a second modification of this embodiment, and more specifically, correspond to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and are illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
　これまで説明した第８の実施形態及び変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの上面と接していた。しかしながら、本変形例においてはこれに限定されるものではなく、図２０Ａに示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの下面と接していてもよい。 In the eighth embodiment and the modified example described so far, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 are in contact with the upper surface of the region 210b of the oxide semiconductor layer 210. However, this modified example is not limited to this, and as shown in FIG. 20A, the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
　以上のように、図２０Ａの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の断面構造、すなわち、これらのトランジスタのソース、ドレインのコンタクトの構造を変形することにより、駆動回路の半導体基板１００の膜厚方向におけるサイズをより小さくすることができる。その結果、本変形例によれば、表示装置１０を小型化、微細化することができる。 As described above, in the example of FIG. 20A, by modifying the cross-sectional structures of the writing transistor Tr2 and the switching transistor Tr4, i.e., the structures of the source and drain contacts of these transistors, the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller. As a result, according to this modified example, the display device 10 can be made smaller and finer.
　また、これまで説明した第８の実施形態及び変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して上方にゲート電極２１２が位置するトップゲート構造として構成されていた。しかしながら、本変形例においては、これに限定されるものではなく、第６の実施形態と同様に、図２０Ｂに示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であってもよい。 In the eighth embodiment and the modified examples described so far, the write transistor Tr2 and the switching transistor Tr4 are configured as a top gate structure in which the gate electrode 212 is located above the oxide semiconductor layer 210. However, this modified example is not limited to this, and similar to the sixth embodiment, as shown in FIG. 20B, the write transistor Tr2 and the switching transistor Tr4 may be configured as a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210.
　以上のように、図２０Ｂの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の断面構造を変形することにより、駆動回路の半導体基板１００の膜厚方向におけるサイズをより小さくすることができる。その結果、本変形例によれば、表示装置１０を小型化、微細化することができる。 As described above, in the example of FIG. 20B, by modifying the cross-sectional structure of the writing transistor Tr2 and the switching transistor Tr4, the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller. As a result, according to this modification, the display device 10 can be made smaller and finer.
　もしくは、図２０Ｃに示す例では、図２０Ｂと同様に、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、酸化物半導体層２１０に対して下方にゲート電極２１２が位置するボトムゲート構造であるものの、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のビア２０６は、酸化物半導体層２１０の領域２１０ｂの下面と接していてもよい。 Alternatively, in the example shown in FIG. 20C, similar to FIG. 20B, the write transistor Tr2 and the switching transistor Tr4 have a bottom gate structure in which the gate electrode 212 is located below the oxide semiconductor layer 210, but the vias 206 of the write transistor Tr2 and the switching transistor Tr4 may be in contact with the lower surface of the region 210b of the oxide semiconductor layer 210.
　以上のように、図２０Ｃの例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の断面構造を変形することにより、駆動回路の半導体基板１００の膜厚方向におけるサイズをより小さくすることができる。その結果、本変形例によれば、表示装置１０を小型化、微細化することができる。 As described above, in the example of FIG. 20C, by modifying the cross-sectional structure of the writing transistor Tr2 and the switching transistor Tr4, the size of the driving circuit in the film thickness direction of the semiconductor substrate 100 can be made smaller. As a result, according to this modification, the display device 10 can be made smaller and finer.
　なお、本変形例３においては、画素２０は、図２０Ａから図２０Ｃに示すような構成に限定されるものではない。 In addition, in this modification example 3, the pixel 20 is not limited to the configuration shown in Figures 20A to 20C.
　＜１０．６　変形例４＞
　次に、図２１Ａ及び図２１Ｂを参照して、本実施形態の変形例４を説明する。図２１Ａ及び図２１Ｂは、本実施形態の変形例４に係る画素２０の要部の断面構成の一例を示した模式図である。 <10.6 Modification 4>
Next, a fourth modification of the present embodiment will be described with reference to Fig. 21A and Fig. 21B. Fig. 21A and Fig. 21B are schematic diagrams showing an example of a cross-sectional configuration of a main part of a pixel 20 according to the fourth modification of the present embodiment.
　本変形例４においては、図２１Ａに示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、デュアルゲート構造であってもよい。詳細には、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、垂直ゲート部（第１の垂直ゲート部）２１２ａと、チャネル形成領域である酸化物半導体層２１０の凸形状部である領域２１０ａを挟んで対向するゲート電極（第３のゲート電極）２１２ｃを有する。本変形例においては、垂直ゲート部２１２ａとゲート電極２１２ｃとは、同じ電位が印加されてもよく、異なる電位が印加されてもよい。 In this fourth modification, as shown in FIG. 21A, the write transistor Tr2 and the switching transistor Tr4 may have a dual gate structure. In detail, the write transistor Tr2 and the switching transistor Tr4 have a vertical gate portion (first vertical gate portion) 212a and a gate electrode (third gate electrode) 212c that faces each other across a region 210a that is a convex portion of the oxide semiconductor layer 210 that is a channel formation region. In this modification, the same potential or different potentials may be applied to the vertical gate portion 212a and the gate electrode 212c.
　また、本変形例４においては、図２１Ｂに示すように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の垂直ゲート部は、完全に金属を埋め込まない構造であってもよい。詳細には、垂直ゲート部２１２ｄは、チャネル形成領域である酸化物半導体層２１０の凸形状部である領域２１０ａに対向する面が閉じられ、且つ、内部が空洞である、筒状構造を持っていてもよい。すなわち、本変形例は、垂直ゲート部を完全に金属を埋め込まない構造であってもよいことから、量産性が高い構造であると言える。 Furthermore, in this modification 4, as shown in FIG. 21B, the vertical gate portions of the write transistor Tr2 and the switching transistor Tr4 may have a structure in which metal is not completely embedded. In detail, the vertical gate portion 212d may have a cylindrical structure in which the surface facing the region 210a, which is the convex portion of the oxide semiconductor layer 210 that is the channel formation region, is closed and the inside is hollow. In other words, since the vertical gate portions of this modification may have a structure in which metal is not completely embedded, it can be said that this structure is highly suitable for mass production.
　なお、図２１Ａ及び図２１Ｂに示す構成は、これまで説明した本開示の各実施形態及び変形例に適用してもよい。さらに、本変形例４においては、画素２０の書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、図２１Ａ及び図２１Ｂに示すような構成に限定されるものではない。 The configurations shown in Figures 21A and 21B may be applied to each of the embodiments and modifications of the present disclosure described thus far. Furthermore, in this modification 4, the writing transistor Tr2 and the switching transistor Tr4 of pixel 20 are not limited to the configurations shown in Figures 21A and 21B.
　＜１０．７　変形例５＞
　次に、図２２を参照して、本実施形態の変形例５を説明する。図２２は、本実施形態の変形例５に係る画素２０の断面構成の一例を示した模式図であり、詳細には、画素２０の積層構造を半導体基板１００の膜厚方向に沿って切断した際の断面に対応し、下側に半導体基板１００が位置するように図示されている。なお、これらの図においては、容量部Ｃ１、Ｃ２については、図示を省略している。 <10.7 Modification 5>
Next, a fifth modification of this embodiment will be described with reference to Fig. 22. Fig. 22 is a schematic diagram showing an example of a cross-sectional configuration of a pixel 20 according to the fifth modification of this embodiment, and in detail corresponds to a cross section obtained when the stacked structure of the pixel 20 is cut along the film thickness direction of the semiconductor substrate 100, and is illustrated so that the semiconductor substrate 100 is located on the lower side. Note that in these figures, the capacitance portions C1 and C2 are omitted from the illustration.
　これまで説明した第８の実施形態及び変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、１つの垂直ゲート部２１２ａを持つ垂直ゲート構造であったが、本変形例においては、複数の垂直ゲート部２１２ｂを持つ垂直ゲート構造であってもよい。詳細には、図２２の例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、２つの垂直ゲート部２１２ｂを持つ。なお、本変形例５においては、２つの垂直ゲート部２１２ｂを持つことに限定されるものではなく、２つ以上の垂直ゲート部２１２ｂを持っていればよい。 In the eighth embodiment and the modified examples described so far, the write transistor Tr2 and the switching transistor Tr4 have a vertical gate structure with one vertical gate portion 212a, but in this modified example, they may have a vertical gate structure with multiple vertical gate portions 212b. In particular, in the example of FIG. 22, the write transistor Tr2 and the switching transistor Tr4 have two vertical gate portions 212b. Note that in the modified example 5, the transistors are not limited to having two vertical gate portions 212b, and may have two or more vertical gate portions 212b.
　以上のように、本変形例５においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のゲート電極２１２が複数の垂直ゲート部２１２ｂを持つことにより、レイアウト面積を拡大することなく、ゲート長をより長くすることができる。さらに、本変形例５においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することをより効果的に抑制することができる。 As described above, in this modification 5, the gate electrodes 212 of the write transistor Tr2 and the switching transistor Tr4 have multiple vertical gate portions 212b, so that the gate length can be increased without increasing the layout area. Furthermore, in this modification 5, the source and drain can be separated further from the channel formation region of the write transistor Tr2 and the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be more effectively prevented from diffusing from the source and drain into the channel formation region, which would cause fluctuations in the characteristics of the channel formation region.
　＜１０．８　変形例６＞
　次に、図２３Ａから図２３Ｅを参照して、本実施形態の変形例６を説明する。図２３Ａから図２３Ｅは、本実施形態の変形例６に係る画素２０の平面構成の一例を示した模式図である。 <10.8 Modification 6>
Next, a sixth modification of this embodiment will be described with reference to Fig. 23A to Fig. 23E. Fig. 23A to Fig. 23E are schematic diagrams showing an example of a planar configuration of a pixel 20 according to the sixth modification of this embodiment.
　図２３Ａに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、互いに離隔して設けられていてもよい。また、図２３Ｂに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視において、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の垂直ゲート部２１２ａは、例えば、コ(日本語のカタカナの「コ」)字状に繋がっていてもよい。 As shown in FIG. 23A, in this modification, the write transistor Tr2 and the switching transistor Tr4 may be spaced apart from each other in a plan view of the write transistor Tr2 and the switching transistor Tr4. Also, as shown in FIG. 23B, in this modification, the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may be connected in a U shape (the Japanese katakana character "KOU") in a plan view of the write transistor Tr2 and the switching transistor Tr4.
　また、図２３Ｃに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視において、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、図中上下に並んで設けられていてもよい。さらに、図２３Ｃに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の垂直ゲート部２１２ａは、図中上下に延伸して互いに接続されていてもよい。 Also, as shown in FIG. 23C, in this modification, the write transistor Tr2 and the switching transistor Tr4 may be arranged vertically in a plan view. Furthermore, as shown in FIG. 23C, in this modification, the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may extend vertically and be connected to each other.
　図２３Ｄに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視において、ソース、ドレインを共有するように設けられていてもよい。このようにすることで、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の専有する面積を小さくすることができる。さらに、図２３Ｅに示すように、本変形例においては、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の平面視において、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の垂直ゲート部２１２ａは、例えば、コ(日本語のカタカナの「コ」)字状に繋がっていてもよい。 As shown in FIG. 23D, in this modification, the write transistor Tr2 and the switching transistor Tr4 may be provided so as to share the source and drain in a plan view. This can reduce the area occupied by the write transistor Tr2 and the switching transistor Tr4. Furthermore, as shown in FIG. 23E, in this modification, the vertical gate portions 212a of the write transistor Tr2 and the switching transistor Tr4 may be connected, for example, in a U shape in a plan view of the write transistor Tr2 and the switching transistor Tr4.
　以上のように、本変形例６によれば、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４の専有する面積を広くすることなく、ゲート長を長くしつつ、レイアウトの自由を確保することができる。 As described above, according to the sixth modification, it is possible to increase the gate length and ensure freedom of layout without increasing the area occupied by the write transistor Tr2 and the switching transistor Tr4.
　なお、図２３Ａから図２３Ｅに示す構成は、これまで説明した本開示の各実施形態及び変形例に適用してもよい。さらに、本変形例６においては、画素２０の書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４は、図２３Ａから図２３Ｅに示すような構成に限定されるものではない。 The configurations shown in Figures 23A to 23E may be applied to each of the embodiments and modifications of the present disclosure described thus far. Furthermore, in Modification 6, the writing transistor Tr2 and switching transistor Tr4 of pixel 20 are not limited to the configurations shown in Figures 23A to 23E.
　＜１０．９　製造方法＞
　次に、図２４Ａから図２４Ｂを参照して、上述の第８の実施形態に係る画素２０の製造方法の一例を説明する。図２４Ａ及び図２４Ｂは、本実施形態に係る画素（画素回路）２０の製造方法を説明するための断面図である。 <10.9 Manufacturing method>
Next, an example of a manufacturing method of the pixel 20 according to the above-described eighth embodiment will be described with reference to Fig. 24A and Fig. 24B. 2 is a cross-sectional view for explaining the manufacturing method of the device 20.
　まずは、図２４Ａの左側に示すように、半導体基板１００に駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を形成し、その上に配線層２００の一部を形成し、さらに、酸化作用膜（例えば、酸化シリコン）からなる絶縁膜２０２を形成する。さらに、絶縁膜２０２の上に、還元作用膜（例えば窒化シリコン）からなる絶縁膜４５０を形成する。次に、図２４Ａの左側から２番目に示すように、絶縁膜２０２、４５０に、エッチング等を用いてトレンチ４００を形成する。 First, as shown on the left side of FIG. 24A, a drive transistor Tr1 and a light emission control transistor Tr3 are formed on the semiconductor substrate 100, a part of the wiring layer 200 is formed thereon, and then an insulating film 202 made of an oxidation film (e.g., silicon oxide) is formed. Furthermore, an insulating film 450 made of a reduction film (e.g., silicon nitride) is formed on the insulating film 202. Next, as shown second from the left in FIG. 24A, a trench 400 is formed in the insulating films 202, 450 by etching or the like.
　さらに、図２４Ａの左側から３番目に示すように、絶縁膜２０２、４５０を覆うように、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域となる酸化物半導体層２１０を、ＡＬＤ（Ａｔｏｍｉｃ　Ｌａｙｅｒ　Ｄｅｐｏｓｉｔｉｏｎ）等の被覆性の高いプロセス技術を用いて形成する。 Furthermore, as shown in the third image from the left in FIG. 24A, an oxide semiconductor layer 210 that will become the channel formation region of the write transistor Tr2 and the switching transistor Tr4 is formed so as to cover the insulating films 202 and 450, using a process technology with high coverage such as ALD (Atomic Layer Deposition).
　次に、図２４Ａの左側から３番目に示すように、酸化物半導体層２１０を覆うように、ゲート絶縁膜となる例えば酸化シリコンからなる絶縁膜２０２を形成する。この際にも、ＡＬＤ等の被覆性の高いプロセス技術を用いることが好ましい。さらに、図２４Ａの右側に示すように、トレンチ内に垂直ゲート部２１２ａとなる電極材料を埋め込む。 Next, as shown in the third figure from the left in FIG. 24A, an insulating film 202 made of, for example, silicon oxide that will become a gate insulating film is formed so as to cover the oxide semiconductor layer 210. In this case, it is preferable to use a process technology with high coverage such as ALD. Furthermore, as shown in the right side of FIG. 24A, an electrode material that will become a vertical gate portion 212a is embedded in the trench.
　さらに、図２４Ｂの左側の上段に示すように、埋め込んだ電極を加工してもよい。もしくは、図２４Ｂの左側の中段に示すように、垂直ゲート部２１２ａの両側に位置する酸化物半導体層２１０にｎ型の不純物をイオン注入して、不純物拡散領域４６０を形成してもよい。もしくは、図２４Ｂの左側の下段に示すように、垂直ゲート部２１２ａの両側に位置する絶縁膜２０２を除去した後に、垂直ゲート部２１２ａの両側に位置する、露出された酸化物半導体層２１０にイオン注入して、不純物拡散領域４６０を形成してもよい。 Furthermore, as shown in the upper left part of FIG. 24B, the buried electrodes may be processed. Alternatively, as shown in the middle left part of FIG. 24B, n-type impurities may be ion-implanted into the oxide semiconductor layer 210 located on both sides of the vertical gate portion 212a to form the impurity diffusion region 460. Alternatively, as shown in the lower left part of FIG. 24B, the insulating film 202 located on both sides of the vertical gate portion 212a may be removed, and then ions may be implanted into the exposed oxide semiconductor layer 210 located on both sides of the vertical gate portion 212a to form the impurity diffusion region 460.
　次に、図２４Ｂの左側から２番目に示すように、絶縁膜２０２を積層する。さらに、図２４Ｂの左側から３番目に示すように、酸化物半導体層２１０のソース及びドレインとなる箇所に接続するビア２１４を形成し、図２４Ｂの右側に示すように、ビア２１４上に配線２０４を形成する。 Next, as shown in the second from the left in FIG. 24B, an insulating film 202 is laminated. Furthermore, as shown in the third from the left in FIG. 24B, vias 214 are formed to connect to the portions that will become the source and drain of the oxide semiconductor layer 210, and wiring 204 is formed on the vias 214 as shown in the right in FIG. 24B.
　以上のように、本実施形態においては、絶縁膜２０２、４５０の積層の上に、トレンチ４００を形成して酸化物半導体層２１０を形成し、さらに絶縁膜２０２を介して酸化物半導体層２１０と接するゲート（垂直ゲート部２１２ａ）を形成している。すなわち、本実施形態によれば、酸化作用膜からなる絶縁膜２０２と還元作用膜からなる絶縁膜４５０との積層を利用することで、チャネルとなる領域２１０ａとソース及びドレインとなる領域２１０ｂを所望の特性を持つように、大幅に工程数を増やすことなく、容易に作り分けることができる。加えて、本実施形態においては、絶縁膜４５０の膜厚等を調整することにより、領域２１０ｂへの還元作用を自由に調整することができる。 As described above, in this embodiment, a trench 400 is formed on the laminate of insulating films 202 and 450 to form an oxide semiconductor layer 210, and a gate (vertical gate portion 212a) is formed in contact with the oxide semiconductor layer 210 via the insulating film 202. That is, according to this embodiment, by utilizing the laminate of the insulating film 202 made of an oxidation film and the insulating film 450 made of a reduction film, the region 210a that becomes the channel and the region 210b that becomes the source and drain can be easily and separately formed so as to have the desired characteristics without significantly increasing the number of processes. In addition, in this embodiment, the reduction action in region 210b can be freely adjusted by adjusting the film thickness of the insulating film 450, etc.
　すなわち、本開示の第８の実施形態に係る画素２０は、一般的な半導体装置の製造に用いられる、方法、装置、及び条件を用いることで製造することが可能である。すなわち、本実施形態に係る画素２０は、既存の半導体装置の製造方法を用いて製造することが可能である。 In other words, the pixel 20 according to the eighth embodiment of the present disclosure can be manufactured using methods, devices, and conditions that are used in the manufacture of general semiconductor devices. In other words, the pixel 20 according to this embodiment can be manufactured using existing semiconductor device manufacturing methods.
　なお、上述の方法としては、例えば、ＰＶＤ（Ｐｈｙｓｉｃａｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）法、ＣＶＤ法及びＡＬＤ法等を挙げることができる。ＰＶＤ法としては、真空蒸着法、ＥＢ（電子ビーム）蒸着法、各種スパッタリング法（マグネトロンスパッタリング法、ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）－ＤＣ（Ｄｉｒｅｃｔ　Ｃｕｒｒｅｎｔ）結合形バイアススパッタリング法、ＥＣＲ（Ｅｌｅｃｔｒｏｎ　Ｃｙｃｌｏｔｒｏｎ　Ｒｅｓｏｎａｎｃｅ）スパッタリング法、対向ターゲットスパッタリング法、高周波スパッタリング法等）、イオンプレーティング法、レーザーアブレーション法、分子線エピタキシー法（ＭＢＥ（Ｍｏｌｅｃｕｌａｒ　Ｂｅａｍ　Ｅｐｉｔａｘｙ）法）、レーザ転写法を挙げることができる。また、ＣＶＤ法としては、プラズマＣＶＤ法、熱ＣＶＤ法、有機金属（ＭＯ）ＣＶＤ法、光ＣＶＤ法を挙げることができる。さらに、他の方法としては、電解メッキ法や無電解メッキ法、スピンコート法；浸漬法；キャスト法；マイクロコンタクトプリント法；ドロップキャスト法；スクリーン印刷法やインクジェット印刷法、オフセット印刷法、グラビア印刷法、フレキソ印刷法といった各種印刷法；スタンプ法；スプレー法；エアドクタコーター法、ブレードコーター法、ロッドコーター法、ナイフコーター法、スクイズコーター法、リバースロールコーター法、トランスファーロールコーター法、グラビアコーター法、キスコーター法、キャストコーター法、スプレーコーター法、スリットオリフィスコーター法、カレンダーコーター法といった各種コーティング法を挙げることができる。さらに、パターニング法としては、シャドーマスク、レーザ転写、フォトリソグラフィー等の化学的エッチング、紫外線やレーザ等による物理的エッチング等を挙げることができる。加えて、平坦化技術としては、ＣＭＰ法、レーザ平坦化法、リフロー法等を挙げることができる。 The above-mentioned methods include, for example, PVD (Physical Vapor Deposition), CVD, and ALD. Examples of PVD methods include vacuum deposition, EB (Electron Beam) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) combined bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Examples of the CVD method include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Examples of the patterning method include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light, laser, and the like. In addition, planarization techniques include CMP, laser planarization, and reflow.
　＜＜１１．　まとめ＞＞
　以上のように、本開示の各実施形態によれば、駆動回路に含まれるトランジスタに対する要求特性を満たしつつ、駆動回路のレイアウトサイズを小さくし、且つ、待機時の消費電力も下げることができる。 <<11. Summary>>
As described above, according to each embodiment of the present disclosure, it is possible to reduce the layout size of the drive circuit and reduce power consumption during standby while satisfying the required characteristics of transistors included in the drive circuit.
　詳細には、本実施形態においては、駆動回路に含まれる駆動トランジスタＴｒ１及び発光制御トランジスタＴｒ３を半導体基板１００に設け、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４を、薄膜トランジスタ（ＴＦＴ）として、半導体基板１００上に積層された配線層２００内に設けている。このようにすることで、本実施形態によれば、所定のトランジスタについては高い耐圧を確保しつつ、駆動回路のレイアウトサイズを小さくすることができ、ひいては、表示装置１０を小型化、微細化することができる。 In detail, in this embodiment, the drive transistor Tr1 and the light emission control transistor Tr3 included in the drive circuit are provided on the semiconductor substrate 100, and the write transistor Tr2 and the switching transistor Tr4 are provided as thin film transistors (TFTs) in the wiring layer 200 laminated on the semiconductor substrate 100. In this way, according to this embodiment, it is possible to reduce the layout size of the drive circuit while ensuring a high withstand voltage for certain transistors, and ultimately to make the display device 10 smaller and finer.
　また、本実施形態においては、薄膜トランジスタ（ＴＦＴ）である書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のチャネル形成領域を酸化物半導体層２１０で形成することにより、書込みトランジスタＴｒ２及びスイッチングトランジスタＴｒ４のリークを抑えることができる。詳細には、本実施形態によれば、書込みトランジスタＴｒ２におけるリークを抑制することができることから、長時間の信号保持が可能となることから、待機時のフレームレートを下げて、多画素化に伴う表示装置１０の消費電力の増加を抑えることができる。また、本実施形態によれば、スイッチングトランジスタＴｒ４におけるリークを抑制することができることから、黒浮きが低減され、コントラストが向上し、表示装置１０の消費電力の増加を抑えることができる。さらに、本実施形態によれば、スイッチングトランジスタＴｒ４をＮチャネル型トランジスタとして形成することが容易である。そのため、Ｎチャネル型トランジスタであるスイッチングトランジスタＴｒ４により、発光素子ＥＬのカソード－アノード間を０Ｖに安定的に制御することが可能となり、発光素子ＥＬに電流が供給されないようにすることができる。その結果、本実施形態によれば、黒階調表示時のコントラストの低下を抑制することができる。 In addition, in this embodiment, the channel formation regions of the write transistor Tr2 and the switching transistor Tr4, which are thin film transistors (TFTs), are formed from the oxide semiconductor layer 210, thereby suppressing leakage from the write transistor Tr2 and the switching transistor Tr4. In detail, according to this embodiment, leakage from the write transistor Tr2 can be suppressed, and therefore a signal can be held for a long time, and the frame rate during standby can be lowered and the increase in power consumption of the display device 10 due to the increase in the number of pixels can be suppressed. In addition, according to this embodiment, leakage from the switching transistor Tr4 can be suppressed, and therefore black floating can be reduced, the contrast can be improved, and the increase in power consumption of the display device 10 can be suppressed. Furthermore, according to this embodiment, it is easy to form the switching transistor Tr4 as an N-channel transistor. Therefore, the switching transistor Tr4, which is an N-channel transistor, can stably control the cathode-anode of the light-emitting element EL to 0 V, and it is possible to prevent current from being supplied to the light-emitting element EL. As a result, according to this embodiment, it is possible to suppress a decrease in contrast when displaying black gradations.
　さらに、本実施形態においては、スイッチングトランジスタＴｒ４のゲート電極２１２を垂直ゲート構造にすることにより、レイアウト面積を拡大することなく、ゲート長を容易に長くすることができる。さらに、垂直ゲート部２１２ａを長くすることにより、スイッチングトランジスタＴｒ４のチャネル形成領域からソース、ドレインをより離すことができることから、ソース、ドレインにコンタクトを形成する際に、ソース、ドレインから水素がチャネル形成領域へ拡散し、チャネル形成領域の特性が変動することを抑制することができる。 Furthermore, in this embodiment, by making the gate electrode 212 of the switching transistor Tr4 a vertical gate structure, the gate length can be easily increased without expanding the layout area. Furthermore, by lengthening the vertical gate portion 212a, the source and drain can be separated further from the channel formation region of the switching transistor Tr4, so that when forming contacts at the source and drain, hydrogen can be prevented from diffusing from the source and drain into the channel formation region, which can cause fluctuations in the characteristics of the channel formation region.
　なお、本開示の技術は、表示装置１０に適用されるだけでなく、照明装置等に適用されてもよい。 The technology disclosed herein may be applied not only to the display device 10 but also to lighting devices, etc.
　また、上述した本開示の実施形態においては、半導体基板１００は、必ずしもシリコン基板でなくてもよく、他の基板（例えば、ＳＯＩ（Ｓｉｌｉｃｏｎ　Ｏｎ　Ｉｎｓｕｌａｔｏｒ）基板やＳｉＧｅ基板等）でも良い。 Furthermore, in the above-described embodiment of the present disclosure, the semiconductor substrate 100 does not necessarily have to be a silicon substrate, but may be another substrate (e.g., an SOI (Silicon On Insulator) substrate, a SiGe substrate, etc.).
　＜＜１２．　適用例＞＞
　例えば、本開示に係る技術は、様々な電子機器の表示部等に適用されてもよい。そこで、以下、本技術を適用することができる電子機器の例について説明する。 <<12. Application Examples>>
For example, the technology according to the present disclosure may be applied to the display units of various electronic devices, etc. Therefore, hereinafter, examples of electronic devices to which the present technology can be applied will be described.
　（具体例１）
　図２５Ａは、デジタルスチルカメラ５００の外観の一例を示す正面図であり、図２５Ｂは、デジタルスチルカメラ５００の外観の一例を示す背面図である。このデジタルスチルカメラ５００は、レンズ交換式一眼レフレックスタイプのものであり、カメラ本体部（カメラボディ）５１１の正面略中央に交換式の撮影レンズユニット（交換レンズ）５１２を有し、正面左側に撮影者が把持するためのグリップ部５１３を有している。 (Specific Example 1)
Fig. 25A is a front view showing an example of the external appearance of digital still camera 500, and Fig. 25B is a rear view showing an example of the external appearance of digital still camera 500. This digital still camera 500 is a lens-interchangeable single-lens reflex type, and has an interchangeable photographing lens unit (interchangeable lens) 512 approximately in the center of the front of a camera main body section (camera body) 511, and a grip section 513 for the photographer to hold on the left side of the front.
　カメラ本体部５１１の背面中央から左側にずれた位置には、モニタ５１４が設けられている。モニタ５１４の上部には、電子ビューファインダ（接眼窓）５１５が設けられている。撮影者は、電子ビューファインダ５１５を覗くことによって、撮影レンズユニット５１２から導かれた被写体の光像を視認して構図決定を行うことが可能である。モニタ５１４や電子ビューファインダ５１５としては、本開示の実施形態に係る表示装置１０を用いることができる。 A monitor 514 is provided at a position shifted to the left from the center of the back of the camera body 511. An electronic viewfinder (eyepiece window) 515 is provided at the top of the monitor 514. By looking through the electronic viewfinder 515, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 512 and determine the composition. The display device 10 according to an embodiment of the present disclosure can be used as the monitor 514 or the electronic viewfinder 515.
　（具体例２）
　図２６は、ヘッドマウントディスプレイ６００の外観図である。ヘッドマウントディスプレイ６００は、例えば、眼鏡形の表示部６１１の両側に、使用者の頭部に装着するための耳掛け部６１２を有している。このヘッドマウントディスプレイ６００において、その表示部６１１として本開示の実施形態に係る表示装置１０を用いることができる。 (Specific Example 2)
26 is an external view of a head mounted display 600. The head mounted display 600 has, for example, ear hooks 612 for mounting on the user's head on both sides of a glasses-shaped display unit 611. In this head mounted display 600, the display device 10 according to the embodiment of the present disclosure can be used as the display unit 611.
　（具体例３）
　図２７は、シースルーヘッドマウントディスプレイ６３４の外観図である。シースルーヘッドマウントディスプレイ６３４は、本体部６３２、アーム６３３および鏡筒６３１で構成される。 (Specific Example 3)
27 is an external view of the see-through head mounted display 634. The see-through head mounted display 634 is composed of a main body 632, an arm 633, and a lens barrel 631.
　本体部６３２は、アーム６４３および眼鏡６３０と接続される。具体的には、本体部６３２の長辺方向の端部はアーム６３３と結合され、本体部６３２の側面の一側は接続部材を介して眼鏡６３０と連結される。なお、本体部６３２は、直接的に人体の頭部に装着されてもよい。 Main body 632 is connected to arm 643 and glasses 630. Specifically, the end of the long side of main body 632 is connected to arm 633, and one side of main body 632 is connected to glasses 630 via a connecting member. Note that main body 632 may also be worn directly on the head of the human body.
　本体部６３２は、シースルーヘッドマウントディスプレイ６３４の動作を制御するための制御基板や、表示部を内蔵する。アーム６３３は、本体部６３２と鏡筒６３１とを接続させ、鏡筒６３１を支える。具体的には、アーム６３３は、本体部６３２の端部および鏡筒６３１の端部とそれぞれ結合され、鏡筒６３１を固定する。また、アーム６３３は、本体部６３２から鏡筒６３１に提供される画像に係るデータを通信するための信号線を内蔵する。 The main body 632 incorporates a control board for controlling the operation of the see-through head mounted display 634, and a display unit. The arm 633 connects the main body 632 to the telescope tube 631, and supports the telescope tube 631. Specifically, the arm 633 is coupled to an end of the main body 632 and an end of the telescope tube 631, respectively, and fixes the telescope tube 631. The arm 633 also incorporates a signal line for communicating data related to images provided from the main body 632 to the telescope tube 631.
　鏡筒６３１は、本体部６３２からアーム６３３を経由して提供される画像光を、接眼レンズを通じて、シースルーヘッドマウントディスプレイ６３４を装着するユーザの目に向かって投射する。このシースルーヘッドマウントディスプレイ６３４において、本体部６３２の表示部に、本開示の実施形態に係る表示装置１０を用いることができる。 The lens barrel 631 projects image light provided from the main body 632 via the arm 633 through an eyepiece lens toward the eyes of a user wearing the see-through head mounted display 634. In this see-through head mounted display 634, the display unit of the main body 632 can use the display device 10 according to an embodiment of the present disclosure.
　（具体例４）
　図２８は、テレビジョン装置７１０の外観の一例を示す。このテレビジョン装置７１０は、例えば、フロントパネル７１２およびフィルターガラス７１３を含む映像表示画面部７１１を有し、この映像表示画面部７１１は、本開示の実施形態に係る表示装置１０により構成されている。 (Specific Example 4)
28 shows an example of the appearance of a television device 710. This television device 710 has, for example, an image display screen unit 711 including a front panel 712 and a filter glass 713, and this image display screen unit 711 is configured by the display device 10 according to the embodiment of the present disclosure.
　（具体例５）
　図２９は、スマートフォン８００の外観の一例を示す。スマートフォン８００は、各種情報を表示する表示部８０２や、ユーザによる操作入力を受け付けるボタン等から構成される操作部等を有する。上記表示部８０２は、本実施形態に係る表示装置１０であることができる。 (Specific Example 5)
29 shows an example of the appearance of a smartphone 800. The smartphone 800 has a display unit 802 that displays various information, an operation unit that includes buttons that accept operation inputs by a user, and the like. The display unit 802 can be the display device 10 according to this embodiment.
　（具体例６）
　図３０Ａ及び図３０Ｂは本開示の実施形態に係る表示装置１０を表示装置として有する自動車の内部の構成を示す図である。詳細には、図３０Ａは自動車の後方から前方にかけての自動車の内部の様子を示す図であり、図３０Ｂは自動車の斜め後方から斜め前方にかけての自動車の内部の様子を示す図である。 (Specific Example 6)
30A and 30B are diagrams showing the internal configuration of a vehicle having the display device 10 according to an embodiment of the present disclosure as a display device. In detail, Fig. 30A is a diagram showing the state of the interior of the vehicle from the rear to the front, and Fig. 30B is a diagram showing the state of the interior of the vehicle from the diagonally rear to the diagonally front.
　図３０Ａ及び図３０Ｂに示される自動車は、センターディスプレイ９１１と、コンソールディスプレイ９１２と、ヘッドアップディスプレイ９１３と、デジタルリアミラー９１４と、ステアリングホイールディスプレイ９１５と、リアエンタテイメントディスプレイ９１６とを有する。これらディスプレイの一部または全部は、本開示の実施形態に係る表示装置１０を適用することができる。 The automobile shown in Figures 30A and 30B has a center display 911, a console display 912, a head-up display 913, a digital rear mirror 914, a steering wheel display 915, and a rear entertainment display 916. Some or all of these displays can be implemented using the display device 10 according to an embodiment of the present disclosure.
　センターディスプレイ９１１は、センターコンソール９０７上の運転席９０１及び助手席９０２に対向する場所に配置されている。図３０Ａ及び図３０Ｂでは、運転席９０１側から助手席９０２側まで延びる横長形状のセンターディスプレイ９１１の例を示すが、センターディスプレイ９１１の画面サイズや配置場所は任意である。センターディスプレイ９１１には、種々のセンサ（図示省略）で検知された情報を表示可能である。具体的な一例として、センターディスプレイ９１１には、イメージセンサで撮影した撮影画像、ＴｏＦ（Ｔｉｍｅ　ｏｆ　Ｆｌｉｇｈｔ）センサで計測された自動車前方や側方の障害物までの距離画像、赤外線センサで検出された乗客の体温などを表示可能である。センターディスプレイ９１１は、例えば、安全関連情報、操作関連情報、ライフログ、健康関連情報、認証／識別関連情報、及びエンタテイメント関連情報の少なくとも一つを表示するために用いることができる。 The center display 911 is disposed on the center console 907 in a position facing the driver's seat 901 and the passenger seat 902. Although Fig. 30A and Fig. 30B show an example of a horizontally elongated center display 911 extending from the driver's seat 901 side to the passenger seat 902 side, the screen size and the location of the center display 911 are arbitrary. The center display 911 can display information detected by various sensors (not shown). As a specific example, the center display 911 can display an image captured by an image sensor, a distance image to an obstacle in front of or to the side of the vehicle measured by a ToF (Time of Flight) sensor, and a passenger's body temperature detected by an infrared sensor. The center display 911 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information.
　安全関連情報は、居眠り検知、よそ見検知、同乗している子供のいたずら検知、シートベルト装着有無、乗員の置き去り検知などの情報であり、例えばセンターディスプレイ９１１の裏面側に重ねて配置されたセンサ（図示省略）にて検知される情報である。操作関連情報は、センサを用いて乗員の操作に関するジェスチャを検知する。検知されるジェスチャは、自動車内の種々の設備の操作を含んでいてもよい。例えば、空調設備、ナビゲーション装置、ＡＶ（Ａｕｄｉｏ/Ｖｉｓｕａｌ）装置、照明装置等の操作を検知する。ライフログは、乗員全員のライフログを含む。例えば、ライフログは、乗車中の各乗員の行動記録を含む。ライフログを取得及び保存することで、事故時に乗員がどのような状態であったかを確認できる。健康関連情報は、温度センサを用いて乗員の体温を検知し、検知した体温に基づいて乗員の健康状態を推測する。あるいは、イメージセンサを用いて乗員の顔を撮像し、撮像した顔の表情から乗員の健康状態を推測してもよい。さらに、乗員に対して自動音声で会話を行って、乗員の回答内容に基づいて乗員の健康状態を推測してもよい。認証／識別関連情報は、センサを用いて顔認証を行うキーレスエントリ機能や、顔識別でシート高さや位置の自動調整機能などを含む。エンタテイメント関連情報は、センサを用いて乗員によるＡＶ装置の操作情報を検出する機能や、センサで乗員の顔を認識して、乗員に適したコンテンツをＡＶ装置にて提供する機能などを含む。 The safety-related information includes information such as detection of drowsiness, detection of distraction, detection of tampering by children in the car, whether or not a seat belt is fastened, and detection of an occupant being left behind, and is information detected, for example, by a sensor (not shown) arranged on the back side of the center display 911. The operation-related information is obtained by detecting gestures related to the operation of the occupant using a sensor. The detected gestures may include operations of various equipment in the car. For example, operations of the air conditioning equipment, navigation device, AV (Audio/Visual) device, lighting device, etc. are detected. The life log includes the life log of all occupants. For example, the life log includes a record of the actions of each occupant while in the car. By acquiring and saving the life log, it is possible to confirm the condition of the occupant at the time of the accident. The health-related information is obtained by detecting the body temperature of the occupant using a temperature sensor, and inferring the health condition of the occupant based on the detected body temperature. Alternatively, the face of the occupant may be captured using an image sensor, and the health condition of the occupant may be inferred from the facial expression captured in the image. Furthermore, the occupant may be spoken to by an automated voice and the occupant's health condition may be inferred based on the occupant's responses. Authentication/identification related information includes a keyless entry function that uses a sensor to perform face authentication, and a function for automatically adjusting seat height and position using face recognition. Entertainment related information includes a function for detecting operation information of an AV device by an occupant using a sensor, and a function for recognizing the occupant's face using a sensor and providing content suitable for the occupant via the AV device.
　コンソールディスプレイ９１２は、例えばライフログ情報の表示に用いることができる。コンソールディスプレイ９１２は、運転席９０１と助手席９０２の間のセンターコンソール９０７のシフトレバー９０８の近くに配置されている。コンソールディスプレイ９１２にも、種々のセンサ（図示省略）で検知された情報を表示可能である。また、コンソールディスプレイ９１２には、イメージセンサで撮像された車両周辺の画像を表示してもよいし、車両周辺の障害物までの距離画像を表示してもよい。 The console display 912 can be used, for example, to display life log information. The console display 912 is disposed near the shift lever 908 on the center console 907 between the driver's seat 901 and the passenger seat 902. The console display 912 can also display information detected by various sensors (not shown). The console display 912 may also display an image of the surroundings of the vehicle captured by an image sensor, or an image showing the distance to obstacles around the vehicle.
　ヘッドアップディスプレイ９１３は、運転席９０１の前方のフロントガラス９０４の奥に仮想的に表示される。ヘッドアップディスプレイ９１３は、例えば、安全関連情報、操作関連情報、ライフログ、健康関連情報、認証／識別関連情報、及びエンタテイメント関連情報の少なくとも一つを表示するために用いることができる。ヘッドアップディスプレイ９１３は、運転席９０１の正面に仮想的に配置されることが多いため、自動車の速度や燃料（バッテリ）残量等の自動車の操作に直接関連する情報を表示するのに適している。 The head-up display 913 is virtually displayed behind the windshield 904 in front of the driver's seat 901. The head-up display 913 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, and entertainment-related information. Since the head-up display 913 is often virtually positioned in front of the driver's seat 901, it is suitable for displaying information directly related to the operation of the vehicle, such as the vehicle's speed and remaining fuel (battery) level.
　デジタルリアミラー９１４は、自動車の後方を表示できるだけでなく、後部座席の乗員の様子も表示できるため、デジタルリアミラー９１４の裏面側に重ねてセンサ（図示省略）を配置することで、例えばライフログ情報の表示に用いることができる。 The digital rear-view mirror 914 can not only display the rear of the vehicle, but also the state of passengers in the back seats. For example, by placing a sensor (not shown) on the back side of the digital rear-view mirror 914, it can be used to display life log information.
　ステアリングホイールディスプレイ９１５は、自動車のハンドル９０６の中心付近に配置されている。ステアリングホイールディスプレイ９１５は、例えば、安全関連情報、操作関連情報、ライフログ、健康関連情報、認証／識別関連情報、及びエンタテイメント関連情報の少なくとも一つを表示するために用いることができる。特に、ステアリングホイールディスプレイ９１５は、運転者の手の近くにあるため、運転者の体温等のライフログ情報を表示したり、ＡＶ装置や空調設備等の操作に関する情報などを表示するのに適している。 The steering wheel display 915 is disposed near the center of the steering wheel 906 of the vehicle. The steering wheel display 915 can be used to display, for example, at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information. In particular, since the steering wheel display 915 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.
　リアエンタテイメントディスプレイ９１６は、運転席９０１や助手席９０２の背面側に取り付けられており、後部座席の乗員が視聴するためのものである。リアエンタテイメントディスプレイ９１６は、例えば、安全関連情報、操作関連情報、ライフログ、健康関連情報、認証／識別関連情報、及びエンタテイメント関連情報の少なくとも一つを表示するために用いることができる。特に、リアエンタテイメントディスプレイ９１６は、後部座席の乗員の目の前にあるため、後部座席の乗員に関連する情報が表示される。例えば、ＡＶ装置や空調設備の操作に関する情報を表示したり、後部座席の乗員の体温等を温度センサ（図示省略）で計測した結果を表示してもよい。 The rear entertainment display 916 is attached to the back of the driver's seat 901 and passenger seat 902, and is intended for viewing by rear seat passengers. The rear entertainment display 916 can be used to display at least one of safety-related information, operation-related information, life log, health-related information, authentication/identification-related information, and entertainment-related information, for example. In particular, since the rear entertainment display 916 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 916. For example, the rear entertainment display 916 may display information related to the operation of AV equipment or air conditioning equipment, or may display the results of measuring the body temperature of the rear seat passengers using a temperature sensor (not shown).
　＜＜１３．　補足＞＞
　以上、添付図面を参照しながら本開示の好適な実施形態について詳細に説明したが、本開示の技術的範囲はかかる例に限定されない。本開示の技術分野における通常の知識を有する者であれば、請求の範囲に記載された技術的思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、これらについても、当然に本開示の技術的範囲に属するものと了解される。 <<13. Supplementary Information>>
Although the preferred embodiment of the present disclosure has been described in detail above with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person having ordinary knowledge in the technical field of the present disclosure can come up with various modified or amended examples within the scope of the technical ideas described in the claims, and it is understood that these also naturally belong to the technical scope of the present disclosure.
　また、本明細書に記載された効果は、あくまで説明的または例示的なものであって限定的ではない。つまり、本開示に係る技術は、上記の効果とともに、または上記の効果に代えて、本明細書の記載から当業者には明らかな他の効果を奏しうる。 Furthermore, the effects described in this specification are merely descriptive or exemplary and are not limiting. In other words, the technology disclosed herein may achieve other effects that are apparent to a person skilled in the art from the description in this specification, in addition to or in place of the above effects.
　なお、本技術は以下のような構成も取ることができる。
（１）
　半導体基板上にマトリックス状に２次元配列する複数の画素を備え、
　前記各画素は、
　供給される電流に応じて輝度が変化する発光素子と、
　前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタと、
　を有し、
　前記第１のトランジスタは、
　前記半導体基板内に第１のチャネル形成領域を有し、
　前記第２のトランジスタは、
　前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、
　前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域と、
　を有する、
　表示装置。
（２）
　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
　前記半導体基板を下側に配置した場合、
　前記第１のトランジスタの上方に、前記第２のトランジスタが積層される、
　上記（１）に記載の表示装置。
（３）
　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
　前記半導体基板を下側に配置した場合、
　前記酸化物半導体層は、前記第１の垂直ゲート部に沿って下方に突出した凸形状部を持つ、
　上記（１）又は（２）に記載の表示装置。
（４）
　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
　前記半導体基板を下側に配置した場合、
　前記酸化物半導体層は、前記第１の垂直ゲート部に沿って上方に突出した凸形状部を持つ、
　上記（１）又は（２）に記載の表示装置。
（５）
　前記第１のゲート電極は、複数の前記第１の垂直ゲート部を有する、上記（１）～（４）のいずれか１つに記載の表示装置。
（６）
　前記酸化物半導体層は、アルミニウム、インジウム、ガリウム、スズ、及び、亜鉛からなる群から選択される少なくとも１つの元素を含む、上記（１）～（５）のいずれか１つに記載の表示装置。
（７）
　前記第２のトランジスタは、前記酸化物半導体層の前記凸形状部を挟み込むソース及びドレインを有する、上記（３）又は（４）に記載の表示装置。
（８）
　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層上に設けられた導電層を有する、上記（７）に記載の表示装置。
（９）
　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層下に設けられた導電層を有する、上記（７）に記載の表示装置。
（１０）
　前記第２のトランジスタの前記ソース及び前記ドレインは、２つの導電層に挟まれている、上記（７）に記載の表示装置。
（１１）
　前記導電層は、アルミニウム、チタン、タンタル及びモリブデンからなる群から選択される少なくとも１つの元素を含む金属又は合金等からなる、上記（８）～（１０）のいずれか１つに記載の表示装置。
（１２）
　前記第２のチャネル形成領域は、周囲から電子を奪う酸化作用膜からなる第１の絶縁層と接する、上記（７）～（１１）のいずれか１つに記載の表示装置。
（１３）
　前記酸化作用膜は、前記第２のチャネル形成領域に酸素を供給する酸素供給膜からなる、上記（１２）に記載の表示装置。
（１４）
　前記第２のトランジスタの前記ソース及び前記ドレインは、周囲に電子を与える還元作用膜からなる第２の絶縁層と接する、上記（７）～（１３）のいずれか１つに記載の表示装置。
（１５）
　前記還元作用膜は、前記ソース及び前記ドレインに水素を供給する水素供給膜からなる、上記（１４）に記載の表示装置。
（１６）
　前記還元作用膜の膜厚は、２０ｎｍ以上である、上記（１４）又は（１５）に記載の表示装置。
（１７）
　前記第１の垂直ゲート部は、前記第２のチャネル形成領域に対向する面が閉じられた筒状構造を持つ、上記（１）～（１６）のいずれか１つに記載の表示装置。
（１８）
　前記第２のトランジスタは、前記第１の垂直ゲート部と、前記第２のチャネル形成領域を挟んで対向する第３のゲート電極をさらに有する、
　上記（１）～（１７）のいずれか１つに記載の表示装置。
（１９）
　前記断面において、前記半導体基板を下側に配置した場合、
　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層の上面と接するコンタクトホールを有する、上記（７）に記載の表示装置。
（２０）
　前記断面において、前記半導体基板を下側に配置した場合、
　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層の下面と接するコンタクトホールを有する、上記（７）に記載の表示装置。
（２１）
　前記半導体基板を上方から見た平面視において、
　一対の前記コンタクトホールと前記第１のゲート電極とは、１つの線上に配列する、
　上記（１９）又は（２０）に記載の表示装置。
（２２）
　前記半導体基板を上方から見た平面視において、
　一対の前記コンタクトホールと前記第１のゲート電極とは、Ｌ字状に配列する、
　上記（１９）又は（２０）に記載の表示装置。
（２３）
　前記半導体基板を上方から見た平面視において、
　一対の前記コンタクトホールと前記第１のゲート電極とは、コ字状に配列する、
　上記（１９）又は（２０）に記載の表示装置。
（２４）
　前記半導体基板を上方から見た平面視において、
　前記画素の前記第２のトランジスタの一対の前記コンタクトホールと前記第１のゲート電極と、前記画素に隣接する他の画素の前記第２のトランジスタの一対の前記コンタクトホールの一方とは、Ｙ字状に配列する、
　上記（１９）又は（２０）に記載の表示装置。
（２５）
　前記複数のトランジスタは、第３のトランジスタ及び第４のトランジスタを含み、
　前記第３のトランジスタは、
　前記半導体基板内に第３のチャネル形成領域を有し、
　前記第４のトランジスタは、
　前記半導体基板の上方に積層された酸化物半導体層内の第４のチャネル形成領域を有する、
　上記（１）～（２３）のいずれか１つに記載の表示装置。
（２６）
　前記第４のトランジスタは、前記半導体基板の膜厚方向に沿って延伸する第２の垂直ゲート部を含む第２のゲート電極を有する、上記（２５）に記載の表示装置。
（２７）
　前記第１のトランジスタは、電流源及び前記発光素子と電気的に接続され、信号電圧に応じた電流を前記発光素子に供給する駆動トランジスタであり、
　前記第２のトランジスタは、前記発光素子と電気的に接続され、非発光期間に前記発光素子が発光しないように制御するスイッチングトランジスタであり、
　前記第３のトランジスタは、前記駆動トランジスタと電気的に接続され、前記発光素子の発光を制御する発光制御トランジスタであり、
　前記第４のトランジスタは、前記駆動トランジスタと電気的に接続し、容量部を介して前記信号電圧を前記駆動トランジスタに供給する書込みトランジスタである、
　上記（２５）又は（２６）に記載の表示装置。
（２８）
　前記発光素子は、ＯＬＥＤである、上記（１）～（２７）のいずれか１つに記載の表示装置。
（２９）
　表示装置を搭載する電子機器であって、
　前記表示装置は、
　半導体基板上にマトリックス状に２次元配列する複数の画素を備え、
　前記各画素は、
　供給される電流に応じて輝度が変化する発光素子と、
　前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタと、
　を有し、
　前記第１のトランジスタは、
　前記半導体基板内に第１のチャネル形成領域を有し、
　前記第２のトランジスタは、
　前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、
　前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域と、
　を有する、
　電子機器。 The present technology can also be configured as follows.
(1)
A plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate,
Each pixel is
A light-emitting element whose luminance changes in response to a current supplied thereto;
a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element;
having
The first transistor is
a first channel forming region in the semiconductor substrate;
The second transistor is
a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate;
a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film;
having
Display device.
(2)
In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
When the semiconductor substrate is placed on the lower side,
The second transistor is stacked above the first transistor.
The display device according to (1) above.
(3)
In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
When the semiconductor substrate is placed on the lower side,
the oxide semiconductor layer has a convex portion that protrudes downward along the first vertical gate portion;
The display device according to (1) or (2) above.
(4)
In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
When the semiconductor substrate is placed on the lower side,
the oxide semiconductor layer has a convex portion protruding upward along the first vertical gate portion;
The display device according to (1) or (2) above.
(5)
The display device according to any one of (1) to (4), wherein the first gate electrode has a plurality of the first vertical gate portions.
(6)
The display device according to any one of (1) to (5) above, wherein the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.
(7)
The display device according to any one of (3) to (4), wherein the second transistor has a source and a drain sandwiching the convex portion of the oxide semiconductor layer.
(8)
The display device according to (7), wherein the source and the drain of the second transistor include a conductive layer provided over the oxide semiconductor layer.
(9)
The display device according to (7), wherein the source and the drain of the second transistor include a conductive layer provided under the oxide semiconductor layer.
(10)
The display device according to claim 7, wherein the source and the drain of the second transistor are sandwiched between two conductive layers.
(11)
The display device according to any one of (8) to (10) above, wherein the conductive layer is made of a metal or an alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum.
(12)
The display device according to any one of (7) to (11) above, wherein the second channel formation region is in contact with a first insulating layer made of an oxidation film that removes electrons from the surroundings.
(13)
The display device according to (12) above, wherein the oxidation film is an oxygen supply film that supplies oxygen to the second channel formation region.
(14)
The display device according to any one of (7) to (13) above, wherein the source and the drain of the second transistor are in contact with a second insulating layer made of a reduction-reactive film that provides electrons to the surroundings.
(15)
The display device according to (14) above, wherein the reduction film is a hydrogen supply film that supplies hydrogen to the source and the drain.
(16)
The display device according to the above (14) or (15), wherein the reduction film has a thickness of 20 nm or more.
(17)
The display device according to any one of (1) to (16) above, wherein the first vertical gate portion has a cylindrical structure with a surface facing the second channel formation region closed.
(18)
the second transistor further includes a third gate electrode that faces the first vertical gate portion with the second channel formation region interposed therebetween;
The display device according to any one of (1) to (17) above.
(19)
In the cross section, when the semiconductor substrate is placed on the lower side,
The display device according to (7), wherein the source and the drain of the second transistor have contact holes in contact with an upper surface of the oxide semiconductor layer.
(20)
In the cross section, when the semiconductor substrate is placed on the lower side,
The display device according to (7), wherein the source and the drain of the second transistor have contact holes in contact with a lower surface of the oxide semiconductor layer.
(21)
In a plan view of the semiconductor substrate from above,
a pair of the contact holes and the first gate electrode are arranged on a line;
The display device according to (19) or (20) above.
(22)
In a plan view of the semiconductor substrate from above,
The pair of contact holes and the first gate electrode are arranged in an L-shape.
The display device according to (19) or (20) above.
(23)
In a plan view of the semiconductor substrate from above,
The pair of contact holes and the first gate electrode are arranged in a U-shape.
The display device according to (19) or (20) above.
(24)
In a plan view of the semiconductor substrate from above,
the pair of contact holes and the first gate electrode of the second transistor of the pixel, and one of the pair of contact holes of the second transistor of another pixel adjacent to the pixel, are arranged in a Y shape;
The display device according to (19) or (20) above.
(25)
the plurality of transistors includes a third transistor and a fourth transistor,
The third transistor is
a third channel forming region in the semiconductor substrate;
The fourth transistor is
a fourth channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate;
The display device according to any one of (1) to (23) above.
(26)
The display device according to (25) above, wherein the fourth transistor has a second gate electrode including a second vertical gate portion extending along a film thickness direction of the semiconductor substrate.
(27)
the first transistor is a drive transistor electrically connected to a current source and the light-emitting element, and supplies a current corresponding to a signal voltage to the light-emitting element;
the second transistor is a switching transistor that is electrically connected to the light-emitting element and controls the light-emitting element not to emit light during a non-light-emitting period;
the third transistor is an emission control transistor that is electrically connected to the drive transistor and controls emission of the light-emitting element;
the fourth transistor is a write transistor that is electrically connected to the drive transistor and supplies the signal voltage to the drive transistor via a capacitance section;
The display device according to (25) or (26) above.
(28)
The display device according to any one of (1) to (27) above, wherein the light-emitting element is an OLED.
(29)
An electronic device equipped with a display device,
The display device includes:
A plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate,
Each pixel is
A light-emitting element whose luminance changes in response to a current supplied thereto;
a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element;
having
The first transistor is
a first channel forming region in the semiconductor substrate;
The second transistor is
a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate;
a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film;
having
Electronics.
　　１０　　表示装置
　　２０、２０ａ　　画素
　　３０　　画素アレイ部
　　３１　　走査線
　　３２、３３　　駆動線
　　３４　　信号線
　　４０　　書き込み走査部
　　５０、６０　　駆動走査部
　　７０　　信号出力部
　　８０　　表示パネル
　　１００　　半導体基板
　　１０２、２１２、２１２ｃ、２３２　　ゲート電極
　　１０４　　拡散領域
　　１０６　　素子分離部
　　２００　　配線層
　　２０２、４５０　　絶縁膜
　　２０４　　配線
　　２０６、２１４　　ビア
　　２１２ａ、２１２ｂ、２１２ｄ　　垂直ゲート部
　　３１０、３１２　　電極
　　２１０、２３０　　酸化物半導体層
　　２１０ａ、２１０ｂ　　領域
　　２２０、２２２　　導電層
　　３００　　発光部
　　３１４　　発光層
　　４００、４０２　　トレンチ
　　４６０　　拡散領域
　　５００　　デジタルスチルカメラ
　　５１１　　カメラ本体部
　　５１２　　撮影レンズユニット
　　５１３　　グリップ部
　　５１４　　モニタ
　　５１５　　電子ビューファインダ
　　６００　　ヘッドマウントディスプレイ
　　６１１、８０２　　表示部
　　６１２　　耳掛け部
　　６３０　　眼鏡
　　６３１　　鏡筒
　　６３２　　本体部
　　６３３、６４３　　アーム
　　６３４　　シースルーヘッドマウントディスプレイ
　　７１０　　テレビジョン装置
　　７１１　　映像表示画面部
　　７１２　　フロントパネル
　　７１３　　フィルターガラス
　　８００　　スマートフォン
　　９０１　　運転席
　　９０２　　助手席
　　９０４　　フロントガラス
　　９０６　　ハンドル
　　９０７　　センターコンソール
　　９０８　　シフトレバー
　　９１１　　センターディスプレイ
　　９１２　　コンソールディスプレイ
　　９１３　　ヘッドアップディスプレイ
　　９１４　　デジタルリアミラー
　　９１５　　ステアリングホイールディスプレイ
　　９１６　　リアエンタテイメントディスプレイ
　　ＥＬ　　発光素子
　　Ｔｒ１、Ｔｒ２、Ｔｒ３、Ｔｒ４　　トランジスタ
　　Ｃ１、Ｃ２　　容量部 10 Display device 20, 20a Pixel 30 Pixel array section 31 Scanning line 32, 33 Drive line 34 Signal line 40 Write scanning section 50, 60 Drive scanning section 70 Signal output section 80 Display panel 100 Semiconductor substrate 102, 212, 212c, 232 Gate electrode 104 Diffusion region 106 Element isolation section 200 Wiring layer 202, 450 Insulating film 204 Wiring 206, 214 Via 212a, 212b, 212d Vertical gate section 310, 312 Electrode 210, 230 Oxide semiconductor layer 210a, 210b Region 220, 222 Conductive layer 300 Light-emitting section 314 Light-emitting layer 400, 402 Trench 460 Diffusion region 500 Digital still camera 511 Camera body 512 Shooting lens unit 513 Grip 514 Monitor 515 Electronic viewfinder 600 Head mounted display 611, 802 Display 612 Ear hook 630 Glasses 631 Lens barrel 632 Body 633, 643 Arm 634 See-through head mounted display 710 Television device 711 Video display screen 712 Front panel 713 Filter glass 800 Smartphone 901 Driver's seat 902 Passenger seat 904 Windshield 906 Steering wheel 907 Center console 908 Shift lever 911 Center display 912 Console display 913 Head-up display 914 Digital rear mirror 915 Steering wheel display 916 Rear entertainment display EL Light emitting element Tr1, Tr2, Tr3, Tr4 Transistors C1, C2 Capacitor

Claims (29)

  1. 　半導体基板上にマトリックス状に２次元配列する複数の画素を備え、
    　前記各画素は、
    　供給される電流に応じて輝度が変化する発光素子と、
    　前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタと、
    　を有し、
    　前記第１のトランジスタは、
    　前記半導体基板内に第１のチャネル形成領域を有し、
    　前記第２のトランジスタは、
    　前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、
    　前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域と、
    　を有する、
    　表示装置。     A plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate,
    Each pixel is
    A light-emitting element whose luminance changes in response to a current supplied thereto;
    a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element;
    having
    The first transistor is
    a first channel forming region in the semiconductor substrate;
    The second transistor is
    a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate;
    a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film;
    having
    Display device.
  2. 　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
    　前記半導体基板を下側に配置した場合、
    　前記第１のトランジスタの上方に、前記第２のトランジスタが積層される、
    　請求項１に記載の表示装置。     In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
    When the semiconductor substrate is placed on the lower side,
    The second transistor is stacked above the first transistor.
    The display device according to claim 1 .
  3. 　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
    　前記半導体基板を下側に配置した場合、
    　前記酸化物半導体層は、前記第１の垂直ゲート部に沿って下方に突出した凸形状部を持つ、
    　請求項１に記載の表示装置。     In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
    When the semiconductor substrate is placed on the lower side,
    the oxide semiconductor layer has a convex portion that protrudes downward along the first vertical gate portion;
    The display device according to claim 1 .
  4. 　前記半導体基板の膜厚方向に沿って前記画素を切断した断面において、
    　前記半導体基板を下側に配置した場合、
    　前記酸化物半導体層は、前記第１の垂直ゲート部に沿って上方に突出した凸形状部を持つ、
    　請求項１に記載の表示装置。     In a cross section obtained by cutting the pixel along a film thickness direction of the semiconductor substrate,
    When the semiconductor substrate is placed on the lower side,
    the oxide semiconductor layer has a convex portion protruding upward along the first vertical gate portion;
    The display device according to claim 1 .
  5. 　前記第１のゲート電極は、複数の前記第１の垂直ゲート部を有する、請求項１に記載の表示装置。 The display device of claim 1, wherein the first gate electrode has a plurality of the first vertical gate portions.
  6. 　前記酸化物半導体層は、アルミニウム、インジウム、ガリウム、スズ、及び、亜鉛からなる群から選択される少なくとも１つの元素を含む、請求項１に記載の表示装置。 The display device according to claim 1, wherein the oxide semiconductor layer contains at least one element selected from the group consisting of aluminum, indium, gallium, tin, and zinc.
  7. 　前記第２のトランジスタは、前記酸化物半導体層の前記凸形状部を挟み込むソース及びドレインを有する、請求項３に記載の表示装置。 The display device according to claim 3, wherein the second transistor has a source and a drain that sandwich the convex portion of the oxide semiconductor layer.
  8. 　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層上に設けられた導電層を有する、請求項７に記載の表示装置。 The display device according to claim 7, wherein the source and the drain of the second transistor have a conductive layer provided on the oxide semiconductor layer.
  9. 　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層下に設けられた導電層を有する、請求項７に記載の表示装置。 The display device according to claim 7, wherein the source and the drain of the second transistor have a conductive layer provided under the oxide semiconductor layer.
  10. 　前記第２のトランジスタの前記ソース及び前記ドレインは、２つの導電層に挟まれている、請求項７に記載の表示装置。 The display device of claim 7, wherein the source and the drain of the second transistor are sandwiched between two conductive layers.
  11. 　前記導電層は、アルミニウム、チタン、タンタル及びモリブデンからなる群から選択される少なくとも１つの元素を含む金属又は合金等からなる、請求項８に記載の表示装置。 The display device according to claim 8, wherein the conductive layer is made of a metal or alloy containing at least one element selected from the group consisting of aluminum, titanium, tantalum, and molybdenum.
  12. 　前記第２のチャネル形成領域は、周囲から電子を奪う酸化作用膜からなる第１の絶縁層と接する、請求項７に記載の表示装置。 The display device according to claim 7, wherein the second channel formation region is in contact with a first insulating layer made of an oxidation film that steals electrons from the surroundings.
  13. 　前記酸化作用膜は、前記第２のチャネル形成領域に酸素を供給する酸素供給膜からなる、請求項１２に記載の表示装置。 The display device according to claim 12, wherein the oxidation film is an oxygen supply film that supplies oxygen to the second channel formation region.
  14. 　前記第２のトランジスタの前記ソース及び前記ドレインは、周囲に電子を与える還元作用膜からなる第２の絶縁層と接する、請求項７に記載の表示装置。 The display device according to claim 7, wherein the source and the drain of the second transistor are in contact with a second insulating layer made of a reduction-reactive film that provides electrons to the surroundings.
  15. 　前記還元作用膜は、前記ソース及び前記ドレインに水素を供給する水素供給膜からなる、請求項１４に記載の表示装置。 The display device according to claim 14, wherein the reduction film is a hydrogen supply film that supplies hydrogen to the source and the drain.
  16. 　前記還元作用膜の膜厚は、２０ｎｍ以上である、請求項１４に記載の表示装置。 The display device according to claim 14, wherein the thickness of the reduction film is 20 nm or more.
  17. 　前記第１の垂直ゲート部は、前記第２のチャネル形成領域に対向する面が閉じられた筒状構造を持つ、請求項１に記載の表示装置。 The display device according to claim 1, wherein the first vertical gate portion has a cylindrical structure with a closed surface facing the second channel formation region.
  18. 　前記第２のトランジスタは、前記第１の垂直ゲート部と、前記第２のチャネル形成領域を挟んで対向する第３のゲート電極をさらに有する、
    　請求項１に記載の表示装置。     the second transistor further includes a third gate electrode that faces the first vertical gate portion with the second channel formation region interposed therebetween;
    The display device according to claim 1 .
  19. 　前記断面において、前記半導体基板を下側に配置した場合、
    　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層の上面と接するコンタクトホールを有する、請求項７に記載の表示装置。     In the cross section, when the semiconductor substrate is placed on the lower side,
    The display device according to claim 7 , wherein the source and the drain of the second transistor have contact holes in contact with an upper surface of the oxide semiconductor layer.
  20. 　前記断面において、前記半導体基板を下側に配置した場合、
    　前記第２のトランジスタの前記ソース及び前記ドレインは、前記酸化物半導体層の下面と接するコンタクトホールを有する、請求項７に記載の表示装置。     In the cross section, when the semiconductor substrate is placed on the lower side,
    The display device according to claim 7 , wherein the source and the drain of the second transistor have contact holes in contact with a lower surface of the oxide semiconductor layer.
  21. 　前記半導体基板を上方から見た平面視において、
    　一対の前記コンタクトホールと前記第１のゲート電極とは、１つの線上に配列する、
    　請求項１９に記載の表示装置。     In a plan view of the semiconductor substrate from above,
    a pair of the contact holes and the first gate electrode are arranged on a line;
    20. The display device according to claim 19.
  22. 　前記半導体基板を上方から見た平面視において、
    　一対の前記コンタクトホールと前記第１のゲート電極とは、Ｌ字状に配列する、
    　請求項１９に記載の表示装置。     In a plan view of the semiconductor substrate from above,
    The pair of contact holes and the first gate electrode are arranged in an L-shape.
    20. The display device according to claim 19.
  23. 　前記半導体基板を上方から見た平面視において、
    　一対の前記コンタクトホールと前記第１のゲート電極とは、コ字状に配列する、
    　請求項１９に記載の表示装置。     In a plan view of the semiconductor substrate from above,
    The pair of contact holes and the first gate electrode are arranged in a U-shape.
    20. The display device according to claim 19.
  24. 　前記半導体基板を上方から見た平面視において、
    　前記画素の前記第２のトランジスタの一対の前記コンタクトホールと前記第１のゲート電極と、前記画素に隣接する他の画素の前記第２のトランジスタの一対の前記コンタクトホールの一方とは、Ｙ字状に配列する、
    　請求項１９に記載の表示装置。     In a plan view of the semiconductor substrate from above,
    the pair of contact holes and the first gate electrode of the second transistor of the pixel, and one of the pair of contact holes of the second transistor of another pixel adjacent to the pixel, are arranged in a Y shape;
    20. The display device according to claim 19.
  25. 　前記複数のトランジスタは、第３のトランジスタ及び第４のトランジスタを含み、
    　前記第３のトランジスタは、
    　前記半導体基板内に第３のチャネル形成領域を有し、
    　前記第４のトランジスタは、
    　前記半導体基板の上方に積層された酸化物半導体層内の第４のチャネル形成領域を有する、
    　請求項１に記載の表示装置。     the plurality of transistors includes a third transistor and a fourth transistor,
    The third transistor is
    a third channel forming region in the semiconductor substrate;
    The fourth transistor is
    a fourth channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate;
    The display device according to claim 1 .
  26. 　前記第４のトランジスタは、前記半導体基板の膜厚方向に沿って延伸する第２の垂直ゲート部を含む第２のゲート電極を有する、請求項２５に記載の表示装置。 The display device of claim 25, wherein the fourth transistor has a second gate electrode including a second vertical gate portion extending along a film thickness direction of the semiconductor substrate.
  27. 　前記第１のトランジスタは、電流源及び前記発光素子と電気的に接続され、信号電圧に応じた電流を前記発光素子に供給する駆動トランジスタであり、
    　前記第２のトランジスタは、前記発光素子と電気的に接続され、非発光期間に前記発光素子が発光しないように制御するスイッチングトランジスタであり、
    　前記第３のトランジスタは、前記駆動トランジスタと電気的に接続され、前記発光素子の発光を制御する発光制御トランジスタであり、
    　前記第４のトランジスタは、前記駆動トランジスタと電気的に接続し、容量部を介して前記信号電圧を前記駆動トランジスタに供給する書込みトランジスタである、
    　請求項２５に記載の表示装置。     the first transistor is a drive transistor electrically connected to a current source and the light-emitting element, and supplies a current corresponding to a signal voltage to the light-emitting element;
    the second transistor is a switching transistor that is electrically connected to the light-emitting element and controls the light-emitting element not to emit light during a non-light-emitting period;
    the third transistor is an emission control transistor that is electrically connected to the drive transistor and controls emission of the light-emitting element;
    the fourth transistor is a write transistor that is electrically connected to the drive transistor and supplies the signal voltage to the drive transistor via a capacitance section;
    The display device according to claim 25.
  28. 　前記発光素子は、ＯＬＥＤである、請求項１に記載の表示装置。 The display device according to claim 1, wherein the light-emitting element is an OLED.
  29. 　表示装置を搭載する電子機器であって、
    　前記表示装置は、
    　半導体基板上にマトリックス状に２次元配列する複数の画素を備え、
    　前記各画素は、
    　供給される電流に応じて輝度が変化する発光素子と、
    　前記発光素子に電気的に接続する、少なくとも第１のトランジスタ及び第２のトランジスタを含む複数のトランジスタと、
    　を有し、
    　前記第１のトランジスタは、
    　前記半導体基板内に第１のチャネル形成領域を有し、
    　前記第２のトランジスタは、
    　前記半導体基板の膜厚方向に沿って延伸する第１の垂直ゲート部を含む第１のゲート電極と、
    　前記半導体基板の上方に積層された酸化物半導体層内であって、絶縁膜を介して前記第１のゲート電極と接する第２のチャネル形成領域と、
    　を有する、
    　電子機器。     An electronic device equipped with a display device,
    The display device includes:
    A plurality of pixels are arranged two-dimensionally in a matrix on a semiconductor substrate,
    Each pixel is
    A light-emitting element whose luminance changes in response to a current supplied thereto;
    a plurality of transistors including at least a first transistor and a second transistor electrically connected to the light emitting element;
    having
    The first transistor is
    a first channel forming region in the semiconductor substrate;
    The second transistor is
    a first gate electrode including a first vertical gate portion extending along a thickness direction of the semiconductor substrate;
    a second channel formation region in an oxide semiconductor layer stacked above the semiconductor substrate, the second channel formation region being in contact with the first gate electrode via an insulating film;
    having
    Electronics.
PCT/JP2024/000190 2023-01-11 2024-01-09 Display device and electronic apparatus WO2024150742A1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119674A (en) * 2009-10-30 2011-06-16 Semiconductor Energy Lab Co Ltd Semiconductor device
US20140216539A1 (en) * 2011-04-28 2014-08-07 Brookhaven Science Associates, Llc Interdigitated electrical contacts for low electronic mobility semiconductors
JP2015188080A (en) * 2014-03-13 2015-10-29 株式会社半導体エネルギー研究所 Semiconductor device, display device having semiconductor device, display module having display device, and electronic equipment having semiconductor device, display device and display module
JP2016187032A (en) * 2015-03-19 2016-10-27 株式会社半導体エネルギー研究所 Semiconductor device and electronic apparatus
JP2017157843A (en) * 2017-04-07 2017-09-07 株式会社半導体エネルギー研究所 Semiconductor device
JP2018025777A (en) * 2016-08-03 2018-02-15 株式会社半導体エネルギー研究所 Display device and electronic apparatus
US20180277614A1 (en) * 2017-03-24 2018-09-27 Apple Inc. Displays With Silicon and Semiconducting-Oxide Top-Gate Thin-Film Transistors
US20190198675A1 (en) * 2016-09-27 2019-06-27 Intel Corporation Non-planar gate thin film transistor

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011119674A (en) * 2009-10-30 2011-06-16 Semiconductor Energy Lab Co Ltd Semiconductor device
US20140216539A1 (en) * 2011-04-28 2014-08-07 Brookhaven Science Associates, Llc Interdigitated electrical contacts for low electronic mobility semiconductors
JP2015188080A (en) * 2014-03-13 2015-10-29 株式会社半導体エネルギー研究所 Semiconductor device, display device having semiconductor device, display module having display device, and electronic equipment having semiconductor device, display device and display module
JP2016187032A (en) * 2015-03-19 2016-10-27 株式会社半導体エネルギー研究所 Semiconductor device and electronic apparatus
JP2018025777A (en) * 2016-08-03 2018-02-15 株式会社半導体エネルギー研究所 Display device and electronic apparatus
US20190198675A1 (en) * 2016-09-27 2019-06-27 Intel Corporation Non-planar gate thin film transistor
US20180277614A1 (en) * 2017-03-24 2018-09-27 Apple Inc. Displays With Silicon and Semiconducting-Oxide Top-Gate Thin-Film Transistors
JP2017157843A (en) * 2017-04-07 2017-09-07 株式会社半導体エネルギー研究所 Semiconductor device

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