WO2024150098A1 - 半導体装置、及びその作製方法 - Google Patents

半導体装置、及びその作製方法 Download PDF

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Publication number
WO2024150098A1
WO2024150098A1 PCT/IB2024/050136 IB2024050136W WO2024150098A1 WO 2024150098 A1 WO2024150098 A1 WO 2024150098A1 IB 2024050136 W IB2024050136 W IB 2024050136W WO 2024150098 A1 WO2024150098 A1 WO 2024150098A1
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Prior art keywords
layer
transistor
insulating layer
conductive layer
opening
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PCT/IB2024/050136
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
木村肇
澤井寛美
倉田求
宮田翔希
和久田真弘
村川努
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to CN202480006297.4A priority Critical patent/CN120457790A/zh
Priority to JP2024569678A priority patent/JPWO2024150098A1/ja
Publication of WO2024150098A1 publication Critical patent/WO2024150098A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device having a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • Display devices are widely used in electronic devices.
  • the applications of display devices have become more diverse, and display devices are used in, for example, mobile information terminals, television devices (also called television receivers), digital signage, and public information displays (PIDs).
  • Examples of display devices include display devices having organic electroluminescence (EL) elements or light-emitting diodes (LEDs), display devices having liquid crystal elements, and electronic paper that displays using an electrophoretic method.
  • EL organic electroluminescence
  • LEDs light-emitting diodes
  • the pixel size can be reduced and the resolution can be increased.
  • the aperture ratio can be increased. For this reason, there is a demand for miniaturized transistors.
  • Devices requiring high-definition display devices such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • Patent document 1 discloses a high-definition display device that uses organic EL elements.
  • the saturation of the transistor decreases.
  • a driving transistor that controls a current flowing through a light-emitting element (also called a light-emitting device) of a pixel of a display device is miniaturized and its channel length is shortened, resulting in a decrease in saturation, the current flowing through the light-emitting element may become unstable, and the light emission luminance of the light-emitting element may become unstable.
  • the current flowing through the light-emitting element may vary over time, and even when a still image is being displayed, the light emission luminance of the light-emitting element may vary over time.
  • One aspect of the present invention has an object to provide a transistor having a fine size.
  • another object is to provide a transistor having a long channel length.
  • another object is to provide a transistor having a long channel length and a transistor having a short channel length.
  • another object is to provide a transistor having high saturation.
  • another object is to provide a transistor having good electrical characteristics.
  • another object is to provide a small semiconductor device.
  • another object is to provide a semiconductor device having low wiring resistance.
  • another object is to provide a semiconductor device or display device that operates at high speed.
  • another object is to provide a low-cost semiconductor device or display device.
  • another object is to provide a semiconductor device or display device that consumes low power.
  • another object is to provide a highly reliable transistor, semiconductor device, or display device. Or, another object is to provide a high-definition display device. Or, another object is to provide a method for manufacturing a semiconductor device or a display device with high productivity. Another objective is to provide a method for manufacturing a semiconductor device or a method for manufacturing a display device with low manufacturing costs. Another objective is to provide a new transistor, semiconductor device, display device, or a method for manufacturing these.
  • One aspect of the present invention is a semiconductor device having a first insulating layer, a second insulating layer on the first insulating layer, and a transistor, the transistor having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer, the second insulating layer having an opening reaching the first insulating layer, the first conductive layer and the second conductive layer being provided on the second insulating layer so as to face each other across the opening in a plan view, the semiconductor layer having a region in contact with the first conductive layer and a region in contact with the second conductive layer and being provided to have a region located inside the opening, the third insulating layer being provided on the semiconductor layer so as to have a region located inside the opening, and the third conductive layer being provided on the third insulating layer so as to have a region located inside the opening.
  • one aspect of the present invention has a first insulating layer, a second insulating layer on the first insulating layer, a first transistor, and a second transistor, the first transistor having a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a third insulating layer, the second transistor having a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a second semiconductor layer, and a third insulating layer, the fourth conductive layer being the first insulating a second insulating layer is provided on the fourth conductive layer, the second insulating layer having a first opening reaching the first insulating layer and a second opening reaching the fourth conductive layer, the first conductive layer and the second conductive layer are provided on the second insulating layer so as to face each other across the first opening in a plan view, the fifth conductive layer is provided on the second insulating layer and has a third opening having a region overlapping with the second opening, and the first semiconductor layer is The semiconductor
  • the length of the component of the channel length of the first transistor along the bottom surface of the first opening may be equal to or greater than the length of the component of the channel length of the first transistor along the side surface of the first opening.
  • the width of the first conductive layer and the width of the second conductive layer may each be greater than the width of the first semiconductor layer.
  • the second insulating layer has a first layer, a second layer on the first layer, and a third layer on the second layer, the first semiconductor layer and the second semiconductor layer contain a metal oxide, and the second layer may have a higher oxygen content than the first layer and the third layer.
  • the first layer and the third layer may have a smaller oxygen diffusion coefficient than the second layer.
  • the oxygen content may be measured using secondary ion mass spectrometry, X-ray photoelectron spectroscopy, or thermal desorption spectrometry.
  • the oxygen diffusion coefficient may be calculated by thermal desorption spectrometry or secondary ion mass spectrometry.
  • one aspect of the present invention includes forming a first insulating layer, forming a first conductive layer on the first insulating layer, forming a second insulating layer on the first insulating layer and on the first conductive layer, forming a conductive film on the second insulating layer, forming a first opening and a second opening having an area overlapping with the first conductive layer in the conductive film, forming a third opening having an area overlapping with the first opening and reaching the first insulating layer, and a fourth opening having an area overlapping with the second opening and reaching the first conductive layer in the second insulating layer, and processing the conductive film to form a second conductive layer and a third conductive layer facing each other across the second opening in a planar view, and forming a fourth conductive layer having the second opening, and
  • a method for manufacturing a semiconductor device includes forming a first semiconductor layer having a region in contact with the first conductive layer and a region in contact with the third conductive layer and a region located inside the third opening
  • a first layer, a second layer on the first layer, and a third layer on the second layer may be formed as the second insulating layer, layers containing metal oxide may be formed as the first semiconductor layer and the second semiconductor layer, and oxygen may be supplied to the second layer after the formation of the second layer and before the formation of the third layer.
  • the first layer and the third layer may be formed so as to have a smaller oxygen diffusion coefficient than the second layer.
  • One embodiment of the present invention can provide a transistor with a fine size.
  • a transistor with a long channel length can be provided.
  • a transistor with a long channel length and a transistor with a short channel length can be provided.
  • a transistor with high saturation can be provided.
  • a transistor with good electrical characteristics can be provided.
  • a small semiconductor device can be provided.
  • a semiconductor device with low wiring resistance can be provided.
  • a semiconductor device or display device that operates at high speed can be provided.
  • a low-cost semiconductor device or display device can be provided.
  • a semiconductor device or display device with low power consumption can be provided.
  • a highly reliable transistor, semiconductor device, or display device can be provided.
  • a high-definition display device can be provided.
  • a highly productive method for manufacturing a semiconductor device or a display device can be provided.
  • a low-cost method for manufacturing a semiconductor device or a display device can be provided.
  • a novel transistor, semiconductor device, display device, or a method for manufacturing these can be provided.
  • FIG. 1A and 1B are plan views showing a configuration example of a semiconductor device
  • Fig. 1C and 1D are cross-sectional views showing a configuration example of a semiconductor device
  • Fig. 2A is a plan view showing a configuration example of a semiconductor device
  • Fig. 2B and Fig. 2C are cross-sectional views showing the configuration example of the semiconductor device
  • 3A to 3C are cross-sectional views showing configuration examples of a semiconductor device
  • 4A and 4B are cross-sectional views showing a configuration example of a semiconductor device
  • Fig. 5A is a plan view showing a configuration example of a semiconductor device
  • Fig. 5B and Fig. 5C are cross-sectional views showing the configuration example of a semiconductor device.
  • 6A and 6B are cross-sectional views showing a configuration example of a semiconductor device.
  • 7A and 7B are plan and cross-sectional views illustrating a configuration example of a semiconductor device.
  • 8A is a plan view showing a configuration example of a semiconductor device
  • FIG 8B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 9A and 9B are plan views showing a configuration example of a semiconductor device.
  • 10A and 10B are plan views showing a configuration example of a semiconductor device.
  • 11A and 11B are plan views showing a configuration example of a semiconductor device.
  • 12A and 12B are plan views showing a configuration example of a semiconductor device.
  • 13A and 13B are plan views and a cross-sectional view showing a configuration example of a semiconductor device.
  • 14A and 14B are plan views and a cross-sectional view showing a configuration example of a semiconductor device.
  • 15A and 15B are plan views and a cross-sectional view showing a configuration example of a semiconductor device.
  • 16A and 16B are plan views and a cross-sectional view showing a configuration example of a semiconductor device.
  • Fig. 17A is a plan view showing a configuration example of a semiconductor device
  • Fig. 17B and Fig. 17C are cross-sectional views showing the configuration example of a semiconductor device.
  • 18A is a plan view showing a configuration example of a semiconductor device
  • FIG 18B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 19A and 19B are cross-sectional views showing a configuration example of a semiconductor device.
  • Fig. 20A is a plan view showing a configuration example of a semiconductor device
  • Fig. 20B and Fig. 20C are cross-sectional views showing the configuration example of a semiconductor device.
  • 21A is a plan view showing a configuration example of a semiconductor device
  • FIG 21B is a cross-sectional view showing the configuration example of a semiconductor device.
  • Fig. 22A is a block diagram showing a configuration example of a display device
  • Fig. 22B is a plan view showing a configuration example of a pixel
  • Fig. 22C and Fig. 22D are circuit diagrams showing a configuration example of a pixel.
  • 23A and 23B are plan views showing a configuration example of a display device
  • FIG. 23C is a cross-sectional view showing the configuration example of the display device.
  • 24A is a plan view showing a configuration example of a semiconductor device
  • FIG 24B is a cross-sectional view showing the configuration example of a semiconductor device.
  • Fig. 25A is a block diagram showing a configuration example of a display device
  • Fig. 25B is a circuit diagram showing a configuration example of a pixel.
  • 26A is a plan view showing a configuration example of a display device
  • FIG 26B is a cross-sectional view showing the configuration example of a display device.
  • FIG. 27 is a circuit diagram showing an example of the configuration of a pixel.
  • FIG. 28 is a timing chart showing an example of a method for driving a pixel.
  • FIG. 29 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 30 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 31 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 32 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 33 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 34 is a circuit diagram showing an example of a method for driving a pixel.
  • FIG. 35 is a circuit diagram showing an example of a method for driving a pixel.
  • 36A and 36B are plan views showing configuration examples of pixel circuits.
  • 37A and 37B are plan views showing configuration examples of pixel circuits.
  • 38A and 38B are plan views showing configuration examples of pixel circuits.
  • FIG. 39 is a plan view showing a configuration example of a pixel circuit.
  • 40A to 40E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 41A to 41C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 42A to 42D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 43A to 43D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 44A and 44B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 45A and 45B are perspective views showing a configuration example of a display device.
  • FIG. 46 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 47 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 48 is a cross-sectional view showing a configuration example of a display device.
  • Fig. 49A is a plan view showing a configuration example of a display device, and Fig. 49B and Fig. 49C are cross-sectional views showing the configuration example of the display device.
  • 50A and 50B are cross-sectional views showing a configuration example of a display device.
  • FIG. 51 is a cross-sectional view showing an example of the configuration of a display device.
  • 52A to 52D are diagrams showing configuration examples of electronic devices.
  • 53A to 53F are diagrams showing configuration examples of electronic devices.
  • FIGS. 54A to 54G are diagrams showing configuration examples of electronic devices.
  • 55A and 55B are cross-sectional views showing the configuration of a sample according to an example.
  • FIG. 56 is a graph showing the Id-Vg characteristics of a transistor according to an example.
  • 57A and 57B are graphs showing the Id-Vg characteristics of a transistor according to an example.
  • 58A and 58B are STEM images according to the embodiment.
  • FIG. 59 is a circuit diagram showing the configuration of a circuit used for evaluating the off-state current of a transistor according to an example.
  • FIG. 60 is an Arrhenius plot showing the evaluation results of the off-state current of the transistor according to the example.
  • 61A and 61B are graphs showing the Id-Vg characteristics of a transistor according to an example.
  • 62A and 62B are graphs showing the Id-Vd characteristics of a transistor according to an example.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.
  • the words “layer” and “film” may be interchangeable depending on the circumstances or situation.
  • the term “conductive layer” may be changed to the term “conductive film.”
  • the term “insulating layer” may be changed to the term “insulating film.”
  • the term “semiconductor layer” may be changed to the term “semiconductor film.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification and the like, the terms “source” and “drain” may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, etc., depending on the situation.
  • Gate and backgate can be used interchangeably. For this reason, in this specification and the like, the terms “gate” and “backgate” can be used interchangeably. Note that the names of the gate and backgate of a transistor can be appropriately changed depending on the situation, such as gate electrode and backgate electrode.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.
  • off-state current refers to the current that flows between the source and drain when a transistor is in an off state (also called a non-conducting state or cut-off state).
  • the off-state refers to a state in which the voltage between the gate and source is lower than the threshold voltage in an n-channel transistor (higher than the threshold voltage in a p-channel transistor).
  • “voltage” often refers to the potential difference between a certain potential and a reference potential (for example, ground potential (GND potential) or source potential). Also, “potential” is relative, and the potential applied to wiring, etc. may change depending on the reference potential. Therefore, “voltage” and “potential” can sometimes be used interchangeably.
  • a reference potential for example, ground potential (GND potential) or source potential.
  • potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential. Therefore, “voltage” and “potential” can sometimes be used interchangeably.
  • planar shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, in which case it may also be said that the planar shapes roughly match. Furthermore, when the planar shapes match or roughly match, it can also be said that the ends are aligned or roughly aligned.
  • planar shape of a certain component refers to the contour shape of the component when viewed in a plane.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed or the surface of the support (e.g., substrate) on which the component is formed.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • MML metal maskless
  • a device with an MML structure can be fabricated without using a metal mask, it is possible to exceed the upper limit of the definition caused by the alignment accuracy of the metal mask.
  • a device with an MML structure can eliminate the need for equipment related to fabricating a metal mask and a process for cleaning the metal mask.
  • a device with an MML structure is suitable for mass production because it is possible to keep fabrication costs low.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom to select materials and configurations and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • layers also called functional layers
  • the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • an insulating layer that functions as a spacer is provided on a base insulating layer.
  • the spacer has a first opening that reaches the base insulating layer.
  • a first transistor is provided so as to have a region located inside the first opening. Note that in the following description, the insulating layer that functions as a spacer may be simply referred to as a spacer, but the spacer may be read as an insulating layer.
  • a source electrode (first source electrode) and a drain electrode (first drain electrode) of the first transistor are provided on the spacer.
  • the first source electrode and the first drain electrode are provided to face each other across the first opening in a plan view.
  • the first semiconductor layer is provided so as to have a region located inside the first opening.
  • the first semiconductor layer is provided with a channel formation region of the first transistor.
  • the first semiconductor layer can be provided along the bottom surface and side surface of the first opening.
  • the first semiconductor layer can have, for example, a region in contact with the top surface of the first source electrode, a region in contact with the side surface of the first source electrode, a region in contact with the top surface of the first drain electrode, and a region in contact with the side surface of the first drain electrode.
  • a gate insulating layer and a gate electrode (first gate electrode) of the first transistor are provided in this order so as to have a region located inside the first opening.
  • the first gate electrode is provided so as to have a region overlapping with the first semiconductor layer through the gate insulating layer inside the first opening.
  • the first gate electrode is also provided so as to have a region facing the first semiconductor layer with the gate insulating layer sandwiched between them inside the first opening.
  • the top surface of A exposed by the opening is referred to as the bottom surface of the opening.
  • the side surface of B exposed by the opening is referred to as the side surface of the opening.
  • the channel length can be set not only in the direction along the bottom surface of the first opening in the first semiconductor layer, but also in the direction along the side surface of the first opening.
  • the channel length of the first transistor can be increased without increasing the area occupied by the first transistor, specifically, the area occupied by the first semiconductor layer, compared to the case where the first opening is not provided and, for example, a planar type transistor is used. Therefore, a transistor with a small size and high saturation can be realized.
  • the saturation of the driving transistor that controls the current flowing to the light-emitting element can be increased while miniaturizing the pixel. Therefore, the current flowing to the light-emitting element can be stabilized, and the light emission luminance of the light-emitting element can be stabilized.
  • the occurrence of variation over time in the current flowing to the light-emitting element can be suppressed, and the occurrence of variation over time in the light emission luminance of the light-emitting element can be suppressed.
  • a second transistor having a different configuration from the first transistor can be provided on the base insulating layer.
  • the first transistor and the second transistor can be formed using some of the same processes.
  • a first conductive layer that functions as one of the source electrode (second source electrode) and drain electrode (second drain electrode) of the second transistor is provided on a base insulating layer.
  • the spacer is provided on the first conductive layer.
  • the spacer has a second opening that reaches the first conductive layer.
  • the second opening can be formed in the same process as the first opening.
  • a second transistor is provided so as to have a region located inside the second opening.
  • a second conductive layer that functions as the other of the second source electrode and the second drain electrode is provided on the spacer.
  • the second conductive layer has a third opening that has an area that overlaps with the second opening.
  • the second conductive layer can be formed in the same process using the same material as the first source electrode and the first drain electrode.
  • the first source electrode, the first drain electrode, and the second conductive layer can be formed by processing the same conductive film.
  • the second semiconductor layer is provided so as to have a region located inside the second opening and a region located inside the third opening.
  • the second semiconductor layer is provided with a channel formation region in the second transistor.
  • the second semiconductor layer can be provided along the side of the second opening and the side of the third opening.
  • the second semiconductor layer can have, for example, a region in contact with the top surface of the first conductive layer, the side of the second conductive layer, and the top surface of the second conductive layer.
  • the second semiconductor layer can be formed in the same process using the same material as the first semiconductor layer.
  • the first semiconductor layer and the second semiconductor layer can be formed by processing the same semiconductor film.
  • a gate insulating layer and a gate electrode (second gate electrode) of the second transistor are provided in this order on the second semiconductor layer so as to have a region located inside the second opening.
  • the second gate electrode is provided inside the second opening so as to have a region that faces the second semiconductor layer with the gate insulating layer sandwiched between them.
  • the gate insulating layer of the second transistor can be shared with the gate insulating layer of the first transistor.
  • the second gate electrode can be formed in the same process using the same material as the first gate electrode.
  • the first gate electrode and the second gate electrode can be formed by processing the same conductive film.
  • the channel length is along the side surface of the second opening of the spacer, but not in the direction parallel to the top surface of the base insulating layer. Therefore, the channel length of the second transistor is shorter than that of the first transistor. Therefore, the second transistor can have a larger on-state current than the first transistor. Therefore, by applying the second transistor to a selection transistor provided in the above-mentioned pixel, for example, a selection transistor having a function of selecting a pixel to which image data is written, the display device of one embodiment of the present invention can be driven at high speed.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less.
  • substantially parallel or “roughly parallel” refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.
  • substantially perpendicular or “approximately perpendicular” refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.
  • the semiconductor device of one embodiment of the present invention for example, multiple transistors with different electrical characteristics can be formed by sharing some of the steps. Therefore, it is possible to easily realize, for example, a circuit having desired performance while suppressing manufacturing costs. As described above, a semiconductor device having low cost and high performance can be realized. For example, when the semiconductor device of one embodiment of the present invention is applied to a display device, a display device that is low cost, has high definition, has high reliability, and operates at high speed can be realized.
  • Fig. 1A is a plan view showing a configuration example of a semiconductor device 10 which is a semiconductor device according to one embodiment of the present invention.
  • some of the components of the semiconductor device 10 for example, some insulating layers, are omitted.
  • some of the components are omitted from the plan views showing the configuration example of the semiconductor device in the subsequent drawings.
  • Fig. 1B is a plan view in which some of the elements are omitted from Fig. 1A.
  • Figure 1C is a cross-sectional view of the cut surface taken along dashed line A1-A2 in Figure 1A.
  • Figure 1D is a cross-sectional view of the cut surface taken along dashed line B1-B2 in Figure 1A.
  • an insulating layer 101 is provided on a substrate 102, and an insulating layer 110 and a transistor 100 are provided on the insulating layer 101.
  • the insulating layer 101 functions as a base insulating layer.
  • the insulating layer 110 functions as a spacer. Note that at least one of an electrode, a wiring, a transistor, a capacitor, a resistor, and the like may be provided between the substrate 102 and the insulating layer 101.
  • a base insulating layer may be provided on the substrate 102, a layer in which wiring is provided (also referred to as a wiring layer) may be provided on the base insulating layer, and the insulating layer 101 may be provided on the wiring layer.
  • the transistor 100 has a conductive layer 104, a conductive layer 112a, a conductive layer 112b, an insulating layer 106, and a semiconductor layer 108.
  • the conductive layer 104 functions as a gate electrode
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode
  • the conductive layer 112b functions as the other of the source electrode and the drain electrode.
  • Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure.
  • the insulating layer 110 has an opening 141 that reaches the insulating layer 101.
  • the transistor 100 is provided so as to have a region located inside the opening 141.
  • Conductive layers 112a and 112b are provided on the insulating layer 110. In other words, two conductive layers 112 are provided on the insulating layer 110 for each transistor 100. In the following description, the conductive layers with alphabetical characters added to the reference numeral "112" will be collectively referred to as conductive layer 112.
  • the ends of the conductive layers 112a and 112b are aligned with the ends of the insulating layer 110 on the opening 141 side.
  • the conductive layers 112a and 112b can be made of the same material.
  • the conductive layers 112a and 112b can be formed in the same process.
  • the conductive layers 112a and 112b can be formed by forming a conductive film that will become the conductive layers 112a and 112b, and processing the conductive film.
  • FIG. 1B is a diagram in which the conductive layer 104 is omitted from FIG. 1A. As shown in FIG. 1B, the conductive layer 112a and the conductive layer 112b are arranged to face each other across the opening 141 in a plan view.
  • the semiconductor layer 108 has a region located inside the opening 141.
  • the semiconductor layer 108 can be provided along the bottom and side surfaces of the opening 141.
  • the semiconductor layer 108 can also have, for example, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surface of the conductive layer 112b.
  • the semiconductor layer 108 can have a region in contact with the top surface of the insulating layer 101 and a region in contact with the side surface of the insulating layer 110.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b functions as the other.
  • a channel formation region is provided between the source region and the drain region.
  • the insulating layer 106 is provided to have a region located inside the opening 141, specifically, to cover the opening 141.
  • the insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, the insulating layer 110, and the insulating layer 101.
  • the insulating layer 106 has a shape along the upper surface and side surface of the semiconductor layer 108, the upper surfaces of the conductive layers 112a and 112b, the upper surface and side surface of the insulating layer 110, and the upper surface of the insulating layer 101.
  • the insulating layer 106 can have a region in contact with the upper surface of the semiconductor layer 108, a region in contact with the side surface of the semiconductor layer 108, a region in contact with the upper surface of the conductive layer 112a, a region in contact with the upper surface of the conductive layer 112b, a region in contact with the upper surface of the insulating layer 110, a region in contact with the side surface of the insulating layer 110, and a region in contact with the upper surface of the insulating layer 101. Also, although not shown in FIG. 1C and FIG.
  • the insulating layer 106 can have a shape that follows the side of the conductive layer 112a and the side of the conductive layer 112b, and can have a region that contacts the side of the conductive layer 112a and a region that contacts the side of the conductive layer 112b.
  • the conductive layer 104 is provided on the insulating layer 106 so as to have a region located inside the opening 141.
  • the conductive layer 104 is provided so as to have a region inside the opening 141 that overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 is also provided so as to have a region inside the opening 141 that faces the semiconductor layer 108 with the insulating layer 106 sandwiched between them.
  • the conductive layer 104 has a shape that follows the insulating layer 106, and specifically, can have a shape that follows the top surface of the insulating layer 106 and the side surface of the insulating layer 106 inside the opening 141.
  • the conductive layer 104 can have a region that contacts the top surface of the insulating layer 106 and a region that contacts the side surface of the insulating layer 106 inside the opening 141.
  • An insulating layer 109 is provided to cover the transistor 100.
  • the insulating layer 109 is provided over the conductive layer 104 and the insulating layer 106.
  • the insulating layer 109 functions as a protective layer for the transistor 100. Note that although an example in which the insulating layer 109 is not planarized is shown in FIG. 1C and FIG. 1D, the insulating layer 109 may be planarized.
  • the insulating layer 109 may have a stacked structure of an insulating layer that is not planarized and an insulating layer that is planarized on the insulating layer.
  • Figures 2A, 2B, and 2C are enlarged views of Figures 1B, 1C, and 1D, respectively.
  • the channel length, channel width, and other aspects of the transistor 100 will be explained using Figures 2A, 2B, and 2C.
  • the channel length of the transistor 100 is length L100
  • the channel width is width W100
  • the width of the opening 141 is width D141
  • the thickness of the insulating layer 110 is thickness T110_1
  • the angle between the side of the opening 141 of the insulating layer 110 and the top surface of the insulating layer 101 is angle ⁇ 110
  • the width of the conductive layer 112a is width W112a
  • the width of the conductive layer 112b is width W112b.
  • the length L100, width W100, width D141, thickness T110_1, width W112a, and width W112b are indicated by double-headed arrows. Similar notations are used in subsequent drawings.
  • the thickness T110_1 can be the shortest distance between the surface on which the insulating layer 110 is formed (here, the upper surface of the insulating layer 101) and the lower surface of the conductive layer 112a or the conductive layer 112b in a cross-sectional view.
  • width of a conductive layer that functions as a source electrode or a drain electrode refers to the length of the conductive layer in a direction parallel to the channel width direction. Therefore, width W112a and width W112b are parallel to width W100.
  • region 108i the regions of the semiconductor layer 108 are shown as region 108i, region 108na, and region 108nb.
  • Region 108i is provided between region 108na and region 108nb.
  • the region 108na is a region in contact with the conductive layer 112a of the semiconductor layer 108 and a region in its vicinity. At least a part of the region 108na functions as one of the source region and the drain region of the transistor 100.
  • the region 108nb is a region in contact with the conductive layer 112b of the semiconductor layer 108 and a region in its vicinity. At least a part of the region 108nb functions as the other of the source region and the drain region of the transistor 100.
  • At least a part of the region 108na and the region 108nb can be regions having lower electrical resistance than at least a part of the region 108i (hereinafter, also referred to as low resistance regions).
  • at least a part of the region 108na and the region 108nb can be regions having a higher carrier concentration or a higher oxygen defect density than at least a part of the region 108i.
  • 2B shows an example in which the height of the boundary between region 108i and region 108na coincides with or approximately coincides with the height of the boundary between insulating layer 110 and conductive layer 112a, and the height of the boundary between region 108i and region 108nb coincides with or approximately coincides with the height of the boundary between insulating layer 110 and conductive layer 112b, but these heights do not have to coincide or approximately coincide.
  • the heights are the same or approximately the same means that the heights from a reference surface (e.g., a flat surface such as a substrate surface) are the same in a cross-sectional view.
  • a planarization process may be performed to expose the surface of a single layer or multiple layers.
  • the surface to be processed in the planarization process has the same height from the reference surface.
  • the heights of the multiple layers may not be strictly the same depending on the processing device, processing method, or material of the processed surface during the planarization process.
  • “the heights are the same or approximately the same” is also used in this case.
  • the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, and this is also referred to as "the heights are the same or approximately the same".
  • the length L100 which is the channel length of the transistor 100, corresponds to the sum of twice the length of the side of the insulating layer 110 at the opening 141 in a cross-sectional view and the width D141 of the opening 141.
  • the length of the side of the insulating layer 110 at the opening 141 in a cross-sectional view can be determined by the thickness T110_1 and the angle ⁇ 110.
  • the height of the opening 141 can be the thickness T110_1.
  • the width D141 can be the length of the bottom of the opening 141 in a direction parallel to the component of the channel length of the transistor 100 along the bottom of the opening 141, for example, the maximum value of that length.
  • the channel length can be set not only in the direction along the bottom surface of the opening 141 (also referred to as the horizontal direction) in the semiconductor layer 108, but also in the direction along the side surface of the opening 141 (also referred to as the vertical direction).
  • the channel length of the transistor 100 can be increased without increasing the area occupied by the transistor 100, specifically, the area occupied by the semiconductor layer 108, compared to the case where the opening 141 is not provided and, for example, a planar type transistor is used. Therefore, a transistor with a small size and high saturation can be realized.
  • the saturation of the driving transistor that controls the current flowing to the light-emitting element can be increased while miniaturizing the pixel. Therefore, the current flowing to the light-emitting element can be stabilized, and the light emission luminance of the light-emitting element can be stabilized.
  • the occurrence of variation over time in the current flowing to the light-emitting element can be suppressed, and the occurrence of variation over time in the light emission luminance of the light-emitting element can be suppressed.
  • transistor 100 is configured so that current flows both vertically and horizontally, it can be called a VLFET (Vertical Lateral Field Effect Transistor).
  • VLFET Vertical Lateral Field Effect Transistor
  • the length L100 which is the channel length of the transistor 100, has a component along the bottom surface of the opening 141 and a component along the side surface of the opening 141.
  • the contribution of the component along the bottom surface of the opening 141 to the length L100 can be made larger than the contribution of the component along the side surface of the opening 141 to the length L100.
  • the width D141 of the opening 141 can be made different for each transistor 100.
  • the thickness T110_1 which can be the height of the opening 141, is equal or approximately equal between the multiple transistors 100. Therefore, by increasing the contribution of the component along the bottom surface of the opening 141 to the length L100, it becomes easier to control the length L100 between the multiple transistors 100, and more specifically, it becomes easier to make the length L100 different. This makes it easier to create multiple transistors 100 with different electrical characteristics in the circuit of the semiconductor device 10. This makes it easier to realize a circuit with desired performance. As a result, a semiconductor device with high performance can be realized.
  • the length of the component of the channel length of the transistor 100 along the bottom surface of the opening 141 is preferably equal to or greater than the length of the component of the channel length of the transistor 100 along the side surface of the opening 141.
  • the length L108 of the semiconductor layer 108 in a planar view in a direction parallel to the component of the channel length of the transistor 100 along the bottom surface of the opening 141 is preferably equal to or greater than the thickness T110_1.
  • the width D141 is preferably equal to or greater than the thickness T110_1.
  • the thickness T110_1 can be, for example, 0.1 nm or more and less than 3 ⁇ m, 0.1 nm or more and less than 2.5 ⁇ m, 1 nm or more and less than 2 ⁇ m, 1 nm or more and less than 1.5 ⁇ m, 5 nm or more and less than 1.2 ⁇ m, 5 nm or more and less than 1 ⁇ m, 7 nm or more and less than 500 nm, 7 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, or 10 nm or more and less than 50 nm.
  • the width D141 of the opening 141 is equal to or greater than the limit resolution of the exposure device.
  • the width D141 can be, for example, 200 nm or more and less than 5 ⁇ m, 200 nm or more and less than 4.5 ⁇ m, 200 nm or more and less than 4 ⁇ m, 300 nm or more and less than 3.5 ⁇ m, 300 nm or more and less than 3 ⁇ m, 400 nm or more and less than 2.5 ⁇ m, 400 nm or more and less than 2 ⁇ m, 500 nm or more and less than 1.5 ⁇ m, or 500 nm or more and less than 1 ⁇ m.
  • Figs. 1A, 1B, and 2A an example is shown in which the planar shape of the opening 141 is circular.
  • the width D141 can correspond to the diameter of the circle. Note that in this specification, a circle is not limited to a perfect circle.
  • the planar shape of the opening 141 is not limited, and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or any other polygon, or any of these polygons with rounded corners.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • planar shape of an opening provided in an insulating layer refers to the shape of the upper end or the lower end of the insulating layer on the opening side.
  • planar shape of opening 141 refers to the shape of the upper end or the lower end of the insulating layer 110 on the opening 141 side.
  • the side surface of the opening 141 of the insulating layer 110 is preferably vertical, for example, perpendicular to the insulating layer 101. That is, the angle ⁇ 110 is preferably 80° or more and 100° or less, and more preferably 85° or more and 95° or less. This allows the transistor 100 to be a transistor of a fine size. Therefore, the area occupied by the circuit provided in the semiconductor device 10 can be reduced, and the semiconductor device 10 can be a small semiconductor device.
  • the side surface of the opening 141 of the insulating layer 110 may be tapered.
  • the angle ⁇ 110 may be less than 90° or less than 80°. In this case, the coverage of the layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved.
  • the smaller the angle ⁇ 110 the larger the length L100 can be, and the larger the angle ⁇ 110, the smaller the length L100 can be.
  • the shape of the side of the opening 141 of the insulating layer 110 is straight in cross-sectional view, but this is not a limitation of one embodiment of the present invention.
  • the shape of the side of the opening 141 of the insulating layer 110 may be curved, or the side may have both straight and curved regions.
  • the width W100 which is the channel width of the transistor 100, corresponds to the length of the semiconductor layer 108 in a direction perpendicular to the component of the length L100 along the bottom surface of the opening 141.
  • the length of the semiconductor layer 108 in a direction perpendicular to the component of the length L100 along the bottom surface of the opening 141 is referred to as the width of the semiconductor layer 108.
  • the width W100 can be taken as the width of the semiconductor layer 108.
  • the width W112a of the conductive layer 112a and the width W112b of the conductive layer 112b are greater than the width W100. This reduces the wiring resistance of the conductive layer 112a and the conductive layer 112b, and allows the semiconductor device 10 to operate at high speed. Note that the width W112a and the width W112b may be less than the width W100.
  • the width D141 of the opening 141 is equal to or greater than the width W112a and the width W112b. This makes it possible to prevent the conductive layers 112a and 112b from coming into contact with each other and causing an electrical short circuit.
  • transistor 100 Next, the detailed configuration of transistor 100 will be described.
  • the semiconductor material used for the semiconductor layer 108 is not particularly limited.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystalline semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the characteristics of the transistor 100.
  • the semiconductor layer 108 can be made of silicon.
  • silicon examples include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • polycrystalline silicon examples include low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon in the channel formation region have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • a transistor that uses silicon in the channel formation region is called a Si transistor.
  • the semiconductor layer 108 preferably contains a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties.
  • a metal oxide also called an oxide semiconductor
  • the band gap of the metal oxide used in the semiconductor layer 108 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • the insulating layer 110 preferably has one or more inorganic insulating films.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate.
  • nitrides include silicon nitride and aluminum nitride.
  • Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride.
  • Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.
  • the insulating layer 110 can be a layer through which impurities are less likely to permeate, and therefore the intrusion of impurities into the channel formation region of the transistor 100 can be suppressed. Therefore, the transistor 100 can be a transistor that exhibits good electrical characteristics and is highly reliable.
  • using silicon nitride for the insulating layer 101 can more effectively prevent impurities from entering the channel formation region of the transistor 100.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • the region of the semiconductor layer 108 in contact with the insulating layer 101 and the region in contact with the insulating layer 110 function as a channel formation region.
  • a metal oxide is used for the semiconductor layer 108, in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 101 and between the semiconductor layer 108 and the insulating layer 110, it is preferable that at least a part of the region of the insulating layer 101 in contact with the semiconductor layer 108 and at least a part of the region of the insulating layer 110 in contact with the semiconductor layer 108 contain oxygen.
  • the region of the insulating layer 101 in contact with the channel formation region of the semiconductor layer 108 and the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 contain oxygen.
  • One or more of an oxide and an oxynitride can be suitably used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.
  • At least a part of a region of the insulating layer 101 in contact with the semiconductor layer 108 preferably has a function of capturing or fixing hydrogen (also referred to as gettering). This can reduce the hydrogen concentration in the channel formation region of the semiconductor layer 108. As a result, oxygen vacancies ( VO ) and VOH in the channel formation region can be reduced, and the channel formation region can be made i-type or substantially i-type. As a result, the transistor 100 can have favorable electrical characteristics and high reliability.
  • An example of an insulating layer that has the function of capturing or fixing hydrogen is a metal oxide having an amorphous structure.
  • a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium.
  • oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen.
  • metal oxides having an amorphous structure have a high ability to capture or fix hydrogen.
  • Figures 3A and 3B are modified versions of the configurations shown in Figures 2B and 2C, respectively, and show an example in which the insulating layer 110 has a two-layer structure of insulating layer 110b and insulating layer 110c on insulating layer 110b.
  • the insulating layer 110b can have a region in contact with the side of the semiconductor layer 108 and a region in contact with the upper surface of the insulating layer 101.
  • the insulating layer 110c can have a region in contact with the side of the semiconductor layer 108, a region in contact with the lower surface of the conductive layer 112a, a region in contact with the lower surface of the conductive layer 112b, and a region in contact with the lower surface of the insulating layer 106.
  • the insulating layer 110b preferably contains oxygen.
  • the oxygen content of the insulating layer 110b is preferably higher than that of the insulating layer 110c.
  • the oxygen content per unit volume of the insulating layer 110b is preferably higher than that of the insulating layer 110c.
  • one or both of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 110b.
  • at least the region of the semiconductor layer 108 in contact with the insulating layer 110b can function as a channel formation region of the transistor 100.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • SIMS X-ray photoelectron spectroscopy
  • the amount of desorption of the above elements can be measured using thermal desorption spectroscopy (TDS), which allows the content of the above elements in, for example, two layers to be compared.
  • TDS thermal desorption spectroscopy
  • SIMS, XPS, TDS, etc. can also be used to measure the content of elements other than oxygen.
  • the transistor 100 can be a transistor that has good electrical characteristics and high reliability.
  • oxygen can be supplied to the insulating layer 110b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.
  • oxygen may be supplied to the insulating layer 110b by forming an oxide film on the upper surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. Then, the oxide film may be removed.
  • the insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the substance diffuses easily in the insulating layer 110b. It can also be said that it is preferable that the diffusion coefficient of the substance in the insulating layer 110b is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110b is large.
  • the oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110b and the semiconductor layer 108.
  • the diffusion coefficient of oxygen can be calculated using TDS.
  • SIMS may be used. Note that the diffusion coefficients of substances other than oxygen may also be calculated using TDS or SIMS in some cases.
  • the threshold voltage of the transistor shifts, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • cutoff current the drain current that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may shift to the negative side, and the cutoff current may become large.
  • the semiconductor device 10 can be a semiconductor device that achieves both low power consumption and high performance.
  • the insulating layer 110c preferably releases a small amount of impurities (e.g., hydrogen and water) from itself and is difficult for impurities to penetrate. This can prevent the impurities contained in the insulating layer 110c from diffusing into the channel formation region of the transistor 100. Therefore, the transistor 100 can be a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., hydrogen and water
  • the insulating layer 110c is preferably a film through which oxygen is less likely to permeate, for example, a film through which oxygen is less likely to permeate than the insulating layer 110b.
  • the insulating layer 110c is preferably a film having a small oxygen diffusion coefficient, for example, a film having a small oxygen diffusion coefficient than the insulating layer 110b.
  • the oxygen contained in the insulating layer 110b can be prevented from diffusing to the conductive layer 112a and the conductive layer 112b through the insulating layer 110c. This can prevent the electrical resistance of the conductive layer 112a and the conductive layer 112b from increasing.
  • the oxygen contained in the insulating layer 110b is prevented from diffusing to the insulating layer 110c side, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor 100 is increased, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.
  • This can make the channel formation region of the transistor 100 i-type or substantially i-type. Therefore, the transistor 100 can be a transistor that exhibits good electrical characteristics and has high reliability.
  • the insulating layer 110c preferably contains nitrogen, and preferably uses one or more of the above-mentioned nitrides and nitride oxides.
  • silicon nitride or silicon nitride oxide may be preferably used for the insulating layer 110c.
  • one or more of an oxide and an oxynitride may be used for the insulating layer 110c.
  • aluminum oxide may be preferably used for the insulating layer 110c.
  • the thickness of insulating layer 110b is thickness T110b_1
  • the thickness of insulating layer 110c is thickness T110c_1.
  • the thickness T110b_1 of the insulating layer 110b can be, for example, 5 nm or more and less than 3 ⁇ m, 5 nm or more and less than 2.5 ⁇ m, 5 nm or more and less than 2 ⁇ m, 5 nm or more and less than 1.5 ⁇ m, 7 nm or more and less than 1.2 ⁇ m, 7 nm or more and less than 1 ⁇ m, 7 nm or more and less than 500 nm, 7 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, or 10 nm or more and less than 30 nm.
  • the thickness T110c_1 of the insulating layer 110c can be equal to or less than the thickness T110b_1.
  • the thickness T110c_1 can be, for example, 3 nm or more and 1 ⁇ m or less, 3 nm or more and 500 nm or less, 3 nm or more and 300 nm or less, 3 nm or more and 200 nm or less, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 5 nm or more and 20 nm or less.
  • thickness T110b_1 can be the shortest distance between the surface on which insulating layer 110b is formed (here, the upper surface of insulating layer 101) and the lower surface of insulating layer 110c in a cross-sectional view.
  • thickness T110c_1 can be the shortest distance between the surface on which insulating layer 110c is formed (here, the upper surface of insulating layer 110b) and the lower surface of conductive layer 112a or conductive layer 112b in a cross-sectional view.
  • the thickness T110c_1 of the insulating layer 110c When the thickness T110c_1 of the insulating layer 110c is large, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing to the channel formation region of the transistor 100 may increase.
  • the thickness T110c_1 when the thickness T110c_1 is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a and the conductive layer 112b through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region of the transistor 100 may decrease.
  • oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. As a result, the channel formation region of the transistor 100 can be made i-type or substantially i-type.
  • the conductive layer 112a and the conductive layer 112b are oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112a and the conductive layer 112b can be prevented from increasing.
  • the transistor 100 can be a transistor that exhibits good electrical characteristics and is highly reliable.
  • FIG. 3C is an enlarged view showing the region 108na shown in FIG. 3A and the region nearby.
  • FIG. 3C shows an example in which the region 108na including the low resistance region includes not only the region of the semiconductor layer 108 that contacts the conductive layer 112a and the region nearby, but also the region 107 that contacts the insulating layer 110c and the region nearby.
  • the region 108nb can include not only the region that contacts the conductive layer 112b and the region nearby, but also the region that contacts the insulating layer 110c and the region nearby.
  • FIG. 3C shows an example in which the region 108na including the low resistance region includes not only the region of the semiconductor layer 108 that contacts the conductive layer 112a and the region nearby, but also the region 107 that contacts the insulating layer 110c and the region nearby.
  • the region 108nb can include not only the region that contacts the conductive layer 112b and the region nearby, but also the region that contacts the insulating layer 110c and the region nearby.
  • 3C shows an example in which the height of the boundary between the region 108i and the region 108na is the same or approximately the same as the height of the boundary between the insulating layer 110b and the insulating layer 110c, but these heights do not have to be the same or approximately the same.
  • the height of the boundary between region 108i and region 108nb may or may not match or approximately match the height of the boundary between insulating layer 110b and insulating layer 110c.
  • the region 107 can be made a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the source and drain regions of the transistor 100 and the channel formation region.
  • the low-resistance region can function as a buffer region for mitigating the drain electric field (the electric field generated in the drain region and its vicinity). Note that these low-resistance regions may function as the source or drain region.
  • the amount of impurities released from the insulating layer 110c is too large, the impurities may diffuse into the channel formation region of the transistor 100. Even if a material that releases impurities is used for the insulating layer 110c, it is preferable that the amount of impurities released is small.
  • the length L100 which is the channel length of the transistor 100, corresponds to the sum of twice the length of the side of the opening 141 of the insulating layer 110b in a cross-sectional view and the width D141 of the opening 141.
  • the length of the side of the opening 141 of the insulating layer 110b in a cross-sectional view can be determined by the thickness T110b_1 and the angle ⁇ 110.
  • Figures 4A and 4B are modified examples of the configurations shown in Figures 2B and 3A, respectively.
  • Figures 4A and 4B show an example in which the insulating layer 106 is processed, for example, into an island shape.
  • Figures 4A and 4B show an example in which the upper surface end of the insulating layer 106 coincides or roughly coincides with the lower surface end of the conductive layer 104.
  • the upper surface end of the insulating layer 106 can coincide or roughly coincide with the lower surface end of the conductive layer 104.
  • the upper surface end of the insulating layer 106 does not have to coincide or roughly coincide with the lower surface end of the conductive layer 104.
  • the upper surface end of the insulating layer 106 may be located outside the lower surface end of the conductive layer 104.
  • Figures 5A, 5B, and 5C are modified versions of the semiconductor device 10 shown in Figures 1A, 3A, and 3B, respectively, and show an example in which the transistor 100 has a conductive layer 103 and an insulating layer 105.
  • the transistor 100 having the conductive layer 103 and the insulating layer 105 is referred to as transistor 100A
  • the semiconductor device 10 having the transistor 100A is referred to as semiconductor device 10A.
  • a conductive layer 103 is provided on the insulating layer 101, and an insulating layer 105 is provided on the conductive layer 103 and on the insulating layer 101.
  • the insulating layer 105 has a shape that conforms to the top and side surfaces of the conductive layer 103 and the top surface of the insulating layer 101.
  • the insulating layer 105 can have a region in contact with the top surface of the conductive layer 103, a region in contact with the side surface of the conductive layer 103, and a region in contact with the top surface of the insulating layer 101.
  • An insulating layer 110 and a semiconductor layer 108 are provided on the insulating layer 105.
  • An opening 141 in the insulating layer 110 reaches the insulating layer 105.
  • the bottom surface of the semiconductor layer 108 can have a region that contacts the top surface of the insulating layer 105.
  • the insulating layer 106 can have a region that contacts the top surface of the insulating layer 105.
  • the conductive layer 103 has a region that overlaps with the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 in the region located inside the opening 141 via the insulating layer 105. This allows not only the conductive layer 104 but also the conductive layer 103 to function as a gate electrode, and not only the insulating layer 106 but also the insulating layer 105 to function as a gate insulating layer. Therefore, the transistor 100A can be said to be a dual-gate transistor in which gate electrodes are arranged on both sides of the channel formation region.
  • the conductive layer 104 can be referred to as a first gate electrode, a front gate electrode, or simply a gate electrode.
  • the conductive layer 103 can be referred to as a second gate electrode or a back gate electrode. Note that the names of the conductive layer 104 and the conductive layer 103 may be interchanged.
  • the insulating layer 106 can be referred to as a first gate insulating layer, and the insulating layer 105 can be referred to as a second gate insulating layer. Note that the insulating layer 105 may be referred to as a first gate insulating layer, and the insulating layer 106 may be referred to as a second gate insulating layer.
  • the transistor 100 Since the transistor 100 has the conductive layer 103, the potential on the back channel side of the semiconductor layer 108 can be fixed, and a shift in the threshold voltage can be suppressed.
  • the cutoff current may become large.
  • a transistor with a small cutoff current By suppressing the shift in the threshold voltage of the transistor 100 in the negative direction, a transistor with a small cutoff current can be obtained. Note that a small cutoff current may be referred to as a normally-off transistor.
  • FIG. 5B shows an example in which the insulating layer 110b is planarized
  • the insulating layer 110b does not have to be planarized.
  • the insulating layer 110c may or may not be planarized.
  • Figures 6A and 6B are modified examples of the configurations shown in Figures 3A and 3B, respectively, and show an example in which insulating layers 147 and 149 are provided.
  • Figure 6A shows an example in which insulating layers 147 and 149 are provided between insulating layer 110 and semiconductor layer 108, between conductive layer 112a and semiconductor layer 108, and between conductive layer 112b and semiconductor layer 108.
  • Figure 6B shows an example in which insulating layer 147 and insulating layer 149 are provided between insulating layer 110 and insulating layer 106.
  • the insulating layer 147 can have a region in contact with the side of the insulating layer 110, a region in contact with the side of the conductive layer 112a, a region in contact with the side of the conductive layer 112b, a region in contact with the top surface of the insulating layer 101, a region in contact with the side of the semiconductor layer 108, and a region in contact with the insulating layer 106.
  • a protrusion is formed at a portion of the insulating layer 147 that contacts the top surface of the insulating layer 101. At the end of the protrusion, the insulating layer 147 can contact the semiconductor layer 108.
  • the protrusion of the insulating layer 147 protrudes toward the center of the opening 141 more than other portions.
  • the insulating layer 147 preferably has a barrier property against hydrogen, and in particular, preferably has a high ability to suppress the diffusion of hydrogen.
  • a barrier property against hydrogen for example, one or more of aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide can be used as the insulating layer 147.
  • silicon nitride can be preferably used as the insulating layer 147.
  • the insulating layer 149 can be provided on the insulating layer 147.
  • the insulating layer 149 can have a region in contact with the side of the insulating layer 147, a region in contact with the upper surface of the protruding portion of the insulating layer 147, a region in contact with the semiconductor layer 108, and a region in contact with the insulating layer 106.
  • the side of the insulating layer 149 may be flush with the side end of the protruding portion of the insulating layer 147.
  • the insulating layer 149 preferably has a barrier property against hydrogen, and in particular, preferably has a high ability to capture or fix hydrogen.
  • a barrier property against hydrogen for example, one or more of an oxide containing magnesium or an oxide containing one or both of aluminum and hafnium can be used as the insulating layer 149.
  • these oxides have an amorphous structure.
  • oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. Note that these oxides preferably have an amorphous structure, but a crystalline region may be formed in a part of the oxide.
  • examples of materials having a high ability to suppress the diffusion of hydrogen include silicon nitride and silicon nitride oxide.
  • hafnium oxide can be suitably used as the insulating layer 149.
  • hydrogen contained in the insulating layer 110 can be captured or fixed by the insulating layer 149.
  • the transistor 100 can be a transistor that exhibits good electrical characteristics and is highly reliable.
  • the insulating layer 101, the insulating layer 110, the conductive layer 112a, and the conductive layer 112b are formed on the substrate 102, and the opening 141 is formed in the insulating layer 110.
  • the insulating layer 147 and the insulating layer 149 are sequentially formed to cover the opening 141.
  • the insulating layer 149 and the insulating layer 147 are processed to form the insulating layer 149 and the insulating layer 147.
  • the insulating layer 149 and the insulating layer 147 can be formed by etching the upper surfaces of the insulating layer 149 and the insulating layer 147 in a substantially uniform manner. Such uniform etching and planarization are also called anisotropic etching.
  • the insulating layer 149 and the insulating layer 147 may be formed by using a photolithography method.
  • the semiconductor layer 108, the insulating layer 106, the conductive layer 104, and the insulating layer 109 are formed in this order. In this manner, the semiconductor device shown in Figures 6A and 6B can be manufactured.
  • FIG. 7A and 7B are modified examples of the semiconductor device 10 shown in FIG. 2A and FIG. 3A, respectively, and show an example in which the conductive layer 112b is provided between the insulating layer 101 and the insulating layer 110. That is, FIG. 7A and FIG. 7B show an example in which the conductive layer 112b is provided under the insulating layer 110.
  • the semiconductor device 10 shown in FIG. 7A is the semiconductor device 10B
  • the transistor 100 shown in FIG. 7B is the transistor 100B.
  • the opening 141 has a region that reaches the conductive layer 112b.
  • the semiconductor device 10B may have the conductive layer 112a provided under the insulating layer 110 and the conductive layer 112b provided on the insulating layer 110.
  • the following description of the semiconductor device 10B and the transistor 100B can be referred to by appropriately reading the conductive layer 112b as the conductive layer 112a and the region 108nb as the region 108na.
  • the boundary between region 108i and region 108nb is located at a position lower than the upper surface of insulating layer 110b.
  • FIG. 7B shows an example in which the height of the boundary between region 108i and region 108nb is lower than the height of the boundary between insulating layer 110b and insulating layer 110c.
  • the vertical channel length can be set to 1 or approximately 1 times the length of the side of the opening 141.
  • the horizontal channel length can be shorter than the width D141 of the opening 141.
  • the transistor 100B can have a shorter channel length than the transistor 100 shown in FIG. 3A, for example.
  • FIGS. 7A and 7B show an example in which the bottom end portion of the semiconductor layer 108 that overlaps with the conductive layer 112b is provided on the insulating layer 110, the bottom end portion may be in contact with the conductive layer 112b. In this case, the region 108nb may not be in contact with the insulating layer 110.
  • Figures 8A and 8B are modified examples of the semiconductor device 10B shown in Figures 7A and 7B, respectively, and show an example in which not only the conductive layer 112b but also the conductive layer 112a is provided between the insulating layer 101 and the insulating layer 110. That is, Figures 8A and 8B show an example in which not only the conductive layer 112b but also the conductive layer 112a is provided under the insulating layer 110.
  • the semiconductor device 10 shown in Figure 8A is referred to as semiconductor device 10C
  • the transistor 100 shown in Figure 8B is referred to as transistor 100C.
  • the opening 141 has a region that reaches the conductive layer 112a and a region that reaches the conductive layer 112b.
  • the transistor 100C does not have a vertical channel length, that is, the vertical channel length can be set to 0.
  • the horizontal channel length can be shorter than that of the transistor 100B.
  • the transistor 100C can have a shorter channel length than that of the transistor 100B. Note that in FIG. 8A and FIG. 8B, an example is shown in which the bottom end portion of the semiconductor layer 108 overlapping with the conductive layer 112a and the bottom end portion overlapping with the conductive layer 112b are provided on the insulating layer 110, but the bottom end portion overlapping with the conductive layer 112a may contact the conductive layer 112a, and the bottom end portion overlapping with the conductive layer 112b may contact the conductive layer 112b. In this case, the region 108na and the region 108nb may not contact the insulating layer 110.
  • Figure 9A shows a modified example of the configuration shown in Figure 2A, in which the width W100 of the semiconductor layer 108 is greater than the width W112a of the conductive layer 112a and the width W112b of the conductive layer 112b. Note that, although Figure 9A shows an example in which the width W100 is smaller than the width D141, the width W100 may be greater than or equal to the width D141.
  • the width W100 By increasing the width W100, the on-current of the transistor 100 in the semiconductor device 10 can be increased. On the other hand, by decreasing the width W100, the transistor 100 can be made into a transistor of a fine size.
  • Figure 9B shows a modified example of the configuration shown in Figure 2A, in which two semiconductor layers 108 are provided in one opening 141.
  • FIG. 9B shows an example in which the semiconductor layer 108[1] and the semiconductor layer 108[2] have regions in contact with the same conductive layer 112a and the same conductive layer 112b, respectively. Note that three or more semiconductor layers 108 may be provided in one opening 141.
  • the area per semiconductor layer 108 can be made smaller than when only one semiconductor layer 108 is provided in one opening 141.
  • oxygen may be easily supplied to the semiconductor layer 108 in the manufacturing process of the semiconductor device 10. Therefore, oxygen vacancies (V O ) and V O H in the channel formation region may be reduced.
  • the transistor 100 included in the semiconductor device 10 may be a transistor that exhibits good electrical characteristics and is highly reliable.
  • the transistor 100 included in the semiconductor device 10 can be miniaturized and the channel width can be increased compared to when a plurality of semiconductor layers 108 are provided in one opening 141.
  • Figures 10A and 10B are modified examples of the configuration shown in Figure 2A, and the planar shape of the opening 141 is different from that of the semiconductor device 10 shown in Figure 2A.
  • Figure 10A shows an example in which the planar shape of the opening 141 is rectangular
  • Figure 10B shows an example in which the planar shape of the opening 141 is rectangular with rounded corners.
  • the processing accuracy when forming the opening 141 can be improved.
  • the side of the opening 141 has a flat or approximately flat area, so that the coverage of the layers provided inside the opening 141, such as the semiconductor layer 108, the insulating layer 106, and the conductive layer 104, may be improved.
  • the corners are made angular, so that the transistor 100 of the semiconductor device 10 can be miniaturized and the area of the opening 141 in a planar view can be increased compared to when the corners are rounded.
  • the corners of the opening 141 are rounded, the coverage of the layers provided inside the opening 141 with respect to the corners of the opening 141 can be improved compared to when the corners of the opening 141 are made angular.
  • Figures 11A and 11B are modified examples of the configurations shown in Figures 10A and 10B, respectively, and show an example in which two semiconductor layers 108 are provided in one opening 141, similar to the configuration shown in Figure 9B. Note that, as described above, three or more semiconductor layers 108 may be provided in one opening 141.
  • FIG. 12A and 12B are modified examples of the configuration shown in FIG. 11A and FIG. 11B, respectively, and show an example in which the opening 141 in which the semiconductor layer 108[1] is provided is different from the opening 141 in which the semiconductor layer 108[2] is provided.
  • the opening 141 in which the semiconductor layer 108[1] is provided is described as opening 141[1]
  • the opening 141 in which the semiconductor layer 108[2] is provided is described as opening 141[2], to distinguish between the two openings 141.
  • the same description is used in the subsequent drawings. Note that when three or more semiconductor layers 108 having regions in contact with the same conductive layer 112a and the same conductive layer 112b are provided, three or more openings 141 can also be provided.
  • oxygen can be more easily supplied from the insulating layer 110 to the semiconductor layer 108 than in the example shown in FIGS. 11A and 11B.
  • the total area occupied by the openings 141 provided in one transistor 100 can be made smaller than in the example shown in FIGS. 12A and 12B, so that the transistor 100 can be made into a fine-sized transistor.
  • FIG. 13A is a modified example of the configuration shown in FIG. 1A.
  • FIG. 13B is a plan view in which the conductive layer 104 is omitted from FIG. 13A.
  • FIG. 13C is a cross-sectional view of the cut surface taken along dashed line A1-A2 shown in FIG. 13A.
  • FIGS. 13A to 13C show an example in which one transistor 100 is provided across the inside of opening 141[1] and the inside of opening 141[2], and a conductive layer 112c is provided between opening 141[1] and opening 141[2] in a plan view.
  • the conductive layer 112a and the conductive layer 112c are provided so as to face each other across opening 141[1] in a plan view.
  • the conductive layer 112b and the conductive layer 112c are provided so as to face each other across opening 141[2] in a plan view.
  • a transistor 100 in which one semiconductor layer 108 is provided across multiple openings 141 and a conductive layer is provided between the multiple openings 141 in a plan view is referred to as transistor 100D
  • a semiconductor device 10 having transistor 100D is referred to as semiconductor device 10D.
  • one transistor 100 has three conductive layers 112. Note that one transistor 100 may be provided across three or more openings 141. In this case, one transistor 100 may have four or more conductive layers 112.
  • the vertical channel length of the transistor 100 can be made longer and the saturation of the transistor 100 can be made higher than when one transistor 100 is provided within one opening 141.
  • the transistor 100 can be made smaller in size than when one transistor 100 is provided across multiple openings 141.
  • FIGS. 14A, 14B, and 14C are modified examples of the configurations shown in FIGS. 13A, 13B, and 13C, respectively, and show an example in which the semiconductor layer 108 having a region located inside the opening 141[1] is different from the semiconductor layer 108 having a region located inside the opening 141[2].
  • the semiconductor layer 108 having a region located inside the opening 141[1] is described as the semiconductor layer 108[1].
  • the semiconductor layer 108 having a region located inside the opening 141[2] is described as the semiconductor layer 108[2]. Note that when one transistor 100 is provided across three or more openings 141, for example, a different semiconductor layer 108 can be provided for each opening 141.
  • a transistor 100 that is provided across multiple openings 141, a different semiconductor layer 108 is provided for each of the multiple openings 141, and a conductive layer is provided between the multiple openings 141 in a plan view is referred to as a transistor 100E
  • a semiconductor device 10 that has a transistor 100E is referred to as a semiconductor device 10E.
  • the area per semiconductor layer 108 can be made smaller than that of the transistor 100D.
  • the semiconductor device 10E may be able to supply oxygen to the semiconductor layer 108 more easily than the semiconductor device 10D in a manufacturing process of the semiconductor device.
  • oxygen vacancies ( VO ) and VOH in the channel formation region may be reduced.
  • the transistor 100E may be able to have better electrical characteristics and higher reliability than the transistor 100D.
  • the transistor 100D can be made a fine-sized transistor because the distance between the openings 141 can be made shorter than that of the transistor 100E.
  • Figures 15A, 15B, and 15C are modifications of the configurations shown in Figures 13A, 13B, and 13C, respectively, and show an example in which the transistor 100 has a conductive layer 103 and an insulating layer 105.
  • Figures 15A, 15B, and 15C can be said to be configurations that combine the configurations shown in Figures 5A, 5B, and 5C with the configurations shown in Figures 13A, 13B, and 13C.
  • Such a transistor 100 is referred to as transistor 100F.
  • a semiconductor device 10 having transistor 100F is referred to as semiconductor device 10F.
  • Transistor 100F can suppress the shift in threshold voltage while achieving higher saturation than transistor 100A.
  • transistor 100A can be made smaller than transistor 100F.
  • Figures 16A, 16B, and 16C are modified versions of the configurations shown in Figures 15A, 15B, and 15C, respectively, and show an example in which a semiconductor layer 108[1] is provided so as to have a region located inside the opening 141[1], and a semiconductor layer 108[2] is provided so as to have a region located inside the opening 141[2].
  • Figures 16A, 16B, and 16C can be said to be configurations that combine the configurations shown in Figures 14A, 14B, and 14C with the configurations shown in Figures 15A, 15B, and 15C.
  • Such a transistor 100 is referred to as transistor 100G.
  • a semiconductor device 10 having transistor 100G is referred to as semiconductor device 10G.
  • Transistor 100G may have better electrical characteristics and be more reliable than transistor 100F.
  • transistor 100F can be made smaller in size because the distance between openings 141 can be made shorter than that of transistor 100G.
  • Fig. 17A is a plan view showing a configuration example of a semiconductor device 20 according to one embodiment of the present invention.
  • Fig. 17B is a cross-sectional view taken along dashed line A3-A4 in Fig. 17A.
  • Fig. 17C is a cross-sectional view taken along dashed line B3-B4 in Fig. 17A.
  • the semiconductor device 20 includes the transistor 100 shown in Figures 1A, 1C, and 1D, as well as a transistor 200 that has a different configuration from the transistor 100.
  • the transistor 200 is provided on the insulating layer 101.
  • the transistor 200 has a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, and a semiconductor layer 208.
  • the conductive layer 204 functions as a gate electrode
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 212a functions as one of the source electrode and the drain electrode
  • the conductive layer 212b functions as the other of the source electrode and the drain electrode.
  • Each layer constituting the transistor 200 may have a single-layer structure or a stacked structure.
  • the conductive layer 212a is provided on the insulating layer 101.
  • the insulating layer 110 is provided on the conductive layer 212a.
  • the insulating layer 110 is provided so as to cover the upper surface and side surfaces of the conductive layer 212a.
  • the insulating layer 110 has an opening 241 that reaches the conductive layer 212a.
  • the transistor 200 is provided so as to have a region located inside the opening 241. Note that although an example in which the insulating layer 110 is planarized is shown in FIG. 17B and FIG. 17C, the insulating layer 110 does not have to be planarized.
  • the conductive layer 212b is provided on the insulating layer 110.
  • the conductive layer 212b has an opening 243 having an area overlapping with the opening 241.
  • the planar shapes of the opening 241 and the opening 243 can be the same as the planar shape that the opening 141 can have.
  • the planar shapes of the opening 241 and the opening 243 can be made to match or approximately match each other.
  • the lower surface of the conductive layer 212b refers to the surface on the insulating layer 110 side.
  • the upper surface of the insulating layer 110 refers to the surface on the conductive layer 212b side.
  • openings 241 and 243 do not have to be the same. When the planar shapes of openings 241 and 243 are circular, openings 241 and 243 may or may not be concentric.
  • the conductive layer 212b can be formed using the same material as the conductive layer 112a and the conductive layer 112b.
  • the conductive layer 212b can be formed in the same process as the conductive layer 112a and the conductive layer 112b. For example, a conductive film that will become the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b is formed, and the conductive film is processed to form the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b.
  • the semiconductor layer 208 has a region located inside the opening 241 and a region located inside the opening 243.
  • the semiconductor layer 208 can be provided along the bottom and side surfaces of the opening 241 and the side surfaces of the opening 243.
  • the semiconductor layer 208 can have, for example, a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surface of the conductive layer 212b, and a region in contact with the top surface of the conductive layer 212b.
  • the semiconductor layer 208 can have a region in contact with the side surface of the insulating layer 110.
  • the region of the semiconductor layer 208 in contact with the conductive layer 212a functions as one of the source region and the drain region, and the region in contact with the conductive layer 212b functions as the other.
  • a channel formation region is provided between the source region and the drain region.
  • the semiconductor layer 208 can be formed using the same material as the semiconductor layer 108.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108.
  • the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming a semiconductor film that will become the semiconductor layer 108 and the semiconductor layer 208, and processing the semiconductor film.
  • the insulating layer 106 is provided to have a region located inside the opening 241 and a region located inside the opening 243, specifically, the insulating layer 106 is provided to cover the opening 241 and the opening 243.
  • the insulating layer 106 is provided on the semiconductor layer 208 and the conductive layer 212b.
  • the insulating layer 106 has a shape that follows the top surface and side surface of the semiconductor layer 208 and the top surface and side surface of the conductive layer 212b.
  • the insulating layer 106 can have a region in contact with the top surface of the semiconductor layer 208, a region in contact with the side surface of the semiconductor layer 208, a region in contact with the top surface of the conductive layer 212b, and a region in contact with the side surface of the conductive layer 212b.
  • the conductive layer 204 is provided on the insulating layer 106 so as to have a region located inside the opening 241 and a region located inside the opening 243.
  • the conductive layer 204 is provided inside the opening 241 so as to have a region facing the semiconductor layer 208 with the insulating layer 106 sandwiched between them.
  • the conductive layer 204 has a shape that follows the insulating layer 106, and specifically, can have a shape that follows the top surface of the insulating layer 106 and the side surfaces of the insulating layer 106 inside the openings 241 and 243.
  • the conductive layer 204 can also have a region that contacts the top surface of the insulating layer 106 and a region that contacts the side surfaces of the insulating layer 106 inside the openings 241 and 243.
  • the conductive layer 204 can be formed using the same material as the conductive layer 104.
  • the conductive layer 204 can be formed in the same process as the conductive layer 104. For example, a conductive film that will become the conductive layer 104 and the conductive layer 204 is formed, and the conductive film is processed to form the conductive layer 104 and the conductive layer 204.
  • An insulating layer 109 is provided to cover the transistor 200.
  • the insulating layer 109 is provided on the conductive layer 204.
  • the insulating layer 109 functions as a protective layer for the transistor 200.
  • the transistor 200 is a so-called top-gate type transistor having a gate electrode above the semiconductor layer 208. Furthermore, since the bottom surface of the semiconductor layer 208 is in contact with the conductive layer 212a and the conductive layer 212b that function as a source electrode and a drain electrode, the transistor 200 can be called a TGBC (Top Gate Bottom Contact) type transistor.
  • the source electrode and the drain electrode of the transistor 200 are located at different heights with respect to the surface of the insulating layer 101, which is the surface on which the transistor 200 is formed, and the drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the insulating layer 101. It can also be said that the drain current flows in the vertical direction or approximately vertical direction in the transistor 200. Therefore, the transistor 200 can be called a vertical channel type transistor or a VFET (Vertical Field Effect Transistor).
  • the channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, a transistor having a channel length smaller than the limit resolution of the exposure device used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic variation between multiple transistors 200 is also reduced. Therefore, the operation of a semiconductor device including the transistor 200 can be stabilized and the reliability can be improved. Furthermore, the reduction in characteristic variation increases the degree of freedom in circuit design and allows the operating voltage of the semiconductor device to be reduced. Therefore, the power consumption of the semiconductor device can be reduced.
  • the transistor 200 can have a source electrode, a layer having a channel formation region, and a drain electrode stacked on top of each other, the area occupied can be significantly reduced compared to a so-called planar type transistor in which the layer having the channel formation region is arranged in a planar shape.
  • the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each function as wiring, and the transistor 200 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 200 and wiring, the area occupied by the transistor 200 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • the transistor 200 with a short channel length and the transistor 100 with a long channel length can be formed on the insulating layer 101 by sharing some of the steps.
  • a high-performance semiconductor device can be obtained by applying the transistor 200 to a transistor that requires a large on-state current and the transistor 100 to a transistor that requires high saturation.
  • the semiconductor device of one embodiment of the present invention has an excellent effect of being able to freely design transistors with different channel lengths on the same substrate by changing the thickness of the insulating layer and pattern formation.
  • width of the opening 241 is width D241. Also, in FIG. 17A, width D241 is indicated by a double-headed arrow. The same notation is used in the subsequent drawings.
  • the width D241 is preferably small, for example, equal to or smaller than the width D141 of the opening 141 in which the transistor 100, which has a channel length that is preferably large, is provided. This allows the transistor 200 to be a transistor of minute size. Furthermore, since the channel length of the transistor 100 depends on the width D141, by making the width D141 larger than the width D241, the channel length of the transistor 100 can be ensured while the transistor 200 is made into a transistor of minute size.
  • the conductive layer 212a which functions as one of the source and drain electrodes of the transistor 200, and the conductive layer 212b, which functions as the other of the source and drain electrodes of the transistor 200, are provided on different surfaces. Specifically, the conductive layer 212a is provided on the insulating layer 101, the conductive layer 212b is provided on the insulating layer 110, and the insulating layer 110 is sandwiched between the conductive layer 212a and the conductive layer 212b.
  • the conductive layer 112a which functions as one of the source and drain electrodes of the transistor 100, and the conductive layer 112b, which functions as the other of the source and drain electrodes of the transistor 100, are provided on the same surface.
  • the conductive layer 112a and the conductive layer 112b are provided on the insulating layer 110. It can also be said that one of the source electrode or drain electrode of transistor 200 is provided on a different surface from the source electrode and drain electrode of transistor 100, and the other of the source electrode or drain electrode of transistor 200 is provided on the same surface as the source electrode and drain electrode of transistor 100.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • Figures 18A and 18B are enlarged views of the transistor 200 shown in Figures 17A and 17B, respectively.
  • the channel length, channel width, etc. of the transistor 200 will be explained using Figures 18A and 18B.
  • the channel length of the transistor 200 is length L200
  • the channel width is width W200
  • the thickness of the insulating layer 110 is thickness T110_2
  • the angle between the side surface of the insulating layer 110 at the opening 241 and the upper surface of the insulating layer 101 is angle ⁇ 110.
  • the length L200, width W200, and thickness T110_2 are indicated by double-headed arrows. The same notation is used in the subsequent drawings.
  • the thickness T110_2 can be the shortest distance between the formation surface of the conductive layer 212a (here, the upper surface of the conductive layer 212a) and the lower surface of the conductive layer 212b in a cross-sectional view, as shown in FIG. 18B.
  • regions 208i, 208na, and 208nb are shown as regions of the semiconductor layer 208. Region 208i is provided between regions 208na and 208nb.
  • At least a part of the region 208i functions as a channel formation region of the transistor 200.
  • the region 208na is a region in contact with the conductive layer 212a of the semiconductor layer 208 and a region in the vicinity thereof. At least a part of the region 208na functions as one of the source region and the drain region of the transistor 200.
  • the region 208nb is a region in contact with the conductive layer 212b of the semiconductor layer 208 and a region in the vicinity thereof. At least a part of the region 208nb functions as the other of the source region and the drain region of the transistor 200.
  • At least a part of the region 208na and the region 208nb can be regions having lower electrical resistance than at least a part of the region 208i (hereinafter, also referred to as low resistance regions).
  • at least a part of the region 208na and the region 208nb can be regions having a higher carrier concentration or a higher oxygen defect density than at least a part of the region 208i.
  • FIG. 18B shows an example in which the height of the boundary between region 208i and region 208nb coincides with or approximately coincides with the height of the boundary between insulating layer 110 and conductive layer 212b, but these heights do not have to coincide or approximately coincide.
  • the length L200 which is the channel length of the transistor 200, corresponds to the length of the side of the opening 241 of the insulating layer 110 in a cross-sectional view.
  • the length L200 is determined by the thickness T110_2 of the insulating layer 110 and the angle ⁇ 110 between the side of the opening 241 of the insulating layer 110 and the surface on which the insulating layer 110 is to be formed (here, the upper surface of the conductive layer 212a). Therefore, the length L200 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely small channel length that could not be realized with a conventional exposure device for mass production of flat panel displays for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m
  • a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the length L200 can be, for example, 0.1 nm or more but less than 3 ⁇ m, 0.1 nm or more but less than 2.5 ⁇ m, 1 nm or more but less than 2 ⁇ m, 1 nm or more but less than 1.5 ⁇ m, 5 nm or more but less than 1.2 ⁇ m, 5 nm or more but less than 1 ⁇ m, 7 nm or more but less than 500 nm, 7 nm or more but less than 300 nm, 10 nm or more but less than 200 nm, 10 nm or more but less than 100 nm, or 10 nm or more but less than 50 nm.
  • the on-state current of the transistor 200 can be increased.
  • the transistor 200 By using the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the length L200 can be controlled by adjusting the thickness T110_2 and angle ⁇ 110 of the insulating layer 110.
  • the side surface of the opening 241 in the insulating layer 110 is preferably vertical like the side surface of the opening 141, and is preferably perpendicular to the insulating layer 101, for example.
  • the side surface of the opening 241 in the insulating layer 110 may be tapered.
  • the shape of the side surface of the opening 241 in the insulating layer 110 may be straight or curved like the shape of the side surface of the opening 141, and may have both straight and curved areas.
  • the conductive layer 212b is not provided inside the opening 241. Specifically, it is preferable that the conductive layer 212b does not have a region that contacts the side of the insulating layer 110 at the opening 241. If the conductive layer 212b is also provided inside the opening 241, the length L200 of the transistor 200 becomes shorter than the length of the side of the insulating layer 110, and control of the length L200 may become difficult. Therefore, it is preferable that the planar shape of the opening 243 matches the planar shape of the opening 241, or that the opening 243 encompasses the opening 241 when viewed from above.
  • Figure 18A shows an example in which the planar shape of opening 241 is circular.
  • width D241 corresponds to the diameter of the circle
  • width W200 which is the channel width of transistor 200, is the length of the circumference of the circle.
  • width W200 is ⁇ x D141.
  • the width D241 of the opening 241 may vary in the depth direction.
  • the average value of the diameter at the highest point of the insulating layer 110 in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters may be used as the width D241 of the opening 241.
  • any of the diameters at the highest point of the insulating layer 110 in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these two diameters may be used as the diameter of the opening 241.
  • the width D241 of the opening 241 is equal to or greater than the limit resolution of the exposure device.
  • the width D241 can be, for example, 200 nm or more and less than 5 ⁇ m, 200 nm or more and less than 4.5 ⁇ m, 300 nm or more and less than 4 ⁇ m, 300 nm or more and less than 3.5 ⁇ m, 400 nm or more and less than 3 ⁇ m, 400 nm or more and less than 2.5 ⁇ m, 500 nm or more and less than 2 ⁇ m, 500 nm or more and less than 1.5 ⁇ m, or 500 nm or more and less than 1 ⁇ m.
  • a step may be formed between the insulating layer 110 and the conductive layer 212a, and the semiconductor layer 208, the insulating layer 106, and the conductive layer 204 may be provided along the step.
  • Figure 19A shows a modified example of the configuration shown in Figure 17B, in which the insulating layer 110 has a three-layer laminate structure of insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b.
  • the planar configuration see Figure 17A.
  • the insulating layer 110a can have a region in contact with the side of the semiconductor layer 108, a region in contact with the side of the semiconductor layer 208, a region in contact with the upper surface of the conductive layer 212a, a region in contact with the side of the conductive layer 212a, and a region in contact with the upper surface of the insulating layer 101.
  • the insulating layer 110b can have a region in contact with the side of the semiconductor layer 108, and a region in contact with the side of the semiconductor layer 208.
  • the insulating layer 110c can have a region in contact with the side of the semiconductor layer 108, a region in contact with the side of the semiconductor layer 208, a region in contact with the lower surface of the conductive layer 112a, a region in contact with the lower surface of the conductive layer 112b, a region in contact with the lower surface of the conductive layer 212b, and a region in contact with the lower surface of the insulating layer 106.
  • FIG. 19A shows an example in which insulating layer 110a is not planarized and insulating layer 110b is planarized, but insulating layer 110a may be planarized and insulating layer 110b may not be planarized. When insulating layer 110b is not planarized, insulating layer 110c may be planarized or may not be planarized.
  • the insulating layer 110a can be made of a material that can be used for the insulating layer 110c, and can have the same function as the insulating layer 110c.
  • the insulating layer 110a preferably has a lower oxygen content than the insulating layer 110b.
  • the insulating layer 110b preferably has a higher oxygen content than the insulating layer 110a.
  • the insulating layer 110b preferably has a higher oxygen content than the insulating layer 110a and the insulating layer 110c.
  • the oxygen content per unit volume of the insulating layer 110b is preferably higher than the oxygen content per unit volume of the insulating layer 110a and the oxygen content per unit volume of the insulating layer 110c.
  • the insulating layer 110a and the insulating layer 110c are preferably made of a film that is less permeable to oxygen, for example, a film that is less permeable to oxygen than the insulating layer 110b.
  • the insulating layer 110a and the insulating layer 110c are preferably made of a film that has a small oxygen diffusion coefficient, for example, a film that has a smaller oxygen diffusion coefficient than the insulating layer 110b. As described above, it is possible to suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 212a through the insulating layer 110a and diffusing to the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b through the insulating layer 110c.
  • the transistor 200 can have favorable electrical characteristics and be highly reliable.
  • FIG. 19B is an enlarged view showing the semiconductor layer 208 shown in FIG. 19A and the region nearby.
  • FIG. 19B shows an example in which the region 208na including the low resistance region includes not only the region of the semiconductor layer 208 that contacts the conductive layer 212a and the region nearby, but also the region 107a that contacts the insulating layer 110a and the region nearby.
  • FIG. 19B also shows an example in which the region 208nb including the low resistance region includes not only the region of the semiconductor layer 208 that contacts the conductive layer 212b and the region nearby, but also the region 107b that contacts the insulating layer 110c and the region nearby.
  • FIG. 19B shows an example in which the region 208na including the low resistance region includes not only the region of the semiconductor layer 208 that contacts the conductive layer 212b and the region nearby, but also the region 107b that contacts the insulating layer 110c and the region nearby.
  • 19B shows an example in which the height of the boundary between the region 208i and the region 208nb is the same or approximately the same as the height of the boundary between the insulating layer 110b and the insulating layer 110c, but these heights do not have to be the same or approximately the same.
  • the region 107a can be a low-resistance region.
  • the region 107b can be a low-resistance region.
  • the semiconductor layer 208 can be configured to have a low-resistance region between the source and drain regions of the transistor 100 and the channel formation region. As described above, the low-resistance region can function as a buffer region for relaxing the drain electric field. Note that these low-resistance regions may function as the source or drain region.
  • a high electric field is unlikely to occur near the drain region. This can suppress the generation of hot carriers and the deterioration of the transistor.
  • the conductive layer 212a functions as a drain electrode and the conductive layer 212b functions as a source electrode, a high electric field is unlikely to occur near the drain region by making the region of the semiconductor layer 208 in contact with the insulating layer 110a a low-resistance region.
  • the conductive layer 212a functions as a source electrode and the conductive layer 212b functions as a drain electrode, a high electric field is unlikely to occur near the drain region by making the region of the semiconductor layer 208 in contact with the insulating layer 110c a low-resistance region.
  • the amount of impurities released from the insulating layer 110a is too large, the impurities may diffuse into the channel formation region. Even when materials that release impurities are used for the insulating layers 110a and 110c, it is preferable that the amount of released impurities is small.
  • the thickness of insulating layer 110a is thickness T110a
  • the thickness of insulating layer 110b is thickness T110b_2
  • the thickness of insulating layer 110c is thickness T110c_2.
  • the thickness T110a of the insulating layer 110a can be, for example, 0.5 nm or more and less than 1 ⁇ m, 0.5 nm or more and less than 500 nm, 0.5 nm or more and less than 400 nm, 1 nm or more and less than 300 nm, 1 nm or more and less than 200 nm, 1 nm or more and less than 150 nm, 2 nm or more and less than 100 nm, 2 nm or more and less than 50 nm, 2 nm or more and less than 30 nm, 3 nm or more and less than 20 nm, 3 nm or more and less than 15 nm, or 3 nm or more and less than 10 nm.
  • the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 212a) and the lower surface of the insulating layer 110b in a cross-sectional view.
  • the thickness T110a of the insulating layer 110a When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 212a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 212a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 212a can be prevented from increasing. This allows the transistor 200 to have good electrical characteristics and high reliability.
  • the length L200 which is the channel length of the transistor 200, corresponds to the length of the side of the opening 241 of the insulating layer 110b in a cross-sectional view. That is, in the example shown in FIG. 19B, the length L200 can be determined by the thickness T110b_2 and the angle ⁇ 110.
  • Figures 20A and 20B are modified examples of the semiconductor device 20 shown in Figures 17A and 19A, respectively, and show an example in which a transistor 100A having a conductive layer 103 and an insulating layer 105 is provided as the transistor 100.
  • the semiconductor device 20 having the transistor 100A is referred to as the semiconductor device 20A.
  • Figure 20B shows an example in which a conductive layer 212a is provided on the insulating layer 105.
  • the conductive layer 212a is provided between the insulating layer 101 and the insulating layer 105.
  • the opening 241 is provided not only in the insulating layer 110 but also in the insulating layer 105.
  • the conductive layer 212a can be formed using the same material as the conductive layer 103 and in the same process.
  • the conductive layer 103 and the conductive layer 212a can be formed by forming a conductive film that will become the conductive layer 103 and the conductive layer 212a, and processing the conductive film.
  • Figures 21A and 21B are modified examples of the semiconductor device 20 shown in Figures 17A and 19A, respectively, and show an example in which the gate electrode of the transistor 100 is electrically connected to the other of the source electrode or drain electrode of the transistor 200.
  • Figures 21A and 21B show an example in which the gate electrode of the transistor 100 and the other of the source electrode or drain electrode of the transistor 200 are both formed as the conductive layer 104.
  • Figures 21A and 21B show an example in which the transistor 200 does not have the conductive layer 212b.
  • the semiconductor device 20 shown in Figures 21A and 21B is referred to as semiconductor device 20B.
  • the insulating layer 110 and the insulating layer 106 have an opening 245 that reaches the conductive layer 212a.
  • the transistor 200 is provided so as to have a region located inside the opening 245.
  • the conductive layer 104 has an opening 247 having an area overlapping with the opening 245.
  • the planar shape of the opening 245 can be the same as the planar shape that the opening 241 can have, and the planar shape of the opening 247 can be the same as the planar shape that the opening 243 can have.
  • the planar shapes of the openings 245 and 247 can be made to match or roughly match each other. In this case, it is preferable that the lower surface end of the conductive layer 104 on the opening 247 side match or roughly match the upper surface end of the insulating layer 106 on the opening 245 side.
  • openings 245 and 247 do not have to be the same. Furthermore, when the planar shapes of openings 245 and 247 are circular, openings 245 and 247 may or may not be concentric.
  • the semiconductor layer 208 has a region located inside the opening 245 and a region located inside the opening 247.
  • the semiconductor layer 208 can be provided along the bottom and side surfaces of the opening 245 and the side surfaces of the opening 247.
  • the semiconductor layer 208 can have, for example, a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surface of the conductive layer 104, and a region in contact with the top surface of the conductive layer 104.
  • the semiconductor layer 208 can have a region in contact with the side surface of the insulating layer 110 and a region in contact with the side surface of the insulating layer 106.
  • An insulating layer 206 that functions as a gate insulating layer of the transistor 200 is provided on the semiconductor layer 208.
  • the insulating layer 206 is provided to have a region located inside the opening 245 and a region located inside the opening 247, specifically, to cover the opening 245 and the opening 247.
  • the insulating layer 206 is provided on the semiconductor layer 208, the conductive layer 104, and the insulating layer 106.
  • the insulating layer 206 has a shape along the top and side surfaces of the semiconductor layer 208, the top and side surfaces of the conductive layer 104, and the insulating layer 106.
  • the insulating layer 206 can have a region in contact with the top surface of the semiconductor layer 208, a region in contact with the side surface of the semiconductor layer 208, a region in contact with the top surface of the conductive layer 104, a region in contact with the side surface of the conductive layer 104, and a region in contact with the insulating layer 106.
  • the conductive layer 204 is provided on the insulating layer 206 so as to have a region located inside the opening 245 and a region located inside the opening 247.
  • the conductive layer 204 is provided inside the opening 245 so as to have a region that faces the semiconductor layer 208 with the insulating layer 206 sandwiched between it and the conductive layer 204.
  • the conductive layer 204 has a shape that follows the insulating layer 206, and specifically, can have a shape that follows the top surface of the insulating layer 206 and the side surfaces of the insulating layer 206 inside the openings 245 and 247.
  • the conductive layer 204 can also have a region that contacts the top surface of the insulating layer 206 and a region that contacts the side surfaces of the insulating layer 206 inside the openings 245 and 247.
  • FIG. 22A is a block diagram showing a configuration example of a display device 30, which is a display device of one embodiment of the present invention.
  • the display device 30 includes a display portion 25, a scanning line driver circuit 31, a signal line driver circuit 33, and a power supply circuit 35.
  • the display portion 25 includes a plurality of pixels 21 arranged in a matrix. Note that the power supply circuit 35 may be provided outside the display device 30.
  • the scanning line driving circuit 31 is electrically connected to the pixels 21 via wiring 41.
  • the wiring 41 extends, for example, in the row direction of the matrix.
  • the signal line driving circuit 33 is electrically connected to the pixels 21 via the wiring 43.
  • the wiring 43 extends, for example, in the column direction of the matrix.
  • the power supply circuit 35 is electrically connected to the pixels 21 via wiring 45.
  • all the pixels 21 can be electrically connected to the power supply circuit 35 via the same wiring 45.
  • wiring 41 and wiring 43 are shown as straight lines, but one straight line is not necessarily one wiring, and multiple wirings may be represented by one straight line. In the block diagrams and circuit diagrams that follow, multiple wirings may also be represented by one straight line. Also, multiple wirings other than wiring 41 and wiring 43 may also be represented by one straight line.
  • the pixel 21 has a display element, and can display an image on the display unit 25 by using the display element.
  • a light-emitting element can be used as the display element, and specifically, an organic EL element can be used.
  • a liquid crystal element also called a liquid crystal device
  • the display element can also be used as the display element.
  • the scanning line driving circuit 31 has a function of selecting, for example, the pixels 21 to which image data is to be written, row by row. Specifically, the scanning line driving circuit 31 can select the pixels 21 to which image data is to be written, by outputting a signal to the wiring 41. Here, the scanning line driving circuit 31 can select all the pixels 21 by, for example, outputting the signal to the wiring 41 in the first row, and then outputting the signal to the wiring 41 in the second row, and so on up to the wiring 41 in the final row. Therefore, the signal that the scanning line driving circuit 31 outputs to the wiring 41 is a scanning signal, and the wiring 41 can be called a scanning line.
  • the signal line driving circuit 33 has a function of generating image data.
  • the image data is supplied to the pixels 21 via the wiring 43.
  • the scanning line driving circuit 31 can write image data to all the pixels 21 included in the row selected.
  • the image data can be expressed as a signal (image signal). Therefore, the wiring 43 can be called a signal line.
  • the power supply circuit 35 has a function of generating a power supply potential and supplying it to the wiring 45.
  • the power supply circuit 35 has a function of generating, for example, a high power supply potential (hereinafter also simply referred to as "high potential” or “VDD”) and supplying it to the wiring 45.
  • the power supply circuit 35 may also have a function of generating a low power supply potential (hereinafter also simply referred to as "low potential” or "VSS"). Because a power supply potential is supplied to the wiring 45, the wiring 45 can be called a power supply line.
  • FIG. 22B is a plan view showing a configuration example of pixel 21.
  • Pixel 21 can have multiple sub-pixels 23.
  • FIG. 22B shows an example in which pixel 21 has sub-pixels 23R, 23G, and 23B.
  • the planar shape of the sub-pixels shown in FIG. 22B corresponds to the planar shape of the light-emitting region of the light-emitting element.
  • FIG. 22B shows the aperture ratios (sizes, or sizes of light-emitting regions) of sub-pixels 23R, 23G, and 23B as being equal or approximately equal, but one embodiment of the present invention is not limited to this.
  • the aperture ratios of sub-pixels 23R, 23G, and 23B can be determined appropriately.
  • the aperture ratios of sub-pixels 23R, 23G, and 23B may be different from each other, or two or more may be equal or approximately equal.
  • subpixel 23 when describing matters common to subpixel 23R, subpixel 23G, and subpixel 23B, the letters that distinguish them may be omitted and they may be referred to as subpixel 23. When describing matters common to other elements that are distinguished by letters, they may also be described using symbols without the letters.
  • a stripe arrangement is applied as the arrangement method of the sub-pixels 23.
  • an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, or the like may also be applied as the arrangement method of the sub-pixels 23.
  • the sub-pixels 23R, 23G, and 23B each emit light of a different color.
  • Examples of the sub-pixels 23R, 23G, and 23B include sub-pixels of three colors, red (R), green (G), and blue (B), and sub-pixels of three colors, yellow (Y), cyan (C), and magenta (M).
  • Four or more sub-pixels 23 may be provided in the pixel 21.
  • the pixel 21 may be provided with four sub-pixels of R, G, B, and white (W).
  • the display device 30 can display a full-color image on the display unit 25 by having the pixel 21 have a plurality of sub-pixels 23 that emit light of different colors.
  • the pixel 21 may be provided with sub-pixels of R, G, B, and infrared light (IR).
  • the display unit 25 may be provided with a sensor, for example, a sensor may be provided in the pixel 21.
  • a sensor may be provided in the pixel 21.
  • the display unit 25 may have a function as a fingerprint sensor.
  • the display unit 25 may have a function as an optical or ultrasonic fingerprint sensor.
  • FIG. 22C is a circuit diagram showing an example of the configuration of a subpixel 23.
  • the subpixel 23 shown in FIG. 22C has a pixel circuit 40A and a light-emitting element 60.
  • the light-emitting element 60 for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used.
  • Examples of the light-emitting material possessed by the light-emitting element 60 include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (for example, a quantum dot material). Additionally, LEDs such as micro LEDs (Light Emitting Diodes) can be used as the light emitting elements 60.
  • Pixel circuit 40A has transistor 200, transistor 100, and capacitance 57.
  • pixel circuit 40A is a 2Tr (transistor) 1C (capacitor) type pixel circuit.
  • one of the source and drain of the transistor 200 is electrically connected to the wiring 43.
  • the other of the source and drain of the transistor 200 is electrically connected to the gate of the transistor 100.
  • the gate of the transistor 100 is electrically connected to one electrode of the capacitor 57.
  • the gate of the transistor 200 is electrically connected to the wiring 41.
  • One of the source or drain of the transistor 100 is electrically connected to the wiring 45.
  • the other of the source or drain of the transistor 100 is electrically connected to the other electrode of the capacitor 57.
  • the other electrode of the capacitor 57 is electrically connected to one electrode of the light-emitting element 60.
  • the other electrode of the light-emitting element 60 is electrically connected to the wiring 47.
  • the one electrode of the light-emitting element 60 is also called a pixel electrode.
  • the wiring 47 can be shared, for example, between all the subpixels 23. Therefore, the other electrode of the light-emitting element 60 is also called a common electrode.
  • wiring 41 functions as a scanning line
  • wiring 43 functions as a signal line
  • wiring 45 functions as a power supply line
  • wiring 47 functions as a power supply line, and when a high power supply potential is supplied to wiring 45, for example, a low power supply potential is supplied to wiring 47.
  • Wiring 47 can be electrically connected to, for example, power supply circuit 35.
  • the transistor 200 functions as a switch and is also called a selection transistor.
  • the transistor 200 has a function of controlling the conductive state or non-conductive state between the wiring 43 and the gate of the transistor 100 based on the potential of the wiring 41.
  • image data is written to the pixel circuit 40A, and by turning off the transistor 200, the written image data is retained.
  • the on-current of the transistor 200 is large, image data can be written to the pixel circuit 40A at high speed, which is preferable.
  • the transistor 100 has a function of controlling the amount of current flowing through the light-emitting element 60 and is also called a driving transistor.
  • the capacitor 57 has a function of holding the potential of the gate of the transistor 100.
  • the light emission luminance of the light-emitting element 60 is controlled according to the potential corresponding to image data supplied to the gate of the transistor 100. Specifically, when a high power supply potential is supplied to the wiring 45 and a low power supply potential is supplied to the wiring 47, the magnitude of the current flowing from the wiring 45 to the wiring 47 is controlled according to the potential of the gate of the transistor 100. This controls the light emission luminance of the light-emitting element 60.
  • the transistor 100 has high saturation, the current flowing through the light-emitting element 60 can be stabilized, and the light emission luminance of the light-emitting element 60 can be stabilized, which is preferable.
  • the current flowing through the light-emitting element 60 can be prevented from varying over time, and the light emission luminance of the light-emitting element 60 can be prevented from varying over time.
  • the transistors 100 and 200 shown in FIG. 22C can be the transistors 100 and 200 shown in FIG. 21A and FIG. 21B. As described above, the transistor 100 has a longer channel length and higher saturation than the transistor 200. In addition, the transistor 100 can be a transistor with a fine size. As described above, by applying the transistor 100 to a driving transistor, the pixel 21 in which the subpixel 23 is provided can be made fine while increasing the saturation of the driving transistor. Therefore, the current flowing through the light-emitting element 60 can be stabilized, and the light emission luminance of the light-emitting element 60 can be stabilized.
  • the transistor 200 has a shorter channel length than the transistor 100. Therefore, the transistor 200 can have a larger on-current than the transistor 100. Furthermore, the transistor 200 can be a transistor with a fine size. As described above, by applying the transistor 200 to a selection transistor, the pixel 21 in which the sub-pixel 23 is provided can be made fine, while the on-current of the selection transistor can be made large. Therefore, the pixel 21 can be made fine, while image data can be written to the pixel 21 at high speed.
  • the semiconductor device 20 As described above, by applying the semiconductor device 20 to a display device, a display device that is high-definition, highly reliable, and operates at high speed can be realized.
  • the width D141 shown in FIG. 3A and FIG. 17A is larger than the thickness T110b_2 shown in FIG. 19B, the difference between the channel length of the transistor 100 and the channel length of the transistor 200 can be increased. This is preferable because it may be possible to increase the saturation of the transistor 100 and increase the on-current of the transistor 200.
  • Figure 22D is a circuit diagram showing an example configuration of a subpixel 23.
  • the subpixel 23 shown in Figure 22D has a pixel circuit 40B and a liquid crystal element 69.
  • Pixel circuit 40B has a transistor 50 and a capacitance 57.
  • pixel circuit 40B is a 1Tr1C type pixel circuit.
  • one of the source and drain of the transistor 50 is electrically connected to the wiring 43.
  • the other of the source and drain of the transistor 50 is electrically connected to one electrode of the capacitor 57.
  • One electrode of the capacitor 57 is electrically connected to one electrode of the liquid crystal element 69.
  • the gate of the transistor 50 is electrically connected to the wiring 41.
  • the other electrode of the capacitor 57 and the other electrode of the liquid crystal element 69 are electrically connected to the wiring 45.
  • the one electrode of the liquid crystal element 69 is also referred to as a pixel electrode.
  • the other electrode of the liquid crystal element 69 may be referred to as a common electrode.
  • a ground potential can be supplied to the wiring 45.
  • the transistor 50 functions as a switch and controls the conductive state or non-conductive state between the wiring 43 and one electrode of the liquid crystal element 69 based on the potential of the wiring 41. By turning on the transistor 50, image data is written to the pixel circuit 40B, and by turning off the transistor 50, the written image data is retained.
  • Capacitor 57 has the function of holding the potential of one electrode of liquid crystal element 69.
  • the orientation state of liquid crystal element 69 is controlled according to the potential corresponding to image data that is supplied to one electrode of liquid crystal element 69.
  • the modes of the liquid crystal element 69 include, for example, TN (Twisted Nematic) mode, STN (Super-Twisted Nematic) mode, VA (Vertical Alignment) mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, and FLC (Ferroelectric Liquid Crystal) mode.
  • TN Transmission Nematic
  • STN Super-Twisted Nematic
  • VA Very Alignment
  • ASM Anaxially Symmetric Aligned Micro-cell
  • OCB Optically Compensated Birefringence
  • FLC Fluorroelectric Liquid Crystal
  • mode AFLC (AntiFerroelectric Liquid Crystal) mode
  • MVA Multidomain Vertical Alignment
  • PVA Powerned Vertical Alignment
  • IPS In Plane Switching
  • FFS Feringe Field Switching
  • TBA Transverse Bend Alignment
  • ECB Electrode Controlled Birefringence
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • the transistor 50 can have a similar structure to the transistor 100 or the transistor 200 described in this specification.
  • the channel length of the transistor 50 can be made longer than when the transistor 50 has a similar structure to the transistor 200, for example, and the off-current of the transistor 50 can be made smaller. This allows image data to be held in the subpixel 23 for a long period of time.
  • the transistor 50 have a similar structure to the transistor 200, the channel length of the transistor 50 can be made shorter than when the transistor 50 has a similar structure to the transistor 100, for example, and the on-current of the transistor 50 can be made larger. This allows image data to be written to the subpixel 23 at high speed.
  • Figure 23A is a plan view showing an example of the configuration of pixel circuit 40A shown in Figure 22C.
  • Figure 23B is a plan view in which the hatching of conductive layer 104 shown in Figure 23A is omitted and represented by dashed lines. Insulating layer 110 is not shown in Figures 23A and 23B.
  • Figure 23C is a cross-sectional view of the cut surface taken along dashed line C1-C2 shown in Figure 23A.
  • Figure 23C shows an example of the configuration of capacitance 57.
  • the transistor 100 and the transistor 200 have the same configuration as that shown in FIG. 21A.
  • the capacitor 57 has a conductive layer 112b on the insulating layer 110, an insulating layer 106 on the conductive layer 112b, and a conductive layer 104 on the insulating layer 106.
  • At least a part of the conductive layer 212a functions as a wiring 43 that functions as a signal line, and is electrically connected to the signal line driver circuit 33 shown in FIG. 22A.
  • At least a part of the conductive layer 112a functions as a wiring 45 that functions as a power line, and is electrically connected to the power supply circuit 35 shown in FIG. 22A.
  • At least a part of the conductive layer 204 functions as a wiring 41 that functions as a scanning line, and is electrically connected to the scanning line driver circuit 31 shown in FIG. 22A.
  • FIG. 24A and 24B are modified examples of the semiconductor device 20 shown in FIG. 17A and FIG. 19A, respectively, and show an example in which the other of the source electrode or drain electrode of the transistor 100 is electrically connected to the other of the source electrode or drain electrode of the transistor 200.
  • FIG. 24A and FIG. 24B show an example in which the other of the source electrode or drain electrode of the transistor 100 and the other of the source electrode or drain electrode of the transistor 200 are both conductive layers 112b.
  • FIG. 24A and FIG. 24B show an example in which the transistor 200 does not have the conductive layer 212b.
  • the semiconductor device 20 shown in FIG. 24A and FIG. 24B is a semiconductor device 20C.
  • the semiconductor layer 208 can have a region in contact with the side surface of the conductive layer 112b and a region in contact with the top surface of the conductive layer 112b.
  • FIG. 25A is a block diagram showing an example of the configuration of a display device 30, which is a modified example of the display device 30 shown in FIG. 22A.
  • the display device 30 shown in FIG. 25A differs from the display device 30 shown in FIG. 22A in that it has wiring 41a and wiring 41b as wiring 41, and that it is provided with a reference potential generating circuit 37.
  • the reference potential generating circuit 37 is electrically connected to the pixels 21 via the wiring 48.
  • all the pixels 21 can be electrically connected to the reference potential generating circuit 37 via the same wiring 48.
  • the reference potential generating circuit 37 has a function of generating a reference potential for correcting the variation of the gate-source voltage (potential difference between the gate and the source) of the driving transistor for each driving transistor, for example, and supplying it to the wiring 48. Since the potential of the wiring 48 becomes the reference potential, the wiring 48 can be called a reference potential line.
  • the reference potential generating circuit 37 may be called a power supply circuit.
  • the power supply circuit 35 and the reference potential generating circuit 37 may be integrated into one circuit.
  • the reference potential generating circuit 37 may be included in the power supply circuit 35.
  • Figure 25B is a circuit diagram showing an example of the configuration of a sub-pixel 23 included in the pixel 21 shown in Figure 25A.
  • the sub-pixel 23 shown in Figure 25B has a pixel circuit 40C and a light-emitting element 60.
  • Pixel circuit 40C has transistor 51, transistor 100, transistor 200, and capacitance 57.
  • pixel circuit 40C is a 3Tr (transistor) 1C (capacitor) type pixel circuit.
  • one of the source and drain of the transistor 51 is electrically connected to the wiring 43.
  • the other of the source and drain of the transistor 51 is electrically connected to the gate of the transistor 100.
  • the gate of the transistor 100 is electrically connected to one electrode of the capacitor 57.
  • the gate of the transistor 51 is electrically connected to the wiring 41a.
  • One of the source or drain of the transistor 100 is electrically connected to the wiring 45.
  • One of the source or drain of the transistor 200 is electrically connected to the wiring 48.
  • the other of the source or drain of the transistor 100 is electrically connected to the other of the source or drain of the transistor 200.
  • the other of the source or drain of the transistor 200 is electrically connected to the other electrode of the capacitor 57.
  • the other electrode of the capacitor 57 is electrically connected to one electrode of the light-emitting element 60.
  • the gate of the transistor 200 is electrically connected to the wiring 41b.
  • the other electrode of the light-emitting element 60 is electrically connected to the wiring 47.
  • transistor 51 functions as a selection transistor.
  • Transistor 100 functions as a drive transistor.
  • Transistor 200 functions as a switch and controls the conductive state and non-conductive state between wiring 48 and one electrode of light-emitting element 60 based on the potential of wiring 41b.
  • a reference potential for example, is supplied to wiring 48.
  • the reference potential of wiring 48 supplied via transistor 200 can suppress the variation in the gate-source voltage of each transistor 100 provided in each of the multiple subpixels 23.
  • the wiring 48 can also function as a monitor line for outputting the current flowing through the transistor 100 or the current flowing through the light-emitting element 60 to the outside of the subpixel 23.
  • the current output to the wiring 48 can be converted to a potential by, for example, a source follower circuit. Or, it can be converted to a digital signal by, for example, an A-D converter.
  • the transistor 100 and transistor 200 shown in FIG. 25B can be the transistor 100 and transistor 200 shown in FIG. 24A and FIG. 24B.
  • the transistor 100 as a driving transistor
  • the subpixel 23 can be miniaturized while the saturation of the driving transistor can be increased.
  • the transistor 200 as a transistor electrically connected to the wiring 48 that functions as a reference potential line
  • the subpixel 23 can be miniaturized while the reference potential can be supplied to the pixel circuit 40C at high speed.
  • the transistor 51 can be a transistor having a similar configuration to the transistor 200, for example.
  • Figure 26A is a plan view showing an example of the configuration of pixel circuit 40C shown in Figure 25B. Insulating layer 110 is not shown in Figure 26A.
  • Figure 26B is a cross-sectional view of the cut surface taken along dashed line C3-C4 shown in Figure 26A.
  • Figure 26B shows an example of the configuration of transistor 51 and capacitor 57.
  • the transistor 51 has a conductive layer 72a functioning as one of the source electrode and the drain electrode, a conductive layer 112b functioning as the other of the source electrode and the drain electrode, a semiconductor layer 78 having a channel formation region, an insulating layer 106 functioning as a gate insulating layer, and a conductive layer 74 functioning as a gate electrode.
  • the insulating layer 110 has an opening 71 reaching the conductive layer 72a, and the conductive layer 112b has an opening 73 having a region overlapping with the opening 71.
  • the semiconductor layer 78, the insulating layer 106, and the conductive layer 74 are provided so as to have a region located inside the opening 71 and a region located inside the opening 73.
  • transistor 51 can be a transistor having a similar configuration to transistor 200.
  • conductive layer 72a, semiconductor layer 78, conductive layer 74, opening 71, and opening 73 correspond to conductive layer 212a, semiconductor layer 208, conductive layer 204, opening 241, and opening 243, respectively.
  • the insulating layer 106 has an opening 75 that reaches the conductive layer 112b, and the conductive layer 112b and the conductive layer 104 are electrically connected inside the opening 75. Specifically, for example, inside the opening 75, there is a region where the conductive layer 112b and the conductive layer 104 are in contact.
  • opening 75 is circular, but this is not limited to one aspect of the present invention, and opening 75 may have a shape similar to the shape that opening 141 can have, a shape similar to the shape that opening 241 can have, or a shape similar to the shape that opening 243 can have.
  • At least a part of the conductive layer 72a functions as a wiring 43 that functions as a signal line, and is electrically connected to the signal line driver circuit 33 shown in FIG. 25A.
  • At least a part of the conductive layer 112a functions as a wiring 45 that functions as a power line, and is electrically connected to the power circuit 35 shown in FIG. 25A.
  • At least a part of the conductive layer 212a functions as a wiring 48 that functions as a reference potential line, and is electrically connected to the reference potential generation circuit 37 shown in FIG. 25A.
  • At least a part of the conductive layer 74 functions as a wiring 41a that functions as a scanning line, and is electrically connected to the scanning line driver circuit 31 shown in FIG. 25A.
  • At least a part of the conductive layer 204 functions as a wiring 41b that functions as a scanning line, and is electrically connected to the scanning line driver circuit 31 shown in FIG. 25A.
  • the insulating layer 110 has a one-layer, two-layer, or three-layer laminated structure, but the insulating layer 110 may have a four or more layer laminated structure.
  • the semiconductor device 20 shown in this embodiment can be provided with an insulating layer 147 and an insulating layer 149, similar to the semiconductor device 10.
  • the insulating layer 147 and the insulating layer 149 can be provided between the insulating layer 110 and the semiconductor layer 208 and between the conductive layer 212b and the semiconductor layer 208.
  • the insulating layer 147 can have a region in contact with the top surface of the conductive layer 212a and a region in contact with the side surface of the conductive layer 212b in the opening 243.
  • the insulating layer 149 can also have a region in contact with the semiconductor layer 208.
  • Figure 27 is a circuit diagram showing an example configuration of a sub-pixel 23 included in the pixel 21 shown in Figure 25A.
  • the sub-pixel 23 shown in Figure 27 has a pixel circuit 40D and a light-emitting element 60.
  • Pixel circuit 40D has transistor Tr1, transistor Tr2, transistor Tr3, transistor Tr4, transistor Tr5, transistor Tr6, transistor Tr7, capacitance C1, capacitance C2, and capacitance C3.
  • pixel circuit 40D is a 7Tr (transistor) 3C (capacitor) type pixel circuit.
  • transistor Tr2 is a dual-gate type transistor having a first gate and a second gate.
  • the first gate of transistor Tr2 is simply referred to as the gate
  • the second gate is referred to as the back gate.
  • one of the source or drain of the transistor Tr1 is electrically connected to the gate of the transistor Tr2, one of the source or drain of the transistor Tr3, and one electrode of the capacitance C1.
  • One of the source or drain of the transistor Tr2 is electrically connected to the other of the source or drain of the transistor Tr3, one of the source or drain of the transistor Tr5, one of the source or drain of the transistor Tr6, the other electrode of the capacitance C1, and one electrode of the capacitance C2.
  • the back gate of the transistor Tr2 is electrically connected to one of the source or drain of the transistor Tr4 and the other electrode of the capacitance C2.
  • the other of the source or drain of the transistor Tr5 is electrically connected to one electrode of the capacitance C3 and one electrode of the light-emitting element 60.
  • the gate of the transistor Tr5 is electrically connected to one of the source or drain of the transistor Tr7 and the other electrode of the capacitance C3.
  • node N1 a node to which one of the source or drain of the transistor Tr2, the other of the source or drain of the transistor Tr3, one of the source or drain of the transistor Tr5, one of the source or drain of the transistor Tr6, the other electrode of the capacitance C1, and one electrode of the capacitance C2 are electrically connected.
  • node N2 A node to which the back gate of the transistor Tr2, one of the source or drain of the transistor Tr4, and the other electrode of the capacitance C2 are electrically connected is referred to as node N2.
  • node N3 A node to which one of the source or drain of the transistor Tr1, the gate of the transistor Tr2, one of the source or drain of the transistor Tr3, and one electrode of the capacitance C1 are electrically connected is referred to as node N3.
  • node N4 A node to which the gate of the transistor Tr5, one of the source or drain of the transistor Tr7, and the other electrode of the capacitance C3 are electrically connected is referred to as node N4.
  • the pixel circuit 40D is electrically connected to wiring 41, which includes wiring 41a, wiring 41b, and wiring 41c.
  • Wiring 41a is electrically connected to the gate of transistor Tr1, the gate of transistor Tr6, and the gate of transistor Tr7.
  • Wiring 41b is electrically connected to the gate of transistor Tr3, and the gate of transistor Tr4.
  • Wiring 41c is electrically connected to the other of the source or drain of transistor Tr7.
  • Wiring 43 is electrically connected to the other of the source or drain of transistor Tr1.
  • Wiring 45 is electrically connected to the other of the source or drain of transistor Tr2.
  • Wiring 48 is electrically connected to the other of the source or drain of transistor Tr6.
  • Wiring 49 is electrically connected to the other of the source or drain of transistor Tr4.
  • Transistor Tr1 and transistors Tr3 to Tr7 function as switches.
  • Transistors Tr1, Tr6, and Tr7 are turned on or off based on the potential of wiring 41a.
  • Transistors Tr3 and Tr4 are turned on or off based on the potential of wiring 41b.
  • Transistor Tr5 is turned on or off based on the potential of wiring 41c when transistor Tr7 is turned on.
  • the on-current of transistors Tr1, Tr6, and Tr7 is large, because this allows the pixel circuit 40D to be driven at high speed.
  • the on-current of transistor 200 can be made larger than the on-current of transistor 100. Therefore, it is preferable to use transistor 200 for transistors Tr1 and transistors Tr3 to Tr7.
  • the potential of the gate of the transistor Tr2 becomes a potential corresponding to the potential of the wiring 43.
  • the wiring 43 is also electrically connected to the signal line driving circuit 33, which has a function of generating image data. As described above, by turning on the transistor Tr1, image data can be written to the pixel circuit 40D, and by turning off the transistor Tr1, the written image data can be retained.
  • the transistor Tr1 is also called a selection transistor.
  • Transistor Tr2 has a function of controlling the amount of current flowing to the light-emitting element 60, and is also called a driving transistor.
  • Capacitor C1 has a function of holding the potential of the gate of transistor Tr2.
  • the light emission luminance of the light-emitting element 60 is controlled according to the potential corresponding to image data that is supplied to the gate of transistor Tr2. Specifically, when a high power supply potential is supplied to wiring 45 and a low power supply potential is supplied to wiring 47, the amount of current flowing from wiring 45 to wiring 47 is controlled according to the potential of the gate of transistor Tr2. This controls the light emission luminance of the light-emitting element 60.
  • the saturation of the transistor Tr2 is high, the current flowing through the light-emitting element 60 can be stabilized, and the light emission brightness of the light-emitting element 60 can be stabilized, which is preferable.
  • the saturation of the transistor 100 can be made higher than the saturation of the transistor 200, for example.
  • the transistor 100A described above is a dual-gate type transistor 100. For the above reasons, the transistor 100A or the transistor 100F, etc., can be applied to the transistor Tr2.
  • Transistor Tr5 has the function of controlling the emission and extinction of the light-emitting element 60.
  • transistors Tr3 and Tr6 are in the off state, turning transistor Tr5 on allows a current of a magnitude corresponding to the gate potential of transistor Tr2 to flow through the light-emitting element 60, causing the light-emitting element 60 to emit light.
  • turning transistor Tr5 off prevents current from flowing through the light-emitting element 60 regardless of the gate potential of transistor Tr2, causing the light-emitting element 60 to not emit light, i.e., to be extinguished.
  • wiring 48 can function as a monitor line for outputting the current flowing through transistor Tr2 functioning as a drive transistor or the current flowing through light-emitting element 60 to the outside of subpixel 23.
  • the threshold voltage of transistor Tr2 can be corrected.
  • the threshold voltage of transistor Tr2 can be corrected by controlling the potential of the backgate of transistor Tr2.
  • the potential of the backgate of transistor Tr2 can be held in capacitance C2.
  • Fig. 28 is a timing chart showing an example of a method for driving the pixel circuit 40D.
  • Figs. 29 to 35 are circuit diagrams showing the state of the pixel circuit 40D in each period shown in the timing chart.
  • potentials Va, Vc, V0, and V1 are supplied to the wiring 45, wiring 47, wiring 48, and wiring 49, respectively.
  • a high potential or a low potential is supplied to each of the wirings 41a, 41b, and 41c.
  • a high potential is a potential that, when supplied to the gate of an n-channel transistor, turns the transistor on
  • a low potential is a potential that, when supplied to the gate of an n-channel transistor, turns the transistor off.
  • transistors Tr1 to Tr7 are all n-channel transistors, but the following description can be referred to even if at least some of transistors Tr1 to Tr7 are p-channel transistors, for example, by appropriately reversing the magnitude relationship of the potentials.
  • the potential Va is the anode potential
  • the potential Vc is the cathode potential.
  • the potential Va is higher than the potential Vc and the potential V0.
  • the potential V1 is higher than the potential V0.
  • the potential V0 is set to 0 V.
  • the pixel circuit 40D has a function of controlling the magnitude of the current flowing through the light-emitting element 60 in response to the image signal supplied from the wiring 43.
  • the light emission brightness of the light-emitting element 60 is controlled by the magnitude of the current.
  • a symbol indicating a potential such as "H”, “L”, “V0”, or “V1” (also called a “potential symbol”) may be written next to a terminal or wiring.
  • “H” indicates a high potential
  • “L” indicates a low potential.
  • the potential symbol attached to the terminal, wiring, etc. where the potential change has occurred may be written in a box.
  • an "x" symbol may be superimposed on a transistor in an off state.
  • a current may be shown with a dashed arrow. Note that when a current is shown with a dashed arrow, the direction of the current flow may be opposite to that of the arrow.
  • the current flowing through the light-emitting element 60 is determined mainly by the image signal and the threshold voltage of the transistor Tr2. Therefore, even if the same image signal is supplied to multiple pixel circuits 40D arranged in a matrix, if the threshold voltage of the transistor Tr2 in each pixel circuit 40D is different, the current flowing through the light-emitting element 60 will be different. Therefore, the variation in the threshold voltage of the transistor Tr2 is one of the causes of deterioration in display quality.
  • the variation in the current flowing through the light-emitting element 60 is reduced by acquiring the threshold voltage of the transistor Tr2 for each subpixel 23.
  • the operation of acquiring the threshold voltage of the transistor Tr2 is sometimes referred to as the "threshold voltage correction operation.”
  • the wirings 41a and 41b are at a low potential, and the wiring 41c is at a high potential.
  • a reset operation is performed. Specifically, a high potential is supplied to the wirings 41a, 41b, and 41c (see FIG. 29). Supplying a high potential to the wiring 41a turns on the transistors Tr1, Tr6, and Tr7. Supplying a high potential to the wiring 41b turns on the transistors Tr3 and Tr4.
  • a potential V0 is supplied to node N1 via transistor Tr6.
  • a potential V1 is supplied to node N2 via transistor Tr4.
  • a potential V0 is supplied to node N3 via transistors Tr6 and Tr3.
  • a high potential is supplied to node N4 from wiring 41c via transistor Tr7, turning on transistor Tr5.
  • the wiring 43 and the wiring 48 are in a conductive state through the transistors Tr1, Tr3, and Tr6. Therefore, in the period T1, it is preferable that the wiring 43 has the same potential as the wiring 48 or that the wiring 43 is in a floating state.
  • Figure 29 shows an example in which the potential of the wiring 43 is set to a potential V0, which is equal to the potential of the wiring 48.
  • the potential of node N1 is lower than the potential of wiring 45. Therefore, a current can flow between the source of transistor Tr2 and node N1. Since the potentials of nodes N3 and N1 are both potential V0, the gate-source voltage of transistor Tr2 is 0V. In addition, since the potential of node N2 is potential V1 and the potential of node N1 is potential V0, the backgate-source voltage of transistor Tr2 (the potential difference between the backgate and source) is "V1-V0".
  • a low potential is supplied to wiring 41a (see FIG. 31).
  • a current flows from wiring 45 to node N1.
  • transistor Tr3 is in an on state, the potential of node N3 also rises.
  • the potentials of nodes N1 and N3 rise to "V1-Vth", which is the value obtained by subtracting the threshold voltage Vth of transistor Tr2 from the potential V1 of the backgate of transistor Tr2. Therefore, the backgate-source voltage of transistor Tr2 becomes the threshold voltage Vth.
  • nodes N1 and N2 are capacitively coupled via capacitance C2
  • the potential of node N1 changes in the same way.
  • the potential of node N2 is expressed as "V1-(V1-Vth-V0)". In other words, the potential of node N2 becomes "Vth+V0", and if potential V0 is 0V, it becomes the threshold voltage Vth.
  • a high potential is supplied to node N4 from wiring 41c via transistor Tr7, turning on transistor Tr5.
  • potential V0 is supplied to the anode of light-emitting element 60 via transistors Tr6 and Tr5.
  • nodes N2 and N3 are in a floating state.
  • Nodes N1 and N3 are capacitively coupled via capacitance C1.
  • the potential of node N3 becomes "Vdata+Va1". That is, even if the potential of the source of transistor Tr2 changes, the gate-source voltage of transistor Tr2 remains at potential Vdata.
  • the anode of the light-emitting element 60 and node N4 are capacitively coupled via capacitance C3. Therefore, when the potential of the anode of the light-emitting element 60 changes from potential V0 to potential Va2, the potential of node N4 also changes in the same way. Here, the potential of node N4 becomes "H+Va2.” In other words, even if the potential of the anode of the light-emitting element 60, which corresponds to the source of transistor Tr5, changes, the gate-source voltage of transistor Tr5 can be maintained at a high potential.
  • the gate of the transistor Tr5 when the gate of the transistor Tr5 is at a fixed potential, the gate-source voltage decreases as the source potential of the transistor Tr5 increases. When the gate-source voltage falls below the threshold voltage of the transistor Tr5, the transistor Tr5 is turned off. For this reason, when the potential of the anode of the light-emitting element 60 is increased, it is necessary to supply a high potential to the gate of the transistor Tr5 as well, and therefore a power supply or power supply circuit must be added. Therefore, by providing a capacitance C3 between the gate and source of the transistor Tr5 to form a bootstrap circuit, the on state of the transistor Tr5 can be maintained without adding a power supply circuit even if the potential of the anode of the light-emitting element 60 is increased.
  • the capacitance C3 may be called a "bootstrap capacitance.”
  • each of the capacitances C1 and C2 also functions as a bootstrap capacitance.
  • the amount of current Ie flowing through the light-emitting element 60 is determined by the potential Vdata corresponding to the image signal and the threshold voltage Vth of the transistor Tr2.
  • the amount of current Ie flowing through the light-emitting element 60 can be controlled by the potential Vdata by performing a threshold correction operation.
  • the transistor Tr5 In order to control the light emission luminance of the light emitting element 60 by the potential Vdata, it is necessary to reliably keep the transistor Tr5 in the on state during light emission operation. In the pixel circuit 40D, the transistor Tr5 can be reliably turned on during light emission operation. This enables accurate control of the current Ie, thereby improving color reproducibility of intermediate tones. Therefore, the display quality of the display device of one embodiment of the present invention can be improved.
  • a low potential is supplied to node N4 from wiring 41c via transistor Tr7, turning off transistor Tr5. This stops current flowing through light-emitting element 60, causing light emission by light-emitting element 60 to stop.
  • a potential VdataX corresponding to image data to be written to another sub-pixel 23 electrically connected to wiring 43 may be supplied to node N3 via transistor Tr1, but this does not impede the extinguishing operation because transistor M5 is in the off state.
  • Display devices that use light-emitting elements such as EL elements as display elements can keep the light-emitting elements lit during one frame period.
  • This type of drive method is also called “hold type” or “hold type drive”.
  • hold type drive By using hold type drive as the drive method for a display device, it is possible to reduce flickering and other phenomena on the display screen.
  • hold type drive is prone to causing afterimages and blurred images when displaying moving images.
  • the resolution that people perceive when displaying moving images is also called “moving image resolution”. In other words, hold type drive is prone to reducing video resolution.
  • Black insertion drive is also called “pseudo-impulse type” or “pseudo-impulse type drive.”
  • Black insertion drive is a drive method in which black is displayed every other frame, or black is displayed for a certain period of time during one frame.
  • black insertion driving can be easily achieved by the extinguishing operation. Therefore, the display device is less likely to experience a decrease in video resolution, and can display videos with high display quality.
  • the potential of wiring 41a is set to a low potential, and then the potential of wiring 41c is set to a high potential. This is an example of a method for driving pixel circuit 40D.
  • Figures 36A, 36B, 37A, 37B, 38A, 38B, and 39 are plan views showing an example of the configuration of a pixel circuit 40D.
  • Figures 36A, 36B, and 37A show components of transistors Tr1 to Tr7.
  • Figures 37B, 38A, 38B, and 39 show components of capacitors C1, C2, and C3 in addition to the components of transistors Tr1 to Tr7.
  • the transistor 100G shown in Figure 16A is used as the transistor Tr2.
  • the transistor 200 shown in Figure 20A for example, is used as the transistor Tr1 and transistors Tr3 to Tr7.
  • 36A shows conductive layer 901A, conductive layer 901B, conductive layer 901C, conductive layer 901D, conductive layer 901E, conductive layer 901F, conductive layer 901G, conductive layer 903A, conductive layer 903B, conductive layer 903C, conductive layer 903D, and conductive layer 903E.
  • conductive layers with the same reference numerals except for the alphabet can be formed using the same material and in the same process.
  • conductive layers 901A to 901G can be formed using the same material and in the same process.
  • conductive layers 903A to 903E can be formed using the same material and in the same process.
  • the conductive layer 901A corresponds to the conductive layer 103 of the transistor 100G and functions as a back gate electrode of the transistor Tr2.
  • the conductive layers 903A to 903E correspond to the conductive layer 212a of the transistor 200.
  • the conductive layer 903A functions as one of the source electrodes or drain electrodes of the transistor Tr1 and the transistor Tr3.
  • the conductive layer 903B functions as one of the source electrodes or drain electrodes of the transistor Tr4.
  • the conductive layer 903C functions as one of the source electrodes or drain electrodes of the transistor Tr5.
  • the conductive layer 903D functions as one of the source electrodes or drain electrodes of the transistor Tr6.
  • the conductive layer 903E functions as one of the source electrodes or drain electrodes of the transistor Tr7.
  • the conductive layer 903D functions as the wiring 48 shown in FIG. 27.
  • FIG. 36B shows conductive layer 905A, conductive layer 905B, conductive layer 905C, conductive layer 905D, conductive layer 905E, conductive layer 905F, conductive layer 905G, conductive layer 905H, semiconductor layer 909A, semiconductor layer 909B, semiconductor layer 909C, semiconductor layer 909D, semiconductor layer 909E, semiconductor layer 909F, semiconductor layer 909G, and semiconductor layer 909H.
  • the conductive layer 905A corresponds to the conductive layer 212b of the transistor 200 and functions as the other of the source electrode or drain electrode of the transistor Tr1.
  • the conductive layer 905B corresponds to the conductive layer 112a of the transistor 100G and functions as one of the source electrode or drain electrode of the transistor Tr2.
  • the conductive layer 905C corresponds to the conductive layer 112b of the transistor 100G and functions as the other of the source electrode or drain electrode of the transistor Tr2.
  • the conductive layer 905D corresponds to the conductive layer 112c of the transistor 100G.
  • the conductive layers 905E to 905H each correspond to the conductive layer 212b of the transistor 200.
  • the conductive layer 905E functions as the other of the source electrode or drain electrode of the transistor Tr3 and the transistor Tr6.
  • the conductive layer 905F functions as the other of the source electrode or drain electrode of the transistor Tr4.
  • the conductive layer 905G functions as the other of the source electrode or drain electrode of the transistor Tr5.
  • the conductive layer 905H functions as the other of the source electrode or drain electrode of the transistor Tr7.
  • Insulating layer 110 (not shown) is provided with openings 907A, 907B, 907C, 907D, 907E, 907F, 907G, and 907H.
  • Opening 907A corresponds to opening 241 shown in FIG. 20A, for example, and reaches conductive layer 903A.
  • Opening 907B corresponds to opening 141[1] shown in FIG. 16A, and reaches conductive layer 901A.
  • Opening 907C corresponds to opening 141[2] shown in FIG. 16A, and reaches conductive layer 901A.
  • Openings 907D to 907H each correspond to opening 241 shown in FIG. 20A etc. Opening 907D reaches conductive layer 903A. Opening 907E reaches conductive layer 903B. Opening 907F reaches conductive layer 903C. Opening 907G reaches conductive layer 903D. Opening 907H reaches conductive layer 903E.
  • An opening 908A is provided in the conductive layer 905A so as to have an area overlapping with the opening 907A.
  • An opening 908B is provided in the conductive layer 905E so as to have an area overlapping with the opening 907D, and an opening 908E is provided so as to have an area overlapping with the opening 907G.
  • An opening 908C is provided in the conductive layer 905F so as to have an area overlapping with the opening 907E.
  • An opening 908D is provided in the conductive layer 905G so as to have an area overlapping with the opening 907F.
  • An opening 908F is provided in the conductive layer 905H so as to have an area overlapping with the opening 907H.
  • Semiconductor layer 909A corresponds to semiconductor layer 208 of transistor 200, and is provided to have a region located inside opening 907A and a region located inside opening 907B.
  • Semiconductor layer 909B corresponds to semiconductor layer 108[1] of transistor 100G, and is provided to have a region located inside opening 907B.
  • Semiconductor layer 909C corresponds to semiconductor layer 108[2] of transistor 100G, and is provided to have a region located inside opening 907C.
  • the semiconductor layers 909D to 909H correspond to the semiconductor layer 208 of the transistor 200.
  • the semiconductor layer 909D is provided to have a region located inside the opening 907D and a region located inside the opening 908B.
  • the semiconductor layer 909E is provided to have a region located inside the opening 907E and a region located inside the opening 908C.
  • the semiconductor layer 909F is provided to have a region located inside the opening 907F and a region located inside the opening 908D.
  • the semiconductor layer 909G is provided to have a region located inside the opening 907G and a region located inside the opening 908E.
  • the semiconductor layer 909H is provided to have a region located inside the opening 907H and a region located inside the opening 908F.
  • FIG. 37A shows conductive layers 911A, 911B, 911C, and 911D.
  • Conductive layer 911A corresponds to conductive layer 204 in transistor 200 and functions as the gate electrodes of transistors Tr1, Tr6, and Tr7.
  • Conductive layer 911B corresponds to conductive layer 104 in transistor 100G and functions as the gate electrode of transistor Tr2.
  • the conductive layer 911C and the conductive layer 911D correspond to the conductive layer 204 of the transistor 200.
  • the conductive layer 911C functions as the gate electrode of the transistor Tr3 and the transistor Tr4.
  • the conductive layer 911D functions as the gate electrode of the transistor Tr5.
  • FIG. 37B shows conductive layer 913A, conductive layer 913B, conductive layer 913C, conductive layer 913D, conductive layer 913E, conductive layer 913F, conductive layer 913G, conductive layer 913H, conductive layer 913I, conductive layer 913J, and conductive layer 913K. Note that in the plan views showing configuration examples of pixel circuit 40D from FIG. 37B onwards, the reference numerals of some of the components are omitted.
  • the conductive layer 913A functions as one electrode of the capacitance C1.
  • the conductive layer 913B functions as one electrode of the capacitance C2.
  • the conductive layer 913G functions as one electrode of the capacitance C3.
  • the conductive layer 913A is electrically connected to the conductive layer 903A through the contact hole 917A, and is electrically connected to the conductive layer 911B through the contact hole 921B.
  • the conductive layer 913B is electrically connected to the conductive layer 901A through the contact hole 915A, and is electrically connected to the conductive layer 903B through the contact hole 917B.
  • the conductive layer 913C is electrically connected to the conductive layer 901B through the contact hole 915B, and is electrically connected to the conductive layer 911C through the contact hole 921C.
  • the conductive layer 913D is electrically connected to the conductive layer 901C through the contact hole 915C, and is electrically connected to the conductive layer 911A through the contact hole 921A.
  • the conductive layer 913E is electrically connected to the conductive layer 901G through the contact hole 915D, and is electrically connected to the conductive layer 905H through the contact hole 919G.
  • the conductive layer 913F is electrically connected to the conductive layer 905C through the contact hole 919C.
  • the conductive layer 913G is electrically connected to the conductive layer 903E through the contact hole 917D, and is electrically connected to the conductive layer 911D through the contact hole 921D.
  • the conductive layer 913H is electrically connected to the conductive layer 905A through the contact hole 919A.
  • the conductive layer 913I is electrically connected to the conductive layer 905B through the contact hole 919B.
  • the conductive layer 913J is electrically connected to the conductive layer 903C through the contact hole 917C, is electrically connected to the conductive layer 905E through the contact hole 919D, and is electrically connected to the conductive layer 905G through the contact hole 919F.
  • the conductive layer 913K is electrically connected to the conductive layer 905F through the contact hole 919E.
  • a contact hole refers to an opening for electrically connecting two conductive layers.
  • a contact hole is one form of an opening.
  • a and B are electrically connected through a contact hole, this includes the case where a plug is provided in the contact hole and A and B are electrically connected through the plug. It also includes the case where at least one of A and B has a region located inside the contact hole, and A and B are in contact inside the contact hole, thereby electrically connecting A and B.
  • the contact hole can be provided, for example, in an insulating layer.
  • FIG. 38A shows the elements shown in FIG. 37B as well as conductive layer 923A and conductive layer 923B.
  • Conductive layer 923A functions as the other electrode of capacitance C1 and the other electrode of capacitance C2.
  • Conductive layer 923B functions as the other electrode of capacitance C3.
  • Insulating layers that function as dielectrics are provided between conductive layer 913A and conductive layer 923A, between conductive layer 913B and conductive layer 923A, and between conductive layer 913G and conductive layer 923B.
  • the overlapping area between conductive layer 913A and conductive layer 923A functions as capacitance C1
  • the overlapping area between conductive layer 913B and conductive layer 923A functions as capacitance C2
  • the overlapping area between conductive layer 913G and conductive layer 923B functions as capacitance C3.
  • FIG. 38B shows conductive layers 925A, 925B, 925C, 925D, 925E, 925F, 925G, and 925H that function as wiring.
  • the conductive layer 925A is electrically connected to the conductive layer 913C through the contact hole 927A.
  • the conductive layer 925B is electrically connected to the conductive layer 913D through the contact hole 927B.
  • the conductive layer 925C is electrically connected to the conductive layer 913E through the contact hole 927C.
  • the conductive layer 925D is electrically connected to the conductive layer 913J through the contact hole 927D and is electrically connected to the conductive layer 923B through the contact hole 929B.
  • the conductive layer 925E is electrically connected to the conductive layer 913H through the contact hole 927E.
  • the conductive layer 925F is electrically connected to the conductive layer 913I through the contact hole 927F.
  • the conductive layer 925G is electrically connected to the conductive layer 913J through the contact hole 927G and is electrically connected to the conductive layer 923A through the contact hole 929A.
  • Conductive layer 925H is electrically connected to conductive layer 913K through contact hole 927H.
  • the conductive layer 925A functions as the wiring 41b shown in FIG. 27.
  • the conductive layer 925B functions as the wiring 41a shown in FIG. 27.
  • the conductive layer 925C functions as the wiring 41c shown in FIG. 27.
  • the conductive layer 925F functions as the wiring 45 shown in FIG. 27.
  • FIG. 39 shows conductive layers 931A, 931B, and 931C that function as wiring.
  • Conductive layer 931A is electrically connected to conductive layer 925D through contact hole 933A.
  • Conductive layer 931B is electrically connected to conductive layer 925E through contact hole 933B.
  • Conductive layer 931C is electrically connected to conductive layer 925H through contact holes 933C and 933D.
  • the conductive layer 931B functions as the wiring 43 shown in FIG. 27.
  • the conductive layer 931C functions as the wiring 49.
  • Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more of gallium and tin.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 108 and the semiconductor layer 208 may each be, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), or aluminum zinc oxide.
  • In oxide indium oxide
  • In-Zn oxide indium zinc oxide
  • In-Sn oxide indium tin oxide
  • ITO indium titanium oxide
  • In-Ga oxide indium gallium oxide
  • In-W oxide also referred to as IWO
  • IWO indium gallium aluminum oxide
  • In-Ga-Sn oxide also
  • indium tin oxide containing silicon also written as ITSO
  • gallium tin oxide Ga-Sn oxide
  • aluminum tin oxide Al-Sn oxide
  • etc. can be used.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table instead of or in addition to indium.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more nonmetallic elements.
  • the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the on-state current or field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V 0 ) can be suppressed.
  • the element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • In:Al:Zn 40:1:10 and metal oxides in the vicinity thereof can be preferably used.
  • a metal oxide having a polycrystalline structure is used for the semiconductor layer 108 and the semiconductor layer 208, the grain boundaries become the recombination center, and carriers are captured, which may reduce the on-current of the transistor.
  • a metal oxide having a composition that is likely to form a polycrystalline structure it is preferable to include an element that inhibits crystallization.
  • ITO indium tin oxide
  • ITSO indium tin oxide containing silicon
  • the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less.
  • energy dispersive X-ray spectrometry EDX
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 108 and the semiconductor layer 208 may each have the same or approximately the same composition.
  • a stacked structure of metal oxide layers with the same composition for example, they can be formed using the same sputtering target, which reduces the manufacturing cost.
  • the two or more metal oxide layers in each of the semiconductor layer 108 and the semiconductor layer 208 may have different compositions.
  • gallium, aluminum, or tin as the element M.
  • the element M in the first metal oxide layer and the second metal oxide layer may be the same or different from each other.
  • the first metal oxide layer and the second metal oxide layer may be IGZO layers having different compositions from each other.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • the boundary (interface) between the first metal oxide layer and the second metal oxide layer may not be clearly identified.
  • the semiconductor layer 108 and the semiconductor layer 208 are preferably made of a crystalline metal oxide.
  • Examples of the structure of the crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the semiconductor layer 108 and the semiconductor layer 208 each use CAAC-OS or nc-OS.
  • CAAC-OS has multiple layered crystals.
  • the c-axis of the crystals is oriented in the normal direction of the surface on which the semiconductor layer 108 and the semiconductor layer 208 are preferably layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 and the semiconductor layer 208 are formed.
  • the semiconductor layer 208 preferably has layered crystals parallel or approximately parallel to the top surface in a region in contact with the top surface of the conductive layer 212b, and has layered crystals parallel or approximately parallel to the side surface in a region in contact with the side surface of the conductive layer 212b.
  • the semiconductor layer 208 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the semiconductor layer 208 is formed, in the opening 241.
  • the layered crystals of the semiconductor layer 208 are formed parallel or approximately parallel to the channel length direction of the transistor 200, and thus the transistor can have a large on-current.
  • the semiconductor layer 108 preferably has layered crystals that are parallel or approximately parallel to the surface on which it is formed (here, the side surface of the insulating layer 110, the side surface of the conductive layer 112a, and the side surface of the conductive layer 112b).
  • the semiconductor layer 108 preferably has layered crystals that are parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which it is formed, in the region that overlaps with the conductive layer 104.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the higher the substrate temperature during formation the more crystalline the metal oxide can be formed.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation.
  • the higher the ratio of the flow rate of oxygen gas to the total film formation gas used in formation (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber the more crystalline the metal oxide can be formed.
  • the crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, the analysis may be performed by combining a plurality of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • V O H When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to reduce V O H in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies (V O ).
  • impurities such as water and hydrogen in the metal oxide
  • V O repair oxygen vacancies
  • supplying oxygen to a metal oxide to repair oxygen vacancies (V O ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., are highly resistant to radiation, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tell
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, conductive layer 212b, and conductive layer 204 may each have a single layer structure or a stacked structure of two or more layers.
  • Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and an alloy containing one or more of the above-mentioned metals as a component.
  • a low-resistance conductive material containing one or more of copper, silver, gold, and aluminum can be preferably used for each of the conductive layers 112a, 112b, 104, 103, 212a, 212b, and 204.
  • copper or aluminum is preferable because of its excellent mass productivity.
  • Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 103, conductive layer 212a, conductive layer 212b, and conductive layer 204 can each be made of a metal oxide (oxide conductor) having electrical conductivity.
  • oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide.
  • Conductive oxides containing indium are particularly preferred because of their high electrical conductivity.
  • a metal oxide that has become a conductor can be called an oxide conductor.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, it can be processed by a wet etching method, so that the manufacturing cost can be reduced.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 103, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 may be made of the same material or different materials.
  • the conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108.
  • the conductive layer 212a and the conductive layer 212b have a region in contact with the semiconductor layer 208.
  • a metal oxide is used as the semiconductor layer 108
  • an insulating oxide e.g., aluminum oxide
  • a metal oxide is used as the semiconductor layer 208
  • a metal that is easily oxidized is used for the conductive layer 212a and the conductive layer 212b
  • an insulating oxide may be formed between the conductive layer 212a and the semiconductor layer 208 and between the conductive layer 212b and the semiconductor layer 208, which may hinder the conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for the conductive layers 112a, 112b, 212a, and 212b.
  • conductive layer 112a, conductive layer 112b, conductive layer 212a, and conductive layer 212b it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel, respectively. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b can each be made of the oxide conductor described above.
  • a conductive oxide such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide doped with gallium can be used.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, and the conductive layer 212b may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 104 may each have a stacked structure.
  • In-Sn-Si oxide can be suitably used for the region in contact with the semiconductor layer 108 or the semiconductor layer 208
  • copper or tungsten can be suitably used for the region not in contact with the semiconductor layer 108 or the semiconductor layer 208.
  • the insulating layer 106, the insulating layer 105, and the insulating layer 206 may have a single-layer structure or a stacked structure of two or more layers.
  • the insulating layer 106, the insulating layer 105, and the insulating layer 206 preferably have one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • the insulating layer 106, the insulating layer 105, and the insulating layer 206 can be made of a material that can be used for the insulating layer 110.
  • the insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208.
  • the insulating layer 105 has a region in contact with the semiconductor layer 108
  • the insulating layer 206 has a region in contact with the semiconductor layer 208.
  • a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208
  • any of the above-mentioned oxides and oxynitrides for at least the films constituting the insulating layer 206 that are in contact with the semiconductor layer 208. It is also more preferable to use films that release oxygen by heating for the insulating layer 106, the insulating layer 105, and the insulating layer 206.
  • the insulating layer 106, the insulating layer 105, and the insulating layer 206 have a single-layer structure, it is preferable to use an oxide or an oxynitride for the insulating layer 106, the insulating layer 105, and the insulating layer 206. Specifically, it is preferable to use silicon oxide or silicon oxynitride for the insulating layer 106, the insulating layer 105, and the insulating layer 206.
  • the insulating film on the side in contact with the semiconductor layer 108 and the semiconductor layer 208 contains an oxide or an oxynitride
  • the insulating film on the side in contact with the conductive layer 204 and the conductive layer 104 contains a nitride or a nitride oxide
  • the insulating layer 105 has a stacked structure, it is preferable that the insulating film on the side in contact with the semiconductor layer 108 contains an oxide or an oxynitride, and that the insulating film on the side in contact with the conductive layer 103 contains a nitride or a nitride oxide.
  • the insulating film on the side in contact with the semiconductor layer 208 contains an oxide or an oxynitride
  • the insulating film on the side in contact with the conductive layer 204 contains a nitride or a nitride oxide.
  • silicon oxide or silicon oxynitride can be preferably used as the oxide or oxynitride.
  • silicon nitride or silicon nitride oxide can be preferably used.
  • Silicon nitride and silicon nitride oxide are characterized by releasing a small amount of impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used as the insulating layer 106, the insulating layer 105, and the insulating layer 206.
  • impurities e.g., water and hydrogen
  • the electrical characteristics of the transistor can be improved and the reliability can be increased.
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • Examples of high-k materials that can be used for the insulating layer 106, the insulating layer 105, and the insulating layer 206 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • the insulating layer 109 which functions as a protective layer for the transistors 100 and 200, is preferably made of a material through which impurities are unlikely to diffuse. By providing the insulating layer 109, diffusion of impurities from the outside into the transistors can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.
  • the insulating layer 109 can be an insulating layer having an inorganic material or an insulating layer having an organic material.
  • an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 109.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • one or more of acrylic resin and polyimide resin can be used as the organic material.
  • a photosensitive material may be used as the organic material. Two or more of the above insulating films may be stacked.
  • the insulating layer 109 may have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.
  • the substrate 102 has at least a heat resistance sufficient to withstand a subsequent heat treatment.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 102.
  • a semiconductor element may be provided on the substrate 102. Note that the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate may be used as the substrate 102, and the transistors 100 and 200 may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistors 100 and 200. By providing the peeling layer, after a semiconductor device is partially or entirely completed on the substrate, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100 and 200 can be transferred to a substrate with poor heat resistance or a flexible substrate.
  • the substrate 102 may be formed by laminating an insulating layer on the aforementioned substrate.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), ALD, and molecular beam epitaxy (MBE).
  • CVD methods include PECVD and thermal CVD.
  • thermal CVD method is metal organic chemical vapor deposition (MOCVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the thin film When processing the thin film that constitutes the semiconductor device, for example, a photolithography method can be used.
  • the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV: Extreme Ultra-violet) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • etching the thin film one or more of the following methods can be used: dry etching, wet etching, and sandblasting.
  • Figures 40A to 41C show cross-sectional views corresponding to the dashed line A3-A4 shown in Figure 17A.
  • an insulating layer 101 is formed on a substrate 102 (FIG. 40A).
  • the insulating layer 101 can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • the method of forming at least one of the layers may be different from the method of forming the other layers.
  • the above also applies to other insulating layers, conductive layers, and semiconductor layers, etc., described below.
  • a conductive film that will become the conductive layer 212a is formed on the insulating layer 101, and the conductive film is processed to form the conductive layer 212a ( Figure 40A).
  • the conductive film can be preferably formed by a sputtering method.
  • insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b are formed on insulating layer 101 and conductive layer 212a, respectively.
  • insulating layer 110 is formed on insulating layer 101 and conductive layer 212a ( Figure 40A).
  • the insulating layers 110a, 110b, and 110c can be formed by, for example, ALD, sputtering, or CVD.
  • the insulating layer 110a can be preferably formed by ALD, and the insulating layers 110b and 110c can be preferably formed by sputtering.
  • the insulating layer 110b can contain a large amount of oxygen.
  • the insulating layer 110b by forming the insulating layer 110b by a sputtering method in an atmosphere containing oxygen, the insulating layer 110b can contain a large amount of oxygen.
  • the hydrogen concentration in the insulating layer 110b can be reduced.
  • oxygen can be supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 and the channel formation region of the semiconductor layer 208, which will be formed in a later process, and oxygen vacancies can be reduced.
  • Oxygen may also be supplied by forming an oxide film on the insulating layer 110b in an oxygen-containing atmosphere by sputtering.
  • the conductivity of the oxide film does not matter.
  • the oxide film at least one of an insulating film, a semiconductor film, and a conductive film can be used.
  • As the oxide film for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide, or indium tin oxide containing silicon can be used.
  • the oxide film it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108.
  • a metal oxide material that can be applied to the semiconductor layer 108.
  • the amount of oxygen supplied to the insulating layer 110b can be increased by increasing the ratio of the oxygen flow rate (oxygen flow rate ratio) to the total flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber.
  • the oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, and more preferably 80% or more and 100% or less.
  • oxygen can be supplied to the insulating layer 110b during the formation of the oxide film, and oxygen can be prevented from being released from the insulating layer 110b.
  • a large amount of oxygen can be trapped in the insulating layer 110b.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by a later heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • heat treatment may be performed.
  • oxygen can be suitably supplied from the oxide film to the insulating layer 110b.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 150°C or higher and 450°C or lower, more preferably 150°C or higher and 350°C or lower, and even more preferably 200°C or higher and 300°C or lower.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen.
  • a noble gas nitrogen, or oxygen.
  • dry air CODA: Clean Dry Air
  • It is preferable that the content of hydrogen, water, etc. in the atmosphere is as small as possible.
  • As the atmosphere it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower.
  • an oven a rapid heating (RTA: Rapid Thermal Annealing) device, etc. can be used. Using an RTA device can shorten the heating process time.
  • RTA Rapid Thermal Annealing
  • oxygen may be further supplied to the insulating layer 110b through the oxide film.
  • methods for supplying oxygen include ion implantation, ion doping, plasma immersion ion implantation, and plasma treatment.
  • an apparatus that converts oxygen gas into plasma by high-frequency power can be suitably used.
  • apparatus that convert gas into plasma by high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.
  • heat treatment may be performed before the oxide film is formed. By performing heat treatment, water and hydrogen can be released from the surface and inside of the insulating layer 110b.
  • the method for removing the oxide film is not particularly limited, but a chemical mechanical polishing (CMP) method or an etching method can be used.
  • CMP chemical mechanical polishing
  • an etching method is used to remove the oxide film, the insulating layer 110b can be prevented from being etched when the oxide film is removed by using a wet etching method.
  • the process of supplying oxygen to the insulating layer 110b is not limited to the above-mentioned method.
  • ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like may be performed without forming the oxide film on the insulating layer 110b.
  • oxygen may be supplied to the insulating layer 110b through the film. The film is preferably removed after oxygen is supplied.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.
  • the insulating layer 110a and the insulating layer 110c are preferably formed so that oxygen is less likely to permeate therethrough, for example, more difficult to permeate therethrough than the insulating layer 110b.
  • the insulating layer 110a and the insulating layer 110c are preferably formed so that the diffusion coefficient of oxygen is smaller, for example, more difficult to permeate therethrough than the insulating layer 110b.
  • the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the transistor is increased because the oxygen contained in the insulating layer 110b is prevented from diffusing to the insulating layer 110a and the insulating layer 110c, thereby reducing oxygen vacancies ( VO ) and VOH in the channel formation region.
  • a transistor with good electrical characteristics and high reliability can be manufactured.
  • the insulating layer 110 is planarized, specifically, the insulating layer 110b is planarized.
  • the planarization can be performed, for example, by using a CMP method.
  • the insulating layer 110a may be planarized, and the insulating layer 110b may not be planarized.
  • the insulating layer 110c may be planarized, or may not be planarized.
  • a conductive film 112f which will become conductive layer 112a, conductive layer 112b, and conductive layer 212b in a later step, is formed on insulating layer 110c (FIG. 40B).
  • the conductive film 112f can be preferably formed by, for example, a sputtering method.
  • the conductive film 112f can be processed using an etching method, and from the viewpoint of fine processing, it is preferable to process it by a dry etching method.
  • openings 141 and 241 in insulating layer 110 are removed to form openings 141 and 241 in insulating layer 110 (FIG. 40D).
  • Opening 141 has an area that overlaps opening 143 and is formed so as to reach insulating layer 101.
  • Opening 241 has an area that overlaps opening 243 and is formed so as to reach conductive layer 212a.
  • Removal of portions of insulating layer 110a, insulating layer 110b, and insulating layer 110c can be performed using an etching method, and from the viewpoint of fine processing, it is preferable to perform the removal using a dry etching method.
  • the opening 241 or after forming the opening 241 a part of the conductive layer 212a in the region overlapping with the opening 241 may be removed.
  • the electric field of the gate electrode applied to the channel formation region near the conductive layer 212a can be strengthened, and the on-current of the transistor 200 can be increased.
  • conductive layer 112a, conductive layer 112b, and conductive layer 212b are formed by processing conductive film 112f (FIG. 40E).
  • Conductive layer 112a and conductive layer 112b are formed to face each other across opening 141 in plan view.
  • Conductive layer 212b is formed to have opening 243.
  • conductive film 112f can be processed using an etching method, and from the viewpoint of fine processing, it is preferable to process it by dry etching.
  • a heat treatment may be performed.
  • the heat treatment may be performed at 250° C. to 650° C., preferably 300° C. to 500° C., and more preferably 320° C. to 450° C.
  • the heat treatment is performed in, for example, a nitrogen gas or inert gas atmosphere.
  • the heat treatment may be performed under reduced pressure.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • the heat treatment may be performed after the openings 143 and 243 are formed in the conductive film 112f and before the conductive layers 112a, 112b, and 212b are formed.
  • the semiconductor film 108f can be formed to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side of the conductive layer 112a, a region in contact with the upper surface of the conductive layer 112b, a region in contact with the side of the conductive layer 112b, a region in contact with the upper surface of the conductive layer 212a, a region in contact with the upper surface of the conductive layer 212b, a region in contact with the side of the conductive layer 212b, a region in contact with the upper surface of the insulating layer 110, a region in contact with the side of the opening 141 of the insulating layer 110, a region in contact with the side of the opening 241 of the insulating layer 110, and a region in contact with the upper surface of the insulating
  • a metal oxide film specifically an oxide semiconductor film
  • the semiconductor film 108f can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • the semiconductor film 108f is preferably formed by a film formation method with good coverage, and more preferably by a CVD method, an ALD method, or the like.
  • an In-Ga-Zn oxide film may be formed by an ALD method as the oxide semiconductor film. Note that when the side surfaces of the opening 141, the opening 241, and the opening 243 are tapered, the semiconductor film 108f can be formed by a sputtering method.
  • microwave treatment refers to treatment using an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can act on the oxide semiconductor.
  • Oxygen acting on the oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with unpaired electrons). Note that the oxygen acting on the oxide semiconductor may take one or more of the above forms, and is particularly preferably an oxygen radical.
  • the temperature at which the above-mentioned substrate is heated may be 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.
  • the carbon concentration in the oxide semiconductor film measured by SIMS can be set to less than 1 ⁇ 10 atoms/cm 3 , preferably less than 1 ⁇ 10 atoms/cm 3 , further preferably less than 1 ⁇ 10 atoms/cm 3 .
  • the semiconductor film 108f can have a stacked structure of two or more layers.
  • the deposition method of each layer may be the same or different.
  • the lower layer of the semiconductor film 108f may be deposited by a sputtering method
  • the upper layer of the semiconductor film 108f may be deposited by an ALD method.
  • An oxide semiconductor film deposited by a sputtering method is likely to have crystallinity. Therefore, by providing a crystalline oxide semiconductor film as the lower layer of the semiconductor film 108f, the crystallinity of the upper layer of the semiconductor film 108f can be improved.
  • the heat treatment may be performed in a temperature range in which the oxide semiconductor film does not become polycrystallized, and may be performed at 250° C. to 650° C., preferably 400° C. to 600° C.
  • the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.
  • the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere.
  • the gas used in the heat treatment is preferably highly purified.
  • the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less.
  • a heat treatment is performed after the semiconductor film 108f is formed, but the present invention is not limited to this. A heat treatment may be performed in a later process.
  • the semiconductor film 108f is processed to form the semiconductor layer 108 and the semiconductor layer 208 (FIG. 41B).
  • the semiconductor layer 108 and the semiconductor layer 208 can be layers containing metal oxide.
  • the semiconductor film 108f can be processed using an etching method, and is preferably processed by a dry etching method from the viewpoint of fine processing.
  • the semiconductor layer 108 is formed to have a region located inside the opening 141.
  • the semiconductor layer 108 can be formed along the bottom and side surfaces of the opening 141.
  • the semiconductor layer 108 can also be formed to have, for example, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the conductive layer 112a, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surface of the conductive layer 112b.
  • the semiconductor layer 108 can be formed to have a region in contact with the top surface of the insulating layer 101, and a region in contact with the side surface of the insulating layer 110.
  • the semiconductor layer 208 is formed to have a region located inside the opening 241 and a region located inside the opening 243.
  • the semiconductor layer 208 can be formed along the bottom and side surfaces of the opening 241 and the side surfaces of the opening 243.
  • the semiconductor layer 208 can be formed to have, for example, a region in contact with the top surface of the conductive layer 212a, a region in contact with the side surface of the conductive layer 212b, and a region in contact with the top surface of the conductive layer 212b.
  • the semiconductor layer 208 can be formed to have a region in contact with the side surface of the insulating layer 110.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112a, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110 (FIG. 41C).
  • the insulating layer 106 is formed on the semiconductor layer 108 and the semiconductor layer 208 so as to have a region located inside the opening 141, a region located inside the opening 241, and a region located inside the opening 243.
  • the insulating layer 106 can be formed by, for example, the ALD method, the CVD method, or the sputtering method.
  • the insulating layer 106 When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, the insulating layer 106 preferably functions as a barrier layer that suppresses oxygen diffusion.
  • the insulating layer 106 has a function of suppressing oxygen diffusion, oxygen contained in the semiconductor layer 108 and the semiconductor layer 208 is suppressed from diffusing above the insulating layer 106, and an increase in oxygen vacancies ( VO ) in the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. As a result, a transistor with good electrical characteristics and high reliability can be manufactured.
  • a barrier layer refers to a layer that has barrier properties.
  • an insulating layer that has barrier properties can be called a barrier insulating layer.
  • barrier properties refer to one or both of the function of suppressing the diffusion of the corresponding substance (also called low permeability) and the function of capturing or fixing the corresponding substance.
  • the substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C.
  • the substrate temperature during the formation of the insulating layer 106 By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108 and the semiconductor layer 208. Therefore, a transistor having good electrical characteristics and high reliability can be manufactured.
  • plasma treatment may be performed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208.
  • the plasma treatment can reduce impurities such as water adsorbed on the surfaces of the semiconductor layer 108 and the semiconductor layer 208. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 and the interface between the semiconductor layer 208 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the semiconductor layer 108 and the semiconductor layer 208 are exposed to the air between the formation of the semiconductor layer 108 and the semiconductor layer 208 and the formation of the insulating layer 106.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • a conductive film that will become the conductive layer 104 and the conductive layer 204 is formed on the insulating layer 106, and the conductive film is processed to form the conductive layer 104 and the conductive layer 204.
  • the transistor 100 and the transistor 200 can be manufactured ( Figure 41C).
  • the conductive layer 104 is formed to have a region located inside the opening 141.
  • the conductive layer 204 is formed to have a region located inside the opening 241 and a region located inside the opening 243.
  • the conductive films that become the conductive layer 104 and the conductive layer 204 can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • the insulating layer 109 is formed to cover the transistor 100 and the transistor 200. Specifically, the insulating layer 109 is formed to cover the conductive layer 104, the conductive layer 204, and the insulating layer 106 (FIG. 17B).
  • the insulating layer 109 can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • a heat treatment may be performed. Note that this heat treatment does not have to be performed. Alternatively, the heat treatment may not be performed here, and may serve as a heat treatment performed in a later step. Also, if there is a high-temperature process (e.g., a film formation process) in a later step, this may serve as the heat treatment.
  • a high-temperature process e.g., a film formation process
  • the semiconductor device 20 shown in Figures 17A and 17B can be manufactured.
  • the conductive layer 112a and the conductive layer 112b of the transistor 100 and the conductive layer 212b of the transistor 200 can be formed in the same step.
  • the semiconductor layer 108 of the transistor 100 and the semiconductor layer 208 of the transistor 200 can be formed in the same step.
  • the conductive layer 104 of the transistor 100 and the conductive layer 204 of the transistor 200 can be formed in the same step.
  • Fig. 20A and Fig. 20B An example of a method for manufacturing the semiconductor device 20A shown in Fig. 20A and Fig. 20B will be described with reference to Fig. 42A to Fig. 42D.
  • Fig. 42A to Fig. 42D show cross-sectional views corresponding to the dashed line A3-A4 shown in Fig. 20A. Note that the description of parts that overlap with the above-mentioned ⁇ Example 1 of manufacturing method for semiconductor device> will be omitted as appropriate, and the description will mainly focus on different parts.
  • an insulating layer 101 is formed on a substrate 102, and a conductive film that will become a conductive layer 103 is formed on the insulating layer 101.
  • the conductive film is then processed to form the conductive layer 103 (FIG. 42A).
  • the conductive film can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • the insulating layer 105 is formed on the insulating layer 101 and the conductive layer 103.
  • the insulating layer 105 can be formed by, for example, the ALD method, the CVD method, or the sputtering method.
  • the insulating layer 105 When a metal oxide is used for the semiconductor layer 108 formed in a later step, the insulating layer 105 preferably functions as a barrier layer that suppresses oxygen diffusion.
  • the insulating layer 105 has a function of suppressing oxygen diffusion, which suppresses oxygen contained in the semiconductor layer 108 from diffusing below the insulating layer 105, and can suppress an increase in oxygen vacancies ( VO ) in the semiconductor layer 108. As a result, a transistor with good electrical characteristics and high reliability can be manufactured.
  • a conductive layer 212a is formed on the insulating layer 105.
  • an insulating layer 110 is formed on the insulating layer 105 and the conductive layer 212a, and a conductive film 112f is formed on the insulating layer 110 ( Figure 42B).
  • the conductive film 112f is processed to form the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b having the opening 243. Furthermore, a part of the insulating layer 110 is removed to form the opening 141 and the opening 241 in the insulating layer 110 (FIG. 42C).
  • the opening 141 has an area overlapping with the conductive layer 103 and reaches the insulating layer 105.
  • the opening 241 reaches the conductive layer 212a.
  • the opening 241, the opening 243, the conductive layer 112a, the conductive layer 112b, and the conductive layer 212b refer to FIG. 40C to FIG. 40E.
  • the opening 141 and the opening 241 in the insulating layer 110 After forming the opening 141 and the opening 241 in the insulating layer 110, an opening reaching the conductive layer 212a is formed in the insulating layer 105. As a result, the opening 241 is also formed in the insulating layer 105.
  • the opening 141 and the opening 241 are formed in the insulating layer 110 by patterning using a resist mask, the resist mask is removed, and then the opening 241 is formed in the insulating layer 105 by patterning using a resist mask again, and the resist mask is removed, whereby the semiconductor device 20A shown in FIG. 20C can be manufactured.
  • the semiconductor layer 108, the semiconductor layer 208, the insulating layer 106, the conductive layer 104, and the conductive layer 204 are formed (FIG. 42D).
  • the insulating layer 109 is formed (FIG. 20B).
  • Fig. 21A and Fig. 21B An example of a method for manufacturing the semiconductor device 20B shown in Fig. 21A and Fig. 21B will be described with reference to Fig. 43A to Fig. 44B.
  • Fig. 43A to Fig. 44B show cross-sectional views corresponding to the dashed line A3-A4 shown in Fig. 21A. Note that the description of parts that overlap with the above-mentioned ⁇ Example 1 of manufacturing method for semiconductor device> will be omitted as appropriate, and the description will mainly focus on different parts.
  • the insulating layer 101, the conductive layer 212a, the insulating layer 110, and the conductive film 112f are formed in this order on the substrate 102.
  • a portion of the conductive film 112f is removed to form an opening.
  • a portion of the insulating layer 110 is removed to form an opening 141 in the insulating layer 110 that has an area that overlaps with the opening ( Figure 43A).
  • the conductive film 112f is processed to form the conductive layers 112a and 112b (FIG. 43B).
  • the conductive film 112f can be processed by an etching method, and is preferably processed by a dry etching method from the viewpoint of fine processing.
  • a heat treatment may be performed after the conductive layers 112a and 112b are formed.
  • the semiconductor layer 108 is formed so as to have a region located inside the opening 141.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112a, the conductive layer 112b, and the insulating layer 110.
  • the conductive film 104f that becomes the conductive layer 104 is formed on the insulating layer 106 (FIG. 43C).
  • the conductive film 104f can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • a portion of the conductive film 104f is removed to form an opening 247, and a portion of the insulating layer 110 is removed to form an opening 245 (FIG. 43D).
  • the opening 245 has an area that overlaps with the opening 247 and reaches the conductive layer 212a.
  • the removal of the portion of the conductive film 104f and the portion of the insulating layer 110 can be performed using an etching method, and from the viewpoint of microfabrication, it is preferable to perform the removal using a dry etching method.
  • the conductive film 104f is processed to form the conductive layer 104.
  • the conductive layer 104 is formed to have an opening 247. Note that after the conductive film 104f is processed to form the conductive layer 104, a part of the conductive layer 104 may be removed to form the opening 247, and then a part of the insulating layer 110 may be removed to form the opening 245.
  • the insulating layer 206 is formed to cover the semiconductor layer 208, the conductive layer 104, and the insulating layer 106 (FIG. 44B).
  • the insulating layer 206 is formed on the semiconductor layer 208 so as to have a region located inside the opening 245 and a region located inside the opening 247.
  • the insulating layer 206 can be formed by, for example, the ALD method, the CVD method, or the sputtering method.
  • the above-mentioned explanation of the formation of the insulating layer 106 can be referred to.
  • a conductive film that will become the conductive layer 204 is formed on the insulating layer 206, and the conductive film is processed to form the conductive layer 204.
  • the transistor 200 can be manufactured (FIG. 44B).
  • the conductive layer 204 is formed to have a region located inside the opening 245 and a region located inside the opening 247.
  • the conductive film that will become the conductive layer 204 can be formed by, for example, a sputtering method, a CVD method, or an ALD method.
  • insulating layer 109 is formed to cover conductive layer 204 and insulating layer 206 (FIG. 21B). Through the above steps, semiconductor device 20B shown in FIGS. 21A and 21B can be manufactured.
  • a display device to which the semiconductor device of one embodiment of the present invention is applied can be a high-definition display device.
  • the display device of one embodiment of the present invention can be used in the display portion of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display portion of a head-mounted display (HMD), a VR device such as a head-mounted display, and a glasses-type AR device, which can be worn on the head.
  • Display module 45A shows a perspective view of a display module 380.
  • the display module 380 includes a display device 30 and an FPC 390.
  • the display module 380 has a substrate 102 and a substrate 170.
  • the display module 380 has a display unit 25.
  • the display unit 25 is an area that displays an image.
  • Figure 45B shows a perspective view that shows a schematic configuration on the substrate 102 side.
  • a circuit portion 382, a pixel circuit portion 383 on the circuit portion 382, and a pixel portion 384 on the pixel circuit portion 383 are stacked.
  • a terminal portion 385 for connecting to an FPC 390 is provided in a portion of the substrate 102 that does not overlap with the pixel portion 384.
  • the terminal portion 385 and the circuit portion 382 are electrically connected by a wiring portion 386 that is composed of multiple wirings.
  • the pixel section 384 has a plurality of pixels 21 arranged periodically. An enlarged view of one pixel 21 is shown on the right side of FIG. 45B.
  • the pixel 21 has a light-emitting element 60R that emits red light, a light-emitting element 60G that emits green light, and a light-emitting element 60B that emits blue light.
  • the pixel circuit section 383 has a plurality of pixel circuits 40 arranged periodically.
  • Each pixel circuit 40 is a circuit that controls the emission of three light-emitting elements in one pixel 21.
  • One pixel circuit 40 may be configured to have three circuits that control the emission of one light-emitting element.
  • the pixel circuit 40 may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element for each light-emitting element. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.
  • the pixel circuit 40 may also be included in the pixel 21.
  • the circuit portion 382 has a circuit that drives each pixel circuit 40 in the pixel circuit portion 383.
  • a gate line driver circuit and a source line driver circuit.
  • it may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • a transistor provided in the circuit portion 382 may constitute a part of the pixel circuit 40.
  • the pixel circuit 40 may be composed of a transistor included in the pixel circuit portion 383 and a transistor included in the circuit portion 382.
  • the FPC 390 functions as wiring for supplying image signals, power supply potential, etc. from the outside to the circuit section 382.
  • an IC may be mounted on the FPC 390.
  • the display module 380 can be configured such that one or both of the pixel circuit section 383 and the circuit section 382 are provided overlappingly below the pixel section 384, so that the aperture ratio (effective display area ratio) of the display section 25 can be extremely high.
  • the aperture ratio of the display section 25 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
  • the pixels 21 can be arranged at an extremely high density, so that the resolution of the display section 25 can be extremely high.
  • the pixels 21 are arranged in the display section 25 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.
  • Such a display module 380 has extremely high resolution and can therefore be suitably used in VR devices such as head-mounted displays, or glasses-type AR devices. For example, even in a configuration in which the display section of the display module 380 is viewed through a lens, the display module 380 has an extremely high resolution display section 25, so that even if the display section is enlarged with a lens, the pixels are not visible, allowing for a highly immersive display.
  • the display module 380 is not limited to this and can be suitably used in electronic devices with relatively small display sections. For example, it can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • display device 30A, display device 30B, and display device 30C are shown as display devices that can be applied to display device 30.
  • a display device 30A shown in Fig. 46 includes a substrate 102, an insulating layer 101, an insulating layer 110, an insulating layer 109, a transistor 100, a capacitor 340, a light-emitting element 60R, a light-emitting element 60G, and a light-emitting element 60B, etc.
  • Fig. 46 shows an example in which the insulating layer 110 has a three-layered structure including an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.
  • the transistor 100 includes a conductive layer 112a, a conductive layer 112b, a semiconductor layer 108, an insulating layer 106, and a conductive layer 104.
  • the various transistors exemplified in embodiment 1 can be applied to the transistor 100.
  • the materials exemplified in embodiment 1 can be applied to the substrate 102, the insulating layer 101, the insulating layer 110a, the insulating layer 110b, the insulating layer 110c, and the insulating layer 109, and the functions exemplified in embodiment 1 can be provided.
  • An insulating layer 119 is provided on the insulating layer 109.
  • the insulating layer 119 functions as an interlayer insulating layer and can be a planarized layer. Note that a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 119 to the transistor 100 may be provided between the insulating layer 119 and the insulating layer 354 provided on the insulating layer 119.
  • the conductive layer 112a is electrically connected to a plug 374 embedded in the insulating layer 119.
  • the plug 374 preferably has a conductive layer 374a that covers the side of the opening of the insulating layer 119, the side of the opening of the insulating layer 109, and a part of the upper surface of the conductive layer 112a, and a conductive layer 374b having a region in contact with the conductive layer 374a.
  • a conductive material from which hydrogen and oxygen are unlikely to diffuse as the conductive layer 374a.
  • tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide.
  • a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, it is possible to suppress impurities such as water and hydrogen from being mixed into the semiconductor layer 108 and the semiconductor layer 208 through the plug 374.
  • the conductive layer 374b also functions as wiring, it is preferable to use a conductor with high conductivity.
  • the conductive layer 374b may be made of a conductive material mainly composed of tungsten, copper, or aluminum.
  • Capacitor 340 is provided on insulating layer 119.
  • Capacitor 340 has conductive layer 341, conductive layer 345, and insulating layer 343 located therebetween.
  • Conductive layer 341 functions as one electrode of capacitor 340
  • conductive layer 345 functions as the other electrode of capacitor 340
  • insulating layer 343 functions as a dielectric of capacitor 340.
  • the conductive layer 341 is provided on the insulating layer 119 and is embedded in the insulating layer 354.
  • the conductive layer 341 is electrically connected to the conductive layer 112a of the transistor 100 by a plug 374.
  • the insulating layer 343 is provided to cover the conductive layer 341.
  • the conductive layer 345 is provided in a region that overlaps with the conductive layer 341 via the insulating layer 343.
  • An insulating layer 355a is provided covering the capacitor 340, an insulating layer 355b is provided on the insulating layer 355a, and an insulating layer 355c is provided on the insulating layer 355b.
  • Insulating layer 119, insulating layer 354, insulating layer 343, insulating layer 355a, insulating layer 355b, and insulating layer 355c can each be preferably made of an inorganic insulating film.
  • examples of materials that can be used for the inorganic insulating film include oxide, nitride, oxynitride, and nitride oxide.
  • a silicon oxide film for the insulating layer 355a and the insulating layer 355c it is preferable to use a silicon oxide film for the insulating layer 355a and the insulating layer 355c, and a silicon nitride film for the insulating layer 355b.
  • an example is shown in which a part of the insulating layer 355c is etched to form a recess, but the insulating layer 355c does not necessarily have to have a recess.
  • Light-emitting elements 60R, 60G, and 60B are provided on insulating layer 355c.
  • Light-emitting element 60R has a pixel electrode 411R, an organic layer 412R, a common layer 414, and a common electrode 413.
  • Light-emitting element 60G has a pixel electrode 411G, an organic layer 412G, a common layer 414, and a common electrode 413.
  • Light-emitting element 60B has a pixel electrode 411B, an organic layer 412B, a common layer 414, and a common electrode 413.
  • the common layer 414 and the common electrode 413 are provided in common to light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B.
  • light-emitting element 60R when describing matters common to light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B, they may be referred to as light-emitting element 60.
  • components distinguished by alphabets such as organic layer 412R, organic layer 412G, and organic layer 412B, they may be described using symbols without the alphabet.
  • the organic layer 412R of the light-emitting element 60R has a light-emitting organic compound that emits at least red light.
  • the organic layer 412G of the light-emitting element 60G has a light-emitting organic compound that emits at least green light.
  • the organic layer 412B of the light-emitting element 60B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 412R, the organic layer 412G, and the organic layer 412B can each be called an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • display device 30A a different light-emitting element is created for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance.
  • organic layer 412R, organic layer 412G, and organic layer 412B are separated from each other, crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. This makes it possible to realize a display panel that is both high-definition and has high display quality.
  • Insulating layer 425, resin layer 426, and layer 428 are provided in the area between adjacent light-emitting elements.
  • the pixel electrode 411R, pixel electrode 411G, and pixel electrode 411B of the light-emitting element are electrically connected to the conductive layer 112a of the transistor 100 by a plug 356 embedded in the insulating layers 355a, 355b, and 355c, a conductive layer 341 embedded in the insulating layer 354, and a plug 374.
  • the height of the upper surface of the insulating layer 355c and the height of the upper surface of the plug 356 are the same or approximately the same.
  • Various conductive materials can be used for the plug. For example, the same material as that which can be used for the plug 374 can be used for the plug 356.
  • a protective layer 421 is provided on the light-emitting elements 60R, 60G, and 60B.
  • the substrate 170 is bonded to the protective layer 421 by an adhesive layer 471.
  • Display device 30B A display device having a configuration partially different from that described above will be described below, but the same configuration as the above will be referred to and the description thereof may be omitted.
  • the display device 30B shown in Figure 47 shows an example in which a transistor 150, which is a planar type transistor in which a semiconductor layer is formed on a flat surface, and a transistor 100 in which current flows both vertically and horizontally, are stacked.
  • the transistor 150 has a semiconductor layer 151, an insulating layer 153, a conductive layer 154, a pair of conductive layers 155, an insulating layer 156, and a conductive layer 157.
  • An insulating layer 152 is provided on the substrate 102.
  • the insulating layer 152 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 102 to the transistor 150 and prevents oxygen from being released from the semiconductor layer 151 toward the insulating layer 152.
  • a film in which one or both of hydrogen and oxygen are less likely to diffuse than in a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • a conductive layer 157 is provided on the insulating layer 152, and an insulating layer 156 is provided covering the conductive layer 157.
  • the conductive layer 157 functions as a first gate electrode of the transistor 150, and a part of the insulating layer 156 functions as a first gate insulating layer.
  • An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 156 that is in contact with the semiconductor layer 151.
  • the top surface of the insulating layer 156 is preferably planarized.
  • the semiconductor layer 151 is provided on the insulating layer 156.
  • the semiconductor layer 151 preferably contains a metal oxide.
  • a pair of conductive layers 155 is provided on and in contact with the semiconductor layer 151 and functions as a source electrode and a drain electrode.
  • An insulating layer 158 and an insulating layer 161 are provided to cover the top and side surfaces of the pair of conductive layers 155 and the side surfaces of the semiconductor layer 151.
  • the insulating layer 158 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 151 and prevents oxygen from being released from the semiconductor layer 151.
  • the insulating layer 158 can be an insulating film similar to the insulating layer 152.
  • An opening that reaches the semiconductor layer 151 is provided between one of the pair of conductive layers 155 of the insulating layer 158 and the insulating layer 161 in a planar view.
  • An insulating layer 153 in contact with the upper surface of the semiconductor layer 151 and a conductive layer 154 are embedded inside the opening.
  • the conductive layer 154 functions as a second gate electrode, and the insulating layer 153 functions as a second gate insulating layer.
  • the top surface of the conductive layer 154, the top surface of the insulating layer 153, and the top surface of the insulating layer 161 are planarized so that their heights are the same or approximately the same, and an insulating layer 159 is provided to cover them.
  • the insulating layer 159 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 100 and the transistor 150.
  • the insulating layer 159 can be an insulating film similar to the insulating layer 152.
  • Transistor 150 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates.
  • the two gates may be connected and the transistor may be driven by supplying the same signal to them.
  • the threshold voltage of transistor 150 may be controlled by supplying a potential to one of the two gates for controlling the threshold voltage and a potential to drive the other.
  • a display device 30C shown in FIG. 48 has a configuration in which a transistor 310 having a channel formed in a semiconductor substrate and a transistor 100 through which current flows both vertically and horizontally are stacked.
  • the transistor 310 is a transistor having a channel formation region in the substrate 102.
  • the substrate 102 of the display device 30C can be, for example, a semiconductor substrate such as a single crystal silicon substrate.
  • the transistor 310 has a part of the substrate 102, a conductive layer 311, a low resistance region 312, an insulating layer 313, and an insulating layer 314.
  • the conductive layer 311 functions as a gate electrode.
  • the insulating layer 313 is located between the substrate 102 and the conductive layer 311 and functions as a gate insulating layer.
  • the low resistance region 312 is a region in which the substrate 102 is doped with impurities, and functions as one of a source and a drain.
  • the insulating layer 314 is provided to cover the side surface of the conductive layer 311.
  • an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 102.
  • one aspect of the present invention is a display device having light-emitting elements.
  • the display device has two or more pixels that emit different light colors.
  • Each pixel has a light-emitting element.
  • a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light, respectively.
  • the shape and position of the island-shaped organic film deviate from the design, making it difficult to achieve high resolution and a high aperture ratio of the display device.
  • the contour of the layer may become blurred and the thickness of the edge may become thin.
  • the thickness of the island-shaped light-emitting layer may vary depending on the location.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM).
  • FMM fine metal mask
  • the EL layer can be produced separately, a display device that is extremely vivid, has high contrast, and has high display quality can be realized.
  • the EL layer may be processed into a fine pattern using both a metal mask and photolithography.
  • a part or the whole of the EL layer can be physically separated. This makes it possible to suppress leakage current between light-emitting elements via a layer shared between adjacent light-emitting elements (also called a common layer). This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.
  • One aspect of the present invention can be a display device that combines a white-emitting light-emitting element and a color filter.
  • light-emitting elements of the same configuration can be applied to light-emitting elements provided in pixels (subpixels) that emit light of different colors, and all layers can be common layers. Furthermore, a part or all of each EL layer can be divided by photolithography. This suppresses leakage current through the common layer, and a display device with high contrast can be realized.
  • leakage current through the intermediate layer can be effectively prevented, and a display device that combines high brightness, high definition, and high contrast can be realized.
  • an insulating layer that covers at least the side surface of the island-shaped light-emitting layer.
  • the insulating layer may be configured to cover a part of the upper surface of the island-shaped EL layer.
  • a material that has barrier properties against water and oxygen For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This makes it possible to suppress deterioration of the EL layer and realize a highly reliable display device.
  • Fig. 49A shows a schematic top view of a display device 30 according to one embodiment of the present invention.
  • the display device 30 includes a display portion 25.
  • the display device 30 includes a plurality of light-emitting elements 60R emitting red light, a plurality of light-emitting elements 60G emitting green light, and a plurality of light-emitting elements 60B emitting blue light over a layer 401.
  • the symbols R, G, and B are attached within the light-emitting regions of the light-emitting elements in order to easily distinguish the light-emitting elements from each other.
  • the layers 401 can include the substrate 102 to the insulating layer 355c shown in Figs. 46 to 48.
  • Light-emitting elements 60R, 60G, and 60B are arranged in a matrix on the display unit 25.
  • Figure 49A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light-emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be applied, and a pentile arrangement, a diamond arrangement, or the like may also be used.
  • FIG. 49A also shows a connection electrode 411C that is electrically connected to the common electrode 413.
  • the connection electrode 411C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 413.
  • the connection electrode 411C is provided outside the display area in which the light-emitting elements 60R, 60G, and 60B are arranged.
  • connection electrode 411C can be provided along the outer periphery of the display area. For example, it may be provided along one side of the outer periphery of the display area, or it may be provided over two or more sides of the outer periphery of the display area. In other words, if the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 411C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.
  • Figure 49B is a cross-sectional view of the cut surface taken along dashed line D1-D2 shown in Figure 49A.
  • Figure 49C is a cross-sectional view of the cut surface taken along dashed line D3-D4 shown in Figure 49A.
  • Figure 49B shows a schematic cross-sectional view of light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B, and
  • Figure 49C shows a schematic cross-sectional view of connection portion 440 where connection electrode 411C and common electrode 413 are connected.
  • the light-emitting element 60R has a pixel electrode 411R, an organic layer 412R, a common layer 414, and a common electrode 413.
  • the light-emitting element 60G has a pixel electrode 411G, an organic layer 412G, a common layer 414, and a common electrode 413.
  • the light-emitting element 60B has a pixel electrode 411B, an organic layer 412B, a common layer 414, and a common electrode 413.
  • the common layer 414 and the common electrode 413 are provided in common to the light-emitting element 60R, the light-emitting element 60G, and the light-emitting element 60B.
  • the organic layer 412 and the common layer 414 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the organic layer 412 can have a laminated structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 411 side, and the common layer 414 can have an electron injection layer.
  • a protective layer 421 is provided on the common electrode 413, covering the light-emitting elements 60R, 60G, and 60B.
  • the protective layer 421 has the function of preventing impurities such as water from diffusing from above to each light-emitting element.
  • the end of the pixel electrode 411 is preferably tapered.
  • the organic layer 412 provided along the end of the pixel electrode 411 can also be tapered.
  • the coverage of the organic layer 412 provided over the end of the pixel electrode 411 can be improved.
  • foreign matter for example, also called dust or particles
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface.
  • the structure it is preferable for the structure to have a region in which the angle between the inclined side and the substrate surface (also called the taper angle) is less than 90°.
  • the organic layer 412 is processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of the organic layer 412 at its edge is close to 90 degrees.
  • an organic film formed using FMM Fine Metal Mask
  • the top surface is formed in a slope over a range of 1 ⁇ m to 10 ⁇ m to the edge, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • an insulating layer 425, a resin layer 426, and a layer 428 are provided in the area between adjacent light-emitting elements.
  • the resin layer 426 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 412 and the area between the two organic layers 412.
  • the resin layer 426 has a smooth convex upper surface, and a common layer 414 and a common electrode 413 are provided covering the upper surface of the resin layer 426.
  • the resin layer 426 functions as a planarization film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 426, it is possible to prevent the phenomenon in which the common electrode 413 is divided by the step at the end of the organic layer 412 (also called step disconnection), and the common electrode 413 on the organic layer 412 is insulated.
  • the resin layer 426 can also be called an LFP (Local Filling Planarization) layer.
  • An insulating layer containing an organic material can be suitably used as the resin layer 426.
  • acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be used as the resin layer 426.
  • organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the resin layer 426.
  • a photosensitive resin can be used as the resin layer 426.
  • a photoresist can be used as the photosensitive resin.
  • a positive type material or a negative type material can be used as the photosensitive resin.
  • the resin layer 426 may contain a material that absorbs visible light.
  • the resin layer 426 itself may be made of a material that absorbs visible light, or the resin layer 426 may contain a pigment that absorbs visible light.
  • the resin layer 426 may be, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.
  • the insulating layer 425 is provided in contact with the side surface of the organic layer 412.
  • the insulating layer 425 is also provided to cover the upper end portion of the organic layer 412.
  • a portion of the insulating layer 425 is also provided in contact with the upper surface of the layer 401.
  • the insulating layer 425 is located between the resin layer 426 and the organic layer 412, and functions as a protective film to prevent the resin layer 426 from contacting the organic layer 412. If the organic layer 412 and the resin layer 426 come into contact, the organic layer 412 may be dissolved by, for example, an organic solvent used when forming the resin layer 426. Therefore, by providing the insulating layer 425 between the organic layer 412 and the resin layer 426, it is possible to protect the side surface of the organic layer 412.
  • the insulating layer 425 may be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used for the insulating layer 425.
  • the insulating layer 425 may have a single layer structure or a stacked structure.
  • the oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film.
  • the nitride insulating film include a silicon nitride film and an aluminum nitride film.
  • the oxynitride insulating film examples include a silicon oxynitride film and an aluminum oxynitride film.
  • the nitride oxide insulating film examples include a silicon nitride oxide film and an aluminum nitride oxide film.
  • a metal oxide film such as an aluminum oxide film or a hafnium oxide film formed by the ALD method, or an inorganic insulating film such as a silicon oxide film, as the insulating layer 425, it is possible to form an insulating layer 425 that has few pinholes and has excellent functionality for protecting the EL layer.
  • the insulating layer 425 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like.
  • the insulating layer 425 is preferably formed by an ALD method, which has good coverage.
  • a reflective film e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.
  • a reflective film may be provided between the insulating layer 425 and the resin layer 426, and the light emitted from the light-emitting layer may be reflected by the reflective film. This can improve the light extraction efficiency.
  • Layer 428 is a portion of a protective layer (also called a mask layer or a sacrificial layer) for protecting organic layer 412 when organic layer 412 is etched.
  • the material that can be used for insulating layer 425 can be used for layer 428.
  • metal oxide films such as aluminum oxide films or hafnium oxide films formed by the ALD method, or inorganic insulating films such as silicon oxide films, have few pinholes and therefore have excellent functionality for protecting the EL layer, and can be suitably used for the insulating layer 425 and the layer 428.
  • the protective layer 421 can have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film.
  • the inorganic insulating film include oxide films and nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, or a hafnium oxide film.
  • a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide may be used as the protective layer 421.
  • the protective layer 421 may be a laminated film of an inorganic insulating film and an organic insulating film.
  • an organic insulating film is sandwiched between a pair of inorganic insulating films.
  • the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties.
  • the upper surface of the protective layer 421 is flat, it is preferable that when a structure (e.g., a color filter, an electrode of a touch sensor, or a lens array, etc.) is provided above the protective layer 421, the influence of the uneven shape caused by the structure below can be reduced.
  • a structure e.g., a color filter, an electrode of a touch sensor, or a lens array, etc.
  • Figure 49C shows a connection portion 440 where the connection electrode 411C and the common electrode 413 are electrically connected.
  • connection portion 440 an opening portion is provided in the insulating layer 425 and the resin layer 426 above the connection electrode 411C.
  • the connection electrode 411C and the common electrode 413 are electrically connected in the opening portion.
  • FIG. 49C shows a connection portion 440 that electrically connects the connection electrode 411C and the common electrode 413
  • the common electrode 413 may be provided on the connection electrode 411C via the common layer 414.
  • the electrical resistivity of the material used for the common layer 414 is sufficiently low and the common layer 414 can be formed thin, so that there is often no problem even if the common layer 414 is located at the connection portion 440. This allows the common electrode 413 and the common layer 414 to be formed using the same masking mask, thereby reducing manufacturing costs.
  • Figure 50A shows a modified example of the configuration shown in Figure 49B, in which the light-emitting element has a different configuration and also has a colored layer.
  • the display device 30 has a light-emitting element 60W that emits white light.
  • the light-emitting element 60W has a pixel electrode 411, an organic layer 412W, a common layer 414, and a common electrode 413.
  • the organic layer 412W emits white light.
  • the organic layer 412W can be configured to include two or more types of light-emitting materials whose emitted light colors are complementary to each other.
  • the organic layer 412W can be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. It may also be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.
  • the organic layer 412W is separated between two adjacent light-emitting elements 60W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 60W via the organic layer 412W, and to suppress crosstalk caused by the leakage current. This makes it possible to realize a display device with high contrast and color reproducibility.
  • An insulating layer 422 that functions as a planarizing film is provided on the protective layer 421, and colored layers 416R, 416G, and 416B are provided on the insulating layer 422.
  • colored layer 416 when describing matters common to the colored layers 416R, 416G, and 416B, they may be referred to as colored layer 416.
  • the colored layer 416 has a higher transmittance for light of a specific wavelength than for light of other wavelengths.
  • the colored layer 416 has a function of transmitting light of a specific color.
  • the colored layer 416R has a function of transmitting red light
  • the colored layer 416G has a function of transmitting green light
  • the colored layer 416B has a function of transmitting blue light.
  • one light-emitting element 60W has an area that overlaps with one of the colored layers 416R, 416G, and 416B.
  • the display unit 25 can emit, for example, red light, green light, and blue light to perform full-color display.
  • Materials that can be used for the colored layer 416 include metal materials, resin materials, and resin materials containing pigments or dyes.
  • the colored layer 416 can be formed, for example, by using an inkjet method.
  • the insulating layer 422 can be an organic resin film or an inorganic insulating film with a flattened upper surface.
  • the insulating layer 422 forms the surface on which the colored layers 416R, 416G, and 416B are formed. Therefore, the flat upper surface of the insulating layer 422 can prevent unevenness from being formed on the upper surfaces of the colored layers 416R, 416G, and 416B. This allows the thickness of the colored layer 416R to be uniform, the thickness of the colored layer 416G to be uniform, and the thickness of the colored layer 416B to be uniform. As a result, the color purity of the image displayed on the display unit 25 can be improved. Note that if the thickness of the colored layer 416 is not uniform, the amount of light absorbed varies depending on the location of the colored layer 416, which may result in a decrease in color purity.
  • Figure 50A shows an example in which colored layers 416 that transmit light of different wavelengths are overlapped on a resin layer 426. This makes it possible to prevent light emitted by a light-emitting element 60W that overlaps with colored layer 416G from passing through the adjacent colored layer 416R or colored layer 416B and being emitted to the outside of the display device. This makes it possible to increase the contrast of the image displayed on the display unit 25 compared to when colored layers 416 that transmit light of different wavelengths do not overlap.
  • Fig. 50B is a modified example of the configuration shown in Fig. 49B.
  • the light-emitting element 60R has a pixel electrode 411, a conductive layer 415R, an organic layer 412W, and a common electrode 413.
  • the light-emitting element 60G has a pixel electrode 411, a conductive layer 415G, an organic layer 412W, and a common electrode 413.
  • the light-emitting element 60B has a pixel electrode 411, a conductive layer 415B, an organic layer 412W, and a common electrode 413.
  • the conductive layer 415R, the conductive layer 415G, and the conductive layer 415B each have light-transmitting properties and function as an optical adjustment layer.
  • a microresonator (microcavity) structure By using a film that reflects visible light for the pixel electrode 411 and a film that is both reflective and transparent to visible light for the common electrode 413, a microresonator (microcavity) structure can be realized.
  • a microresonator (microcavity) structure By adjusting the thicknesses of the conductive layers 415R, 415G, and 415B so as to provide optimal optical path lengths, even when an organic layer 412 that emits white light is used, it is possible to obtain light with intensified light of different wavelengths from the light-emitting elements 60R, 60G, and 60B.
  • colored layers 416R, 416G, and 416B are provided on the optical paths of light-emitting element 60R, light-emitting element 60G, and light-emitting element 60B, respectively, to obtain light with high color purity.
  • the contrast of the image displayed on display unit 25 can be increased.
  • an insulating layer 423 is provided to cover the ends of the pixel electrode 411, the conductive layer 415R, the conductive layer 415G, and the conductive layer 415B.
  • the insulating layer 423 preferably has a tapered end.
  • the organic layer 412W and the common electrode 413 are each provided as a continuous film common to each light-emitting element. This configuration is preferable because it can greatly simplify the manufacturing process of the display device.
  • the pixel electrode 411 has an end shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 423, and allows a thin portion to be formed in a portion of the organic layer 412W that covers this portion, or allows a portion of the organic layer 412W to be separated. Therefore, it is possible to suppress leakage current through the organic layer 412W that occurs between adjacent light-emitting elements, for example, without processing the organic layer 412W by photolithography.
  • Display device 70] 51 is a cross-sectional view showing a configuration example of a display device 70.
  • the display device 70 has, as a display element, the liquid crystal element 69 shown in FIG. 22D of the first embodiment.
  • the configuration of the display device 30 described above can be applied to the display device 70 as appropriate.
  • the display device 70 has a transistor 50 in addition to a liquid crystal element 69.
  • An insulating layer 109 is provided to cover the transistor 50, and an insulating layer 119 is provided on the insulating layer 109.
  • the liquid crystal element 69 is provided on the insulating layer 119.
  • the insulating layer 119 of the display device 70 can be suitably an insulating layer containing an organic material.
  • an organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.
  • the insulating layer 119 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 119 may be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • a photoresist may be used as the photosensitive resin.
  • Either a positive-type material or a negative-type material may be used as the photosensitive organic resin.
  • the insulating layer 119 may have a laminated structure of an organic insulating layer and an inorganic insulating layer.
  • the insulating layer 119 may have a laminated structure of an organic insulating layer and an inorganic insulating layer on the organic insulating layer.
  • the inorganic insulating layer can function as an etching protection layer. This prevents a portion of the insulating layer 119 from being etched when the pixel electrode 512 is formed, which reduces the flatness of the insulating layer 119.
  • the same material as that which can be used for the insulating layer 119 of the display device 70 may be used for the insulating layer 119 of the display device 30. Also, the same material as that which can be used for the insulating layer 119 of the display device 30 may be used for the insulating layer 119 of the display device 70.
  • the transistor 50 can have a structure similar to that of the transistor 100 or the transistor 200 described in this specification.
  • FIG. 51 shows an example in which the transistor 50 has a structure similar to that of the transistor 100.
  • the display device 70 may have a capacitor 57.
  • the liquid crystal element 69 has a pixel electrode 512 and a common electrode 516, and liquid crystal 543 is provided between the pixel electrode 512 and the common electrode 516.
  • An opening 529 reaching the conductive layer 112a is provided in the insulating layer 106, the insulating layer 109, and the insulating layer 119.
  • the pixel electrode 512 is electrically connected to the conductive layer 112a of the transistor 50 inside the opening 529.
  • Figure 51 shows an example in which the vertical electric field method is applied to the liquid crystal element 69, and liquid crystal 543 is provided between the pixel electrode 512 and the common electrode 516.
  • the pixel electrode 512 is provided separately for each liquid crystal element 69, and the common electrode 516 is shared by multiple liquid crystal elements 69.
  • the common electrode can also be called an opposing electrode.
  • a light-shielding layer 517, a colored layer 416, an insulating layer 533, a common electrode 516, and an insulating layer 547 are provided in this order. That is, in FIG. 51, the pixel electrode 512 and the layers below it are provided on the substrate 102 side, and the insulating layer 547 and the layers above it are provided on the substrate 170 side.
  • colored layer 416R and colored layer 416G are shown as the colored layer 416.
  • the display device 70 When manufacturing the display device 70, first, layers up to the pixel electrode 512 are formed on the substrate 102, and layers up to the insulating layer 547 are formed on the substrate 170. Next, the substrate 102 and the substrate 170, specifically the insulating layer 119 and the insulating layer 533, are bonded together using an adhesive layer (not shown). In addition, liquid crystal 543 is disposed between the pixel electrode 512 and the common electrode 516, for example, by a liquid crystal injection method or a liquid crystal dropping method. In this manner, the display device 70 can be manufactured.
  • the display device 70 is a transmissive liquid crystal display device, for example, a backlight that emits white light is provided on the outside of the substrate 102 (the side opposite to the substrate 170). Then, light emitted by the backlight and transmitted through the liquid crystal element 69 is extracted from the substrate 170 side, so that an image can be displayed on the display unit of the display device 70. Therefore, in the display device 70, it is preferable to use a material with high light-transmitting properties for the substrate 102 and the substrate 170. In addition, it is preferable to use a conductive material with high light-transmitting properties, for example, a conductive material with high light-transmitting properties for visible light, for the pixel electrode 512 and the common electrode 516.
  • a conductive material with high light-transmitting properties for example, a conductive material with high light-transmitting properties for visible light, for the pixel electrode 512 and the common electrode 516.
  • Examples of conductive materials with high light-transmitting properties include indium oxide, indium tin oxide, indium zinc oxide, and zinc oxide.
  • a conductive oxide such as zinc oxide to which gallium is added can be used as a conductive material with high light-transmitting properties.
  • graphene may be used as a conductive material with high light-transmitting properties.
  • Graphene can be formed by reducing graphene oxide.
  • graphene can be formed by applying heat to graphene oxide.
  • a metal or alloy that is thin enough to have light transmission can be used for the pixel electrode 512 and the common electrode 516.
  • a metal such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy containing such a metal can be used.
  • a nitride of such a metal or alloy for example, titanium nitride, can be used.
  • Two or more conductive layers containing the above-mentioned materials can be stacked.
  • a highly reflective conductive material for example, a conductive material that is highly reflective to visible light
  • a highly reflective conductive material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these metals in appropriate combinations.
  • highly reflective conductive materials include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), as well as alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).
  • aluminum alloys such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La)
  • Al-Ni-La alloy of aluminum, nickel, and lanthanum
  • silver such as an alloy of silver and magnesium
  • Ag-Pd-Cu also referred to as APC
  • various optical components such as a polarizing plate can be provided on the outside of the substrate 102 (the side opposite the substrate 170) and on the outside of the substrate 170 (the side opposite the substrate 102).
  • a backlight can be provided on the outside of the various optical components.
  • the insulating layer 547 functions as a spacer, and for example, the liquid crystal 543 can be configured not to overlap with the insulating layer 547.
  • the insulating layer 547 has a function of controlling the distance between the substrate 102 and the substrate 170 and controlling the thickness of the liquid crystal 543.
  • the insulating layer 547 does not overlap the pixel electrode 512, but the insulating layer 547 may overlap part of the pixel electrode 512.
  • the insulating layer 547 may overlap the pixel electrode 512 in the opening 529.
  • the insulating layer 547 overlaps part of the pixel electrode 512, the insulating layer 547 is provided between the pixel electrode 512 and the common electrode 516.
  • the alignment layer 541 can be provided on the substrate 102 side so as to cover the pixel electrode 512, and the alignment layer 545 can be provided on the substrate 170 side so as to cover the common electrode 516 and the insulating layer 547.
  • the liquid crystal 543 is provided between the alignment layer 541 and the alignment layer 545.
  • the liquid crystal 543 has a region in contact with the alignment layer 541 and a region in contact with the alignment layer 545.
  • the alignment layer 545 can have a region in contact with the alignment layer 541 in the region overlapping with the insulating layer 547.
  • the alignment layer 541 and the alignment layer 545 have the function of controlling the alignment of the liquid crystal 543. Note that the alignment layer 541 and the alignment layer 545 do not necessarily have to be provided.
  • the alignment layer 541 and the alignment layer 545 in the display device 70 When providing the alignment layer 541 and the alignment layer 545 in the display device 70, first, layers up to the pixel electrode 512 are formed on the substrate 102, and then the alignment layer 541 is formed so as to cover the pixel electrode 512. Also, layers up to the insulating layer 547 are formed on the substrate 170, and then the alignment layer 545 is formed so as to cover the common electrode 516 and the insulating layer 547. Next, the substrate 102 and the substrate 170, specifically the insulating layer 119 and the insulating layer 533, are bonded together using an adhesive layer (not shown). Also, the liquid crystal 543 is disposed between the alignment layer 541 and the alignment layer 545. In this manner, the display device 70 having the alignment layer 541 and the alignment layer 545 can be produced.
  • colored layer 416R transmits red light
  • colored layer 416G transmits green light
  • colored layer 416B transmits blue light. Therefore, even if the light emitted by the backlight is, for example, white light, the display unit of display device 70 can emit, for example, red light, green light, and blue light to perform full-color display.
  • the backlight may emit blue or purple light
  • the coloring layer 416 may be configured to use a color conversion material that converts the blue or purple light to another color (e.g., red or green).
  • a color conversion material e.g., a fluorescent material, a phosphorescent material, or a resin material in which quantum dots are dispersed, may be used.
  • the coloring layer 416 has a laminated structure of a color conversion material and a color filter from the backlight side.
  • a light-shielding layer 517 is provided between adjacent colored layers 416.
  • the portion where the light-shielding layer 517 is provided becomes a non-display area.
  • the light-shielding layer 517 is provided so as to have an area that overlaps with the insulating layer 547.
  • the light-shielding layer 517 can also be provided so as to have an area that overlaps with the opening 529. For example, by providing the light-shielding layer 517 so that the end of the colored layer 416 overlaps with the light-shielding layer 517, the colored layer 416 and the light-shielding layer 517 can be provided without any gaps.
  • the light-shielding layer 517 By providing the light-shielding layer 517, for example, it is possible to prevent light that has passed through the liquid crystal element 69 overlapping the colored layer 416R from passing through the adjacent colored layer 416G or colored layer 416B. In addition, by providing the light-shielding layer 517, for example, it is possible to prevent reflection of external light. As a result, it is possible to increase the contrast of the image displayed on the display unit of the display device 70. Note that a configuration without providing the light-shielding layer 517 is also possible. This allows the light emitted by the backlight to be efficiently extracted to the outside of the display device 70, specifically, for example, to the outside of the substrate 170.
  • the insulating layer 533 functions as an overcoat that, for example, prevents the components contained in the coloring layer 416 from diffusing into the liquid crystal element 69.
  • the insulating layer 533 is planarized, it is preferable because it is easy to form the common electrode 516 on the insulating layer 533.
  • the insulating layer 533 does not have to be planarized.
  • the insulating layer 533 can be made of the same material as the insulating layer 119.
  • FIG. 51 shows an example of a display device having a vertical electric field type liquid crystal element, but one embodiment of the present invention is not limited thereto, and may be, for example, a display device having a horizontal electric field type liquid crystal element.
  • a liquid crystal exhibiting a blue phase without using an alignment film may be used.
  • the blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to an isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal 543 in order to improve the temperature range.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and exhibits optical isotropy.
  • a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependency.
  • a rubbing treatment is also not required. Therefore, electrostatic damage caused by the rubbing treatment can be suppressed, and defects or damage to the display device during the manufacturing process can be reduced.
  • the electronic device of this embodiment has a display panel (display device) in which the semiconductor device of one embodiment of the present invention is applied to a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution, is highly reliable, and can achieve high display quality. Therefore, the display device can be used in the display portion of various electronic devices.
  • Examples of electronic devices include television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display panel of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 52A to 52D An example of a wearable device that can be worn on the head will be described using Figures 52A to 52D.
  • These wearable devices have one or both of the functions of displaying AR content and VR content. Note that these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR.
  • Electronic device 700A shown in FIG. 52A and electronic device 700B shown in FIG. 52B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display panel of one embodiment of the present invention can be applied to the display panel 751.
  • the electronic devices 700A and 700B can provide a user with a high sense of immersion because they can display images with extremely high resolution.
  • Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply, for example, a video signal through the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • electronic device 700A and electronic device 700B are provided with batteries, which can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation, a slide operation, or the like by the user, and can execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding.
  • a tap operation can execute processes such as pausing or resuming a video
  • a slide operation can execute processes such as fast-forwarding or rewinding.
  • the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, or an optical type.
  • a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element).
  • the active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 52C and electronic device 800B shown in FIG. 52D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display panel of one embodiment of the present invention can be applied to the display portion 820.
  • the electronic device 800A and the electronic device 800B can provide a user with a high sense of immersion because they can display images with extremely high resolution.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Each of the electronic devices 800A and 800B can be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head.
  • the mounting unit 823 is shown shaped like the temples of glasses, but is not limited to this.
  • the mounting unit 823 may be shaped like a helmet or band, for example, as long as it can be worn by the user.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies, for example, a video signal from a video output device and power for charging a battery provided in the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 52A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 52C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • Electronic device 700B shown in FIG. 52B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • the electronic device 800B shown in FIG. 52D has an earphone unit 827.
  • the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the mounting unit 823.
  • the earphone unit 827 and the mounting unit 823 may also have a magnet. This allows the earphone unit 827 to be fixed to the mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • the electronic device 6500 shown in Figure 53A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.
  • a display panel of one embodiment of the present invention can be applied to the display portion 6502.
  • the electronic device 6500 can be a highly reliable electronic device capable of displaying images with extremely high resolution.
  • Figure 53B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 53C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the television device 7100 shown in FIG. 53C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 53D shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7216 includes, for example, one or more of a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like.
  • the use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.
  • Figures 53E and 53F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 53E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 53F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 7000 of the electronic device shown in Figures 53C to 53F. This makes it possible to realize an electronic device that is capable of displaying with extremely high resolution and has high reliability.
  • the electronic device shown in Figures 54A to 54G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared), a microphone 9008, etc.
  • the electronic devices shown in Figures 54A to 54G have various functions. For example, they may have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic device are not limited to these, and the electronic device may have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a function of, for example, providing a camera, taking still images or videos, storing them on a recording medium (external or built into the camera), and displaying the taken images on the display unit.
  • FIG. 54A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 54A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notification of incoming e-mail, SNS, or telephone call, the title of the e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • the icon 9050, etc. may be displayed at the position where the information 9051 is displayed.
  • Figure 54B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • FIG 54C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG 54D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge the mobile information terminal 9200 through the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • Figures 54E to 54G are perspective views showing a foldable mobile information terminal 9201.
  • Figure 54E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • Figure 54G is a folded state
  • Figure 54F is a perspective view of a state in the middle of changing from one of Figures 54E and 54G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 9001 of the electronic device shown in Figures 54A to 54G. This makes it possible to realize an electronic device that is capable of displaying with extremely high resolution and is highly reliable.
  • sample 1 having the configuration shown in FIG. 55A and sample 2 having the configuration shown in FIG. 55B were fabricated.
  • sample 1 having a transistor 100 having the configuration shown in FIG. 19A and an insulating layer 110, etc. were fabricated.
  • sample 2 having a transistor 200 having the configuration shown in FIG. 19A and an insulating layer 110, etc. were fabricated.
  • sample 1 was fabricated so as to include multiple transistors 100
  • sample 2 was fabricated so as to include multiple transistors 200.
  • Sample 1 was manufactured by the method for manufacturing the transistor 100 shown in FIGS. 40A to 41C.
  • Sample 2 was manufactured by the method for manufacturing the transistor 200 shown in FIGS. 40A to 41C. Note that the transistor 200 was not manufactured in Sample 1, and the transistor 100 was not manufactured in Sample 2. The methods for manufacturing Sample 1 and Sample 2 are specifically described below.
  • sample 1 a silicon nitride film with a thickness of about 5 nm was formed as an insulating layer 101_1 on a silicon substrate 102_1 by the ALD method, and then a hafnium oxide film with a thickness of about 15 nm was formed by the ALD method.
  • the silicon nitride film was formed at a substrate temperature of 400° C.
  • the hafnium oxide film was formed at a substrate temperature of 250° C. using ozone (O 3 ) as an oxidizing agent.
  • the temperature of the substrate 102_1 is referred to as the substrate temperature.
  • insulating layer 110a_1, insulating layer 110b_1, and insulating layer 110c_1 were formed in this order as insulating layer 110_1 on insulating layer 101_1.
  • a silicon nitride film having a thickness of about 5 nm was formed as insulating layer 110a_1 by the ALD method.
  • the substrate temperature during the formation of insulating layer 110a_1 was set to 400°C.
  • a silicon oxide film with a thickness of about 20 nm was formed by sputtering using silicon as a target.
  • the insulating layer 110b_1 was formed with an oxygen gas flow rate of 100 sccm, an argon gas flow rate of 20 sccm, a substrate temperature of 200°C, a source power of 3000 W, a pressure of 0.6 Pa, and a bias power of 200 W.
  • a silicon nitride film with a thickness of about 10 nm was formed by sputtering using silicon as a target.
  • the insulating layer 110c_1 was formed with a nitrogen gas flow rate of 20 sccm, an argon gas flow rate of 5 sccm, a substrate temperature of room temperature, a source power of 1500 W, and a pressure of 0.2 Pa.
  • an ITSO film with a thickness of about 20 nm was formed by sputtering on the insulating layer 110c_1 as the conductive film 112f shown in FIG. 40B.
  • the ITSO film was a film containing 5 wt% silicon oxide relative to ITO.
  • the ITSO film was formed with an oxygen gas flow rate of 1.5 sccm, an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.4 Pa.
  • an opening 143 was formed in the ITSO film as shown in FIG. 40C and FIG. 40D.
  • An opening 141 was also formed in the insulating layers 110c_1, 110b_1, and 110a_1, overlapping with the opening 143 and reaching the insulating layer 101_1.
  • the opening 141 was designed to be a circle having a diameter of 350 nm in a plan view.
  • the ITSO film was processed using a dry etching method to form conductive layers 112a and 112b.
  • the semiconductor film 108f shown in FIG. 41A was formed on the conductive layer 112a, the conductive layer 112b, and the insulating layer 101_1.
  • a first metal oxide film with a thickness of about 2 nm and a second metal oxide film with a thickness of about 5 nm were formed in this order on the first metal oxide film.
  • the first metal oxide film was formed with an oxygen gas flow rate of 90 sccm, an argon gas flow rate of 10 sccm, and a substrate temperature of 250°C.
  • the second metal oxide film was formed using ozone as an oxidizing agent, with one cycle lasting 60 seconds.
  • the semiconductor film 108f was then processed by dry etching to form a two-layer stacked metal oxide layer as the semiconductor layer 108 with a width of 100 nm.
  • an insulating layer 106_1 was formed on the semiconductor layer 108, the conductive layer 112a, and the conductive layer 112b.
  • an aluminum oxide film having a thickness of about 1 nm, a silicon oxide film having a thickness of about 2 nm, a hafnium oxide film having a thickness of about 2 nm, and a silicon nitride film having a thickness of about 1 nm were sequentially formed by the ALD method.
  • the aluminum oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 300°C.
  • the silicon oxide film was formed using an organic precursor at a pressure of 400 Pa, a source power of 100 W, and a temperature of 350°C.
  • the hafnium oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 250°C.
  • the silicon nitride film was formed at a substrate temperature of 400°C.
  • a conductive film that becomes the conductive layer 104 was formed on the insulating layer 106_1 and processed to form the conductive layer 104.
  • a titanium nitride film with a thickness of about 5 nm was formed by CVD, and then a tungsten film with a thickness of about 20 nm was formed by sputtering.
  • the titanium nitride film was formed at a substrate temperature of 400°C.
  • the tungsten film was formed with an argon gas flow rate of 60 sccm, a substrate temperature of 130°C, a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film that became the conductive layer 104 was processed using a dry etching method. In this manner, the transistor 100 was formed.
  • an insulating layer 109_1 was formed so as to cover the transistor 100.
  • a silicon nitride film having a thickness of about 5 nm was formed as the insulating layer 109_1 by a sputtering method.
  • the insulating layer 109_1 was formed with a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 200° C., a source power of 1000 W, and a pressure of 0.5 Pa.
  • insulating layer 101_2 a silicon oxide film with a thickness of about 200 nm was formed as insulating layer 101_2 on substrate 102_2, which was a silicon substrate, by sputtering using silicon as a target.
  • Insulating layer 101_2 was formed with an oxygen gas flow rate of 25 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 170°C, a source power of 2500 W, and a pressure of 0.7 Pa.
  • a conductive film that becomes the conductive layer 212a was formed on the insulating layer 101_2 and processed to form the conductive layer 212a.
  • a titanium nitride film with a thickness of about 5 nm, a tungsten film with a thickness of about 20 nm, and an ITSO film with a thickness of about 10 nm were sequentially formed by sputtering.
  • the titanium nitride film was formed with a nitrogen gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 4000 W, and a pressure of 0.2 Pa.
  • the tungsten film was formed with an argon gas flow rate of 50 sccm, a substrate temperature of 130° C., a source power of 1000 W, and a pressure of 0.4 Pa.
  • the ITSO film was a film containing 5 wt % silicon oxide relative to ITO.
  • the ITSO film was formed with an oxygen gas flow rate of 1.5 sccm, an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film that became the conductive layer 212a was processed using a dry etching method.
  • insulating layer 110a_2, insulating layer 110b_2, and insulating layer 110c_2 were formed in this order as insulating layer 110_2 on insulating layer 101_2 and conductive layer 212a.
  • insulating layer 110a_2 a silicon nitride film having a thickness of about 5 nm was formed by the ALD method.
  • the substrate temperature during the formation of insulating layer 110a_2 was set to 400°C.
  • a first silicon oxide film having a thickness of about 40 nm, a second silicon oxide film having a thickness of about 35 nm, and a silicon nitride film having a thickness of about 100 nm were sequentially formed by a sputtering method using silicon as a target.
  • the first silicon oxide film was formed with an oxygen gas flow rate of 164 sccm, an argon gas flow rate of 36 sccm, a substrate temperature of 200°C, a source power of 1000 W, a pressure of 0.9 Pa, and a bias power of 200 W.
  • the second silicon oxide film was formed with an oxygen gas flow rate of 100 sccm, an argon gas flow rate of 20 sccm, a substrate temperature of 200°C, a source power of 3000 W, a pressure of 0.6 Pa, and a bias power of 200 W.
  • the silicon nitride film was formed with a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 200°C, a source power of 4000 W, and a pressure of 0.5 Pa.
  • the insulating layer 110b_2 was planarized using the CMP method so that the thickness of the insulating layer 110b_2 on the conductive layer 212a was 20 nm.
  • a silicon nitride film with a thickness of approximately 10 nm was formed by sputtering using silicon as a target.
  • the insulating layer 110c_2 was formed with a nitrogen gas flow rate of 20 sccm, an argon gas flow rate of 5 sccm, a substrate temperature of room temperature, a source power of 1500 W, and a pressure of 0.2 Pa.
  • an ITSO film with a thickness of about 20 nm was formed as the conductive layer 212b on the insulating layer 110c_2 by sputtering.
  • the ITSO film was a film containing 5 wt% silicon oxide relative to ITO.
  • the conductive layer 212b was formed with an oxygen gas flow rate of 1.5 sccm, an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.4 Pa.
  • opening 243 was formed in the ITSO film.
  • An opening 241 was formed in the insulating layers 110c_2, 110b_2, and 110a_2, overlapping with the opening 243 and reaching the conductive layer 212a.
  • openings 241 and 243 designed to be circular with a diameter of 60 nm in plan view, and openings 241 and 243 designed to be circular with a diameter of 150 nm in plan view were formed.
  • the semiconductor film 108f shown in FIG. 41A was formed on the conductive layer 212a and the conductive layer 212b.
  • a first metal oxide film with a thickness of about 2 nm and a second metal oxide film with a thickness of about 5 nm were formed in that order on the first metal oxide film.
  • the first metal oxide film was formed with an oxygen gas flow rate of 90 sccm, an argon gas flow rate of 6 sccm, and a substrate temperature of 250°C.
  • the second metal oxide film was formed using ozone as an oxidizing agent, with one cycle lasting 60 seconds.
  • the semiconductor film 108f was then processed by dry etching to form a two-layer stacked metal oxide layer as the semiconductor layer 208.
  • an insulating layer 106_2 was formed on the semiconductor layer 208.
  • an aluminum oxide film having a thickness of about 1 nm, a silicon oxide film having a thickness of about 2 nm, a hafnium oxide film having a thickness of about 2 nm, and a silicon nitride film having a thickness of about 1 nm were sequentially formed by the ALD method.
  • the aluminum oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 300°C.
  • the silicon oxide film was formed using an organic precursor at a pressure of 400 Pa, a source power of 100 W, and a temperature of 350°C.
  • the hafnium oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 250°C.
  • the silicon nitride film was formed at a substrate temperature of 400°C.
  • a conductive film to be the conductive layer 204 was formed on the insulating layer 106_2 and processed to form the conductive layer 204.
  • a titanium nitride film with a thickness of about 5 nm and a tungsten film with a thickness of about 20 nm were sequentially formed by a CVD method.
  • the titanium nitride film and the tungsten film were formed at a substrate temperature of 400° C.
  • the conductive film to be the conductive layer 204 was processed by a dry etching method. In this manner, the transistor 200 was formed.
  • the transistor 200 designed so that the openings 241 and 243 are circular with a diameter of 60 nm in a plan view, and the transistor 200 designed so that the openings 241 and 243 are circular with a diameter of 150 nm in a plan view were formed on the same substrate 102_2.
  • an insulating layer 109_2 was formed so as to cover the transistor 200.
  • a silicon nitride film having a thickness of about 5 nm was formed as the insulating layer 109_2 by a sputtering method.
  • the insulating layer 109_2 was formed with a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 200° C., a source power of 1000 W, and a pressure of 0.5 Pa.
  • FIG. 56 shows the measurement results of the Id-Vg characteristics of the transistor 100 included in the sample 1.
  • FIGS. 57A and 57B show the measurement results of the Id-Vg characteristics of the transistor 200 included in the sample 2.
  • FIG. 57A shows the measurement results of the Id-Vg characteristics of the transistor 200 designed so that the openings 241 and 243 are circular with a diameter of 60 nm in a plan view.
  • 57B shows the measurement results of the Id-Vg characteristics of the transistor 200 designed so that the openings 241 and 243 are circular with a diameter of 150 nm in a plan view.
  • the vertical axis shows the drain current Id [A] and the horizontal axis shows the gate voltage Vg [V].
  • the prototype transistors 100 and 200 are n-channel transistors.
  • the measurement conditions for the Id-Vg characteristics of the transistor were as follows: the voltage applied to the gate electrode (gate voltage Vg) was changed in 0.1 V increments from -4 V to 4 V.
  • the voltage applied to the source electrode (source voltage) was 0 V
  • the voltage applied to the drain electrode (drain voltage Vd) was 0.1 V and 1.2 V.
  • the threshold voltage was 0.22 V and the subthreshold swing value (S value) was 83.35 mV/dec.
  • the threshold voltage was 0.28 V
  • the threshold voltage variation was 41 mV
  • the S value was 124 mV/dec.
  • the threshold voltage was -0.23 V
  • the threshold voltage variation was 30 mV
  • the S value was 105 mV/dec.
  • the threshold voltage was set to the gate voltage Vg at which the drain current Id was 1 pA.
  • one aspect of the present invention makes it possible to fabricate a transistor with good switching characteristics.
  • Figure 58A is a scanning transmission electron microscope (STEM) image of sample 1.
  • Figure 58B is a STEM image of sample 2.
  • the semiconductor layer 108 was formed by processing the first metal oxide film with a thickness of about 20 nm. In other words, the second metal oxide film was not formed.
  • an aluminum oxide film with a thickness of about 1 nm, a silicon oxide film with a thickness of about 10 nm, a hafnium oxide film with a thickness of about 2 nm, and a silicon nitride film with a thickness of about 1 nm were formed in this order as the insulating layer 106_1.
  • a titanium nitride film with a thickness of about 5 nm, a tungsten film with a thickness of about 20 nm, and an ITSO film with a thickness of about 20 nm were sequentially formed as the conductive film that becomes the conductive layer 212a, and the conductive film was processed to form the conductive layer 212a.
  • a silicon nitride film with a thickness of about 15 nm was formed as the insulating layer 110a_2.
  • a first silicon oxide film with a thickness of about 40 nm, a second silicon oxide film with a thickness of about 45 nm, and a silicon nitride film with a thickness of about 100 nm were sequentially formed as the insulating layer 110b_2.
  • the semiconductor layer 208 was formed by processing the first metal oxide film with a thickness of about 5 nm and the second metal oxide film on the first metal oxide film with a thickness of about 5 nm.
  • the opening 241 and the opening 243 were designed to be circular with a diameter of 60 nm in a plan view.
  • the transistor 100 can be fabricated in the desired shape shown in FIG. 55A.
  • an opening 141 can be formed in the insulating layer 110_1, and the semiconductor layer 108 can be formed to have a region located inside the opening 141.
  • an insulating layer 106_1 can be formed on the semiconductor layer 108, and a conductive layer 104 can be formed on the insulating layer 106_1.
  • the transistor 200 can be manufactured in the desired shape shown in FIG. 55B, as shown in FIG. 58B.
  • an opening 241 can be formed in the insulating layer 110_2, and an opening 243 having a region overlapping with the opening 241 can be formed in the conductive layer 212b on the insulating layer 110_2.
  • the semiconductor layer 208, the insulating layer 106_2, and the conductive layer 204 can be formed in this order so as to have a region located inside the opening 241 and a region located inside the opening 243.
  • Figure 59 is a circuit diagram showing the configuration of a circuit 600 used to evaluate the off-state current of the transistor 200.
  • the circuit 600 includes a transistor 601, a transistor 603, a transistor 605, and a transistor 607.
  • One of the source and drain of the transistor 601 is electrically connected to the terminal IN.
  • the other of the source and drain of the transistor 601 is electrically connected to one of the source and drain of the transistor 603.
  • One of the source and drain of the transistor 603 is electrically connected to the gate of the transistor 605.
  • One of the source and drain of the transistor 605 and one of the source and drain of the transistor 607 are electrically connected to the terminal OUT.
  • a node to which the other of the source and drain of the transistor 601, one of the source and drain of the transistor 603, and the gate of the transistor 605 are electrically connected is referred to as a node FN.
  • the transistors 605 and 607 constitute a read circuit 610 having a function of reading the potential of the node FN from the terminal OUT.
  • Transistors 601, 603, 605, and 607 were each designed to have the desired channel length and channel width by connecting multiple transistors 200, each with a channel length of 20 nm and a channel width of 471 nm, in series and parallel.
  • openings 241 and 243 were designed to be circular with a diameter of 150 nm in a plan view, so that the design value of the channel width of transistor 200 was 150 ⁇ [nm] ⁇ 471 nm.
  • Transistor 601 has five transistors 200 connected in series and connected in parallel so that the channel width is 0.5 ⁇ m.
  • Transistor 603 does not have the transistors 200 connected in series, but has 20,000 transistors 200 connected in parallel, resulting in a channel length design value of 20 nm and a channel width design value of 9.4 mm.
  • Transistors 605 and 607 have 13 transistors 200 connected in series and connected in parallel so that the channel width is 7.1 ⁇ m.
  • the off-state current was evaluated by the following procedure. First, the transistor 601 was turned on, and the potential of the terminal IN was set to 1.2 V. As a result, a potential of 1.2 V was written to the node FN. Next, the potential of the gate of the transistor 601 and the potential of the gate of the transistor 603 were set to -1.5 V, and the transistors 601 and 603 were turned off. The change over time in the potential of the terminal OUT during this period was measured to measure the change over time in the potential of the node FN. Then, the off-state current of the transistor 603 was evaluated based on the change over time in the potential of the node FN.
  • the design value of the channel width of the transistor 603 was 18,800 times the design value of the channel width of the transistor 601, so the decrease in the potential of the node FN was attributed to the off-state current of the transistor 603.
  • Figure 60 is an Arrhenius plot showing the evaluation results of the off-current of transistor 200.
  • the horizontal axis shows the inverse (1000/T) [1/K] of temperature T [K], and the vertical axis shows the off-current Ioff [A/ ⁇ m] per 1 ⁇ m of channel width.
  • Figure 60 plots the calculated values of the off-current under each of the environments of 125°C, 100°C, and 85°C. The plot is the calculated value of the off-current of transistor 200, and the solid line is the regression line obtained from the calculated values.
  • the off-current of the fabricated transistor 200 in an environment of 27° C. was estimated to be 4.6 zA/ ⁇ m. Therefore, it was confirmed that the off-current of the fabricated transistor 200 was extremely low.
  • a display device was manufactured having transistors 100A and 200 with the configurations shown in Figures 20A and 20B.
  • a display device including the subpixel 23 shown in Figure 27 was manufactured with the pixel circuit 40D having the planar configuration shown in Figure 39. That is, transistor Tr2 was manufactured as transistor 100A, and transistors Tr1 and transistors Tr3 to Tr7 were manufactured as transistor 200. Note that transistors Tr1 to Tr7 were all n-channel transistors.
  • Transistors 100A and 200 were manufactured by the method shown in Figures 42A to 42D. The manufacturing method of the display device will be specifically described below.
  • a layer including a Si transistor is formed on the substrate 102, which is a silicon substrate.
  • a silicon nitride film having a thickness of about 60 nm, an aluminum oxide film having a thickness of about 40 nm, and a silicon oxide film having a thickness of about 120 nm are formed on the layer as an insulating layer 101 by a sputtering method in this order.
  • the silicon nitride film was formed using silicon as a target under the conditions of a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 30 sccm, a substrate temperature of 200° C., a power supply power of 1000 W, and a pressure of 0.5 Pa.
  • the aluminum oxide film was formed to a thickness of 5 nm using aluminum as a target under the conditions of an oxygen gas flow rate of 42 sccm, an argon gas flow rate of 42 sccm, a substrate temperature of 200° C., a power supply power of 5000 W, and a pressure of 0.4 Pa, and then formed to a thickness of 35 nm with a bias power of 50 W.
  • the silicon oxide film was formed using silicon as a target under the following conditions: oxygen gas flow rate 60 sccm, argon gas flow rate 60 sccm, substrate temperature 200°C, source power 3000 W, and pressure 0.6 Pa.
  • a conductive film that becomes the conductive layer 103 was formed on the insulating layer 101 and processed to form the conductive layer 103.
  • a tungsten film with a thickness of about 25 nm was formed as the conductive film that becomes the conductive layer 103.
  • the conductive film that becomes the conductive layer 103 was formed by a sputtering method under the conditions of an argon gas flow rate of 60 sccm, a substrate temperature of 130°C, a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film that became the conductive layer 103 was processed using a dry etching method.
  • an insulating layer 105 was formed on the insulating layer 101 and the conductive layer 103.
  • a silicon nitride film having a thickness of about 5 nm and a hafnium oxide film having a thickness of about 15 nm were formed in that order by the ALD method.
  • the silicon nitride film was formed at a substrate temperature of 400°C.
  • the hafnium oxide film was formed at a substrate temperature of 250°C using ozone as an oxidizing agent.
  • a conductive film that becomes the conductive layer 212a was formed on the insulating layer 105 and processed to form the conductive layer 212a.
  • a titanium nitride film with a thickness of about 5 nm, a tungsten film with a thickness of about 20 nm, and an ITSO film with a thickness of about 10 nm were sequentially formed by sputtering.
  • the titanium nitride film was formed with a nitrogen gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 4000 W, and a pressure of 0.2 Pa.
  • the tungsten film was formed with an argon gas flow rate of 60 sccm, a substrate temperature of 130° C., a source power of 1000 W, and a pressure of 0.4 Pa.
  • the ITSO film was a film containing 5 wt % silicon oxide relative to ITO.
  • the ITSO film was formed with an oxygen gas flow rate of 1.5 sccm, an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film that became the conductive layer 212a was processed using a dry etching method.
  • insulating layer 110a and insulating layer 110b were formed in this order on insulating layer 105 and conductive layer 212a.
  • insulating layer 110a a silicon nitride film having a thickness of about 5 nm was formed by the ALD method.
  • the substrate temperature during the formation of insulating layer 110a was set to 400°C.
  • a first silicon oxide film having a thickness of about 40 nm, a second silicon oxide film having a thickness of about 25 nm, and a silicon nitride film having a thickness of about 90 nm were sequentially formed by a sputtering method using silicon as a target.
  • the first silicon oxide film was formed with an oxygen gas flow rate of 164 sccm, an argon gas flow rate of 41 sccm, a substrate temperature of 200°C, a source power of 1000 W, a pressure of 0.9 Pa, and a bias power of 200 W.
  • the second silicon oxide film was formed with an oxygen gas flow rate of 100 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 200°C, a source power of 3000 W, a pressure of 0.6 Pa, and a bias power of 200 W.
  • the silicon nitride film was formed to a thickness of 20 nm under conditions of a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 30 sccm, a substrate temperature of 200°C, a power supply power of 4000 W, and a pressure of 0.5 Pa, and then formed to a thickness of 70 nm with a bias power of 100 W.
  • the insulating layer 110b was then planarized using the CMP method.
  • an aluminum oxide film with a thickness of about 10 nm was formed on the insulating layer 110b by sputtering using aluminum as a target.
  • the insulating layer 110c was formed to a thickness of 5 nm with an oxygen gas flow rate of 69 sccm, an argon gas flow rate of 14 sccm, a substrate temperature of 200°C, a source power of 5000 W, a pressure of 0.4 Pa, and a bias power of 300 W, and then a bias power of 100 W was used to form a thickness of 5 nm.
  • the aluminum oxide film was then removed using CMP.
  • insulating layer 110c was formed on insulating layer 110b.
  • a silicon nitride film with a thickness of about 10 nm was formed as insulating layer 110c by sputtering using silicon as a target.
  • Insulating layer 110c was formed with a nitrogen gas flow rate of 20 sccm, an argon gas flow rate of 5 sccm, a substrate temperature of room temperature, a source power of 1500 W, and a pressure of 0.2 Pa.
  • an ITSO film with a thickness of about 20 nm was formed as the conductive film 112f on the insulating layer 110c by sputtering.
  • the ITSO film was a film containing 5 wt% silicon oxide relative to ITO.
  • the conductive film 112f was formed with an oxygen gas flow rate of 1.5 sccm, an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film 112f, the insulating layer 110c, the insulating layer 110b, and a part of the insulating layer 110a were removed by dry etching.
  • an opening 243 overlapping with the conductive layer 212a was formed in the conductive film 112f.
  • an opening 141 overlapping with the conductive layer 103 and reaching the insulating layer 105, and an opening 241 overlapping with the opening 243 and reaching the conductive layer 212a were formed in the insulating layers 110c, 110b, and 110a.
  • the opening 141 was designed to be a circle with a diameter of 350 nm in a plan view, and the openings 241 and 243 were designed to be a circle with a diameter of 160 nm in a plan view.
  • the conductive film 112f was processed by dry etching to form the conductive layers 112a, 112b, and 212b.
  • the semiconductor film 108f shown in FIG. 41A was formed on the conductive layer 112a, the conductive layer 112b, the conductive layer 212a, the conductive layer 212b, the insulating layer 105, and the insulating layer 110c.
  • a first metal oxide film having a thickness of about 2 nm and a second metal oxide film having a thickness of about 5 nm on the first metal oxide film were formed in that order.
  • the first metal oxide film was formed with an oxygen gas flow rate of 90 sccm, an argon gas flow rate of 10 sccm, and a substrate temperature of 250°C.
  • the second metal oxide film was formed using ozone as an oxidizing agent, with one cycle lasting 60 seconds.
  • the semiconductor film 108f was then processed by dry etching to form a two-layer stacked metal oxide layer as the semiconductor layer 108 and the semiconductor layer 208.
  • the insulating layer 106 was formed on the semiconductor layer 108, the semiconductor layer 208, the conductive layer 112a, the conductive layer 112b, the conductive layer 212b, and the insulating layer 110c.
  • an aluminum oxide film having a thickness of about 1 nm, a silicon oxide film having a thickness of about 10 nm, a hafnium oxide film having a thickness of about 2 nm, and a silicon nitride film having a thickness of about 3 nm were sequentially formed by the ALD method.
  • the aluminum oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 300°C.
  • the silicon oxide film was formed using an organic precursor at a pressure of 400 Pa, a power supply power of 100 W, and a temperature of 350°C.
  • the hafnium oxide film was formed using ozone as an oxidizing agent at a substrate temperature of 250°C.
  • the silicon nitride film was formed at a substrate temperature of 400°C.
  • a conductive film to become the conductive layer 104 and the conductive layer 204 was formed on the insulating layer 106 and processed to form the conductive layer 104 and the conductive layer 204.
  • a titanium nitride film with a thickness of about 5 nm and a tungsten film with a thickness of about 20 nm were formed in this order by a CVD method.
  • the titanium nitride film and the tungsten film were formed at a substrate temperature of 400°C.
  • the formed conductive film to become the conductive layer 104 and the conductive layer 204 was processed by a dry etching method. In this manner, the transistor 100 and the transistor 200 were formed.
  • an insulating layer 109 was formed so as to cover the transistor 200.
  • a silicon nitride film having a thickness of about 5 nm was formed as the insulating layer 109 by a sputtering method.
  • the insulating layer 109 was formed with a nitrogen gas flow rate of 85 sccm, an argon gas flow rate of 25 sccm, a substrate temperature of 200°C, a source power of 1000 W, and a pressure of 0.5 Pa.
  • an insulating layer 119 for example, as shown in FIG. 48, was formed on the insulating layer 109.
  • the insulating layer 119 was formed under the same conditions as the insulating layer 110b.
  • the insulating layer 119 was planarized by using the CMP method so that the thickness of the insulating layer 119 on the conductive layer 104 and the conductive layer 204 was 40 nm.
  • insulating layer 119, insulating layer 109, and insulating layer 106 were removed by dry etching to form an opening.
  • a titanium nitride film with a thickness of about 5 nm was deposited by CVD at a substrate temperature of 400° C. as a conductive film to become conductive layer 374a so as to cover the opening.
  • a tungsten film with a thickness of about 150 nm was deposited by CVD at a substrate temperature of 400° C. as a conductive film to become conductive layer 374b on the conductive film to become conductive layer 374a.
  • the conductive film that will become conductive layer 374b and the conductive film that will become conductive layer 374a are removed by CMP until the top surface of insulating layer 119 is exposed, forming conductive layer 374a along the side of the opening and conductive layer 374b that fills the opening. This forms plug 374.
  • a conductive film that becomes conductive layer 341 was formed on plug 374 and insulating layer 119 and processed to form conductive layer 341.
  • a tungsten film with a thickness of about 50 nm was formed as the conductive film that becomes conductive layer 341 by sputtering under conditions of an argon gas flow rate of 60 sccm, a substrate temperature of 230° C., a source power of 1000 W, and a pressure of 0.4 Pa.
  • the conductive film that became conductive layer 341 was processed using a dry etching method.
  • an aluminum oxide film with a thickness of about 14 nm was formed as an insulating layer 343 on the conductive layer 341 by the ALD method, and then a silicon oxynitride film with a thickness of about 7 nm was formed by the CVD method.
  • the aluminum oxide film was formed at a substrate temperature of 300°C, and the silicon oxynitride film was formed at a substrate temperature of 350°C.
  • a conductive film that becomes conductive layer 345 was deposited on insulating layer 343 and processed to form conductive layer 345.
  • a tungsten film with a thickness of about 30 nm was formed as the conductive film that becomes conductive layer 345 by sputtering under the same conditions as the conductive film that becomes conductive layer 341.
  • the deposited conductive film that becomes conductive layer 345 was processed by dry etching. In this manner, capacitor 340 was formed.
  • insulating layer 355a, insulating layer 355b, and insulating layer 355c were formed in this order on capacitor 340. Then, insulating layer 355c, insulating layer 355b, insulating layer 355a, and part of insulating layer 343 were removed to form an opening reaching conductive layer 341. Then, a titanium nitride film with a thickness of about 10 nm was formed by CVD at a substrate temperature of 340° C. to cover the opening as a conductive film to become plug 356. In addition, a tungsten film with a thickness of about 150 nm was formed by CVD at a substrate temperature of 345° C. on the titanium nitride film. Then, the conductive film to become plug 356 was removed by CMP until the upper surface of insulating layer 355c was exposed, thereby forming plug 356.
  • a conductive film that will become pixel electrodes 411R, 411G, and 411B was formed on plug 356 and insulating layer 355c, and processed to form pixel electrodes 411R, 411G, and 411B.
  • a first titanium film with a thickness of about 50 nm, an aluminum film with a thickness of about 70 nm, a second titanium film with a thickness of about 6 nm, and an ITSO film with a thickness of about 10 nm were formed in this order by sputtering.
  • the ITSO film was a film containing 5 wt% silicon oxide relative to ITO.
  • the first titanium film was formed under the conditions of an argon gas flow rate of 20 sccm, a substrate temperature of room temperature, a source power of 12000 W, and a pressure of 0.1 Pa.
  • the aluminum film was formed under the conditions of an argon gas flow rate of 50 sccm, a substrate temperature of room temperature, a source power of 4000 W, and a pressure of 0.4 Pa.
  • the second titanium film was formed under the conditions of an argon gas flow rate of 20 sccm, a substrate temperature of room temperature, a source power of 1000 W, and a pressure of 0.1 Pa.
  • the ITSO film was formed under the same conditions as the conductive film 112f.
  • the ITSO film was processed using a wet etching method, and the second titanium film, the aluminum film, and the first titanium film were processed using a dry etching method.
  • an organic layer 412B having a thickness of about 176 nm was formed on the pixel electrode 411B, an organic layer 412G having a thickness of about 85 nm was formed on the pixel electrode 411G, and an organic layer 412R having a thickness of about 115 nm was formed on the pixel electrode 411R in this order by photolithography without using a fine metal mask. After that, an insulating layer 425 and a resin layer 426 were formed.
  • a common layer 414 having a thickness of about 1.5 nm was formed on the organic layers 412R, 412G, and 412B, and on the resin layer 426. Then, an alloy film having a thickness of about 25 nm and a volume ratio of silver to magnesium of 1:0.1 was formed as the common electrode 413 on the common layer 414. In this manner, the light-emitting elements 60R, 60G, and 60B were formed. Then, ITO having a thickness of about 70 nm was formed as the protective layer 421 on the common electrode 413. In this manner, a display device was produced.
  • the Id-Vg and Id-Vd characteristics of the transistor 100A and the transistor 200 included in the manufactured display device were measured. Specifically, the Id-Vg and Id-Vd characteristics of the transistor Tr2 shown in FIG. 27 as the transistor 100A were measured, and the Id-Vg and Id-Vd characteristics of the transistor Tr3 shown in FIG. 27 as the transistor 200 were measured.
  • Figure 61A shows the measurement results of the Id-Vg characteristics of the transistor 100A.
  • Figure 61B shows the measurement results of the Id-Vg characteristics of the transistor 200.
  • the vertical axis represents the drain current Id [A]
  • the horizontal axis represents the gate voltage Vg [V].
  • the voltage (gate voltage Vg) applied to the gate electrode was changed in 0.1 V increments from -4 V to 4 V.
  • the voltage (source voltage) applied to the source electrode was set to 0 V
  • the voltage (drain voltage Vd) applied to the drain electrode was set to 0.1 V and 1.2 V.
  • Figure 62A shows the measurement results of the Id-Vd characteristics of transistor 100A.
  • Figure 62B shows the measurement results of the Id-Vd characteristics of transistor 200.
  • the vertical axis represents drain current Id [A] and the horizontal axis represents drain voltage Vd [V].
  • the measurement conditions for the Id-Vg characteristics of transistors 100A and 200 were as follows: the voltage applied to the drain electrode (drain voltage Vd) was changed from 0.0 V to 5.0 V in 0.1 V increments. The voltage applied to the source electrode (source voltage) was set to 0 V, and the voltage applied to the gate electrode (gate voltage Vg) was set to 0.5 V, 1.0 V, 1.5 V, and 2.0 V.
  • the transistor 100A has high saturation and can be suitably used as the transistor Tr2 that functions as a drive transistor.
  • the transistor 200 has a large drain current Id and can be suitably used as the transistor Tr1 that functions as a switch, and the transistors Tr3 to Tr7.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009135380A (ja) * 2007-05-30 2009-06-18 Canon Inc 酸化物半導体を用いた薄膜トランジスタの製造方法および表示装置
JP2011171581A (ja) * 2010-02-19 2011-09-01 Kobe Steel Ltd 薄膜トランジスタ基板および表示デバイス
JP2014232867A (ja) * 2013-04-29 2014-12-11 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2017139276A (ja) * 2016-02-02 2017-08-10 株式会社ジャパンディスプレイ 半導体装置
JP2021019197A (ja) * 2019-07-19 2021-02-15 株式会社半導体エネルギー研究所 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009135380A (ja) * 2007-05-30 2009-06-18 Canon Inc 酸化物半導体を用いた薄膜トランジスタの製造方法および表示装置
JP2011171581A (ja) * 2010-02-19 2011-09-01 Kobe Steel Ltd 薄膜トランジスタ基板および表示デバイス
JP2014232867A (ja) * 2013-04-29 2014-12-11 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2017139276A (ja) * 2016-02-02 2017-08-10 株式会社ジャパンディスプレイ 半導体装置
JP2021019197A (ja) * 2019-07-19 2021-02-15 株式会社半導体エネルギー研究所 半導体装置

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