WO2024148643A1 - 存储器及其测试方法、存储器系统 - Google Patents

存储器及其测试方法、存储器系统 Download PDF

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Publication number
WO2024148643A1
WO2024148643A1 PCT/CN2023/072856 CN2023072856W WO2024148643A1 WO 2024148643 A1 WO2024148643 A1 WO 2024148643A1 CN 2023072856 W CN2023072856 W CN 2023072856W WO 2024148643 A1 WO2024148643 A1 WO 2024148643A1
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Prior art keywords
data
storage module
ecc
test
write
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English (en)
French (fr)
Inventor
陆天辰
程彪
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check

Definitions

  • the present disclosure is based on Chinese patent application with application number 202310025504.8, application date January 9, 2023, and invention name “Memory and testing method thereof, memory system”, and claims the priority of the Chinese patent application.
  • the entire contents of the Chinese patent application are hereby introduced into the present disclosure as a reference.
  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a memory and a testing method thereof, and a memory system.
  • Memory is an important component for storing data in various electronic devices. With the development of integrated circuit technology, the precision and complexity of memory are increasing. Various applications have also put forward higher and higher requirements on the performance of memory to meet the needs of various application scenarios.
  • a method for testing a memory wherein the memory includes a main storage module and an ECC storage module, and the method includes:
  • first test data is used to determine whether the read and write functions of the ECC storage module and the main storage module are normal
  • second test data is used to determine whether the read and write functions of the main storage module are normal
  • test mode signal In response to a test mode signal, writing the first test data or the second test data as ECC check data into the ECC storage module; the test mode signal is used to indicate execution of the first test mode or the second test mode;
  • the number of bits of the first write data is M
  • the number of bits of the first test data is 2M
  • the first M bits and the last M bits of the first test data are the same
  • M is an even number greater than or equal to 2.
  • the number of bits of the second test data is 2M
  • the number of bits of the second write data is The number is 2N
  • M is an even number greater than or equal to 2
  • N is an even number greater than M.
  • the method further comprises:
  • the method further includes:
  • the third write data or the second write data stored in the main storage module is read.
  • the number of bits of the third written data is the same as the number of bits of the second written data, and the first N bits and the last N bits of the third written data are the same.
  • receiving the third write data in the first test mode includes:
  • the number of bits of data transmitted by each data pad is 2Z, the first Z bits and the last Z bits of data transmitted by each data pad are the same, and Z is an even number greater than or equal to 2.
  • the judging based on the ECC check data includes:
  • Whether the read and write functions of the ECC storage module are normal is determined based on the compression-processed data output from the data pad.
  • the judging based on the ECC check data further includes:
  • the ECC check data is the second test data, it is determined whether the read and write functions of the main storage module are normal based on the read ECC check data stored in the ECC storage module and the second write data stored in the main storage module.
  • a memory including:
  • Main storage module and ECC storage module are Main storage module and ECC storage module
  • a data input/output unit configured to receive first write data in a first test mode, or to receive second write data in a second test mode
  • a first processing unit is configured to copy and expand the first written data to obtain first test data
  • a second processing unit configured to calculate the second write data using an ECC algorithm to obtain second test data; wherein the first test data is used to determine whether the read and write functions of the ECC storage module and the main storage module are normal, and the second test data is used to determine whether the read and write functions of the main storage module are normal;
  • a writing unit connected to the first processing unit and the second processing unit, and configured to write the first test data or the second test data as ECC check data into the ECC storage module in response to a test mode signal;
  • the test mode signal is used to indicate the execution of the first test data or the second test data as ECC check data; a first test mode or a second test mode;
  • the reading unit is configured to read the ECC check data stored in the ECC storage module.
  • the number of bits of the first write data is M
  • the number of bits of the first test data is 2M
  • the first M bits and the last M bits of the first test data are the same
  • M is an even number greater than or equal to 2.
  • the number of bits of the second test data is 2M
  • the number of bits of the second write data is 2N
  • M is an even number greater than or equal to 2
  • N is an even number greater than M.
  • the data input/output unit is further configured to receive third write data in the first test mode; the write unit is further configured to write the third write data or the second write data into the main storage module in response to the test mode signal;
  • the reading unit is further configured to read the third write data or the second write data stored in the main storage module while reading the ECC check data stored in the ECC storage module.
  • the number of bits of the third written data is the same as the number of bits of the second written data, and the first N bits and the last N bits of the third written data are the same.
  • the memory also includes multiple data pads, each of which is configured to receive third write data in the first test mode; the number of bits of data transmitted by each data pad is 2Z, the first Z bits and the last Z bits of the data transmitted by each data pad are the same, and Z is an even number greater than or equal to 2.
  • the memory further includes: a compression unit;
  • the compression unit is connected to the reading unit and is configured to compress the third write data stored in the main storage module and the ECC verification data stored in the ECC storage module and output the compressed data to the data pad when the ECC verification data is the first test data.
  • the memory also includes: a signal generating unit, configured to perform logical operations on the test mode signal, the first control signal and the second control signal to generate a first trigger signal; the first control signal is used to indicate the opening or closing of the second processing unit; the second control signal is used to indicate the opening or closing of the compression unit; the first trigger signal is used to instruct the writing unit to write the first test data or the second test data as ECC verification data into the ECC storage module.
  • a signal generating unit configured to perform logical operations on the test mode signal, the first control signal and the second control signal to generate a first trigger signal
  • the first control signal is used to indicate the opening or closing of the second processing unit
  • the second control signal is used to indicate the opening or closing of the compression unit
  • the first trigger signal is used to instruct the writing unit to write the first test data or the second test data as ECC verification data into the ECC storage module.
  • the signal generating unit is specifically configured to generate a first trigger signal indicating that the first test data is written into the ECC storage module when the test mode signal indicates that the first test mode is executed and the first control signal indicates that the second processing unit is turned off and the second control signal indicates that the compression unit is turned on.
  • a memory system characterized in that it includes the memory and a controller as described above; the controller is configured to make judgments based on the ECC check data stored in the ECC storage module.
  • controller is specifically configured as follows:
  • the ECC check data is the first test data, judging whether the read and write functions of the ECC storage module are normal based on the compressed data output from the data pad;
  • ECC check data is the second test data
  • whether the read and write functions of the main storage module are normal is determined based on the read ECC check data stored in the ECC storage module and the second write data stored in the main storage module.
  • the technical solution provided by the embodiment of the present disclosure can flexibly switch between the first test mode and the second test mode according to actual needs during testing.
  • the first write data is copied and extended to obtain the first test data that can directly access the ECC storage module, thereby achieving simultaneous testing of the main storage module and the ECC storage module, thereby improving test efficiency.
  • FIG1 is a block diagram of a memory system according to an embodiment of the present disclosure.
  • FIG2 is a block diagram of a memory according to an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of a circuit structure of a logic operation unit according to an embodiment of the present disclosure
  • FIG4 is a timing diagram showing a signal generating unit generating a first trigger signal according to an embodiment of the present disclosure
  • FIG5 is a partial block diagram of another memory according to an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a circuit structure of a signal generating unit according to an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a circuit structure of a selection unit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic flow chart of a method for testing a memory according to an embodiment of the present disclosure.
  • spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, the spatial relational terms are intended to include use and operation . For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “under” other elements would be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can include both an up and down orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • ECC error checking and correcting technology Due to the limitations of production processes and production conditions, the produced memory is not perfect. In the research and development and manufacturing process of memory, it is often necessary to perform a large number of tests on the memory to determine whether there are abnormalities generated during the manufacturing process.
  • the memory that introduces ECC needs to set up an ECC storage area outside the main storage area for storing write data to store ECC check data. Therefore, when testing the main storage area of the memory, the ECC storage area also needs to be tested to prevent errors in the ECC storage area that stores ECC check data and avoid erroneous error correction.
  • the ECC check data in the ECC storage area is generated by an ECC algorithm.
  • the memory When a read operation is performed on the memory, the memory only outputs the read write data, but does not output the ECC check data.
  • the write data stored in the read storage can only complete the test of the main storage area, and cannot complete the test of the main storage area and the ECC storage area at the same time.
  • the present disclosure proposes the following implementation modes.
  • FIG1 is a block diagram of a memory system according to an embodiment of the present disclosure. As shown in FIG1 , the memory system 10 includes a memory 110 and a controller 120 .
  • the controller 120 may control the overall operation of the memory system 10.
  • the controller 120 may control the overall data exchange between an external host (not shown) and the memory 110.
  • the controller 110 may write data to the memory 110 or read data from the memory 110 in response to a request from the host.
  • the controller 120 may send command and address signals to the memory 110.
  • the memory 110 includes, but is not limited to, a dynamic random access memory (DRAM), a static random access memory (SRAM), a three-dimensional NAND memory, a phase change memory (PCM), an electrically erasable programmable read only memory (EEPROM), a NOR flash memory, a phase change random access memory, and a phase change random access memory.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • PCM phase change memory
  • EEPROM electrically erasable programmable read only memory
  • NOR flash memory a phase change random access memory
  • phase change random access memory Phase Change Random Access Memory
  • PRAM Phase Change Random Access Memory
  • MRAM Magnetic Random Access Memory
  • RRAM Resistive Random Access Memory
  • FRAM Ferro-electric Random Access Memory
  • FIG2 is a block diagram of a memory according to an embodiment of the present disclosure.
  • the memory 110 includes: a storage module 130, the storage module 130 includes a main storage module 132 and an ECC storage module 131; a data input/output unit 112, configured to receive first write data W_data1 in a first test mode, or to receive second write data W_data2 in a second test mode; a first processing unit 113, configured to copy and extend the first write data W_data1 to obtain first test data T_data1; a second processing unit 114, configured to calculate the second write data W_data2 using an ECC algorithm to obtain second test data T_data2; wherein the first test data T_data 1 is used to judge whether the read and write functions of the ECC storage module 131 and the main storage module 132 are normal, and the second test data T_data2 is used to judge whether the read and write functions of the main storage module 132 are normal; the writing unit 115 is connected to the first processing unit 113 and the second processing unit 114,
  • the data input/output unit 112 is further configured to receive the third write data W_data3 in the first test mode; the write unit 115 is further configured to write the third write data W_data3 or the second write data W_data2 into the main storage module 132 in response to the test mode signal T_mode;
  • the reading unit 117 is further configured to read the third write data W_data3 or the second write data W_data2 stored in the main storage module 132 while reading the ECC check data stored in the ECC storage module 131 .
  • the controller may send write data W_data to the memory 110 or receive read data R_data from the memory 110.
  • the write data W_data sent by the controller to the memory 110 includes the first write data W_data1 and the third write data W_data3, and the read data R_data received by the controller 120 from the memory 110 is the compressed data P_data.
  • the write data W_data sent by the controller to the memory 110 is the second write data W_data2
  • the read data R_data received by the controller 120 from the memory 110 is the decoded data D_data obtained after the second processing unit performs ECC error detection and correction.
  • the memory module 130 may be a DRAM memory cell array in which word lines and bit lines are cross-distributed and composed of MOS devices and storage capacitors.
  • the ECC storage module 131 is configured to store ECC check data
  • the main storage module 132 is configured to store write data W_data.
  • the number of bits of the first write data W_data1 is M
  • the first test data The number of bits of the first test data T_data1 is 2M
  • the first M bits and the last M bits of the first test data T_data1 are the same
  • M is an even number greater than or equal to 2.
  • the number of bits of the third written data W_data3 is 2N, the first N bits and the last N bits of the third written data W_data3 are the same, and N is an even number greater than M.
  • the memory 110 has a storage space with a width of 72 bits, wherein the main storage module 132 may be a storage space with a width of 8 ⁇ 8 bits, and the ECC storage module may be a storage space with a width of 8 bits.
  • the memory 110 includes 8 data pads (DQ) 111.
  • DQ data pads
  • the number of bits of the first write data W_data1 is 4, for example, the first write data W_data1 is 1100, and the first write data W_data1 is transmitted through 4 data pads 111, and each of the 4 data pads 111 transmitting the first write data W_data1 transmits 1 bit of data.
  • the first processing unit 113 copies and expands the first write data W_data1 to obtain the first test data T_data1, and the number of bits of the first test data T_data1 is 8, for example, the first test data T_data1 is 11001100, and the first 4 bits and the last 4 bits of the first test data T_data1 are the same.
  • the number of bits of the third write data W_data3 is 64, for example, the third write data W_data3 is 1100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100.
  • the first 32 bits and the last 32 bits of the third write data W_data3 are the same.
  • the memory 110 further includes a plurality of data pads 111 , each of the data pads 111 being configured to receive the third write data W_data3 in the first test mode.
  • the number of bits of the third write data W_data3 is 64, for example, the third write data W_data3 is 11001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100.
  • the memory 110 includes 8 data pads 111, and the number of bits of data transmitted by each data pad 111 is 8. The first 4 bits and the last 4 bits of the data transmitted by each data pad 111 are the same, for example, the data transmitted by each data pad 111 is 11001100.
  • the writing unit 115 is configured to respond to the test mode signal T_mode, write the first test data T_data1 as ECC check data into the ECC storage module 131, and write the third write data W_data3 into the main storage module 132. That is, 11001100 is written into the ECC storage module 131, and the data 11001100 transmitted through each data pad 111 is written into each 8-bit storage space in the main storage module 132.
  • the number of bits of the first test data T_data1 is the same as the bit width of the ECC storage module 131, and the number of bits of the third write data W_data3 is the same as the bit width of the main storage module 132.
  • the bit width of the main storage module and the ECC storage module in the above memory is only an example and can be adjusted according to actual needs in actual applications.
  • the memory has a storage space with a bit width of 136 bits, in which the main storage module can be a storage space with a bit width of 8 ⁇ 16 bits, and the ECC storage module can be a storage space with a bit width of 8 bits.
  • the first write data W_data1 can be 1100, and the first test data T_data1 is 11001100.
  • the third write data W_data3 is 11001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011110011001111001100111100110011110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100.
  • the memory 110 also includes: a compression unit 118; the compression unit 118 is connected to the reading unit 117, and is configured to compress the third write data W_data3 stored in the read main storage module 132 and the ECC verification data stored in the ECC storage module 131 when the ECC verification data is the first test data T_data1, and output the compressed processing data P_data to the data pad 111.
  • a compression unit 118 is connected to the reading unit 117, and is configured to compress the third write data W_data3 stored in the read main storage module 132 and the ECC verification data stored in the ECC storage module 131 when the ECC verification data is the first test data T_data1, and output the compressed processing data P_data to the data pad 111.
  • the controller 120 shown in FIG1 is configured to determine whether the read and write functions of the ECC storage module 131 are normal based on the compressed data P_data output from the data pad 111 when the ECC check data is the first test data T_data1. It should be noted that, when the memory 110 includes 8 data pads 111, only 4 data pads 111 are needed to realize the transmission of the compressed data P_data, which can effectively improve the data transmission rate.
  • the controller 120 receives the compressed data P_data outputted by the memory 110 through the data pad 111, and may decompress the compressed data P_data to compare whether the data read from the main storage module 132 and the ECC storage module 131 are the same as the data written into the main storage module 132 and the ECC storage module 131. If the data read from the main storage module 132 is the same as the data written into the main storage module 132, the read and write functions of the main storage module 132 are normal, and if the data read from the ECC storage module 131 is the same as the data written into the ECC storage module 131, the read and write functions of the ECC storage module 131 are normal.
  • the read and write functions of the main storage module 132 and the ECC storage module 131 are both normal.
  • the data read from the main storage module 132 is different from the data written into the main storage module 132, or the data read from the ECC storage module 131 is different from the data written into the ECC storage module 131, then it can be determined whether the read and write functions of the main storage module 132 or the ECC storage module 131 are normal based on the corresponding comparison results.
  • the data read from the main storage module 132 and the ECC storage module 131 may not be compressed normally.
  • the data read from the ECC storage module 131 may have errors such as bit flipping, for example, the first test data 11001100 changes to 11011100, and the data read from the main storage module 132 and the ECC storage module 131 cannot be compressed normally.
  • the controller 120 when the controller 120 sends a read command to the memory 110 in the first test mode, but does not receive the correct compressed data P_data within a predetermined time, the controller 120 can determine that the read and write functions of the storage module 130 are abnormal, and can determine the specific abnormal area through further testing.
  • the memory 110 further includes: a signal generating unit 116, configured to A logical operation is performed on the test mode signal T_mode, the first control signal Ctrl_1 and the second control signal Ctrl_2 to generate a first trigger signal Signal_1; the first control signal Ctrl_1 is used to indicate whether the second processing unit 114 is turned on or off; the second control signal Ctrl_2 is used to indicate whether the compression unit 118 is turned on or off; the first trigger signal Signal_1 is used to instruct the write unit 115 to write the first test data T_data1 or the second test data T_data2 as ECC check data into the ECC storage module 131.
  • a signal generating unit 116 configured to A logical operation is performed on the test mode signal T_mode, the first control signal Ctrl_1 and the second control signal Ctrl_2 to generate a first trigger signal Signal_1
  • the first control signal Ctrl_1 is used to indicate whether the second processing unit 114 is turned on or off
  • the signal generating unit 116 is specifically configured to generate a first trigger signal Signal_1 indicating that the first test data T_data1 is written into the ECC storage module 131 when the test mode signal T_mode indicates that the first test mode is executed, the first control signal Ctrl_1 indicates that the second processing unit is turned off, and the second control signal Ctrl_2 indicates that the compression unit 118 is turned on.
  • the signal generating unit 116 includes a logic operation unit 140 as shown in FIG3
  • the logic operation unit 140 includes a first logic NOR gate 141 and a second logic NOR gate 142
  • the first logic NOR gate 141 is used to receive the first control signal Ctrl_1 and the second control signal Ctrl_2, and output the third control signal Ctrl_3.
  • the output end of the first logic NOR gate 141 is connected to the input end of the second logic NOR gate 142
  • the second logic NOR gate 142 is used to receive the test mode signal T_mode and the third control signal Ctrl_3, and output the first trigger signal Signal_1.
  • FIG4 is a timing diagram of a signal generating unit according to an embodiment of the present disclosure generating a first trigger signal.
  • Table 1 shows logic level values of various signals corresponding to FIG4 in different test modes.
  • the test mode signal T_mode is at a logic low level to indicate that the first test mode is executed and the first processing unit 113 is turned on
  • the first control signal Ctrl_1 is at a logic low level to indicate that the second processing unit 114 is turned off
  • the second control signal Ctrl_2 is at a logic high level to indicate that the compression unit 118 is turned on.
  • the first trigger signal Signal_1 at a logic high level is generated, indicating that the write unit 115 writes the first test data T_data1 as the ECC check data ECC_data into the ECC storage module 131.
  • the test mode signal T_mode is at a logic high level to indicate that the second test mode is executed and the first processing unit 113 is turned off
  • the first control signal Ctrl_1 is at a logic high level to indicate that the second processing unit 114 is turned on
  • the second control signal Ctrl_2 is at a logic low level to indicate that the compression unit 118 is turned off.
  • the first trigger signal Signal_1 at a logic low level is generated, indicating that the write unit 115 writes the second test data T_data2 as the ECC check data ECC_data into the ECC storage module 131.
  • a selection unit 150 may be provided between the writing unit 115 and the signal generating unit 116.
  • the selection unit 150 is also connected to the first processing unit 113 and the second processing unit 114.
  • the signal generating unit 116 further includes an inverter 143.
  • a logical negation operation is performed on the first trigger signal Signal_1 to generate the second trigger signal Signal_2.
  • the selection unit 150 includes a first area 151 and a second area 152.
  • the first area 151 is connected to the first input terminal for receiving the first test data T_data1
  • the second area 152 is connected to the second input terminal for receiving the second test data T_data2.
  • the test mode signal T_mode is at a logic low level to indicate that the first test mode is executed and the first processing unit 113 is turned on
  • the first control signal Ctrl_1 is at a logic low level to indicate that the second processing unit 114 is turned off
  • the second control signal Ctrl_2 is at a logic high level to indicate that the compression unit 118 is turned on.
  • a first trigger signal Signal_1 at a logic high level is generated, and the inverter 143 performs a logic negation operation on the first trigger signal Signal_1 to generate a second trigger signal Signal_2.
  • the transistors in the first area 151 connected to the first trigger signal Signal_1 and the second trigger signal Signal_2 are turned on, and the transistors in the second area 152 connected to the first trigger signal Signal_1 and the second trigger signal Signal_2 are turned off.
  • the first test data T_data1 can be output to the write unit 115 through the selection unit 150 and written into the ECC storage module 131 as the ECC check data ECC_data.
  • the test mode signal T_mode is at a logic high level to indicate that the second test mode is executed and the first processing unit 113 is turned off
  • the first control signal Ctrl_1 is at a logic high level to indicate that the second processing unit 114 is turned on
  • the second control signal Ctrl_2 is at a logic low level to indicate that the compression unit 118 is turned off.
  • the first trigger signal Signal_1 at a logic low level is generated, and the first trigger signal Signal_1 is logically negated by the inverter 143 to generate the second trigger signal Signal_2.
  • the transistors connected to the first trigger signal Signal_1 and the second trigger signal Signal_2 in the first area 151 are turned off, and the transistors connected to the first trigger signal Signal_1 and the second trigger signal Signal_2 in the second area 152 are turned on, and the second test data T_data2 can be output to the write unit 115 through the selection unit 150 and written into the ECC storage module 131 as the ECC check data ECC_data.
  • the number of bits of the second test data T_data2 is 2M
  • the number of bits of the second write data W_data2 is 2N
  • M is an even number greater than or equal to 2
  • N is an even number greater than M.
  • the memory 110 has a storage space with a width of 72 bits, wherein the main storage module 132 may be a storage space with a width of 8 ⁇ 8 bits, and the ECC storage module may be a storage space with a width of 8 bits.
  • the number of bits of the second write data W_data2 is 64, and the second processing unit 114 calculates the second write data W_data2 using the ECC algorithm to obtain the second test data T_data2, and the number of bits of the second test data T_data2 is 8.
  • the second processing unit 114 may be an ECC engine.
  • the ECC engine uses the ECC algorithm in the second test mode to calculate (or encode) the second write data W_data2 sent by the controller 120 to the memory 10 to obtain the second test data T_data2 having a bit number of 8.
  • the ECC engine may perform encoding in various ways. For example, the ECC engine may perform encoding based on, but not limited to, AN code, BCH code, Hamming code, polar code, Turbo code, etc.
  • the number of bits of the second test data T_data2 is related to the second write data W_data2 and the ECC algorithm.
  • the number of bits of the second test data T_data2 obtained by the ECC algorithm selected here is 8.
  • the bit width of the second write data W_data2 is the same as the bit width of the main storage module 132 .
  • the write unit 115 is configured to write the second test data T_data2 as ECC check data into the ECC storage module 131 and write the second write data W_data2 into the main storage module 132 in response to the test mode signal T_mode.
  • the controller 120 shown in FIG1 is configured to be configured to make a judgment based on the ECC check data stored in the ECC storage module 131.
  • the ECC check data is the second test data T_data2
  • the reading unit 117 is connected to the second processing unit 114, and in the second test mode, the reading unit 117 outputs the data read from the main storage module 132 and the ECC storage module 131 to the second processing unit 114.
  • the second processing unit 114 may be an ECC engine, which may perform various functions and operations associated with error correction decoding, for example, the ECC engine may generate an ECC syndrome, generate an ECC error position, correct an ECC error, and may also generate an ECC error detection flag.
  • the second processing unit 114 decodes the data read from the main storage module 132 and the ECC storage module 131 to obtain decoded data D_data, and the decoding process specifically includes performing ECC check on the data read from the main storage module 132 and the ECC storage module 131 to obtain a syndrome, which can be used for error detection and error correction.
  • the syndrome includes the number of bit errors in the data read from the main storage module 132.
  • the decoded data D_data obtained by the second processing unit 114 is the second write data W_data2, that is, the read data R_data received by the controller 120 from the memory via the data pad 111 is the second write data W_data2, and the controller 120 will determine that the read and write functions of the main storage module 132 are normal.
  • the second processing unit 114 when the number of bit errors is less than or equal to a threshold value, such as a single bit error, the second processing unit 114 corrects the data with bit errors in the data read from the main storage module 132 to obtain decoded data D_data, and outputs the decoded data D_data to the data input/output unit 112, and then outputs it to the controller 120 via the data pad 111.
  • a threshold value such as a single bit error
  • the number of bit errors when the number of bit errors is greater than a threshold, such as a double-bit error, it means that the bit errors existing in the data read from the main storage module 132 have exceeded the error correction capability of the second processing unit 114. At this time, the data stored in the read main storage module 132 cannot be corrected, and a signal will be sent to the controller 120 to indicate that the memory 10 has multi-bit errors that cannot be corrected by ECC. The controller 120 will determine that the read and write functions of the main storage module 132 are abnormal.
  • a threshold such as a double-bit error
  • the memory can flexibly switch the first test according to actual needs during testing.
  • the first test mode and the second test mode are used to obtain the first test data that can directly access the ECC storage module by introducing the first processing unit, so that the main storage module and the ECC storage module can be tested at the same time, thereby improving the test efficiency.
  • possible abnormalities of the ECC storage module can be discovered in time, error correction can be avoided, and the reliability of the data transmission process can be improved.
  • FIG8 is a flow chart of a memory test method provided by an embodiment of the present disclosure, wherein the memory includes a main storage module and an ECC storage module.
  • the test method will be described below in conjunction with FIG1 to FIG2, FIG4 and FIG8.
  • the memory test method specifically includes the following steps:
  • Step S10 receiving first write data in a first test mode, and copying and extending the first write data to obtain first test data, or receiving second write data in a second test mode, and calculating the second write data using an ECC algorithm to obtain second test data; wherein the first test data is used to determine whether the read and write functions of the ECC storage module and the main storage module are normal, and the second test data is used to determine whether the read and write functions of the main storage module are normal;
  • Step S20 In response to a test mode signal, writing the first test data or the second test data as ECC check data into the ECC storage module; the test mode signal is used to indicate the execution of the first test mode or the second test mode;
  • Step S30 reading the ECC check data stored in the ECC storage module, and making a judgment based on the ECC check data.
  • a first test mode is executed and the first processing unit 113 is turned on, in response to a first control signal Ctrl_1 at a low logic level, the second processing unit 114 is turned off, and in response to a second control signal Ctrl_2 at a logic high level, the compression unit 118 is turned on.
  • first write data W_data1 is received, and the first write data W_data1 is copied and extended to obtain first test data T_data1.
  • the number of bits of the first write data W_data1 is M
  • the number of bits of the first test data T_data1 is 2M
  • the first M bits and the last M bits of the first test data T_data1 are the same
  • M is an even number greater than or equal to 2.
  • the main storage module 132 can be 8 pieces of storage space with a width of 8 bits, and the ECC storage module can be 1 piece of storage space with a width of 8 bits.
  • the memory 110 includes 8 data pads 111.
  • the number of bits of the first write data W_data1 is 4.
  • the first write data W_data1 is 1100. Only 4 data pads 111 are needed to realize the transmission of the first write data W_data1, and each of the 4 data pads 111 that transmit the first write data W_data1 transmits 1 bit of data.
  • the first processing unit 113 copies and expands the first write data W_data1 to obtain the first test data T_data1.
  • the number of bits of the first test data T_data1 is 8.
  • the first test data T_data1 is 11001100, and the first 4 bits and the last 4 bits of the first test data T_data1 are the same.
  • the above-mentioned testing method further includes:
  • the number of bits of the third written data W_data3 is 2N, the first N bits and the last N bits of the third written data W_data3 are the same, and N is an even number greater than M.
  • the number of bits of the third write data W_data3 is 64, for example, the third write data W_data3 is 1100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100.
  • the first 32 bits and the last 32 bits of the third write data W_data3 are the same.
  • receiving third write data in the first test mode includes:
  • the number of bits of data transmitted by each data pad is 2Z, the first Z bits and the last Z bits of data transmitted by each data pad are the same, and Z is an even number greater than or equal to 2.
  • the number of bits of the third write data W_data3 is 64, for example, the third write data W_data3 is 11001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100.
  • the memory 110 includes 8 data pads 111, and the number of bits of data transmitted by each data pad 111 is 8. The first 4 bits and the last 4 bits of the data transmitted by each data pad 111 are the same, for example, the data transmitted by each data pad 111 is 11001100.
  • a logic operation is performed on the test mode signal T_mode, the first control signal Ctrl_1 and the second control signal Ctrl_2 to generate a first trigger signal Signal_1 at a logic high level.
  • the first test data T_data1 is written into the ECC storage module 131, and the third write data W_data3 is written into the main storage module 132.
  • the ECC check data stored in the ECC storage module 131 and the third write data W_data3 stored in the main storage module 132 are read.
  • the ECC check data is the first test data T_data1.
  • the third write data stored in the read main storage module and the ECC check data stored in the ECC storage module are compressed and the compressed data P_data is output to the data pad 111.
  • Whether the read and write functions of the ECC storage module 131 are normal is determined based on the compressed data P_data output from the data pad 111.
  • the controller 120 receives the compressed data P_data output by the memory 110 through the data pad 111, and can decompress the compressed data P_data to compare whether the data read from the main storage module 132 and the ECC storage module 131 are the same as the data written into the main storage module 132 and the ECC storage module 131.
  • the read and write functions of the main storage module 132 are normal, and if the data read from the ECC storage module 131 is the same as the data written into the ECC storage module 131, the read and write functions of the ECC storage module 131 are normal. That is, when the data read from the main storage module 132 is the third write data W_data3 and the data read from the ECC storage module 131 is the first test data T_data1, the read and write functions of the main storage module 132 and the ECC storage module 131 are normal.
  • the data read from the main storage module 132 is different from the data written into the main storage module 132, or the data read from the ECC storage module 131 is different from the data written into the ECC storage module 131, then it can be determined whether the read and write functions of the main storage module 132 or the ECC storage module 131 are normal based on the corresponding comparison results.
  • the data read from the main storage module 132 and the ECC storage module 131 may not be compressed normally.
  • the data read from the ECC storage module 131 may have errors such as bit flipping, for example, from 11001100 to 11011100, and the data read from the main storage module 132 and the ECC storage module 131 cannot be compressed normally.
  • the controller 120 when the controller 120 sends a read command to the memory 110 in the first test mode, but does not receive the correct compressed data P_data within a predetermined time, the controller 120 can determine that the read and write functions of the storage module 130 are abnormal, and can determine the specific abnormal area through further testing.
  • a second test mode is executed and the first processing unit 113 is turned off, in response to a first control signal Ctrl_1 at a high logic level, the second processing unit 114 is turned on, and in response to a second control signal Ctrl_2 at a logic low level, the compression unit 118 is turned off.
  • the second write data W_data12 is received, and the second write data W_data1 is calculated using an ECC algorithm to obtain the second test data T_data2.
  • the number of bits of the second test data T_data2 is 2M
  • the number of bits of the second write data W_data2 is 2N
  • M is an even number greater than or equal to 2
  • N is an even number greater than M.
  • the main storage module 132 may be a storage space with a width of 8 ⁇ 8 bits
  • the ECC storage module may be a storage space with a width of 8 bits.
  • the number of bits of the second write data W_data2 is 64
  • the second processing unit 114 calculates the second write data W_data2 using the ECC algorithm to obtain the second test data T_data2, and the number of bits of the second test data T_data2 is 8.
  • a logic operation is performed on the test mode signal T_mode, the first control signal Ctrl_1 and the second control signal Ctrl_2 to generate a first trigger signal Signal_1 at a logic low level.
  • the second test data T_data2 is written into the ECC storage module 131, and the second write data W_data2 is written into the main storage module 132.
  • the ECC check data stored in the ECC storage module 131 and the second write data W_data2 stored in the main storage module 132 are read.
  • the judgment is made based on the ECC verification data read from the ECC storage module 131. Specifically, in the second test mode, the ECC verification data is the second test data T_data2. Based on the ECC verification data stored in the read ECC storage module and the second write data W_data2 stored in the main storage module, it is judged whether the read and write functions of the main storage module are normal.
  • the second processing unit 114 decodes the data read from the main storage module 132 and the ECC storage module 131 to obtain decoded data D_data, and the decoding process specifically includes performing ECC check on the data read from the main storage module 132 and the ECC storage module 131 to obtain a syndrome, which can be used for error detection and error correction.
  • the syndrome includes the number of bit errors in the data read from the main storage module 132.
  • the decoded data D_data obtained by the second processing unit 114 is the second write data W_data2, that is, the read data R_data received by the controller 120 from the memory via the data pad 111 is the second write data W_data2, and the controller 120 will determine that the read and write functions of the main storage module 132 are normal.
  • the second processing unit 114 when the number of bit errors is less than or equal to a threshold value, such as a single bit error, the second processing unit 114 corrects the data with bit errors in the data read from the main storage module 132 to obtain decoded data D_data, and outputs the decoded data D_data to the data input/output unit 112, and then outputs it to the controller 120 via the data pad 111.
  • a threshold value such as a single bit error
  • the number of bit errors when the number of bit errors is greater than a threshold, such as a double-bit error, it means that the bit errors existing in the data read from the main storage module 132 have exceeded the error correction capability of the second processing unit 114. At this time, the data stored in the read main storage module 132 cannot be corrected, and a signal will be sent to the controller 120 to indicate that the memory 10 has multi-bit errors that cannot be corrected by ECC. The controller 120 will determine that the read and write functions of the main storage module 132 are abnormal.
  • a threshold such as a double-bit error
  • the memory test method provided in the embodiment of the present disclosure can flexibly switch between the first test mode and the second test mode according to actual needs during the test, and obtains the first test data that can directly access the ECC storage module by introducing the first processing unit, so that the main storage module and the ECC storage module can be tested at the same time, thereby improving the test efficiency.
  • possible abnormalities of the ECC storage module can be discovered in time, error correction can be avoided, and the reliability of the data transmission process can be improved.
  • the technical solution provided by the embodiment of the present disclosure can flexibly switch between the first test mode and the second test mode according to actual needs during testing.
  • the first write data is copied and extended to obtain the first test data that can directly access the ECC storage module, thereby achieving simultaneous testing of the main storage module and the ECC storage module, thereby improving test efficiency.

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Abstract

本公开实施例提供了一种存储器的测试方法，该存储器包括主存储模块以及ECC存储模块，该方法包括：在第一测试模式下接收第一写入数据，对第一写入数据进行复制扩展得到第一测试数据，或者，在第二测试模式下接收第二写入数据，利用ECC算法对第二写入数据进行计算得到第二测试数据；其中，第一测试数据用于判断ECC存储模块和主存储模块的读写功能是否正常，第二测试数据用于判断主存储模块的读写功能是否正常；响应于测试模式信号，将第一测试数据或者第二测试数据作为ECC校验数据写入ECC存储模块；测试模式信号用于指示执行第一测试模式或者第二测试模式；读取ECC存储模块中存储的ECC校验数据，基于ECC校验数据进行判断。

Description

存储器及其测试方法、存储器系统
相关申请的交叉引用
本公开基于申请号为202310025504.8、申请日为2023年01月09日、发明名称为“存储器及其测试方法、存储器系统”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，涉及但不限于一种存储器及其测试方法、存储器系统。
背景技术
存储器是各种电子设备中用于存储数据的重要部件，随着集成电路技术的发展，存储器的精密程度和复杂程度日益提高。各种不同的应用对存储器的性能也提出了越来越高的要求，以满足各种不同应用场景的需求。
发明内容
根据本公开实施例的第一方面，提供了一种存储器的测试方法，所述存储器包括主存储模块以及ECC存储模块，所述方法包括：
在第一测试模式下接收第一写入数据，对所述第一写入数据进行复制扩展得到第一测试数据，或者，在第二测试模式下接收第二写入数据，利用ECC算法对所述第二写入数据进行计算得到第二测试数据；其中，所述第一测试数据用于判断所述ECC存储模块和所述主存储模块的读写功能是否正常，所述第二测试数据用于判断所述主存储模块的读写功能是否正常；
响应于测试模式信号，将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块；所述测试模式信号用于指示执行第一测试模式或者第二测试模式；
读取所述ECC存储模块中存储的ECC校验数据，基于所述ECC校验数据进行判断。
上述方案中，所述第一写入数据的位数为M，所述第一测试数据的位数为2M，所述第一测试数据的前M位和后M位的数据相同，M为大于或等于2的偶数。
上述方案中，所述第二测试数据的位数为2M，所述第二写入数据的位 数为2N，M为大于或等于2的偶数，N为大于M的偶数。
上述方案中，所述方法还包括：
在第一测试模式下接收第三写入数据；
响应于所述测试模式信号，将所述第三写入数据或者所述第二写入数据写入所述主存储模块；
在所述读取所述ECC存储模块中存储的ECC校验数据的同时，所述方法还包括：
读取所述主存储模块中存储的所述第三写入数据或者所述第二写入数据。
上述方案中，所述第三写入数据的位数与第二写入数据的位数相同，所述第三写入数据的前N位和后N位的数据相同。
上述方案中，所述在第一测试模式下接收第三写入数据，包括：
在第一测试模式下经由数据焊盘接收第三写入数据；
每个数据焊盘传输的数据的位数为2Z，每个数据焊盘传输的数据的前Z位和后Z位的数据相同，Z为大于或等于2的偶数。
上述方案中，所述基于所述ECC校验数据进行判断，包括：
所述ECC校验数据为所述第一测试数据的情况下，对读取的所述主存储模块中存储的第三写入数据和所述ECC存储模块中存储的ECC校验数据进行压缩处理并输出压缩处理数据至数据焊盘；
基于从所述数据焊盘输出的所述压缩处理数据判断所述ECC存储模块的读写功能是否正常。
上述方案中，所述基于所述ECC校验数据进行判断，还包括：
所述ECC校验数据为所述第二测试数据的情况下，基于读取的所述ECC存储模块中存储的ECC校验数据和所述主存储模块中存储的第二写入数据判断所述主存储模块的读写功能是否正常。
根据本公开实施例的第二方面，提供了一种存储器，包括：
主存储模块和ECC存储模块；
数据输入/输出单元，被配置为在第一测试模式下接收第一写入数据，或者，在第二测试模式下接收第二写入数据；
第一处理单元，被配置为对所述第一写入数据进行复制扩展得到第一测试数据；
第二处理单元，被配置为利用ECC算法对所述第二写入数据进行计算得到第二测试数据；其中，所述第一测试数据用于判断所述ECC存储模块和所述主存储模块的读写功能是否正常，所述第二测试数据用于判断所述主存储模块的读写功能是否正常；
写入单元，与所述第一处理单元和所述第二处理单元连接，被配置为响应于测试模式信号，将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块；所述测试模式信号用于指示执行第 一测试模式或者第二测试模式；
读取单元，被配置为读取所述ECC存储模块中存储的ECC校验数据。
上述方案中，所述第一写入数据的位数为M，所述第一测试数据的位数为2M，所述第一测试数据的前M位和后M位的数据相同，M为大于或等于2的偶数。
上述方案中，所述第二测试数据的位数为2M，所述第二写入数据的位数为2N，M为大于或等于2的偶数，N为大于M的偶数。
上述方案中，所述数据输入/输出单元，还被配置为在第一测试模式下接收第三写入数据；所述写入单元，还被配置为响应于所述测试模式信号，将所述第三写入数据或者所述第二写入数据写入所述主存储模块；
所述读取单元，还被配置为在所述读取所述ECC存储模块中存储的ECC校验数据的同时，读取所述主存储模块中存储的所述第三写入数据或者所述第二写入数据。
上述方案中，所述第三写入数据的位数与第二写入数据的位数相同，所述第三写入数据的前N位和后N位的数据相同。
上述方案中，所述存储器还包括多个数据焊盘，每个所述数据焊盘被配置为在第一测试模式下接收第三写入数据；每个所述数据焊盘传输的数据的位数为2Z，每个所述数据焊盘传输的数据的前Z位和后Z位的数据相同，Z为大于或等于2的偶数。
上述方案中，所述存储器还包括：压缩单元；
所述压缩单元，与所述读取单元连接，被配置为所述ECC校验数据为所述第一测试数据的情况下，对读取的所述主存储模块中存储的第三写入数据和所述ECC存储模块中存储的ECC校验数据进行压缩处理并输出压缩处理数据至所述数据焊盘。
上述方案中，所述存储器还包括：信号生成单元，被配置为对所述测试模式信号、第一控制信号和第二控制信号进行逻辑运算，生成第一触发信号；所述第一控制信号用于指示所述第二处理单元的开启或关闭；所述第二控制信号用于指示所述压缩单元的开启或关闭；所述第一触发信号用于指示所述写入单元将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块。
上述方案中，所述信号生成单元具体被配置为，当所述测试模式信号指示执行第一测试模式时，所述第一控制信号指示所述第二处理单元关闭，所述第二控制信号指示所述压缩单元开启时，生成指示将所述第一测试数据写入所述ECC存储模块的第一触发信号。
根据本公开实施例的第三方面，提供了一种存储器系统，其特征在于，包括如上所述的存储器和控制器；所述控制器，被配置基于所述ECC存储模块中存储的ECC校验数据进行判断。
上述方案中，所述控制器具体被配置为：
在所述ECC校验数据为所述第一测试数据的情况下，基于从所述数据焊盘输出的所述压缩处理数据判断所述ECC存储模块的读写功能是否正常；
或者，
在所述ECC校验数据为所述第二测试数据的情况下，基于读取的所述ECC存储模块中存储的ECC校验数据和所述主存储模块中存储的第二写入数据判断所述主存储模块的读写功能是否正常。
本公开实施例所提供的技术方案能够在测试时根据实际需求灵活切换第一测试模式和第二测试模式，在第一测试模式下通过对第一写入数据进行复制扩展处理获得可以直接访问ECC存储模块的第一测试数据，实现了同时对主存储模块和ECC存储模块进行测试，提高了测试效率。
附图说明
图1为根据本公开实施例示出的存储器系统的框图；
图2为根据本公开实施例示出的存储器的框图；
图3为根据本公开实施例示出的逻辑运算单元的电路结构示意图；
图4为根据本公开实施例示出的信号生成单元生成第一触发信号的时序图；
图5为根据本公开实施例示出的另一种存储器的局部框图；
图6为根据本公开实施例示出的信号生成单元的电路结构示意图；
图7为根据本公开实施例示出的选择单元的电路结构示意图；
图8为根据本公开实施例示出的存储器的测试方法的流程示意图。
具体实施方式
下面将结合附图和实施例对本公开的技术方案进一步详细阐述。虽然附图中显示了本公开的示例性实施方法，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻的理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下列段落中参照附图以举例方式更具体的描述本公开。根据下面说明和权利要求书，本公开的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本公开实施例的目的。
应当明白，空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作 中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是，本公开实施例所记载的技术方案之间，在不冲突的情况下，可以任意组合。
目前对存储器的应用中，通过引用错误检查和纠正技术(Error Checking and Correcting，ECC)提高存储器存储数据的稳定性和正确性。由于生产工艺和生产条件的限制，生产得到的存储器也并非完美无缺，在存储器的研发与制造过程中，往往需要对存储器进行大量的测试以确定是否存在制造过程中产生的异常。引入ECC的存储器需要在存储写入数据的主存储区域外设置ECC存储区域用于存储ECC校验数据，因此在对存储器的主存储区域进行测试时，ECC存储区域也需要进行测试，以防止存储ECC校验数据的ECC存储区域也出现错误，避免出现错误的纠错。
然而，ECC存储区域中的ECC校验数据通过ECC算法产生，在对存储器中执行读取操作时，存储器仅输出读取的写入数据，而不会输出ECC校验数据，通过读取的存储中存储的写入数据只能完成对主存储区域的测试，无法同时完成对主存储区域和ECC存储区域的测试。
对此，本公开提出了以下实施方式。
图1为根据本公开实施例示出的存储器系统的框图。如图1所示，存储器系统10包括存储器110和控制器120。
控制器120可控制存储器系统10的总体操作。控制器120可控制外部主机(图中未示出)与存储器110之间的总体数据交换。例如，控制器110可响应于来自主机的请求而将数据写入存储器110或从存储器110读取数据。另外，控制器120可向存储器110发送命令和地址信号。
在一些实施例中，存储器110包括但不限于动态随机存取存储器(Dynamic Random Access Memory，DRAM)、静态随机存取存储器(Static Random Access Memory，SRAM)、三维NAND型存储器、相变存储器(Phase Change Memory，PCM)、电可擦除可编程只读存储器(Electrically Erasable Programmable Read only Memory，EEPROM)、NOR型闪存存储器、相变随 机存储器(Phase Change Random Access Memory，PRAM)、磁性随机存储器(Magnetoresistive Random Access Memory，MRAM)、阻变随机存储器(Resistive Random Access Memory，RRAM)、铁电随机存储器(Ferro-electric Random Access Memory，FRAM)等。
图2为根据本公开实施例示出的存储器的框图。如图2所示，存储器110包括：存储模块130，存储模块130包括主存储模块132和ECC存储模块131；数据输入/输出单元112，被配置为在第一测试模式下接收第一写入数据W_data1，或者，在第二测试模式下接收第二写入数据W_data2；第一处理单元113，被配置为对第一写入数据W_data1进行复制扩展得到第一测试数据T_data1；第二处理单元114，被配置为利用ECC算法对第二写入数据W_data2进行计算得到第二测试数据T_data2；其中，第一测试数据T_data1用于判断ECC存储模块131和主存储模块132的读写功能是否正常，第二测试数据T_data2用于判断主存储模块132的读写功能是否正常；写入单元115，与第一处理单元113和第二处理单元114连接，被配置为响应于测试模式信号T_mode，将第一测试数据T_data1或者第二测试数据T_data2作为ECC校验数据写入ECC存储模块131；测试模式信号T_mode用于指示执行第一测试模式或者第二测试模式；读取单元117，被配置为读取ECC存储模块131中存储的ECC校验数据。
在本公开实施例中，数据输入/输出单元112，还被配置为在第一测试模式下接收第三写入数据W_data3；写入单元115，还被配置为响应于测试模式信号T_mode，将第三写入数据W_data3或者第二写入数据W_data2写入主存储模块132；
读取单元117，还被配置为在读取ECC存储模块131中存储的ECC校验数据的同时，读取主存储模块132中存储的第三写入数据W_data3或者第二写入数据W_data2。
在一些实施例中，控制器可向存储器110发送写入数据W_data或者从存储器110接收读取数据R_data。需要说明的是，在第一测试模式下控制器向存储器110发送的写入数据W_data包括第一写入数据W_data1和第三写入数据W_data3，控制器120从存储器110接收的读取数据R_data为压缩数据P_data。在第二测试模式下控制器向存储器110发送的写入数据W_data为第二写入数据W_data2，控制器120从存储器110接收的读取数据R_data为经过第二处理单元进行ECC检错并纠正后得到的解码数据D_data。
在一些实施例中，存储模块130可以是由字线和位线交叉分布并由MOS器件及存储电容构成的DRAM存储单元阵列。
在一些实施例中，ECC存储模块131配置为存储ECC校验数据，主存储模块132配置为存储写入数据W_data。
在本公开实施例中，第一写入数据W_data1的位数为M，第一测试数 据T_data1的位数为2M，第一测试数据T_data1的前M位和后M位的数据相同，M为大于或等于2的偶数。
在本公开实施例中，第三写入数据W_data3的位数为2N，第三写入数据W_data3的前N位和后N位的数据相同，N为大于M的偶数。
在一具体实施方式中，存储器110有72bit位宽的存储空间，其中主存储模块132可以为8×8bit位宽的存储空间，ECC存储模块可以为8bit位宽的存储空间。存储器110包括8个数据焊盘(DQ)111，在第一测试模式下第一写入数据W_data1的位数为4，例如第一写入数据W_data1为1100，通过4个数据焊盘111传输第一写入数据W_data1，并且传输第一写入数据W_data1的4个数据焊盘111中的每一个传输1bit的数据。经过第一处理单元113对第一写入数据W_data1进行复制扩展得到第一测试数据T_data1，第一测试数据T_data1的位数为8，例如第一测试数据T_data1为11001100，第一测试数据T_data1的前4位和后4位的数据相同。
示例性地，第三写入数据W_data3的位数为64，例如第三写入数据W_data3为1100110011001100110011001100110011001100110011001100110011001100。第三写入数据W_data3的前32位和后32位的数据相同。
在本公开实施例中，存储器110还包括多个数据焊盘111，每个所述数据焊盘111被配置为在第一测试模式下接收第三写入数据W_data3。
示例性地，第三写入数据W_data3的位数为64，例如第三写入数据W_data3为1100110011001100110011001100110011001100110011001100110011001100。存储器110包括8个数据焊盘111，每个数据焊盘111传输的数据的位数为8，每个数据焊盘111传输的数据的前4位和后4位的数据相同，例如每个数据焊盘111传输的数据为11001100。
可以理解的是，在第一测试模式下写入单元115被配置为响应于测试模式信号T_mode，将第一测试数据T_data1作为ECC校验数据写入ECC存储模块131；将第三写入数据W_data3写入主存储模块132。也就是将11001100写入ECC存储模块131，将经每一个数据焊盘111传输的数据11001100写入主存储模块132中每一片8bit位宽的存储空间。第一测试数据T_data1的位数与ECC存储模块131的位宽相同，第三写入数据W_data3的位数与主存储模块132的位宽相同。
需要说明的是，上述存储器中主存储模块和ECC存储模块的位宽大小仅作为一种示例，在实际应用中可以根据实际需求进行调整。例如存储器有136bit位宽的存储空间，其中主存储模块可以为8×16bit位宽的存储空间，ECC存储模块可以为8bit位宽的存储空间。第一写入数据W_data1可以为1100，第一测试数据T_data1为11001100。第三写入数据W_data3为110011001100110011001100110011001100110011001100110011001100110011 00110011001100110011001100110011001100110011001100110011001100，每个数据焊盘传输的数据为1100110011001100。
在本公开实施例中，存储器110还包括：压缩单元118；压缩单元118，与读取单元117连接，被配置为ECC校验数据为第一测试数据T_data1的情况下，对读取的主存储模块132中存储的第三写入数据W_data3和ECC存储模块131中存储的ECC校验数据进行压缩处理并输出压缩处理数据P_data至数据焊盘111。
图1中所示的控制器120被配置为在ECC校验数据为第一测试数据T_data1的情况下，基于从数据焊盘111输出的压缩处理数据P_data判断ECC存储模块131的读写功能是否正常。需要说明的是，在存储器110包括8个数据焊盘111的情况下，仅需4个数据焊盘111就能实现压缩处理数据P_data的传输，可有效提高数据的传输速率。
示例性地，控制器120经过数据焊盘111接收由存储器110输出的压缩处理数据P_data，可对压缩处理数据P_data进行解压缩处理，以比较从主存储模块132和ECC存储模块131中读取的数据与写入主存储模块132和ECC存储模块131中的数据是否相同，如果从主存储模块132中读取的数据与写入主存储模块132中的数据相同则主存储模块132的读写功能正常，且从ECC存储模块131中读取的数据与写入ECC存储模块131中的数据相同则ECC存储模块131的读写功能正常。即从主存储模块132中读取的数据为第三写入数据W_data3，从ECC存储模块131中读取的数据为第一测试数据T_data1时，主存储模块132和ECC存储模块131的读写功能均正常。
当然，如果从主存储模块132中读取的数据与写入主存储模块132中的数据不同或者从ECC存储模块131中读取的数据与写入ECC存储模块131中的数据不同，则可根据对应的比较结果判断主存储模块132或者ECC存储模块131的读写功能是否正常。
可以理解的是，在第一测试模式下只要存储模块130的读写功能存在异常，即主存储模块132和ECC存储模块131中存在至少一个读写功能不正常时，从主存储模块132和ECC存储模块131中读取的数据可能存在无法正常压缩处理的情况。例如主存储模块132的读写功能正常，ECC存储模块131的读写功能异常，那么从ECC存储模块131中读取的数据可能发生错误如比特翻转，例如从第一测试数据11001100变为了11011100，则无法对主存储模块132和ECC存储模块131中读取的数据进行正常的压缩处理。也就是说，在控制器120在第一测试模式下向存储器110发出读取命令，但在预定时间内未接收到正确的压缩处理数据P_data的情况下，控制器120可以判断存储模块130的读写功能存在异常，并且可通过进一步的测试判断具体的异常区域。
在本公开实施例中，存储器110还包括：信号生成单元116，被配置为 对测试模式信号T_mode、第一控制信号Ctrl_1和第二控制信号Ctrl_2进行逻辑运算，生成第一触发信号Signal_1；第一控制信号Ctrl_1用于指示第二处理单元114的开启或关闭；第二控制信号Ctrl_2用于指示压缩单元118的开启或关闭；第一触发信号Signal_1用于指示写入单元115将第一测试数据T_data1或者第二测试数据T_data2作为ECC校验数据写入ECC存储模块131。
在本公开实施例中，信号生成单元116具体被配置为，当测试模式信号T_mode指示执行第一测试模式时，第一控制信号Ctrl_1指示第二处理单元关闭，第二控制信号Ctrl_2指示压缩单元118开启时，生成指示将第一测试数据T_data1写入ECC存储模块131的第一触发信号Signal_1。
示例性地，信号生成单元116包括如图3所示的逻辑运算单元140，逻辑运算单元140包括第一逻辑或非门141和第二逻辑或非门142，第一逻辑或非门141用于接收第一控制信号Ctrl_1和第二控制信号Ctrl_2，并输出第三控制信号Ctrl_3。第一逻辑或非门141的输出端连接至第二逻辑或非门142的输入端，第二逻辑或非门142用于接收测试模式信号T_mode和第三控制信号Ctrl_3，并输出第一触发信号Signal_1。
图4为本公开实施例提供的信号生成单元生成第一触发信号的时序图，表1为与图4对应的各信号在不同测试模式下的逻辑电平值。
表1
请参阅图3、图4及表1，在T1至T2阶段，测试模式信号T_mode处于逻辑低电平指示执行第一测试模式并开启第一处理单元113，第一控制信号Ctrl_1处于逻辑低电平指示第二处理单元114关闭，第二控制信号Ctrl_2处于逻辑高电平指示压缩单元118开启，经过逻辑运算单元140的运算生成了处于逻辑高电平的第一触发信号Signal_1，指示写入单元115将第一测试数据T_data1作为ECC校验数据ECC_data写入ECC存储模块131。
在T2至T3阶段，测试模式信号T_mode处于逻辑高电平指示执行第二测试模式并关闭第一处理单元113，第一控制信号Ctrl_1处于逻辑高电平指示第二处理单元114开启，第二控制信号Ctrl_2处于逻辑低电平指示压缩单元118关闭，经过逻辑运算单元140的运算生成了处于逻辑低电平的第一触发信号Signal_1，指示写入单元115将第二测试数据T_data2作为ECC校验数据ECC_data写入ECC存储模块131。
在另一些实施例中，如图5所示，可在写入单元115与信号生成单元116之间设置选择单元150。选择单元150也与第一处理单元113和第二处理单元114连接。
如图6所示，信号生成单元116中还包括反相器143，通过反相器143 对第一触发信号Signal_1进行逻辑非运算生成第二触发信号Signal_2。
如图7所示，选择单元150包括第一区域151和第二区域152，第一区域151与第一输入端连接用于接收第一测试数据T_data1，第二区域152与第二输入端连接用于接收第二测试数据T_data2。结合图4至图7及表1可知，在T1至T2阶段，测试模式信号T_mode处于逻辑低电平指示执行第一测试模式并开启第一处理单元113，第一控制信号Ctrl_1处于逻辑低电平指示第二处理单元114关闭，第二控制信号Ctrl_2处于逻辑高电平指示压缩单元118开启，经过逻辑运算单元140的运算生成了处于逻辑高电平的第一触发信号Signal_1，通过反相器143对第一触发信号Signal_1进行逻辑非运算生成第二触发信号Signal_2。此时第一区域151内与第一触发信号Signal_1和第二触发信号Signal_2相连的晶体管导通，第二区域152内与第一触发信号Signal_1和第二触发信号Signal_2相连的晶体管截止，第一测试数据T_data1即可通过选择单元150输出至写入单元115并作为ECC校验数据ECC_data写入ECC存储模块131。
在T2至T3阶段，测试模式信号T_mode处于逻辑高电平指示执行第二测试模式并关闭第一处理单元113，第一控制信号Ctrl_1处于逻辑高电平指示第二处理单元114开启，第二控制信号Ctrl_2处于逻辑低电平指示压缩单元118关闭，经过逻辑运算单元140的运算生成了处于逻辑低电平的第一触发信号Signal_1，通过反相器143对第一触发信号Signal_1进行逻辑非运算生成第二触发信号Signal_2，此时第一区域151内与第一触发信号Signal_1和第二触发信号Signal_2相连的晶体管截止，第二区域152内与第一触发信号Signal_1和第二触发信号Signal_2相连的晶体管导通，第二测试数据T_data2即可通过选择单元150输出至写入单元115并作为ECC校验数据ECC_data写入ECC存储模块131。
在本公开实施例中，第二测试数据T_data2的位数为2M，第二写入数据W_data2的位数为2N，M为大于或等于2的偶数，N为大于M的偶数。
在一具体实施方式中，存储器110有72bit位宽的存储空间，其中主存储模块132可以为8×8bit位宽的存储空间，ECC存储模块可以为8bit位宽的存储空间。第二写入数据W_data2的位数为64，经过第二处理单元114利用ECC算法对第二写入数据W_data2进行计算得到第二测试数据T_data2，第二测试数据T_data2的位数为8。
示例性地，第二处理单元114可以为ECC引擎(ECC engine)，在选定ECC算法后，ECC引擎在第二测试模式下利用ECC算法对控制器120发送给存储器10的第二写入数据W_data2进行计算(或者编码)，得到位数为8的第二测试数据T_data2。ECC引擎可以以各种方式执行编码，例如，ECC引擎可基于，但不限于诸如AN码、BCH码、汉明码、极化码、Turbo码等来执行编码。第二测试数据T_data2的位数与第二写入数据W_data2和ECC算法有关，此处选定的ECC算法得到的第二测试数据T_data2的位数 与ECC存储模块的位宽相同。第二写入数据W_data2的位数与主存储模块132的位宽相同。
可以理解的是，在第二测试模式下写入单元115被配置为响应于测试模式信号T_mode，将第二测试数据T_data2作为ECC校验数据写入ECC存储模块131；将第二写入数据W_data2写入主存储模块132。
图1中所示的控制器120被配置为被配置基于ECC存储模块131中存储的ECC校验数据进行判断。在一些实施例中，在ECC校验数据为第二测试数据T_data2的情况下，基于读取的ECC存储模块131中存储的ECC校验数据和主存储模块132中存储的第二写入数据W_data2判断主存储模块132的读写功能是否正常。
在一具体实施方式中，读取单元117与第二处理单元114连接，在第二测试模式下，读取单元117将从主存储模块132和ECC存储模块131中读取的数据输出至第二处理单元114。示例性地，第二处理单元114可以为ECC引擎，ECC引擎可以执行与纠错解码相关联的各种功能和操作，例如，ECC引擎可以产生ECC校验子(syndrome)、产生ECC错误位置、纠正ECC错误，并且还可以产生ECC检错标志。
第二处理单元114对从主存储模块132和ECC存储模块131中读取的数据进行解码处理得到解码数据D_data，解码处理具体包括对从主存储模块132和ECC存储模块131中读取的数据进行ECC校验得到校验子，校验子可用于检错和纠错。校验子包括从主存储模快132中读取的数据中存在的比特错误的数量。
在一些实施例中，当比特错误的数量为0时，经第二处理单元114得到的解码数据D_data即为第二写入数据W_data2，即控制器120经由数据焊盘111从存储器接收的读取数据R_data为第二写入数据W_data2，控制器120将判断主存储模块132的读写功能正常。
在一些实施例中，当比特错误的数量小于或等于阈值时，例如单个比特错误，第二处理单元114对从主存储模快132中读取的数据中存在比特错误的数据进行纠正得到解码数据D_data，并将解码数据D_data输出至数据输入/输出单元112，然后经由数据焊盘111输出至控制器120。虽然读取的主存储模快132中存储的数据存在比特错误，但是比特错误的数量在第二处理单元114的纠错能力范围内，控制器120将判断主存储模块132的读写功能正常。
在一些实施例中，当比特错误的数量大于阈值时，例如双比特错误，则说明从主存储模快132中读取的数据中存在的比特错误已经超出了第二处理单元114的纠错能力范围，此时无法对读取的主存储模快132中存储的数据进行纠正，将向控制器120发送信号以指示存储器10无法通过ECC校正的多位错误，控制器120将判断主存储模块132的读写功能异常。
本公开实施例中存储器能够在测试时根据实际需求灵活切换第一测试 模式和第二测试模式，通过引入第一处理单元获得可以直接访问ECC存储模块的第一测试数据，如此，实现了同时对主存储模块和ECC存储模块进行测试，提高了测试效率。在对主存储模块的读写功能进行测试时，能够及时发现ECC存储模块可能存在的异常，避免发生错误的纠错，提高数据传输过程的可靠性。
图8为本公开实施例提供的一种存储器的测试方法的流程示意图，该存储器包括主存储模块以及ECC存储模块，下面将结合图1至图2、图4和图8描述该测试方法。存储器的测试方法具体包括以下步骤：
步骤S10：在第一测试模式下接收第一写入数据，对所述第一写入数据进行复制扩展得到第一测试数据，或者，在第二测试模式下接收第二写入数据，利用ECC算法对所述第二写入数据进行计算得到第二测试数据；其中，所述第一测试数据用于判断所述ECC存储模块和所述主存储模块的读写功能是否正常，所述第二测试数据用于判断所述主存储模块的读写功能是否正常；
步骤S20：响应于测试模式信号，将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块；所述测试模式信号用于指示执行第一测试模式或者第二测试模式；
步骤S30：读取所述ECC存储模块中存储的ECC校验数据，基于所述ECC校验数据进行判断。
在一些实施例中，如图4所示，响应于处于低逻辑电平的测试模式信号T_mode，执行第一测试模式并开启第一处理单元113，响应于处于低逻辑电平的第一控制信号Ctrl_1关闭第二处理单元114，响应于处于逻辑高电平的第二控制信号Ctrl_2开启压缩单元118。
在第一测试模式下，接收第一写入数据W_data1，对第一写入数据W_data1进行复制扩展得到第一测试数据T_data1。
在一些实施例中，第一写入数据W_data1的位数为M，第一测试数据T_data1的位数为2M，第一测试数据T_data1的前M位和后M位的数据相同，M为大于或等于2的偶数。
以存储器110有72bit位宽的存储空间为例进行说明，主存储模块132可以为8片8bit位宽的存储空间，ECC存储模块可以为1片8bit位宽的存储空间。存储器110包括8个数据焊盘111，在第一测试模式下第一写入数据W_data1的位数为4，例如第一写入数据W_data1为1100，仅需4个数据焊盘111就能实现第一写入数据W_data1的传输，并且传输第一写入数据W_data1的4个数据焊盘111中的每一个传输1bit的数据。经过第一处理单元113对第一写入数据W_data1进行复制扩展得到第一测试数据T_data1，第一测试数据T_data1的位数为8，例如第一测试数据T_data1为11001100，第一测试数据T_data1的前4位和后4位的数据相同。
在本公开实施例中，上述测试方法还包括：
在第一测试模式下接收第三写入数据W_data3；
在本公开实施例中，第三写入数据W_data3的位数为2N，第三写入数据W_data3的前N位和后N位的数据相同，N为大于M的偶数。
示例性地，第三写入数据W_data3的位数为64，例如第三写入数据W_data3为1100110011001100110011001100110011001100110011001100110011001100。第三写入数据W_data3的前32位和后32位的数据相同。
在本公开实施例中，在第一测试模式下接收第三写入数据，包括：
在第一测试模式下经由数据焊盘接收第三写入数据；
每个数据焊盘传输的数据的位数为2Z，每个数据焊盘传输的数据的前Z位和后Z位的数据相同，Z为大于或等于2的偶数。
示例性地，第三写入数据W_data3的位数为64，例如第三写入数据W_data3为1100110011001100110011001100110011001100110011001100110011001100。存储器110包括8个数据焊盘111，每个数据焊盘111传输的数据的位数为8，每个数据焊盘111传输的数据的前4位和后4位的数据相同，例如每个数据焊盘111传输的数据为11001100。
在本公开实施例中，对测试模式信号T_mode、第一控制信号Ctrl_1和第二控制信号Ctrl_2进行逻辑运算生成处于逻辑高电平的第一触发信号Signal_1。响应于第一触发信号Signal_1，将第一测试数据T_data1写入ECC存储模块131，将第三写入数据W_data3写入主存储模块132。
在本公开实施例中，读取ECC存储模块131中存储的ECC校验数据和主存储模块132中存储的第三写入数据W_data3。
基于从ECC存储模块131中读取的ECC校验数据进行判断，具体地，在第一测试模式下ECC校验数据为第一测试数据T_data1，对读取的主存储模块中存储的第三写入数据和ECC存储模块中存储的ECC校验数据进行压缩处理并输出压缩处理数据P_data至数据焊盘111。
基于从数据焊盘111输出的压缩处理数据P_data判断ECC存储模块131的读写功能是否正常。示例性地，控制器120经过数据焊盘111接收由存储器110输出的压缩处理数据P_data，可对压缩处理数据P_data进行解压缩处理，以比较从主存储模块132和ECC存储模块131中读取的数据与写入主存储模块132和ECC存储模块131中的数据是否相同，如果从主存储模块132中读取的数据与写入主存储模块132中的数据相同则主存储模块132的读写功能正常，且从ECC存储模块131中读取的数据与写入ECC存储模块131中的数据相同则ECC存储模块131的读写功能正常。即从主存储模块132中读取的数据为第三写入数据W_data3，从ECC存储模块131中读取的数据为第一测试数据T_data1时，主存储模块132和ECC存储模块131的读写功能均正常。
当然，如果从主存储模块132中读取的数据与写入主存储模块132中的数据不同或者从ECC存储模块131中读取的数据与写入ECC存储模块131中的数据不同，则可根据对应的比较结果判断主存储模块132或者ECC存储模块131的读写功能是否正常。
可以理解的是，在第一测试模式下只要存储模块130的读写功能存在异常，即主存储模块132和ECC存储模块131中存在至少一个读写功能不正常时，从主存储模块132和ECC存储模块131中读取的数据可能存在无法正常压缩处理的情况。例如主存储模块132的读写功能正常，ECC存储模块131的读写功能异常，那么从ECC存储模块131中读取的数据可能发生错误如比特翻转，例如从11001100变为了11011100，则无法对主存储模块132和ECC存储模块131中读取的数据进行正常压缩处理。也就是说，在控制器120在第一测试模式下向存储器110发出读取命令，但在预定时间内未接收到正确的压缩处理数据P_data的情况下，控制器120可以判断存储模块130的读写功能存在异常，并且可通过进一步的测试判断具体的异常区域。
在一些实施例中，如图4所示，响应于处于高逻辑电平的测试模式信号T_mode，执行第二测试模式并关闭第一处理单元113，响应于处于高逻辑电平的第一控制信号Ctrl_1开启第二处理单元114，响应于处于逻辑低电平的第二控制信号Ctrl_2关闭压缩单元118。
在第二测试模式下，接收第二写入数据W_data12，利用ECC算法对第二写入数据W_data1进行计算得到第二测试数据T_data2。
在本公开实施例中，第二测试数据T_data2的位数为2M，第二写入数据W_data2的位数为2N，M为大于或等于2的偶数，N为大于M的偶数。
以存储器110有72bit位宽的存储空间为例进行说明，其中主存储模块132可以为8×8bit位宽的存储空间，ECC存储模块可以为8bit位宽的存储空间。第二写入数据W_data2的位数为64，经过第二处理单元114利用ECC算法对第二写入数据W_data2进行计算得到第二测试数据T_data2，第二测试数据T_data2的位数为8。
在本公开实施例中，对测试模式信号T_mode、第一控制信号Ctrl_1和第二控制信号Ctrl_2进行逻辑运算生成处于逻辑低电平的第一触发信号Signal_1。响应于第一触发信号Signal_1，将第二测试数据T_data2写入ECC存储模块131，将第二写入数据W_data2写入主存储模块132。
在一些实施例中，读取ECC存储模块131中存储的ECC校验数据和主存储模块132中存储的第二写入数据W_data2。
基于从ECC存储模块131中读取的ECC校验数据进行判断，具体地，在第二测试模式下ECC校验数据为第二测试数据T_data2，基于读取的ECC存储模块中存储的ECC校验数据和主存储模块中存储的第二写入数据W_data2判断主存储模块的读写功能是否正常。
在一具体实施方式中，第二处理单元114对从主存储模块132和ECC存储模块131中读取的数据进行解码处理得到解码数据D_data，解码处理具体包括对从主存储模块132和ECC存储模块131中读取的数据进行ECC校验得到校验子，校验子可用于检错和纠错。校验子包括从主存储模快132中读取的数据中存在的比特错误的数量。
在一些实施例中，当比特错误的数量为0时，经第二处理单元114得到的解码数据D_data即为第二写入数据W_data2，即控制器120经由数据焊盘111从存储器接收的读取数据R_data为第二写入数据W_data2，控制器120将判断主存储模块132的读写功能正常。
在一些实施例中，当比特错误的数量小于或等于阈值时，例如单个比特错误，第二处理单元114对从主存储模快132中读取的数据中存在比特错误的数据进行纠正得到解码数据D_data，并将解码数据D_data输出至数据输入/输出单元112，然后经由数据焊盘111输出至控制器120。虽然读取的主存储模快132中存储的数据存在比特错误，但是比特错误的数量在第二处理单元114的纠错能力范围内，控制器120将判断主存储模块132的读写功能正常。
在一些实施例中，当比特错误的数量大于阈值时，例如双比特错误，则说明从主存储模快132中读取的数据中存在的比特错误已经超出了第二处理单元114的纠错能力范围，此时无法对读取的主存储模快132中存储的数据进行纠正，将向控制器120发送信号以指示存储器10无法通过ECC校正的多位错误，控制器120将判断主存储模块132的读写功能异常。
本公开实施例中提供的存储器的测试方法能够在测试时根据实际需求灵活切换第一测试模式和第二测试模式，通过引入第一处理单元获得可以直接访问ECC存储模块的第一测试数据，如此，实现了同时对主存储模块和ECC存储模块进行测试，提高了测试效率。在对主存储模块的读写功能进行测试时，能够及时发现ECC存储模块可能存在的异常，避免发生错误的纠错，提高数据传输过程的可靠性。
应理解，说明书通篇中提到的“一实施例”或“一些实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一实施例中”或“在一些实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。
工业实用性
本公开实施例所提供的技术方案能够在测试时根据实际需求灵活切换第一测试模式和第二测试模式，在第一测试模式下通过对第一写入数据进行复制扩展处理获得可以直接访问ECC存储模块的第一测试数据，实现了同时对主存储模块和ECC存储模块进行测试，提高了测试效率。

Claims (19)

  1. 一种存储器的测试方法，所述存储器包括主存储模块以及ECC存储模块，所述方法包括：
    在第一测试模式下接收第一写入数据，对所述第一写入数据进行复制扩展得到第一测试数据，或者，在第二测试模式下接收第二写入数据，利用ECC算法对所述第二写入数据进行计算得到第二测试数据；其中，所述第一测试数据用于判断所述ECC存储模块和所述主存储模块的读写功能是否正常，所述第二测试数据用于判断所述主存储模块的读写功能是否正常；
    响应于测试模式信号，将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块；所述测试模式信号用于指示执行第一测试模式或者第二测试模式；
    读取所述ECC存储模块中存储的ECC校验数据，基于所述ECC校验数据进行判断。
  2. 根据权利要求1所述的测试方法，其中，所述第一写入数据的位数为M，所述第一测试数据的位数为2M，所述第一测试数据的前M位和后M位的数据相同，M为大于或等于2的偶数。
  3. 根据权利要求1所述的测试方法，其中，所述第二测试数据的位数为2M，所述第二写入数据的位数为2N，M为大于或等于2的偶数，N为大于M的偶数。
  4. 根据权利要求1至3中任一项所述的测试方法，其中，所述方法还包括：
    在第一测试模式下接收第三写入数据；
    响应于所述测试模式信号，将所述第三写入数据或者所述第二写入数据写入所述主存储模块；
    在所述读取所述ECC存储模块中存储的ECC校验数据的同时，所述方法还包括：
    读取所述主存储模块中存储的所述第三写入数据或者所述第二写入数据。
  5. 根据权利要求4所述的测试方法，其中，所述第三写入数据的位数与第二写入数据的位数相同，所述第三写入数据的前N位和后N位的数据相同。
  6. 根据权利要求5所述的测试方法，其中，所述在第一测试模式下接收第三写入数据，包括：
    在第一测试模式下经由数据焊盘接收第三写入数据；
    每个数据焊盘传输的数据的位数为2Z，每个数据焊盘传输的数据的前Z位和后Z位的数据相同，Z为大于或等于2的偶数。
  7. 根据权利要求6所述的测试方法，其中，所述基于所述ECC校验 数据进行判断，包括：
    所述ECC校验数据为所述第一测试数据的情况下，对读取的所述主存储模块中存储的第三写入数据和所述ECC存储模块中存储的ECC校验数据进行压缩处理并输出压缩处理数据至数据焊盘；
    基于从所述数据焊盘输出的所述压缩处理数据判断所述ECC存储模块的读写功能是否正常。
  8. 根据权利要求7所述的测试方法，其中，所述基于所述ECC校验数据进行判断，还包括：
    所述ECC校验数据为所述第二测试数据的情况下，基于读取的所述ECC存储模块中存储的ECC校验数据和所述主存储模块中存储的第二写入数据判断所述主存储模块的读写功能是否正常。
  9. 一种存储器，包括：
    主存储模块和ECC存储模块；
    数据输入/输出单元，被配置为在第一测试模式下接收第一写入数据，或者，在第二测试模式下接收第二写入数据；
    第一处理单元，被配置为对所述第一写入数据进行复制扩展得到第一测试数据；
    第二处理单元，被配置为利用ECC算法对所述第二写入数据进行计算得到第二测试数据；其中，所述第一测试数据用于判断所述ECC存储模块和所述主存储模块的读写功能是否正常，所述第二测试数据用于判断所述主存储模块的读写功能是否正常；
    写入单元，与所述第一处理单元和所述第二处理单元连接，被配置为响应于测试模式信号，将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块；所述测试模式信号用于指示执行第一测试模式或者第二测试模式；
    读取单元，被配置为读取所述ECC存储模块中存储的ECC校验数据。
  10. 根据权利要求9所述的存储器，其中，所述第一写入数据的位数为M，所述第一测试数据的位数为2M，所述第一测试数据的前M位和后M位的数据相同，M为大于或等于2的偶数。
  11. 根据权利要求9所述的存储器，其中，所述第二测试数据的位数为2M，所述第二写入数据的位数为2N，M为大于或等于2的偶数，N为大于M的偶数。
  12. 根据权利要求9至11中任一项所述的存储器，其中，
    所述数据输入/输出单元，还被配置为在第一测试模式下接收第三写入数据；
    所述写入单元，还被配置为响应于所述测试模式信号，将所述第三写入数据或者所述第二写入数据写入所述主存储模块；
    所述读取单元，还被配置为在所述读取所述ECC存储模块中存储的 ECC校验数据的同时，读取所述主存储模块中存储的所述第三写入数据或者所述第二写入数据。
  13. 根据权利要求12所述的存储器，其中，所述第三写入数据的位数与第二写入数据的位数相同，所述第三写入数据的前N位和后N位的数据相同。
  14. 根据权利要求13所述的存储器，其中，所述存储器还包括多个数据焊盘，每个所述数据焊盘被配置为在第一测试模式下接收第三写入数据；每个所述数据焊盘传输的数据的位数为2Z，每个所述数据焊盘传输的数据的前Z位和后Z位的数据相同，Z为大于或等于2的偶数。
  15. 根据权利要求14所述的存储器，其中，所述存储器还包括：压缩单元；
    所述压缩单元，与所述读取单元连接，被配置为所述ECC校验数据为所述第一测试数据的情况下，对读取的所述主存储模块中存储的第三写入数据和所述ECC存储模块中存储的ECC校验数据进行压缩处理并输出压缩处理数据至所述数据焊盘。
  16. 根据权利要求15所述的存储器，其中，所述存储器还包括：
    信号生成单元，被配置为对所述测试模式信号、第一控制信号和第二控制信号进行逻辑运算，生成第一触发信号；所述第一控制信号用于指示所述第二处理单元的开启或关闭；所述第二控制信号用于指示所述压缩单元的开启或关闭；所述第一触发信号用于指示所述写入单元将所述第一测试数据或者所述第二测试数据作为ECC校验数据写入所述ECC存储模块。
  17. 根据权利要求16所述的存储器，其中，所述信号生成单元具体被配置为，当所述测试模式信号指示执行第一测试模式时，所述第一控制信号指示所述第二处理单元关闭，所述第二控制信号指示所述压缩单元开启时，生成指示将所述第一测试数据写入所述ECC存储模块的第一触发信号。
  18. 一种存储器系统，包括如权利要求9至17中任一项所述的存储器和控制器；所述控制器，被配置基于所述ECC存储模块中存储的ECC校验数据进行判断。
  19. 根据权利要求18所述的存储器系统，其中，所述控制器具体被配置为：
    在所述ECC校验数据为所述第一测试数据的情况下，基于从所述数据焊盘输出的所述压缩处理数据判断所述ECC存储模块的读写功能是否正常；
    或者，
    在所述ECC校验数据为所述第二测试数据的情况下，基于读取的所述ECC存储模块中存储的ECC校验数据和所述主存储模块中存储的第二写入数据判断所述主存储模块的读写功能是否正常。
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