WO2024138849A1

WO2024138849A1 - Inverter prediction control method based on optimal switching sequence model

Info

Publication number: WO2024138849A1
Application number: PCT/CN2023/077290
Authority: WO
Inventors: 杨勇; 陈胜伟; 肖扬; 樊明迪; 王铀程; 莫仁基; 龚铭祺; 李相澄
Original assignee: 苏州大学
Priority date: 2022-12-29
Filing date: 2023-02-21
Publication date: 2024-07-04

Abstract

Provided in the present invention are an inverter prediction control method based on an optimal switching sequence model, the inverter being a T-type single-phase three-level inverter. The voltage state prediction control method comprises the following steps: 1) creating an output voltage model, the output voltage model comprising a plurality of small voltage vectors; 2) building an OSS-MPC prediction model, and, at a K moment, predicting an output current at the K+1 moment according to the MPC prediction model; 3) building a switching sequence set, each built switching sequence comprising two redundant small voltage vectors which have opposite effects on a direct-current capacitor voltage; 4) by adjusting the operating time of the redundant small voltage vectors, achieving dynamic adjustment of a direct-current voltage-dividing capacitor voltage; 5) dividing the switching sequence set by means of a reference current to obtain a candidate switching sequence, and finding the optimal switching sequence among the candidates; and 6) according to the optimal switching sequence, controlling a switch sequence generator to output a prediction control signal for controlling an inverter.

Description

Inverter predictive control method based on optimal switching sequence model

Technical Field

The present invention relates to the technical field of inverters, and in particular to an inverter prediction control method based on an optimal switching sequence model.

Background technique

Traditional linear control strategies for single-phase inverters commonly use resonant control, proportional integral (PI) control, etc. These methods have high requirements for the controller parameter design process. Dynamic performance and steady-state performance need to go through a cumbersome parameter tuning process to achieve relative balance. Repetitive control is a zero-static error control strategy based on the internal model principle, which can ensure that the output waveform can accurately track the command. However, slow dynamic response is a major disadvantage of this strategy. In general, these control strategies provide good performance. However, for some nonlinear links that cannot be ignored, model predictive control (MPC) is needed to improve the dynamic and steady-state performance of the system. MPC control first defines a cost function based on the control objective. Then, a prediction model is constructed using the discrete characteristics of power electronics, and the future output corresponding to different switching states is predicted based on the constructed prediction model and the current state of the system. Finally, the defined cost function is used to evaluate the future output and determine the optimal switching state. MPC applied to inverters in the field of power electronics can be divided into two categories: finite control set MPC (FCS-MPC) and continuous control set MPC (CCS-MPC).

technical problem

Traditional linear control strategies (such as resonant control, proportional integral (PI) control, etc.) have relatively high requirements for the controller parameter design process. Dynamic performance and steady-state performance need to go through a cumbersome parameter tuning process to achieve relative balance. Due to the complex iterative process and a large amount of previous information, the repetitive control method has high performance requirements for the control chip. The disadvantages of the traditional FCS-MPC algorithm include: 1. The change of switching frequency leads to large output current ripple and difficulty in filter design. 2. In order to achieve neutral point potential balance, a weight coefficient is introduced into the cost function. The determination of the specific value of the weight coefficient requires a lot of experiments to find a relatively suitable value because there is no specific theoretical support. The disadvantages of the several FCS-MPC strategies with fixed switching frequencies proposed at present are: 1. The weight coefficient still exists. 2. The complex control algorithm leads to a large computational burden.

Technical Solutions

The objectives of the present invention are achieved through the following technical solutions.

The present invention provides an inverter predictive control method based on an optimal switching sequence model, wherein the inverter is a T-type single-phase three-level inverter, and the voltage state predictive control method comprises the following steps:

1) Creating an output voltage model, wherein the output voltage model includes a plurality of small voltage vectors;

2) constructing an OSS-MPC prediction model, and predicting the output current at time K+1 according to the MPC prediction model at time K;

3) constructing a set of switching sequences, each of which contains two redundant small voltage vectors having opposite effects on the DC capacitor voltage, and a zero voltage vector or a large voltage vector having no effect on the DC capacitor voltage;

4) Dynamically adjusting the voltage of the DC voltage divider capacitor by adjusting the running time of the redundant small voltage vector, thereby achieving NP balance;

5) Divide the switching sequence set by reference current to obtain candidate switching sequences, and find the optimal switching sequence among the candidates;

6) Controlling a switch sequence generator according to the optimal switching sequence to output a prediction control signal for controlling the inverter.

Beneficial Effects

1. The code time of the simplified OSS-MPC without weighting coefficients proposed in this application is about half of that of the traditional OSS-MPC algorithm with weighting coefficients, which greatly reduces the computational burden of the code. 2. The simplified OSS-MPC without weighting coefficients proposed in this application, like the traditional OSS-MPC algorithm with weighting coefficients, can accurately and quickly track the reference current and has good steady-state and dynamic performance. Even the ripple of the output current of the simplified OSS-MPC without weighting coefficients is smaller. 3. The proposed simplified OSS-MPC without weighting coefficients realizes a fixed switching frequency, and the high-order harmonics are mainly distributed around the sampling frequency (16khz) and twice the sampling frequency (32khz). 4. The simplified OSS-MPC without weighting coefficients proposed in this application makes full use of the smaller voltage vector to balance the NP voltage, removes the weight coefficient in the cost function, simplifies the control implementation, and has good NP voltage balancing performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

FIG1 shows a topology diagram of a T-type single-phase three-level inverter according to an embodiment of the present application.

FIG2 is a schematic diagram showing the detailed working process of the DC capacitor and NP current of the redundant small voltage vector according to an embodiment of the present application, wherein (a) V1 (0, -1), (b) V5 (1, 0), (c) V3 (-1, 0), and (d) V7 (0, 1).

FIG3 shows a schematic diagram of a control region of a discrete output voltage vector of an inverter according to an embodiment of the present application.

FIG. 4 shows a graphical example diagram of a constructed switching sequence according to an embodiment of the present application.

FIG5 is a schematic diagram showing the switching modes and action times of different voltage vectors in each switching sequence according to an embodiment of the present application.

FIG6 shows a flow chart of a simplified OSS-MPC without weighting coefficients according to an embodiment of the present application.

FIG. 7 shows a block diagram of a simplified OSS-MPC without weighted coefficients according to an embodiment of the present application.

FIG8 shows a waveform diagram of a steady-state performance analysis experiment of an embodiment of the present application.

FIG9 is a schematic diagram comparing the harmonic spectrum of the output current of the conventional OSS-MPC algorithm and the one proposed in this application.

FIG. 10 is a schematic diagram showing the results of a dynamic performance analysis experiment according to an embodiment of the present application.

FIG. 11 shows a schematic diagram of NP fluctuation simulation of an embodiment of the present application and a schematic diagram of waveforms of an OSS-MPCNP voltage balance experiment proposed in the present application.

Embodiments of the present invention

术语解释：Terminology explanation:

Diode clamped (neutral point clamped) multilevel inverter: Diode clamped multilevel inverter mainly generates multi-level AC voltage through clamping diodes and series DC capacitors. The topology of this inverter usually consists of three, four, and five levels.

Flying capacitor type multilevel inverter: Compared with the diode clamped multilevel inverter, the DC side capacitor remains unchanged, and the clamping diode is replaced by a flying capacitor. The working principle is similar to the diode clamped circuit. Each phase has 4 switching devices that are simultaneously in the on or off state, forming 4 complementary switching device pairs, but the combination of the switching device pairs is different from the diode clamped type, and in terms of voltage synthesis, the choice of switching state is more flexible.

Cascaded multilevel inverter: Cascaded multilevel inverter is formed by combining several basic inverter modules (such as H-bridge).

Hybrid clamped multilevel inverter: A hybrid clamped multilevel inverter is a traditional diode clamped multilevel inverter in which a floating capacitor is connected in parallel to the clamping diode of each bridge arm.

Finite Control Set Model Predictive Control (FCS-MPC): Finite set model predictive control combines the switching characteristics of the inverter to generate a finite number of voltage vectors. The motor output results generated by each switching state are predicted in the current control cycle, and the switching state with the predicted result closest to the expected result is used as the optimal switching state for the next control cycle. The value function is used to evaluate the degree of similarity between the predicted results and the expected results corresponding to different switching states, and the optimal switching state is selected based on this standard.

Continuous Control Set Model Predictive Control (CCS-MPC): Continuous Control Set Model Predictive Control uses modulation technology to generate a continuous voltage vector in the vector complex plane. It is a model-based optimal control method in the time domain.

Optimal switching sequence model predictive control (OSS-MPC). Based on the finite control set model predictive control, the idea of space vector pulse width modulation (SVPWM) is used to apply a switching sequence (including switch state and duty cycle) composed of multiple voltage vector combinations within one control cycle.

The present application proposes a simplified optimal switching sequence model predictive control (OSS-MPC) without weighted coefficients for T-type single-phase three-level inverters. A fixed switching frequency is achieved by adopting the OSS-MPC control method. In order to remove the weight coefficients in the cost function, the different effects of redundant small voltage vectors on the voltages of the upper and lower DC link capacitors are considered when constructing the switching sequence. In each switching sequence, there are two symmetrical redundant small voltage vectors that have opposite effects on the DC link capacitor voltage. Therefore, the neutral point voltage balance of the inverter can be achieved by adjusting the action time of the two redundant small voltage vectors, rather than adding NP voltage balance terms to the cost function. According to the different effects of the switching sequence, the switching sequence is simply divided by reference to obtain candidate switching sequences. Then the optimal switching sequence is found among the candidates, thereby simplifying the optimization process and reducing the computational burden.

A. Output voltage model construction

Table 1: Variables sampled by the system

As shown in FIG1 , the present application adopts a T-type single-phase three-level inverter topology. Wherein E _dc represents a DC voltage source, C ₁ and C ₂ represent DC voltage-dividing capacitors, L represents a filter inductor, and C represents a filter capacitor. S _xi represents the power electronic switch device in the figure, and V _AO and V _BO are the output voltages of bridge arm A and bridge arm B relative to the neutral point O , respectively. The variables sampled by other systems are shown in detail in Table 1. For ease of description, the on and off states of the power electronic switch device are represented by "0" and "1", respectively, that is, S _xi Î{0,1}. In addition, S _x1 , S _x3 and S _x2 , S _x4 work in a complementary manner to prevent the occurrence of a shoot-through phenomenon. Under the ideal condition of assuming NP voltage balance, Table 2 specifically gives the corresponding relationship between the output voltage and the switch state. Wherein "P", "O" and "N" respectively represent that the output voltage of bridge arm A or B relative to the DC side neutral point O is V _dc /2, 0 and -V _dc /2.

Table 2: Correspondence between output voltage and switch status

Assuming that all devices are ideal devices and ignoring the dead time and nonlinear characteristics of power electronic switches, the output voltage of the inverter can be determined based on the state of the power electronic switches. defined as

Among them, "1", "0" and "-1" represent the status of all switches on the bridge arm when the output state is "P", "O" and "N" respectively.

According to the switching state defined in (1), the output voltage V _AB of the inverter can be expressed as

Assuming that the NP voltage is in a balanced state, the output voltage of the inverter can be discretized into 9 (3 ² ) voltage vectors. Table 3 gives the specific correspondence between the inverter switch state and the voltage vector.

There are 9 voltage vectors in Table 3, including 2 large voltage vectors V ₂ , V ₆ , 4 small voltage vectors V ₁ , V ₅ , V ₃ , V ₇ , and 3 zero voltage vectors V ₀ , V ₄ , V ₈ . For the T-type three-phase three-level inverter, the NP voltage is affected by both the small voltage vector and the medium voltage vector. For the T-type single-phase three-level inverter, the NP voltage is only affected by the small voltage vector. Therefore, for the T-type single-phase three-level inverter, the small voltage vector can be used to adjust the NP voltage.

Table 3: Specific correspondence between inverter switching state and voltage vector

B. Building a predictive model

According to the topology in Figure 1, the dynamic output of the inverter in continuous time can be expressed as:

To construct the output current prediction formula of the T-type single-phase three-level inverter, formula (3) is rewritten as:

Then, the dynamic increment of the inverter output current in each inverter output voltage switching interval can be expressed by equation (4). As shown in Table 3, according to different switching states, the inverter output voltage V _AB has 9 possible output voltage vectors V _j , where j ∈ {0, ..., 8}. Therefore, for each output voltage vector V _j , the function of the inverter output current increment can be defined as:

Three voltage vectors are selected from all nine voltage vectors to define the switching sequence:

Where X, Y, Z ∈ {0, ..., 8}. The action time of the output voltage vectors V _X , V _Y , and V _Z can be expressed as t ₁ , t ₂ , and t ₃ respectively, and the relationship between the action times can be expressed as

Where T _S represents the sampling time. Then the switching sequence The corresponding time series of each voltage vector can be defined as

Will switch sequence Substituting the voltage vector in into formula (5), the output current increment sequence corresponding to the switching sequence can be expressed as

Assume that the inverter output current changes slowly with the sampling frequency. Therefore, if the prediction step size is small enough, the current can be approximately equivalent to a constant. Since this application only considers one time step, the measured value at sampling time k is and It can be approximately regarded as unchanged during the sampling time interval T _S. According to formulas (4) and (5), during the sampling time interval T _S , the switching sequence The influence of each output voltage vector on the output current is accumulated and summed. Therefore, the output current at the next sampling time k+ 1 can be predicted as

In the above formula is the predicted current at time k + 1, is the instantaneous current at time k .

Since the sampling time Ts _is small enough, using the idea of calculus, formula (10) can be transformed into

C. Constructing the Optimal Switching Sequence (OSS)

In order to achieve a three-level output in a single-phase three-level inverter, two capacitors connected in series are used on the DC side to form a neutral point. During the charging and discharging process of the DC capacitor, the neutral point potential fluctuates. When the voltage difference between the upper and lower DC capacitors increases, the performance of the inverter deteriorates. In order to obtain better inverter performance, the weighting coefficient λ in the cost function must be appropriately adjusted to achieve a balance of NP voltage. However, in practical applications, selecting a suitable weighting coefficient is a very cumbersome process, and a large number of experiments are required to find a relatively suitable value.

Among all possible output voltage vectors of a single-phase three-level inverter, there are 4 redundant small voltage vectors: V ₁ , V ₅ , V ₃ , and V ₇ . These redundant small voltage vectors can be divided into two groups according to their output levels. One group is V ₁ and V ₅ , whose output voltages are both -V _dc /2; the other group is V ₃ and V ₇ , whose output voltages are both V _dc /2. Figure 2 shows the detailed working process of the DC capacitor and NP current of the redundant small voltage vectors. It can be clearly seen from Figure 2 that although the output voltages of the two voltage vectors in each group are the same, their effects on the DC capacitor voltage are opposite. Specifically, the voltage vectors V ₁ and V ₃ will increase the upper DC capacitor voltage _VP and reduce the lower DC capacitor voltage _VN ; the voltage vectors V ₅ and V ₇ will reduce the upper DC capacitor voltage _VP and increase the lower DC capacitor voltage _VN . Therefore, according to the above analysis, it can be found that by using redundant small voltage vectors, the NP voltage can be adjusted, thereby removing the weight coefficient in the cost function of the traditional MPC algorithm.

According to the voltage vectors shown in Table 3, the control area of the discrete output voltage vector of the inverter is shown in Figure 3. It can be found from Figure 3 that the output voltage vectors along the darker dotted lines have the same output voltage level. The darker dotted lines A , B , C , D , and E correspond to the output voltage levels -V _dc , -V _dc /2, 0, V _dc /2, and V _dc , respectively. Each output voltage vector along the lighter dotted line has the same effect on the DC capacitor voltage. The vector on the lighter dotted line b can reduce the upper DC capacitor voltage V _P and increase the lower DC capacitor voltage V _N , which is called a positive vector; the vector on the lighter dotted line d can increase the upper DC capacitor voltage V _P and reduce the lower DC capacitor voltage V _N , which is called a negative vector.

In order to facilitate the construction of the switching sequence set, the control areas of the 9 voltage vectors are rearranged. The horizontal axis represents the output voltage V _AB and the vertical axis represents the influence of the vector on the NP. It can be found from the figure that the redundant small voltage vectors with the same output voltage are symmetrically distributed along the direction of the NP influence axis. Therefore, in order to more conveniently achieve NP balance, each constructed switching sequence contains two redundant small voltage vectors that have opposite effects on the DC capacitor voltage, and a zero voltage vector or a large voltage vector that has no effect on the DC capacitor voltage. Figure 4 specifically gives a graphical example of the constructed switching sequence.

After constructing the switching sequence, the next step is to determine the time sequence corresponding to the switching sequence. The output current deviation can be expressed as:

In the above formula is the predicted current at time k + 1, is the expected output current. Substituting formula (11) into (12) yields:

In the same switching sequence, the optimal time sequence is to make the output current deviation 0. Considering the relationship of formula (7), the system can be simplified as:

Since the two redundant small voltage vectors with opposite effects on the DC divider capacitor voltage are placed symmetrically when constructing the switching sequence, in order to ensure NP voltage balance, their running time should be the same in theory, that is, t ₁ =t ₃ . This condition can be used to solve formula (14). Therefore, the running time of each voltage vector in the switching sequence can be determined as:

D. Time compensation of NP balance

Although the proposed switching sequence is symmetrically constructed, the NP imbalance problem still occurs in practical applications due to the different values of the upper and lower DC voltage divider capacitors caused by manufacturing defects. Since the redundant small voltage vector will affect the DC voltage divider capacitor voltage, the DC voltage divider capacitor voltage can be dynamically adjusted by adjusting the running time of the redundant small voltage vector, thereby achieving NP balance. The time compensation t _comp of NP balance can be defined as:

Therefore, the adjusted time series It can be expressed as:

The present application adopts a symmetrical pulse mode, so the switching mode and action time of different voltage vectors in each switching sequence are shown in Figure 5. Among them, (a) SS ₀ . (b) SS ₁ . (c) SS ₂ . (d) SS ₃ .

After the above operation, the weighting coefficient λ can be removed from the cost function, and the simplified cost function is specifically expressed as:

E. Simplify the optimization process

As shown in Figure 4, four switching sequences are obtained. In the traditional OSS-MPC algorithm, the optimization process needs to traverse all four switching sequences to find the optimal switching sequence, and each switching sequence needs to calculate (9) and (19), which will bring a lot of calculation.

A careful observation of FIG4 shows that no matter which time sequence is applied, the corresponding outputs of SS ₀ and SS ₁ are always less than or equal to 0, while the outputs of SS ₂ and SS ₃ are always greater than or equal to 0. Therefore, the reference current i _ref can be judged first: if i _ref is greater than 0, it is only necessary to select the optimal switching sequence from the candidate switching sequences SS ₂ and SS ₃ ; otherwise, it is necessary to select the optimal switching sequence from the candidate switching sequences SS ₀ and SS _1. In this way, the optimization process of four candidate switching sequences can be simplified to the optimization process of two candidate switching sequences, thereby greatly reducing the amount of calculation. FIG6 shows the flowchart of the proposed simplified OSS-MPC without weighted coefficients, and FIG7 shows the block diagram of the proposed simplified OSS-MPC without weighted coefficients.

Table 4: Specific experimental parameters

This application has carried out specific experimental verification and built an experimental platform based on the digital signal processor (DSP) TMS320F28377D. The experimental platform includes a DC power supply, a resistive load box, a T-type three-level inverter module and driver, a control board based on the digital signal processor (DSP) TMS320F28377D, a computer, and an oscilloscope. Its specific parameters are shown in Table 4. The inverter output current is measured with a VAC current sensor, and the filter capacitor and the upper and lower DC voltage divider capacitor voltages are measured with a LEM voltage sensor.

This application compares the performance of the traditional OSS-MPC algorithm with weighted coefficients and the simplified OSS-MPC algorithm without weighted coefficients. First, a comparative experiment of algorithm execution time is conducted, comparing the algorithm execution time of the traditional OSS-MPC and the OSS-MPC proposed in this application.

Then, a steady-state performance analysis experiment was conducted, with reference currents of 2.5A and 5A for the traditional OSS-MPC and the OSS-MPC proposed in this application, respectively.

Then, the dynamic performance analysis experiment was carried out, and experiments were conducted on the traditional OSS-MPC and the OSS-MPC proposed in this application when the reference current suddenly increased and suddenly decreased.

Finally, an NP voltage balance experiment was conducted. By suddenly adding resistance to the upper DC voltage divider capacitor to simulate NP voltage fluctuation, an experimental NP voltage fluctuation experiment of the OSS-MPC proposed in this application was conducted.

A. Algorithm execution time experiment

The clock function of the CCS software is used to measure the execution time of the traditional OSS-MPC and the OSS-MPC algorithm proposed in this application. The specific results are shown in Table 5.

As can be seen from Table 5, the execution time of the OSS-MPC algorithm proposed in this application is 22.23 μs, which is only about 52% of the traditional OSS-MPC algorithm. This proves that the proposed simplified process reduces the computational complexity.

Table 5: Algorithm execution time experiment

B. Steady-state performance analysis experiment

In the steady-state performance comparison, in order to ensure effective NP voltage balance, the weighting coefficient λ of the traditional OSS-MPC algorithm is determined to be 4. FIG8 compares the steady-state experimental waveforms of the inverter output voltage V _AB , the upper DC voltage divider capacitor voltage V _P and the output _current is of the traditional and the OSS-MPC algorithms proposed in this application. (a) The traditional OSS-MPC waveform when i _ref is 2.5A. (b) The proposed OSS-MPC waveform when i _ref is 2.5A. (c) The traditional OSS-MPC waveform when i _ref is 5A. (d) The proposed OSS-MPC waveform when i _ref is 5A. FIG9 compares the harmonic spectra of the output current of the traditional and the OSS-MPC algorithms proposed in this application. In FIG9, (a) The harmonic spectrum of the traditional OSS-MPC when i _ref is 2.5A. (b) The harmonic spectrum of the proposed OSS-MPC when i _ref is 2.5A. (c) The harmonic spectrum of the traditional OSS-MPC when i _ref is 5A. (d) Harmonic spectrum of the proposed OSS-MPC when i _ref is 5A.

By observing FIG8, it can be found that the output current of the two algorithms can accurately track the reference current _iref . The upper DC voltage divider capacitor voltage can be effectively controlled, and its value is about 100V, which is half of the DC bus voltage. Both algorithms can achieve NP balance. In addition, it can be observed from FIG9 that when _iref is 5A, the total harmonic distortion (THD) of the output current of the traditional and the OSS-MPC algorithms proposed in this application are 3.94% and 3.77%, respectively. When the _iref current is 2.5A, the output current THD of the traditional OSS-MPC algorithm and the OSS-MMPC algorithm proposed in this application is increased to 7.66% and 7.58%, respectively. This is because the current reference is too small and the switching sequence containing a large voltage vector cannot be selected, resulting in a higher THD. In addition, the high-order harmonics are mainly distributed near the sampling frequency (16kHz) and near twice the sampling frequency (32kHz). In summary, the simplified OSS-MPC algorithm without weighting coefficients and the traditional OSS-MMPC algorithm with weighting coefficients both have good steady-state performance. It is worth noting that the THD of the simplified OSS-MPC algorithm without weighting coefficients proposed in this application is lower than that of the traditional OSS-MPC algorithm with weighting coefficients.

C. Dynamic performance analysis experiment

Figure 10: Experimental results of dynamic performance analysis. (a) The waveform of the traditional OSS-MPC when i _ref suddenly changes from 2.5A to 5A. (b) The waveform of the traditional OSS-MPC when i _ref suddenly changes from 5A to 2.5A. (c) The waveform of the proposed OSS-MPC when i _ref suddenly changes from 2.5A to 5A. (d) The waveform of the proposed OSS-MPC when i _ref suddenly changes from 5A to 2.5A.

Figure 10 shows the waveforms of the inverter output voltage V _AB , the upper DC voltage divider capacitor voltage V _P and the output current i _s of the traditional and proposed OSS-MPC algorithms when i _ref changes suddenly. The circles are the mutation points. Figures 10 (a) and 10 (b) show the waveforms of the traditional OSS-MPC when i _ref jumps from 2.5A to 5A and from 5A to 2.5A, respectively. Figures 10 (c) and 10 (d) show the waveforms of the proposed OSS-MPC algorithm when i _ref jumps from 2.5A to 5A and from 5A to 2.5A, respectively. It can be seen from the figures that both algorithms can quickly track the reference current and have similar dynamic performance when i _ref changes suddenly.

D.NP voltage balance experiment

In order to verify the NP voltage balancing ability of the proposed OSS-MPC algorithm, the NP voltage fluctuation is simulated by suddenly connecting a resistor in parallel to the upper DC voltage-dividing capacitor _VP .

The circuit diagram in Figure 11(a) shows the schematic diagram of NP fluctuation simulation in detail, using a manual switch _SX and a resistor R (100Ω) in series. Figures 11(b) and 11(c) are the waveforms of the upper DC voltage divider capacitor voltage V _P , the inverter output voltage V _AB and the output current i _s when the switch _SX is suddenly turned on and off under the proposed OSS-MPC algorithm, respectively.

It can be seen that, when the switch _SX is suddenly opened or closed, the fluctuation of the upper DC voltage divider capacitor voltage _VP of the OSS-MPC algorithm proposed in the present application can be ignored, and the NP voltage is well balanced.

Claims

An inverter predictive control method based on an optimal switching sequence model, wherein the inverter is a T-type single-phase three-level inverter, characterized in that the voltage state predictive control method comprises the following steps:

1) creating an output voltage model, wherein the output voltage model includes a plurality of small voltage vectors; 2) constructing an OSS-MPC prediction model, and predicting the output current at time k+1 according to the OSS-MPC prediction model at time k; 3) constructing a switching sequence set, wherein each constructed switching sequence includes two redundant small voltage vectors having opposite effects on the DC capacitor voltage, and a zero voltage vector or a large voltage vector having no effect on the DC capacitor voltage; 4) dynamically adjusting the DC capacitor voltage by adjusting the running time of the redundant small voltage vectors, thereby achieving NP balance; 5) dividing the switching sequence set by reference current, obtaining candidate switching sequences, and finding an optimal switching sequence among the candidate switching sequences; 6) controlling a switch sequence generator according to the optimal switching sequence to output a prediction control signal for controlling the inverter.
According to the inverter predictive control method based on the optimal switching sequence model according to claim 1, it is characterized in that the output current at the sampling time k+1 is predicted to be

In the above formula is the predicted current at time k+1, is the instantaneous current at time k.
According to the inverter predictive control method based on the optimal switching sequence model according to claim 1, it is characterized in that the switching sequence set includes four switching sequences.
According to the inverter predictive control method based on the optimal switching sequence model of claim 3, it is characterized in that the four switching sequences are divided into two groups of candidate switching sequences, each group includes two candidate switching sequences.
According to the inverter predictive control method based on the optimal switching sequence model of claim 4, it is characterized in that in step 5), the reference current is judged, and if the reference current is greater than 0, the optimal switching sequence is selected from the first group of candidate switching sequences; otherwise, the optimal switching sequence is selected from the second group of candidate switching sequences.
According to the inverter predictive control method based on the optimal switching sequence model of claim 5, it is characterized in that in step 5), the cost function of each candidate switching sequence is calculated, and the candidate switching sequence with the smallest cost function is taken as the optimal switching sequence.
According to the inverter predictive control method based on the optimal switching sequence model of claim 6, it is characterized in that in step 6), the switching sequence generator converts the optimal switching sequence into a duty cycle signal and a switching signal in sequence, and then outputs the switching signal to the switching device in the inverter.