WO2024134444A1 - 半導体装置、及び、半導体装置の作製方法 - Google Patents

半導体装置、及び、半導体装置の作製方法 Download PDF

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WO2024134444A1
WO2024134444A1 PCT/IB2023/062853 IB2023062853W WO2024134444A1 WO 2024134444 A1 WO2024134444 A1 WO 2024134444A1 IB 2023062853 W IB2023062853 W IB 2023062853W WO 2024134444 A1 WO2024134444 A1 WO 2024134444A1
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layer
insulating layer
conductive layer
region
transistor
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PCT/IB2023/062853
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English (en)
French (fr)
Japanese (ja)
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黒崎大輔
田邉美和
保本清治
肥塚純一
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株式会社半導体エネルギー研究所
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Priority to JP2024565387A priority Critical patent/JPWO2024134444A1/ja
Priority to CN202380083759.8A priority patent/CN120323103A/zh
Priority to KR1020257022974A priority patent/KR20250127097A/ko
Publication of WO2024134444A1 publication Critical patent/WO2024134444A1/ja

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00—Electroluminescent light sources
    • H05B33/12—Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14—Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • H10K39/34—Organic image sensors integrated with organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device having a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • Semiconductor devices having transistors are widely used in electronic devices. For example, in display devices, by reducing the area occupied by transistors, the pixel size can be reduced and higher definition can be achieved. For this reason, there is a demand for miniaturization of transistors.
  • Devices requiring high-definition display devices such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • display devices for example, light-emitting devices having organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs: Light Emitting Diodes) have been developed.
  • organic EL Electro Luminescence
  • LEDs Light Emitting Diodes
  • Patent document 1 discloses a high-definition display device that uses organic EL elements.
  • the on-state current of the transistor may become small. This may slow down the operating speed of a semiconductor device having a transistor. For example, when the operating speed of a semiconductor device in a display device becomes slow, the frame frequency may decrease.
  • An object of one embodiment of the present invention is to provide a transistor with a large on-state current. Or, an object of the present invention is to provide a transistor with good electrical characteristics. Or, an object of the present invention is to provide a transistor with a fine size. Or, an object of the present invention is to provide a transistor with a small channel length. Or, an object of the present invention is to provide a semiconductor device including such a transistor.
  • Another object is to provide a semiconductor device that operates at high speed.
  • Another object is to provide a semiconductor device that occupies a small area.
  • Another object is to provide a semiconductor device with low wiring resistance.
  • Another object is to provide a semiconductor device or display device with low power consumption.
  • Another object is to provide a highly reliable transistor, semiconductor device, or display device.
  • Another object is to provide a display device with a high frame frequency.
  • Another object is to provide a display device that can be easily made high-definition.
  • Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity.
  • Another object is to provide a novel transistor, semiconductor device, display device, and a manufacturing method thereof.
  • One aspect of the present invention is a semiconductor device having a first insulating layer, a second insulating layer, a first conductive layer, and a metal oxide layer, the first conductive layer being provided on the first insulating layer, the second insulating layer being provided on the first conductive layer, a first opening being provided in the second insulating layer that reaches the first conductive layer, the metal oxide layer being located inside the first opening and having a region in contact with the first conductive layer, and the first insulating layer containing hydrogen.
  • the second insulating layer may have a first layer and a second layer on the first layer, the first layer having a region in contact with the first insulating layer, and the first insulating layer may have a region in which the hydrogen content is equal to or greater than the hydrogen content of the first layer.
  • the hydrogen diffusion coefficient of the first layer may be smaller than the hydrogen diffusion coefficient of the first conductive layer.
  • the second layer may contain oxygen.
  • the semiconductor device may have a second conductive layer, the second conductive layer being provided on the second insulating layer, the second conductive layer being provided with a second opening having a region overlapping with the first opening, and the second conductive layer having a region in contact with the metal oxide layer.
  • the semiconductor device may have a second conductive layer, the second conductive layer being provided on a second insulating layer, the second conductive layer being provided with a second opening having a region overlapping with the first opening, the second conductive layer having a region in contact with the metal oxide layer, the second insulating layer having a third layer on the second layer and a fourth layer on the third layer, the fourth layer having a region in contact with the second conductive layer, and the fourth layer having a region in which the hydrogen content is equal to or greater than the hydrogen content of the third layer.
  • the semiconductor device may have a third insulating layer and a third conductive layer, the third insulating layer being provided on the metal oxide layer so as to have a region located inside the first opening, and the third conductive layer being provided inside the first opening so as to have a region facing the metal oxide layer with the third insulating layer sandwiched between them.
  • the hydrogen content of the first insulating layer, the first layer, the third layer, and the fourth layer may be measured using SIMS.
  • the hydrogen diffusion coefficient of the third layer may be smaller than the hydrogen diffusion coefficient of the second conductive layer.
  • the hydrogen diffusion coefficients of the first conductive layer, the second conductive layer, the first layer, and the second layer may be measured using TDS or SIMS.
  • the third layer may contain the same material as the material contained in the first layer
  • the fourth layer may contain the same material as the material contained in the first insulating layer.
  • one aspect of the present invention is a method for manufacturing a semiconductor device, which includes forming a first insulating layer containing hydrogen, forming a first conductive layer on the first insulating layer, forming a second insulating layer on the first conductive layer, forming a second conductive layer on the second insulating layer, forming a first opening having a region overlapping with the first conductive layer by processing the second conductive layer, forming a second opening reaching the first conductive layer by processing the second insulating layer so as to have a region overlapping with the first opening, forming a metal oxide layer having a region located inside the second opening and having a region in contact with the first conductive layer and a region in contact with the second conductive layer, forming a third insulating layer on the metal oxide layer so as to have a region located inside the second opening, and forming a third conductive layer so as to have a region facing the third insulating layer sandwiched between the metal oxide layer and the third insulating layer inside the second opening.
  • a first layer having an area in contact with the first insulating layer and a second layer on the first layer are formed as the second insulating layer, and the proportion of hydrogen-containing molecules in the deposition gas for the first layer may be equal to or less than the proportion of hydrogen-containing molecules in the deposition gas for the first insulating layer.
  • the first layer may be formed so that the hydrogen diffusion coefficient of the first layer is smaller than the hydrogen diffusion coefficient of the first conductive layer.
  • oxygen may be supplied to the second layer after the second layer is formed and before the second conductive layer is formed.
  • a third layer on the second layer and a fourth layer on the third layer may be formed as the second insulating layer, the proportion of hydrogen-containing molecules in the deposition gas for the fourth layer being equal to or greater than the proportion of hydrogen-containing molecules in the deposition gas for the third layer, and the second conductive layer may be formed so as to have an area in contact with the fourth layer.
  • the third layer may be formed so that the hydrogen diffusion coefficient of the third layer is smaller than the hydrogen diffusion coefficient of the second conductive layer.
  • the third layer may be formed to contain the same material as the material contained in the first layer
  • the fourth layer may be formed to contain the same material as the material contained in the first insulating layer.
  • One aspect of the present invention can provide a transistor with a large on-state current. Or a transistor with good electrical characteristics can be provided. Or a transistor with a small size can be provided. Or a transistor with a small channel length can be provided. Or a semiconductor device including such a transistor can be provided.
  • a semiconductor device that operates at high speed can be provided.
  • a semiconductor device that occupies a small area can be provided.
  • a semiconductor device with low wiring resistance can be provided.
  • a semiconductor device or display device with low power consumption can be provided.
  • a highly reliable transistor, semiconductor device, or display device can be provided.
  • a display device with a high frame frequency can be provided.
  • a display device that can be easily made high-definition can be provided.
  • a method for manufacturing a semiconductor device or display device with high productivity can be provided.
  • a novel transistor, semiconductor device, display device, and a method for manufacturing these can be provided.
  • Fig. 1A is a plan view showing a configuration example of a semiconductor device
  • Fig. 1B and Fig. 1C are cross-sectional views showing the configuration example of the semiconductor device.
  • 2A to 2D are perspective views showing configuration examples of a semiconductor device.
  • 3A is a plan view showing a configuration example of a semiconductor device
  • FIG. 3B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 4A and 4B are cross-sectional views showing a configuration example of a semiconductor device.
  • 5A and 5B are cross-sectional views showing a configuration example of a semiconductor device.
  • Fig. 6A is a plan view showing a configuration example of a semiconductor device
  • FIG. 6C are cross-sectional views showing the configuration example of a semiconductor device.
  • 7A and 7B are plan and cross-sectional views illustrating a configuration example of a semiconductor device.
  • 8A and 8B are cross-sectional views showing a configuration example of a semiconductor device.
  • 9A to 9C are cross-sectional views showing configuration examples of a semiconductor device.
  • 10A to 10C are cross-sectional views showing configuration examples of a semiconductor device.
  • Fig. 11A is a plan view showing a configuration example of a semiconductor device
  • Fig. 11B and Fig. 11C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 12A is a plan view showing a configuration example of a semiconductor device
  • FIG. 12C are cross-sectional views showing the configuration example of a semiconductor device.
  • Fig. 13A is a plan view showing a configuration example of a semiconductor device
  • Fig. 13B and Fig. 13C are cross-sectional views showing the configuration example of the semiconductor device.
  • 14A is a plan view showing a configuration example of a semiconductor device
  • FIG 14B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 15A and 15B are cross-sectional views showing a configuration example of a semiconductor device.
  • Fig. 16A is a plan view showing a configuration example of a semiconductor device
  • Fig. 16B and Fig. 16C are cross-sectional views showing the configuration example of a semiconductor device.
  • 17A and 17B are cross-sectional views showing a configuration example of a semiconductor device.
  • 18A to 18C are plan views showing examples of opening shapes.
  • 19A to 19D are circuit diagrams showing configuration examples of a semiconductor device.
  • 20A and 20B are cross-sectional views showing a configuration example of a semiconductor device.
  • 21A is a plan view showing a configuration example of a semiconductor device, and
  • FIG 21B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 22A and 22B are cross-sectional views showing a configuration example of a semiconductor device.
  • 23A is a plan view showing a configuration example of a semiconductor device, and
  • FIG 23B is a cross-sectional view showing the configuration example of a semiconductor device.
  • 24A to 24D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 25A to 25C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 26A and 26B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • 27A and 27B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
  • FIG. 28 is a perspective view showing a configuration example of a display device.
  • 29A and 29B are cross-sectional views showing a configuration example of a display device.
  • FIG. 30 is a cross-sectional view showing a configuration example of a display device.
  • 31A to 31C are cross-sectional views showing configuration examples of a display device.
  • FIG. 32A and 32B are cross-sectional views showing a configuration example of a display device.
  • FIG. 33 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 34 is a cross-sectional view showing a configuration example of a display device.
  • FIG. 35 is a cross-sectional view showing a configuration example of a display device.
  • 36A and 36B are cross-sectional views showing a configuration example of a display device.
  • 37A to 37D are diagrams showing an example of an electronic device.
  • 38A to 38F are diagrams showing an example of an electronic device.
  • 39A to 39G are diagrams showing an example of an electronic device.
  • FIG. 40 is a cross-sectional view showing the structure of a sample of the example.
  • 41A and 41B are graphs showing the carrier concentration and contact resistance of the sample of the example.
  • 42A and 42B are graphs showing the carrier concentration and contact resistance of the sample of the example.
  • FIG. 43 is a graph showing the carrier concentration and contact resistance of the sample of the example.
  • FIG. 44 is a graph showing the Id-Vg characteristics and the field-effect mobility of the transistor of the example.
  • FIG. 45 is a graph showing the Id-Vg characteristics and the field-effect mobility of the transistor of the example.
  • 46A and 46B are graphs showing probability distributions of threshold voltage and field effect mobility of the transistors of the example.
  • 47A and 47B are graphs showing the channel length and the variation in threshold voltage of the transistor of the example.
  • 48 is a graph showing the Id-Vg characteristics and the field-effect mobility of the transistor of the example.
  • 49A and 49B are graphs showing probability distributions of threshold voltage and drain current of the transistors of the example; 50A and 50B are graphs showing the channel length and the variation in threshold voltage of the transistor of the example.
  • 51A and 51B are graphs showing the Id-Vg characteristics and the change over time in threshold voltage of the transistor of the example.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances or situation.
  • conductive layer can be changed to the term “conductive film.”
  • insulating layer can be changed to the term “insulating film.”
  • semiconductor layer can be changed to the term “semiconductor film.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conduction.
  • transistor includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, capacitive elements, and other elements with various functions.
  • the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (higher than Vth for a p-channel transistor).
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that “top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned.
  • the top surface shape of a certain component refers to the contour shape of the component when viewed from a planar view.
  • a planar view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.
  • a tapered shape refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed.
  • the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a fine curvature, or approximately planar with fine irregularities.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • a nitride oxide refers to a material whose composition contains more nitrogen than oxygen.
  • an oxide film includes a film having an oxynitride, and a nitride film includes a film having a nitride oxide.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, which increases the freedom to select materials and configurations and makes it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer may be referred to as the "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as the “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as the "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes or characteristics.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • the layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be called a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • the source electrode and the drain electrode are located at different heights, and a current flows in the semiconductor layer in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor of one embodiment of the present invention can also be called a vertical transistor or a vertical channel transistor, etc.
  • an insulating layer that functions as a spacer is provided between a lower electrode, which is one of the source and drain electrodes of the transistor, and an upper electrode, which is the other.
  • the insulating layer that functions as a spacer may be simply referred to as a spacer, but spacer may also be interpreted as an insulating layer.
  • the spacer is provided with a first opening that reaches the lower electrode, and the upper electrode is provided with a second opening having a region that overlaps with the first opening.
  • a semiconductor layer in which a channel is formed is provided so as to have a region in contact with the lower electrode and a region in contact with the upper electrode, and also a region located inside the first opening and a region located inside the second opening.
  • a gate insulating layer and a gate electrode are provided overlapping with the semiconductor layer. Since the source electrode, semiconductor layer, and drain electrode can be provided overlapping with each other, the occupied area can be significantly reduced compared to so-called planar type transistors in which the semiconductor layer is arranged on a flat surface.
  • a layer containing a metal oxide (also referred to as an oxide semiconductor) exhibiting semiconductor characteristics can be used as the semiconductor layer of the transistor of one embodiment of the present invention.
  • a layer containing a metal oxide exhibiting semiconductor characteristics is referred to as a metal oxide layer or an oxide semiconductor layer.
  • metal oxides that can be used for the semiconductor layer include oxides containing indium, oxides containing gallium, and oxides containing zinc.
  • metal oxides that can be used for the semiconductor layer include indium oxide, indium zinc oxide, and indium gallium zinc oxide.
  • the on-current of the transistor may become small.
  • a transistor is provided on a base insulating layer containing hydrogen.
  • a base insulating layer containing hydrogen is provided on a substrate
  • a lower electrode of the transistor is provided on the base insulating layer
  • a metal oxide layer is provided on the lower electrode.
  • the lower electrode of the transistor is provided so as to have a region in contact with the upper surface of the base insulating layer containing hydrogen
  • the metal oxide layer is provided so as to have a region in contact with the upper surface of the lower electrode.
  • hydrogen contained in the base insulating layer permeates the lower electrode and is supplied to the region of the metal oxide layer that is in contact with the lower electrode and a region nearby the region.
  • the base insulating layer has at least a region in which the hydrogen content per unit volume is equal to or greater than the hydrogen content per unit volume of the spacer.
  • content may refer to the content per unit volume or unit area.
  • V O H oxygen vacancies
  • a defect in which hydrogen is introduced into the oxygen vacancy (hereinafter referred to as V O H) functions as a donor, and electrons that are carriers are generated.
  • a part of hydrogen may bond with oxygen that is bonded to a metal atom to generate electrons that are carriers.
  • the generation of electrons that are carriers in the metal oxide layer reduces the resistance of the metal oxide layer.
  • the contact resistance between the metal oxide layer and the lower electrode can be reduced. This increases the on-current of the transistor, and improves the electrical characteristics. Therefore, a semiconductor device that operates at high speed can be realized.
  • the spacer may have a single layer structure or a laminated structure of multiple layers.
  • the spacer may have a three-layer laminated structure of a first insulating layer, a second insulating layer on the first insulating layer, and a third insulating layer on the second insulating layer.
  • the spacer may also have a four-layer laminated structure in which a fourth insulating layer is provided on the third insulating layer.
  • the first insulating layer can be made of a material through which hydrogen is less likely to diffuse.
  • the first insulating layer can be made of a material through which hydrogen is less likely to diffuse than the first conductive layer, and can be made of a material through which hydrogen is less likely to diffuse than the second insulating layer.
  • the first insulating layer can be made of a material having a smaller hydrogen diffusion coefficient than the first conductive layer, and can be made of a material having a smaller hydrogen diffusion coefficient than the second insulating layer. This can prevent hydrogen contained in the base insulating layer from being supplied to a region of the metal oxide layer away from the region where the lower electrode and the metal oxide layer are in contact.
  • the base insulating layer can prevent hydrogen contained in the base insulating layer from being supplied to a region of the metal oxide layer that is in contact with the second insulating layer.
  • the channel length of the transistor is reduced, and the threshold voltage of the transistor is reduced, that is, a negative shift in the threshold voltage can be prevented.
  • This can reduce the cutoff current and realize a transistor with normally-off characteristics (i.e., a threshold voltage of a positive value). Therefore, the reliability of the transistor of one embodiment of the present invention can be improved, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • a layer containing oxygen can be used for the second insulating layer.
  • the second insulating layer can have a region with a higher oxygen content than at least one of the first insulating layer, the third insulating layer, and the fourth insulating layer. This allows oxygen to be supplied to a region of the metal oxide layer that is not in contact with either the lower electrode or the upper electrode. Thus, oxygen can be supplied to the channel formation region of the metal oxide layer. This reduces oxygen vacancies in the metal oxide layer, making it easier to form an i-type channel formation region.
  • the electrical characteristics of the transistor of one embodiment of the present invention can be improved and the reliability can be increased. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be increased.
  • the third insulating layer can be made of a material that is difficult for hydrogen to diffuse into.
  • the third insulating layer can be made of, for example, a material that can be used for the first insulating layer.
  • the first insulating layer and the third insulating layer can be made of a material through which not only hydrogen but also oxygen is less likely to diffuse.
  • the first insulating layer and the third insulating layer can be made of a material through which oxygen is less likely to diffuse than the second insulating layer, for example.
  • the first insulating layer and the third insulating layer can be made of a material with a smaller oxygen diffusion coefficient than the second insulating layer, for example.
  • a nitride insulating film can be used for the first insulating layer and the third insulating layer, and an oxide insulating film can be used for the second insulating layer.
  • a silicon nitride film or a silicon nitride oxide film can be used for the first insulating layer and the third insulating layer, and a silicon oxide film or a silicon oxynitride film can be used for the second insulating layer.
  • the fourth insulating layer can be provided to have a region in contact with the lower surface of the upper electrode, and can contain hydrogen.
  • hydrogen contained in the fourth insulating layer permeates the upper electrode and is supplied to the region of the metal oxide layer in contact with the upper electrode and the region in the vicinity thereof.
  • the contact resistance between the metal oxide layer and the upper electrode can be reduced.
  • the on-current of the transistor can be increased and the electrical characteristics can be improved.
  • a semiconductor device that operates at high speed can be realized.
  • the fourth insulating layer by using a material that does not easily diffuse hydrogen for the third insulating layer provided under the fourth insulating layer, it is possible to suppress the hydrogen contained in the fourth insulating layer from being supplied to, for example, a region of the metal oxide layer that is distant from the upper electrode and the fourth insulating layer. For example, it is possible to suppress the hydrogen contained in the fourth insulating layer from being supplied to a region of the metal oxide layer that is in contact with the fourth insulating layer. As a result, the channel length of the transistor is reduced, and a negative shift in the threshold voltage of the transistor can be suppressed. As a result, the cut-off current can be reduced, and a transistor with normally-off characteristics can be realized. Therefore, the reliability of the transistor of one embodiment of the present invention can be improved, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • the base insulating layer and the fourth insulating layer have regions where the hydrogen content is, for example, equal to or greater than the hydrogen content of the first insulating layer and equal to or greater than the hydrogen content of the third insulating layer.
  • the first insulating layer and the third insulating layer have regions where the hydrogen content is, for example, equal to or less than the hydrogen content of the base insulating layer and equal to or less than the hydrogen content of the fourth insulating layer.
  • the base insulating layer and the fourth insulating layer can have the same hydrogen content per unit volume.
  • the fourth insulating layer can be made of a material that can be used for the base insulating layer.
  • a nitride insulating film can be used as the base insulating layer and the fourth insulating layer.
  • the nitride insulating film include silicon nitride and silicon nitride oxide.
  • the silicon nitride film and the silicon nitride oxide film can be made into films that release a lot of hydrogen by changing the film formation conditions (for example, film formation gas or power during film formation), so they can be suitably used as the base insulating layer and the fourth insulating layer.
  • the base insulating layer and the fourth insulating layer contain the same material and have the same hydrogen content per unit volume
  • the base insulating layer and the fourth insulating layer can be formed under the same conditions.
  • ⁇ Configuration Example 1 of Semiconductor Device> 1A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100. Some components, such as an insulating layer, are not illustrated in FIG. Some components are also not illustrated in the plan views illustrated later.
  • FIG. 1B is a cross-sectional view taken along dashed lines A1-A2 in FIG. 1A
  • FIG. 1C is a cross-sectional view taken along dashed lines B1-B2 in FIG. 1A
  • FIG. 2A is a perspective view corresponding to the configuration example in FIGS. 1A to 1C. In the example shown in FIG. 2A, some of the elements shown in FIGS. 1A to 1C, such as some insulating layers, are omitted.
  • a semiconductor device includes a substrate 102, an insulating layer 101 functioning as a base insulating layer over the substrate 102, an insulating layer 110 over the insulating layer 101, and a transistor 100.
  • the transistor 100 includes a conductive layer 112a, a semiconductor layer 108, a conductive layer 112b, an insulating layer 106, and a conductive layer 104.
  • Each layer included in the transistor 100 may have a single-layer structure or a stacked-layer structure.
  • the conductive layer 112a is provided on the insulating layer 101 so as to have a region in contact with the top surface of the insulating layer 101.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of the transistor 100.
  • the insulating layer 110 is provided on the insulating layer 101 and on the conductive layer 112a.
  • the insulating layer 110 can have a region in contact with the upper surface of the insulating layer 101, a region in contact with the upper surface of the conductive layer 112a, and a region in contact with the side surface of the conductive layer 112a.
  • the insulating layer 110 is provided with an opening 141 that reaches the conductive layer 112a.
  • the conductive layer 112b is provided on the insulating layer 110.
  • the conductive layer 112b can have a region in contact with the top surface of the insulating layer 110.
  • the conductive layer 112b has an opening 143 having a region overlapping with the opening 141.
  • the conductive layer 112b functions as the other of the source electrode or drain electrode of the transistor 100.
  • the conductive layer 112a is provided under the insulating layer 110, and the conductive layer 112b is provided on the insulating layer 110. Therefore, the conductive layer 112a can be called the lower electrode of the transistor 100, and the conductive layer 112b can be called the upper electrode of the transistor 100. As described above, the conductive layer 112a functions as one of the source electrode or drain electrode of the transistor 100, and the conductive layer 112b functions as the other of the source electrode or drain electrode of the transistor 100. As described above, the transistor 100 is a transistor in which one of the source electrode or drain electrode is the lower electrode and the other of the source electrode or drain electrode is the upper electrode. In addition, the insulating layer 110 functions as a spacer that controls the distance between the lower electrode and the upper electrode of the transistor 100.
  • the insulating layer 110 has a laminated structure of insulating layer 110a on insulating layer 101 and on conductive layer 112a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b.
  • Figures 1B and 1C show an example in which the insulating layer 110 has a three-layer laminated structure.
  • the insulating layer 110a can have a region in contact with the upper surface of the insulating layer 101, a region in contact with the upper surface of the conductive layer 112a, and a region in contact with the side surface of the conductive layer 112a.
  • the insulating layer 110c can have a region in contact with the lower surface of the conductive layer 112b.
  • the conductive layer 112b can have a region in contact with the upper surface of the insulating layer 110c.
  • FIG. 2B is a diagram showing the insulating layer 101, the conductive layer 112a, the conductive layer 112b, the opening 141, and the opening 143 from the perspective view shown in FIG. 2A.
  • the opening 141 provided in the insulating layer 110 is shown by a dashed line.
  • the conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a. It is preferable that the conductive layer 112b is not provided inside the opening 141. In other words, it is preferable that the conductive layer 112b does not have a region that contacts the side of the insulating layer 110 on the opening 141 side.
  • the semiconductor layer 108 has a region located inside the opening 141 and a region located inside the opening 143.
  • the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side surface of the conductive layer 112b.
  • the semiconductor layer 108 has a region in contact with the end of the insulating layer 110 on the opening 141 side (also referred to as the side wall of the opening 141) and the end of the conductive layer 112b on the opening 143 side (also referred to as the side wall of the opening 143).
  • the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a inside the opening 141.
  • the semiconductor layer 108 is provided over the conductive layer 112a and the conductive layer 112b.
  • the conductive layer 112a is provided over the insulating layer 101.
  • the conductive layer 112a is provided between the insulating layer 101 and the semiconductor layer 108.
  • the insulating layer 101 is an insulating layer containing hydrogen.
  • the insulating layer 101 is an insulating layer having a region in which the hydrogen content per unit volume is equal to or greater than the hydrogen content per unit volume of the insulating layer 110.
  • the semiconductor layer 108 is a layer containing a material that is reduced in resistance by supplying hydrogen.
  • the semiconductor layer 108 is a layer containing an oxide semiconductor, which is a metal oxide that exhibits semiconductor characteristics.
  • the semiconductor layer 108 is also referred to as a metal oxide layer or an oxide semiconductor layer.
  • metal oxides that can be used for the semiconductor layer 108 include oxides containing indium, oxides containing gallium, and oxides containing zinc.
  • metal oxides that can be used for the semiconductor layer 108 include indium oxide, indium zinc oxide, and indium gallium zinc oxide. Note that the insulating layer 101 does not need to contain hydrogen as long as it contains a material that reduces the resistance of the semiconductor layer 108 when supplied to the semiconductor layer 108.
  • the hydrogen contained in the insulating layer 101 permeates the conductive layer 112a and is supplied to the region of the semiconductor layer 108 that is in contact with the conductive layer 112a and to the region nearby the conductive layer 112a.
  • the semiconductor layer 108 contains a material that is reduced in resistance when hydrogen is supplied. Therefore, by supplying hydrogen to the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, the contact resistance between the semiconductor layer 108 and the conductive layer 112a can be reduced. This increases the on-current of the transistor 100 and improves the electrical characteristics. Therefore, a semiconductor device that operates at high speed can be realized.
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectroscopy
  • the hydrogen content is preferably measured using SIMS, since it can be measured with high sensitivity.
  • TDS thermal desorption spectroscopy
  • FIG. 2C is a diagram showing the insulating layer 101, the conductive layer 112a, the semiconductor layer 108, the opening 141, and the opening 143 from the perspective view shown in FIG. 2A.
  • the semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143.
  • FIG. 1B and FIG. 1C an example is shown in which the end of the semiconductor layer 108 is provided on the upper surface of the conductive layer 112b, but for example, the semiconductor layer 108 may cover the end of the conductive layer 112b, and the end of the semiconductor layer 108 may be provided on the insulating layer 110.
  • the insulating layer 106 is provided on the insulating layer 110, the semiconductor layer 108, and the conductive layer 112b.
  • the insulating layer 106 is provided on the semiconductor layer 108 so as to have a region located inside the opening 141 and a region located inside the opening 143.
  • the insulating layer 106 is provided along the sidewall of the opening 141 and the sidewall of the opening 143 via the semiconductor layer 108.
  • the insulating layer 106 functions as a gate insulating layer of the transistor.
  • the conductive layer 104 is provided on the insulating layer 106.
  • the conductive layer 104 is provided so as to have a region located inside the opening 141 and a region facing the semiconductor layer 108 with the insulating layer 106 sandwiched between the conductive layer 104 and the semiconductor layer 108 inside the opening 143.
  • the conductive layer 104 is provided so as to have a region overlapping with the semiconductor layer 108 via the insulating layer 106 inside the openings 141 and 143.
  • the conductive layer 104 functions as a gate electrode of the transistor 100.
  • FIG. 2D is a diagram showing the insulating layer 101, the conductive layer 112a, the conductive layer 104, the opening 141, and the opening 143 from the perspective view shown in FIG. 2A.
  • the conductive layer 104 is provided so as to cover the opening 141 and the opening 143.
  • the conductive layers 112a, 112b, and 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • An insulating layer 109 is provided on the conductive layer 104 and on the insulating layer 106.
  • the insulating layer 109 is provided so as to cover the conductive layer 104.
  • the insulating layer 109 functions as a protective layer. It is preferable to use a material that does not easily diffuse impurities for the insulating layer 109. By providing the insulating layer 109, it is possible to suitably suppress the diffusion of impurities from the outside into the transistor 100, and to improve the reliability of the semiconductor device. Examples of impurities include water and hydrogen.
  • the insulating layer 109 has one or both of an inorganic insulating film and an organic insulating film.
  • the insulating layer 109 may have a stacked structure of an inorganic insulating film and an organic insulating film.
  • the insulating layer 109 can be made of a material that can be used for the insulating layer 110.
  • inorganic insulating films that can be used for the insulating layer 109 include oxide insulating films and nitride insulating films.
  • the insulating layer 109 can be made of one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate.
  • an organic insulating film is used for the insulating layer 109, for example, one or both of acrylic resin and polyimide resin can be used.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • FIG. 3A is a plan view showing an example of the configuration of a semiconductor device according to one embodiment of the present invention, and shows an example of the configuration of a transistor 100.
  • the diameter D143 and the channel width W100 are shown in the plan view shown in FIG. 1A.
  • FIG. 3B is an enlarged view including the configuration shown in FIG. 1B, showing an example of the configuration of a transistor 100.
  • the diameter D143, the channel width W100, the channel length L100, the thickness T110, and the angle ⁇ 110 are shown.
  • FIG. 4A is an enlarged view of the semiconductor layer 108 and the area nearby shown in FIG. 3B.
  • the region in contact with the conductive layer 112a functions as one of the source region and the drain region
  • the region in contact with the conductive layer 112b functions as the other of the source region and the drain region.
  • the semiconductor layer 108 has a channel formation region between the source region and the drain region.
  • the insulating layer 101 is an insulating layer containing hydrogen
  • the semiconductor layer 108 is a layer containing a material that is reduced in resistance by supplying hydrogen.
  • the semiconductor layer 108 is a metal oxide layer
  • oxygen that is bonded to a metal atom contained in the semiconductor layer 108 reacts with hydrogen to form water, and oxygen vacancies (V O ) are formed in the metal oxide.
  • part of hydrogen may be bonded to oxygen that is bonded to a metal atom to generate electrons that are carriers.
  • the resistance of the semiconductor layer 108 is reduced.
  • the insulating layer 101 does not need to contain hydrogen as long as it contains a material that reduces the resistance of the semiconductor layer 108 when supplied to the semiconductor layer 108 .
  • FIG. 3B and 4A an example of the state in which hydrogen contained in the insulating layer 101 is supplied to the semiconductor layer 108 is shown by a dashed single arrow.
  • the hydrogen contained in the insulating layer 101 passes through the conductive layer 112a and is supplied to the region of the semiconductor layer 108 that is in contact with the conductive layer 112a and the region nearby.
  • the region of the semiconductor layer 108 that is in contact with the conductive layer 112a and the region nearby becomes a low resistance region.
  • the low resistance region is referred to as region 108n.
  • Region 108n functions as the source region or drain region of the transistor 100.
  • the contact resistance between the semiconductor layer 108 and the conductive layer 112a can be reduced. This increases the on-state current of the transistor 100 and improves the electrical characteristics. This makes it possible to realize a semiconductor device that operates at high speed.
  • the insulating layer 101 can be made of a material that can be used for the insulating layer 110.
  • a nitride insulating film and an oxide insulating film can be used for the insulating layer 101.
  • the nitride insulating film include a silicon nitride film, a silicon nitride oxide film, and an aluminum nitride film.
  • the oxide insulating film include a silicon oxynitride film, a silicon oxide film, an aluminum oxynitride film, an aluminum oxide film, a hafnium oxide film, and a hafnium aluminate film.
  • the insulating layer 101 it is preferable to use one or both of a silicon nitride film and a silicon nitride oxide film for the insulating layer 101, because the insulating layer 101 can be made into a film that releases a lot of hydrogen by changing the film formation conditions (for example, the film formation gas or the power during film formation).
  • the insulating layer 101 is preferably a layer that releases hydrogen when heated.
  • hydrogen can be suitably supplied to the semiconductor layer 108.
  • the thickness of the insulating layer 101 is preferably 1 nm or more and 500 nm or less, more preferably 5 nm or more and 500 nm or less, more preferably 5 nm or more and 200 nm or less, more preferably 10 nm or more and 200 nm or less, more preferably 30 nm or more and 200 nm or less, and even more preferably 50 nm or more and 200 nm or less.
  • the thickness of the insulating layer 101 is increased, the hydrogen content of the insulating layer 101 can be increased, and hydrogen can be suitably supplied to the semiconductor layer 108.
  • the productivity of the semiconductor device of one embodiment of the present invention decreases, and therefore, it is preferable to set the thickness in consideration of the productivity.
  • the insulating layer 110 is preferably made of an inorganic insulating film.
  • the inorganic insulating film include an oxide insulating film and a nitride insulating film.
  • the oxide insulating film include a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a magnesium oxide film, a gallium oxide film, a gallium oxynitride film, a germanium oxide film, an yttrium oxide film, an yttrium oxynitride film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a hafnium oxynitride film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film.
  • the nitride insulating film include a silicon nit
  • the insulating layer 110 has a region in contact with the semiconductor layer 108.
  • the semiconductor layer 108 is a metal oxide layer
  • the channel formation region is a high resistance region with a low carrier concentration. It can be said that the channel formation region is i-type (intrinsic) or substantially i-type.
  • the insulating layer 110b having a region in contact with the channel formation region of the semiconductor layer 108 is preferably a layer containing oxygen.
  • the insulating layer 110b preferably has a region containing more oxygen than one or both of the insulating layer 110a and the insulating layer 110c.
  • oxygen can be supplied to a region of the semiconductor layer 108 that is not in contact with either the conductive layer 112a or the conductive layer 112b.
  • oxygen can be supplied to a region of the semiconductor layer 108 that is in contact with the insulating layer 110b and a region in the vicinity thereof.
  • oxygen can be supplied to the channel formation region of the semiconductor layer 108.
  • oxygen vacancies in the semiconductor layer 108 can be reduced, and an i-type channel formation region can be easily formed.
  • the electrical characteristics of the transistor 100 can be improved and the reliability can be increased.
  • the reliability of the semiconductor device of one embodiment of the present invention can be improved. Note that the oxygen content can be measured by a method similar to that for measuring the hydrogen content.
  • the insulating layer 110b is preferably a film that releases oxygen when heated.
  • the insulating layer 110b releases oxygen due to heat applied during the manufacturing process of the transistor 100, and oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies in the semiconductor layer 108 can be reduced, and a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.
  • oxygen can be supplied to the insulating layer 110b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.
  • oxygen may be supplied to the insulating layer 110b by forming an oxide film on the upper surface of the insulating layer 110b in an oxygen atmosphere by a sputtering method. Then, the oxide film may be removed.
  • the insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the oxide insulating films described above for the insulating layer 110b. Specifically, it is preferable to use one or both of a silicon oxide film and a silicon oxynitride film for the insulating layer 110b.
  • the insulating layer 110a and the insulating layer 110c can each be made of a material through which hydrogen does not easily diffuse. This can prevent hydrogen from diffusing from the outside of the transistor to the semiconductor layer 108 through the insulating layer 110a or the insulating layer 110c.
  • a material through which hydrogen does not easily diffuse is used for the insulating layer 110a, it can prevent hydrogen contained in the insulating layer 101 from being supplied to, for example, a region of the semiconductor layer 108 that is away from the region where the conductive layer 112a and the semiconductor layer 108 are in contact with each other.
  • it can prevent hydrogen contained in the insulating layer 101 from being supplied to a region of the semiconductor layer 108 that is in contact with the insulating layer 110a.
  • the channel length of the transistor 100 is reduced, and the threshold voltage of the transistor 100 is reduced, that is, a negative shift in the threshold voltage can be prevented.
  • This can reduce the cutoff current and realize a transistor with normally-off characteristics. Therefore, the reliability of the transistor 100 can be improved, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • the insulating layer 110a may be made of a material in which hydrogen is less likely to diffuse than the conductive layer 112a, and may also be made of a material in which hydrogen is less likely to diffuse than the insulating layer 110b.
  • the insulating layer 110a may be made of a material in which hydrogen is less likely to diffuse than the conductive layer 112a, and may also be made of a material in which hydrogen is less likely to diffuse than the insulating layer 110b.
  • the insulating layer 110c may be made of a material in which hydrogen is less likely to diffuse than the conductive layer 112b ...
  • the hydrogen diffusion coefficient in the insulating layer 110c may be approximately the same as the hydrogen diffusion coefficient in the insulating layer 110a.
  • the insulating layer 110c may contain the same material as the insulating layer 110a.
  • the insulating layer 110c may use the same material as the insulating layer 110a.
  • the insulating layer 110a and the insulating layer 110c may be formed under the same conditions. Note that, for example, by differentiating the film formation time of the insulating layer 110a from the film formation time of the insulating layer 110c, the film thickness of the insulating layer 110a and the film thickness of the insulating layer 110c may be different.
  • the insulating layer 110a and the insulating layer 110c can be made of a material through which oxygen is less likely to diffuse than hydrogen.
  • the insulating layer 110a and the insulating layer 110c can be made of a material through which oxygen is less likely to diffuse than the insulating layer 110b.
  • the insulating layer 110a and the insulating layer 110c can be made of a material that has a smaller oxygen diffusion coefficient than the insulating layer 110b. This can prevent oxygen contained in the insulating layer 110b from permeating through the insulating layer 110a to the substrate 102 side due to heating, and from permeating through the insulating layer 110c to the conductive layer 112b and the insulating layer 106 side.
  • the oxygen contained in the insulating layer 110b can be trapped. This can suitably supply oxygen to the semiconductor layer 108.
  • the diffusion coefficients of hydrogen, oxygen, etc. can be calculated using, for example, TDS.
  • SIMS may be used.
  • the oxide insulating film and the nitride insulating film described above it is preferable to use one or more of the oxide insulating film and the nitride insulating film described above, respectively, and it is preferable to use one or more of a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, an aluminum nitride film, a hafnium oxide film, and a hafnium aluminate film.
  • nitride insulating films for the insulating layer 110a and the insulating layer 110c.
  • a silicon nitride film and a silicon nitride oxide film for the insulating layer 110a and the insulating layer 110c.
  • Silicon nitride film and silicon oxynitride film each emit little impurities (e.g., water and hydrogen) from themselves, and can be used as insulating layer 110a and insulating layer 110c because they can be formed into films that are difficult for oxygen and hydrogen to permeate.
  • impurities e.g., water and hydrogen
  • the insulating layer 110a and the insulating layer 110c may be formed of, for example, a film containing aluminum as described above.
  • a film containing aluminum as described above.
  • the aluminum oxide film is preferable because it can reduce the hydrogen content compared to a silicon nitride film.
  • the oxygen contained in the insulating layer 110b may oxidize the conductive layer 112a and the conductive layer 112b, resulting in an increase in electrical resistance.
  • the conductive layer 112a can be prevented from being oxidized and the resistance from increasing.
  • the conductive layer 112b can be prevented from being oxidized and the resistance from increasing.
  • the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108 increases, reducing oxygen deficiencies in the semiconductor layer 108.
  • the thicknesses of the insulating layers 110a and 110c are preferably 5 nm to 150 nm, more preferably 5 nm to 100 nm, more preferably 5 nm to 70 nm, even more preferably 10 nm to 70 nm, even more preferably 10 nm to 50 nm, and even more preferably 20 nm to 50 nm.
  • the thicknesses of the insulating layers 110a and 110c may be equal to or different from each other.
  • a silicon nitride film or a silicon nitride oxide film for the insulating layer 110a and the insulating layer 110c it is preferable to use a silicon nitride film or a silicon nitride oxide film for the insulating layer 110a and the insulating layer 110c, and a silicon oxide film or a silicon oxynitride film for the insulating layer 110b.
  • the insulating layer 110a may contain hydrogen depending on the film formation conditions.
  • the insulating layer 110a may contain hydrogen.
  • hydrogen may be supplied to the region of the semiconductor layer 108 that is in contact with the insulating layer 110a and the region nearby, and these regions may become low-resistance. In FIG. 4A, such a low-resistance region is referred to as the region 108na- .
  • the insulating layer 110c may contain hydrogen depending on the film formation conditions, and hydrogen may be supplied to the region of the semiconductor layer 108 that is in contact with the insulating layer 110c and the region nearby, and these regions may become low-resistance.
  • a low-resistance region is referred to as the region 108nb- .
  • the region 108na- functions as one of the source region or drain region of the transistor 100, and the region 108nb- functions as the other of the source region or drain region of the transistor 100.
  • a region of the semiconductor layer 108 that functions as a channel formation region of the transistor 100 is referred to as a region 108i.
  • the region 108i can be an i-type region.
  • the region 108na- and the region 108nb- may not be formed in the semiconductor layer 108 as shown in FIG. 4B.
  • the insulating layer 101 has a region in which the hydrogen content is equal to or greater than the hydrogen content of the insulating layer 110a.
  • the insulating layer 110a has a region in which the hydrogen content is equal to or less than the hydrogen content of the insulating layer 101.
  • the region 108na- and the region 108nb- shown in Fig. 4A can be regions having a lower electrical resistance than the region 108i and a higher electrical resistance than the region 108n.
  • the contact resistance between the semiconductor layer 108 and the conductive layer 112a can be reduced, and the channel length of the transistor 100 can be prevented from being reduced by supplying hydrogen to a region of the semiconductor layer 108 that is in contact with, for example, the insulating layer 110b. Therefore, the transistor 100 can have a large on-state current and high reliability.
  • the semiconductor device of one embodiment of the present invention can be a semiconductor device that operates at high speed and has high reliability.
  • the channel length and channel width of transistor 100 are explained below.
  • the channel length L100 of the transistor 100 is indicated by a dashed double-headed arrow.
  • the region of the semiconductor layer 108 that contacts the insulating layer 110b and the region nearby are made i-type and function as a channel formation region.
  • the region of the semiconductor layer 108 that contacts the insulating layer 110a and the region nearby, as well as the region that contacts the insulating layer 110c and the region nearby are low resistance regions as shown in FIG. 4A.
  • the channel length L100 can be the shortest distance between the part of the semiconductor layer 108 that contacts the insulating layer 110a and the part that contacts the insulating layer 110c in a cross-sectional view.
  • the channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110 of the insulating layer 110b and the angle ⁇ 110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, for example, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely small channel length that could not be realized with a conventional exposure device for mass production of flat panel displays for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m
  • a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L100 can be 100 nm or more and 1 ⁇ m or less.
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Therefore, by applying the semiconductor device of one embodiment of the present invention to a display device, the frame frequency of the display device can be increased.
  • the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained.
  • the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-resolution display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed.
  • the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L100 can be controlled by adjusting the thickness T110 and angle ⁇ 110 of the insulating layer 110b. Note that in FIG. 3B, the thickness T110 of the insulating layer 110b is indicated by a dashed double-headed arrow.
  • the thickness T110 of the insulating layer 110b can be, for example, 10 nm or more, 50 nm or more, 100 nm or more, 150 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and can be less than 3.0 ⁇ m, 2.5 ⁇ m or less, 2.0 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, or 1.0 ⁇ m or less.
  • the region of the semiconductor layer 108 that contacts the insulating layer 110a and the region nearby it, as well as the region that contacts the insulating layer 110c and the region nearby it, may be included in the channel formation region.
  • the channel length L100 can be the shortest distance between the part of the semiconductor layer 108 that contacts the conductive layer 112a and the part that contacts the conductive layer 112b in a cross-sectional view.
  • the channel length L100 corresponds to the sum of the lengths of the side surfaces of the insulating layers 110a, 110b, and 110c on the opening 141 side in a cross-sectional view.
  • the diameter D143 of opening 143 is indicated by a double-headed arrow with a two-dot chain line.
  • Figure 3A shows an example in which the top surface shape of openings 141 and 143 is a circle with diameter D143.
  • the channel width W100 of transistor 100 matches the circumference of the circle.
  • channel width W100 is ⁇ x D143. In this way, when the top surface shape of openings 141 and 143 is circular, it is possible to realize a transistor with a smaller channel width compared to other shapes.
  • the diameter of the opening 141 and the diameter of the opening 143 may differ from each other. Furthermore, the diameter of the opening 141 and the diameter of the opening 143 may each change in the depth direction.
  • the diameter of the opening may be, for example, the average value of the diameter at the highest point of the insulating layer 110 (or the insulating layer 110b) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these.
  • the diameter of the opening may be, for example, any of the diameters at the highest point of the insulating layer 110 (or the insulating layer 110b) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these.
  • the diameter D143 of the opening 143 is equal to or greater than the limit resolution of the exposure device.
  • the diameter D143 can be, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and less than 5.0 ⁇ m, 4.5 ⁇ m or less, 4.0 ⁇ m or less, 3.5 ⁇ m or less, 3.0 ⁇ m or less, 2.5 ⁇ m or less, 2.0 ⁇ m or less, 1.5 ⁇ m or less, or 1.0 ⁇ m or less.
  • the upper surface shape of the openings 141 and 143 is not limited, and each of them may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or any other polygon with rounded corners.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • the upper surface shape of the openings 141 and 143 is preferably a circle.
  • the top shape of the opening 141 refers to the shape of the top end of the insulating layer 110 on the opening 141 side.
  • the top shape of the opening 143 refers to the shape of the bottom end of the conductive layer 112b on the opening 143 side.
  • the top surface shapes of opening 141 and opening 143 can be made to match or roughly match each other.
  • the bottom surface end of conductive layer 112b on the opening 143 side match or roughly match the top surface end of insulating layer 110 on the opening 141 side.
  • the bottom surface of conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of insulating layer 110 refers to the surface on the conductive layer 112b side.
  • opening 141 and opening 143 do not have to be the same. Furthermore, when the top surface shapes of opening 141 and opening 143 are circular, opening 141 and opening 143 may or may not be concentric.
  • the side of the insulating layer 110b on the opening 141 side is preferably tapered or vertical.
  • the angle ⁇ 110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed is preferably 90 degrees or less.
  • the coverage of the layer (e.g., the semiconductor layer 108) provided on the insulating layer 110b can be improved.
  • Figures 1B, 1C, and 3B show an example in which the side of the insulating layer 110b on the opening 141 side is tapered (angle ⁇ 110 is less than 90 degrees).
  • Figures 5A and 5B show an example in which the side of the insulating layer 110b on the opening 141 side shown in Figures 1B and 1C, respectively, is vertical (angle ⁇ 110 is 90 degrees).
  • the angle ⁇ 110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and 90 degrees or less, 85 degrees or less, or 80 degrees or less.
  • the angle ⁇ 110 may also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.
  • the angle ⁇ 110 is 80 degrees or more and 90 degrees or less, it is preferable to form a film covering the insulating layer 110 using a film formation method with high coverage.
  • a film formation method with high coverage For example, it is preferable to form the conductive layer 104 by a CVD method, and the insulating layer 106 and the semiconductor layer 108 by an ALD method.
  • a film covering the insulating layer 110 may be formed using a film formation method with higher productivity.
  • the angle ⁇ 110 is set based on the insulating layer 110b, but it may be set based on the entire insulating layer 110.
  • the angle ⁇ 110 may be the angle between the side of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is to be formed (here, the upper surface of the conductive layer 112a).
  • 6A, 6B, 6C, 7A, 7B, 8A, and 8B are modified examples of the configurations shown in Fig. 1A, 1B, 1C, 3A, 3B, 4A, and 4B, respectively, in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c.
  • the insulating layer 110 has a four-layer laminated structure.
  • the insulating layer 110d can have a region that contacts the lower surface of the conductive layer 112b.
  • the conductive layer 112b can have a region that contacts the upper surface of the insulating layer 110d.
  • the insulating layer 110d is an insulating layer containing hydrogen
  • the semiconductor layer 108 is a layer containing a material that is reduced in resistance by supplying hydrogen, such as a metal oxide layer. Note that the insulating layer 110d does not need to contain hydrogen as long as it contains a material that is reduced in resistance by supplying hydrogen to the semiconductor layer 108.
  • FIGs 7B, 8A, and 8B in addition to an example of how hydrogen contained in the insulating layer 101 is supplied to the semiconductor layer 108, an example of how hydrogen contained in the insulating layer 110d is supplied to the semiconductor layer 108 is shown by a dashed single arrow.
  • the hydrogen contained in the insulating layer 110d permeates the conductive layer 112b and is supplied to the region of the semiconductor layer 108 that contacts the conductive layer 112b and the region nearby.
  • the region of the semiconductor layer 108 that contacts the conductive layer 112b and the region nearby becomes the region 108nb, which is a low resistance region.
  • the region 108nb is also formed in the region of the semiconductor layer 108 that contacts the insulating layer 110d and the region nearby.
  • region 108na functions as one of the source region and drain region of the transistor 100.
  • Region 108nb functions as the other of the source region and drain region of the transistor 100.
  • the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced. This increases the on-state current of the transistor 100 and improves the electrical characteristics. This makes it possible to realize a semiconductor device that operates at high speed.
  • the hydrogen content per unit volume of the insulating layer 110d can be approximately the same as the hydrogen content per unit volume of the insulating layer 101.
  • the insulating layer 110d can be made of a material that can be used for the insulating layer 101.
  • a nitride insulating film and an oxide insulating film can be used for the insulating layer 110d, and it is preferable to use one or both of a silicon nitride film and a silicon nitride oxide film.
  • the insulating layer 110d may contain the same material as the insulating layer 101.
  • the insulating layer 110d may be made of the same material as the insulating layer 101.
  • the insulating layer 110d is preferably a layer that releases hydrogen when heated, like the insulating layer 101.
  • the film thickness of the insulating layer 101 can be made different from the film thickness of the insulating layer 110d by making the film formation time of the insulating layer 101 and the film formation time of the insulating layer 110d different.
  • the thickness of the insulating layer 110d is preferably 5 nm to 200 nm, more preferably 5 nm to 150 nm, more preferably 10 nm to 150 nm, more preferably 20 nm to 150 nm, more preferably 30 nm to 150 nm, and even more preferably 30 nm to 120 nm.
  • the thickness of the insulating layer 110d is increased, the hydrogen content of the insulating layer 110d can be increased, and hydrogen can be suitably supplied to the semiconductor layer 108.
  • the productivity of the semiconductor device of one embodiment of the present invention decreases, and therefore, it is preferable to set the thickness in consideration of the productivity.
  • the insulating layer 110 includes the insulating layer 110d
  • the insulating layer 110b has a region with a higher oxygen content than at least one of the insulating layers 110a, 110c, and 110d. This makes it easier to supply oxygen to the channel formation region of the semiconductor layer 108 and make the channel formation region i-type. As a result, the electrical characteristics of the transistor 100 can be improved and the reliability can be increased. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • the insulating layer 110c can be made of a material that does not easily diffuse hydrogen. This can prevent hydrogen contained in the insulating layer 110d from being supplied to, for example, a region of the semiconductor layer 108 that is away from the region where the insulating layer 110d and the semiconductor layer 108 are in contact with each other. For example, it can prevent hydrogen contained in the insulating layer 110d from being supplied to a region of the semiconductor layer 108 that is in contact with the insulating layer 110c. As a result, the channel length of the transistor 100 is reduced, and the threshold voltage of the transistor 100 is reduced, that is, a negative shift in the threshold voltage is prevented. This can reduce the cutoff current and realize a transistor with normally-off characteristics. Therefore, the reliability of the transistor 100 can be improved, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • the insulating layer 110c can be made of a material in which hydrogen is less likely to diffuse than the conductive layer 112b, and can also be made of a material in which hydrogen is less likely to diffuse than the insulating layer 110b.
  • the insulating layer 110c can be made of a material in which hydrogen is less likely to diffuse than the conductive layer 112b, and can also be made of a material in which hydrogen is less likely to diffuse than the insulating layer 110b.
  • the diffusion coefficient of hydrogen in the insulating layer 110c can be approximately the same as the diffusion coefficient of hydrogen in the insulating layer 110a.
  • the insulating layer 110d has a region in which the hydrogen content is equal to or greater than the hydrogen content of the insulating layer 110c.
  • the insulating layer 110c has a region in which the hydrogen content is equal to or less than the hydrogen content of the insulating layer 110d.
  • the region 108nb- shown in FIG. 8A can be a region having a lower electrical resistance than the region 108i and a higher electrical resistance than the region 108nb.
  • the contact resistance between the semiconductor layer 108 and the conductive layer 112b can be reduced, and the channel length of the transistor 100 can be prevented from being reduced by supplying hydrogen to, for example, a region in contact with the insulating layer 110b. Therefore, the transistor 100 can have a large on-state current and high reliability.
  • the semiconductor device of one embodiment of the present invention can be a semiconductor device that operates at high speed and has high reliability.
  • components of a semiconductor device according to one embodiment of the present invention other than the insulating layer 101 functioning as a base insulating layer and the insulating layer 110 functioning as a spacer will be described.
  • materials that can be used for the components will be described.
  • Conductive Layer 112a, Conductive Layer 112b, and Conductive Layer 104 For the conductive layer 112a, the conductive layer 112b, and the conductive layer 104, it is preferable to use a metal element selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, and an alloy containing the metal element. In addition, a nitride of the above metal or alloy, or an oxide of the above metal or alloy may be used.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.
  • a semiconductor with low electrical resistivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 it is preferable to use, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize, or conductive materials that maintain their conductivity even when oxidized.
  • a conductive oxide such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide, In-Sn-Si oxide, or Ga-Zn oxide can be used.
  • a conductive oxide containing indium is preferable because of its high conductivity.
  • the conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108.
  • the semiconductor layer 108 is a metal oxide layer
  • a metal that is easily oxidized is used for the conductive layer 112a or the conductive layer 112b
  • an insulating oxide may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder electrical conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains its conductivity even when oxidized, or an oxide conductive material for the conductive layer 112a and the conductive layer 112b.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 may be formed by stacking a plurality of layers containing the above-mentioned conductive material.
  • the semiconductor layer 108 is a metal oxide layer
  • oxygen may be supplied from the semiconductor layer 108 to the conductive layer 112a and the conductive layer 112b having a region in contact with the semiconductor layer 108. Therefore, it is preferable to use a conductive material that is difficult to oxidize, a conductive material that maintains conductivity even when oxidized, or an oxide conductive material for the layer having a region in contact with the semiconductor layer 108, for example, the layer having the largest contact area with the semiconductor layer 108.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 may all be made of the same material, or at least one of them may be made of a different material.
  • the semiconductor layer 108 includes a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystalline semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the band gap of the metal oxide used in the semiconductor layer 108 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • metal oxides examples include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium.
  • element M examples include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • metal elements and metalloid elements are sometimes collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 108 may be, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc Indium tin zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may contain one or more metal elements having a high period number in the periodic table instead of or in addition to indium.
  • metal elements having a high period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the carrier concentration increases or the band gap decreases, which may increase the field effect mobility of the transistor.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the nearby composition includes a range of ⁇ 30% of the desired atomic ratio.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the metal oxide can be formed by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the metal oxide after film formation may differ from the composition of the target.
  • the zinc content in the metal oxide after film formation may decrease to about 50% compared to the target.
  • the semiconductor layer 108 may have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 108 may have the same or approximately the same composition.
  • the two or more metal oxide layers in the semiconductor layer 108 may have different compositions.
  • gallium, aluminum, or tin as the element M.
  • a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) can be used.
  • the semiconductor layer 108 preferably has a crystalline metal oxide layer.
  • crystalline metal oxide structures include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the semiconductor layer 108 may have a stacked structure of two or more metal oxide layers with different crystallinity.
  • the semiconductor layer 108 may have a stacked structure of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, and the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer.
  • the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer.
  • the first metal oxide layer and the second metal oxide layer may have different compositions, or may have the same or approximately the same composition.
  • the thickness of the semiconductor layer 108 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less.
  • oxygen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, and oxygen vacancies ( VO ) may be formed in the oxide semiconductor.
  • a defect ( VOH ) in which hydrogen is introduced into the oxygen vacancy may function as a donor and generate an electron that is a carrier.
  • some of the hydrogen may bond with oxygen bonded to a metal atom to generate an electron that is a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to have normally-on characteristics (that is, the threshold voltage has a negative value).
  • hydrogen in an oxide semiconductor is easily mobile due to stress such as heat and an electric field; therefore, if an oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be deteriorated.
  • an oxide semiconductor When an oxide semiconductor is used for the semiconductor layer 108, it is preferable to reduce VOH in the semiconductor layer 108 as much as possible to make the semiconductor layer 108 highly pure intrinsic or substantially highly pure intrinsic.
  • it is important to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to repair oxygen vacancies.
  • impurities such as water and hydrogen from the oxide semiconductor
  • an oxide semiconductor with sufficiently reduced impurities such as VOH for a channel formation region of a transistor, stable electrical characteristics can be imparted.
  • oxygen addition treatment By supplying oxygen to an oxide semiconductor to repair oxygen vacancies may be referred to as oxygen addition treatment.
  • the carrier concentration of the oxide semiconductor in the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the lower limit of the carrier concentration of the oxide semiconductor in the channel formation region is not particularly limited, and can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., are highly resistant to radiation, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • semiconductor materials that can be used for the semiconductor layer 108 include, for example, semiconductors made of single elements or compound semiconductors.
  • semiconductors made of single elements include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • compound semiconductors include organic semiconductors and nitride semiconductors.
  • the aforementioned oxide semiconductor is also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.
  • Silicon that can be used for the semiconductor layer 108 includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon for the semiconductor layer 108 can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer 108 have high field effect mobility and can operate at high speed. Transistors using microcrystalline silicon for the semiconductor layer 108 have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • the semiconductor layer 108 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 molybdenum tellurium
  • the insulating layer 106 may have a single-layer structure or a stacked structure of two or more layers.
  • the insulating layer 106 preferably has one or more inorganic insulating films.
  • the inorganic insulating film include an insulating oxide film and an insulating nitride film. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 106 has a portion in contact with the semiconductor layer 108.
  • an oxide semiconductor is used for the semiconductor layer 108
  • the insulating layer 106 has a single-layer structure, it is preferable to use a silicon oxide film or a silicon oxynitride film for the insulating layer 106.
  • the insulating layer 106 can have a stacked structure of an oxide insulating film on the side in contact with the semiconductor layer 108 and a nitride insulating film on the side in contact with the conductive layer 104.
  • oxide insulating film for example, a silicon oxide film or a silicon oxynitride film is preferably used.
  • nitride insulating film a silicon nitride film or a silicon nitride oxide film is preferably used.
  • Silicon nitride films and silicon nitride oxide films have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, so they can be suitably used as the insulating layer 106.
  • impurities e.g., water and hydrogen
  • the electrical characteristics of the transistor can be improved and the reliability can be increased.
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • the substrate 102 has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, or an SOI (Silicon On Insulator) substrate can be used as the substrate 102.
  • a semiconductor element may be provided on the substrate 102.
  • a polarizing plate may be used as the substrate 102.
  • the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate may be used as the substrate 102, and the transistor 100, for example, may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistor 100, etc. The peeling layer can be used to separate the semiconductor device from the substrate 102 after a part or whole of the semiconductor device is completed thereon, and to transfer the semiconductor device to another substrate.
  • the transistor 100 can be transferred to a substrate with poor heat resistance or a flexible substrate.
  • the substrate 102 may be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, or cellulose nanofiber.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • PC polycarbonate
  • PES polyethersulfone
  • polyamide resin nylon, aramid, etc.
  • FIG. 9A shows an example in which the insulating layer 101 has an insulating layer 101a and an insulating layer 101b on the insulating layer 101a. That is, Fig. 9A shows an example in which the insulating layer 101 has a two-layer laminated structure.
  • Insulating layer 101b corresponds to insulating layer 101 shown in FIG. 6C, for example, and can be an insulating layer containing hydrogen.
  • Insulating layer 101a can be an insulating layer having a region with a lower hydrogen content than insulating layer 101b.
  • Insulating layer 101a can be, for example, an insulating layer that does not contain hydrogen.
  • the insulating layer 101a can be made of a material that can be used for the insulating layer 110.
  • the insulating layer 101a can be made of an inorganic insulating film, for example, an oxide insulating film or a nitride insulating film.
  • the insulating layer 101a can be made of, for example, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film.
  • the insulating layer 101a may have a stacked structure of two or more layers
  • the insulating layer 101b may have a stacked structure of two or more layers.
  • Figure 9B shows an example of patterning the insulating layer 101.
  • the insulating layer 101 is formed on the substrate 102, a conductive film that will become the conductive layer 112a is formed on the insulating layer 101, and then a resist mask is formed by a photolithography process, and the conductive film and the insulating layer 101 are processed to form the conductive layer 112a and the insulating layer 101 shown in Figure 9B.
  • the area of the insulating layer 101 containing hydrogen in a plan view can be made smaller than that of the semiconductor device shown in FIG. 9A.
  • This can prevent the reliability of the semiconductor device of one embodiment of the present invention from decreasing due to hydrogen contained in the insulating layer 101.
  • the semiconductor device shown in FIG. 9A can reduce the step generated in the insulating layer 110 and simplify the manufacturing process of the semiconductor device compared to the semiconductor device shown in FIG. 9B.
  • Figure 9C shows an example in which insulating layer 101 has insulating layer 101a and insulating layer 101b on insulating layer 101a, and insulating layer 101b is patterned.
  • insulating layer 101b if a material having a high etching selectivity with respect to insulating layer 101a is used for insulating layer 101b, it is preferable to prevent a part of insulating layer 101a from being processed when insulating layer 101b is processed, and to prevent insulating layer 101a from becoming thin.
  • Figure 10A shows an example in which the thickness of the insulating layer 101 in the area that does not overlap with the conductive layer 112a is thinner than the thickness of the insulating layer 101 in the area that overlaps with the conductive layer 112a. If the etching selectivity ratio between the insulating layer 101 and the conductive layer 112a is low, a part of the insulating layer 101 may be processed when processing the conductive film that becomes the conductive layer 112a, and the thickness of the insulating layer 101 may become thinner as shown in Figure 10A.
  • Figure 10B shows an example in which the insulating layer 101 has an insulating layer 101a and an insulating layer 101b on the insulating layer 101a, and the thickness of the insulating layer 101b in the area that does not overlap with the conductive layer 112a is thinner than the thickness of the insulating layer 101b in the area that overlaps with the conductive layer 112a. If the etching selectivity between the insulating layer 101b and the conductive layer 112a is low, a part of the insulating layer 101b may be processed when processing the conductive film that becomes the conductive layer 112a, and the thickness of the insulating layer 101b may become thinner as shown in Figure 10B.
  • Figure 10C shows an example in which the thickness of insulating layer 101a in the region that does not overlap insulating layer 101b is thinner than the thickness of insulating layer 101a in the region that overlaps insulating layer 101b in the configuration shown in Figure 9C. If the etching selectivity between insulating layer 101a and insulating layer 101b is low, a portion of insulating layer 101a may be processed when insulating layer 101b is processed, resulting in a thinner thickness of insulating layer 101a as shown in Figure 10C.
  • Transistor 100A 11A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100A, Fig. 11B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 11A, and Fig. 11C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 11A.
  • Transistor 100A differs from transistor 100 mainly in that opening 143 is larger than opening 141 in plan view.
  • the end of conductive layer 112b on the opening 143 side is located outside the end of insulating layer 110 on the opening 141 side.
  • semiconductor layer 108 can have a region inside opening 143 that contacts the top surface of insulating layer 110.
  • Transistor 100B] 12A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100B, Fig. 12B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 12A, and Fig. 12C is a cross-sectional view taken along dashed dotted line B1-B2 in Fig. 12A.
  • Transistor 100B differs from transistor 100 mainly in that semiconductor layer 108 has an area in contact with the side of conductive layer 112b that does not face opening 143 (opposite side to opening 143). As shown in FIG. 12C, semiconductor layer 108 of transistor 100B can be configured to cover the side of conductive layer 112b that does not face opening 143. The end of semiconductor layer 108 is located outside the end of conductive layer 112b and is in contact with the upper surface of insulating layer 110. The left end of semiconductor layer 108 in FIG. 12C covers the end of conductive layer 112b and is in contact with the upper surface of insulating layer 110. The right end of semiconductor layer 108 in FIG. 12C is in contact with the upper surface of conductive layer 112b.
  • Transistor 100C 13A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100C
  • Fig. 13B is a cross-sectional view taken along dashed line A1-A2 in Fig. 13A
  • Fig. 13C is a cross-sectional view taken along dashed line B1-B2 in Fig. 13A.
  • Transistor 100C is a modified example of transistor 100A and differs from transistor 100A mainly in that conductive layer 112b is provided on semiconductor layer 108. Transistor 100C can be configured such that conductive layer 112b covers at least a portion of the top surface and side surface of semiconductor layer 108.
  • Transistor 100D 14A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, and illustrates a configuration example of a transistor 100D.
  • FIG 14B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 14A.
  • the transistor 100D is mainly different from the transistor 100 in that it has a conductive layer 103 on the conductive layer 112a.
  • the conductive layer 103 is provided to have a region in contact with the upper surface of the conductive layer 112a.
  • the conductive layer 103 can function as an auxiliary wiring for the conductive layer 112a.
  • the conductive layer 103 has an opening 148 that reaches the conductive layer 112a.
  • the conductive layer 103 is provided to have a region that faces the conductive layer 104 with the insulating layer 110, the semiconductor layer 108, and the insulating layer 106 sandwiched therebetween.
  • the conductive layer 103 can function as a back gate electrode (also referred to as a second gate electrode) of the transistor 100D.
  • the insulating layer 110 functions as a back gate insulating layer (also referred to as a second gate insulating layer) of the transistor 100D.
  • the conductive layer 104 is referred to as a front gate electrode, a first gate electrode, or simply a gate electrode
  • the insulating layer 106 is referred to as a front gate insulating layer, a first gate insulating layer, or simply a gate insulating layer.
  • the transistor 100D has a back gate electrode, the potential of the back gate side (also called the back channel) of the semiconductor layer 108 can be fixed. Therefore, the saturation of the Id-Vd characteristics of the transistor 100D can be increased.
  • a transistor's Id-Vd characteristics may refer to a transistor having a small change in current in the saturation region (small slope).
  • the transistor 100D has a back gate electrode, the potential of the back channel of the semiconductor layer can be fixed, and a negative shift in the threshold voltage can be suppressed. This allows the cutoff current to be reduced, and a transistor with normally-off characteristics can be realized.
  • the conductive layer 103 and the conductive layer 112a which are in contact with each other, are supplied with the same potential.
  • the conductive layer 103 which functions as a backgate electrode, is preferably supplied with the lower potential of the source potential and the drain potential. Therefore, when the transistor 100D is an n-channel transistor, it is preferable that the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode. When the transistor 100D is a p-channel transistor, it is preferable that the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode.
  • top surface shape of the opening 148 refers to the shape of the top surface end or bottom surface end of the conductive layer 103 on the opening 148 side.
  • Transistor 100D can have a region in which conductive layer 103, insulating layer 110, semiconductor layer 108, insulating layer 106, and conductive layer 104 overlap in this order in one direction without any other layers in between.
  • the one direction can be a direction perpendicular to channel length L100. By widening the region, the electric field of the back channel of semiconductor layer 108 can be more reliably controlled.
  • the conductive layer 103 may have a single layer structure or a stacked structure of two or more layers.
  • the conductive layer 103 can be made of any of the materials that can be used for the conductive layer 112a, the conductive layer 112b, or the conductive layer 104.
  • the conductive layer 103 is preferably made of a material having a higher conductivity than the conductive layer 112a. This allows the conductive layer 103 to function favorably as an auxiliary wiring for the conductive layer 112a.
  • the conductive layer 103 can be made of one or more of copper, aluminum, titanium, tungsten, and molybdenum, or an alloy containing one or more of the above-mentioned metals.
  • Transistor 100E] 15A is a cross-sectional view illustrating a configuration example of a transistor 100E.
  • Transistor 100E differs from transistor 100D mainly in that conductive layer 103 is electrically insulated from conductive layer 112a and that insulating layer 110 has a five-layer structure.
  • the conductive layer 103 is provided on the insulating layer 110a.
  • the conductive layer 112a and the conductive layer 103 are electrically insulated by the insulating layer 110a.
  • An opening 148 is provided in the conductive layer 103 at a position overlapping with the conductive layer 112a.
  • the insulating layer 110 includes an insulating layer 110a on the conductive layer 112a, an insulating layer 110e on the insulating layer 110a and on the conductive layer 103, an insulating layer 110b on the insulating layer 110e, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c.
  • the insulating layer 110e covers the upper and side surfaces of the conductive layer 103.
  • the insulating layer 110e is provided so as to cover a portion of the opening 148.
  • the insulating layer 110e has a region inside the opening 148 that contacts the upper surface of the insulating layer 110a.
  • the insulating layer 110e can contain the same material as the insulating layer 110a, and can also contain the same material as the insulating layer 110c. For example, it is preferable to use a material into which oxygen does not easily diffuse for the insulating layer 110e. It is also preferable to use a material into which hydrogen does not easily diffuse for the insulating layer 110e.
  • Figure 15A shows an example in which the thickness of insulating layer 110a is uniform regardless of location. Note that insulating layer 110a may have different thicknesses in areas that overlap conductive layer 103 and areas that do not. For example, when processing the film that will become conductive layer 103, parts of insulating layer 110a that do not overlap conductive layer 103 may be removed, resulting in a thinner thickness.
  • Transistor 100F] 15B is a cross-sectional view illustrating a configuration example of a transistor 100E.
  • Transistor 100F differs mainly from transistor 100F in that insulating layer 110 has a seven-layer structure.
  • insulating layer 110 includes insulating layer 110a on conductive layer 112a, insulating layer 110b1 on insulating layer 110a, insulating layer 110e1 on insulating layer 110b1, insulating layer 110e2 on insulating layer 110e1 and conductive layer 103, insulating layer 110b2 on insulating layer 110e2, insulating layer 110c on insulating layer 110b2, and insulating layer 110d on insulating layer 110c.
  • the insulating layer 110b1 and the insulating layer 110b2 can each have a configuration similar to that applicable to the insulating layer 110b. Specifically, it is preferable to use an insulating layer containing oxygen for each of the insulating layer 110b1 and the insulating layer 110b2, and it is preferable to have a region with a higher oxygen content than at least one of the insulating layer 110a, the insulating layer 110c, the insulating layer 110d, the insulating layer 110e1, and the insulating layer 110e2.
  • the insulating layer 110e1 and the insulating layer 110e2 can be configured in the same manner as the insulating layer 110e. Specifically, it is preferable to use a material into which oxygen does not easily diffuse for the insulating layer 110e1 and the insulating layer 110e2. It is also preferable to use a material into which hydrogen does not easily diffuse for the insulating layer 110e1 and the insulating layer 110e2.
  • channel length L100 can be the shortest distance between the portion of semiconductor layer 108 that contacts insulating layer 110a and the portion that contacts insulating layer 110c.
  • the configuration of insulating layer 110 can be made symmetrical or roughly symmetrical above and below conductive layer 103.
  • oxygen can be supplied to semiconductor layer 108 from both insulating layer 110b1 and insulating layer 110b2, improving the characteristics of the transistor.
  • Transistor 100G 16A is a plan view illustrating a configuration example of a semiconductor device of one embodiment of the present invention, illustrating a configuration example of a transistor 100G
  • Fig. 16B is a cross-sectional view taken along dashed line A1-A2 in Fig. 16A
  • Fig. 16C is a cross-sectional view taken along dashed line B1-B2 in Fig. 16A .
  • Transistor 100G differs from transistor 100 primarily in that it has conductive layer 105 between insulating layer 110d and conductive layer 112b.
  • the conductive layer 105 is provided on the insulating layer 110, and the conductive layer 112b is provided on the conductive layer 105.
  • the conductive layer 112b has a region in contact with the upper surface of the conductive layer 105.
  • the conductive layer 105 can function as an auxiliary wiring for the conductive layer 112b.
  • the conductive layer 105 has an opening 143.
  • the semiconductor layer 108 preferably has a region in contact with the side surface of the conductive layer 105.
  • the semiconductor layer 108 is preferably provided in contact with the end of the conductive layer 105 on the opening 143 side.
  • the conductive layer 105 and the conductive layer 112b function as the upper electrode of the transistor 100G.
  • the semiconductor layer 108 can be configured to have a region in contact with the upper surface of the conductive layer 112b and not to have a region in contact with the upper surface of the conductive layer 105. Therefore, the contact area of the semiconductor layer 108 with the conductive layer 112b can be made larger than the contact area with the conductive layer 105. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains its conductivity even when oxidized, or an oxide conductive material for the conductive layer 112b.
  • a material with a lower electrical resistivity than the conductive layer 112b for the conductive layer 105.
  • a metal or an alloy is preferably used for the conductive layer 105.
  • the conductive layer 105 can be made of a material that can be used for the conductive layer 103.
  • the upper electrode of transistor 100G can be made into an electrode with low electrical resistivity while suppressing poor electrical conductivity with semiconductor layer 108 due to oxidation.
  • Transistor 100H 17A and 17B are cross-sectional views showing a configuration example of a transistor 100H.
  • FIG. 17A is a cross-sectional view taken along dashed line A1-A2 in FIG. 6A
  • FIG. 17B is a cross-sectional view taken along dashed line B1-B2 in FIG. 6A.
  • Transistor 100H differs from transistor 100 mainly in that insulating layer 106 is processed, for example, into an island shape.
  • FIGS. 17A and 17B show an example in which the upper surface end of insulating layer 106 coincides with or roughly coincides with the lower surface end of conductive layer 104.
  • the upper surface end of insulating layer 106 can coincide with or roughly coincides with the lower surface end of conductive layer 104.
  • the upper surface end of insulating layer 106 does not have to coincide with or roughly coincide with the lower surface end of conductive layer 104.
  • the upper surface end of insulating layer 106 may be located outside the lower surface end of conductive layer 104.
  • planar shape of the openings 141 and 143 is circular, but the planar shape of the openings 141 and 143 is not limited to circular.
  • Figures 18A, 18B, and 18C are plan views showing examples of the shapes of the openings 141 and 143.
  • the planar shape of the openings 141 and 143 may be elliptical as shown in Figure 18A, or rectangular as shown in Figure 18B. Note that Figure 18B shows a rectangle with curved corners.
  • the planar shape of the openings 141 and 143 may also be a shape that includes one or both of straight lines and curved lines as shown in Figure 18C.
  • FIG. 19A to 19D are circuit diagrams illustrating configuration examples of a semiconductor device of one embodiment of the present invention.
  • the semiconductor device illustrated in FIG. 19A and FIG. 19B includes a transistor 100 and a transistor 200.
  • the semiconductor device illustrated in FIG. 19C includes a transistor 100 and a capacitor 190.
  • the semiconductor device illustrated in FIG. 19D includes a transistor 100, a transistor 200, and a capacitor 190. Any of the above-described transistors 100A to 100H may be used as the transistor 100 illustrated in FIG. 19A to FIG. 19D.
  • one of the source or drain of the transistor 100 is electrically connected to one of the source or drain of the transistor 200.
  • one of the source or drain of the transistor 200 is electrically connected to the gate of the transistor 100.
  • one of the source or drain of the transistor 100 is electrically connected to one electrode of the capacitor 190.
  • the gate of the transistor 100 is electrically connected to one of the source or drain of the transistor 200 and one electrode of the capacitor 190.
  • each transistor is shown as an n-channel type, but one embodiment of the present invention is not limited to this.
  • One or both of the transistor 100 and the transistor 200 may be a p-channel type.
  • FIGSemiconductor device 10 20A and 20B are cross-sectional views illustrating a configuration example of a semiconductor device 10 which is a semiconductor device of one embodiment of the present invention.
  • the semiconductor device 10 includes a transistor 100 and a transistor 150.
  • any of a gate electrode, a source electrode, and a drain electrode of the transistor 100 can be electrically connected to any of a gate electrode, a source electrode, and a drain electrode of the transistor 150.
  • FIG. 20A and 20B show an example in which the transistor 100 has the configuration shown in Figures 1B and 1C. Note that in the semiconductor device 10, the insulating layer 101 may have the configuration shown in any one of Figures 9A to 10C.
  • the transistor 150 has a conductive layer 120, an insulating layer 121, a semiconductor layer 108a, an insulating layer 106, a conductive layer 107a, a conductive layer 107b, and a conductive layer 104a.
  • Each layer constituting the transistor 150 may have a single-layer structure or a stacked structure.
  • the conductive layer 120 functions as a backgate electrode of the transistor 150.
  • the backgate electrode of the transistor 150 can be formed using the same material and in the same process as the conductive layer 112b. Note that the transistor 150 does not necessarily have to include the conductive layer 120.
  • An insulating layer 121 is provided to cover the upper surface and side surfaces of the conductive layer 120.
  • the insulating layer 121 functions as a back-gate insulating layer of the transistor 150.
  • the insulating layer 121 is preferably an insulating layer containing oxygen because it has a region in contact with the channel formation region of the semiconductor layer 108a.
  • the insulating layer 121 can be made of a material that can be used for the insulating layer 110b.
  • the semiconductor layer 108a is provided on the insulating layer 121.
  • the semiconductor layer 108a has an area that overlaps with the conductive layer 120 via the insulating layer 121.
  • Figure 20A shows an example in which the end of the semiconductor layer 108a is located on the upper surface of the insulating layer 121
  • Figure 20B shows an example in which the semiconductor layer 108a covers the upper surface and side surfaces of the insulating layer 121.
  • Semiconductor layer 108a can be formed using the same materials and processes as semiconductor layer 108.
  • the semiconductor layer 108 and the semiconductor layer 108a may be made of the same material.
  • the semiconductor layer 108 and the semiconductor layer 108a may be made of materials having different compositions.
  • In-Ga-Zn oxide having the same composition may be used for both the semiconductor layer 108 and the semiconductor layer 108a.
  • In-Ga-Zn oxide may be used for both the semiconductor layer 108 and the semiconductor layer 108a, and the ratio of the number of In atoms in the metal oxide in one layer may be larger than that in the other layer.
  • In-Ga-Zn oxide may be used for one of the semiconductor layers 108 and 108a, and In-Zn oxide may be used for the other layer.
  • the semiconductor layer 108 and the semiconductor layer 108a may be formed in different processes, so that the material contained in the semiconductor layer 108 and the material contained in the semiconductor layer 108a can be made different.
  • An insulating layer 106 is provided to cover the insulating layer 121 and the semiconductor layer 108a.
  • the insulating layer 106 functions as a gate insulating layer for the transistor 150.
  • a conductive layer 104a is provided on the insulating layer 106.
  • the conductive layer 104a has a region that overlaps with the semiconductor layer 108a via the insulating layer 106.
  • the conductive layer 104a functions as a gate electrode of the transistor 150.
  • the conductive layer 104a can be formed using the same material and in the same process as the conductive layer 104.
  • an insulating layer 109 is provided to cover the conductive layer 104a, and conductive layers 107a and 107b are provided on the insulating layer 109.
  • the conductive layers 107a and 107b each have an area in contact with the semiconductor layer 108a inside the openings provided in the insulating layer 106 and the insulating layer 109.
  • the conductive layers 107a and 107b are formed using the same material and in the same process as the conductive layers 104a and 104.
  • the conductive layers 107a and 107b each have a region in contact with the semiconductor layer 108a inside an opening provided in the insulating layer 106.
  • One of the conductive layers 107a and 107b functions as a source electrode of the transistor 150, and the other functions as a drain electrode of the transistor 150.
  • the transistor 150 is a so-called top-gate transistor that has a gate electrode above the semiconductor layer 108a. For example, by adding an impurity element to the semiconductor layer 108a using the conductive layer 104a that functions as the gate electrode as a mask, the source region and the drain region can be formed in a self-aligned manner.
  • the transistor 150 can be called a TGSA (Top Gate Self-Aligned) type transistor.
  • the channel length of the transistor 150 can be controlled by the width of the conductive layer 104a in the channel length direction. Therefore, the channel length of the transistor 150 is equal to or greater than the resolution limit of the exposure device used to manufacture the transistor. By increasing the channel length, a transistor with high saturation characteristics can be obtained.
  • a transistor 100 with a small channel length and a transistor 150 with a large channel length can be formed on the same substrate by sharing some of the steps.
  • a high-performance semiconductor device can be obtained by applying the transistor 100 to a transistor that requires a large on-current and the transistor 150 to a transistor that requires high saturation characteristics.
  • FIG. 21A is a plan view illustrating a configuration example of a semiconductor device 10A that is a semiconductor device of one embodiment of the present invention.
  • FIG. 21B is a cross-sectional view taken along dashed line A1-A2 in FIG. 21A
  • FIG. 22A is a cross-sectional view taken along dashed line B1-B2 in FIG. 21A
  • FIG. 22B is a cross-sectional view taken along dashed line B3-B4 in FIG. 21A.
  • the semiconductor device 10A is a semiconductor device having a circuit configuration illustrated in FIG. 19A.
  • FIGS. 21A, 21B, and 22A illustrate an example in which the transistor 100 has the configuration illustrated in FIGS. 6A to 6C.
  • the insulating layer 101 may have the configuration illustrated in any of FIGS. 9A to 10C.
  • the insulating layer 110 may have the configuration illustrated in FIGS. 1A to 1C.
  • the transistor 200 of the semiconductor device 10A has a conductive layer 112c, a semiconductor layer 108a, a conductive layer 112b, an insulating layer 106, and a conductive layer 104a.
  • the conductive layer 112c functions as one of the source and drain electrodes of the transistor 200.
  • the conductive layer 112c can be formed using the same material and in the same process as the conductive layer 112a.
  • an opening 141a is provided in the insulating layer 110, which reaches the conductive layer 112c, and an opening 143a is provided in the conductive layer 112b, which has an area overlapping with the opening 141a.
  • the semiconductor layer 108a, the insulating layer 106, and the conductive layer 104a are provided so as to have an area located inside the opening 141a and an area located inside the opening 143a.
  • the semiconductor layer 108a can be formed using the same material and in the same process as the semiconductor layer 108. Alternatively, the semiconductor layer 108 and the semiconductor layer 108a may be formed using different materials and in different processes. For the configurations of the semiconductor layer 108 and the semiconductor layer 108a, the description of the semiconductor layer in the semiconductor device 10 can also be referred to.
  • the conductive layer 112b functions as the other of the source electrode or drain electrode of the transistor 100 and also functions as the other of the source electrode or drain electrode of the transistor 200. By sharing the conductive layer 112b between the transistors 100 and 200, the area occupied by the semiconductor device can be reduced.
  • the conductive layer 104a functions as the gate electrode of the transistor 200.
  • the conductive layer 104a can be formed using the same material and in the same process as the conductive layer 104.
  • Opening 141a can have a shape similar to that which opening 141 can have.
  • Opening 143a can have a shape similar to that which opening 143 can have.
  • the shapes and sizes (diameter, etc.) of opening 141 and opening 141a provided in insulating layer 110 may be the same or different.
  • the shapes and sizes (diameter, etc.) of opening 143 and opening 143a provided in conductive layer 112b may be the same or different from each other.
  • Fig. 23A is a plan view illustrating a configuration example of a semiconductor device 10B which is a semiconductor device of one embodiment of the present invention.
  • Fig. 23B is a cross-sectional view along dashed dotted line A1-A2 in Fig. 23A.
  • the semiconductor device 10B is a semiconductor device having a circuit configuration illustrated in Fig. 19A.
  • Figs. 23A and 23B illustrate an example in which the transistor 100 has the configuration illustrated in Figs. 6A to 6C.
  • the insulating layer 101 may have the configuration illustrated in any one of Figs. 9A to 10C.
  • the insulating layer 110 may have the configuration illustrated in Figs. 1A to 1C.
  • the transistor 200 of the semiconductor device 10B has a conductive layer 112a, a semiconductor layer 108a, a conductive layer 112d, an insulating layer 106, and a conductive layer 104a.
  • the conductive layer 112a functions as one of the source electrode or drain electrode of the transistor 100 and one of the source electrode or drain electrode of the transistor 200. By sharing the conductive layer 112a between the transistors 100 and 200, the area occupied by the semiconductor device can be reduced.
  • the conductive layer 112d functions as the other of the source electrode and drain electrode of the transistor 200.
  • the conductive layer 112d can be formed using the same material and in the same process as the conductive layer 112b.
  • the conductive layer 104a functions as the gate electrode of the transistor 200.
  • the conductive layer 104a can be formed using the same material and in the same process as the conductive layer 104.
  • 21A, 21B, 22B, 23A, and 23B show an example in which the transistor 200 has a similar structure to the transistor 100. Note that the transistor 200 may have a similar structure to the transistors 100A to 100H described above. The structure of the transistor 200 described above can also be applied to the transistor 200 shown in FIG. 19B.
  • Fig. 24A to Fig. 27B show a cross-sectional view taken along dashed line A1-A2 and a cross-sectional view taken along dashed line B1-B2 shown in Fig. 6A side by side.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, pulsed laser deposition (PLD: Pulsed Laser Deposition), or ALD.
  • CVD methods include PECVD and thermal CVD.
  • One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD: Metal Organic CVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by wet film formation methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the above-mentioned thin film can be processed, for example, by forming a resist mask by photolithography, and then etching the thin film according to the pattern of the resist mask.
  • the thin film may be processed by nanoimprinting, sandblasting, lift-off, or the like.
  • an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.
  • a photosensitive thin film can be processed by exposure and development. In other words, a photosensitive thin film can be processed by photolithography.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • Dry etching or wet etching can be used to etch thin films.
  • an insulating layer 101 is formed on a substrate 102 (FIG. 24A).
  • the insulating layer 101 is an insulating layer containing hydrogen.
  • the insulating layer 101 is formed so as to have a region in which the hydrogen content is equal to or greater than the hydrogen content of the insulating layer 110a to be formed in a later step.
  • the insulating layer 101 and the insulating layer 110a can be formed, for example, by a CVD method, specifically, a PECVD method. Note that the insulating layer 101 and the insulating layer 110a can also be formed, for example, by a sputtering method.
  • a nitride insulating film can be formed as described above, specifically, a silicon nitride film or a silicon nitride oxide film can be formed.
  • a nitride insulating film as the insulating layer 101 and the insulating layer 110a, it is possible to prevent the conductive layer 112a formed in a later process from being oxidized in a later heating process or the like in the region in contact with the insulating layer 101 and the region nearby, and the region in contact with the insulating layer 110a and the region nearby, thereby preventing the resistance from increasing.
  • the ratio of molecules containing hydrogen in the deposition gas of the insulating layer 101 is preferably equal to or greater than the ratio of molecules containing hydrogen in the deposition gas of the insulating layer 110a.
  • the ratio of the flow rate of NH 3 gas in the deposition gas of the insulating layer 101 is preferably equal to or greater than the flow rate of NH 3 gas in the deposition gas of the insulating layer 110a. Note that the deposition gas of the insulating layer 110a does not need to contain NH 3 gas.
  • the deposition gas of the insulating layer 110a does not need to contain NH 3 gas.
  • the insulating layer 101 can be formed under conditions where the ratio of the flow rate of, for example, NH 3 gas to the total deposition gas is high, thereby increasing the hydrogen content in the insulating layer 101. This can increase the amount of hydrogen released from the insulating layer 101 by heating.
  • the deposition conditions for the insulating layer 101 and the insulating layer 110a different, the amount of hydrogen released by heating in the insulating layer 101 can be adjusted.
  • the deposition conditions for the insulating layer 101 can be made different from those for the insulating layer 110a in any one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode.
  • the substrate temperature during the formation of the insulating layer 101 and the substrate temperature during the formation of the insulating layer 110a are preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and more preferably 300°C or higher and 400°C or lower, and typically 350°C.
  • the substrate temperature during the formation of the insulating layer 101 and the substrate temperature during the formation of the insulating layer 110a within the above-mentioned range, for example, the amount of hydrogen released from the insulating layer 101 and the amount of hydrogen released from the insulating layer 110a can be suitably controlled.
  • the amount of hydrogen supplied from the insulating layer 101 to the semiconductor layer 108 and the amount of hydrogen supplied from the insulating layer 110a to the semiconductor layer 108 become too large, and the threshold voltage of the transistor 100 becomes smaller, that is, the threshold voltage is prevented from shifting negatively.
  • the reliability of the transistor 100 can be improved, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.
  • a conductive layer 112a is formed on the insulating layer 101 (FIG. 24B).
  • a conductive film that will become the conductive layer 112a is formed on the insulating layer 101, and the conductive film is processed to form the conductive layer 112a.
  • the conductive film that will become the conductive layer 112a can be formed, for example, by using a sputtering method.
  • the conductive film can be processed, for example, by using one or both of a wet etching method and a dry etching method to form the conductive layer 112a.
  • a conductive layer having a stacked structure of a layer containing copper and a layer containing indium tin oxide having silicon on the layer can be formed as the conductive layer 112a.
  • insulating layer 110a is formed on conductive layer 112a and insulating layer 101.
  • insulating layer 110a is formed so as to have a region in contact with the top surface of insulating layer 101, a region in contact with the top surface of conductive layer 112a, and a region in contact with the side surface of conductive layer 112a.
  • insulating layer 110b is formed on insulating layer 110a ( Figure 24C).
  • the deposition conditions of the insulating layer 110a are as described above.
  • the insulating layer 110a is formed to have a region in which the hydrogen content is, for example, equal to or less than the hydrogen content of the insulating layer 101.
  • the ratio of molecules containing hydrogen in the deposition gas of the insulating layer 110a is preferably equal to or less than the ratio of molecules containing hydrogen in the deposition gas of the insulating layer 101.
  • the flow rate of NH 3 gas in the deposition gas of the insulating layer 110a is preferably equal to or less than the flow rate of NH 3 gas in the deposition gas of the insulating layer 101.
  • the insulating layer 110a can be formed under conditions that make it more difficult for hydrogen to diffuse than the conductive layer 112a, and can also be formed under conditions that make it more difficult for hydrogen to diffuse than the insulating layer 110b.
  • the insulating layer 110a can be formed under conditions that make it less likely for hydrogen to diffuse than the conductive layer 112a, and can also be formed under conditions that make it less likely for hydrogen to diffuse than the insulating layer 110b.
  • the insulating layer 110b can be formed by, for example, a CVD method, specifically a PECVD method. Note that the insulating layer 110b can also be formed by, for example, a sputtering method. As the insulating layer 110b, for example, an oxide insulating film can be formed as described above, specifically a silicon oxide film or a silicon oxynitride film can be formed.
  • the insulating layer 110a After forming the insulating layer 110a, it is preferable to continuously form the insulating layer 110b in a vacuum without exposing the surface of the insulating layer 110a to the atmosphere.
  • the insulating layer 110a and the insulating layer 110b By continuously forming the insulating layer 110a and the insulating layer 110b, it is possible to prevent impurities from the atmosphere from adhering to the surface of the insulating layer 110a. Examples of such impurities include water and organic matter.
  • the substrate temperature during the formation of the insulating layer 110b is preferably in the range of the substrate temperature during the formation of the insulating layer 110a described above. This can reduce the release of impurities (e.g., water and hydrogen) from the insulating layer 110b, and can suppress the diffusion of the impurities into the channel formation region of the semiconductor layer 108. Therefore, a transistor that exhibits good electrical characteristics and is highly reliable can be manufactured.
  • impurities e.g., water and hydrogen
  • the insulating layer 101, the insulating layer 110a, and the insulating layer 110b are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to the heat applied during the formation of the insulating layer 101, the insulating layer 110a, and the insulating layer 110b.
  • the insulating layer 110b After the insulating layer 110b is formed, it is preferable to perform a treatment for supplying oxygen to the insulating layer 110b. This allows a large amount of oxygen to be supplied to the semiconductor layer 108 by a subsequent heat treatment. As a result, oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be manufactured.
  • a plasma treatment is performed in an atmosphere containing oxygen without exposure to the air (in-situ), so that oxygen can be supplied to the insulating layer 110b.
  • N 2 O plasma treatment is preferable.
  • a metal oxide layer 149 on the insulating layer 110b ( Figure 24D).
  • oxygen can be supplied to the insulating layer 110b.
  • the conductivity of the metal oxide layer 149 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the metal oxide layer 149.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide, or indium tin oxide containing silicon can be used as the metal oxide layer 149.
  • the metal oxide layer 149 it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use a metal oxide material that can be applied to the semiconductor layer 108.
  • the amount of oxygen supplied to the insulating layer 110b can be increased by increasing the ratio of the oxygen flow rate (oxygen flow rate ratio) to the total flow rate of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber.
  • the oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.
  • oxygen can be supplied to the insulating layer 110b during the formation of the metal oxide layer 149, and oxygen can be prevented from being released from the insulating layer 110b.
  • a large amount of oxygen can be trapped in the insulating layer 110b.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by a later heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be manufactured which has favorable electrical characteristics.
  • the metal oxide layer 149 After forming the metal oxide layer 149, it is preferable to perform heat treatment. By performing heat treatment after forming the metal oxide layer 149, oxygen can be suitably supplied from the metal oxide layer 149 to the insulating layer 110b.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 150°C or higher and 450°C or lower, more preferably 150°C or higher and 350°C or lower, and even more preferably 200°C or higher and 300°C or lower.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen.
  • a noble gas nitrogen, or oxygen.
  • dry air CODA: Clean Dry Air
  • It is preferable that the content of hydrogen, water, etc. in the atmosphere is as small as possible.
  • As the atmosphere it is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower.
  • an oven a rapid heating (RTA: Rapid Thermal Annealing) device, etc. can be used. Using an RTA device can shorten the heating process time.
  • RTA Rapid Thermal Annealing
  • oxygen may be further supplied to the insulating layer 110b through the metal oxide layer 149.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen.
  • an apparatus that turns oxygen gas into plasma by high-frequency power can be preferably used. Examples of the apparatus that turns gas into plasma by high-frequency power include a plasma etching apparatus and a plasma ashing apparatus.
  • heat treatment may be performed before the metal oxide layer 149 is formed.
  • the temperature of the heat treatment is preferably 150° C. or higher and lower than the distortion point of the substrate, more preferably 200° C. or higher and 450° C. or lower, more preferably 250° C. or higher and 450° C. or lower, even more preferably 300° C. or higher and 450° C. or lower, and even more preferably 350° C. or higher and 450° C. or lower.
  • the method for removing the metal oxide layer 149 is not particularly limited, but a wet etching method can be preferably used.
  • a wet etching method By using a wet etching method, etching of the insulating layer 110b can be suppressed when removing the metal oxide layer 149. This can suppress the thickness of the insulating layer 110b from becoming thin, and the thickness of the insulating layer 110b can be made uniform.
  • the process of supplying oxygen to the insulating layer 110b is not limited to the above-mentioned method.
  • oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, or the like can be supplied to the insulating layer 110b by ion doping, ion implantation, or plasma treatment.
  • oxygen may be supplied to the insulating layer 110b through the film. It is preferable to remove the film after supplying oxygen.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.
  • the formation and removal of the metal oxide layer 149 is not necessarily required.
  • the formation and removal of the metal oxide layer 149 is not necessarily required.
  • Insulating layer 110c is formed on insulating layer 110b.
  • insulating layer 110d is formed on insulating layer 110c (FIG. 25A). This forms insulating layer 110 including insulating layers 110a, 110b, 110c, and 110d. Insulating layers 110c and 110d can be formed by, for example, a CVD method, specifically a PECVD method. Note that insulating layers 110c and 110d can also be formed by, for example, a sputtering method.
  • the insulating layer 110c can be formed under conditions that make it more difficult for hydrogen to diffuse than the conductive layer 112b formed in a later process, and can also be formed under conditions that make it more difficult for hydrogen to diffuse than the insulating layer 110b.
  • the insulating layer 110c can be formed under conditions that make it less difficult for hydrogen to diffuse than the conductive layer 112b, for example, and can also be formed under conditions that make it less difficult for hydrogen to diffuse than the insulating layer 110b.
  • insulating layer 110d is an insulating layer containing hydrogen. Insulating layer 110d is formed to have a region in which the hydrogen content is equal to or greater than the hydrogen content of insulating layer 110c, for example.
  • the insulating layer 110c can be formed to contain the same material as the insulating layer 110a.
  • the insulating layer 110c can be formed using the same material as the insulating layer 110a.
  • the insulating layer 110c can be formed under the same conditions as the insulating layer 110a. Note that, for example, by making the deposition time of the insulating layer 110c different from the deposition time of the insulating layer 110a, the thickness of the insulating layer 110c can be made different from the thickness of the insulating layer 110a.
  • the insulating layer 110d may contain the same material as the insulating layer 101.
  • the insulating layer 110d may be made of the same material as the insulating layer 101.
  • the insulating layer 110d may be formed under the same conditions as the insulating layer 110c.
  • the film formation time of the insulating layer 110d may be made different from the film formation time of the insulating layer 101, thereby making the film thickness of the insulating layer 110d different from the film thickness of the insulating layer 101.
  • a nitride insulating film can be formed as described above, specifically, a silicon nitride film or a silicon nitride oxide film can be formed.
  • a nitride insulating film as the insulating layer 110c and the insulating layer 110d, it is possible to prevent the conductive layer 112b formed in a later process from being oxidized in a later heating process or the like in the region in contact with the insulating layer 110c and the region nearby, and the region in contact with the insulating layer 110d and the region nearby, thereby preventing the resistance from increasing.
  • the ratio of hydrogen-containing molecules in the deposition gas of the insulating layer 110d is preferably equal to or greater than the ratio of hydrogen-containing molecules in the deposition gas of the insulating layer 110c.
  • the ratio of the flow rate of NH 3 gas in the deposition gas of the insulating layer 110d is preferably equal to or greater than the flow rate of NH 3 gas in the deposition gas of the insulating layer 110c. Note that the deposition gas of the insulating layer 110c does not need to contain NH 3 gas.
  • the deposition gas of the insulating layer 110c does not need to contain NH 3 gas.
  • the insulating layer 110d can be formed under conditions where the ratio of the flow rate of, for example, NH 3 gas to the total deposition gas is high, thereby increasing the hydrogen content in the insulating layer 110d, thereby increasing the amount of hydrogen released by heating the insulating layer 110d.
  • the deposition conditions for the insulating layer 110c and the insulating layer 110d can be made different from those for the insulating layer 110c by making one or more of the deposition power (deposition power density), deposition pressure, deposition gas type, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode.
  • the substrate temperature during the formation of insulating layer 110c and the substrate temperature during the formation of insulating layer 110d can be set within the range of the substrate temperature during the formation of insulating layer 110a and the range of the substrate temperature during the formation of insulating layer 101, respectively. This can improve the reliability of the transistor 100 and the reliability of the semiconductor device of one embodiment of the present invention.
  • a conductive film 112f that will become the conductive layer 112b is formed on the insulating layer 110d (FIG. 25B).
  • the conductive film 112f is formed so as to have a region that contacts the upper surface of the insulating layer 110d.
  • a sputtering method is suitable for forming the conductive film 112f.
  • the conductive film 112f is processed into a desired shape to form the conductive layer 112b on the insulating layer 110d (FIG. 25C).
  • the conductive layer 112b is formed so as to have a region that contacts the upper surface of the insulating layer 110d.
  • the conductive layer 112b is processed to form an opening 143 (FIG. 26A).
  • the opening 143 is formed to have an area that overlaps with the conductive layer 112a. Note that after the opening 143 is formed in the conductive film 112f, the conductive film 112f may be processed into a desired shape to form the conductive layer 112b in which the opening 143 is provided.
  • Opening 141 has an area that overlaps with opening 143, and is formed to reach conductive layer 112a. By forming opening 141, the area of conductive layer 112a that overlaps with opening 141 and opening 143 is exposed.
  • the conductive film 112f can be processed by wet etching or dry etching, or both.
  • the wet etching method is suitable for forming the opening 143.
  • the opening 141 can be formed by using either or both of a wet etching method and a dry etching method, and for example, a dry etching method is preferred.
  • the opening 141 can be formed, for example, by using the resist mask used to form the opening 143.
  • a resist mask is formed on the conductive layer 112b, and the conductive layer 112b is partially removed using the resist mask to form the opening 143.
  • the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a are partially removed using the resist mask to form the opening 141.
  • the opening 141 and the opening 143 may each be formed using a different resist mask.
  • a semiconductor film 108f that will become the semiconductor layer 108 is formed so as to cover the openings 141 and 143 (FIG. 26B).
  • the semiconductor film 108f is formed so as to have a region in contact with the upper surface of the conductive layer 112a, a region in contact with the side surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 112b, a region in contact with the upper surface of the conductive layer 112b, and a region in contact with the upper surface of the insulating layer 110.
  • the semiconductor film 108f is preferably formed as a film with as uniform a thickness as possible on the side surface of the insulating layer 110 on the opening 141 side and on the side surface of the conductive layer 112b on the opening 143 side.
  • the semiconductor film 108f can be formed, for example, by a sputtering method or an ALD method.
  • the semiconductor film 108f is preferably formed by a sputtering method using a metal oxide target.
  • the semiconductor film 108f is preferably a dense film with as few defects as possible.
  • the semiconductor film 108f is preferably a high-purity film in which impurities including hydrogen elements are reduced as much as possible.
  • oxygen gas When forming the semiconductor film 108f, it is preferable to use oxygen gas.
  • oxygen gas when forming the semiconductor film 108f, oxygen can be suitably supplied to the insulating layer 110.
  • oxygen when an oxide is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced.
  • oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.).
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • oxygen flow ratio oxygen flow ratio
  • the lower the oxygen flow ratio the lower the crystallinity of the semiconductor film 108f can be, and a transistor with a large on-current can be obtained.
  • the substrate temperature during the formation of the semiconductor film 108f is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, it is preferable to set the substrate temperature to from room temperature to 140°C, as this increases productivity. In addition, by forming the semiconductor film 108f at room temperature or without heating the substrate, the crystallinity can be reduced.
  • the ALD method it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • the thermal ALD method is preferable because it shows extremely high step coverage.
  • the PEALD method is preferable because it shows high step coverage and allows low-temperature film formation.
  • the semiconductor film 108f can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • precursors containing indium include trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.
  • precursors containing gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.
  • precursors containing tin include tetramethyltin, tetraethyltin, tetraethenyltin, tetraallyltin, tributylvinyltin, allyltributyltin, tributylstannylacetylene, tributylphenyltin, chlorotrimethyltin, chlorotriethyltin, and tin(IV) chloride.
  • Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • Methods for controlling the composition of the resulting film include adjusting the flow ratio of the source gases, the time for which the source gases are flowed, or the order in which the source gases are flowed. By adjusting these, it is also possible to deposit a film whose composition changes continuously. It is also possible to deposit films with different compositions continuously.
  • a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110.
  • heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere.
  • plasma treatment in an atmosphere containing oxygen may be performed.
  • oxygen may be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide ( N 2 O).
  • nitrous oxide N 2 O
  • plasma treatment containing nitrous oxide gas oxygen can be supplied while organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to continuously form the semiconductor film 108f without exposing the surface of the insulating layer 110 to the air.
  • the semiconductor layer 108 has a laminated structure, it is preferable to deposit a metal oxide film first, and then deposit the next metal oxide film in succession without exposing the surface to the air.
  • all layers constituting the semiconductor layer 108 may be formed by the same film formation method (e.g., sputtering or ALD), or different film formation methods may be used for each layer.
  • the first metal oxide film may be formed by sputtering
  • the second metal oxide film may be formed by ALD.
  • the semiconductor film 108f is processed into an island shape to form the semiconductor layer 108 (FIG. 27A).
  • the semiconductor layer 108 can be formed to have a region located inside the opening 141 and a region located inside the opening 143.
  • the semiconductor layer 108 can be formed to have a region in contact with the top surface of the conductive layer 112a, a region in contact with the side of the insulating layer 110, a region in contact with the top surface of the conductive layer 112b, and a region in contact with the side of the conductive layer 112b.
  • the semiconductor layer 108 can be formed by using either or both of a wet etching method and a dry etching method.
  • a wet etching method is preferable.
  • a part of the conductive layer 112b in the region that does not overlap with the semiconductor layer 108 may be etched and become thin.
  • a part of the insulating layer 110 in the region that does not overlap with both the semiconductor layer 108 and the conductive layer 112b may be etched and become thin.
  • the insulating layer 110d of the insulating layer 110 may disappear by etching, and the surface of the insulating layer 110c may be exposed.
  • the thickness of the insulating layer 110d can be prevented from becoming thin.
  • heat treatment is preferably performed.
  • the heat treatment can remove hydrogen or water contained in the semiconductor film 108f or the semiconductor layer 108 or adsorbed on the surface.
  • the heat treatment may improve the film quality of the semiconductor film 108f or the semiconductor layer 108 (for example, reduce defects or improve crystallinity). It is more preferable to perform the heat treatment before processing into the semiconductor layer 108.
  • the channel formation region can be made an i-type (intrinsic) or substantially i-type region. This allows the transistor to have stable electrical characteristics.
  • hydrogen contained in the insulating layer 101 can be permeated through the conductive layer 112a and supplied to the region of the semiconductor film 108f or the semiconductor layer 108 that is in contact with the conductive layer 112a and the region nearby. This can reduce the contact resistance between the semiconductor layer 108 and the conductive layer 112a.
  • hydrogen contained in the insulating layer 110d can be permeated through the conductive layer 112b and supplied to the region of the semiconductor film 108f or the semiconductor layer 108 that is in contact with the conductive layer 112b and the region nearby. This can reduce the contact resistance between the semiconductor layer 108 and the conductive layer 112b.
  • a transistor with a large on-current and good electrical characteristics can be manufactured. Therefore, a semiconductor device that operates at high speed can be manufactured.
  • the temperature of the heat treatment is preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and more preferably 300°C or higher and 400°C or lower, typically 350°C.
  • For other conditions of the heat treatment refer to the description of the heat treatment after the formation of the metal oxide layer 149.
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it may be performed in combination with a heat treatment performed in a later process. Also, a high-temperature process in a later process (e.g., a film formation process) may also serve as the heat treatment.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 27B).
  • the insulating layer 106 can be formed on the semiconductor layer 108 so as to have a region located inside the opening 141 and a region located inside the opening 143.
  • the insulating layer 106 can be formed along the sidewalls of the opening 141 and the sidewalls of the opening 143 via the semiconductor layer 108.
  • the PECVD method or the ALD method is suitable for forming the insulating layer 106.
  • the insulating layer 106 preferably functions as a barrier film that suppresses the diffusion of oxygen. Since the insulating layer 106 has the function of suppressing the diffusion of oxygen, the diffusion of oxygen from above the insulating layer 106 to the conductive layer 104 can be suppressed, and the conductive layer 104 can be suppressed from being oxidized. As a result, a transistor that exhibits good electrical characteristics and is highly reliable can be manufactured.
  • a barrier film refers to a film having barrier properties.
  • an insulating layer having barrier properties can be called a barrier insulating layer.
  • barrier properties refer to one or both of the function of suppressing the diffusion of the corresponding substance (also called low permeability) and the function of capturing or fixing the corresponding substance (also called gettering).
  • the substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., further preferably 250° C. to 450° C., further preferably 300° C. to 450° C., and further preferably 300° C. to 400° C.
  • the substrate temperature during the formation of the insulating layer 106 By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor that exhibits good electrical characteristics and is highly reliable can be manufactured.
  • plasma treatment may be performed on the surface of the semiconductor layer 108.
  • the plasma treatment can reduce impurities such as water adsorbed to the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example. In addition, it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • a film containing a large amount of oxygen for the insulating layer 106, because oxygen can be supplied from the insulating layer 106 to the semiconductor layer 108. It is more preferable to use a film that releases oxygen when heated for the insulating layer 106. When the insulating layer 106 releases oxygen due to heat applied during the transistor manufacturing process, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 106 to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced, and a transistor that exhibits good electrical characteristics and is highly reliable can be manufactured.
  • the conductive layer 104 is formed on the insulating layer 106 (FIG. 27B). This forms the transistor 100.
  • the conductive layer 104 can be formed to have a region located inside the opening 141 and a region facing the semiconductor layer 108 with the insulating layer 106 sandwiched between them inside the opening 143.
  • the conductive film that becomes the conductive layer 104 is preferably formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method. After forming a resist mask on the conductive film by a photolithography process, the conductive film can be processed to form an island-shaped conductive layer 104 that functions as a gate electrode.
  • the insulating layer 109 is formed to cover the conductive layer 104 and the insulating layer 106 (FIGS. 6B and 6C).
  • the insulating layer 109 can be formed, for example, by a CVD method, specifically, a PECVD method. Note that the insulating layer 109 can also be formed, for example, by a sputtering method.
  • a semiconductor device according to one embodiment of the present invention can be manufactured.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, and a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device of one embodiment of the present invention can be used for a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (Chip On Glass) method, a COF (Chip On Film) method, or the like.
  • FPC flexible printed circuit
  • TCP Tape Carrier Package
  • the display device of this embodiment may also have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include a surface capacitance type and a projected capacitance type.
  • Examples of the projected capacitance type include a self-capacitance type and a mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.
  • FIG. 28 shows a perspective view of a display device 50A.
  • Display device 50A has a configuration in which substrate 152 and substrate 102 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 50A has a display portion 162, a connection portion 140, a circuit portion 164, a conductive layer 165, and the like.
  • FIG. 28 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 28 can also be said to be a display module having the display device 50A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140.
  • FIG. 28 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164.
  • the signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.
  • an example is shown in which an IC 173 is provided on the substrate 102 by a COG method or a COF method.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 50A and the display module may be configured without an IC.
  • the IC may be mounted on the FPC by, for example, a COF method.
  • the semiconductor device of one embodiment of the present invention can be used, for example, as one or both of the display portion 162 and the circuit portion 164 of the display device 50A.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using the semiconductor device in the display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using the semiconductor device in the display device.
  • the display unit 162 is an area that displays an image in the display device 50A, and has a number of periodically arranged pixels 201.
  • Figure 28 shows an enlarged view of one pixel 201.
  • the pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied.
  • Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.
  • the pixel 201 shown in FIG. 28 has a subpixel 11R that emits red light, a subpixel 11G that emits green light, and a subpixel 11B that emits blue light. There is no particular limit to the number of subpixels that one pixel has.
  • Each of the sub-pixels 11R, 11G, and 11B has a display element and a circuit that controls the driving of the display element.
  • the display element including, for example, a liquid crystal element and a light-emitting element.
  • a shutter type or optical interference type MEMS (Micro Electro Mechanical Systems) element a display element using a microcapsule type, an electrophoresis type, an electrowetting type, or an electronic liquid powder (registered trademark) type, etc. can also be used.
  • a QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials may be used.
  • Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.
  • Modes that can be used in display devices using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode.
  • VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.
  • Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PNLC Polymer Network liquid crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc.
  • either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • the light-emitting element may be, for example, a self-emitting light-emitting element such as an LED (Light Emitting Diode), an OLED (Organic LED), or a semiconductor laser.
  • the LED may be, for example, a mini LED or a micro LED.
  • Examples of light-emitting materials that light-emitting elements have include fluorescent materials, phosphorescent materials, materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).
  • the light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white, etc.
  • the color purity can be increased by providing the light-emitting element with a microcavity structure.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the display device of one embodiment of the present invention may be a top emission type that emits light in a direction opposite to the substrate on which the light emitting elements are formed, a bottom emission type that emits light toward the substrate on which the light emitting elements are formed, or a dual emission type that emits light to both sides.
  • Figure 29A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.
  • the display device 50A shown in FIG. 29A includes transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between the substrate 102 and the substrate 152.
  • the circuit portion 164 includes transistor 205D
  • the display portion 162 includes transistors 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B.
  • Light-emitting element 130R is a display element of sub-pixel 11R that emits red light.
  • Light-emitting element 130G is a display element of sub-pixel 11G that emits green light.
  • Light-emitting element 130B is a display element of sub-pixel 11B that emits blue light.
  • the display device 50A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 50A is also a top emission type.
  • a top emission type for example, a transistor can be arranged so as to overlap the light emitting region of the light emitting element, so that the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • An insulating layer 101 containing, for example, hydrogen is provided on a substrate 102, and transistors 205D, 205R, 205G, and 205B are provided on the insulating layer 101. These transistors can be manufactured using the same material and in the same process.
  • the display device 50A includes the transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the transistors of one embodiment of the present invention in the display portion 162 the pixel size can be reduced and high definition can be achieved.
  • the transistors of one embodiment of the present invention in the circuit portion 164 the area occupied by the circuit portion 164 can be reduced and a narrower frame can be achieved.
  • any of the transistors 100, 100A to 100H, and 150 described in the previous embodiment can be used as the transistors 205D, 205R, 205G, and 205B.
  • the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B each have a conductive layer 112a that functions as one of the source electrode and the drain electrode, a conductive layer 112b that functions as the other of the source electrode and the drain electrode, a semiconductor layer 108 having a channel formation region, an insulating layer 106 that functions as a gate insulating layer, and a conductive layer 104 that functions as a gate electrode.
  • an insulating layer 110 is provided on the insulating layer 101 and on the conductive layer 112a, and an opening that reaches the conductive layer 112a is provided in the insulating layer 110.
  • the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are provided in this order so as to have a region located inside the opening.
  • FIG. 29A shows an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110d on the insulating layer 110c. That is, FIG. 29A shows an example in which the insulating layer 110 has a four-layer stacked structure of the insulating layers 110a to 110d. The subsequent drawings in this embodiment also show an example in which the insulating layer 110 has a four-layer stacked structure of the insulating layers 110a to 110d.
  • FIG. 29A the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. This also applies to the subsequent figures in this embodiment.
  • the transistors included in the display device of this embodiment are not limited to the transistors of one embodiment of the present invention.
  • the display device may include a combination of a transistor of one embodiment of the present invention and a transistor having another structure.
  • the display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors included in the display device of this embodiment may be either a top-gate type or a bottom-gate type.
  • a gate may be provided above and below a semiconductor layer in which a channel is formed.
  • the display device of this embodiment may also have a transistor that uses silicon in the channel formation region (hereinafter, referred to as a Si transistor).
  • the OS transistor when the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This allows a larger number of gray levels to be achieved in the pixel circuit.
  • an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to the light-emitting element, for example, even when the current-voltage characteristics of the light-emitting element vary. In other words, when the OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, so that the light emission luminance of the light-emitting element can be stabilized.
  • the transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures.
  • the transistors in the circuit unit 164 may all have the same structure or may have two or more types.
  • the transistors in the display unit 162 may all have the same structure or may have two or more types.
  • All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.
  • LTPS transistor For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized.
  • a configuration in which an LTPS transistor and an OS transistor are combined is sometimes called LTPO.
  • a more suitable example is a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling conduction and non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.
  • one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can be called a driving transistor.
  • One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.
  • the other transistor in the display unit 162 functions as a switch for controlling pixel selection/non-selection and can be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This allows the gradation of the pixel to be maintained even if the frame frequency is significantly reduced (for example, 1 fps or less), so that power consumption can be reduced by stopping the driver when displaying a still image.
  • An insulating layer 109 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on insulating layer 109.
  • the insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film.
  • Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film.
  • the outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This can prevent a recess from being formed in the insulating layer 235 when processing the pixel electrodes 111R, 111G, and 111B. Alternatively, a recess may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, and 111B.
  • Light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 130R shown in FIG. 29A emits red light (R).
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light-emitting element 130G shown in FIG. 29A emits green light (G).
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light-emitting element 130B shown in FIG. 29A emits blue light (B).
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • EL layer 113R, EL layer 113G, and EL layer 113B are all shown with the same film thickness, but this is not limited to this.
  • EL layer 113R, EL layer 113G, and EL layer 113B may each have a different film thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layers 106, 109, and 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the ends of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall.
  • the insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 109 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode.
  • the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the insulating layer 237 is provided at least in the display section 162.
  • the insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164.
  • the insulating layer 237 may also be provided up to the edge of the display device 50A.
  • the common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B.
  • the common electrode 115 shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140.
  • the conductive layer 123 it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light is used for the pixel electrode and the common electrode, which is the electrode from which light is extracted. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • a metal, an alloy, an electrically conductive compound, a mixture thereof, and the like can be appropriately used as a material for forming a pair of electrodes of a light-emitting element.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations.
  • examples of the material include indium tin oxide (In-Sn oxide, also referred to as ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also referred to as APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, it is preferable that one of the pair of electrodes of the light-emitting element has an electrode that is transparent and reflective to visible light (semi-transmissive/semi-reflective electrode), and the other has an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layer 113R, the EL layer 113G, and the EL layer 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 29A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • the EL layer 113R, the EL layer 113G, and the EL layer 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting material.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably has, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • the light-emitting element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers constituting the light-emitting element can be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units) may be applied to the light-emitting element.
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high luminance. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same luminance, thereby improving reliability.
  • the tandem structure may also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting element.
  • the space between the substrate 152 and the substrate 102 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (nitrogen, argon, etc.) and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting element.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162.
  • the protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164.
  • the protective layer 131 is also preferably provided up to the end of the display device 50A.
  • the connection unit 204 there are portions where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light-emitting elements can be improved.
  • the protective layer 131 may have a single-layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 115 and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.
  • an inorganic insulating film such as an oxide insulating film and a nitride insulating film can be used for the protective layer 131.
  • an inorganic insulating film such as an oxide insulating film and a nitride insulating film can be used for the protective layer 131.
  • the protective layer 131 preferably has a nitride insulating film, and more preferably has a nitride insulating film.
  • the protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, and more specifically, preferably has a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using such a laminated structure, it is possible to prevent impurities (such as water and oxygen) from entering the EL layer.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.
  • connection portion 204 is provided in an area of the substrate 102 where the substrate 152 does not overlap.
  • the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 165 can be a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 can be a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the conductive layer 166 is exposed. This allows the connection portion 204 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 50A is a top emission type. Light emitted by the light emitting elements is emitted toward the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of the substrate 152 facing the substrate 102 or on the protective layer 131.
  • a color filter By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • the colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • a metal material a resin material, a pigment, and a dye
  • the colored layers are formed at the desired positions by a printing method, an inkjet method, or an etching method using photolithography.
  • the substrate 152 can be made of a material that can be used for the substrate 102.
  • Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 102). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light collecting film.
  • the outside of the substrate 152 may be provided with a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, or an impact absorbing layer.
  • a glass layer or a silica layer is provided as the surface protection layer, which can suppress the occurrence of surface contamination and scratches, and is therefore preferable.
  • the surface protection layer may be made of DLC (diamond-like carbon), aluminum oxide (AlO x ), a polyester-based material, a polycarbonate-based material, or the like. It is preferable to use a material with high transmittance for visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • curing adhesives can be used, such as a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, or an anaerobic adhesive.
  • a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, or an anaerobic adhesive.
  • These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin, are preferred.
  • a two-part mixed resin may also be used.
  • an adhesive sheet may also be used.
  • connection layer 242 may be an anisotropic conductive film (ACF) or an anisotropic conductive paste (ACP), etc.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • Display device 50B] 29B shows an example of a cross section of the display unit 162 of the display device 50B.
  • the display device 50B is mainly different from the display device 50A in that a light-emitting element having a common EL layer 113 and a colored layer are used in each subpixel of each color.
  • the configuration shown in FIG. 29B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 102 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 29A. Note that in the following description of the display device, the description of the same parts as those of the display device described above may be omitted.
  • the display device 50B shown in FIG. 29B has light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.
  • the light-emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.
  • Light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each share an EL layer 113 and a common electrode 115.
  • a configuration in which a common EL layer 113 is provided for subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 29B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • a light-emitting element that emits white light preferably includes two or more light-emitting layers.
  • light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting element as a whole emits white light.
  • the emission colors of the three or more light-emitting layers can be combined to obtain a configuration in which the light-emitting element as a whole emits white light.
  • the EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and red light, and a light-emitting unit that emits blue light, etc.
  • the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B.
  • the number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B shown in FIG. 29B emit blue light.
  • the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • a part of the light emitted by the light-emitting element may be transmitted as it is without being converted by the color conversion layer.
  • the color conversion layer By extracting the light that has passed through the color conversion layer via the colored layer, light other than the desired color is absorbed by the colored layer, and the color purity of the light emitted by the subpixel can be increased.
  • Display device 50C A display device 50C shown in FIG. 30 differs from the display device 50B mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 102. It is preferable to use a material that is highly transparent to visible light for the substrate 102. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.
  • FIG. 30 shows an example in which the light-shielding layer 117 is provided on the substrate 102, the insulating layer 153 is provided on the light-shielding layer 117, and the insulating layer 101 is provided on the insulating layer 153.
  • the colored layer 132R, the colored layer 132G, and the colored layer 132B are provided on the insulating layer 109, and the insulating layer 235 is provided on the colored layer 132R, the colored layer 132G, and the colored layer 132B.
  • the light-emitting element 130R which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.
  • Pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for common electrode 115.
  • common electrode 115 can be made of, for example, a metal with low electrical resistance, so that voltage drops caused by the resistance of common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the pixel size can be reduced.
  • a display device 50D shown in FIG. 31A differs from the display device 50A mainly in that a light receiving element 130S is included.
  • Display device 50D has a light-emitting element and a light-receiving element in each pixel.
  • display device 50D it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element.
  • the organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device that uses an organic EL element.
  • display unit 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all of the sub-pixels of display device 50D, some of the sub-pixels can provide light as a light source, some other sub-pixels can perform light detection, and the remaining sub-pixels can display the image.
  • the display device 50D can capture an image using the light receiving element.
  • the image sensor can be used to capture images for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.
  • the light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor).
  • a touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object are in direct contact with each other.
  • a non-contact sensor can detect an object even if the object does not come into contact with the display device.
  • the light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S.
  • Light Lin is incident on the functional layer 113S from outside the display device 50D.
  • the pixel electrode 111S is electrically connected to the conductive layer 112b of the transistor 205S through openings provided in the insulating layer 106, the insulating layer 109, and the insulating layer 235.
  • the transistor 205S can have a structure similar to that of the transistor 205D, the transistor 205R, the transistor 205G, and the transistor 205B.
  • any of the transistor 100, the transistors 100A to 100H, and the transistor 150 described in the previous embodiment can be applied to the transistor 205S.
  • the ends of the pixel electrode 111S are covered by an insulating layer 237.
  • the common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B.
  • the common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140.
  • the functional layer 113S has at least an active layer (also called a photoelectric conversion layer).
  • the active layer includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds.
  • an organic semiconductor is used as the semiconductor in the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be shared, which is preferable.
  • the functional layer 113S may further include a layer containing a material with high hole transport properties, a material with high electron transport properties, or a bipolar material, as a layer other than the active layer.
  • the functional layer 113S may further include a layer containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material.
  • the materials that can be used in the light-emitting element described above can be used for the functional layer 113S.
  • the light receiving element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers constituting the light receiving element can be formed by a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • the display device 50D shown in Figures 31B and 31C has a layer 353 having a light receiving element, a circuit layer 355, and a layer 357 having a light emitting element between the substrate 102 and the substrate 152.
  • Layer 353 has, for example, light receiving element 130S.
  • Layer 357 has, for example, light emitting element 130R, light emitting element 130G, and light emitting element 130B.
  • the circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element.
  • the circuit layer 355 has, for example, a transistor 205R, a transistor 205G, and a transistor 205B.
  • the circuit layer 355 can be provided with one or more of a switch, a capacitance, a resistance, a wiring, a terminal, and the like.
  • Figure 31B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in Figure 31B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50D.
  • Figure 31C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in Figure 31C, light emitted by a light emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in layer 353 detects the reflected light.
  • Display device 50E] 32A is an example of a display device to which an MML (metal maskless) structure is applied, that is, the display device 50E has light-emitting elements fabricated without using a fine metal mask.
  • MML metal maskless
  • the island-shaped light-emitting layer in the light-emitting element of a display device to which the MML structure is applied is formed by depositing a light-emitting layer on one surface and then processing it using a photolithography method. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.
  • Devices with an MML structure can be fabricated without using a metal mask, and therefore exceed the upper limit of resolution due to the alignment accuracy of the metal mask. Furthermore, when fabricating devices without using a metal mask, the equipment required for fabricating the metal mask and the process of cleaning the metal mask are unnecessary. Furthermore, since the same or similar equipment as that used to fabricate transistors can be used for photolithography processing, there is no need to introduce special equipment to fabricate devices with an MML structure. In this way, the MML structure makes it possible to keep fabrication costs low, making it suitable for mass production of devices.
  • a display device to which the MML structure is applied for example, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, so a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized with a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.
  • the layered structure from the substrate 102 to the insulating layer 235, and the layered structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore will not be described.
  • light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130R shown in FIG. 32A emits red light (R).
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.
  • the light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130G shown in FIG. 32A emits green light (G).
  • the layer 133G has a light-emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.
  • the light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130B shown in FIG. 32A emits blue light (B).
  • the layer 133B has a light-emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114.
  • the layer 133R, layer 133G, and layer 133B may be referred to as an island-shaped EL layer, an EL layer formed in an island shape, etc., without including the common layer 114.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the EL layer in an island shape for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission caused by crosstalk, and realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same film thickness, but this is not limited to the above. Layers 133R, 133G, and 133B may each have a different film thickness.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 109, and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • the layer 128 has a function of planarizing the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B.
  • the conductive layer 126R, the conductive layer 126G, and the conductive layer 126B, which are electrically connected to the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B, are provided on the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B and the layer 128.
  • the region overlapping with the recesses of the conductive layer 124R, the conductive layer 124G, and the conductive layer 124B can also be used as a light-emitting region, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for the conductive layer 124R and the conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be used for layer 128.
  • FIG. 32A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • Conductive layer 124G and conductive layer 124B are similar to conductive layer 124R, and conductive layer 126G and conductive layer 126B are similar to conductive layer 126R, so detailed description will be omitted.
  • conductive layer 126R The upper surface and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper surface and side surfaces of conductive layer 126G are covered by layer 133G, and the upper surface and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layer 126R, conductive layer 126G, and conductive layer 126B are provided can be used as the light-emitting area of light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B, thereby increasing the aperture ratio of the pixel.
  • a common layer 114 is provided on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 29A is not provided between the conductive layer 126R and the layer 133R.
  • the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. Therefore, the distance between adjacent light-emitting elements can be made extremely narrow. Therefore, a high-definition or high-resolution display device can be obtained.
  • a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.
  • Insulating layer 125 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.
  • the common layer 114 (or common electrode 115) is prevented from contacting the pixel electrodes and the side surfaces of layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.
  • the insulating layer 125 is preferably in contact with the side surfaces of the layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which the layers (e.g., carrier injection layer, common electrode, etc.) are formed on the island-shaped layers, making it possible to make the surface flatter. Therefore, the coverage of the carrier injection layer, common electrode, etc. can be improved.
  • the layers e.g., carrier injection layer, common electrode, etc.
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, and 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step due to the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided.
  • the step can be flattened by having the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, connection failure due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.
  • the upper surface of the insulating layer 127 preferably has a shape with high flatness.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.
  • the insulating layer 125 can be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film and a nitride insulating film can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 125 may have a single layer structure or a laminated structure. In particular, aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127 described later.
  • an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method to the insulating layer 125, it is possible to form an insulating layer 125 with few pinholes and excellent function of protecting the EL layer.
  • the insulating layer 125 may also have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of capturing or fixing (also called gettering) at least one of water and oxygen.
  • the insulating layer 125 functions as a barrier insulating layer, making it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to realize a highly reliable light-emitting element and further a highly reliable display device.
  • impurities typically at least one of water and oxygen
  • the insulating layer 125 has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer.
  • the impurity concentration in the insulating layer 125 it is possible to improve the barrier properties against at least one of water and oxygen.
  • the insulating layer 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • the photosensitive resin may be a photoresist.
  • the photosensitive resin may be either a positive-type material or a negative-type material.
  • the insulating layer 127 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element with the insulating layer 127, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • FIG. 32B shows an example of a cross section of the display unit 162 of the display device 50F.
  • the display device 50F is mainly different from the display device 50E in that a light-emitting element having a layer 133 and a colored layer are used in each subpixel of each color.
  • the configuration shown in Fig. 32B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 102 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Fig. 32A.
  • the display device 50F shown in FIG. 32B has light-emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.
  • Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed of the same material and in the same process. In addition, these three layers 133 are separated from each other. By providing an island-shaped EL layer for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This makes it possible to prevent unintended light emission due to crosstalk, and realize a display device with extremely high contrast.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 32B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B shown in FIG. 32B emit blue light.
  • the layer 133 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • Display device 50G A display device 50G shown in FIG. 33 differs from the display device 50F mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 102. It is preferable to use a material that is highly transparent to visible light for the substrate 102. On the other hand, the light-transmitting property of the material used for the substrate 152 does not matter.
  • FIG. 33 shows an example in which the light-shielding layer 117 is provided on the substrate 102, the insulating layer 153 is provided on the light-shielding layer 117, and the insulating layer 101 is provided on the insulating layer 153.
  • the colored layer 132R, the colored layer 132G, and the colored layer 132B are provided on the insulating layer 109, and the insulating layer 235 is provided on the colored layer 132R, the colored layer 132G, and the colored layer 132B.
  • the light-emitting element 130R which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.
  • Conductive layer 124R, conductive layer 124G, conductive layer 124B, conductive layer 126R, conductive layer 126G, and conductive layer 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115.
  • the common electrode 115 can be made of, for example, a metal with low electrical resistance, so that the voltage drop caused by the resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the aperture ratio of a pixel can be increased or the pixel size can be reduced.
  • Display device 50H] 34 shows a display device 50H that is a VA-mode liquid crystal display device.
  • a transistor 205R and a transistor 205G are shown as transistors provided in the display portion 162.
  • the display device 50H is provided with a liquid crystal element 60.
  • the liquid crystal element 60 has a conductive layer 112b, a conductive layer 263, and a liquid crystal 262 sandwiched between them.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 60.
  • the conductive layer 263 functions as a common electrode of the liquid crystal element 60.
  • the substrate 102 and the substrate 152 are bonded together by an adhesive layer 144.
  • liquid crystal 262 is sealed in the area surrounded by the substrate 102, the substrate 152, and the adhesive layer 144.
  • An insulating layer 224 can be provided between the insulating layer 109 and the conductive layer 263.
  • the insulating layer 224 functions as a spacer, and for example, the liquid crystal 262 can be configured not to overlap with the insulating layer 224.
  • the insulating layer 224 has a function of controlling the distance between the substrate 102 and the substrate 152 and controlling the thickness of the liquid crystal 262.
  • the insulating layer 224 is preferably provided so as to overlap, for example, with a transistor, in order to suppress a decrease in the aperture ratio caused by the insulating layer 224.
  • a colored layer 132R On the substrate 152 side, a colored layer 132R, a colored layer 132G, a light-shielding layer 117, an insulating layer 225, and a conductive layer 263 are provided.
  • a polarizing plate 260a is located on the outer surface of the substrate 152 (the side opposite the liquid crystal 262), and a polarizing plate 260b is located on the outer surface of the substrate 102 (the side opposite the liquid crystal 262).
  • a backlight can be provided outside the polarizing plate 260a (the side opposite the liquid crystal 262) or outside the polarizing plate 260b (the side opposite the liquid crystal 262).
  • the subpixels provided in the display unit 162 of the display device 50H each have a transistor, a liquid crystal element 60, and a colored layer.
  • a subpixel that emits red light has a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light.
  • a subpixel that emits green light has a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light.
  • a subpixel that emits blue light similarly has a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.
  • a conductive layer 264 is provided on the insulating layer 101, which can be formed of the same material and in the same process as the conductive layer 112a.
  • the conductive layer 264 has a portion that overlaps with the conductive layer 112b via the insulating layer 110.
  • a storage capacitor is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 between them.
  • an insulating layer 225 is provided to cover the colored layer 132R, the colored layer 132G, and the light-shielding layer 117.
  • the insulating layer 225 may function as a planarizing film.
  • the insulating layer 225 can make the surface of the conductive layer 263 approximately flat, so that the orientation state of the liquid crystal 262 can be made uniform.
  • an orientation layer for controlling the orientation of the liquid crystal 262 may be provided on the surfaces of the conductive layer 263 and the insulating layer 109, etc. that come into contact with the liquid crystal 262 (see the orientation layer 265 in Figures 36A and 36B).
  • the conductive layer 112b and the conductive layer 263 transmit visible light. That is, the display device 50H can be a transmissive liquid crystal display device.
  • the display device 50H can be a transmissive liquid crystal display device.
  • the orientation of the liquid crystal 262 can be controlled by the voltage supplied between the conductive layer 112b and the conductive layer 263, and the optical modulation of the light can be controlled. That is, the intensity of the light emitted through the polarizing plate 260b can be controlled.
  • the light that is incident is absorbed by the coloring layer except for a specific wavelength range, and the extracted light becomes light that exhibits a specific color.
  • the light that has passed through the coloring layer 132R can be light that exhibits red.
  • the light that has passed through the coloring layer 132G can be light that exhibits green.
  • a linear polarizing plate may be used as polarizing plate 260b, but a circular polarizing plate may also be used.
  • a circular polarizing plate for example, a linear polarizing plate and a quarter-wave retardation plate stacked together may be used.
  • polarizer 260b When a circular polarizer is used as polarizer 260b, a circular polarizer may also be used as polarizer 260a, or a normal linear polarizer may be used. Depending on the type of polarizer used for polarizer 260a and polarizer 260b, the cell gap, orientation, driving voltage, etc. of the liquid crystal element used in liquid crystal element 60 can be adjusted to achieve the desired contrast.
  • the conductive layer 263 is electrically connected to the conductive layer 166b provided on the substrate 102 side by the connector 223 in the connection portion 140.
  • the conductive layer 166b is electrically connected to the conductive layer 165b through an opening provided in the insulating layer 110. This allows a potential or signal to be supplied to the conductive layer 263 from an FPC or IC (not shown) arranged on the substrate 102 side.
  • the conductive layer 165b is formed from the same material and in the same process as the conductive layer 112a
  • the conductive layer 166b is formed from the same material and in the same process as the conductive layer 112b.
  • the connector 223 may be, for example, a conductive particle.
  • the conductive particles may be particles of resin or silica, etc., whose surfaces are coated with a metal material. Nickel or gold is preferably used as the metal material because it can reduce the contact resistance. It is also preferable to use particles coated with two or more metal materials in layers, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connector 223. In this case, the conductive particles may be crushed in the vertical direction. This increases the contact area between the connector 223 and the conductive layer electrically connected thereto, thereby reducing the contact resistance and suppressing the occurrence of defects such as poor connection. It is preferable to arrange the connector 223 so that it is covered by the adhesive layer 144. For example, it is preferable to disperse the connector 223 in the adhesive layer 144 before hardening.
  • connection portion 204 is provided in a region near the end of the substrate 102.
  • the conductive layer 166a is electrically connected to the FPC 172 via the connection layer 242.
  • the conductive layer 166a is electrically connected to the conductive layer 165a via an opening provided in the insulating layer 110.
  • the conductive layer 165a is formed from the same material and in the same process as the conductive layer 112a, and the conductive layer 166a is formed from the same material and in the same process as the conductive layer 112b.
  • Display device 50I] 35 is a liquid crystal display device in the FFS mode.
  • the display device 50I differs from the display device 50H mainly in the configuration of the liquid crystal element 60.
  • a conductive layer 263 that functions as a common electrode of the liquid crystal element 60 is provided on the insulating layer 110, and an insulating layer 261 is provided on the conductive layer 263.
  • a conductive layer 112b that functions as the other of the source electrode or drain electrode of the transistor and as a pixel electrode of the liquid crystal element 60 is provided on the insulating layer 261.
  • An insulating layer 109 is provided on the conductive layer 112b.
  • the conductive layer 112b has a comb-like shape or a shape with slits in a plan view.
  • the conductive layer 263 is arranged to have an area that overlaps with the conductive layer 112b. In the area that overlaps with the colored layer, there is a portion on the conductive layer 263 where the conductive layer 112b is not arranged.
  • a capacitance is formed by stacking the conductive layer 112b and the conductive layer 263 with the insulating layer 261 interposed therebetween. This eliminates the need to form a separate capacitive element, and allows the aperture ratio of the pixel to be increased.
  • both the conductive layer 112b and the conductive layer 263 may have a comb-shaped top surface.
  • the display device 50I in the liquid crystal element 60, only one of the conductive layer 112b and the conductive layer 263 has a comb-shaped top surface, so that the conductive layer 112b and the conductive layer 263 partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 263 to be used as a storage capacitance, eliminating the need to provide a separate capacitance element and increasing the aperture ratio of the display device.
  • Display device 50J In the display device 50J shown in Fig. 36A, the portion of the insulating layer 110b that overlaps with the liquid crystal element 60 is removed by, for example, etching.
  • the liquid crystal element 60 of the display device 50J has a portion in which a conductive layer 112c, an insulating layer 110a, an insulating layer 110c, an insulating layer 110d, and a conductive layer 112b are laminated in this order.
  • Figure 36A shows an example in which an alignment layer 265 is provided on the surfaces of the insulating layer 109, insulating layer 224, insulating layer 225, etc., facing the liquid crystal 262.
  • the alignment layer 265 has the function of controlling the alignment of the liquid crystal 262.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 60.
  • the conductive layer 112c functions as a common electrode of the liquid crystal element 60.
  • the conductive layer 112c can be formed using the same material and in the same process as the conductive layer 112a.
  • either one or both of the insulating layers 106 and 109 may have their portions overlapping with the liquid crystal element 60 removed by, for example, etching.
  • the insulating layer 109 may not be provided. This allows the electric field of the conductive layers 112b and 112c to be easily transmitted to the liquid crystal 262, enabling the liquid crystal element 60 to operate at high speed. Furthermore, not only is the light transmittance in the portion overlapping with the liquid crystal element 60 increased, but the effects of interface reflection and interface scattering can be suppressed.
  • one or two of the insulating layers 110a, 110c, and 110d may have their portions overlapping with the liquid crystal element 60 removed by, for example, etching. This also allows the electric field of the conductive layers 112b and 112c to be easily transmitted to the liquid crystal 262. Furthermore, the capacitance between the conductive layers 112b and 112c may be increased in some cases.
  • both the conductive layer 112b and the conductive layer 112c may have a comb-shaped top surface.
  • the display device 50J in the liquid crystal element 60, only one of the conductive layer 112b and the conductive layer 112c has a comb-shaped top surface, so that the conductive layer 112b and the conductive layer 112c partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 112c to be used as a storage capacitance, eliminating the need to provide a separate capacitance element and increasing the aperture ratio of the display device.
  • Display device 50K] 36B is different from the display device 50I in that a pixel electrode is provided over a common electrode.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 60.
  • An insulating layer 106 and an insulating layer 109 are provided over the conductive layer 112b, and a conductive layer 263 is provided over the insulating layer 109.
  • the conductive layer 263 functions as a common electrode in the liquid crystal element 60.
  • the conductive layer 263 has a comb-like shape or a shape provided with slits in a plan view.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution, and has a high frame frequency. Therefore, the display device can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can be applied to portions other than the display portion of an electronic device.
  • the semiconductor device of one embodiment of the present invention for a control portion of an electronic device, high speed and low power consumption can be achieved, which is preferable.
  • Examples of electronic devices include television devices, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display unit, since it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 37A to 37D An example of a wearable device that can be worn on the head will be described using Figures 37A to 37D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content
  • Electronic device 700A shown in FIG. 37A and electronic device 700B shown in FIG. 37B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • the display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device 700A and the electronic device 700B can be electronic devices capable of displaying images with extremely high resolution and a high frame frequency.
  • Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply, for example, a video signal through the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are equipped with batteries and can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation, a slide operation, or the like by the user, and can execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding.
  • a tap operation can execute processes such as pausing or resuming a video
  • a slide operation can execute processes such as fast-forwarding or rewinding.
  • the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, or an optical type.
  • a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 37C and electronic device 800B shown in FIG. 37D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, the electronic device 800A and the electronic device 800B can be electronic devices capable of displaying images with extremely high resolution and a high frame frequency. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Each of the electronic devices 800A and 800B can be considered to be electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head.
  • the mounting unit 823 is shown shaped like the temples of glasses, but is not limited to this.
  • the mounting unit 823 may be shaped like a helmet or band, for example, as long as it can be worn by the user.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies, for example, a video signal from a video output device and power for charging a battery provided in the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 37A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 37C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 37B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • electronic device 800B shown in FIG. 37D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • An electronic device can transmit information to an earphone via wire or wirelessly.
  • the electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and the like.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502. Therefore, the electronic device 6500 can be an electronic device capable of displaying images with extremely high resolution and a high frame frequency.
  • Figure 38B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 38C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the television device 7100 can be an electronic device capable of displaying images with extremely high resolution and a high frame frequency.
  • the television device 7100 shown in FIG. 38C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • a touch sensor may be provided on the display unit 7000, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG 38D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214.
  • the display unit 7000 is built into the housing 7211.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the notebook personal computer 7200 can be an electronic device capable of displaying images with extremely high resolution and a high frame frequency.
  • Figures 38E and 38F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 38E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 38F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000. Therefore, the digital signage 7300 and the digital signage 7400 can be electronic devices capable of displaying images with extremely high resolution and a high frame frequency.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 39A to 39G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • the display device of one embodiment of the present invention can be applied to the display portion 9001. Therefore, the electronic device can be one that is capable of displaying with extremely high resolution and has a high frame frequency.
  • the electronic device shown in Figures 39A to 39G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic device are not limited to these, and it can have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a function of, for example, providing a camera, taking still images or videos, and storing them on a recording medium (external or built into the camera), a function of displaying the taken images on the display unit, etc.
  • Figure 39A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as, for example, a smartphone.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • Figure 39A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notification of incoming e-mail, SNS, or telephone call, the title of the e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • the icon 9050, etc. may be displayed at the position where the information 9051 is displayed.
  • Figure 39B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.
  • FIG 39C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG 39D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself through the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • Figures 39E to 39G are perspective views showing a foldable mobile information terminal 9201.
  • Figure 39E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • Figure 39G is a folded state
  • Figure 39F is a perspective view of a state in the middle of changing from one of Figures 39E and 39G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and has excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.
  • Figure 40 is a cross-sectional view showing the structure of the sample produced in this example.
  • an insulating layer 401 was first formed on a glass substrate 402.
  • multiple samples were produced in which at least one of the material, film thickness, and film formation conditions of the insulating layer 401 was different from each other.
  • a copper film having a thickness of about 300 nm was formed on the insulating layer 401 by sputtering and processed to form conductive layers 411a and 411b.
  • an ITSO film having a thickness of about 100 nm was formed on the insulating layer 401, the conductive layer 411a, and the conductive layer 411b by sputtering and processed to form conductive layer 412a covering conductive layer 411a and conductive layer 412b covering conductive layer 411b.
  • a metal oxide layer 408 was formed on the insulating layer 401, the conductive layer 412a, and the conductive layer 412b.
  • the metal oxide layer 408 was formed so as to contact a part of the upper surface of the conductive layer 412a and a part of the upper surface of the conductive layer 412b.
  • the metal oxide layer 408 was formed in the region between the conductive layer 412a and the conductive layer 412b so as to contact the upper surface of the insulating layer 401, the side of the conductive layer 412a, and the side of the conductive layer 412b.
  • the metal oxide layer 408 was an In-Ga-Zn oxide film with a thickness of about 20 nm.
  • a silicon oxynitride film with a thickness of approximately 100 nm was formed as the insulating layer 406 on the metal oxide layer 408, the conductive layer 412a, and the conductive layer 412b by a PECVD method.
  • Table 1 shows the carrier concentration [cm ⁇ 3 ] in the metal oxide layer 408 of the sample produced in this example, and the contact resistance (hereinafter also simply referred to as contact resistance) [ ⁇ cm 2 ] between the conductive layer 412 a and the conductive layer 412 b and the metal oxide layer 408.
  • 41A, 41B, 42A, 42B, and 43 are graphs with the horizontal axis representing carrier concentration [cm -3 ] and the vertical axis representing contact resistance [ ⁇ cm2 ].
  • the "sample” in Table 1 and the legends in Figs. 41A to 43 indicate the material and film thickness of the insulating layer 401.
  • aluminum oxide is represented as AlOx and silicon nitride is represented as SiNx.
  • the insulating layer 401 was formed by sputtering using aluminum oxide as a target under conditions of an oxygen flow ratio of 70%, a substrate temperature at room temperature, a pressure of 0.6 Pa, and a source power of 2500 W.
  • the insulating layer 401 was formed by PECVD using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 2000 sccm under conditions of a pressure of 200 Pa, a source power of 2000 W, and a substrate temperature of 350° C.
  • the insulating layer 401 was formed by PECVD using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350°C. That is, in both condition 1 and condition 2, the insulating layer 401 was formed by PECVD in an atmosphere containing hydrogen. In condition 1, the flow rate of NH3 was made larger than that in condition 2.
  • condition 2 is a condition assuming the same film formation conditions as those of the insulating layer 110a and the insulating layer 110c shown in the first embodiment.
  • the insulating layer 401 had a laminated structure of a silicon nitride (SiNx) layer formed under condition 2 and a silicon nitride layer formed under condition 1 on the silicon nitride layer.
  • the insulating layer 401 had a laminated structure of an aluminum oxide (AlOx) layer formed under the same conditions as the above "AlOx”, and a silicon nitride layer formed under condition 1 on the aluminum oxide layer.
  • the carrier concentration was 1 ⁇ 10 20 cm ⁇ 3 or more and the contact resistance was 1 ⁇ 10 ⁇ 3 ⁇ cm 2 or less. It was also confirmed that the thicker the SiNx layer is, the higher the carrier concentration in the metal oxide layer 408 is, and the smaller the contact resistance is.
  • the carrier concentration in the metal oxide layer 408 is higher and the contact resistance is smaller under condition 1 than under condition 2.
  • the carrier concentration in the metal oxide layer 408 is higher and the contact resistance is smaller under the condition in which the SiNx layer is formed under an atmosphere with a high NH 3 flow rate.
  • a transistor corresponding to the configuration of the transistor 100 shown in Figures 6A, 6B, and 6C was manufactured.
  • Figures 24A to 27B can be referred to for the method of manufacturing the transistor.
  • a silicon nitride film having a thickness of about 200 nm was formed by PECVD on a glass substrate 102 as an insulating layer 101.
  • the insulating layer 101 was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 2000 sccm under conditions of a pressure of 200 Pa, a source power of 2000 W, and a substrate temperature of 350°C.
  • a copper film having a thickness of approximately 300 nm and an ITSO film having a thickness of approximately 100 nm were deposited in that order on the insulating layer 101 by sputtering, and then processed to form the conductive layer 112a.
  • the insulating layer 110a and the insulating layer 110b were formed in this order on the conductive layer 112a and the insulating layer 101.
  • a silicon nitride film having a thickness of about 100 nm was formed by the PECVD method. Specifically, the insulating layer 110a was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350° C.
  • a silicon oxynitride film having a thickness of 500 nm was formed by the PECVD method. Specifically, the insulating layer 110b was formed using SiH4 gas at a flow rate of 200 sccm and N2O gas at a flow rate of 6000 sccm under conditions of a pressure of 200 Pa, a source power of 1200 W, and a substrate temperature of 350°C.
  • the thickness of the insulating layer 110b was set to be the designed channel length of the transistor.
  • the designed channel length of the transistor was set to 0.50 ⁇ m.
  • an In-Ga-Zn oxide film having a thickness of about 20 nm was formed on the insulating layer 110b to form the metal oxide layer 149.
  • the insulating layer 110c and the insulating layer 110d were formed in sequence on the insulating layer 110b.
  • a silicon nitride film having a thickness of about 50 nm was formed by the PECVD method.
  • the insulating layer 110c was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350°C.
  • a silicon nitride film having a thickness of about 100 nm was formed by the PECVD method. Specifically, the insulating layer 110d was formed using SiH4 gas at a flow rate of 200 sccm, N2 gas at a flow rate of 2000 sccm, and NH3 gas at a flow rate of 2000 sccm under conditions of a pressure of 200 Pa, a source power of 2000 W, and a substrate temperature of 350°C.
  • an ITSO film with a thickness of approximately 100 nm was formed on the insulating layer 110d by sputtering and processed to form the conductive layer 112b.
  • the conductive layer 112b was processed using a wet etching method to form an opening 143 in the conductive layer 112b. Furthermore, the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a were processed using a dry etching method to form an opening 141 in the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a.
  • a metal oxide film was formed as the semiconductor film 108f on the insulating layer 110d and the conductive layer 112b.
  • An In-Ga-Zn oxide film with a thickness of about 20 nm was formed as the semiconductor film 108f.
  • the insulating layer 106 was formed on the insulating layer 110d, the conductive layer 112b, and the semiconductor layer 108.
  • a silicon oxynitride film having a thickness of about 50 nm was formed by the PECVD method. Specifically, the insulating layer 106 was formed under the conditions of a SiH 4 gas flow rate of 50 sccm, a N 2 O gas flow rate of 18000 sccm, a pressure of 200 Pa, a source power of 250 W, and a substrate temperature of 350° C. The insulating layer 106 was formed under the conditions of a lower film formation rate than the insulating layer 110b.
  • a conductive film that becomes the conductive layer 104 was formed on the insulating layer 106 and processed to form the conductive layer 104.
  • a titanium film with a thickness of about 50 nm, an aluminum film with a thickness of about 400 nm, and a titanium film with a thickness of about 50 nm were formed in this order by a sputtering method.
  • a silicon nitride oxide film with a thickness of about 300 nm was formed as the insulating layer 109 by the PECVD method. Then, a heat treatment was performed at 300° C. for 1 hour in a CDA atmosphere. Then, a polyimide film with a thickness of about 1.5 ⁇ m was formed as a planarization layer (not shown), and a heat treatment was performed at 250° C. for 1 hour in a nitrogen atmosphere.
  • the transistor fabricated in this example is an n-channel transistor, and as described above, the designed channel length (L) was 0.50 ⁇ m.
  • the designed channel width (W) was 6.30 ⁇ m (opening diameter 2 ⁇ m ⁇ ).
  • Fig. 44 shows the Id-Vg characteristics of the transistor when the conductive layer 112b functions as a source electrode.
  • the vertical axis represents the drain current Id [A] and the field effect mobility ⁇ FE [cm 2 /Vs], and the horizontal axis represents the gate voltage Vg [V].
  • the Id-Vg characteristics are shown by a solid line, and the field effect mobility is shown by a dotted line.
  • the voltage (gate voltage Vg) applied to the conductive layer 104 was changed from -10 V to +10 V in increments of 0.1 V.
  • the voltage (source voltage Vs) applied to the source electrode was set to 0 V
  • the voltage (drain voltage Vd) applied to the drain electrode was set to 0.1 V and 5.1 V.
  • the transistors fabricated in this example had high on-state current and good switching characteristics.
  • the average threshold voltage of the transistors fabricated in this example was 0.72 V, a positive value. Therefore, it was confirmed that a transistor with normally-off characteristics was fabricated.
  • the effective channel length of the transistor was 0.62 ⁇ m, which was larger than the designed channel length of 0.50 ⁇ m.
  • the insulating layer 101 and the insulating layer 110d were formed under conditions where the flow rate of NH 3 was larger than that of the insulating layer 110a and the insulating layer 110c. It is considered that the hydrogen content of the insulating layer 101 and the insulating layer 110d was larger than that of the insulating layer 110a and the insulating layer 110c.
  • the hydrogen contained in the insulating layer 101 was supplied to a region in contact with the conductive layer 112a of the semiconductor layer 108, so that the contact resistance between the semiconductor layer 108 and the conductive layer 112a was reduced, and the hydrogen contained in the insulating layer 110d was supplied to a region in contact with the conductive layer 112b of the semiconductor layer 108, so that the contact resistance between the semiconductor layer 108 and the conductive layer 112b was reduced, and therefore a transistor with a high on-current was fabricated.
  • the insulating layer 110a is an insulating layer in which hydrogen does not easily diffuse, and it is believed that this has prevented the hydrogen contained in the insulating layer 101 from being supplied to the region of the semiconductor layer 108 that is in contact with the insulating layer 110a and the region of the semiconductor layer 108 that is in contact with the insulating layer 110b.
  • the insulating layer 110c is an insulating layer in which hydrogen does not easily diffuse, and it is believed that this has prevented the hydrogen contained in the insulating layer 110d from being supplied to the region of the semiconductor layer 108 that is in contact with the insulating layer 110c and the region of the semiconductor layer 108 that is in contact with the insulating layer 110b.
  • the effective channel length of the transistor fabricated in this embodiment is longer than the designed channel length. It is believed that this has allowed the fabrication of a transistor that has normally-off characteristics and exhibits good switching characteristics.
  • a transistor corresponding to the configuration of the transistor 100 shown in FIG. 6A, FIG. 6B, FIG. 6C, etc. was manufactured.
  • a plurality of such transistors were manufactured on one substrate 102.
  • For the method of manufacturing the transistor refer to FIG. 24A to FIG. 27B.
  • a silicon nitride film having a thickness of about 30 nm was formed by PECVD on a glass substrate 102 as an insulating layer 101.
  • the insulating layer 101 was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 2000 sccm under conditions of a pressure of 200 Pa, a source power of 2000 W, and a substrate temperature of 200°C.
  • an ITSO film with a thickness of about 10 nm and a copper film with a thickness of about 100 nm were formed in that order on the insulating layer 101 by sputtering and processed.
  • an ITSO film with a thickness of about 100 nm was formed by sputtering and processed. In this way, the conductive layer 112a was formed.
  • the insulating layer 110a and the insulating layer 110b were formed in this order on the conductive layer 112a and the insulating layer 101.
  • a silicon nitride film having a thickness of about 200 nm was formed by the PECVD method. Specifically, the insulating layer 110a was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350° C.
  • a silicon oxynitride film having a thickness of 500 nm was formed by the PECVD method. Specifically, the insulating layer 110b was formed using SiH4 gas at a flow rate of 200 sccm and N2O gas at a flow rate of 6000 sccm under conditions of a pressure of 200 Pa, a source power of 1200 W, and a substrate temperature of 350°C.
  • the thickness of the insulating layer 110b was set to be the designed channel length of the transistor.
  • the designed channel length of the transistor was set to 0.50 ⁇ m.
  • a heat treatment was performed in a nitrogen atmosphere at 400° C. for 1 hour.
  • a plasma treatment was performed for 240 seconds in an atmosphere containing N 2 O gas.
  • the flow rate of N 2 O gas was 3000 sccm, the pressure was 133 Pa, and the power supply power was 500 W.
  • an In-Ga-Zn oxide film having a thickness of about 20 nm was formed on the insulating layer 110b to form the metal oxide layer 149.
  • the insulating layer 110c and the insulating layer 110d were formed in sequence on the insulating layer 110b.
  • a silicon nitride film having a thickness of about 100 nm was formed by the PECVD method.
  • the insulating layer 110c was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350°C.
  • a silicon nitride film having a thickness of about 100 nm was formed by the PECVD method. Specifically, the insulating layer 110d was formed using SiH4 gas at a flow rate of 200 sccm, N2 gas at a flow rate of 2000 sccm, and NH3 gas at a flow rate of 2000 sccm under conditions of a pressure of 200 Pa, a source power of 2000 W, and a substrate temperature of 350°C.
  • an ITSO film with a thickness of approximately 100 nm was formed on the insulating layer 110d by sputtering and processed to form the conductive layer 112b.
  • the conductive layer 112b was processed using a wet etching method to form an opening 143 in the conductive layer 112b. Furthermore, the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a were processed using a dry etching method to form an opening 141 in the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a.
  • a metal oxide film was formed as the semiconductor film 108f on the insulating layer 110d and the conductive layer 112b.
  • An In-Ga-Zn oxide film with a thickness of about 20 nm was formed as the semiconductor film 108f.
  • the insulating layer 106 was formed on the insulating layer 110d, the conductive layer 112b, and the semiconductor layer 108.
  • a silicon oxynitride film having a thickness of about 50 nm was formed by the PECVD method. Specifically, the insulating layer 106 was formed under the conditions of a SiH 4 gas flow rate of 50 sccm, a N 2 O gas flow rate of 18000 sccm, a pressure of 200 Pa, a source power of 250 W, and a substrate temperature of 350° C. The insulating layer 106 was formed under the conditions of a lower film formation rate than the insulating layer 110b.
  • a conductive film that becomes the conductive layer 104 was formed on the insulating layer 106 and processed to form the conductive layer 104.
  • a titanium film with a thickness of about 50 nm, an aluminum film with a thickness of about 400 nm, and a titanium film with a thickness of about 50 nm were formed in this order by a sputtering method.
  • a silicon nitride oxide film with a thickness of about 300 nm was formed as the insulating layer 109 by the PECVD method. Then, a heat treatment was performed at 300° C. for 1 hour in a CDA atmosphere. Then, a polyimide film with a thickness of about 1.5 ⁇ m was formed as a planarization layer (not shown), and a heat treatment was performed at 250° C. for 1 hour in a nitrogen atmosphere.
  • the transistors fabricated in this example were n-channel transistors, and as mentioned above, the designed channel length was 0.50 ⁇ m.
  • the designed channel width was 6.30 ⁇ m (opening diameter 2 ⁇ m ⁇ ).
  • Fig. 45 shows the Id-Vg characteristics of the transistor when the conductive layer 112b functions as a source electrode.
  • the vertical axis represents the drain current Id [A] and the field effect mobility ⁇ FE [cm 2 /Vs], and the horizontal axis represents the gate voltage Vg [V].
  • the Id-Vg characteristics are shown by a solid line, and the field effect mobility is shown by a dotted line.
  • the voltage (gate voltage Vg) applied to the conductive layer 104 was changed from -10 V to +10 V in increments of 0.1 V.
  • the voltage (source voltage Vs) applied to the source electrode was set to 0 V
  • the voltage (drain voltage Vd) applied to the drain electrode was set to 0.1 V and 5.1 V.
  • the transistors fabricated in this example had high on-state current and good switching characteristics.
  • the average threshold voltage of the transistors fabricated in this example was 0.58 V, a positive value. Therefore, it was confirmed that a transistor with normally-off characteristics was fabricated.
  • Figure 46A shows the probability distribution of the threshold voltage Vth of the transistor fabricated in this example.
  • Figure 46B shows the probability distribution of the field effect mobility ⁇ FE of the transistor fabricated in this example.
  • the threshold voltage Vth and the field effect mobility ⁇ FE were measured with the source voltage Vs set to 0 V and the drain voltage Vd set to 0.1 V.
  • 46A and 46B show the cumulative probability of the threshold voltage Vth and field effect mobility ⁇ FE of 120 transistors, respectively.
  • the horizontal axis shows the threshold voltage Vth [V]
  • the vertical axis shows the cumulative probability [%].
  • the horizontal axis shows the field effect mobility ⁇ FE [cm 2 /Vs]
  • the vertical axis shows the cumulative probability [%].
  • 3 ⁇ ( ⁇ is the standard deviation) of the threshold voltage Vth was 0.10 V
  • 3 ⁇ of the field effect mobility ⁇ FE was 1.3 cm 2 /Vs.
  • Figure 47A is a graph showing the effective channel length L [ ⁇ m] of the transistors fabricated in this example.
  • the effective channel length L was calculated using Figure 45.
  • the average value of the effective channel length L was 0.46 ⁇ m, which was close to the designed channel length of 0.50 ⁇ m.
  • 3 ⁇ of the effective channel length L was 0.04 ⁇ m, which was a very small value compared to the average value of the effective channel length L of 0.46 ⁇ m. Therefore, it was confirmed that the variation in the effective channel length L for each transistor was very small.
  • GBT Gate Bias Temperature
  • PBTS Positive Bias Temperature Stress
  • NBTIS Negative Bias Temperature Illumination Stress
  • PBTS test a test in which a positive potential (positive bias) is applied to the gate relative to the source potential and drain potential and the device is held at high temperature
  • NBTS test a test in which a negative potential (negative bias) is applied to the gate and the device is held at high temperature
  • the PBTS and NBTS tests conducted under light irradiation are called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS test, respectively.
  • the substrate 102 was kept at 60°C, and a voltage of 0 V was applied to the source of the transistor, 0.1 V to the drain, and 10 V to the gate, and this state was maintained for 1 hour.
  • the test environment was dark.
  • the substrate 102 was kept at 60°C, and a voltage of 0 V was applied to the source and drain of the transistor and -10 V to the gate while irradiating with 5000 lx of white LED light, and this state was maintained for 1 hour.
  • the white LED light was irradiated from the substrate 102 side.
  • the threshold voltage of the transistor before the PBTS test and before the NBTIS test was 0.25 V.
  • Figure 47B shows the variation ⁇ Vth [V] of the threshold voltage before and after the PBTS test and before and after the NBTIS test. As shown in Figure 47B, the variation of the threshold voltage was small in both the PBTS test and the NBTIS test, confirming good reliability.
  • a transistor corresponding to the configuration of the transistor 100 shown in FIG. 6A, FIG. 6B, FIG. 6C, etc. was manufactured.
  • a plurality of such transistors were manufactured on one substrate 102.
  • For the method of manufacturing the transistor refer to FIG. 24A to FIG. 27B.
  • insulating layer 101 and conductive layer 112a were formed on substrate 102, which was a glass substrate, under the same conditions as those shown in Example 3.
  • insulating layer 110a and insulating layer 110b were formed in this order on conductive layer 112a and insulating layer 101.
  • As insulating layer 110a an aluminum oxide film having a thickness of about 5 nm was formed by sputtering with an oxygen flow rate ratio of 70% and a substrate temperature of room temperature. Insulating layer 110b was formed under the same conditions as those shown in Example 3.
  • N 2 O gas The flow rate of N 2 O gas was 8700 sccm, the pressure was 200 Pa, and the source power was 500 W.
  • a metal oxide layer 149 was formed on the insulating layer 110b, a heat treatment was performed, and then the metal oxide layer 149 was removed.
  • insulating layer 110c and insulating layer 110d were formed in this order on insulating layer 110b.
  • insulating layer 110c an aluminum oxide film having a thickness of about 5 nm was formed by sputtering with an oxygen flow rate ratio of 70% and a substrate temperature of room temperature. Insulating layer 110d was formed under the same conditions as those shown in Example 3.
  • conductive layer 112b was formed under the same conditions as those shown in Example 3.
  • the conductive layer 112b was processed using a wet etching method to form an opening 143 in the conductive layer 112b. Furthermore, the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a were processed using a dry etching method to form an opening 141 in the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a.
  • the semiconductor layer 108, the insulating layer 106, the conductive layer 104, the insulating layer 109, and the planarization layer were formed under the same conditions as those shown in Example 3.
  • the transistor fabricated in this example was an n-channel transistor, with a designed channel length of 0.50 ⁇ m.
  • the designed channel width was 6.30 ⁇ m (opening diameter 2 ⁇ m ⁇ ).
  • FIG. 48 shows the Id-Vg characteristics of the transistor when the conductive layer 112b functions as a source electrode.
  • the vertical axis represents the drain current Id [A] and the field effect mobility ⁇ FE [cm 2 /Vs], and the horizontal axis represents the gate voltage Vg [V].
  • the Id-Vg characteristics are shown by a solid line, and the field effect mobility is shown by a dotted line.
  • the measurement conditions of the Id-Vg characteristics of the transistor were the same as in Example 3. In FIG.
  • the drain current Id [A] and the field effect mobility ⁇ FE [cm 2 /Vs] each show two data, as in FIG. 45.
  • the transistor fabricated in this example had a high on-current and good switching characteristics.
  • the average threshold voltage of the transistor fabricated in this example was 0.55 V, a positive value. Therefore, it was confirmed that a transistor with normally-off characteristics was fabricated.
  • Figure 49A shows the probability distribution of the threshold voltage Vth of the transistor fabricated in this example.
  • Figure 49B shows the probability distribution of the drain current Id of the transistor fabricated in this example.
  • the threshold voltage Vth was measured with a source voltage Vs of 0 V and a drain voltage Vd of 0.1 V.
  • the drain current Id was measured with a source voltage Vs of 0 V, a drain voltage Vd of 5.1 V, and a gate voltage of 10 V.
  • the drain current Id of the transistor in the on state was measured.
  • Figures 49A and 49B show the cumulative probability of the threshold voltage Vth and drain current Id of 120 transistors, respectively.
  • the horizontal axis shows the threshold voltage Vth [V]
  • the vertical axis shows the cumulative probability [%].
  • the horizontal axis shows the drain current Id [ ⁇ A]
  • the vertical axis shows the cumulative probability [%].
  • the 3 ⁇ ( ⁇ is the standard deviation) of the threshold voltage Vth was 0.13 V
  • the 3 ⁇ of the field effect mobility ⁇ FE was 66.2 ⁇ A.
  • the threshold voltage Vth of 116 of the 120 transistors was 0.46 V or more and 0.60 V or less.
  • the drain current Id of 116 of the 120 transistors was 500 ⁇ A or more and 600 ⁇ A or less. From the above, it was confirmed that the variation in electrical characteristics between transistors was small.
  • Figure 50A is a graph showing the effective channel length L [ ⁇ m] of the transistors fabricated in this example.
  • the effective channel length L was calculated using Figure 48.
  • the average value of the effective channel length L was 0.41 ⁇ m, which is close to the designed channel length of 0.50 ⁇ m.
  • 3 ⁇ of the effective channel length L was 0.04 ⁇ m, which is a very small value compared to the average value of the effective channel length L of 0.41 ⁇ m. Therefore, it was confirmed that the variation in the effective channel length L for each transistor is very small.
  • the reliability of the transistor fabricated above was evaluated by a PBTS test and an NBTIS test.
  • the PBTS test and the NBTIS test were performed under the same conditions as those shown in Example 3.
  • the threshold voltage of the transistor before the PBTS test and before the NBTIS test was 0.29 V.
  • Figure 50B shows the variation ⁇ Vth [V] of the threshold voltage before and after the PBTS test and before and after the NBTIS test. As shown in Figure 50B, the variation of the threshold voltage was small in both the PBTS test and the NBTIS test, confirming good reliability.
  • a transistor corresponding to the configuration of the transistor 100 shown in Figures 6A, 6B, and 6C was manufactured.
  • Figures 24A to 27B can be referred to for the method of manufacturing the transistor.
  • the insulating layer 101 and the conductive layer 112a were formed on the substrate 102, which was a glass substrate, under the same conditions as those shown in Example 3. Then, the insulating layer 110a and the insulating layer 110b were formed in order on the conductive layer 112a and the insulating layer 101.
  • a silicon nitride film having a thickness of about 100 nm was formed by the PECVD method.
  • the insulating layer 110a was formed using SiH4 gas with a flow rate of 200 sccm, N2 gas with a flow rate of 2000 sccm, and NH3 gas with a flow rate of 100 sccm under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350°C. Also, as the insulating layer 110b, a silicon oxynitride film having a thickness of 500 nm was formed by the PECVD method.
  • the insulating layer 110b was formed using SiH4 gas at a flow rate of 290 sccm and N2O gas at a flow rate of 8700 sccm under conditions of a pressure of 200 Pa, a source power of 1160 W, and a substrate temperature of 350°C.
  • the thickness of the insulating layer 110b was set to be the designed channel length of the transistor.
  • the designed channel length of the transistor was set to 0.50 ⁇ m.
  • plasma treatment was performed for 240 seconds in an atmosphere containing N 2 O gas.
  • the flow rate of N 2 O gas was 3000 sccm, the pressure was 133 Pa, and the power of the source was 500 W.
  • an In-Ga-Zn oxide film having a thickness of about 20 nm was formed on the insulating layer 110b to form the metal oxide layer 149.
  • the insulating layer 110c and the insulating layer 110d were formed in order on the insulating layer 110b.
  • a silicon nitride film having a thickness of about 50 nm was formed by the PECVD method. Specifically, the insulating layer 110c was formed under the conditions of a pressure of 100 Pa, a power supply power of 2000 W, and a substrate temperature of 350° C., using SiH 4 gas with a flow rate of 200 sccm, N 2 gas with a flow rate of 2000 sccm, and NH 3 gas with a flow rate of 100 sccm.
  • the insulating layer 110d was formed under the same conditions as those shown in Example 3.
  • the conductive layer 112b was formed under the same conditions as those shown in Example 3.
  • the conductive layer 112b was processed using a wet etching method to form an opening 143 in the conductive layer 112b. Furthermore, the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a were processed using a dry etching method to form an opening 141 in the insulating layer 110d, the insulating layer 110c, the insulating layer 110b, and the insulating layer 110a. Three openings 143 and three openings 141 were formed in parallel.
  • a metal oxide film was formed as the semiconductor film 108f on the insulating layer 110d and the conductive layer 112b.
  • An In-Ga-Zn oxide film with a thickness of about 50 nm was formed as the semiconductor film 108f.
  • the insulating layer 106 was formed on the insulating layer 110d, the conductive layer 112b, and the semiconductor layer 108.
  • the insulating layer 106 was formed under the same conditions as those shown in Example 3.
  • a conductive film that becomes the conductive layer 104 was formed on the insulating layer 106 and processed to form the conductive layer 104.
  • a titanium film with a thickness of about 50 nm, an aluminum film with a thickness of about 200 nm, and a titanium film with a thickness of about 50 nm were formed in this order by a sputtering method.
  • the insulating layer 109 and the planarization layer were formed under the same conditions as those shown in Example 3.
  • the transistor fabricated in this example is an n-channel transistor, and as described above, the designed channel length was 0.50 ⁇ m.
  • the designed channel width was 18.84 ⁇ m (three openings 141 with an opening diameter of 2 ⁇ m ⁇ ).
  • the constant current stress test was performed by maintaining the following conditions for a predetermined time: source voltage Vs was 0 V, drain voltage Vd was 6.0 V, gate voltage Vg was 5.0 V, drain current Id was 100 ⁇ A, and substrate temperature was 85° C.
  • the predetermined time was the retention time.
  • the conductive layer 112b was made to function as a source electrode.
  • Figure 51A shows the Id-Vg characteristics of a transistor when the conductive layer 112b functions as a source electrode.
  • the vertical axis represents the drain current Id [A]
  • the horizontal axis represents the gate voltage Vg [V].
  • the transistors fabricated in this example were confirmed to have high on-currents and good switching characteristics at all retention times.
  • the threshold voltages of the transistors fabricated in this example were confirmed to be higher than 0 V at all retention times, and to have normally-off characteristics.
  • Figure 51B is a graph showing the variation ⁇ Vth [V] of the threshold voltage of a transistor when the retention time is 100 s, 500 s, 1000 s, 2000 s, 1 hr, 2 hr, 4 hr, 6 hr, and 10 hr.
  • the variation ⁇ Vth indicates the variation based on a retention time of 0 s.
  • the drain voltage Vd was set to 5.1 V.
  • Fig. 51B shows an approximation formula based on the actual measurement value of the fluctuation amount ⁇ Vth.
  • x is the retention time [hr]
  • y is the fluctuation amount Vth [V]
  • y 0.1107x 0.4072 .
  • the fluctuation amount ⁇ Vth when the retention time is 1000 hr is extrapolated from the approximation formula, it is 1.85V.
  • the transistor fabricated in this example is estimated to have a threshold voltage fluctuation of less than 2.00 V even with a retention time of 1000 hours, confirming that the threshold voltage fluctuation is small.

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010177450A (ja) * 2009-01-29 2010-08-12 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2015111663A (ja) * 2013-11-01 2015-06-18 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2016092058A (ja) * 2014-10-30 2016-05-23 株式会社ジャパンディスプレイ 半導体装置
WO2016084732A1 (ja) * 2014-11-28 2016-06-02 シャープ株式会社 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010177450A (ja) * 2009-01-29 2010-08-12 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2015111663A (ja) * 2013-11-01 2015-06-18 株式会社半導体エネルギー研究所 半導体装置およびその作製方法
JP2016092058A (ja) * 2014-10-30 2016-05-23 株式会社ジャパンディスプレイ 半導体装置
WO2016084732A1 (ja) * 2014-11-28 2016-06-02 シャープ株式会社 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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