WO2024127580A1 - Phase adjusting circuit - Google Patents

Phase adjusting circuit Download PDF

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Publication number
WO2024127580A1
WO2024127580A1 PCT/JP2022/046188 JP2022046188W WO2024127580A1 WO 2024127580 A1 WO2024127580 A1 WO 2024127580A1 JP 2022046188 W JP2022046188 W JP 2022046188W WO 2024127580 A1 WO2024127580 A1 WO 2024127580A1
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Prior art keywords
circuit
signal
output
amplifier circuit
phase adjustment
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PCT/JP2022/046188
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French (fr)
Japanese (ja)
Inventor
勉 竹谷
宗彦 長谷
宏行 高橋
斉 脇田
照男 徐
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日本電信電話株式会社
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Priority to PCT/JP2022/046188 priority Critical patent/WO2024127580A1/en
Publication of WO2024127580A1 publication Critical patent/WO2024127580A1/en

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  • the present invention relates to a sine wave phase adjustment circuit.
  • sine waves play an important role.
  • sine waves are sometimes used to generate carrier waves, and sometimes as clocks.
  • clocks are used not only as carrier waves, but also as a timing reference to determine data.
  • clock data recovery When using a clock as a timing reference for such data judgments, it is necessary to adjust the phase of the clock and make data judgments at the appropriate timing.
  • One method for making data judgments at the appropriate timing is clock data recovery.
  • a known means for achieving clock data recovery is a configuration that uses a phase comparator and a phase adjustment circuit. In this configuration, the phase is compared by some means, and the desired phase is generated based on the comparison results.
  • ⁇ is as follows:
  • sine waves sin ⁇ t and cos ⁇ t are generated by using a Quadrature-VCO (Voltage Controlled Oscillator) 200.
  • the Quadrature-VCO 200 Due to its structure, the Quadrature-VCO 200 has a low oscillation frequency, which makes it difficult to use in the device's limit range.
  • a method of using a 90-degree hybrid is known as a method of creating a sine wave with a fixed phase difference of ⁇ /2 from a sine wave, but when using a 90-degree hybrid, there is an issue that it only works at specific frequencies.
  • the present invention has been made to solve the above problems, and aims to provide a phase adjustment circuit that can be used over a wide range of frequencies.
  • the phase adjustment circuit of the present invention is characterized by comprising a clock generation circuit configured to generate a sine wave clock signal, an amplifier circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line whose input end is connected to the output terminal of the amplifier circuit, a load circuit whose impedance can be adjusted externally and connected to the end of the transmission line, and an output circuit whose input is a signal obtained by adding the output signal of the amplifier circuit and the return signal from the transmission line at the output terminal of the amplifier circuit.
  • the present invention by providing a clock generation circuit, an amplifier circuit, a transmission line, a load circuit, and an output circuit, it is no longer necessary to use a quadrature-VCO as in the past as a clock generation circuit that is the basis of a sine wave signal, and an LC-VCO consisting of a general LC oscillator can be used as the clock generation circuit, making it possible to generate a clock with an intermediate phase and to achieve operation at a higher frequency. Furthermore, compared to a configuration that uses a 90-degree hybrid as the clock generation circuit, the present invention can be used at a wider range of frequencies.
  • FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing a simulation result of the phase adjustment circuit according to the first embodiment of the present invention.
  • FIG. 3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention.
  • FIG. 4 is a circuit diagram showing the configuration of an amplifier circuit according to a second embodiment of the present invention.
  • FIG. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a third embodiment of the present invention.
  • FIG. 6 is a circuit diagram showing the configuration of a mixer according to a third embodiment of the present invention.
  • FIG. 7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention.
  • FIG. 8 is a block diagram showing the configuration of a phase adjustment circuit according to a fifth embodiment of the present invention.
  • FIG. 9 is a block diagram showing the configuration of a phase adjustment circuit according to a sixth embodiment of the present invention.
  • FIG. 10 is a circuit diagram showing the configuration of a signal quality evaluation circuit according to a sixth embodiment of the present invention.
  • FIG. 11 is a circuit diagram showing the configuration of a load circuit according to a seventh embodiment of the present invention.
  • FIG. 12 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 14 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 15 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 16 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 17 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 18 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 19 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 20 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • FIG. 21 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention.
  • a function of adjusting a sine wave to an arbitrary phase is realized by a circuit configuration in which a transmission line having a variable impedance load is provided for a clock buffer.
  • Fig. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention.
  • the phase adjustment circuit includes a clock generation circuit 1 that generates a sine wave clock signal, an amplifier circuit 2 that amplifies the clock signal output from the clock generation circuit 1, an amplifier circuit 3 whose input terminal is connected to the output terminal of the amplifier circuit 2, a transmission line 4 whose input end is connected to the output terminal of the amplifier circuit 2, and a load circuit 5 connected to the end of the transmission line 4 and capable of adjusting the impedance from outside.
  • the sinusoidal clock signal output from the clock generation circuit 1 passes through the amplifier circuit 2 and is input to the amplifier circuit 3 and the transmission line 4. Because the impedance of the transmission line 4 differs from the impedance of the load circuit 5, the signal input to the transmission line 4 is reflected at the end of the transmission line 4 and returns to the output of the amplifier circuit 2. As a result, the signal output from the amplifier circuit 2 and the signal delayed by traveling back and forth on the transmission line 4 are added together at the output terminal of the amplifier circuit 2.
  • the amplifier circuits 2 and 3 a buffer circuit with an amplification factor of 1, an amplifier circuit with an amplification factor higher than 1, or an amplifier circuit with an amplification factor higher than 0 and lower than 1 may be used.
  • the amplifier circuit 3 is used as an output circuit that receives as input a signal obtained by adding the output signal of the amplifier circuit 2 and the return signal from the transmission line 4 at the output terminal of the amplifier circuit 2.
  • the output circuit does not have to be an amplifier circuit, and may be a circuit that combines a mixer and a filter.
  • phase adjustment circuit The operation of the phase adjustment circuit will be explained using a formula. If the signal input from the amplifier circuit 2 to the transmission line 4 is A sin ⁇ t, and the signal reflected back from the transmission line 4 is B sin( ⁇ t + ⁇ ), then the final output signal OUT of the amplifier circuit 3 will be expressed by the following formula.
  • the amplification degree of the amplifier circuit 3 is set to 1.
  • e j ⁇ t indicates a reference sine wave.
  • B sin( ⁇ t + ⁇ ) is a reflected wave returning from the transmission line 4, so it is not amplified and B ⁇ A.
  • the values of B and ⁇ depend on the impedance of the load circuit 5 and the length of the transmission line 4.
  • equation (3) From equation (3), it can be seen that by adding a sine wave of a reference frequency and a sine wave differing by an arbitrary phase ⁇ , a sine wave with a phase difference of ⁇ from the sine wave of the reference phase can be generated. Since the amount of change in the output phase can be calculated by re j ⁇ , equation (3) can be rearranged to obtain equation (4).
  • the output impedance of the amplifier circuit 2 is r o
  • the characteristic impedance of the transmission line 4 is Z 0
  • the impedance of the load circuit 5 is Z T.
  • the impedance Z in of the transmission line 4 and the load circuit 5 as viewed from the input of the transmission line 4 is given by equation (6).
  • B is the phase constant
  • L is the length of the transmission line 4. Since B ⁇ L is determined by the physical structure and the frequency of the signal, when focusing on a specific frequency, tanBL may be regarded as a constant.
  • the impedance Z out at the output terminal of the amplifier circuit 2 is the combined resistance of Z in and r o , and can be expressed as in equation (7).
  • the output voltage of an amplifier circuit is expressed as the product of the transconductance and the impedance of the output terminal. Therefore, if the transconductance of the amplifier circuit 2 is gma, the output voltage Vout of the amplifier circuit 2 can be expressed as shown in equation (8).
  • V out gma ⁇ Z out (8)
  • Reference numeral 20 denotes a sine wave output from the clock generation circuit 1
  • reference numeral 21 denotes a sine wave whose phase has been changed by the phase adjustment circuit of this embodiment.
  • the frequency of the sine wave is 60 GHz. It can be confirmed that by changing the impedance ZT of the load circuit 5, the phase of the sine wave changes by approximately 3 ps in time.
  • the range of the impedance ZT is not limited to real numbers, but may be complex numbers.
  • the characteristic impedance Z0 of the transmission line 4 and the output impedance r0 of the amplifier circuit 2 may be made to match each other.
  • [Second embodiment] 3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention.
  • the phase adjustment circuit of this embodiment includes a differential output type clock generation circuit 1a that generates a sine wave differential clock signal, a differential input/differential output type amplifier circuit 2a whose non-inverting input terminal is connected to the non-inverting output terminal of the clock generation circuit 1a and whose inverting input terminal is connected to the inverting output terminal of the clock generation circuit 1a, a differential input/differential output type amplifier circuit 3a whose non-inverting input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a and whose inverting input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a transmission line 4p whose input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a, a transmission line 4n whose input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a load circuit 5p
  • the transmission lines 4p, 4n are lines having the same length L and the same characteristic impedance Z0 .
  • the load circuits 5p, 5n are circuits having the same impedance ZT . However, as described later, the impedances ZT of the load circuits 5p, 5n may be adjusted to different values.
  • the amplifier circuits 2a and 3a may have the configuration shown in FIG. 4, which is a typical differential amplifier circuit.
  • NPN bipolar transistor Q3 It is composed of an NPN bipolar transistor Q3, a resistor R1 connected to the power supply voltage VCC at one end and the collector of transistor Q1 at the other end, a resistor R2 connected to the power supply voltage VCC at one end and the collector of transistor Q2 at the other end, a resistor R3 connected to the emitter of transistor Q1 at one end and the collector of transistor Q3 at the other end, a resistor R4 connected to the emitter of transistor Q2 at one end and the collector of transistor Q3 at the other end, and a resistor R5 connected to the emitter of transistor Q3 at one end and the ground at the other end.
  • amplifier circuit 3a is the same as that of amplifier circuit 2a.
  • the amplification degree of amplifier circuits 2a and 3a may be 1, may be higher than 1, or may be higher than 0 and lower than 1.
  • FIG. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a third embodiment of the present invention.
  • the phase adjustment circuit of this embodiment includes a clock generation circuit 1a, an amplifier circuit 2a, transmission lines 4p, 4n, load circuits 5p, 5n, a differential input/differential output type mixer 6 that mixes sum signals IN6p, IN6n of the output signal of the amplifier circuit 2a and the return signal from the transmission lines 4p, 4n, and carrier signals IN7p, IN7n input from the outside, and a differential input/differential output type filter 7 that filters the output signal of the mixer 6 and passes differential signals OUTp, OUTn of a desired frequency.
  • the frequency of the sum signals IN6p, IN6n is f1
  • the frequency of the carrier signals IN7p, IN7n is f2.
  • a signal having the sum and difference frequencies f1 ⁇ f2 is output from the mixer 6.
  • the filter 7 filters the output signal of the mixer 6, for example, to pass a signal of frequency f1+f2. In this way, the sum signals IN6p and IN6n input to the mixer 6 can be converted to signals OUTp and OUTn of higher frequencies and output.
  • the Gilbert cell circuit shown in Figure 6 can be used as the mixer 6 that functions as a multiplier.
  • the mixer 6 is made up of an NPN bipolar transistor Q4, which receives the negative-phase addition signal IN6n at its base and outputs the positive-phase output signal OUT6p of the mixer 6 from its collector, an NPN bipolar transistor Q5, which receives the positive-phase addition signal IN6p at its base and outputs the negative-phase output signal OUT6n of the mixer 6 from its collector, an NPN bipolar transistor Q6, which receives the addition signal IN6n at its base and outputs the output signal OUT6n from its collector, an NPN bipolar transistor Q7, which receives the addition signal IN6p at its base and outputs the output signal OUT6p from its collector, an NPN bipolar transistor Q8, which receives the positive-phase carrier signal IN7p at its base and has its collector connected to the emitters of the transistors Q4 and Q5, and an NPN bipolar transistor Q9, which receives the negative-phase carrier signal I N7n is
  • a differential circuit configuration is shown, but in a single-phase configuration as shown in FIG. 1, a single-phase input/single-phase output mixer and a single-phase input/single-phase output filter may be provided instead of the amplifier circuit 3.
  • [Fourth embodiment] 7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention.
  • the phase adjustment circuit of this embodiment includes a clock generation circuit 1a, a differential input/differential output type variable gain amplifier circuit 2b having a non-inverting input terminal connected to the non-inverting output terminal of the clock generation circuit 1a and an inverting input terminal connected to the inverting output terminal of the clock generation circuit 1a, a differential input/differential output type amplifier circuit 3a having a non-inverting input terminal connected to the non-inverting output terminal of the variable gain amplifier circuit 2b and an inverting input terminal connected to the inverting output terminal of the variable gain amplifier circuit 2b, transmission lines 4p, 4n, and load circuits 5p, 5n.
  • variable gain amplifier circuit 2b is provided instead of the amplifier circuit 2a in the second embodiment in order to adjust the amplitude of the differential signals OUTp and OUTn output from the amplifier circuit 3a.
  • the configuration of the variable gain amplifier circuit 2b is not important, but for example, the Gilbert cell circuit shown in FIG. 6 can be used.
  • variable gain amplifier circuit 2b When a Gilbert cell circuit is used as the variable gain amplifier circuit 2b, the positive phase gain control signal is input instead of IN6p in FIG. 6, the negative phase gain control signal is input instead of IN6n, the positive phase clock signal output from the clock generation circuit 1a is input instead of IN7p, and the negative phase clock signal output from the clock generation circuit 1a is input instead of IN7n.
  • the gain of the variable gain amplifier circuit 2b can be controlled by the voltage difference between the positive phase gain control signal and the negative phase gain control signal.
  • [Fifth Example] 8 is a block diagram showing the configuration of a phase adjustment circuit according to a fifth embodiment of the present invention.
  • the phase adjustment circuit of this embodiment includes a clock generation circuit 1a, a variable gain amplifier circuit 2b, an amplifier circuit 3a, transmission lines 4p and 4n, load circuits 5p and 5n, and an amplitude control circuit 8.
  • the amplitude control circuit 8 outputs a gain control signal to the variable gain amplifier circuit 2b so that the amplitudes of the output signals OUTp, OUTn of the amplifier circuit 3a are constant. In this way, by performing feedback control in which the amplitude of the output signals OUTp, OUTn is detected and the gain of the variable gain amplifier circuit 2b is adjusted, the amplitude of the output signals OUTp, OUTn can be made constant.
  • FIG. 9 is a block diagram showing the configuration of a phase adjustment circuit according to a sixth embodiment of the present invention.
  • the phase adjustment circuit of this embodiment includes a clock generation circuit 1a, amplifier circuits 2a and 3a, transmission lines 4p and 4n, load circuits 5p and 5n, and an impedance control circuit 9.
  • an impedance control circuit 9 is used to maintain the signal quality of the differential signal.
  • the impedance control circuit 9 evaluates the signal quality of the differential signals OUTp, OUTn output from the amplifier circuit 3a, and individually controls the impedance of each of the load circuits 5p, 5n based on the evaluation results.
  • FIG. 10 is a circuit diagram showing the configuration of a signal quality evaluation circuit 10 in the impedance control circuit 9.
  • the signal quality evaluation circuit 10 comprises an NPN bipolar transistor Q11, which receives the positive phase output signal OUTp output from the amplifier circuit 3a at its base and outputs the negative phase output signal OUT10n from its collector, an NPN bipolar transistor Q12, which receives the negative phase output signal OUTn output from the amplifier circuit 3a at its base and outputs the positive phase output signal OUT10p from its collector, an NPN bipolar transistor Q13, whose base is given a bias voltage Vb, and an NPN bipolar transistor Q14, which has one end connected to the power supply voltage VCC and the other end connected to the transistor 12.
  • resistor R11 connected to the collector of transistor Q11
  • resistor R12 having one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q12
  • resistor R13 having one end connected to the emitter of transistor Q11 and the other end connected to the collector of transistor Q13
  • resistor R14 having one end connected to the emitter of transistor Q12 and the other end connected to the collector of transistor Q13
  • resistor R15 having one end connected to the emitter of transistor Q13 and the other end connected to ground.
  • the difference between the output signals OUT10p, OUT10n of the signal quality evaluation circuit 10 is 0.
  • the impedance of the load circuits 5p, 5n so that the sum of the differential signals OUTp, OUTn is 0 (so that the difference between the output signals OUT10p, OUT10n is 0)
  • the quality of the differential signals OUTp, OUTn can be improved.
  • a processor or the like that performs digital signal processing is provided after the signal quality evaluation circuit 10 in the impedance control circuit 9, and the impedance of the load circuits 5p, 5n is controlled based on the output signals OUT10p, OUT10n of the signal quality evaluation circuit 10 so that the time average of the sum of the differential signals OUTp, OUTn becomes 0.
  • the signal quality evaluation circuit 10 is not limited to the configuration shown in FIG. 10, and may be realized by a passive multiplexing circuit.
  • the amplifier circuit 2a may be replaced by a variable gain amplifier circuit 2b, and in the fourth to sixth embodiments, the mixer 6 and filter 7 described in the third embodiment may be replaced by the amplifier circuit 3a.
  • the load circuits 5, 5p, and 5n in the first to sixth embodiments may be a circuit as shown in Fig. 11, which is made up of a capacitance for blocking DC components and a variable resistor.
  • One end of the capacitance C1 is connected to the end of the transmission line 4, 4p, or 4n, and the other end of the capacitance C1 is connected to one end of the variable resistor VR1.
  • the other end of the variable resistor VR1 is connected to ground.
  • variable resistor VR1 is composed of an NPN bipolar transistor Q14, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of capacitor C1, and a resistor R16, whose one end is connected to the emitter of transistor Q14 and whose other end is connected to ground.
  • variable resistor VR1 is composed of an NPN bipolar transistor Q15, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of capacitance C1, and an NPN bipolar transistor Q16, whose base receives a bias voltage Vb, whose collector is connected to the emitter of transistor Q15, and whose emitter is connected to ground.
  • the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl.
  • increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.
  • the load circuit 5 may be realized by a feedback configuration using a variable gain amplifier circuit as shown in FIG. 14.
  • the variable resistor VR1 is composed of a variable gain amplifier circuit A1 having a reference voltage VRef input to its non-inverting input terminal and an inverting input terminal connected to the other end of the capacitor C1, and a resistor R17 having one end connected to the output terminal of the variable gain amplifier circuit A1 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A1.
  • increasing the gain of the variable gain amplifier circuit A1 reduces the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A1 increases the impedance of the load circuit 5.
  • the gain of the variable gain amplifier circuit A1 can be changed by the control voltage Vctrl, thereby changing the impedance of the load circuit 5.
  • a Gilbert cell circuit can be used in the same manner as above.
  • the capacitance C1 is inserted to consider the bias point, but depending on the design, the capacitance C1 may not be inserted and the ends of the transmission lines 4, 4p, and 4n may be directly connected to the variable resistor VR1.
  • variable capacitance VC1 As the load circuits 5, 5p, and 5n in the first to sixth embodiments, it is also possible to use a variable capacitance VC1 as shown in FIG. 15. One end of the variable capacitance VC1 is connected to the end of the transmission line 4, 4p, and 4n, and the other end of the variable capacitance VC1 is connected to ground.
  • variable capacitance VC1 is composed of a capacitance C2, one end of which is connected to the end of the transmission lines 4, 4p, and 4n, a diode D1, the anode of which receives the control voltage Vctrl and the cathode of which is connected to the other end of the capacitance C2, and a resistor R18, one end of which is connected to the cathode of the diode D1 and the other end of which is connected to ground.
  • variable capacitance VC1 is composed of a capacitance C3, one end of which is connected to the end of the transmission lines 4, 4p, and 4n; a diode D2, whose anode receives a control voltage Vctrl and whose cathode is connected to the other end of the capacitance C3; and an NPN bipolar transistor Q17, whose base is supplied with a bias voltage Vb, whose collector is connected to the cathode of the diode D2, and whose emitter is connected to ground.
  • the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl.
  • increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.
  • variable capacitance VC1 may be realized by a feedback configuration using a variable gain amplifier circuit.
  • the variable capacitance VC1 is composed of a capacitance C4 having one end connected to the end of the transmission line 4, 4p, 4n, a variable gain amplifier circuit A2 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitance C4, and a capacitance C5 having one end connected to the output terminal of the variable gain amplifier circuit A2 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A2.
  • increasing the gain of the variable gain amplifier circuit A2 reduces the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A2 increases the impedance of the load circuit 5.
  • the impedance of the load circuit 5 can be changed by changing the gain of the variable gain amplifier circuit A2 using the control voltage Vctrl.
  • a Gilbert cell circuit can be used as the variable gain amplifier circuit A2.
  • the load circuits 5, 5p, and 5n in the first to sixth embodiments it is also possible to use a circuit that combines a variable resistor VR1 and a variable capacitor VC1 as shown in FIG. 19.
  • the configurations shown in FIGS. 20 to 22 can be used as the load circuits 5, 5p, and 5n.
  • the load circuit 5 is composed of a capacitor C1, one end of which is connected to the end of the transmission lines 4, 4p, and 4n; an NPN bipolar transistor Q15, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of the capacitor C1; an NPN bipolar transistor Q16, whose base receives a bias voltage Vb, whose collector is connected to the emitter of the transistor Q15, and whose emitter is connected to ground; and a diode D2, whose anode receives a control voltage Vctrlc, and whose cathode is connected to the other end of the capacitor C1.
  • the load circuit 5 is composed of a capacitor C1 having one end connected to the end of the transmission line 4, 4p, 4n, a variable gain amplifier circuit A1 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitor C1, a resistor R17 having one end connected to the output terminal of the variable gain amplifier circuit A1 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A1, a variable gain amplifier circuit A2 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitor C1, and a capacitor C5 having one end connected to the output terminal of the variable gain amplifier circuit A2 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A2.
  • variable inductor VL1 As the load circuits 5, 5p, 5n in the first to sixth embodiments, it is also possible to use a variable inductor VL1 as shown in FIG. 23. One end of the capacitance C1 is connected to the termination of the transmission line 4, 4p, 4n, and the other end of the capacitance C1 is connected to one end of the variable inductor VL1. The other end of the variable inductor VL1 is connected to ground.
  • the load circuits 5, 5p, 5n in the first to sixth embodiments it is also possible to use a circuit that combines a variable resistor VR1, a variable capacitance VC1, and a variable inductor VL1, as shown in FIG. 24. It is also possible to combine a variable resistor VR1 with a variable inductor VL1, or to combine a variable capacitance VC1 with a variable inductor VL1.
  • the configuration of the load circuit 5 is taken as an example for explanation, but the configuration of the load circuits 5p and 5n is also similar to that of the load circuit 5.
  • the impedance control circuit 9 when the load circuits 5p, 5n are combined with the impedance control circuit 9, if the sum of the differential signals OUTp, OUTn is positive, the impedance of the load circuit 5n is increased and the impedance of the load circuit 5p is decreased. Also, if the sum of the differential signals OUTp, OUTn is negative, the impedance of the load circuit 5p is increased and the impedance of the load circuit 5n is decreased.
  • FIG. 25 shows an example of a microstrip line.
  • the transmission line 4p is composed of a dielectric 400, a signal line 401 made of a conductor formed on the surface of the dielectric 400, and a ground plane 403 made of a conductor formed on the back surface of the dielectric 400.
  • the transmission line 4n is composed of a dielectric 400, a signal line 402 made of a conductor formed on the surface of the dielectric 400, and a ground plane 403.
  • the example in FIG. 26 shows an example of a coplanar line.
  • the transmission line 4p is composed of a dielectric 400, a signal line 401, and a ground plane 404 made of a conductor formed on the surface of the dielectric 400 on the side opposite the signal line 402, with the signal line 401 in between.
  • the transmission line 4n is composed of a dielectric 400, a signal line 402, and a ground plane 405 made of a conductor formed on the surface of the dielectric 400 on the side opposite the signal line 401, with the signal line 402 in between.
  • Transmission line 4p is composed of a dielectric 400, a signal line 401, and ground planes 403 and 404.
  • Transmission line 4n is composed of a dielectric 400, a signal line 402, and ground planes 403 and 405.
  • the configuration of the transmission lines 4p and 4n is taken as an example for explanation, but in the case of the transmission line 4, it is sufficient to provide only one of the signal lines 401 and 402.
  • the structures of the transmission lines 4, 4p, 4n are not limited to the cross-sectional structures shown in FIGS. 25 to 27, but may be other structures as long as the characteristic impedance can be defined.
  • bipolar transistors are used as transistors Q1 to Q17, but MOS transistors may also be used.
  • MOS transistors simply replace the base with the gate, the collector with the drain, and the emitter with the source in the above explanation.
  • the phase adjustment circuit of the present invention comprises a clock generation circuit configured to generate a sine wave clock signal, an amplifier circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line whose input end is connected to the output terminal of the amplifier circuit, a load circuit whose impedance can be adjusted externally and connected to the end of the transmission line, and an output circuit whose input is a signal obtained by adding the output signal of the amplifier circuit and a return signal from the transmission line at the output terminal of the amplifier circuit.
  • the load circuit is made of a variable resistor whose impedance can be adjusted externally.
  • the load circuit is made of a variable inductor whose impedance can be adjusted externally.
  • the load circuit is composed of a combination of at least two of a variable resistor, a variable capacitor, and a variable inductor whose impedance can be adjusted externally.
  • the clock generation circuit generates a sine wave differential clock signal
  • the amplifier circuit is a differential input/differential output type circuit that amplifies the differential clock signal
  • the transmission line is composed of a first transmission line whose input end is connected to the non-inverting output terminal of the amplifier circuit and a second transmission line whose input end is connected to the inverting output terminal of the amplifier circuit
  • the load circuit is composed of a first load circuit connected to the end of the first transmission line and capable of adjusting impedance from the outside, and a second load circuit connected to the end of the second transmission line and capable of adjusting impedance from the outside.
  • the output circuit is a differential input/differential output type circuit that receives as input a signal obtained by adding the positive-phase output signal of the amplifier circuit and the return signal from the first transmission line at the non-inverting output terminal of the amplifier circuit, and a signal obtained by adding the negative-phase output signal of the amplifier circuit and the return signal from the second transmission line at the inverting output terminal of the amplifier circuit, and further includes an impedance control circuit configured to control the impedances of the first and second load circuits so that the sum of the differential signals output from the output circuit is 0.
  • the output circuit is an amplifier circuit configured to amplify the signal added at the output terminal of the amplifier circuit.
  • the output circuit is composed of a mixer configured to mix the signal added at the output terminal of the amplifier circuit with an externally input carrier signal, and a filter configured to filter the output signal of the mixer and pass a signal of a desired frequency.
  • the present invention can be applied to technology for adjusting the phase of a sine wave.

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Abstract

This phase adjusting circuit comprises: a clock generation circuit (1) that generates a clock signal of a sinusoidal shape; an amplification circuit (2) that amplifies the clock signal; a transfer line (4) the input end of which is connected to the output terminal of the amplification circuit (2); a load circuit (5) which is connected to the terminal end of the transfer line (4) and the impedance of which can be externally adjusted; and an amplification circuit (3) that receives, as an input thereof, a signal obtained by adding, at the output terminal of the amplification circuit (2), the output signal of the amplification circuit (2) and a return signal from the transfer line (4).

Description

位相調整回路Phase Adjustment Circuit
　本発明は、正弦波の位相調整回路に関するものである。 The present invention relates to a sine wave phase adjustment circuit.
　現代において、正弦波は重要な役割を果たしている。通信において、搬送波の生成に正弦波を用いることもあれば、正弦波をクロックとして使用することもある。通信においては、搬送波として用いられるだけでなく、データを判定するタイミング基準としてもクロックが使用される。 In modern times, sine waves play an important role. In communications, sine waves are sometimes used to generate carrier waves, and sometimes as clocks. In communications, clocks are used not only as carrier waves, but also as a timing reference to determine data.
　こういったデータ判定のタイミング基準としてクロックを使用する場合、クロックの位相を調整し、適切なタイミングでデータ判定を行うことが必要である。適切なタイミングでデータ判定を行う方法として、クロック・データ・リカバリがある。クロック・データ・リカバリを実現する手段としては、位相比較器と位相調整回路を用いる構成が知られている。この構成では、何らかの手段で位相を比較し、その比較結果に基づき、所望する位相を生成する。 When using a clock as a timing reference for such data judgments, it is necessary to adjust the phase of the clock and make data judgments at the appropriate timing. One method for making data judgments at the appropriate timing is clock data recovery. A known means for achieving clock data recovery is a configuration that uses a phase comparator and a phase adjustment circuit. In this configuration, the phase is compared by some means, and the desired phase is generated based on the comparison results.
　従来、位相調整回路として、非特許文献１に開示された構成が知られていた。従来の位相調整回路の構成を図２８に示す。図２８の構成では、基準となる正弦波ｓｉｎωｔと、正弦波ｓｉｎωｔに対してπ／２の固定位相差を持つ正弦波ｃｏｓωｔとを加算器２０３によって加算することで、任意の中間位相の波形を生成する。正弦波ｓｉｎωｔ，ｃｏｓωｔには、それぞれ乗算器２０１，２０２によって定数Ａ，Ｂが乗算される。三角関数合成の式より、次式が成立する。 　Conventionally, the configuration disclosed in Non-Patent Document 1 has been known as a phase adjustment circuit. The configuration of a conventional phase adjustment circuit is shown in FIG. 28. In the configuration of FIG. 28, a reference sine wave sinωt and a sine wave cosωt having a fixed phase difference of π/2 with respect to the sine wave sinωt are added by adder 203 to generate a waveform of any intermediate phase. The sine waves sinωt and cosωt are multiplied by constants A and B by multipliers 201 and 202, respectively. The following equation is established from the trigonometric function synthesis equation.
Figure JPOXMLDOC01-appb-M000001
Figure JPOXMLDOC01-appb-M000001
　式（１）におけるαは以下のようになる。 In equation (1), α is as follows:
Figure JPOXMLDOC01-appb-M000002
Figure JPOXMLDOC01-appb-M000002
　図２８の構成では、Ｑｕａｄｒａｔｕｒｅ－ＶＣＯ（Voltage Controlled Oscillator）２００を用いることで、正弦波ｓｉｎωｔ，ｃｏｓωｔを生成している。しかしながら、Ｑｕａｄｒａｔｕｒｅ－ＶＣＯ２００は、構造上、発振周波数が低くなるため、デバイスの限界領域で用いることが難しい、という課題があった。また、正弦波からπ／２の固定位相差を持つ正弦波を作成する方法として、９０度ハイブリッドを使用する方法が知られているが、９０度ハイブリッドを使用する場合、特定の周波数においてしか動作しない、という課題があった。 In the configuration of Figure 28, sine waves sinωt and cosωt are generated by using a Quadrature-VCO (Voltage Controlled Oscillator) 200. However, due to its structure, the Quadrature-VCO 200 has a low oscillation frequency, which makes it difficult to use in the device's limit range. In addition, a method of using a 90-degree hybrid is known as a method of creating a sine wave with a fixed phase difference of π/2 from a sine wave, but when using a 90-degree hybrid, there is an issue that it only works at specific frequencies.
　本発明は、上記課題を解決するためになされたもので、幅広い周波数で利用が可能な位相調整回路を提供することを目的とする。 The present invention has been made to solve the above problems, and aims to provide a phase adjustment circuit that can be used over a wide range of frequencies.
　本発明の位相調整回路は、正弦波状のクロック信号を生成するように構成されたクロック生成回路と、前記クロック生成回路から出力されたクロック信号を増幅するように構成された増幅回路と、入力端が前記増幅回路の出力端子に接続された伝送線路と、前記伝送線路の終端に接続された、外部からインピーダンスの調整が可能な負荷回路と、前記増幅回路の出力信号と前記伝送線路からの戻り信号とが前記増幅回路の出力端子において加算された信号を入力とする出力回路とを備えることを特徴とするものである。 The phase adjustment circuit of the present invention is characterized by comprising a clock generation circuit configured to generate a sine wave clock signal, an amplifier circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line whose input end is connected to the output terminal of the amplifier circuit, a load circuit whose impedance can be adjusted externally and connected to the end of the transmission line, and an output circuit whose input is a signal obtained by adding the output signal of the amplifier circuit and the return signal from the transmission line at the output terminal of the amplifier circuit.
　本発明によれば、クロック生成回路と増幅回路と伝送線路と負荷回路と出力回路とを設けることにより、正弦波信号の基となるクロック生成回路として従来のようなＱｕａｄｒａｔｕｒｅ－ＶＣＯを使う必要がなくなり、クロック生成回路として一般的なＬＣ発振器からなるＬＣ－ＶＣＯを使用することができるので、中間位相のクロックを生成することができ、より高い周波数での動作を実現することができる。また、本発明では、クロック生成回路として９０度ハイブリッドを用いる構成に比べて、幅広い周波数で利用が可能となる。 According to the present invention, by providing a clock generation circuit, an amplifier circuit, a transmission line, a load circuit, and an output circuit, it is no longer necessary to use a quadrature-VCO as in the past as a clock generation circuit that is the basis of a sine wave signal, and an LC-VCO consisting of a general LC oscillator can be used as the clock generation circuit, making it possible to generate a clock with an intermediate phase and to achieve operation at a higher frequency. Furthermore, compared to a configuration that uses a 90-degree hybrid as the clock generation circuit, the present invention can be used at a wider range of frequencies.
図１は、本発明の第１の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. 図２は、本発明の第１の実施例に係る位相調整回路のシミュレーション結果を示す図である。FIG. 2 is a diagram showing a simulation result of the phase adjustment circuit according to the first embodiment of the present invention. 図３は、本発明の第２の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention. 図４は、本発明の第２の実施例に係る増幅回路の構成を示す回路図である。FIG. 4 is a circuit diagram showing the configuration of an amplifier circuit according to a second embodiment of the present invention. 図５は、本発明の第３の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a third embodiment of the present invention. 図６は、本発明の第３の実施例に係るミキサの構成を示す回路図である。FIG. 6 is a circuit diagram showing the configuration of a mixer according to a third embodiment of the present invention. 図７は、本発明の第４の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention. 図８は、本発明の第５の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 8 is a block diagram showing the configuration of a phase adjustment circuit according to a fifth embodiment of the present invention. 図９は、本発明の第６の実施例に係る位相調整回路の構成を示すブロック図である。FIG. 9 is a block diagram showing the configuration of a phase adjustment circuit according to a sixth embodiment of the present invention. 図１０は、本発明の第６の実施例に係る信号品質評価回路の構成を示す回路図である。FIG. 10 is a circuit diagram showing the configuration of a signal quality evaluation circuit according to a sixth embodiment of the present invention. 図１１は、本発明の第７の実施例に係る負荷回路の構成を示す回路図である。FIG. 11 is a circuit diagram showing the configuration of a load circuit according to a seventh embodiment of the present invention. 図１２は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 12 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１３は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 13 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１４は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 14 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１５は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 15 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１６は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 16 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１７は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 17 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１８は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 18 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図１９は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 19 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２０は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 20 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２１は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 21 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２２は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 22 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２３は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 23 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２４は、本発明の第７の実施例に係る負荷回路の別の構成を示す回路図である。FIG. 24 is a circuit diagram showing another configuration of the load circuit according to the seventh embodiment of the present invention. 図２５は、本発明の第８の実施例に係る伝送線路の構成を示す断面図である。FIG. 25 is a cross-sectional view showing the configuration of a transmission line according to an eighth embodiment of the present invention. 図２６は、本発明の第８の実施例に係る伝送線路の別の構成を示す断面図である。FIG. 26 is a cross-sectional view showing another configuration of a transmission line according to the eighth embodiment of the present invention. 図２７は、本発明の第８の実施例に係る伝送線路の別の構成を示す断面図である。FIG. 27 is a cross-sectional view showing another configuration of a transmission line according to the eighth embodiment of the present invention. 図２８は、従来の位相調整回路の構成を示すブロック図である。FIG. 28 is a block diagram showing a configuration of a conventional phase adjustment circuit.
［発明の原理］
　本発明では、クロックバッファに対して、インピーダンス可変な負荷を有する伝送線路を設けた回路構成により、正弦波を任意の位相に調整する機能を実現する。 [Principle of the Invention]
In the present invention, a function of adjusting a sine wave to an arbitrary phase is realized by a circuit configuration in which a transmission line having a variable impedance load is provided for a clock buffer.
［第１の実施例］
　以下、本発明の実施例について図面を参照して説明する。図１は本発明の第１の実施例に係る位相調整回路の構成を示すブロック図である。位相調整回路は、正弦波状のクロック信号を生成するクロック生成回路１と、クロック生成回路１から出力されたクロック信号を増幅する増幅回路２と、入力端子が増幅回路２の出力端子と接続された増幅回路３と、入力端が増幅回路２の出力端子に接続された伝送線路４と、伝送線路４の終端に接続された、外部からインピーダンスの調整が可能な負荷回路５とを備えている。 [First embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram showing the configuration of a phase adjustment circuit according to a first embodiment of the present invention. The phase adjustment circuit includes a clock generation circuit 1 that generates a sine wave clock signal, an amplifier circuit 2 that amplifies the clock signal output from the clock generation circuit 1, an amplifier circuit 3 whose input terminal is connected to the output terminal of the amplifier circuit 2, a transmission line 4 whose input end is connected to the output terminal of the amplifier circuit 2, and a load circuit 5 connected to the end of the transmission line 4 and capable of adjusting the impedance from outside.
　図１の構成では、クロック生成回路１から出力された正弦波状のクロック信号は、増幅回路２を通過して、増幅回路３と伝送線路４とに入力される。伝送線路４のインピーダンスと負荷回路５のインピーダンスとが異なるため、伝送線路４に入力された信号は、伝送線路４の終端で反射され、増幅回路２の出力に戻る。このため、増幅回路２から出力された信号と、伝送線路４を往復することによって遅延された信号とが増幅回路２の出力端子において加算されることとなる。 In the configuration of FIG. 1, the sinusoidal clock signal output from the clock generation circuit 1 passes through the amplifier circuit 2 and is input to the amplifier circuit 3 and the transmission line 4. Because the impedance of the transmission line 4 differs from the impedance of the load circuit 5, the signal input to the transmission line 4 is reflected at the end of the transmission line 4 and returns to the output of the amplifier circuit 2. As a result, the signal output from the amplifier circuit 2 and the signal delayed by traveling back and forth on the transmission line 4 are added together at the output terminal of the amplifier circuit 2.
　増幅回路２，３としては、増幅度が１のバッファ回路を用いてもよいし、増幅度が１より高い増幅回路を用いてもよいし、増幅度が０より高く１より低い増幅回路を用いてもよい。
　本実施例では、増幅回路２の出力信号と伝送線路４からの戻り信号とが増幅回路２の出力端子において加算された信号を入力とする出力回路として、増幅回路３を用いているが、後述のように出力回路は、増幅回路でなくてもよく、ミキサとフィルタを組み合わせた回路でもよい。 As the amplifier circuits 2 and 3, a buffer circuit with an amplification factor of 1, an amplifier circuit with an amplification factor higher than 1, or an amplifier circuit with an amplification factor higher than 0 and lower than 1 may be used.
In this embodiment, the amplifier circuit 3 is used as an output circuit that receives as input a signal obtained by adding the output signal of the amplifier circuit 2 and the return signal from the transmission line 4 at the output terminal of the amplifier circuit 2. However, as described later, the output circuit does not have to be an amplifier circuit, and may be a circuit that combines a mixer and a filter.
　位相調整回路の動作を数式を用いて説明する。増幅回路２から伝送線路４に入力された信号をＡｓｉｎωｔとし、伝送線路４から反射して戻ってきた信号をＢｓｉｎ（ωｔ＋φ）とすると、最終的に増幅回路３の出力信号ＯＵＴは、次式のようになる。 The operation of the phase adjustment circuit will be explained using a formula. If the signal input from the amplifier circuit 2 to the transmission line 4 is A sinωt, and the signal reflected back from the transmission line 4 is B sin(ωt + φ), then the final output signal OUT of the amplifier circuit 3 will be expressed by the following formula.
Figure JPOXMLDOC01-appb-M000003
Figure JPOXMLDOC01-appb-M000003
　式（３）では増幅回路３の増幅度を１としている。ｅｊωｔは基準となる正弦波を示す。Ｂｓｉｎ（ωｔ＋φ）は、伝送線路４から戻ってきた反射波なので、増幅されておらず、Ｂ＜Ａである。Ｂとφの値は、負荷回路５のインピーダンスと伝送線路４の長さとに依存する。 In equation (3), the amplification degree of the amplifier circuit 3 is set to 1. e jωt indicates a reference sine wave. B sin(ωt + φ) is a reflected wave returning from the transmission line 4, so it is not amplified and B < A. The values of B and φ depend on the impedance of the load circuit 5 and the length of the transmission line 4.
　式（３）より、基準周波数の正弦波と、任意位相φだけ異なる正弦波とを加算することにより、基準位相の正弦波からρだけ位相の異なる正弦波を生成できることが分かる。出力位相の変化量はｒｅｊρを計算すれば良いため、式（３）を整理すると、式（４）のようになる。 From equation (3), it can be seen that by adding a sine wave of a reference frequency and a sine wave differing by an arbitrary phase φ, a sine wave with a phase difference of ρ from the sine wave of the reference phase can be generated. Since the amount of change in the output phase can be calculated by re jρ , equation (3) can be rearranged to obtain equation (4).
Figure JPOXMLDOC01-appb-M000004
Figure JPOXMLDOC01-appb-M000004
　よって、位相角ρは式（５）で与えられる。 Then, the phase angle ρ is given by equation (5).
Figure JPOXMLDOC01-appb-M000005
　　　　　　　　　　　　　　　　　　　　　　　　　・・・（５）
Figure JPOXMLDOC01-appb-M000005
...(5)
　なお、ここでは多重反射の影響を無視したが、多重反射がある場合であっても、同様の議論により、中間位相の正弦波の生成可能性が説明できる。図１の例では、単相の構成を示しているが、差動構成の回路で実現することも可能である。 Note that the effects of multiple reflections have been ignored here, but even when multiple reflections are present, a similar argument can be used to explain the possibility of generating a sine wave with an intermediate phase. The example in Figure 1 shows a single-phase configuration, but it can also be realized with a differential circuit.
　次に、位相調整回路の実際の動作について更に詳細に説明する。増幅回路２の出力インピーダンスをｒｏ、伝送線路４の特性インピーダンスをＺ０、負荷回路５のインピーダンスをＺＴとする。伝送線路４の入力から見た伝送線路４と負荷回路５のインピーダンスＺｉｎは式（６）のようになる。 Next, the actual operation of the phase adjustment circuit will be described in more detail. The output impedance of the amplifier circuit 2 is r o , the characteristic impedance of the transmission line 4 is Z 0 , and the impedance of the load circuit 5 is Z T. The impedance Z in of the transmission line 4 and the load circuit 5 as viewed from the input of the transmission line 4 is given by equation (6).
Figure JPOXMLDOC01-appb-M000006
Figure JPOXMLDOC01-appb-M000006
　Ｂは位相定数、Ｌは伝送線路４の長さである。Ｂ×Ｌは、物理的な構造と信号の周波数とによって決まるので、ある特定の周波数に着目する場合、ｔａｎＢＬは定数とみなしてよい。増幅回路２の出力端子におけるインピーダンスＺｏｕｔは、Ｚｉｎとｒｏの合成抵抗であり、式（７）のように示すことができる。 B is the phase constant, and L is the length of the transmission line 4. Since B×L is determined by the physical structure and the frequency of the signal, when focusing on a specific frequency, tanBL may be regarded as a constant. The impedance Z out at the output terminal of the amplifier circuit 2 is the combined resistance of Z in and r o , and can be expressed as in equation (7).
Figure JPOXMLDOC01-appb-M000007
Figure JPOXMLDOC01-appb-M000007
　一般に、増幅回路の出力電圧は、トランスコンダクタンスと出力端子のインピーダンスとの積で表現される。したがって、増幅回路２のトランスコンダクタンスをｇｍａとおけば、増幅回路２の出力電圧Ｖｏｕｔは式（８）のように表すことができる。
　Ｖｏｕｔ＝ｇｍａ×Ｚｏｕｔ　　　　　　　　　　　　　　・・・（８） In general, the output voltage of an amplifier circuit is expressed as the product of the transconductance and the impedance of the output terminal. Therefore, if the transconductance of the amplifier circuit 2 is gma, the output voltage Vout of the amplifier circuit 2 can be expressed as shown in equation (8).
V out = gma × Z out (8)
　式（７）より、負荷回路５のインピーダンスＺＴを変化させることで、インピーダンスＺｏｕｔの偏角が変化することが分かる。つまり、インピーダンスＺＴを変化させることで、位相調整回路の出力の位相を調整することができる。ただし、信号周波数と伝送線路４の長さの組み合わせのうち、ｔａｎＢＬ＝０が成立する組み合わせを除く必要がある。 From equation (7), it can be seen that the argument of the impedance Zout changes by changing the impedance ZT of the load circuit 5. In other words, the phase of the output of the phase adjustment circuit can be adjusted by changing the impedance ZT . However, among the combinations of the signal frequency and the length of the transmission line 4, it is necessary to exclude combinations where tanBL=0 holds.
　本実施例の位相調整回路によって正弦波の位相が変化することを回路シミュレーションによって確認した結果を図２に示す。２０はクロック生成回路１から出力される正弦波を示し、２１は本実施例の位相調整回路によって位相を変化させた正弦波を示す。正弦波の周波数は６０ＧＨｚである。負荷回路５のインピーダンスＺＴを変化させることにより、時間にして凡そ３ｐｓ分、正弦波の位相が変化していることが確認できる。 2 shows the results of confirming by circuit simulation that the phase of a sine wave is changed by the phase adjustment circuit of this embodiment. Reference numeral 20 denotes a sine wave output from the clock generation circuit 1, and reference numeral 21 denotes a sine wave whose phase has been changed by the phase adjustment circuit of this embodiment. The frequency of the sine wave is 60 GHz. It can be confirmed that by changing the impedance ZT of the load circuit 5, the phase of the sine wave changes by approximately 3 ps in time.
　なお、上記の数値解析のとおり、インピーダンスＺＴの範囲は実数に留まらず、複素数としてもよい。また、伝送線路４の多重反射を防ぐために、伝送線路４の特性インピーダンスＺ０と増幅回路２の出力インピーダンスｒｏとを一致させてもよい。 As shown in the above numerical analysis, the range of the impedance ZT is not limited to real numbers, but may be complex numbers. In order to prevent multiple reflections in the transmission line 4, the characteristic impedance Z0 of the transmission line 4 and the output impedance r0 of the amplifier circuit 2 may be made to match each other.
［第２の実施例］
　図３は本発明の第２の実施例に係る位相調整回路の構成を示すブロック図である。本実施例の位相調整回路は、正弦波状の差動クロック信号を生成する差動出力型のクロック生成回路１ａと、非反転入力端子がクロック生成回路１ａの非反転出力端子と接続され、反転入力端子がクロック生成回路１ａの反転出力端子と接続された差動入力差動出力型の増幅回路２ａと、非反転入力端子が増幅回路２ａの非反転出力端子と接続され、反転入力端子が増幅回路２ａの反転出力端子と接続された差動入力差動出力型の増幅回路３ａと、入力端が増幅回路２ａの非反転出力端子に接続された伝送線路４ｐと、入力端が増幅回路２ａの反転出力端子に接続された伝送線路４ｎと、伝送線路４ｐの終端に接続された、外部からインピーダンスの調整が可能な負荷回路５ｐと、伝送線路４ｎの終端に接続された、外部からインピーダンスの調整が可能な負荷回路５ｎとを備えている。 [Second embodiment]
3 is a block diagram showing the configuration of a phase adjustment circuit according to a second embodiment of the present invention. The phase adjustment circuit of this embodiment includes a differential output type clock generation circuit 1a that generates a sine wave differential clock signal, a differential input/differential output type amplifier circuit 2a whose non-inverting input terminal is connected to the non-inverting output terminal of the clock generation circuit 1a and whose inverting input terminal is connected to the inverting output terminal of the clock generation circuit 1a, a differential input/differential output type amplifier circuit 3a whose non-inverting input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a and whose inverting input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a transmission line 4p whose input terminal is connected to the non-inverting output terminal of the amplifier circuit 2a, a transmission line 4n whose input terminal is connected to the inverting output terminal of the amplifier circuit 2a, a load circuit 5p whose impedance can be adjusted from the outside and connected to the end of the transmission line 4p, and a load circuit 5n whose impedance can be adjusted from the outside and connected to the end of the transmission line 4n.
　伝送線路４ｐ，４ｎは、長さＬが同一であり、また特性インピーダンスＺ０が同一の線路である。負荷回路５ｐ，５ｎは、インピーダンスＺＴが同一の回路である。ただし、後述のように、負荷回路５ｐ，５ｎのインピーダンスＺＴを異なる値に調整してもよい。
　増幅回路２ａ，３ａとしては、典型的な差動増幅回路である図４の構成を用いることができる。 The transmission lines 4p, 4n are lines having the same length L and the same characteristic impedance Z0 . The load circuits 5p, 5n are circuits having the same impedance ZT . However, as described later, the impedances ZT of the load circuits 5p, 5n may be adjusted to different values.
The amplifier circuits 2a and 3a may have the configuration shown in FIG. 4, which is a typical differential amplifier circuit.
　増幅回路２ａは、クロック生成回路１ａから出力された逆相側のクロック信号ＩＮ２ｎがベース（増幅回路２ａの反転入力端子）に入力され、コレクタ（増幅回路２ａの非反転出力端子）から正相側の出力信号ＯＵＴ２ｐを出力するＮＰＮバイポーラトランジスタＱ１と、クロック生成回路１ａから出力された正相側のクロック信号ＩＮ２ｐがベース（増幅回路２ａの非反転入力端子）に入力され、コレクタ（増幅回路２ａの反転出力端子）から逆相側の出力信号ＯＵＴ２ｎを出力するＮＰＮバイポーラトランジスタＱ２と、ベースにバイアス電圧Ｖｂが与えられたＮＰＮバイポーラトランジスタＱ３と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ１のコレクタに接続された抵抗Ｒ１と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ２のコレクタに接続された抵抗Ｒ２と、一端がトランジスタＱ１のエミッタに接続され、他端がトランジスタＱ３のコレクタに接続された抵抗Ｒ３と、一端がトランジスタＱ２のエミッタに接続され、他端がトランジスタＱ３のコレクタに接続された抵抗Ｒ４と、一端がトランジスタＱ３のエミッタに接続され、他端がグラウンドに接続された抵抗Ｒ５とから構成される。 The amplifier circuit 2a is an NPN bipolar transistor Q1 that receives the negative phase clock signal IN2n output from the clock generation circuit 1a at its base (the inverting input terminal of the amplifier circuit 2a) and outputs the positive phase output signal OUT2p from its collector (the non-inverting output terminal of the amplifier circuit 2a), an NPN bipolar transistor Q2 that receives the positive phase clock signal IN2p output from the clock generation circuit 1a at its base (the non-inverting input terminal of the amplifier circuit 2a) and outputs the negative phase output signal OUT2n from its collector (the inverting output terminal of the amplifier circuit 2a), and a bias voltage Vb is applied to the base. It is composed of an NPN bipolar transistor Q3, a resistor R1 connected to the power supply voltage VCC at one end and the collector of transistor Q1 at the other end, a resistor R2 connected to the power supply voltage VCC at one end and the collector of transistor Q2 at the other end, a resistor R3 connected to the emitter of transistor Q1 at one end and the collector of transistor Q3 at the other end, a resistor R4 connected to the emitter of transistor Q2 at one end and the collector of transistor Q3 at the other end, and a resistor R5 connected to the emitter of transistor Q3 at one end and the ground at the other end.
　増幅回路３ａの構成は増幅回路２ａと同様である。第１の実施例と同様に、増幅回路２ａ，３ａの増幅度は１でもよいし、１より高くてもよいし、０より高く１より低くてもよい。 The configuration of amplifier circuit 3a is the same as that of amplifier circuit 2a. As in the first embodiment, the amplification degree of amplifier circuits 2a and 3a may be 1, may be higher than 1, or may be higher than 0 and lower than 1.
［第３の実施例］
　第１、第２の実施例において、２段目の増幅回路の代わりに任意のアクティブ回路を用いてもよい。図５は本発明の第３の実施例に係る位相調整回路の構成を示すブロック図である。本実施例の位相調整回路は、クロック生成回路１ａと、増幅回路２ａと、伝送線路４ｐ，４ｎと、負荷回路５ｐ，５ｎと、増幅回路２ａの出力信号と伝送線路４ｐ，４ｎからの戻り信号との加算信号ＩＮ６ｐ，ＩＮ６ｎと、外部から入力された搬送波信号ＩＮ７ｐ，ＩＮ７ｎとを混合する差動入力差動出力型のミキサ６と、ミキサ６の出力信号をろ波して、所望の周波数の差動信号ＯＵＴｐ，ＯＵＴｎを通過させる差動入力差動出力型のフィルタ７とを備えている。 [Third Example]
In the first and second embodiments, an arbitrary active circuit may be used instead of the second stage amplifier circuit. Fig. 5 is a block diagram showing the configuration of a phase adjustment circuit according to a third embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, an amplifier circuit 2a, transmission lines 4p, 4n, load circuits 5p, 5n, a differential input/differential output type mixer 6 that mixes sum signals IN6p, IN6n of the output signal of the amplifier circuit 2a and the return signal from the transmission lines 4p, 4n, and carrier signals IN7p, IN7n input from the outside, and a differential input/differential output type filter 7 that filters the output signal of the mixer 6 and passes differential signals OUTp, OUTn of a desired frequency.
　加算信号ＩＮ６ｐ，ＩＮ６ｎの周波数をｆ１、搬送波信号ＩＮ７ｐ，ＩＮ７ｎの周波数をｆ２とする。加算信号ＩＮ６ｐ，ＩＮ６ｎと搬送波信号ＩＮ７ｐ，ＩＮ７ｎとをミキサ６によって混合すると、和と差の周波数ｆ１±ｆ２の信号がミキサ６から出力される。
　フィルタ７は、ミキサ６の出力信号をろ波して、例えば周波数ｆ１＋ｆ２の信号を通過させる。こうして、ミキサ６に入力される加算信号ＩＮ６ｐ，ＩＮ６ｎをさらに高い周波数の信号ＯＵＴｐ，ＯＵＴｎに変換して出力することができる。 The frequency of the sum signals IN6p, IN6n is f1, and the frequency of the carrier signals IN7p, IN7n is f2. When the sum signals IN6p, IN6n and the carrier signals IN7p, IN7n are mixed by the mixer 6, a signal having the sum and difference frequencies f1±f2 is output from the mixer 6.
The filter 7 filters the output signal of the mixer 6, for example, to pass a signal of frequency f1+f2. In this way, the sum signals IN6p and IN6n input to the mixer 6 can be converted to signals OUTp and OUTn of higher frequencies and output.
　乗算器として機能するミキサ６としては、図６に示すギルバートセル回路を用いることができる。ミキサ６は、ベースに逆相側の加算信号ＩＮ６ｎが入力され、コレクタからミキサ６の正相側の出力信号ＯＵＴ６ｐを出力するＮＰＮバイポーラトランジスタＱ４と、ベースに正相側の加算信号ＩＮ６ｐが入力され、コレクタからミキサ６の逆相側の出力信号ＯＵＴ６ｎを出力するＮＰＮバイポーラトランジスタＱ５と、ベースに加算信号ＩＮ６ｎが入力され、コレクタから出力信号ＯＵＴ６ｎを出力するＮＰＮバイポーラトランジスタＱ６と、ベースに加算信号ＩＮ６ｐが入力され、コレクタから出力信号ＯＵＴ６ｐを出力するＮＰＮバイポーラトランジスタＱ７と、ベースに正相側の搬送波信号ＩＮ７ｐが入力され、コレクタがトランジスタＱ４，Ｑ５のエミッタに接続されたＮＰＮバイポーラトランジスタＱ８と、ベースに逆相側の搬送波信号ＩＮ７ｎが入力され、コレクタがトランジスタＱ６，Ｑ７のエミッタに接続されたＮＰＮバイポーラトランジスタＱ９と、ベースにバイアス電圧ＶＢが与えられたＮＰＮバイポーラトランジスタＱ１０と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ４，Ｑ７のコレクタに接続された抵抗Ｒ６と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ５，Ｑ６のコレクタに接続された抵抗Ｒ７と、一端がトランジスタＱ８のエミッタに接続され、他端がトランジスタＱ１０のコレクタに接続された抵抗Ｒ８と、一端がトランジスタＱ９のエミッタに接続され、他端がトランジスタＱ１０のコレクタに接続された抵抗Ｒ９と、一端がトランジスタＱ１０のエミッタに接続され、他端がグラウンドに接続された抵抗Ｒ１０とから構成される。 The Gilbert cell circuit shown in Figure 6 can be used as the mixer 6 that functions as a multiplier. The mixer 6 is made up of an NPN bipolar transistor Q4, which receives the negative-phase addition signal IN6n at its base and outputs the positive-phase output signal OUT6p of the mixer 6 from its collector, an NPN bipolar transistor Q5, which receives the positive-phase addition signal IN6p at its base and outputs the negative-phase output signal OUT6n of the mixer 6 from its collector, an NPN bipolar transistor Q6, which receives the addition signal IN6n at its base and outputs the output signal OUT6n from its collector, an NPN bipolar transistor Q7, which receives the addition signal IN6p at its base and outputs the output signal OUT6p from its collector, an NPN bipolar transistor Q8, which receives the positive-phase carrier signal IN7p at its base and has its collector connected to the emitters of the transistors Q4 and Q5, and an NPN bipolar transistor Q9, which receives the negative-phase carrier signal I N7n is input, and the collector of the NPN bipolar transistor Q9 is connected to the emitters of the transistors Q6 and Q7; the base of the NPN bipolar transistor Q10 is given a bias voltage VB; one end of the resistor R6 is connected to the power supply voltage VCC and the other end is connected to the collectors of the transistors Q4 and Q7; one end of the resistor R7 is connected to the power supply voltage VCC and the other end is connected to the collectors of the transistors Q5 and Q6; one end of the resistor R8 is connected to the emitter of the transistor Q8 and the other end is connected to the collector of the transistor Q10; one end of the resistor R9 is connected to the emitter of the transistor Q9 and the other end is connected to the collector of the transistor Q10; and one end of the resistor R10 is connected to the emitter of the transistor Q10 and the other end is connected to the ground.
　図５の例では、差動構成の回路を示しているが、図１に示したような単相の構成において、増幅回路３の代わりに単相入力単相出力型のミキサと単相入力単相出力型のフィルタとを設けるようにしてもよい。 In the example of FIG. 5, a differential circuit configuration is shown, but in a single-phase configuration as shown in FIG. 1, a single-phase input/single-phase output mixer and a single-phase input/single-phase output filter may be provided instead of the amplifier circuit 3.
［第４の実施例］
　図７は本発明の第４の実施例に係る位相調整回路の構成を示すブロック図である。本実施例の位相調整回路は、クロック生成回路１ａと、非反転入力端子がクロック生成回路１ａの非反転出力端子と接続され、反転入力端子がクロック生成回路１ａの反転出力端子と接続された差動入力差動出力型の可変利得増幅回路２ｂと、非反転入力端子が可変利得増幅回路２ｂの非反転出力端子と接続され、反転入力端子が可変利得増幅回路２ｂの反転出力端子と接続された差動入力差動出力型の増幅回路３ａと、伝送線路４ｐ，４ｎと、負荷回路５ｐ，５ｎとを備えている。 [Fourth embodiment]
7 is a block diagram showing the configuration of a phase adjustment circuit according to a fourth embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, a differential input/differential output type variable gain amplifier circuit 2b having a non-inverting input terminal connected to the non-inverting output terminal of the clock generation circuit 1a and an inverting input terminal connected to the inverting output terminal of the clock generation circuit 1a, a differential input/differential output type amplifier circuit 3a having a non-inverting input terminal connected to the non-inverting output terminal of the variable gain amplifier circuit 2b and an inverting input terminal connected to the inverting output terminal of the variable gain amplifier circuit 2b, transmission lines 4p, 4n, and load circuits 5p, 5n.
　本実施例では、増幅回路３ａから出力される差動信号ＯＵＴｐ，ＯＵＴｎの振幅調整を行うために、第２の実施例の増幅回路２ａの代わりに可変利得増幅回路２ｂを設けている。可変利得増幅回路２ｂの構成は問わないが、例えば図６に示したギルバートセル回路を用いることもできる。 In this embodiment, a variable gain amplifier circuit 2b is provided instead of the amplifier circuit 2a in the second embodiment in order to adjust the amplitude of the differential signals OUTp and OUTn output from the amplifier circuit 3a. The configuration of the variable gain amplifier circuit 2b is not important, but for example, the Gilbert cell circuit shown in FIG. 6 can be used.
　可変利得増幅回路２ｂとしてギルバートセル回路を用いる場合、図６のＩＮ６ｐの代わりに正相側の利得制御信号を入力し、ＩＮ６ｎの代わりに逆相側の利得制御信号を入力し、ＩＮ７ｐの代わりにクロック生成回路１ａから出力された正相側のクロック信号を入力し、ＩＮ７ｎの代わりにクロック生成回路１ａから出力された逆相側のクロック信号を入力すればよい。正相側の利得制御信号と逆相側の利得制御信号の電圧差によって可変利得増幅回路２ｂの利得を制御することができる。 When a Gilbert cell circuit is used as the variable gain amplifier circuit 2b, the positive phase gain control signal is input instead of IN6p in FIG. 6, the negative phase gain control signal is input instead of IN6n, the positive phase clock signal output from the clock generation circuit 1a is input instead of IN7p, and the negative phase clock signal output from the clock generation circuit 1a is input instead of IN7n. The gain of the variable gain amplifier circuit 2b can be controlled by the voltage difference between the positive phase gain control signal and the negative phase gain control signal.
［第５の実施例］
　図８は本発明の第５の実施例に係る位相調整回路の構成を示すブロック図である。本実施例の位相調整回路は、クロック生成回路１ａと、可変利得増幅回路２ｂと、増幅回路３ａと、伝送線路４ｐ，４ｎと、負荷回路５ｐ，５ｎと、振幅制御回路８とを備えている。 [Fifth Example]
8 is a block diagram showing the configuration of a phase adjustment circuit according to a fifth embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, a variable gain amplifier circuit 2b, an amplifier circuit 3a, transmission lines 4p and 4n, load circuits 5p and 5n, and an amplitude control circuit 8.
　振幅制御回路８は、増幅回路３ａの出力信号ＯＵＴｐ，ＯＵＴｎの振幅が一定になるように可変利得増幅回路２ｂに対して利得制御信号を出力する。
　こうして、出力信号ＯＵＴｐ，ＯＵＴｎの振幅を検出して可変利得増幅回路２ｂの利得を調整するフィードバック制御を行うことにより、出力信号ＯＵＴｐ，ＯＵＴｎの振幅を一定にすることができる。 The amplitude control circuit 8 outputs a gain control signal to the variable gain amplifier circuit 2b so that the amplitudes of the output signals OUTp, OUTn of the amplifier circuit 3a are constant.
In this way, by performing feedback control in which the amplitude of the output signals OUTp, OUTn is detected and the gain of the variable gain amplifier circuit 2b is adjusted, the amplitude of the output signals OUTp, OUTn can be made constant.
［第６の実施例］
　図９は本発明の第６の実施例に係る位相調整回路の構成を示すブロック図である。本実施例の位相調整回路は、クロック生成回路１ａと、増幅回路２ａ，３ａと、伝送線路４ｐ，４ｎと、負荷回路５ｐ，５ｎと、インピーダンス制御回路９とを備えている。 [Sixth Example]
9 is a block diagram showing the configuration of a phase adjustment circuit according to a sixth embodiment of the present invention. The phase adjustment circuit of this embodiment includes a clock generation circuit 1a, amplifier circuits 2a and 3a, transmission lines 4p and 4n, load circuits 5p and 5n, and an impedance control circuit 9.
　差動構成の伝送線路４ｐ，４ｎにおいては、差動信号の品質が問題となる。本実施例では、差動信号の信号品質を維持するために、インピーダンス制御回路９を用いる。インピーダンス制御回路９は、増幅回路３ａから出力された差動信号ＯＵＴｐ，ＯＵＴｎの信号品質を評価し、評価結果に基づいて負荷回路５ｐ，５ｎのそれぞれのインピーダンスを個別に制御する。 In the differential transmission lines 4p, 4n, the quality of the differential signal becomes an issue. In this embodiment, an impedance control circuit 9 is used to maintain the signal quality of the differential signal. The impedance control circuit 9 evaluates the signal quality of the differential signals OUTp, OUTn output from the amplifier circuit 3a, and individually controls the impedance of each of the load circuits 5p, 5n based on the evaluation results.
　信号品質は、正相側の出力信号ＯＵＴｐと逆相側の出力信号ＯＵＴｎの和が０であることに着目することで評価できる。図１０はインピーダンス制御回路９内の信号品質評価回路１０の構成を示す回路図である。信号品質評価回路１０は、増幅回路３ａから出力された正相側の出力信号ＯＵＴｐがベースに入力され、コレクタから逆相側の出力信号ＯＵＴ１０ｎを出力するＮＰＮバイポーラトランジスタＱ１１と、増幅回路３ａから出力された逆相側の出力信号ＯＵＴｎがベースに入力され、コレクタから正相側の出力信号ＯＵＴ１０ｐを出力するＮＰＮバイポーラトランジスタＱ１２と、ベースにバイアス電圧Ｖｂが与えられたＮＰＮバイポーラトランジスタＱ１３と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ１１のコレクタに接続された抵抗Ｒ１１と、一端が電源電圧ＶＣＣに接続され、他端がトランジスタＱ１２のコレクタに接続された抵抗Ｒ１２と、一端がトランジスタＱ１１のエミッタに接続され、他端がトランジスタＱ１３のコレクタに接続された抵抗Ｒ１３と、一端がトランジスタＱ１２のエミッタに接続され、他端がトランジスタＱ１３のコレクタに接続された抵抗Ｒ１４と、一端がトランジスタＱ１３のエミッタに接続され、他端がグラウンドに接続された抵抗Ｒ１５とから構成される。 The signal quality can be evaluated by noting that the sum of the positive phase output signal OUTp and the negative phase output signal OUTn is 0. FIG. 10 is a circuit diagram showing the configuration of a signal quality evaluation circuit 10 in the impedance control circuit 9. The signal quality evaluation circuit 10 comprises an NPN bipolar transistor Q11, which receives the positive phase output signal OUTp output from the amplifier circuit 3a at its base and outputs the negative phase output signal OUT10n from its collector, an NPN bipolar transistor Q12, which receives the negative phase output signal OUTn output from the amplifier circuit 3a at its base and outputs the positive phase output signal OUT10p from its collector, an NPN bipolar transistor Q13, whose base is given a bias voltage Vb, and an NPN bipolar transistor Q14, which has one end connected to the power supply voltage VCC and the other end connected to the transistor 12. It is composed of a resistor R11 connected to the collector of transistor Q11, a resistor R12 having one end connected to the power supply voltage VCC and the other end connected to the collector of transistor Q12, a resistor R13 having one end connected to the emitter of transistor Q11 and the other end connected to the collector of transistor Q13, a resistor R14 having one end connected to the emitter of transistor Q12 and the other end connected to the collector of transistor Q13, and a resistor R15 having one end connected to the emitter of transistor Q13 and the other end connected to ground.
　差動信号ＯＵＴｐ，ＯＵＴｎの和が０の場合、信号品質評価回路１０の出力信号ＯＵＴ１０ｐ，ＯＵＴ１０ｎの差が０となる。差動信号ＯＵＴｐ，ＯＵＴｎの和が０となるように（出力信号ＯＵＴ１０ｐ，ＯＵＴ１０ｎの差が０となるように）、負荷回路５ｐ，５ｎのインピーダンスを制御することで、差動信号ＯＵＴｐ，ＯＵＴｎの品質を高めることができる。 When the sum of the differential signals OUTp, OUTn is 0, the difference between the output signals OUT10p, OUT10n of the signal quality evaluation circuit 10 is 0. By controlling the impedance of the load circuits 5p, 5n so that the sum of the differential signals OUTp, OUTn is 0 (so that the difference between the output signals OUT10p, OUT10n is 0), the quality of the differential signals OUTp, OUTn can be improved.
　差動信号ＯＵＴｐ，ＯＵＴｎの和が時間によって変化するため、インピーダンス制御回路９内において信号品質評価回路１０の後段に、デジタル信号処理を行うプロセッサ等を設け、信号品質評価回路１０の出力信号ＯＵＴ１０ｐ，ＯＵＴ１０ｎに基づいて、差動信号ＯＵＴｐ，ＯＵＴｎの和の時間平均が０となるように、負荷回路５ｐ，５ｎのインピーダンスを制御すればよい。 Since the sum of the differential signals OUTp, OUTn changes over time, a processor or the like that performs digital signal processing is provided after the signal quality evaluation circuit 10 in the impedance control circuit 9, and the impedance of the load circuits 5p, 5n is controlled based on the output signals OUT10p, OUT10n of the signal quality evaluation circuit 10 so that the time average of the sum of the differential signals OUTp, OUTn becomes 0.
　信号品質評価回路１０は、図１０に示した構成に限るものではなく、パッシブな合波回路によって実現してもよい。
　なお、第３、第６の実施例において、増幅回路２ａの代わりに可変利得増幅回路２ｂを設けるようにしてもよい。また、第４～第６の実施例において、増幅回路３ａの代わりに第３の実施例で説明したミキサ６とフィルタ７とを設けるようにしてもよい。 The signal quality evaluation circuit 10 is not limited to the configuration shown in FIG. 10, and may be realized by a passive multiplexing circuit.
In the third and sixth embodiments, the amplifier circuit 2a may be replaced by a variable gain amplifier circuit 2b, and in the fourth to sixth embodiments, the mixer 6 and filter 7 described in the third embodiment may be replaced by the amplifier circuit 3a.
［第７の実施例］
　第１～第６の実施例における負荷回路５，５ｐ，５ｎとして、直流成分を遮断するための容量と可変抵抗とからなる図１１のような回路を用いることができる。容量Ｃ１の一端は伝送線路４，４ｐ，４ｎの終端に接続され、容量Ｃ１の他端は可変抵抗ＶＲ１の一端に接続される。可変抵抗ＶＲ１の他端はグラウンドに接続される。 [Seventh Example]
The load circuits 5, 5p, and 5n in the first to sixth embodiments may be a circuit as shown in Fig. 11, which is made up of a capacitance for blocking DC components and a variable resistor. One end of the capacitance C1 is connected to the end of the transmission line 4, 4p, or 4n, and the other end of the capacitance C1 is connected to one end of the variable resistor VR1. The other end of the variable resistor VR1 is connected to ground.
　実際の回路においては、可変抵抗ＶＲ１として、図１２、図１３に示した構成を採用することもできる。図１２の構成では、可変抵抗ＶＲ１は、ベースに制御電圧Ｖｃｔｒｌが入力され、コレクタが電源電圧ＶＣＣに接続され、エミッタが容量Ｃ１の他端に接続されたＮＰＮバイポーラトランジスタＱ１４と、一端がトランジスタＱ１４のエミッタに接続され、他端がグラウンドに接続された抵抗Ｒ１６とから構成される。 In an actual circuit, the configuration shown in Figures 12 and 13 can also be used for variable resistor VR1. In the configuration in Figure 12, variable resistor VR1 is composed of an NPN bipolar transistor Q14, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of capacitor C1, and a resistor R16, whose one end is connected to the emitter of transistor Q14 and whose other end is connected to ground.
　図１３の構成では、可変抵抗ＶＲ１は、ベースに制御電圧Ｖｃｔｒｌが入力され、コレクタが電源電圧ＶＣＣに接続され、エミッタが容量Ｃ１の他端に接続されたＮＰＮバイポーラトランジスタＱ１５と、ベースにバイアス電圧Ｖｂが与えられ、コレクタがトランジスタＱ１５のエミッタに接続され、エミッタがグラウンドに接続されたＮＰＮバイポーラトランジスタＱ１６とから構成される。 In the configuration of Figure 13, variable resistor VR1 is composed of an NPN bipolar transistor Q15, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of capacitance C1, and an NPN bipolar transistor Q16, whose base receives a bias voltage Vb, whose collector is connected to the emitter of transistor Q15, and whose emitter is connected to ground.
　図１２、図１３のいずれの構成においても、制御電圧Ｖｃｔｒｌを変化させることにより、負荷回路５のインピーダンスを変化させることができる。図１２、図１３の例では、制御電圧Ｖｃｔｒｌを上昇させると負荷回路５のインピーダンスが増大し、制御電圧Ｖｃｔｒｌを低下させると負荷回路５のインピーダンスが減少する。 In either of the configurations shown in FIG. 12 and FIG. 13, the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl. In the examples shown in FIG. 12 and FIG. 13, increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.
　また、図１４に示すように可変利得増幅回路を用いたフィードバック構成により、負荷回路５を実現してもよい。図１４の構成では、可変抵抗ＶＲ１は、非反転入力端子に基準電圧ＶＲｅｆが入力され、反転入力端子が容量Ｃ１の他端に接続された可変利得増幅回路Ａ１と、一端が可変利得増幅回路Ａ１の出力端子に接続され、他端が可変利得増幅回路Ａ１の反転入力端子に接続された抵抗Ｒ１７とから構成される。図１４の構成の場合、可変利得増幅回路Ａ１の利得を上昇させると負荷回路５のインピーダンスが減少し、可変利得増幅回路Ａ１の利得を低下させると負荷回路５のインピーダンスが増大する。 Furthermore, the load circuit 5 may be realized by a feedback configuration using a variable gain amplifier circuit as shown in FIG. 14. In the configuration of FIG. 14, the variable resistor VR1 is composed of a variable gain amplifier circuit A1 having a reference voltage VRef input to its non-inverting input terminal and an inverting input terminal connected to the other end of the capacitor C1, and a resistor R17 having one end connected to the output terminal of the variable gain amplifier circuit A1 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A1. In the configuration of FIG. 14, increasing the gain of the variable gain amplifier circuit A1 reduces the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A1 increases the impedance of the load circuit 5.
　制御電圧Ｖｃｔｒｌによって可変利得増幅回路Ａ１の利得を変化させることにより、負荷回路５のインピーダンスを変化させることができる。可変利得増幅回路Ａ１としては、上記と同様にギルバートセル回路を用いることができる。
　図１１～図１４の例では、バイアス点の兼ね合いから、容量Ｃ１を挿入しているが、設計によっては容量Ｃ１を挿入せずに、伝送線路４，４ｐ，４ｎの終端と可変抵抗ＶＲ１とを直接接続してもよい。 The gain of the variable gain amplifier circuit A1 can be changed by the control voltage Vctrl, thereby changing the impedance of the load circuit 5. As the variable gain amplifier circuit A1, a Gilbert cell circuit can be used in the same manner as above.
In the examples of Figures 11 to 14, the capacitance C1 is inserted to consider the bias point, but depending on the design, the capacitance C1 may not be inserted and the ends of the transmission lines 4, 4p, and 4n may be directly connected to the variable resistor VR1.
　第１～第６の実施例における負荷回路５，５ｐ，５ｎとして、図１５に示すような可変容量ＶＣ１を用いることも可能である。可変容量ＶＣ１の一端は伝送線路４，４ｐ，４ｎの終端に接続され、可変容量ＶＣ１の他端はグラウンドに接続される。 As the load circuits 5, 5p, and 5n in the first to sixth embodiments, it is also possible to use a variable capacitance VC1 as shown in FIG. 15. One end of the variable capacitance VC1 is connected to the end of the transmission line 4, 4p, and 4n, and the other end of the variable capacitance VC1 is connected to ground.
　実際の回路においては、可変容量ＶＣ１として、図１６、図１７に示した構成を採用することもできる。図１６の構成では、可変容量ＶＣ１は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ２と、アノードに制御電圧Ｖｃｔｒｌが入力され、カソードが容量Ｃ２の他端に接続されたダイオードＤ１と、一端がダイオードＤ１のカソードに接続され、他端がグラウンドに接続された抵抗Ｒ１８とから構成される。 In an actual circuit, the configuration shown in Figures 16 and 17 can also be used for the variable capacitance VC1. In the configuration in Figure 16, the variable capacitance VC1 is composed of a capacitance C2, one end of which is connected to the end of the transmission lines 4, 4p, and 4n, a diode D1, the anode of which receives the control voltage Vctrl and the cathode of which is connected to the other end of the capacitance C2, and a resistor R18, one end of which is connected to the cathode of the diode D1 and the other end of which is connected to ground.
　図１７の構成では、可変容量ＶＣ１は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ３と、アノードに制御電圧Ｖｃｔｒｌが入力され、カソードが容量Ｃ３の他端に接続されたダイオードＤ２と、ベースにバイアス電圧Ｖｂが与えられ、コレクタがダイオードＤ２のカソードに接続され、エミッタがグラウンドに接続されたＮＰＮバイポーラトランジスタＱ１７とから構成される。 In the configuration of FIG. 17, the variable capacitance VC1 is composed of a capacitance C3, one end of which is connected to the end of the transmission lines 4, 4p, and 4n; a diode D2, whose anode receives a control voltage Vctrl and whose cathode is connected to the other end of the capacitance C3; and an NPN bipolar transistor Q17, whose base is supplied with a bias voltage Vb, whose collector is connected to the cathode of the diode D2, and whose emitter is connected to ground.
　図１６、図１７のいずれの構成においても、制御電圧Ｖｃｔｒｌを変化させることにより、負荷回路５のインピーダンスを変化させることができる。図１６、図１７の例では、制御電圧Ｖｃｔｒｌを上昇させると負荷回路５のインピーダンスが増大し、制御電圧Ｖｃｔｒｌを低下させると負荷回路５のインピーダンスが減少する。 In either of the configurations shown in Figures 16 and 17, the impedance of the load circuit 5 can be changed by changing the control voltage Vctrl. In the examples shown in Figures 16 and 17, increasing the control voltage Vctrl increases the impedance of the load circuit 5, and decreasing the control voltage Vctrl decreases the impedance of the load circuit 5.
　また、図１８に示すように可変利得増幅回路を用いたフィードバック構成により、可変容量ＶＣ１を実現してもよい。図１８の構成では、可変容量ＶＣ１は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ４と、非反転入力端子に基準電圧ＶＲｅｆが入力され、反転入力端子が容量Ｃ４の他端に接続された可変利得増幅回路Ａ２と、一端が可変利得増幅回路Ａ２の出力端子に接続され、他端が可変利得増幅回路Ａ２の反転入力端子に接続された容量Ｃ５とから構成される。図１８の構成の場合、可変利得増幅回路Ａ２の利得を上昇させると負荷回路５のインピーダンスが減少し、可変利得増幅回路Ａ２の利得を低下させると負荷回路５のインピーダンスが増大する。 Also, as shown in FIG. 18, the variable capacitance VC1 may be realized by a feedback configuration using a variable gain amplifier circuit. In the configuration of FIG. 18, the variable capacitance VC1 is composed of a capacitance C4 having one end connected to the end of the transmission line 4, 4p, 4n, a variable gain amplifier circuit A2 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitance C4, and a capacitance C5 having one end connected to the output terminal of the variable gain amplifier circuit A2 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A2. In the configuration of FIG. 18, increasing the gain of the variable gain amplifier circuit A2 reduces the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuit A2 increases the impedance of the load circuit 5.
　制御電圧Ｖｃｔｒｌによって可変利得増幅回路Ａ２の利得を変化させることにより、負荷回路５のインピーダンスを変化させることができる。可変利得増幅回路Ａ２としては、上記と同様にギルバートセル回路を用いることができる。 The impedance of the load circuit 5 can be changed by changing the gain of the variable gain amplifier circuit A2 using the control voltage Vctrl. As with the above, a Gilbert cell circuit can be used as the variable gain amplifier circuit A2.
　第１～第６の実施例における負荷回路５，５ｐ，５ｎとして、図１９に示すように可変抵抗ＶＲ１と可変容量ＶＣ１とを組み合わせた回路を用いることも可能である。実際の回路においては、負荷回路５，５ｐ，５ｎとして、図２０～図２２に示した構成を採用することができる。 As the load circuits 5, 5p, and 5n in the first to sixth embodiments, it is also possible to use a circuit that combines a variable resistor VR1 and a variable capacitor VC1 as shown in FIG. 19. In an actual circuit, the configurations shown in FIGS. 20 to 22 can be used as the load circuits 5, 5p, and 5n.
　図２０の構成では、負荷回路５は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ１と、ベースに制御電圧Ｖｃｔｒｌが入力され、コレクタが電源電圧ＶＣＣに接続され、エミッタが容量Ｃ１の他端に接続されたＮＰＮバイポーラトランジスタＱ１４と、一端がトランジスタＱ１４のエミッタに接続され、他端がグラウンドに接続された抵抗Ｒ１６と、アノードに制御電圧Ｖｃｔｒｌｃが入力され、カソードが容量Ｃ１の他端に接続されたダイオードＤ１とから構成される。 In the configuration of FIG. 20, the load circuit 5 is composed of a capacitor C1, one end of which is connected to the end of the transmission lines 4, 4p, and 4n; an NPN bipolar transistor Q14, the base of which receives a control voltage Vctrl, the collector of which is connected to the power supply voltage VCC, and the emitter of which is connected to the other end of the capacitor C1; a resistor R16, the one end of which is connected to the emitter of the transistor Q14 and the other end of which is connected to ground; and a diode D1, the anode of which receives a control voltage Vctrlc, and the cathode of which is connected to the other end of the capacitor C1.
　図２１の構成では、負荷回路５は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ１と、ベースに制御電圧Ｖｃｔｒｌが入力され、コレクタが電源電圧ＶＣＣに接続され、エミッタが容量Ｃ１の他端に接続されたＮＰＮバイポーラトランジスタＱ１５と、ベースにバイアス電圧Ｖｂが与えられ、コレクタがトランジスタＱ１５のエミッタに接続され、エミッタがグラウンドに接続されたＮＰＮバイポーラトランジスタＱ１６と、アノードに制御電圧Ｖｃｔｒｌｃが入力され、カソードが容量Ｃ１の他端に接続されたダイオードＤ２とから構成される。 In the configuration of FIG. 21, the load circuit 5 is composed of a capacitor C1, one end of which is connected to the end of the transmission lines 4, 4p, and 4n; an NPN bipolar transistor Q15, whose base receives a control voltage Vctrl, whose collector is connected to the power supply voltage VCC, and whose emitter is connected to the other end of the capacitor C1; an NPN bipolar transistor Q16, whose base receives a bias voltage Vb, whose collector is connected to the emitter of the transistor Q15, and whose emitter is connected to ground; and a diode D2, whose anode receives a control voltage Vctrlc, and whose cathode is connected to the other end of the capacitor C1.
　図２０、図２１の例では、制御電圧Ｖｃｔｒｌ，Ｖｃｔｒｌｃを上昇させると負荷回路５のインピーダンスが増大し、制御電圧Ｖｃｔｒｌ，Ｖｃｔｒｌｃを低下させると負荷回路５のインピーダンスが減少する。 In the examples of Figures 20 and 21, increasing the control voltages Vctrl and Vctrlc increases the impedance of the load circuit 5, and decreasing the control voltages Vctrl and Vctrlc decreases the impedance of the load circuit 5.
　図２２の構成では、負荷回路５は、一端が伝送線路４，４ｐ，４ｎの終端に接続された容量Ｃ１と、非反転入力端子に基準電圧ＶＲｅｆが入力され、反転入力端子が容量Ｃ１の他端に接続された可変利得増幅回路Ａ１と、一端が可変利得増幅回路Ａ１の出力端子に接続され、他端が可変利得増幅回路Ａ１の反転入力端子に接続された抵抗Ｒ１７と、非反転入力端子に基準電圧ＶＲｅｆが入力され、反転入力端子が容量Ｃ１の他端に接続された可変利得増幅回路Ａ２と、一端が可変利得増幅回路Ａ２の出力端子に接続され、他端が可変利得増幅回路Ａ２の反転入力端子に接続された容量Ｃ５とから構成される。 In the configuration of FIG. 22, the load circuit 5 is composed of a capacitor C1 having one end connected to the end of the transmission line 4, 4p, 4n, a variable gain amplifier circuit A1 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitor C1, a resistor R17 having one end connected to the output terminal of the variable gain amplifier circuit A1 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A1, a variable gain amplifier circuit A2 having a non-inverting input terminal to which a reference voltage VRef is input and an inverting input terminal connected to the other end of the capacitor C1, and a capacitor C5 having one end connected to the output terminal of the variable gain amplifier circuit A2 and the other end connected to the inverting input terminal of the variable gain amplifier circuit A2.
　図２２の構成の場合、可変利得増幅回路Ａ１，Ａ２の利得を上昇させると負荷回路５のインピーダンスが減少し、可変利得増幅回路Ａ１，Ａ２の利得を低下させると負荷回路５のインピーダンスが増大する。制御電圧Ｖｃｔｒｌ，Ｖｃｔｒｌｃによって可変利得増幅回路Ａ１，Ａ２の利得を変化させることにより、負荷回路５のインピーダンスを変化させることができる。 In the configuration of FIG. 22, increasing the gain of the variable gain amplifier circuits A1 and A2 reduces the impedance of the load circuit 5, and decreasing the gain of the variable gain amplifier circuits A1 and A2 increases the impedance of the load circuit 5. The impedance of the load circuit 5 can be changed by changing the gain of the variable gain amplifier circuits A1 and A2 with the control voltages Vctrl and Vctrlc.
　第１～第６の実施例における負荷回路５，５ｐ，５ｎとして、図２３に示すような可変インダクタＶＬ１を用いることも可能である。容量Ｃ１の一端は伝送線路４，４ｐ，４ｎの終端に接続され、容量Ｃ１の他端は可変インダクタＶＬ１の一端に接続される。可変インダクタＶＬ１の他端はグラウンドに接続される。 As the load circuits 5, 5p, 5n in the first to sixth embodiments, it is also possible to use a variable inductor VL1 as shown in FIG. 23. One end of the capacitance C1 is connected to the termination of the transmission line 4, 4p, 4n, and the other end of the capacitance C1 is connected to one end of the variable inductor VL1. The other end of the variable inductor VL1 is connected to ground.
　第１～第６の実施例における負荷回路５，５ｐ，５ｎとして、図２４に示すように可変抵抗ＶＲ１と可変容量ＶＣ１と可変インダクタＶＬ１とを組み合わせた回路を用いることも可能である。また、可変抵抗ＶＲ１と可変インダクタＶＬ１とを組み合わせてもよいし、可変容量ＶＣ１と可変インダクタＶＬ１とを組み合わせてもよい。 As the load circuits 5, 5p, 5n in the first to sixth embodiments, it is also possible to use a circuit that combines a variable resistor VR1, a variable capacitance VC1, and a variable inductor VL1, as shown in FIG. 24. It is also possible to combine a variable resistor VR1 with a variable inductor VL1, or to combine a variable capacitance VC1 with a variable inductor VL1.
　図１１～図２４では、負荷回路５の構成を例に挙げて説明しているが、負荷回路５ｐ，５ｎの構成も負荷回路５と同様である。
　第６の実施例で説明したように、負荷回路５ｐ，５ｎとインピーダンス制御回路９とを組み合わせる場合、差動信号ＯＵＴｐ，ＯＵＴｎの和が正の場合、負荷回路５ｎのインピーダンスを上昇させて、負荷回路５ｐのインピーダンスを低下させる。また、差動信号ＯＵＴｐ，ＯＵＴｎの和が負の場合、負荷回路５ｐのインピーダンスを上昇させて、負荷回路５ｎのインピーダンスを低下させる。 11 to 24, the configuration of the load circuit 5 is taken as an example for explanation, but the configuration of the load circuits 5p and 5n is also similar to that of the load circuit 5.
As described in the sixth embodiment, when the load circuits 5p, 5n are combined with the impedance control circuit 9, if the sum of the differential signals OUTp, OUTn is positive, the impedance of the load circuit 5n is increased and the impedance of the load circuit 5p is decreased. Also, if the sum of the differential signals OUTp, OUTn is negative, the impedance of the load circuit 5p is increased and the impedance of the load circuit 5n is decreased.
［第８の実施例］
　次に、本発明の第８の実施例について説明する。本実施例は、第１～第７の実施例の伝送線路４，４ｐ，４ｎの具体例を示すものである。伝送線路４ｐ，４ｎの断面図を図２５～図２７に示す。図２５の例は、マイクロストリップ線路の例を示している。伝送線路４ｐは、誘電体４００と、誘電体４００の表面に形成された導体からなる信号線路４０１と、誘電体４００の裏面に形成された導体からなるグラウンドプレーン４０３とから構成される。伝送線路４ｎは、誘電体４００と、誘電体４００の表面に形成された導体からなる信号線路４０２と、グラウンドプレーン４０３とから構成される。 [Eighth embodiment]
Next, an eighth embodiment of the present invention will be described. This embodiment shows a specific example of the transmission lines 4, 4p, and 4n of the first to seventh embodiments. Cross-sectional views of the transmission lines 4p and 4n are shown in Figs. 25 to 27. The example in Fig. 25 shows an example of a microstrip line. The transmission line 4p is composed of a dielectric 400, a signal line 401 made of a conductor formed on the surface of the dielectric 400, and a ground plane 403 made of a conductor formed on the back surface of the dielectric 400. The transmission line 4n is composed of a dielectric 400, a signal line 402 made of a conductor formed on the surface of the dielectric 400, and a ground plane 403.
　図２６の例は、コプレーナ線路の例を示している。伝送線路４ｐは、誘電体４００と、信号線路４０１と、信号線路４０１を間に挟んで信号線路４０２と反対側の誘電体４００の表面に形成された導体からなるグラウンドプレーン４０４とから構成される。伝送線路４ｎは、誘電体４００と、信号線路４０２と、信号線路４０２を間に挟んで信号線路４０１と反対側の誘電体４００の表面に形成された導体からなるグラウンドプレーン４０５とから構成される。 The example in FIG. 26 shows an example of a coplanar line. The transmission line 4p is composed of a dielectric 400, a signal line 401, and a ground plane 404 made of a conductor formed on the surface of the dielectric 400 on the side opposite the signal line 402, with the signal line 401 in between. The transmission line 4n is composed of a dielectric 400, a signal line 402, and a ground plane 405 made of a conductor formed on the surface of the dielectric 400 on the side opposite the signal line 401, with the signal line 402 in between.
　本発明においては、実装面積を削減するため、特にコプレーナ線路とマイクロストリップ線路とを組み合わせた複合型の構造を採用してもよい。図２７の例は、複合型の裏面グラウンド付きコプレーナ線路の例を示している。伝送線路４ｐは、誘電体４００と、信号線路４０１と、グラウンドプレーン４０３，４０４とから構成される。伝送線路４ｎは、誘電体４００と、信号線路４０２と、グラウンドプレーン４０３，４０５とから構成される。 In the present invention, in order to reduce the mounting area, a hybrid structure that combines a coplanar line and a microstrip line may be adopted. The example in FIG. 27 shows an example of a hybrid coplanar line with a back-side ground. Transmission line 4p is composed of a dielectric 400, a signal line 401, and ground planes 403 and 404. Transmission line 4n is composed of a dielectric 400, a signal line 402, and ground planes 403 and 405.
　図２５～図２７では、伝送線路４ｐ，４ｎの構成を例に挙げて説明しているが、伝送線路４の場合には、信号線路４０１と４０２のうちどちらか一方のみを設けるようにすればよい。
　伝送線路４，４ｐ，４ｎの構造は、図２５～図２７に示した断面構造のみに制限されるものではなく、特性インピーダンスが定義できる構造であれば、他の構造であってもよい。 25 to 27, the configuration of the transmission lines 4p and 4n is taken as an example for explanation, but in the case of the transmission line 4, it is sufficient to provide only one of the signal lines 401 and 402.
The structures of the transmission lines 4, 4p, 4n are not limited to the cross-sectional structures shown in FIGS. 25 to 27, but may be other structures as long as the characteristic impedance can be defined.
　図４、図６、図１０、図１２、図１３、図１７、図２０、図２１では、トランジスタＱ１～Ｑ１７としてバイポーラトランジスタを使用した例を示しているが、ＭＯＳトランジスタを使用してもよい。ＭＯＳトランジスタを使用する場合には、上記の説明において、ベースをゲートに置き換え、コレクタをドレインに置き換え、エミッタをソースに置き換えるようにすればよい。 In Figures 4, 6, 10, 12, 13, 17, 20, and 21, bipolar transistors are used as transistors Q1 to Q17, but MOS transistors may also be used. When using MOS transistors, simply replace the base with the gate, the collector with the drain, and the emitter with the source in the above explanation.
　上記の実施例の一部又は全部は、以下の付記のようにも記載されうるが、以下には限られない。 Some or all of the above examples may be described as follows, but are not limited to the following:
　（付記１）本発明の位相調整回路は、正弦波状のクロック信号を生成するように構成されたクロック生成回路と、前記クロック生成回路から出力されたクロック信号を増幅するように構成された増幅回路と、入力端が前記増幅回路の出力端子に接続された伝送線路と、前記伝送線路の終端に接続された、外部からインピーダンスの調整が可能な負荷回路と、前記増幅回路の出力信号と前記伝送線路からの戻り信号とが前記増幅回路の出力端子において加算された信号を入力とする出力回路とを備える。 (Note 1) The phase adjustment circuit of the present invention comprises a clock generation circuit configured to generate a sine wave clock signal, an amplifier circuit configured to amplify the clock signal output from the clock generation circuit, a transmission line whose input end is connected to the output terminal of the amplifier circuit, a load circuit whose impedance can be adjusted externally and connected to the end of the transmission line, and an output circuit whose input is a signal obtained by adding the output signal of the amplifier circuit and a return signal from the transmission line at the output terminal of the amplifier circuit.
　（付記２）付記１記載の位相調整回路において、前記負荷回路は、外部からインピーダンスの調整が可能な可変抵抗からなる。 (Note 2) In the phase adjustment circuit described in Note 1, the load circuit is made of a variable resistor whose impedance can be adjusted externally.
　（付記３）付記１記載の位相調整回路において、前記負荷回路は、外部からインピーダンスの調整が可能な可変容量からなる。 (Appendix 3) In the phase adjustment circuit described in Appendix 1, the load circuit is made of a variable capacitance whose impedance can be adjusted externally.
　（付記４）付記１記載の位相調整回路において、前記負荷回路は、外部からインピーダンスの調整が可能な可変インダクタからなる。 (Note 4) In the phase adjustment circuit described in Note 1, the load circuit is made of a variable inductor whose impedance can be adjusted externally.
　（付記５）付記１記載の位相調整回路において、前記負荷回路は、外部からインピーダンスの調整が可能な可変抵抗と可変容量と可変インダクタのうち少なくとも２つの組み合わせからなる。 (Appendix 5) In the phase adjustment circuit described in Appendix 1, the load circuit is composed of a combination of at least two of a variable resistor, a variable capacitor, and a variable inductor whose impedance can be adjusted externally.
　（付記６）付記１記載の位相調整回路において、前記クロック生成回路は、正弦波状の差動クロック信号を生成し、前記増幅回路は、前記差動クロック信号を増幅する差動入力差動出力型の回路であり、前記伝送線路は、入力端が前記増幅回路の非反転出力端子に接続された第１の伝送線路と、入力端が前記増幅回路の反転出力端子に接続された第２の伝送線路とからなり、前記負荷回路は、前記第１の伝送線路の終端に接続された、外部からインピーダンスの調整が可能な第１の負荷回路と、前記第２の伝送線路の終端に接続された、外部からインピーダンスの調整が可能な第２の負荷回路とからなり、前記出力回路は、前記増幅回路の正相側の出力信号と前記第１の伝送線路からの戻り信号とが前記増幅回路の非反転出力端子において加算された信号と、前記増幅回路の逆相側の出力信号と前記第２の伝送線路からの戻り信号とが前記増幅回路の反転出力端子において加算された信号とを入力とする差動入力差動出力型の回路であり、前記出力回路から出力された差動信号の和が０となるように、前記第１、第２の負荷回路のインピーダンスを制御するように構成されたインピーダンス制御回路をさらに備える。 (Appendix 6) In the phase adjustment circuit described in Appendix 1, the clock generation circuit generates a sine wave differential clock signal, the amplifier circuit is a differential input/differential output type circuit that amplifies the differential clock signal, the transmission line is composed of a first transmission line whose input end is connected to the non-inverting output terminal of the amplifier circuit and a second transmission line whose input end is connected to the inverting output terminal of the amplifier circuit, and the load circuit is composed of a first load circuit connected to the end of the first transmission line and capable of adjusting impedance from the outside, and a second load circuit connected to the end of the second transmission line and capable of adjusting impedance from the outside. The output circuit is a differential input/differential output type circuit that receives as input a signal obtained by adding the positive-phase output signal of the amplifier circuit and the return signal from the first transmission line at the non-inverting output terminal of the amplifier circuit, and a signal obtained by adding the negative-phase output signal of the amplifier circuit and the return signal from the second transmission line at the inverting output terminal of the amplifier circuit, and further includes an impedance control circuit configured to control the impedances of the first and second load circuits so that the sum of the differential signals output from the output circuit is 0.
　（付記７）付記１記載の位相調整回路において、前記出力回路は、前記増幅回路の出力端子において加算された信号を増幅するように構成された増幅回路である。 (Appendix 7) In the phase adjustment circuit described in Appendix 1, the output circuit is an amplifier circuit configured to amplify the signal added at the output terminal of the amplifier circuit.
　（付記８）付記１記載の位相調整回路において、前記出力回路は、前記増幅回路の出力端子において加算された信号と外部から入力された搬送波信号とを混合するように構成されたミキサと、前記ミキサの出力信号をろ波して、所望の周波数の信号を通過させるように構成されたフィルタとから構成される。 (Appendix 8) In the phase adjustment circuit described in Appendix 1, the output circuit is composed of a mixer configured to mix the signal added at the output terminal of the amplifier circuit with an externally input carrier signal, and a filter configured to filter the output signal of the mixer and pass a signal of a desired frequency.
　本発明は、正弦波の位相を調整する技術に適用することができる。 The present invention can be applied to technology for adjusting the phase of a sine wave.
　１，１ａ…クロック生成回路、２，２ａ，３，３ａ…増幅回路、２ｂ，Ａ１，Ａ２…可変利得増幅回路、４，４ｐ，４ｎ…伝送線路、５，５ｐ，５ｎ…負荷回路、６…ミキサ、７…フィルタ、８…振幅制御回路、９…インピーダンス制御回路、１０…信号品質評価回路、４００…誘電体、４０１，４０２…信号線路、４０３～４０５…グラウンドプレーン、Ｑ１～Ｑ１７…ＮＰＮトランジスタ、Ｄ１，Ｄ２…ダイオード、Ｒ１～Ｒ１８…抵抗、Ｃ１～Ｃ５…容量、ＶＲ１…可変抵抗、ＶＣ１…可変容量、ＶＬ１…可変インダクタ。
 
  1, 1a...clock generation circuit, 2, 2a, 3, 3a...amplification circuit, 2b, A1, A2...variable gain amplifier circuit, 4, 4p, 4n...transmission line, 5, 5p, 5n...load circuit, 6...mixer, 7...filter, 8...amplitude control circuit, 9...impedance control circuit, 10...signal quality evaluation circuit, 400...dielectric, 401, 402...signal line, 403-405...ground plane, Q1-Q17...NPN transistor, D1, D2...diode, R1-R18...resistor, C1-C5...capacitance, VR1...variable resistor, VC1...variable capacitance, VL1...variable inductor.

Claims (8)

  1. 　正弦波状のクロック信号を生成するように構成されたクロック生成回路と、
    　前記クロック生成回路から出力されたクロック信号を増幅するように構成された増幅回路と、
    　入力端が前記増幅回路の出力端子に接続された伝送線路と、
    　前記伝送線路の終端に接続された、外部からインピーダンスの調整が可能な負荷回路と、
    　前記増幅回路の出力信号と前記伝送線路からの戻り信号とが前記増幅回路の出力端子において加算された信号を入力とする出力回路とを備えることを特徴とする位相調整回路。     a clock generation circuit configured to generate a sinusoidal clock signal;
    an amplifier circuit configured to amplify the clock signal output from the clock generation circuit;
    a transmission line having an input end connected to an output terminal of the amplifier circuit;
    a load circuit whose impedance can be adjusted externally and which is connected to an end of the transmission line;
    a phase adjustment circuit comprising: an output circuit which receives as its input a signal obtained by adding an output signal of said amplifier circuit and a return signal from said transmission line at an output terminal of said amplifier circuit;
  2. 　請求項１記載の位相調整回路において、
    　前記負荷回路は、外部からインピーダンスの調整が可能な可変抵抗からなることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    13. A phase adjustment circuit, comprising: a load circuit including a variable resistor capable of adjusting impedance from outside;
  3. 　請求項１記載の位相調整回路において、
    　前記負荷回路は、外部からインピーダンスの調整が可能な可変容量からなることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    11. A phase adjustment circuit, comprising: a load circuit including a variable capacitance having an externally adjustable impedance.
  4. 　請求項１記載の位相調整回路において、
    　前記負荷回路は、外部からインピーダンスの調整が可能な可変インダクタからなることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    1 is a circuit diagram showing a phase adjustment circuit according to the first embodiment of the present invention;
  5. 　請求項１記載の位相調整回路において、
    　前記負荷回路は、外部からインピーダンスの調整が可能な可変抵抗と可変容量と可変インダクタのうち少なくとも２つの組み合わせからなることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    The load circuit is a phase adjustment circuit comprising a combination of at least two of a variable resistor, a variable capacitor, and a variable inductor, each of which has an externally adjustable impedance.
  6. 　請求項１記載の位相調整回路において、
    　前記クロック生成回路は、正弦波状の差動クロック信号を生成し、
    　前記増幅回路は、前記差動クロック信号を増幅する差動入力差動出力型の回路であり、
    　前記伝送線路は、
    　入力端が前記増幅回路の非反転出力端子に接続された第１の伝送線路と、
    　入力端が前記増幅回路の反転出力端子に接続された第２の伝送線路とからなり、
    　前記負荷回路は、
    　前記第１の伝送線路の終端に接続された、外部からインピーダンスの調整が可能な第１の負荷回路と、
    　前記第２の伝送線路の終端に接続された、外部からインピーダンスの調整が可能な第２の負荷回路とからなり、
    　前記出力回路は、前記増幅回路の正相側の出力信号と前記第１の伝送線路からの戻り信号とが前記増幅回路の非反転出力端子において加算された信号と、前記増幅回路の逆相側の出力信号と前記第２の伝送線路からの戻り信号とが前記増幅回路の反転出力端子において加算された信号とを入力とする差動入力差動出力型の回路であり、
    　前記出力回路から出力された差動信号の和が０となるように、前記第１、第２の負荷回路のインピーダンスを制御するように構成されたインピーダンス制御回路をさらに備えることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    the clock generation circuit generates a sinusoidal differential clock signal;
    the amplifier circuit is a differential input/differential output type circuit that amplifies the differential clock signal,
    The transmission line is
    a first transmission line having an input end connected to a non-inverting output terminal of the amplifier circuit;
    a second transmission line having an input end connected to an inverting output terminal of the amplifier circuit;
    The load circuit includes:
    a first load circuit, the first load circuit having an externally adjustable impedance, connected to an end of the first transmission line;
    a second load circuit connected to an end of the second transmission line and having an externally adjustable impedance;
    the output circuit is a differential input/differential output type circuit which receives as inputs a signal obtained by adding, at a non-inverting output terminal of the amplifier circuit, an output signal on the positive phase side of the amplifier circuit and a return signal from the first transmission line, and a signal obtained by adding, at an inverting output terminal of the amplifier circuit, an output signal on the negative phase side of the amplifier circuit and a return signal from the second transmission line,
    13. A phase adjustment circuit comprising: an impedance control circuit configured to control impedances of the first and second load circuits so that a sum of differential signals output from the output circuit becomes zero.
  7. 　請求項１記載の位相調整回路において、
    　前記出力回路は、前記増幅回路の出力端子において加算された信号を増幅するように構成された増幅回路であることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    11. A phase adjustment circuit, wherein the output circuit is an amplifier circuit configured to amplify the added signal at an output terminal of the amplifier circuit.
  8. 　請求項１記載の位相調整回路において、
    　前記出力回路は、
    　前記増幅回路の出力端子において加算された信号と外部から入力された搬送波信号とを混合するように構成されたミキサと、
    　前記ミキサの出力信号をろ波して、所望の周波数の信号を通過させるように構成されたフィルタとから構成されることを特徴とする位相調整回路。     2. The phase adjustment circuit according to claim 1,
    The output circuit includes:
    a mixer configured to mix the signal added at the output terminal of the amplifier circuit with an externally input carrier signal;
    a filter configured to filter the output signal of the mixer to pass a signal of a desired frequency.
PCT/JP2022/046188 2022-12-15 2022-12-15 Phase adjusting circuit WO2024127580A1 (en)

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Application Number Priority Date Filing Date Title
PCT/JP2022/046188 WO2024127580A1 (en) 2022-12-15 2022-12-15 Phase adjusting circuit

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Application Number Title Priority Date Filing Date
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223945A (en) * 1996-02-16 1997-08-26 Nec Eng Ltd Phase adjustment device
JP2003168956A (en) * 2001-11-30 2003-06-13 Fujitsu Ltd Variable phase shifter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09223945A (en) * 1996-02-16 1997-08-26 Nec Eng Ltd Phase adjustment device
JP2003168956A (en) * 2001-11-30 2003-06-13 Fujitsu Ltd Variable phase shifter

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