WO2024126206A1 - Procédé de production de composants électroniques - Google Patents

Procédé de production de composants électroniques Download PDF

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Publication number
WO2024126206A1
WO2024126206A1 PCT/EP2023/084538 EP2023084538W WO2024126206A1 WO 2024126206 A1 WO2024126206 A1 WO 2024126206A1 EP 2023084538 W EP2023084538 W EP 2023084538W WO 2024126206 A1 WO2024126206 A1 WO 2024126206A1
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WO
WIPO (PCT)
Prior art keywords
grid structure
metal structures
cells
layer
photoresist mask
Prior art date
Application number
PCT/EP2023/084538
Other languages
German (de)
English (en)
Inventor
Markus Kirsch
Andreas Waldschik
Karlheinz Arndt
Dirk Becker
Bodo Wallikewitz
Thomas Schwarz
Original Assignee
Ams-Osram International Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ams-Osram International Gmbh filed Critical Ams-Osram International Gmbh
Publication of WO2024126206A1 publication Critical patent/WO2024126206A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination

Definitions

  • the present invention relates to a method for producing electronic components.
  • MIS molded interconnect substrate
  • One object of the present invention is to provide a method for producing electronic components. This object is achieved by a method having the features of the independent claim. Various further developments are specified in the dependent claims.
  • a method for producing electronic components comprises steps for providing a carrier with a release layer arranged on a top side, for forming a plurality of metal structures above the release layer, for forming a first grid structure made of a photoresist that surrounds the metal structures above the release layer, for arranging a potting material in cells of the first grid structure, wherein the metal structures are embedded in the potting material, for supplementing the metal structures with a structure layer raised above a top side of the potting material, for arranging a plurality of electronic semiconductor chips above the metal structures, for forming a second grid structure made of a photoresist that surrounds the electronic semiconductor chips, for arranging an encapsulation material terials in cells of the second grid structure, wherein the electronic semiconductor chips are embedded in the encapsulation material, for removing the first grid structure and the second grid structure to expose the electronic components formed in the cells of the first grid structure and the second grid structure, and for detaching the electronic components from the release layer.
  • the method enables a number of electronic components to be manufactured simultaneously.
  • the electronic components are separated by removing the grid structures made from photoresist.
  • a separate separation process e.g. sawing, lasering, scoring, cutting
  • This advantageously allows the electronic components to be manufactured with smaller distances from one another, which enables a larger number of electronic components per area to be manufactured together.
  • the separation of the electronic components by removing the grid structures also advantageously enables a higher level of precision than separation using a sawing process.
  • a further advantage of the method is that it enables the production of electronic components with a non-rectangular basic shape.
  • the formation of the plurality of metal structures comprises steps of forming a first photoresist mask over the release layer, of galvanically growing a first inner structural layer of the metal structures in openings of the first photoresist mask, of forming a second photoresist mask over the first photoresist mask and the first inner structural layer, wherein openings of the second photoresist mask are arranged over the metal structures of the first inner structural layer, of galvanically growing a second inner structural layer of the metal structures in the openings of the second photoresist mask and of removing the second photoresist mask and the first photoresist mask.
  • this method enables the metal structures to be formed with a flexibly predeterminable geometry.
  • the release layer is electrically conductive. This makes it possible to use the release layer as an electrode for the galvanic growth of the first inner structural layer and the second inner structural layer of the metal structures.
  • a step is carried out to form a first seed layer over the release layer, the first seed layer having a plurality of first seed surfaces that are electrically conductively connected to one another, the openings of the first photoresist mask being arranged over the first seed surfaces.
  • the first seed surfaces can serve as an electrode for the galvanic growth of the first inner structural layer and the second inner structural layer of the metal structures.
  • the first seed layer is formed using a first seed layer generation mask.
  • the first seed layer generation mask is removed after the first seed layer has been formed.
  • the first seed layer generation mask can be designed as a resist mask, for example.
  • the first seed layer generation mask can also be designed as a shadow mask or as another mask.
  • the first lattice structure is formed with walls that are at least as high as the metal structures. This advantageously makes it possible to completely embed the metal structures in the potting material.
  • the arrangement of the potting material in the cells of the first grid structure comprises an additional step of grinding off a part of the potting material covering the first grid structure and the metal structures, so that the first grid structure and the Metal structures are accessible on the upper side of the potting material. This advantageously enables further processing of the metal structures and later removal of the first grid structure.
  • the addition of the structural layer raised above the encapsulation material to the metal structures comprises steps for forming a second seed layer having a plurality of separate second seed surfaces over the encapsulation material and the metal structures, with a second seed surface being arranged over each metal structure, for forming a third photoresist mask over the first grid structure and the encapsulation material, with the second seed surfaces being exposed in openings in the third photoresist mask, and for galvanically growing the structural layer raised above the encapsulation material in the openings in the third photoresist mask.
  • the third photoresist mask is removed before the second grid structure is formed.
  • the second seed layer is formed using a second seed layer generation mask.
  • the second seed layer generation mask is removed after the second seed layer has been formed.
  • the second seed layer generation mask can be designed, for example, as a resist mask or as another mask.
  • the second lattice structure is formed with walls that protrude above the electronic semiconductor chips arranged above the metal structures. This advantageously makes it possible to completely embed the electronic semiconductor chips in the encapsulation material.
  • arranging the capsule material in the cells of the second lattice structure comprises a step for removing a part of the capsule material covering the second grid structure so that the second grid structure is accessible at an upper side of the capsule material. This advantageously enables later removal of the second grid structure.
  • the part of the capsule material covering the second lattice structure is removed by wet blasting, by sandblasting, by grinding, by etching or by means of a laser beam.
  • these methods each enable reliable removal of the part of the capsule material covering the second lattice structure.
  • the capsule material is cured in a location-dependent manner before the part covering the second lattice structure is removed.
  • the location-dependent curing can be carried out, for example, by a location-dependent exposure of the capsule material.
  • the location-dependent curing of the capsule material enables removal of only the non-cured parts of the capsule material.
  • a step is carried out for arranging a cover layer covering the capsule material in the cells of the second lattice structure.
  • the cover layer can, for example, comprise a different material than the capsule material.
  • the cover layer can therefore assume a different function than the capsule material.
  • the cover layer can have a wavelength-converting function or a reflective function.
  • a step is carried out to form cavity walls in the cells of the second lattice structure.
  • the capsule material is arranged in cavities delimited by the cavity walls.
  • the method also enables the formation of cavity walls surrounding the electronic semiconductor chips, which can serve as reflectors, for example.
  • the cavity walls are formed by a molding process. This advantageously enables the cavity walls to be formed with a flexibly predeterminable geometry.
  • the cells of the first grid structure have a non-rectangular base area, in particular a circular, triangular, hexagonal or L-shaped base area.
  • the method therefore advantageously enables the production of electronic components with different housing shapes.
  • At least two cells of the first grid structure have a different base area. The method therefore enables the simultaneous production of differently designed electronic components.
  • Figure 1 is a sectional side view of a carrier
  • Figure 2 shows the carrier with the release layer arranged thereon
  • Figure 3 shows the carrier with the first nucleation layer generation mask arranged on the release layer;
  • Figure 4 is a plan view of the first seed layer generation mask;
  • Figure 5 shows the carrier with first germ surfaces formed in openings of the first germ layer generation mask
  • Figure 6 is a plan view of the first germination surfaces
  • Figure 7 is a plan view of a first photoresist mask formed over the first seed surfaces
  • Figure 8 is a sectional side view of a first inner structural layer of metal structures formed in openings of the first photoresist mask
  • Figure 9 is a sectional side view of a second photoresist mask formed over the first photoresist mask with a second inner structural layer of the metal structures formed in openings;
  • Figure 10 is a plan view of the second inner structural layer of the metal structures
  • Figure 11 is a sectional side view of the metal structures after removal of the first photoresist mask and the second photoresist mask;
  • Figure 12 is a sectional side view of a first lattice structure surrounding the metal structures
  • Figure 13 is a plan view of the first lattice structure
  • Figure 14 shows a potting material arranged in cells of the first lattice structure, in which the metal structures are embedded;
  • Figure 15 shows the first grid structure and the potting material after removal of a part of the potting material;
  • Figure 16 shows a second seed layer generation mask arranged over the potting material and the metal structures
  • Figure 17 shows second germination surfaces formed in openings of the second germination layer generation mask
  • Figure 18 is a plan view of the second germination surfaces
  • Figure 19 is a plan view of a third photoresist mask formed over the first grid structure and the encapsulation material
  • Figure 20 is a sectional side view of the third photoresist mask with an outer structural layer of the metal structures formed in openings of the third photoresist mask;
  • Figure 21 shows a coating of the metal structures arranged on the outer structural layer
  • Figure 22 is a plan view of electronic semiconductor chips arranged above the metal structures
  • Figure 23 is a sectional side view of the electronic semiconductor chips arranged above the metal structures
  • Figure 24 shows the arrangements after removal of the third photoresist mask
  • Figure 25 is a sectional side view of a second grid structure surrounding the electronic semiconductor chips;
  • Figure 26 shows a capping material arranged in the second lattice structure;
  • Figure 27 shows the capsule material after removal of a part of the capsule material
  • Figure 28 shows a plurality of electronic components after removal of the first grid structure and the second grid structure
  • Figure 29 the electronic components after detachment from the release layer
  • Figure 30 is a sectional side view of the carrier, the release layer and the first photoresist mask arranged thereover;
  • Figure 31 is a sectional side view of a cover layer arranged over the capsule material
  • Figure 32 is a sectional side view of a mold used to form cavity walls
  • Figure 33 is a sectional side view of cavity walls formed in the cells of the second lattice structure
  • Figure 34 the cavities delimited by the cavity walls with capsule material arranged therein;
  • Figure 35 shows the cavity walls with the capsule material arranged therein after removal of a part of the capsule material
  • Figures 36 to 40 show different base areas of cells of the first lattice structure.
  • Figure 1 shows a schematic sectional side view of a part of a carrier 100.
  • the carrier 100 is designed as a substantially flat disk with a substantially flat upper side 101.
  • Figure 2 shows the carrier 100 after a release layer 110 has been arranged on the top side 101 of the carrier 100.
  • the release layer 110 can be designed, for example, as a foil or as a thin film and has a top side 111 that faces away from the top side 101 of the carrier 100.
  • the top side 111 of the release layer 110 is also essentially flat and level.
  • the release layer 110 can be designed, for example, to enable detachment by means of a laser detachment process (laser lift-off).
  • Figure 3 shows the carrier 100 with a first seed layer generation mask 200 arranged on the top side 111 of the release layer 110.
  • Figure 4 shows a plan view of the top side 111 of the release layer 110 and the first seed layer generation mask 200 arranged thereon.
  • Figure 4 like all other figures, shows only a section of the carrier 100 and the layers and components arranged above its top side 101.
  • the carrier 100 can in reality have larger dimensions.
  • Figure 4 also shows the course of the cut in the sectional view shown in Figure 3.
  • the first seed layer generation mask 200 has a top side 201 facing away from the top side 111 of the release layer 110.
  • the first seed layer generation mask 200 has openings 210. In the area of the openings 210, the top side 111 of the release layer 110 is exposed and is not covered by the first seed layer generation mask 200.
  • the first seed layer generation mask 200 can be formed from a photoresist, for example. However, the first seed layer generation mask 200 can also be another mask, for example a reusable mask.
  • Figure 5 shows a schematic sectional side view of the carrier 100 in a processing stage subsequent to the representation in Figure 3. The section in Figure 5 runs as in Figure 3.
  • a first seed layer 250 has been formed on the upper side 111 of the release layer 110.
  • Figure 6 shows a plan view of the upper side 111 of the release layer
  • the first seed layer 250 comprises an electrically conductive material, for example a metal.
  • the first seed layer 250 forms a customer metallization of the electronic components obtainable by the manufacturing method described here.
  • the first seed layer 250 comprises a plurality of first seed surfaces 260 which are electrically conductively connected to one another via connecting sections 270.
  • An upper side 251 of the first seed layer 250 is separated from the upper side
  • Figure 7 shows a top view of the top side 251 of the first seed layer 250 after forming a first photoresist mask 300 over the release layer 110.
  • the first photoresist mask 300 has been formed from a photoresist.
  • the first photoresist mask 300 has openings 310 arranged over the first seed surfaces 260 of the first seed layer 250.
  • the first seed surfaces 260 of the first seed layer 250 are exposed in the openings 310 of the first photoresist mask 300, while the connecting sections 270 of the first seed layer 250 and the sections of the top side 111 of the release layer 110 not covered by the first seed layer 250 are covered by the first photoresist mask 300.
  • Figure 8 shows a schematic sectional side view of the carrier 100 in a temporally different position from the representation of Figure 7. subsequent processing stage. The cut runs along a cutting plane marked in Figure 7.
  • a first inner structural layer 410 of metal structures 400 has been produced in the openings 310 of the first photoresist mask 300 by galvanic growth.
  • the first inner structural layer 410 of the metal structures 400 expediently completely fills the openings 310 of the first photoresist mask 300.
  • the first inner structural layer 410 of the metal structures 400 can be formed from copper, for example.
  • Figure 9 shows a schematic sectional side view of the carrier 100 in a processing stage that follows the representation in Figure 8. The section in Figure 9 runs as in Figure 8.
  • Figure 10 shows a top view of the processing stage in Figure 9.
  • a second photoresist mask 320 has been formed over the first photoresist mask 300 and the first inner structural layer 410.
  • the second photoresist mask 320 has been formed from a photoresist, for example from the same photoresist as the first photoresist mask 300.
  • the second photoresist mask 320 has openings 330 which are arranged over the openings 310 of the first photoresist mask 300 and thus over the first inner structural layer 410 of the metal structures 400.
  • the openings 330 of the second photoresist mask 320 can be smaller than the openings 310 of the first photoresist mask 300 in order to compensate for positioning inaccuracies.
  • a second inner structural layer 420 of the metal structures 400 is produced in the openings 330 of the second photoresist mask 320 by galvanic growth.
  • the second inner structural layer 420 adjoins the first inner structural layer 410, so that the metal structures 400 comprising the first inner structural layer 410 and the second inner structural layer 420 are each formed integrally.
  • the second inner structural layer 420 can be For example, it can also be made of copper and expediently completely fills the openings 330 of the second photoresist mask 320.
  • Figure 11 shows a schematic sectional side view of the carrier 100 after removal of the second photoresist mask 320 and the first photoresist mask 300.
  • the section runs as in Figure 9.
  • the metal structures 400 formed over the first seed surfaces 260 of the first seed layer 250 are exposed.
  • the metal structures 400 are spaced apart from one another and are each formed from the first inner structure layer 410 and the second inner structure layer 420.
  • Figure 12 shows a schematic sectional side view of the carrier 100 in a processing stage that follows the representation in Figure 11.
  • Figure 13 shows a plan view of the top side 111 of the release layer 110 and the metal structures 400 in the processing stage shown in Figure 12.
  • a first grid structure 500 made of a photoresist has been formed on the upper side 111 of the release layer 110.
  • the first grid structure 500 has walls 510 that delimit the metal structures 400.
  • the walls 510 of the first grid structure 500 form cells 520.
  • One or more metal structures 400 are arranged in each cell 520 of the first grid structure 500. In the example shown in the figures, two metal structures 400 are arranged in each cell 520 of the first grid structure 500.
  • the walls 510 of the first grid structure 500 are at least as high as the metal structures 400 in the direction perpendicular to the upper side 111 of the release layer 110. It is expedient if the walls 510 of the first grid structure 500 are approximately as high as the metal structures 400.
  • the cells 520 of the first grid structure 500 each have a base area 525. In the example shown in Figure 13, the base area 525 of each cell 520 is rectangular. It is explained further below with reference to Figures 36 to 40 that the base areas 525 of the cells 520 can also be designed differently.
  • the first grid structure 500 has an upper side 501 which faces away from the upper side 111 of the release layer 110.
  • Figure 14 shows a schematic sectional side view of the carrier 100 after arranging a potting material 600 in the cells 520 of the first grid structure 500.
  • the metal structures 400 arranged in the cells 520 have been embedded in the potting material 600.
  • the potting material 600 covers the first grid structure 500 so completely that the top side 501 of the first grid structure 500 is also covered by a covering part 610 of the potting material
  • the metal structures 400 are arranged on a top side facing away from the top side 111 of the release layer 110.
  • the potting material 600 can be, for example, an epoxy, a silicone or another plastic material.
  • the potting material 600 can, for example, be opaque and can, for example, be black or white in color. Fillers, for example glass beads, can also be incorporated into the potting material 600 in order to enable CTE adjustments or to influence the flow behavior.
  • the potting material 600 can, for example, have been arranged in the cells 520 of the first lattice structure 500 by a molding process.
  • Figure 15 shows a schematic sectional side view of the carrier 100 after removal of the part 610 of the Casting material 600.
  • the covering part 610 of the casting material 600 can be removed, for example, by grinding.
  • the covering part 610 has been removed so completely that the top side 501 of the first grid structure 500 and the metal structures 400 arranged in the cells 520 of the first grid structure 500 are now accessible on the top side 601 of the casting material 600.
  • Figure 16 shows a schematic sectional side view of the carrier 100 after arranging a second seed layer generation mask 700 over the top side 501 of the first grid structure 500 and the top side 601 of the encapsulation material 600.
  • the second seed layer generation mask 700 can be designed, for example, as a photoresist mask or as a reusable mask.
  • the second seed layer generation mask 700 has openings 710 that are arranged over the metal structures 400 embedded in the encapsulation material 600.
  • the second seed layer generation mask 700 has a top side 701 that faces away from the top side 501 of the first grid structure 500 and the top side 601 of the encapsulation material 600.
  • Figure 17 shows a schematic sectional side view of the carrier 100 after arranging a second seed layer 750.
  • the second seed layer 750 forms second seed surfaces 760 arranged in the openings 710 of the second seed layer generation mask 700.
  • the second seed layer 750 can have been deposited by sputtering, for example.
  • the second seed layer 750 comprises an electrically conductive material, for example a metal.
  • the second seed layer 750 can comprise copper, for example.
  • Figure 18 shows a top view of the top side 501 of the first lattice structure 500, the top side 601 of the potting material 600 and a top side 751 of the second seed surfaces 760 after removal of the second seed layer generation mask 700.
  • the individual second seed surfaces 760 are separated from each other. Every second germ surface 760 is arranged above one of the metal structures 400 embedded in the potting material 600 and is in contact with this metal structure 400.
  • the size of the second seed surfaces 760 determined by the size of the openings 710 of the second seed layer generation mask 700 can be larger than that of the second inner structure layer 420 of the metal structures 400, so that the second seed surfaces 760 are also partially arranged on the upper side 601 of the potting material 600.
  • Figure 19 shows a plan view of a third photoresist mask 340 applied in a processing step following the illustration in Figure 18.
  • the third photoresist mask 340 covers the upper side 501 of the first grid structure 500 and the upper side 601 of the encapsulation material 600.
  • the third photoresist mask 340 has openings 350 which are arranged above the second seed surfaces 760, so that the second seed surfaces 760 are not covered by the third photoresist mask 340, but are exposed in the openings 350 of the third photoresist mask 340.
  • Figure 20 shows a schematic sectional side view of the carrier 100 after the metal structures 400 have been supplemented by an outer structural layer 430 raised above the upper side 601 of the encapsulation material 600.
  • the outer structural layer 430 of the metal structures 400 has been produced by galvanic growth in the openings 350 of the third photoresist mask 340. It is expedient if the outer structural layer 430 of the metal structures 400 completely fills the openings 350 of the third photoresist mask 340.
  • the outer structural layer 430 of the metal structures 400 has a metal, expediently the same metal as the first inner structural layer 410 and the second inner structural layer 420.
  • the outer structural layer 430 can have copper.
  • Figure 21 shows a schematic sectional side view of the carrier 100 after deposition of a coating 440 on the outer structural layer 430 of the metal structures 400.
  • the coating 440 can be, for example, a solderable coating.
  • the coating 440 forms an upper side 401 of the metal structures 400.
  • Figure 22 shows a plan view of the third photoresist mask 340 and the upper sides 401 of the metal structures 400 in a processing stage that follows the representation in Figure 21.
  • Figure 23 shows a schematic sectional side view of this processing stage.
  • a plurality of electronic semiconductor chips 800 have been arranged over the metal structures 400.
  • one electronic semiconductor chip 800 has been arranged over each of the two metal structures 400 arranged in a common cell 520 of the first grid structure 500 and has been electrically connected to these two metal structures 400.
  • Each electronic semiconductor chip 800 has an outer side 801 and a contact side 802 opposite the outer side 801.
  • On the contact side 802, each electronic semiconductor chip 800 has two electrical contact surfaces.
  • the electronic semiconductor chips 800 are arranged on the metal structures 400 in such a way that the contact side 802 faces the upper sides 401 of the metal structures 400 and each of the electrical contact surfaces is electrically connected to one of the metal structures 400 via a solder contact 810 or another electrically conductive connection.
  • the electronic semiconductor chips 800 can be, for example, optoelectronic semiconductor chips.
  • the electronic semiconductor chips 800 can be, for example, light-emitting diode chips (LED chips).
  • the electronic semiconductor chips 800 can also be other electronic or optoelectronic semiconductor chips.
  • Figure 24 shows a schematic sectional side view of the carrier 100 after removal of the third photoresist mask 340.
  • the third photoresist mask 340 could also have been removed before the deposition of the coating 440 or before the arrangement of the electronic semiconductor chips 800.
  • first grid structure 500 is not removed when removing the third photoresist mask 340.
  • Figure 25 shows a schematic sectional side view of the carrier 100 after forming a second grid structure 550 that delimits the electronic semiconductor chips 800.
  • the second grid structure 550 has been formed from a photoresist.
  • the second grid structure 550 has walls 560 that are arranged on the walls 510 of the first grid structure 500.
  • the walls 560 of the second grid structure 550 delimit cells 570 that are arranged above the cells 520 of the first grid structure 500.
  • One of the electronic semiconductor chips 800 is arranged in each cell 570 of the second grid structure 550.
  • the walls 560 of the second grid structure 550 protrude beyond the electronic semiconductor chips 800 arranged above the metal structures 400 in a direction perpendicular to the top side 101 of the carrier 100.
  • the second grid structure 550 has an upper side 551 which faces away from the upper side 501 of the first grid structure 500.
  • FIG. 26 shows a schematic sectional side view of the carrier 100 after arranging an encapsulation material 650 in the cells 570 of the second grid structure 550.
  • the electronic semiconductor chips 800 have been embedded in the encapsulation material 650.
  • the encapsulation material 650 extends beyond the cells 570 of the second grid structure 550, so that a part 660 of the encapsulation material 650 covers the top side 551 of the second grid structure 550.
  • the encapsulation material 650 can comprise, for example, a silicone. If the electronic semiconductor chips 800 are designed as light-emitting optoelectronic semiconductor chips 800, it is expedient if the encapsulation material 650 is permeable to light emitted by the electronic semiconductor chips 800. In this case, the encapsulation material 650 can also comprise embedded wavelength-converting particles.
  • the capsule material 650 may, for example, have been arranged in the cells 570 of the second lattice structure 550 by a molding process.
  • Figure 27 shows a schematic sectional side view of the carrier 100 after removal of the part 660 of the capsule material 650 covering the second grid structure 550.
  • the part 660 of the capsule material 650 covering the second grid structure 550 has been completely removed such that the upper side 551 of the second grid structure 550 is now accessible on an upper side 651 of the capsule material 650.
  • the removal of the part 660 of the capsule material 650 covering the second grid structure 500 can be carried out, for example, before the capsule material 650 hardens, for example by wet blasting.
  • the removal of the covering part 660 can also be carried out by sandblasting, grinding, etching or by means of a laser beam.
  • the capsule material 650 can be removed before the removal of the covering part 660 may have been either partially or completely hardened.
  • the location-dependent exposure can be carried out, for example, by a laser beam. If the electronic semiconductor chips 800 are designed as light-emitting optoelectronic semiconductor chips 800, a location-dependent exposure of the encapsulation material 650 can also be carried out by operating the electronic semiconductor chips 800.
  • the capsule material 650 is also possible to arrange the capsule material 650 in the cells 570 of the second grid structure 550 in such a way that the second grid structure 550 is not covered at all, but remains accessible at the top 651 of the capsule material 650. In this case, the capsule material 650 is therefore only arranged in the cells 570 and does not cover the top 551 of the second grid structure 550.
  • Figure 28 shows a schematic sectional side view of the carrier 100 after removal of the first grid structure 500 and the second grid structure 550.
  • electronic components 10 formed in the cells 520, 570 of the first grid structure 500 and the second grid structure 550 have been exposed.
  • a plasma process may optionally be carried out.
  • connection sections 270 of the first seed layer 250 which are now exposed on the upper side 111 of the release layer 110, have been removed, for example by means of an etching process.
  • the removal of the connecting sections 270 can also be omitted.
  • the connecting sections 270 can be connection sections 270 may, for example, break off by themselves during the subsequent processing step.
  • Figure 29 shows a schematic sectional side view of the electronic components 10 after detachment from the release layer 110.
  • the detachment from the carrier 100 and the release layer 110 can be carried out, for example, with the aid of one or more films.
  • the processing of the isolated electronic components 10 can be completed in the processing state shown in Figure 29.
  • the electronic components 10 are light-emitting optoelectronic components.
  • the electronic components 10 can have very compact external dimensions and can be produced cost-effectively in large quantities using the method described above.
  • the release layer 110 it is not necessary for the release layer 110 to be electrically conductive. However, if the release layer 110 is designed to be electrically conductive, the method can be simplified in the manner described below.
  • the production of the first seed layer 250 using the first seed layer production mask 200 described with reference to Figures 3 to 6 can be dispensed with.
  • Figure 30 shows a schematic sectional side view of the carrier 100 with the release layer 110 arranged on the upper side 101 of the carrier 100.
  • the release layer 110 is in this case electrically conductive.
  • the first photoresist mask 300 has been formed on the upper side 111 of the release layer 110.
  • the processing status shown in Figure 30 thus corresponds to that of Figure 7, but with the difference that in the processing status of Figure 30 no first Seed layer 250 with first seed surfaces 260 and connecting sections 270 is present.
  • the top side 111 of the release layer 110 is exposed in the openings 310 of the first photoresist mask 300.
  • the electrically conductive release layer 110 serves as an electrode.
  • the processing status then reached corresponds to that of Figure 8. The process is then continued as described above.
  • Figure 31 shows a schematic sectional side view of a processing stage in a further variant of the method described above.
  • the processing stage shown in Figure 31 corresponds to that in Figure 27.
  • the encapsulation material 650 arranged in the cells 570 of the second grid structure 550 does not completely fill the cells 570 in this variant.
  • the amount of encapsulation material 650 introduced into the cells 570 of the second grid structure 550 has been dimensioned such that the electronic semiconductor chips 800 arranged in the cells are embedded in the encapsulation material 650, but the outer sides 801 of the electronic semiconductor chips 800 are not covered by the encapsulation material 650.
  • the top side 651 of the encapsulation material 650 and the outer sides 801 of the electronic semiconductor chips 800 are approximately flush with one another in the example shown.
  • the fill level of the encapsulation material 650 arranged in the cells 570 of the second grid structure 550 could also be selected differently.
  • a cover layer 670 has been arranged in the cells 570.
  • the cover layer 670 fills the remaining space after the introduction of the capsule material 650. Free space in the cells 570 in the example shown is completely filled. However, it would also be possible that the cover layer 670 does not yet completely fill the cells 570 of the second grid structure 550. It is also possible that the material of the cover layer 670 initially covers the top side 551 of the second grid structure 550. In this case, the material of the cover layer 670 is then removed until the top side 551 of the second grid structure 550 is accessible again. This can be done, for example, as described above with reference to Figures 26 and 27 for the capsule material 650.
  • the material of the cover layer 670 can differ from the encapsulation material 650. It is also possible that the encapsulation material 650 and the material of the cover layer 670 have the same base material, for example a silicone, and different fillers. This can be particularly useful if the electronic semiconductor chips 800 are designed as light-emitting optoelectronic semiconductor chips.
  • the capsule material 650 has a light-absorbing or light-reflecting filler, for example a filler that contains TiO2.
  • the cover layer 670 is completely transparent or has embedded wavelength-converting particles.
  • the capsule material 650 is transparent or has embedded wavelength-converting particles, while the cover layer 670 is light-absorbing or light-reflecting.
  • the construction materials obtainable by the process can be elements 10, light emission can only occur in a lateral direction, while light emitted on the outside 801 of the electronic semiconductor chip 800 is reflected or absorbed by the cover layer 670.
  • Figure 32 shows a schematic sectional side view of a still unfinished processing stage during implementation of a further variant of the method described above.
  • the processing stage shown in Figure 32 follows the processing stage described with reference to Figure 25.
  • a molding tool 900 has been arranged above the upper side 551 of the second lattice structure 550, which molding tool has sections that protrude into the cells 570 of the second lattice structure 550 and divide each cell 570 into an outer region 910 and an inner region 920.
  • the electronic semiconductor chips 800 arranged in the cells 570 of the second lattice structure 550 are located in the inner regions 920.
  • the inner regions 920 and the outer regions 910 are sealed off from one another by the molding tool 900.
  • Figure 33 shows a schematic sectional side view of a processing stage following Figure 32.
  • a molding material that forms cavity walls 960 has been arranged by a molding process.
  • the molding material that forms the cavity walls 960 can, for example, be designed to reflect light.
  • the molding material that forms the cavity walls 960 can comprise a silicone and light-reflecting particles embedded therein, for example particles that comprise TiCt.
  • Figure 34 shows a schematic sectional side view of a processing stage following the representation in Figure 33.
  • the mold 900 has been removed. This exposes cavities 950 delimited by the cavity walls 960.
  • each cell 570 of the second A cavity 950 has been formed in the lattice structure 550.
  • the respective electronic semiconductor chip 800 is arranged in the cavity 950.
  • the cavity wall 960 that borders the cavity 950 has the shape of a reflector, for example the shape of a paraboloid of revolution.
  • the capsule material 650 was arranged in the cavities 950 formed in the cells 570 of the second lattice structure 550.
  • the part 660 of the capsule material 650 covering the upper side 551 of the second lattice structure 550 can be removed, as described with reference to Figures 26 and 27. In this way, the processing status shown in Figure 35 is achieved. Further processing then takes place as described above with reference to Figures 28 and 29.
  • the base areas 525 of the cells 520 of the first grid structure 500 are rectangular.
  • the cells 570 of the second grid structure 550 are essentially identical ( Figure 25).
  • the potting material 600 and the encapsulation material 650 of the finished electronic components 10 also have a rectangular shape when viewed from above.
  • the second grid structure 550 is always formed such that the cells 570 of the second grid structure 550 have a base area 525 that is as similar as possible to the cells 520 of the first grid structure 500.
  • Figure 36 shows a schematic view of cells 520 of the first grid structure 500 with a circular disk-shaped (circular) base area 525.
  • Figure 37 shows cells 520 with a triangular base area 525.
  • Figure 38 shows cells 520 with a hexagonal base area 525.
  • Figure 39 shows cells 520 with an L-shaped base area 525.
  • Figure 40 shows an example in which different cells 520 of the first grid structure 500 have different base areas 525.
  • the base area 525 of some cells 520 is larger than the base area 525 of other cells 520 of the first grid structure 500.
  • some of the cells 520 have a rectangular base area 525, while other cells 520 have a square base area 525.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé de production de composants électroniques comprenant les étapes consistant à fournir un support ayant une couche de libération disposée au niveau d'un côté supérieur, pour former une pluralité de structures métalliques sur la couche de libération, pour former une première structure de grille composée d'une résine photosensible sur la couche de libération, ladite première structure de grille délimitant les structures métalliques, pour agencer un matériau d'enrobage dans des cellules de la première structure de grille, les structures métalliques étant incorporées dans le matériau d'enrobage, pour compléter les structures métalliques par une couche de structure élevée sur un côté supérieur du matériau d'enrobage, pour agencer une pluralité de puces à semi-conducteur électroniques sur les structures métalliques, pour former une seconde structure de grille composée d'une résine photosensible, ladite seconde structure de grille délimitant les puces à semi-conducteur électroniques, pour agencer un matériau d'encapsulation dans des cellules de la seconde structure de grille, les puces à semi-conducteur électroniques étant incorporées dans le matériau d'encapsulation, pour retirer la première structure de grille et la seconde structure de grille afin d'exposer les composants électroniques formés dans les cellules de la première structure de grille et de la seconde structure de grille, et pour libérer les composants électroniques de la couche de libération.
PCT/EP2023/084538 2022-12-12 2023-12-06 Procédé de production de composants électroniques WO2024126206A1 (fr)

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DE102022133000.1A DE102022133000A1 (de) 2022-12-12 2022-12-12 Verfahren zum herstellen elektronischer bauelemente

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014060355A2 (fr) * 2012-10-17 2014-04-24 Osram Opto Semiconductors Gmbh Procédé de fabrication d'une pluralité de composants optoélectroniques à semi-conducteurs
US20170062382A1 (en) * 2014-02-20 2017-03-02 Osram Opto Semiconductors Gmbh Production of optoelectronic components
US20170222094A1 (en) * 2014-08-05 2017-08-03 Osram Opto Semiconductors Gmbh Electronic Component, Optoelectronic Component, Component Arrangement, and Method for Producing an Electronic Component
DE102022133000A1 (de) 2022-12-12 2024-06-13 Ams-Osram International Gmbh Verfahren zum herstellen elektronischer bauelemente

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Publication number Priority date Publication date Assignee Title
DE102014112540A1 (de) 2014-09-01 2016-03-03 Osram Opto Semiconductors Gmbh Optoelektronisches Bauteil
DE102017126338A1 (de) 2017-11-10 2019-05-16 Osram Opto Semiconductors Gmbh Bauteilverbund, Bauteil und Verfahren zur Herstellung von Bauteilen
DE102021104189A1 (de) 2021-02-22 2022-08-25 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Sensorvorrichtung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014060355A2 (fr) * 2012-10-17 2014-04-24 Osram Opto Semiconductors Gmbh Procédé de fabrication d'une pluralité de composants optoélectroniques à semi-conducteurs
US20170062382A1 (en) * 2014-02-20 2017-03-02 Osram Opto Semiconductors Gmbh Production of optoelectronic components
US20170222094A1 (en) * 2014-08-05 2017-08-03 Osram Opto Semiconductors Gmbh Electronic Component, Optoelectronic Component, Component Arrangement, and Method for Producing an Electronic Component
DE102022133000A1 (de) 2022-12-12 2024-06-13 Ams-Osram International Gmbh Verfahren zum herstellen elektronischer bauelemente

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