WO2024120188A1 - 等效电容的确定方法及计算机设备 - Google Patents

等效电容的确定方法及计算机设备 Download PDF

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WO2024120188A1
WO2024120188A1 PCT/CN2023/133098 CN2023133098W WO2024120188A1 WO 2024120188 A1 WO2024120188 A1 WO 2024120188A1 CN 2023133098 W CN2023133098 W CN 2023133098W WO 2024120188 A1 WO2024120188 A1 WO 2024120188A1
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matrix
capacitance
target
initial
inductance
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PCT/CN2023/133098
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English (en)
French (fr)
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赵汇海
夏天
陈建军
吴沣
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阿里巴巴达摩院(杭州)科技有限公司
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Publication of WO2024120188A1 publication Critical patent/WO2024120188A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/60—Quantum algorithms, e.g. based on quantum optimisation, quantum Fourier or Hadamard transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers

Definitions

  • the present invention relates to the field of quantum technology, and in particular to a method for determining equivalent capacitance and a computer device.
  • the embodiments of the present invention provide a method for determining an equivalent capacitance and a computer device to at least solve the technical problem of inaccurate determination of the equivalent capacitance of a Fluxonium quantum bit in the related art.
  • a method for determining an equivalent capacitance comprising: determining the Hamiltonian of a full circuit of a Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting a plurality of Josephson junctions in series, the plurality of Josephson junctions correspond to a plurality of modes, the Hamiltonian comprises a capacitance coupling term and an inductance coupling term, wherein the capacitance coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to the mode, and the inductance coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to the mode; transforming the initial capacitance matrix to obtain a first capacitance matrix in which non-diagonal elements of the first row and the first column are all zero; removing the first
  • transforming the initial capacitance matrix to obtain a first capacitance matrix whose first row and first column non-diagonal elements are all zero includes: constructing a second transformation matrix, wherein the initial inductance matrix remains unchanged under the action of the second transformation matrix; transforming the initial capacitance matrix by the second transformation matrix to obtain a first row and first column non-diagonal elements.
  • the first capacitance matrix has diagonal elements all being zero.
  • the obtaining of the first transformation matrix for diagonalizing the target inductance matrix includes: obtaining a first transformation submatrix for setting the non-diagonal elements of the first row and the first column in the target inductance matrix to zero; obtaining a second transformation submatrix for setting the non-diagonal elements of the second row and the second column in the target inductance matrix to zero; performing operations in sequence until obtaining an nth transformation submatrix for setting the non-diagonal elements of the nth row and the nth column in the target inductance matrix to zero, wherein n*n is the dimension of the target inductance matrix; and multiplying the first transformation submatrix, the second transformation submatrix, and until the nth transformation submatrix to obtain the first transformation matrix.
  • determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix includes: obtaining a target matrix element corresponding to the last row and last column in an inverse matrix of the target capacitance matrix; and determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element.
  • determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element includes: determining the reciprocal of the target matrix element as the equivalent capacitance of the Fluxonium quantum bit.
  • the method further includes: determining the initial capacitance matrix in the following manner: determining the parasitic capacitance of multiple Josephson junctions in the Josephson junction array, the parallel capacitance of the single Josephson junction, and the capacitance to ground of the mode corresponding nodes, wherein the number of mode corresponding nodes included in the Josephson junction array is the number of modes plus one; constructing the initial capacitance matrix based on the parasitic capacitance, the parallel capacitance and the capacitance to ground.
  • the method further includes: determining the initial inductance matrix by: obtaining the linear inductance of the plurality of Josephson junctions connected in series in the Josephson junction array; and constructing the initial inductance matrix with the first row and the first column both being zero based on the linear inductance.
  • the equivalent capacitance of the Fluxonium quantum bit after determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, it also includes: detecting whether the obtained equivalent capacitance is the target equivalent capacitance; when the detection result is that the obtained equivalent capacitance is not the target equivalent capacitance, adjusting the design parameters of the size and position of the two superconducting metal plates of the single Josephson junction in the Fluxonium quantum bit for multiple times until the obtained equivalent capacitance is the target equivalent capacitance, and determining that the design parameters corresponding to the equivalent capacitance being the target equivalent capacitance are the design parameters of the size and position of the two superconducting metal plates.
  • a method for determining an equivalent capacitance comprising: displaying a Fluxonium quantum bit and an equivalent capacitance determination control on a display interface, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting a plurality of Josephson junctions in series, the plurality of Josephson junctions correspond to a plurality of modes, the Hamiltonian of the Fluxonium quantum bit comprises a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to the mode, and the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to the mode; in response to an operation on the equivalent capacitance determination control, obtaining the equivalent capacitance of the Fluxonium quantum bit, wherein,
  • a method for determining an equivalent capacitance comprising: determining the Hamiltonian of a circuit corresponding to a Fluxonium quantum bit, wherein the Hamiltonian comprises a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to a mode, wherein the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to a mode, wherein a plurality of Josephson junctions in parallel with a capacitor and a single Josephson junction in the Fluxonium quantum bit correspond to a plurality of modes; obtaining a target capacitance matrix based on the initial inductance matrix and the initial capacitance matrix, wherein in the target capacitance matrix; determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix.
  • obtaining a target capacitance matrix based on the initial inductance matrix and the initial capacitance matrix includes: acquiring a first transformation matrix based on the initial inductance matrix; and obtaining the target capacitance matrix based on the initial capacitance matrix and the first transformation matrix.
  • obtaining a first transformation matrix based on the initial inductance matrix includes: removing the first row and first column of the initial inductance matrix which are all zero to obtain a target inductance matrix; and obtaining the first transformation matrix for diagonalizing the target inductance matrix.
  • obtaining the target capacitance matrix based on the initial capacitance matrix and the first transformation matrix includes: transforming the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and first column are all zero; removing the first row and first column of the first capacitance matrix to obtain a second capacitance matrix; and applying the first transformation matrix to the second capacitance matrix to obtain a target capacitance matrix.
  • determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix includes: obtaining a target matrix element corresponding to the last row and last column in an inverse matrix of the target capacitance matrix; and determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element.
  • a computer-readable storage medium is further provided, wherein the computer-readable storage medium includes a stored program, wherein when the program is run, the method for determining the equivalent capacitance described in any one of the above-mentioned devices where the computer-readable storage medium is located is controlled.
  • a computer device comprising: a memory and a processor, wherein the memory stores a computer program; and the processor is used to execute the computer program stored in the memory, wherein when the computer program is run, the processor executes any one of the above-mentioned methods for determining equivalent capacitance.
  • the initial capacitance matrix in the capacitance coupling term in the Hamiltonian is transformed to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero.
  • Matrix remove the first row and first column in the first capacitance matrix to obtain the second capacitance matrix, and remove the first row and first column in the initial inductance matrix that are all zero to obtain the target inductance matrix, delete the meaningless mode (i.e., free mode) in the Hamiltonian, can simplify the dimension of the capacitance matrix in the Hamiltonian, and the dimension of the inductance matrix, and effectively reduce the complexity of subsequent transformation calculations.
  • the non-diagonal influence of the target inductance matrix is transferred to other items of the Hamiltonian, for example, on the second capacitance matrix, the perturbation of the capacitance by other circuit devices (inductors) in the Fluxonium quantum bit can be fully considered, thereby making the equivalent capacitance determined based on the second capacitance matrix more accurate.
  • FIG1 shows a hardware structure block diagram of a computer terminal for implementing a method for determining equivalent capacitance
  • FIG2 is a flow chart of a first method for determining equivalent capacitance according to Embodiment 1 of the present invention
  • FIG. 3 is a flow chart of a second method for determining equivalent capacitance according to Embodiment 1 of the present invention.
  • FIG. 4 is a flow chart of a third method for determining equivalent capacitance according to Embodiment 1 of the present invention.
  • FIG5 is a schematic diagram of a chip design layout of a Fluxonium quantum bit according to an optional embodiment of the present invention.
  • FIG6 is a schematic diagram of a full circuit model of a Fluxonium qubit provided according to an optional embodiment of the present invention.
  • FIG7 is a schematic diagram of an equivalent circuit model of a Fluxonium quantum bit provided according to an optional embodiment of the present invention.
  • FIG8 is a framework diagram of a first device for determining equivalent capacitance according to an embodiment of the present invention.
  • FIG. 9 is a framework diagram of a second device for determining equivalent capacitance according to an embodiment of the present invention.
  • FIG. 10 is a framework diagram of a third device for determining equivalent capacitance according to an embodiment of the present invention.
  • FIG. 11 is a structural block diagram of a computer device according to an embodiment of the present invention.
  • a qubit In a classical mechanics system, the state of a qubit is unique, while quantum mechanics allows a qubit to be a superposition of two states at the same time, which is the basic property of quantum computing. Physically speaking, a qubit is a quantum state, so a qubit has the properties of a quantum state. Due to the unique quantum properties of a quantum state, a qubit has many characteristics that are different from classical bits, which is one of the basic characteristics of quantum information science.
  • Fluxonium bit A superconducting quantum bit consisting of a capacitor, a Josephson junction, and an inductor connected in parallel.
  • Josephson junction A superconductor-insulator-superconductor (SIS) sandwich structure, in which the superconducting Cooper pairs in the superconductor at one end can tunnel through the interlayer insulator to the superconductor at the other end.
  • the tunneling phenomenon of the Josephson junction exhibits lossless and nonlinear inductance, and is therefore used as the core component of superconducting quantum bits.
  • Josephson junction parasitic capacitance In addition to nonlinear inductance, the Josephson junction also has a relatively large capacitance, which is called parasitic capacitance, because the insulating layer between the two layers of superconductors is relatively thin (usually a few nanometers thick).
  • a method embodiment of a method for determining equivalent capacitance is also provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.
  • FIG. 1 shows a hardware structure block diagram of a computer terminal for implementing a method for determining equivalent capacitance.
  • the computer terminal 10 may include one or more processors (102a, 102b, ..., 102n are used in the figure to illustrate that the processor may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device for a communication function.
  • a processing device such as a microprocessor MCU or a programmable logic device FPGA
  • the computer terminal 10 may also include: a display, an input/output interface (I/O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and/or a camera.
  • I/O interface input/output interface
  • USB universal serial bus
  • the structure shown in Figure 1 is only for illustration and does not limit the structure of the above-mentioned electronic device.
  • the computer terminal 10 may also include more or fewer components than those shown in Figure 1, or have a configuration different from that shown in Figure 1.
  • the one or more processors and/or other data processing circuits described above may generally be referred to herein as "data processing circuits".
  • the data processing circuits may be embodied in whole or in part as software, hardware, firmware, or any combination thereof.
  • the data processing circuits may be a single independent processing module, or may be integrated in whole or in part into a computer. Any one of the other components in the terminal 10.
  • the data processing circuit acts as a processor control (eg, selection of a variable resistance terminal path connected to an interface).
  • the memory 104 can be used to store software programs and modules of application software, such as the program instructions/data storage device corresponding to the method for determining equivalent capacitance in the embodiment of the present invention.
  • the processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, realizing the vulnerability detection method of the above-mentioned application program.
  • the memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the transmission device is used to receive or send data via a network.
  • the specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 10.
  • the transmission device includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device can be a radio frequency (Radio Frequency, RF) module, which is used to communicate with the Internet wirelessly.
  • RF Radio Frequency
  • the display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 .
  • LCD liquid crystal display
  • the computer device shown in Figure 1 above may include hardware elements (including circuits), software elements (including computer codes stored on computer-readable media), or a combination of hardware elements and software elements. It should be noted that Figure 1 is only an example of a specific specific example and is intended to illustrate the types of components that may be present in the above-mentioned computer device.
  • the computer device shown in FIG. 1 above has a touch display (also referred to as a "touch screen” or a “touch display screen”).
  • the computer device shown in FIG. 1 above has a graphical user interface (GUI), and a user can perform human-computer interaction with the GUI through finger contact and/or gestures on the surface of the touch screen.
  • GUI graphical user interface
  • the human-computer interaction functions here optionally include the following interactions: creating web pages, drawing, word processing, making electronic documents, games, video conferencing, instant messaging, sending and receiving emails, call interfaces, playing digital videos, playing digital music and/or web browsing, etc.
  • the executable instructions for executing the above human-computer interaction functions are configured/stored in a computer program product or a computer-readable storage medium executable by one or more processors.
  • FIG2 is a flow chart of a method for determining equivalent capacitance according to Embodiment 1 of the present invention. As shown in FIG2, the method for determining equivalent capacitance provided in the embodiment of the present application can be implemented by the following steps:
  • Step S202 determining the Hamiltonian of the full circuit of the Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes.
  • the Hamiltonian of the Fluxonium quantum bit It includes capacitive coupling terms and inductive coupling terms, wherein the capacitive coupling terms are represented by the charge operator of the initial capacitance matrix and the mode corresponding node, and the inductive coupling terms are represented by the flux operator of the initial inductance matrix and the mode corresponding node;
  • the execution subject of the above-mentioned method for determining the equivalent capacitance of a quantum bit can be a terminal or a server.
  • the terminal can be of various types, for example, a fixed computer or a mobile terminal, and the mobile terminal can also be of various types, for example, a mobile phone, a pad, etc.
  • the server can be a single computer or a computer group including multiple computers, etc.
  • the Hamiltonian of the full circuit of the Fluxonium quantum bit can be characterized in a variety of different ways depending on the factors considered. For example, when considering the equivalent capacitance of the Fluxonium quantum bit, the inductance of the series-connected Josephson junction can be approximated as a linear inductance.
  • the Hamiltonian of the full circuit of the Fluxonium quantum bit can be written as the sum of the following energy terms: the energy term corresponding to the capacitance, the energy term corresponding to the inductance, and the energy term of a single Josephson junction, wherein, since the equivalent capacitance of the full circuit of the Fluxonium quantum bit is considered, that is, the above capacitance includes: the parasitic capacitance of each Josephson junction connected in series, the capacitance to ground of each Josephson junction connected in series, and the parallel capacitance in the Fluxonium quantum bit, therefore, the energy terms involved in the capacitance include: the sub-energy terms corresponding to the parasitic capacitance of each Josephson junction connected in series, the sub-energy terms corresponding to the capacitance to ground of each Josephson junction connected in series, and the sub-energy terms of the parallel capacitance in the Fluxonium quantum bit.
  • the several energy terms included in the Hamiltonian of the full circuit of the above-mentioned Fluxonium quantum bit can be characterized in a variety of ways. For example, a combination of multiple physical quantity parameters can be selected for characterization. For example, for the independent capacitance and inductance in the full circuit of the Fluxonium quantum bit, the matrices and operators corresponding to the capacitance and inductance can be used to characterize them respectively.
  • the above-mentioned Hamiltonian can include capacitive coupling terms and inductive coupling terms, wherein the capacitive coupling terms are characterized by the charge operator of the initial capacitance matrix and the mode corresponding node, and the inductive coupling terms are characterized by the flux operator of the initial inductance matrix and the mode corresponding node.
  • the multiple Josephson junctions connected in series in the Fluxonium quantum bit correspond to multiple modes. When multiple Josephson junctions are connected in series, one end point of the first Josephson junction in series corresponds to the zeroth node, and the other end corresponds to the first node.
  • the second Josephson junction is connected through the first node, and so on..., when N j Josephson junctions are connected in series, one end point of the N j Josephson junction corresponds to the N j -1th node, and the other end corresponds to the N jth node.
  • the above-mentioned initial capacitance matrix and initial inductance matrix can be constructed based on the above-mentioned nodes.
  • the initial capacitance matrix can be determined by: determining the parasitic capacitance of multiple Josephson junctions in the Josephson junction array, the parallel capacitance of a single Josephson junction, and the capacitance to ground of the mode corresponding node, wherein the number of mode corresponding nodes included in the Josephson junction array is the number of modes plus one; constructing the initial capacitance matrix based on the parasitic capacitance, the parallel capacitance, and the capacitance to ground.
  • the initial capacitance matrix is constructed by considering all capacitance types of the entire circuit of the Fluxonium quantum bit. Since the complete capacitance effect is taken into account, the subsequent calculation of the equivalent capacitance based on the initial capacitance matrix is also more accurate, so that the equivalent capacitance obtained is more accurate.
  • multiple methods may be used, for example, by: Method to determine the initial inductance matrix: obtain the linear inductance of multiple Josephson junctions connected in series in the Josephson junction array; based on the linear inductance, construct an initial inductance matrix with zero in the first row and first column.
  • Method to determine the initial inductance matrix obtain the linear inductance of multiple Josephson junctions connected in series in the Josephson junction array; based on the linear inductance, construct an initial inductance matrix with zero in the first row and first column.
  • Step S204 transforming the initial capacitance matrix to obtain a first capacitance matrix in which all non-diagonal elements in the first row and first column are zero;
  • the initial capacitance matrix is transformed to obtain a first capacitance matrix whose first row and first column non-diagonal elements are all zero, including: constructing a second transformation matrix, wherein the initial inductance matrix remains unchanged under the action of the second transformation matrix; transforming the second transformation matrix on the initial capacitance matrix to obtain a first capacitance matrix whose first row and first column non-diagonal elements are all zero.
  • the initial inductance matrix can be constructed as a matrix whose first row and first column are both zero based on demand
  • the second transformation matrix constructed for transforming the initial capacitance matrix into a first capacitance matrix whose first row and first column non-diagonal elements are all zero can be a matrix that has no effect on the initial inductance matrix.
  • Step S206 removing the first row and first column of the first capacitance matrix to obtain a second capacitance matrix, and removing the first row and first column of the initial inductance matrix which are all zero to obtain a target inductance matrix;
  • the first row and first column in the first capacitance matrix are removed to obtain the second capacitance matrix, and the first row and first column in the initial inductance matrix are removed to obtain the target inductance matrix, that is, the first row and first column in the first capacitance matrix are directly deleted, and the first row and first column in the initial inductance matrix are directly deleted.
  • the second capacitance matrix obtained after deleting the first row and first column has significantly fewer dimensions relative to the first capacitance matrix
  • the target inductance matrix obtained after deleting the first row and first column has significantly fewer dimensions relative to the initial inductance matrix, which effectively reduces the amount of subsequent calculations.
  • Step S208 obtaining a first transformation matrix for diagonalizing the target inductance matrix
  • the first transformation matrix may not be a matrix, but may be the result of a series of continuous matrices.
  • the following method may be used: obtain a first transformation submatrix for setting the non-diagonal elements of the first row and the first column in the target inductance matrix to zero; obtain a second transformation submatrix for setting the non-diagonal elements of the second row and the second column in the target inductance matrix to zero; operate sequentially until obtaining the nth transformation submatrix for setting the non-diagonal elements of the nth row and the nth column in the target inductance matrix to zero, where n*n is the dimension of the target inductance matrix; multiply the first transformation submatrix, the second transformation submatrix, and the nth transformation submatrix to obtain the first transformation matrix. That is, through the above method, the above first transformation matrix is effectively obtained by multiplying multiple continuous transformation submatrices.
  • Step S210 applying the first transformation matrix to the second capacitance matrix to obtain a target capacitance matrix
  • Step S212 determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix.
  • determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix includes: obtaining the target matrix element corresponding to the last row and last column in the inverse matrix of the target capacitance matrix; based on the target matrix
  • determining the equivalent capacitance of the Fluxonium qubit includes: determining the inverse of the target matrix element as the equivalent capacitance of the Fluxonium qubit.
  • the equivalent capacitance of the Fluxonium quantum bit after determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, it also includes: detecting whether the obtained equivalent capacitance is the target equivalent capacitance; when the detection result is that the obtained equivalent capacitance is not the target equivalent capacitance, adjusting the design parameters of the size and position of the two superconducting metal plates of the single Josephson junction in the Fluxonium quantum bit for many times until the obtained equivalent capacitance is the target equivalent capacitance, and determining that the design parameters corresponding to the equivalent capacitance being the target equivalent capacitance are the design parameters of the size and position of the two superconducting metal plates. .
  • the above processing is used to effectively realize the design of the Fluxonium quantum bit. Since the above method for determining the equivalent capacitance does not have any conditional restrictions on the device, the above method is used for the design of the Fluxonium quantum bit and has a certain universality.
  • the initial capacitance matrix in the capacitance coupling term in the Hamiltonian is transformed to obtain a first capacitance matrix in which the non-diagonal elements of the first row and column are all zero, the first row and first column in the first capacitance matrix are removed to obtain a second capacitance matrix, and the first row and first column in the initial inductance matrix are removed to obtain a target inductance matrix, and the meaningless mode (i.e., free mode) in the Hamiltonian is deleted, which can simplify the dimension of the capacitance matrix in the Hamiltonian and the dimension of the inductance matrix, and effectively reduce the complexity of subsequent transformation calculations.
  • the meaningless mode i.e., free mode
  • the first transformation matrix that diagonalizes the target inductance matrix is applied to the second capacitance matrix, so that the non-diagonal influence of the target inductance matrix is transferred to other terms of the Hamiltonian, for example, the second capacitance matrix, and the perturbation of the capacitance by other circuit devices (inductors) in the Fluxonium quantum bit can be fully considered, thereby making the equivalent capacitance determined based on the second capacitance matrix more accurate.
  • FIG3 is a flow chart of a second method for determining equivalent capacitance according to Embodiment 1 of the present application.
  • the method for determining equivalent capacitance provided in the embodiment of the present application can be implemented by the following steps:
  • Step S302 displaying the Fluxonium quantum bit and the equivalent capacitance determination control on the display interface, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes.
  • the Hamiltonian of the Fluxonium quantum bit includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the mode corresponding node, and the inductive coupling term is characterized by the initial inductance matrix and the flux operator of the mode corresponding node;
  • Step S304 in response to the operation of the equivalent capacitance determination control, obtaining the equivalent capacitance of the Fluxonium quantum bit, wherein the equivalent capacitance is obtained based on the target capacitance matrix, and the target capacitance matrix is obtained by transforming the second capacitance matrix by the first transformation matrix.
  • the first capacitance matrix is obtained by transforming the first row and the first column of the first capacitance matrix, the non-diagonal elements of the first row and the first column of the first capacitance matrix are all zero, the first capacitance matrix is obtained by transforming the initial capacitance matrix, the first transformation matrix is a matrix that diagonalizes the target inductance matrix, and the target inductance matrix is a matrix obtained by removing the first row and the first column of the initial inductance matrix;
  • Step S306 displaying the equivalent capacitance on the display interface.
  • a Fluxonium quantum bit and an equivalent capacitance of the Fluxonium quantum bit are displayed on a display interface, wherein, after determining the Hamiltonian of the entire circuit of the Fluxonium quantum bit, the initial capacitance matrix in the capacitance coupling term in the Hamiltonian is transformed to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero, the first row and the first column of the first capacitance matrix are removed to obtain a second capacitance matrix, and the first row and the first column of the initial inductance matrix that are all zero are removed to obtain a target inductance matrix, and the meaningless modes (i.e., free modes) in the Hamiltonian are deleted, so that the dimensions of the capacitance matrix and the inductance matrix in the Hamiltonian can be simplified, and the complexity of subsequent transformation calculations can be effectively reduced.
  • the meaningless modes i.e., free modes
  • the non-diagonal influence of the target inductance matrix is transferred to other items of the Hamiltonian.
  • the perturbation of the capacitance by other circuit devices (inductors) in the Fluxonium quantum bit can be fully considered, thereby making the equivalent capacitance determined based on the second capacitance matrix more accurate.
  • the display interface is used to display the determination process of the Fluxonium quantum bit and the equivalent capacitance of the Fluxonium quantum bit, so that the visualization of the process is realized, and the effect of improving the user experience is achieved.
  • FIG4 is a flow chart of method 3 for determining equivalent capacitance according to embodiment 1 of the present application.
  • the method for determining equivalent capacitance provided in the embodiment of the present application can be implemented by the following steps:
  • Step S402 determining the Hamiltonian of the circuit corresponding to the Fluxonium quantum bit, wherein the Hamiltonian includes a capacitive coupling term and an inductive coupling term, the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the mode corresponding node, the inductive coupling term is characterized by the initial inductance matrix and the flux operator of the mode corresponding node, and the multiple Josephson junctions in parallel with the capacitor and the single Josephson junction in the Fluxonium quantum bit correspond to multiple modes;
  • Step S404 obtaining a target capacitance matrix based on the initial inductance matrix and the initial capacitance matrix
  • Step S406 determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix.
  • the target capacitance matrix is determined based on the Hamiltonian of the circuit corresponding to the Fluxonium quantum bit, and based on the initial capacitance matrix and the initial inductance matrix in the Hamiltonian, and the equivalent capacitance of the Fluxonium quantum bit is determined based on the target capacitance matrix.
  • the equivalent capacitance is determined based on the large capacitance associated with the Fluxonium quantum bit, the accuracy of the equivalent capacitance of the Fluxonium quantum bit is effectively improved.
  • the technical processing adopted by the method for determining equivalent capacitance can adopt the above-mentioned equivalent capacitance.
  • the initial capacitance matrix and the initial inductance matrix can be constructed based on the above similar methods.
  • the target capacitance matrix is a capacitance matrix transformed from the initial capacitance matrix, and the equivalent capacitance of the Fluxonium quantum bit can be directly read from the target capacitance matrix.
  • the transformation from the initial capacitance matrix to the target capacitance matrix can be a matrix simplification process, for example, deleting some meaningless coupling terms, etc. Through the matrix simplification process, not only a simplified target capacitance matrix can be obtained, but also the matrix calculation process for matrix transformation is simpler and less error-prone.
  • the initial capacitance matrix and the initial inductance matrix are combined to describe the entire Hamiltonian, so the transformation of the initial capacitance matrix and the transformation of the initial inductance matrix are adaptive.
  • the first transformation matrix can be obtained based on the initial inductance matrix; and the target capacitance matrix can be obtained based on the initial capacitance matrix and the first transformation matrix.
  • the following method when obtaining the first transformation matrix based on the initial inductance matrix, the following method can be used: remove the first row and first column of the initial inductance matrix that are all zero to obtain the target inductance matrix; obtain the first transformation matrix for diagonalizing the target inductance matrix.
  • the target inductance matrix can also be effectively simplified when it is subsequently diagonalized, thereby improving processing efficiency.
  • the conversion of inductance coupling is effectively achieved, so that the equivalent capacitance in the entire Hamiltonian is more intuitively reflected in the capacitance matrix.
  • a target capacitance matrix is obtained, including: transforming the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero; removing the first row and the first column in the first capacitance matrix to obtain a second capacitance matrix; applying the first transformation matrix to the second capacitance matrix to obtain a target capacitance matrix.
  • the first row and the first column of the initial capacitance matrix may be removed first, and before removing the first row and the first column of the initial capacitance matrix, to ensure accuracy, the initial capacitance matrix may be transformed first, that is, the matrix elements of the first row and the first column in the initial capacitance matrix are converted to zero.
  • the first transformation matrix obtained above is used to act on the obtained capacitance matrix to obtain the desired target capacitance matrix, effectively achieving the purpose of accurately representing the equivalent capacitance of the target capacitance matrix.
  • the equivalent capacitance of a Fluxonium qubit when determining the equivalent capacitance of a Fluxonium qubit based on a target capacitance matrix, the equivalent capacitance of a Fluxonium qubit can be directly read out based on the target capacitance matrix. For example, the target matrix element corresponding to the last row and last column of the inverse matrix of the target capacitance matrix can be first obtained; based on the target matrix element, the equivalent capacitance of the Fluxonium qubit is determined. When determining the equivalent capacitance of a Fluxonium qubit based on the target matrix element, the reciprocal of the target matrix element is determined as the equivalent capacitance.
  • the capacitance of a fluxonium qubit is about 10 to 20 fF. In a typical layout design, most of this capacitance is provided by two close superconducting metal plates. In addition, the parasitic capacitance of the Josephson junction also contributes several fF. Capacitance. In addition to the parasitic capacitance of the series Josephson junctions that constitute the Fluxonium equivalent inductance, each junction contributes about 0.01-0.1fF to other circuit elements, and the total capacitance contribution of hundreds of junctions is also about fF, which cannot be ignored. In this optional implementation, a method for accurately determining the Fluxonium bit capacitance through full-layout simulation is proposed.
  • the size of the components that need to be simulated in the entire layout ranges from micrometers to hundreds of micrometers, spanning more than two orders of magnitude, and the amount of calculation is large. Therefore, in this optional implementation, the surface integral equation method is used for fast simulation.
  • the Fluxonium full circuit model has symmetry, that is, each Josephson junction in series is the same, the capacitance to ground is also the same, and the capacitance between the junction and the metal plate of the bit is ignored.
  • the circuit model is obtained from the simulation of the entire layout, and there is no need to assume any symmetry or uniformity, which can more accurately describe the bit capacitance obtained by the general layout design.
  • FIG5 is a schematic diagram of a chip design layout of a Fluxonium quantum bit according to an optional embodiment of the present invention.
  • the oblique line portion of the figure is an insulator substrate, and the other portion is a superconductor.
  • the intersection of two mutually perpendicular dark strips near the center of the figure is a small Josephson junction.
  • the ring composed of squares and thin wires in the lower middle is a series-connected Josephson junction, which provides the inductance of the Fluxonium quantum bit, wherein each square is a Josephson junction.
  • the ground plane is composed of superconducting metal surrounding the bit, and is not drawn here for the sake of simplicity.
  • FIG6 is a schematic diagram of a full circuit model of a Fluxonium quantum bit provided according to an optional embodiment of the present invention. As shown in FIG6 , each Josephson junction connected in series is approximately a parallel connection of a linear inductor and a parasitic capacitance of the junction.
  • the inductance of the Fluxonium quantum bit is generally composed of a series of Josephson junctions.
  • the series-connected Josephson junctions are large in size and large in number, so the nonlinear effect of each junction is weak, and it can be approximately regarded as a series connection of several linear inductors.
  • the Josephson energy of each Josephson junction in series is expressed as E JA . If a linear approximation is made, the corresponding linear inductance is
  • each Josephson junction is represented by CA.
  • ⁇ ext is the external magnetic flux passing through the Josephson junction loop. Represents the flux operator at each node.
  • the capacitance and inductance matrices after removal are expressed as
  • Mode N J corresponds to the Fluxonium qubit mode. Ignoring other modes except mode N J in equation (2), the Fluxonium equivalent Hamiltonian is obtained
  • FIG7 is a schematic diagram of an equivalent circuit model of a Fluxonium qubit provided according to an optional embodiment of the present invention.
  • the simplification from equation (2) to equation (3) corresponds to the simplification from the full circuit model of FIG6 to the equivalent circuit model of FIG7 . Therefore, the equivalent capacitance of the circuit model of FIG7 can be obtained as
  • the electrostatic field simulation is first performed on the Fluxonium quantum bit chip design layout to obtain the Fluxonium full circuit model, and then a series of equivalent transformations are constructed to separate the equivalent Hamiltonian corresponding to the bit pattern, and finally the capacitance of the Fluxonium quantum bit is extracted from the Hamiltonian. The entire process accurately determines the Fluxonium bit capacitance from the actual layout design.
  • the entire layout of the Fluxonium quantum bit chip is simulated by using the surface integral equation method. Since it is necessary to simulate micrometer-scale Josephson junctions and other superconducting elements of several hundred micrometers, spanning more than two orders of magnitude, the calculation is relatively complex.
  • the surface integral equation method divides the system into two-dimensional grids, which is less computationally intensive than the finite element method of three-dimensional grid division, and the calculation results are also more accurate.
  • the actual Fluxonium full circuit model is obtained by electrostatic field simulation, and then an equivalent transformation is constructed to extract the capacitance of the Fluxonium quantum bit.
  • This method is applicable to general chip layout design and does not require the assumption of any symmetry and uniformity, so that the capacitance of the quantum bit can be accurately determined.
  • the uniformity of the series Josephson junction is assumed, that is, each junction is exactly the same and the capacitance to the ground is also the same, while the capacitance of each junction to the ground in the actual layout design is different. Therefore, a more accurate bit capacitance can be obtained by using the method of this optional implementation.
  • the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method.
  • the technical solution of the present invention, or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a computer-readable storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of various embodiments of the present invention.
  • a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk
  • a terminal device which can be a mobile phone, a computer, a server, or a network device, etc.
  • FIG. 7 is a framework diagram of the device for determining equivalent capacitance according to an embodiment of the present invention.
  • the device includes: a first determining module 802, a first processing module 804, a second processing module 806, a first acquiring module 808, a third processing module 810 and a second determining module 812. They are described below.
  • the first determination module 802 is used to determine the Hamiltonian of the full circuit of the Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes.
  • the Hamiltonian of the Fluxonium quantum bit includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the node corresponding to the mode, and the inductive coupling term is characterized by the initial inductance matrix and the flux operator of the node corresponding to the mode;
  • the first processing module 804 is connected to the above-mentioned first determination module 802, and is used to transform the initial capacitance matrix, A first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero is obtained;
  • a second processing module 806 is connected to the first processing module 804, and is used to remove the first row and the first column in the first capacitance matrix to obtain a second capacitance matrix, and to remove the first row and the first column in the initial inductance matrix that are all zero to obtain a target inductance matrix;
  • a first acquisition module 808 is connected to the second processing module 806, and is
  • first determination module 802, first processing module 804, second processing module 806, first acquisition module 808, third processing module 810 and second determination module 812 correspond to steps S202 to S212 in Example 1, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1. It should be noted that the above-mentioned modules as part of the device can be run in the computer terminal 10 provided in Example 1.
  • FIG. 9 is a framework diagram of the device for determining equivalent capacitance 2 according to an embodiment of the present invention. As shown in FIG. 9 , the device includes: a first display module 902, a second acquisition module 904, and a second display module 906. The following are described respectively.
  • the first display module 902 is used to display the Fluxonium quantum bit and the equivalent capacitance determination control on the display interface, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and multiple Josephson junctions correspond to multiple modes.
  • the Hamiltonian of the Fluxonium quantum bit includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the node corresponding to the mode, and the inductive coupling term is characterized by the flux operator of the initial inductance matrix and the node corresponding to the mode;
  • the second acquisition module 904 is connected to the first display module 902, and is used
  • the equivalent capacitance of the Fluxonium quantum bit is obtained, wherein the equivalent capacitance is obtained based on the target capacitance matrix, the target capacitance matrix is obtained by transforming the second capacitance matrix by the first transformation matrix, the second capacitance matrix is the matrix obtained by removing the first row and first column of the first capacitance matrix, the non-diagonal elements of the first row and first column of the first capacitance matrix are all zero, the first capacitance matrix is obtained by transforming the initial capacitance matrix, the first transformation
  • first display module 902, the second acquisition module 904 and the second display module 906 correspond to steps S302 to S306 in Example 1, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1. It should be noted that the above-mentioned modules as part of the device can be run in the computer terminal 10 provided in Example 1.
  • FIG. 10 is a framework diagram of the device for determining equivalent capacitance three according to an embodiment of the present invention. As shown in FIG. 10 , the device includes: a third determining module 1002, a fourth processing module 1004 and a fourth determining module 1006. They are described below respectively.
  • the third determination module 1002 is used to determine the Hamiltonian of the circuit corresponding to the Fluxonium quantum bit, wherein the Hamiltonian includes a capacitive coupling term and an inductive coupling term, the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the mode corresponding node, the inductive coupling term is characterized by the initial inductance matrix and the flux operator of the mode corresponding node, and the multiple Josephson junctions in the Fluxonium quantum bit connected in parallel with the capacitor and the single Josephson junction correspond to multiple modes; the fourth processing module 1004 is connected to the third determination module 1002, and is used to obtain a target capacitance matrix based on the initial inductance matrix and the initial capacitance matrix; the fourth determination module 1006 is connected to the fourth processing module 1004, and is used to determine the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix.
  • the Hamiltonian includes a capacitive coupling term and an inductive coupling term, the capacitive
  • the third determination module 1002, the fourth processing module 1004 and the third determination module 1006 correspond to steps S402 to S406 in Example 1, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above-mentioned Example 1. It should be noted that the above-mentioned modules, as part of the device, can be run in the computer terminal 10 provided in Example 1.
  • the embodiment of the present invention further provides a computer-readable storage medium.
  • the computer-readable storage medium can be used to store the program code executed by the method for determining equivalent capacitance provided in the first embodiment.
  • the computer-readable storage medium may be located in any one of the computer terminals in a computer terminal group in a computer network, or in any one of the mobile terminals in a mobile terminal group.
  • the computer-readable storage medium is configured to store program codes for performing the following steps: determining the Hamiltonian of the full circuit of the Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes, and the Hamiltonian includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to the mode, and the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to the mode; transforming the initial capacitance matrix to obtain a first capacitance matrix in which all non-diagonal elements of the first row and first column are zero; removing the first row and first column of the first capacitance matrix to obtain a second capac
  • the computer-readable storage medium is also configured to store program code for executing the following steps: transforming the initial capacitance matrix to obtain a first capacitance matrix whose first row and first column non-diagonal elements are all zero, including: constructing a second transformation matrix, wherein the initial inductance matrix remains unchanged under the action of the second transformation matrix; transforming the initial capacitance matrix by the second transformation matrix to obtain a first capacitance matrix whose first row and first column non-diagonal elements are all zero.
  • the computer-readable storage medium is further configured to store program codes for executing the following steps: obtaining a first transformation matrix for diagonalizing the target inductance matrix, including: obtaining a first transformation matrix for diagonalizing the target inductance matrix; A first transformation submatrix for setting the first row and first column non-diagonal elements in the target inductance matrix to zero is obtained; a second transformation submatrix for setting the second row and second column non-diagonal elements in the target inductance matrix to zero is obtained; operations are performed sequentially until an nth transformation submatrix for setting the nth row and nth column non-diagonal elements in the target inductance matrix to zero is obtained, wherein n*n is the dimension of the target inductance matrix; the first transformation submatrix, the second transformation submatrix, and the nth transformation submatrix are multiplied together to obtain a first transformation matrix.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, including: obtaining the target matrix element corresponding to the last row and last column in the inverse matrix of the target capacitance matrix; determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element, including: determining the reciprocal of the target matrix element as the equivalent capacitance of the Fluxonium quantum bit.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: determining an initial capacitance matrix in the following manner: determining the parasitic capacitance of multiple Josephson junctions in a Josephson junction array, the parallel capacitance of a single Josephson junction, and the capacitance to ground of mode-corresponding nodes, wherein the number of mode-corresponding nodes included in the Josephson junction array is the number of modes plus one; constructing an initial capacitance matrix based on the parasitic capacitance, the parallel capacitance, and the capacitance to ground.
  • the computer-readable storage medium is also configured to store program code for executing the following steps: determining an initial inductance matrix by: obtaining the linear inductance of multiple Josephson junctions connected in series in a Josephson junction array; and constructing an initial inductance matrix with zero first row and first column based on the linear inductance.
  • the computer-readable storage medium is also configured to store program code for executing the following steps: after determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, it also includes: detecting whether the obtained equivalent capacitance is the target equivalent capacitance; when the detection result is that the obtained equivalent capacitance is not the target equivalent capacitance, adjusting the design parameters of the size and position of the two superconducting metal plates of a single Josephson junction in the Fluxonium quantum bit for multiple times until the obtained equivalent capacitance is the target equivalent capacitance, and determining that the design parameters corresponding to the equivalent capacitance being the target equivalent capacitance are the design parameters of the size and position of the two superconducting metal plates.
  • the computer-readable storage medium is configured to store program code for performing the following steps: displaying a Fluxonium quantum bit and an equivalent capacitance determination control on a display interface, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes, and the Hamiltonian includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to the mode, and the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to the mode; in response to an operation on the equivalent capacitance determination control, obtaining the equivalent capacitance of the Fluxonium quantum bit, wherein the equivalent capacitance is obtained based on a target capacitance matrix, and
  • the first capacitance matrix is obtained by transforming the first row and first column of the target inductance matrix, and the non-diagonal elements of the first row and first column of the first capacitance matrix are all zero.
  • the first capacitance matrix is obtained by transforming the initial capacitance matrix.
  • the first transformation matrix is the matrix that diagonalizes the target inductance matrix.
  • the target inductance matrix is the matrix obtained by removing the first row and first column of the initial inductance matrix.
  • the equivalent capacitance is displayed on the display interface.
  • the computer-readable storage medium is configured to store program code for performing the following steps: determining the Hamiltonian of the circuit corresponding to the Fluxonium quantum bit, wherein the Hamiltonian includes a capacitive coupling term and an inductive coupling term, the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to a mode, and the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to a mode, and multiple Josephson junctions in parallel with a capacitor and a single Josephson junction in the Fluxonium quantum bit correspond to multiple modes; based on the initial inductance matrix and the initial capacitance matrix, a target capacitance matrix is obtained, wherein in the target capacitance matrix; determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: obtaining a target capacitance matrix based on an initial inductance matrix and an initial capacitance matrix, including: obtaining a first transformation matrix based on the initial inductance matrix; obtaining a target capacitance matrix based on the initial capacitance matrix and the first transformation matrix.
  • the computer-readable storage medium is also configured to store program code for executing the following steps: based on the initial inductance matrix, obtaining a first transformation matrix, including: removing the first row and first column of the initial inductance matrix that are all zero to obtain a target inductance matrix; obtaining a first transformation matrix for diagonalizing the target inductance matrix.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: based on the initial capacitance matrix and the first transformation matrix, a target capacitance matrix is obtained, including: transforming the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and first column are all zero; removing the first row and first column of the first capacitance matrix to obtain a second capacitance matrix; applying the first transformation matrix to the second capacitance matrix to obtain a target capacitance matrix.
  • the computer-readable storage medium is also configured to store program code for performing the following steps: determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, including: obtaining the target matrix element corresponding to the last row and last column in the inverse matrix of the target capacitance matrix; determining the equivalent capacitance of the Fluxonium quantum bit based on the target matrix element.
  • the embodiment of the present invention may provide a computer device, which may be any computer terminal device in a computer terminal group.
  • the computer terminal may also be replaced by a terminal device such as a mobile terminal.
  • the computer device may be located in at least one network device among a plurality of network devices of a computer network.
  • the computer device can execute the program code of the following steps in the method for determining the equivalent inductance of the application program: determining the Hamiltonian of the full circuit of the Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor, and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, the multiple Josephson junctions correspond to multiple modes, and the Hamiltonian includes a capacitive coupling term and an inductive coupling term.
  • the capacitance coupling term is characterized by the charge operator of the initial capacitance matrix and the node corresponding to the mode, and the inductance coupling term is characterized by the flux operator of the initial inductance matrix and the node corresponding to the mode;
  • the initial capacitance matrix is transformed to obtain a first capacitance matrix whose non-diagonal elements of the first row and the first column are all zero;
  • the first row and the first column of the first capacitance matrix are removed to obtain a second capacitance matrix, and the first row and the first column of the initial inductance matrix are removed to obtain a target inductance matrix;
  • a first transformation matrix for diagonalizing the target inductance matrix is obtained;
  • the first transformation matrix is applied to the second capacitance matrix to obtain a target capacitance matrix; and the equivalent capacitance of the Fluxonium quantum bit is determined based on the target capacitance matrix.
  • Fig. 11 is a structural block diagram of a computer device according to an embodiment of the present invention.
  • the computer device may include: one or more (only one is shown in the figure) processors 1102, a memory 1104, etc.
  • the memory 1104 may be used to store software programs and modules, such as program instructions/modules corresponding to the search processing method and device in the embodiment of the present invention.
  • the processor 1102 executes various functional applications and data processing by running the software programs and modules stored in the memory 1104, that is, the above-mentioned search processing method is realized.
  • the memory 1104 may include a high-speed random access memory 1104, and may also include a non-volatile memory 1104, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory 1104.
  • the memory 1104 may further include a memory 1104 remotely arranged relative to the processor 1102, and these remote memories 1104 may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • the processor 1102 can call the information and application stored in the memory 1104 through the transmission device to perform the following steps: determine the Hamiltonian of the full circuit of the Fluxonium quantum bit, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes, and the Hamiltonian includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by an initial capacitance matrix and a charge operator of a node corresponding to the mode, and the inductive coupling term is characterized by an initial inductance matrix and a flux operator of a node corresponding to the mode; transform the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero; remove the first row and the first column of the first capacitance matrix to obtain a
  • the processor 1102 can also call the information and application stored in the memory 1104 through the transmission device to perform the following steps: transform the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero, including: constructing a second transformation matrix, wherein the initial inductance matrix remains unchanged under the action of the second transformation matrix; transforming the initial capacitance matrix with the second transformation matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero.
  • the processor 1102 may also call the information and application program stored in the memory 1104 through the transmission device to perform the following steps: obtaining a first transformation matrix for diagonalizing the target inductance matrix, including: obtaining a first transformation submatrix for setting the first row and first column non-diagonal elements in the target inductance matrix to zero; obtaining a second transformation submatrix for setting the second row and second column non-diagonal elements in the target inductance matrix to zero; and sequentially performing operations until obtaining a first transformation submatrix for diagonalizing the target inductance matrix.
  • nth transformation submatrix with the nth row and nth column non-diagonal elements set to zero, wherein n*n is the dimension of the target inductance matrix; the first transformation submatrix, the second transformation submatrix, and finally the nth transformation submatrix are multiplied to obtain the first transformation matrix.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: determine the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, including: obtaining the target matrix element corresponding to the last row and last column in the inverse matrix of the target capacitance matrix; based on the target matrix element, determine the equivalent capacitance of the Fluxonium quantum bit.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: based on the target matrix element, determine the equivalent capacitance of the Fluxonium quantum bit, including: determine the reciprocal of the target matrix element as the equivalent capacitance of the Fluxonium quantum bit.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: determine the initial capacitance matrix in the following manner: determine the parasitic capacitance of multiple Josephson junctions in the Josephson junction array, the parallel capacitance of a single Josephson junction, and the capacitance to ground of the mode corresponding nodes, wherein the number of mode corresponding nodes included in the Josephson junction array is the number of modes plus one; construct an initial capacitance matrix based on the parasitic capacitance, the parallel capacitance and the capacitance to ground.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: determine the initial inductance matrix by: obtaining the linear inductance of multiple Josephson junctions connected in series in the Josephson junction array; based on the linear inductance, construct an initial inductance matrix with the first row and the first column both being zero.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: after determining the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, it also includes: detecting whether the obtained equivalent capacitance is the target equivalent capacitance; when the detection result is that the obtained equivalent capacitance is not the target equivalent capacitance, adjusting the design parameters of the size and position of the two superconducting metal plates of a single Josephson junction in the Fluxonium quantum bit for multiple times until the obtained equivalent capacitance is the target equivalent capacitance, and determining that the design parameters corresponding to the equivalent capacitance being the target equivalent capacitance are the design parameters of the size and position of the two superconducting metal plates.
  • the processor 1102 can call the information and application stored in the memory 1104 through the transmission device to perform the following steps: display the Fluxonium quantum bit and the equivalent capacitance determination control on the display interface, wherein the full circuit of the Fluxonium quantum bit is formed by a Josephson junction array, a capacitor and a single Josephson junction in parallel, the Josephson junction array is obtained by connecting multiple Josephson junctions in series, and the multiple Josephson junctions correspond to multiple modes, and the Hamiltonian includes a capacitive coupling term and an inductive coupling term, wherein the capacitive coupling term is characterized by the charge operator of the initial capacitance matrix and the node corresponding to the mode, and the inductive coupling term is characterized by the flux operator of the initial inductance matrix and the node corresponding to the mode; in response to the operation of the equivalent capacitance determination control, the equivalent capacitance of the Fluxonium quantum bit is obtained, wherein the equivalent capacitance is obtained based on the target capacitance matrix, the target capacitance matrix is
  • the processor 1102 can call the information and application stored in the memory 1104 through the transmission device to perform the following steps: determine the Hamiltonian of the circuit corresponding to the Fluxonium quantum bit, wherein the Hamiltonian includes a capacitive coupling term and an inductive coupling term, the capacitive coupling term is represented by the charge operator of the initial capacitance matrix and the mode corresponding node, the inductive coupling term is represented by the initial inductance matrix and the flux operator of the mode corresponding node, and the multiple Josephson junctions in the Fluxonium quantum bit connected in parallel with the capacitor and the single Josephson junction correspond to multiple modes; based on the initial inductance matrix and the initial capacitance matrix, a target capacitance matrix is obtained, wherein in the target capacitance matrix; based on the target capacitance matrix, the equivalent capacitance of the Fluxonium quantum bit is determined.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: based on the initial inductance matrix and the initial capacitance matrix, obtain the target capacitance matrix, including: based on the initial inductance matrix, obtain the first transformation matrix; based on the initial capacitance matrix and the first transformation matrix, obtain the target capacitance matrix.
  • the processor 1102 can also call the information and application stored in the memory 1104 through the transmission device to perform the following steps: based on the initial inductance matrix, obtain a first transformation matrix, including: removing the first row and first column of the initial inductance matrix that are all zero to obtain a target inductance matrix; obtain a first transformation matrix for diagonalizing the target inductance matrix.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: based on the initial capacitance matrix and the first transformation matrix, obtain the target capacitance matrix, including: transforming the initial capacitance matrix to obtain a first capacitance matrix in which the non-diagonal elements of the first row and the first column are all zero; removing the first row and the first column of the first capacitance matrix to obtain a second capacitance matrix; applying the first transformation matrix to the second capacitance matrix to obtain the target capacitance matrix.
  • the processor 1102 can also call the information and application programs stored in the memory 1104 through the transmission device to perform the following steps: determine the equivalent capacitance of the Fluxonium quantum bit based on the target capacitance matrix, including: obtaining the target matrix element corresponding to the last row and last column in the inverse matrix of the target capacitance matrix; based on the target matrix element, determine the equivalent capacitance of the Fluxonium quantum bit.
  • FIG. 11 is for illustration only, and the computer terminal may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a palm computer, a mobile Internet device (Mobile Internet Devices, MID), a PAD, and other terminal devices.
  • FIG. 11 does not limit the structure of the above-mentioned electronic device.
  • the computer terminal may also include more or fewer components (such as a network interface, a display device, etc.) than those shown in FIG. 11, or have a configuration different from that shown in FIG. 11.
  • a person of ordinary skill in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the hardware related to the terminal device through a program, and the program may be stored in a computer-readable storage medium, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.
  • a computer-readable storage medium which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, etc.
  • the disclosed technical content can be implemented in other ways.
  • the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present invention in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a computer-readable storage medium, including a number of instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the various embodiments of the present invention.
  • the aforementioned computer-readable storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

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Abstract

本发明公开了一种等效电容的确定方法及计算机设备。其中，该方法涉及量子技术领域，包括：确定Fluxonium量子比特的全电路的哈密顿量，哈密顿量包括电容耦合项和电感耦合项；对电容耦合项中的初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉电感耦合项中的初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；基于目标电容矩阵确定Fluxonium量子比特的等效电容。本发明解决了在相关技术中，存在Fluxonium量子比特的等效电容确定不精确的技术问题。

Description

等效电容的确定方法及计算机设备
本申请要求于2022年12月07日提交中国专利局、申请号为202211565904.X、申请名称为“等效电容的确定方法及计算机设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及量子技术领域，具体而言，涉及一种等效电容的确定方法及计算机设备。
背景技术
在相关技术中，Fluxonium量子比特的电容大部分由两个靠近的超导金属板提供，但基于此部分电容确定Fluxonium量子比特的比特电容是比较粗糙的，无法对Fluxonium量子比特的设计提供有益帮助。
因此，在相关技术中，存在Fluxonium量子比特的等效电容确定不精确的问题。
针对上述的问题，目前尚未提出有效的解决方案。
发明内容
本发明实施例提供了一种等效电容的确定方法及计算机设备，以至少解决在相关技术中，存在Fluxonium量子比特的等效电容确定不精确的技术问题。
根据本发明实施例的一个方面，提供了一种等效电容的确定方法，包括：确定Fluxonium量子比特的全电路的哈密顿量，其中，所述Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，所述约瑟夫森结阵列由多个约瑟夫森结串联得到，所述多个约瑟夫森结对应多个模式，所述哈密顿量包括电容耦合项和电感耦合项，其中，所述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉所述第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉所述初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将所述目标电感矩阵对角化的第一变换矩阵；将所述第一变换矩阵作用于所述第二电容矩阵，得到目标电容矩阵；基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容。
可选地，所述对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵，包括：构造第二变换矩阵，其中，所述初始电感矩阵在所述第二变换矩阵的作用下保持不变；将所述第二变换矩阵作对所述初始电容矩阵进行变换，得到首行首列的非 对角元均为零的所述第一电容矩阵。
可选地，所述获取用于将所述目标电感矩阵对角化的第一变换矩阵，包括：获取用于将所述目标电感矩阵中的第一行第一列非对角元置零的第一变换子矩阵；获取用于将所述目标电感矩阵中的第二行第二列非对角元置零的第二变换子矩阵；依次操作，直到得到用于将所述目标电感矩阵中的第n行第n列非对角元置零的第n变换子矩阵，其中，n*n为所述目标电感矩阵的维数；将所述第一变换子矩阵，第二变换子矩阵，直到所述第n变换子矩阵连乘，得到所述第一变换矩阵。
可选地，所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容，包括：获取所述目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容。
可选地，所述基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容，包括：确定所述目标矩阵元的倒数为所述Fluxonium量子比特的所述等效电容。
可选地，所述方法还包括：通过以下方式，确定所述初始电容矩阵：确定所述约瑟夫森结阵列中多个约瑟夫森结的寄生电容，以及所述单个约瑟夫森结的并联电容，以及所述模式对应节点的对地电容，其中，所述约瑟夫森结阵列中包括的模式对应节点的数量为模式数量加一；基于所述寄生电容，所述并联电容以及所述对地电容，构造所述初始电容矩阵。
可选地，所述方法还包括：通过以下方式，确定所述初始电感矩阵：获取所述约瑟夫森结阵列中串联的所述多个约瑟夫森结的线性电感；基于所述线性电感，构造首行和首列均为零的所述初始电感矩阵。
可选地，在所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容之后，还包括：检测得到的等效电容是否为目标等效电容；在检测结果为得到的所述等效电容不为所述目标等效电容的情况下，多次调整Fluxonium量子比特中所述单个约瑟夫森结的两个超导金属板的尺寸和位置的设计参数，直到得到的等效电容为所述目标等效电容，并确定等效电容为所述目标等效电容对应的设计参数为所述两个超导金属板的尺寸和位置的设计参数。
根据本发明的另一方面，提供了一种等效电容的确定方法，包括：在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，所述Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，所述约瑟夫森结阵列由多个约瑟夫森结串联得到，所述多个约瑟夫森结对应多个模式，所述Fluxonium量子比特的哈密顿量包括电容耦合项和电感耦合项，其中，所述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；响应于对所述等效电容确定控件的操作，获取所述Fluxonium量子比特的等效电容，其中， 所述等效电容基于目标电容矩阵得到，所述目标电容矩阵由第一变换矩阵对第二电容矩阵进行变换得到，所述第二电容矩阵为去掉第一电容矩阵中的首行首列后得到的矩阵，所述第一电容矩阵的首行首列的非对角元均为零，所述第一电容矩阵由所述初始电容矩阵进行变换得到，所述第一变换矩阵为将目标电感矩阵对角化的矩阵，所述目标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；在所述显示界面上显示所述等效电容。
根据本发明的还一方面，提供了一种等效电容的确定方法，包括：确定Fluxonium量子比特对应的电路的哈密顿量，其中，所述哈密顿量包括电容耦合项和电感耦合项，所述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，所述Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；基于所述初始电感矩阵和所述初始电容矩阵，得到目标电容矩阵，其中，所述目标电容矩阵中；基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容。
可选地，所述基于所述初始电感矩阵和所述初始电容矩阵，得到目标电容矩阵，包括：基于所述初始电感矩阵，获取第一变换矩阵；基于所述初始电容矩阵和所述第一变换矩阵，得到所述目标电容矩阵。
可选地，所述基于所述初始电感矩阵，获取第一变换矩阵，包括：去掉所述初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将所述目标电感矩阵对角化的所述第一变换矩阵。
可选地，所述基于所述初始电容矩阵和所述第一变换矩阵，得到所述目标电容矩阵，包括：对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉所述第一电容矩阵中的首行首列，得到第二电容矩阵；将所述第一变换矩阵作用于所述第二电容矩阵，得到目标电容矩阵。
可选地，所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容，包括：获取所述目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容。
根据本发明实施例的又一方面，还提供了一种计算机可读存储介质，所述计算机可读存储介质包括存储的程序，其中，在所述程序运行时控制所述计算机可读存储介质所在设备上述任意一项所述的等效电容的确定方法。
根据本发明实施例的还一方面，还提供了一种计算机设备，包括：存储器和处理器，所述存储器存储有计算机程序；所述处理器，用于执行所述存储器中存储的计算机程序，所述计算机程序运行时使得所述处理器执行上述任意一项所述的等效电容的确定方法。
在本发明实施例中，在确定Fluxonium量子比特的全电路的哈密顿量后，对哈密顿量中电容耦合项中的初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩 阵，去掉所述第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉所述初始电感矩阵中均为零的首行首列，得到目标电感矩阵，删除哈密顿量中无意义的模式(即自由模式)，能够简化哈密顿量中电容矩阵的维数，以及电感矩阵的维数，有效地降低后续变换计算的复杂度。另外，在得到目标电感矩阵和第二电容矩阵后，通过将目标电感矩阵对角化的第一变换矩阵作用于第二电容矩阵，实现了将目标电感矩阵的非对角影响转移到哈密顿的其它项，例如，第二电容矩阵上，能够完整地考虑Fluxonium量子比特中其它电路器件(电感)对电容的微扰，进而使得基于第二电容矩阵确定出的等效电容更为准确。通过上述处理，不仅能够解决相关技术中存在Fluxonium量子比特的等效电容确定不精确的问题，而且效率高，达到了实现确定Fluxonium量子比特的等效电容时，精度与效率兼顾的效果。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本申请的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1示出了一种用于实现等效电容的确定方法的计算机终端的硬件结构框图；
图2是根据本发明实施例1的等效电容的确定方法一的流程图；
图3是根据本发明实施例1的等效电容的确定方法二的流程图；
图4是根据本发明实施例1的等效电容的确定方法三的流程图；
图5是根据本发明可选实施方式的Fluxonium量子比特的芯片设计版图的示意图；
图6是根据本发明可选实施方式提供的Fluxonium量子比特的全电路模型的示意图；
图7是根据本发明可选实施方式提供的Fluxonium量子比特的等效电路模型的示意图；
图8是根据本发明实施例的等效电容的确定装置一的框架图；
图9是根据本发明实施例的等效电容的确定装置二的框架图；
图10是根据本发明实施例的等效电容的确定装置三的框架图；
图11是根据本发明实施例的一种计算机设备的结构框图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分的实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
需要说明的是，本发明的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的 数据在适当情况下可以互换，以便这里描述的本发明的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先，在对本申请实施例进行描述的过程中出现的部分名词或术语适用于如下解释：
量子比特，在经典力学系统中，一个比特的状态是唯一的，而量子力学允许量子比特是同一时刻两个状态的叠加，这是量子计算的基本性质。从物理上来说，量子比特就是量子态，因此，量子比特具有量子态的属性。由于量子态的独特量子属性，量子比特具有许多不同于经典比特的特征，这是量子信息科学的基本特征之一。
Fluxonium比特：一种超导量子比特，由并联的电容，约瑟夫森结，和电感构成。
约瑟夫森结(Josephson Junction)：一种超导体-绝缘体-超导体(SIS)的三明治结构，其中一端超导体中的超导库珀对可以穿过夹层绝缘体隧穿到另一端超导中。约瑟夫森结的隧穿现象表现出无损耗和非线性的电感，从而被用于超导量子比特的核心元件。
约瑟夫森结寄生电容：约瑟夫森结除了具有非线性的电感，由于两层超导体之间的绝缘层比较薄(一般几个纳米厚)，所以也具有比较大的电容，被称为寄生电容。
实施例1
根据本发明实施例，还提供了一种等效电容的确定方法的方法实施例，需要说明的是，在附图的流程图示出的步骤可以在诸如一组计算机可执行指令的计算机系统中执行，并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
本申请实施例1所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。图1示出了一种用于实现等效电容的确定方法的计算机终端的硬件结构框图。如图1所示，计算机终端10可以包括一个或多个处理器(图中采用102a、102b，……，102n来示出，处理器可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)、用于存储数据的存储器104、以及用于通信功能的传输装置。除此以外，还可以包括：显示器、输入/输出接口(I/O接口)、通用串行总线(USB)端口(可以作为BUS总线的端口中的一个端口被包括)、网络接口、电源和/或相机。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述电子装置的结构造成限定。例如，计算机终端10还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
应当注意到的是上述一个或多个处理器和/或其他数据处理电路在本文中通常可以被称为“数据处理电路”。该数据处理电路可以全部或部分的体现为软件、硬件、固件或其他任意组合。此外，数据处理电路可为单个独立的处理模块，或全部或部分的结合到计算 机终端10中的其他元件中的任意一个内。如本申请实施例中所涉及到的，该数据处理电路作为一种处理器控制(例如与接口连接的可变电阻终端路径的选择)。
存储器104可用于存储应用软件的软件程序以及模块，如本发明实施例中的等效电容的确定方法对应的程序指令/数据存储装置，处理器通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的应用程序的漏洞检测方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端10。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端10的通信供应商提供的无线网络。在一个实例中，传输装置包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
显示器可以例如触摸屏式的液晶显示器(LCD)，该液晶显示器可使得用户能够与计算机终端10的用户界面进行交互。
此处需要说明的是，在一些可选实施例中，上述图1所示的计算机设备可以包括硬件元件(包括电路)、软件元件(包括存储在计算机可读介质上的计算机代码)、或硬件元件和软件元件两者的结合。应当指出的是，图1仅为特定具体实例的一个实例，并且旨在示出可存在于上述计算机设备中的部件的类型。
此处需要说明的是，在一些实施例中，上述图1所示的计算机设备具有触摸显示器(也被称为“触摸屏”或“触摸显示屏”)。在一些实施例中，上述图1所示的计算机设备具有图像用户界面(GUI)，用户可以通过触摸屏表面上的手指接触和/或手势来与GUI进行人机交互，此处的人机交互功能可选的包括如下交互：创建网页、绘图、文字处理、制作电子文档、游戏、视频会议、即时通信、收发电子邮件、通话界面、播放数字视频、播放数字音乐和/或网络浏览等、用于执行上述人机交互功能的可执行指令被配置/存储在一个或多个处理器可执行的计算机程序产品或计算机可读存储介质中。
在上述运行环境下，本申请提供了如图2所示的一种可选的等效电容的确定方法的流程图。图2是根据本发明实施例1的等效电容的确定方法一的流程图。如图2所示，本申请实施例所提供的等效电容的确定方法可以通过如下步骤实现：
步骤S202，确定Fluxonium量子比特的全电路的哈密顿量，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，Fluxonium量子比特的哈密顿量 包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；
作为一种可选的实施例，上述量子比特的等效电容的确定方法的执行主体可以是一种终端，也可以是一种服务器。其中，终端的类型可以多种，例如，可以是固定计算机，也可以是移动终端，移动终端的类型也可以多种，比如，可以是手机，Pad等；服务器可以是单独的计算机，也可以是包括多个计算机的计算机群，等。
作为一种可选的实施例，Fluxonium量子比特的全电路的哈密顿量依据考虑的因素不同，可以有多种不同的表征方式。例如，当考虑Fluxonium量子比特的等效电容时，串联的约瑟夫森结的电感可以近似为线性电感。因此，基于上述考虑，可以将Fluxonium量子比特的全电路的哈密顿量可以写成以下几个能量项之和：电容对应的能量项，电感对应的能量项，以及单个约瑟夫森结的能量项，其中，由于考虑的是Fluxonium量子比特的全电路的等效电容，即上述电容包括：串联的各个约瑟夫森结的寄生电容,串联的各个约瑟夫森结的对地电容，以及Fluxonium量子比特中并联电容，因此，电容涉及的能量项包括：串联的各个约瑟夫森结的寄生电容对应的子能量项，串联的各个约瑟夫森结的对地电容对应的子能量项，Fluxonium量子比特中并联电容的子能量项。
作为一种可选的实施例，上述Fluxonium量子比特的全电路的哈密顿量所包括的几个能量项可以采用多种表征方式，例如，可以选择多种物理量参数的组合方式来表征，比如，针对Fluxonium量子比特的全电路中独立的电容和电感，可以分别采用分别与电容和电感对应的矩阵和算符来表征。例如，上述哈密顿量可以包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征。需要说明的是，Fluxonium量子比特中串联的多个约瑟夫森结对应多个模式，当多个约瑟夫森结串联起来时，以串联的第一个约瑟夫森结的一个端点对应第零节点，另一端对应第一节点，通过该第一节点连接第二个约瑟夫森结，以此类推......,当串联Nj个约瑟夫森结时，第Nj个约瑟夫森结的一个端点对应第Nj-1节点，另一端对应第Nj节点。其中，上述初始电容矩阵，以及初始电感矩阵均可以基于上述节点进行构建。
作为一种可选的实施例，确定初始电容矩阵时，可以采用多种方式，例如，通过以下方式，确定初始电容矩阵：确定约瑟夫森结阵列中多个约瑟夫森结的寄生电容，以及单个约瑟夫森结的并联电容，以及模式对应节点的对地电容，其中，约瑟夫森结阵列中包括的模式对应节点的数量为模式数量加一；基于寄生电容，并联电容以及对地电容，构造初始电容矩阵。采用上述处理，通过考虑Fluxonium量子比特的全电路所有电容类型构造初始电容矩阵，由于考虑了完整的电容影响，因此，后续基于该初始电容矩阵进行的等效电容的计算也更为精确，使得得到的等效电容更为精确。
作为一种可选的实施例，确定初始电感矩阵时，可以采用多种方式，例如，通过以下 方式，确定初始电感矩阵：获取约瑟夫森结阵列中串联的多个约瑟夫森结的线性电感；基于线性电感，构造首行和首列均为零的初始电感矩阵。在基于线性电感，构造首行和首列均为零的初始电感矩阵时，由于是计算Fluxonium量子比特的等效电容，因此，串联的多个约瑟夫森结的近似的线性电感，可以用作一个常数来简单，准确地构造首行和首列均为零的初始电感矩阵。
步骤S204，对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；
作为一种可选的实施例，对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵，包括：构造第二变换矩阵，其中，初始电感矩阵在第二变换矩阵的作用下保持不变；将第二变换矩阵作对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵。通过上述处理，由于初始电感矩阵基于需求，可以构造成首行和首列均为零的矩阵，因此，构造的用于将初始电容矩阵变换为首行首列的非对角元均为零的第一电容矩阵的第二变换矩阵，可以是对初始电感矩阵无作用的矩阵。
步骤S206，去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；
作为一种可选的实施例，去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵时，即将第一电容矩阵中的首行首列直接删除，以及将初始电感矩阵中均为零的首行首列直接删除。删除了首行首列后得到的第二电容矩阵相对于第一电容矩阵而言，维度明显少了，删除了首行首列后得到的目标电感矩阵相对于初始电感矩阵而言，维度也明显少了，有效地减少了后续的计算量。
步骤S208，获取用于将目标电感矩阵对角化的第一变换矩阵；
作为一种可选的实施例，上述第一变换矩阵可能不是一个矩阵，可以是一系列矩阵连续作用的结果，例如，获取用于将目标电感矩阵对角化的第一变换矩阵时，可以采用以下方式：获取用于将目标电感矩阵中的第一行第一列非对角元置零的第一变换子矩阵；获取用于将目标电感矩阵中的第二行第二列非对角元置零的第二变换子矩阵；依次操作，直到得到用于将目标电感矩阵中的第n行第n列非对角元置零的第n变换子矩阵，其中，n*n为目标电感矩阵的维数；将第一变换子矩阵，第二变换子矩阵，直到第n变换子矩阵连乘，得到第一变换矩阵。即通过上述方法，有效地实现通过多个连续变换子矩阵的连乘，得到上述第一变换矩阵。
步骤S210，将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；
步骤S212，基于目标电容矩阵确定Fluxonium量子比特的等效电容。
作为一种可选的实施例，基于目标电容矩阵确定Fluxonium量子比特的等效电容，包括：获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵 元，确定Fluxonium量子比特的等效电容。作为一种可选的实施例，基于目标矩阵元，确定Fluxonium量子比特的等效电容，包括：确定目标矩阵元的倒数为Fluxonium量子比特的等效电容。通过上述处理，基于从目标电容矩阵的逆矩阵中查找矩阵元的方式，方便，高效，精确地确定了Fluxonium量子比特的等效电容。
作为一种可选的实施例，在基于目标电容矩阵确定Fluxonium量子比特的等效电容之后，还包括：检测得到的等效电容是否为目标等效电容；在检测结果为得到的等效电容不为目标等效电容的情况下，多次调整Fluxonium量子比特中单个约瑟夫森结的两个超导金属板的尺寸和位置的设计参数，直到得到的等效电容为目标等效电容，并确定等效电容为目标等效电容对应的设计参数为两个超导金属板的尺寸和位置的设计参数。。采用上述处理，有效地实现了对Fluxonium量子比特的设计，由于上述确定等效电容的方法对器件并没有任何的条件限制，因此，上述方法用于Fluxonium量子比特的设计，具备一定的普适性。
在本发明实施例中，在确定Fluxonium量子比特的全电路的哈密顿量后，对哈密顿量中电容耦合项中的初始电容矩阵进行变换，得到行首列的非对角元均为零的第一电容矩阵，去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵，删除哈密顿量中无意义的模式(即自由模式)，能够简化哈密顿量中电容矩阵的维数，以及电感矩阵的维数，有效地降低后续变换计算的复杂度。另外，在得到目标电感矩阵和第二电容矩阵后，通过将目标电感矩阵对角化的第一变换矩阵作用于第二电容矩阵，实现了将目标电感矩阵的非对角影响转移到哈密顿的其它项，例如，第二电容矩阵上，能够完整地考虑Fluxonium量子比特中其它电路器件(电感)对电容的微扰，进而使得基于第二电容矩阵确定出的等效电容更为准确。通过上述处理，不仅能够解决相关技术中存在Fluxonium量子比特的等效电容确定不精确的问题，而且效率高，达到了实现确定Fluxonium量子比特的等效电容时，精度与效率兼顾的效果。
本申请提供了如图3所示的一种可选的等效电容的确定方法的流程图。图3是根据本发明实施例1的等效电容的确定方法二的流程图。如图3所示，本申请实施例所提供的等效电容的确定方法可以通过如下步骤实现：
步骤S302，在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，Fluxonium量子比特的哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；
步骤S304，响应于对等效电容确定控件的操作，获取Fluxonium量子比特的等效电容，其中，等效电容基于目标电容矩阵得到，目标电容矩阵由第一变换矩阵对第二电容矩阵进 行变换得到，第二电容矩阵为去掉第一电容矩阵中的首行首列后得到的矩阵，第一电容矩阵的首行首列的非对角元均为零，第一电容矩阵由初始电容矩阵进行变换得到，第一变换矩阵为将目标电感矩阵对角化的矩阵，目标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；
步骤S306，在显示界面上显示等效电容。
在本发明实施例中，通过在显示界面上显示Fluxonium量子比特，以及该Fluxonium量子比特的等效电容，其中，在确定Fluxonium量子比特的全电路的哈密顿量后，对哈密顿量中电容耦合项中的初始电容矩阵进行变换，得到行首列的非对角元均为零的第一电容矩阵，去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵，删除哈密顿量中无意义的模式(即自由模式)，能够简化哈密顿量中电容矩阵的维数，以及电感矩阵的维数，有效地降低后续变换计算的复杂度。另外，在得到目标电感矩阵和第二电容矩阵后，通过将目标电感矩阵对角化的第一变换矩阵作用于第二电容矩阵，实现了将目标电感矩阵的非对角影响转移到哈密顿的其它项，例如，第二电容矩阵上，能够完整地考虑Fluxonium量子比特中其它电路器件(电感)对电容的微扰，进而使得基于第二电容矩阵确定出的等效电容更为准确。通过上述处理，不仅能够解决在相关技术中，存在Fluxonium量子比特的等效电容确定不精确的技术问题，而且效率高，达到了实现确定Fluxonium量子比特的等效电容时，精度与效率兼顾的效果。通过上述处理，采用显示界面展示Fluxonium量子比特以及Fluxonium量子比特的等效电容的确定过程，实现了流程的可视化，达到了提升用户体验的效果。
本申请提供了如图4所示的一种可选的等效电容的确定方法的流程图。图4是根据本发明实施例1的等效电容的确定方法三的流程图。如图4所示，本申请实施例所提供的等效电容的确定方法可以通过如下步骤实现：
步骤S402，确定Fluxonium量子比特对应的电路的哈密顿量，其中，哈密顿量包括电容耦合项和电感耦合项，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；
步骤S404，基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵；
步骤S406，基于目标电容矩阵确定Fluxonium量子比特的等效电容。
通过上述步骤，基于Fluxonium量子比特对应的电路的哈密顿量，以及基于哈密顿量中的初始电容矩阵和初始电感矩阵确定目标电容矩阵，并基于该目标电容矩阵确定Fluxonium量子比特的等效电容，相比于相关技术中，依据Fluxonium量子比特中关联的大电容确定等效电容而言，有效地提升了Fluxonium量子比特的等效电容的精确性。
作为一种可选的实施例，本等效电容的确定方法所采用的技术处理均可采纳上述等效 电容的确定方法一中所对应的场景。例如，上述初始电容矩阵以及上述初始电感矩阵均可以基于上述类似的方式构建得到。
作为一种可选的实施例，上述目标电容矩阵为从初始电容矩阵变换得来的一种电容矩阵，从该目标电容矩阵中可以直接读取出Fluxonium量子比特的等效电容。从初始电容矩阵变换到目标电容矩阵可以是一种矩阵简化过程，例如，删除一些无意义的耦合项，等。通过该矩阵简化过程，不仅能够得到简化的目标电容矩阵，而且进行矩阵变换的矩阵计算过程也更简单，并不易出错。
作为一种可选的实施例，基于初始电容矩阵和初始电感矩阵是结合起来描述整个哈密顿量的，因此，初始电容矩阵的变换与初始电感矩阵的变换是适应性的。例如，基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵时，可以先基于初始电感矩阵，获取第一变换矩阵；基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵。
作为一种可选的实施例，在基于初始电感矩阵，获取第一变换矩阵时，可以采用以下方式：去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵。采用上述先对初始电感矩阵进行简化的方式，得到目标电感矩阵，使得后续对目标电感矩阵进行对角化时也能够有效简化，提高处理效率。通过对目标电感矩阵进行对角化，有效地实现了对电感耦合的转化，使得整个哈密顿量中的等效电容更直观地体现在电容矩阵中。
作为一种可选的实施例，基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵，包括：对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵。为得到与目标电感矩阵相同尺寸的电容矩阵，也可以先将初始电容矩阵的首行首列去掉，而在将初始电容矩阵的首行首列去掉之前，为确保准确性，可以先对初始电容矩阵进行变换，即将初始电容矩阵中首行首列的矩阵元转换为零。这样再采用上述得到的第一变换矩阵对得到的电容矩阵进行作用，即可得到需要的目标电容矩阵，有效地实现了目标电容矩阵准确表征等效电容的目的。
作为一种可选的实施例，在基于目标电容矩阵确定Fluxonium量子比特的等效电容时，可以直接基于目标电容矩阵直接读取出Fluxonium量子比特的等效电容，比如，可以先获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵元，确定Fluxonium量子比特的等效电容。在基于目标矩阵元，确定Fluxonium量子比特的等效电容时，将该目标矩阵元的倒数确定为该等效电容。
基于上述实施例及可选实施例，提供了一种可选实施方式。
Fluxonium量子比特的电容大约在10到20fF，在通常的版图设计里面，该电容大部分由两个靠近的超导金属板提供，除此之外约瑟夫森结的寄生电容也会贡献几个fF的电 容。构成Fluxonium等效电感的串联约瑟夫森结除了结的寄生电容，每个结对其他电路元件的电容大约有0.01-0.1fF量级，上百个左右的结的总电容贡献也有大约fF量级，对比特电容的贡献不可忽略。在本可选实施方式中，提出了一种通过全版图模拟精确确定Fluxonium比特电容的方法。
整个版图需要模拟的元件尺寸从微米量级到百微米量级，横跨超过两个数量级，计算量较大，所以，在本可选实施方式，采用了表面积分方程方法进行快速模拟。在相关技术的一些确定等效电容的方法中，需要假设Fluxonium全电路模型具有对称性，也就是说串联的每个约瑟夫森结都相同，对地电容也都相同，并且忽略结和比特的金属板之间的电容。相对于相关技术中的方案，在本可选实施方式中，电路模型是从全版图模拟得到，不需要假设任何的对称性或者均匀性，能够更准确的描述一般性的版图设计所得到的比特电容。
下面对本可选实施方式进行说明。
图5是根据本发明可选实施方式的Fluxonium量子比特的芯片设计版图的示意图。如图5所示，图中斜线部分是绝缘体衬底，其他部分是超导体。图的中心附近两个互相垂直的深色长条交叠处为一个小约瑟夫森结。中间偏下的由方块和细线组成的环是串联的约瑟夫森结，提供Fluxonium量子比特的电感，其中每个方块是一个约瑟夫森结。地平面由包围在比特四周的超导金属构成，为了简明起见，这里没有画出来。
图6是根据本发明可选实施方式提供的Fluxonium量子比特的全电路模型的示意图，如图6所示，串联的每个约瑟夫森结近似为线性电感和结的寄生电容的并联。
基于图5所示的Fluxonium量子比特的芯片设计版图，通过表面积分方程方法对该版图进行静电场模拟，可以得到如图6所示的全电路模型。Fluxonium量子比特的电感一般由串联的约瑟夫森结构成。通常的Fluxonium设计里面，串联的约瑟夫森结尺寸较大，且数量较多，所以每个结的非线性效应较弱，可以近似认为是若干线性电感的串联。串联的每个约瑟夫森结的约瑟夫森能量表示为EJA,如果做线性近似，对应的线性电感为
其中为约化量子磁通。另外，每个约瑟夫森结的寄生电容表示为CA。各个节点对地电容.Φext为穿过约瑟夫森结环路的外加磁通。表示各个节点的磁通算符。
定义新的磁通算符组

图6所示电路模型在此新的磁通算符组表示之下的哈密顿量如下
其中为电容矩阵，定义为
为电感矩阵，定义为
和都是维数为(NJ+1)×(NJ+1)的矩阵。
定义变换矩阵
使得

其中
容易得到的逆矩阵表示
用表示变换之后的电容矩阵，那么
容易看出，在变换中保持不变，也即变换之后,和算符对应的第0个模式没有势能项，并且和其他NJ个模式完全没有耦合，被称为自由模式。自由模式可以去掉，去掉之后对模型不会产生可观测的影响。去掉之后的电容，电感矩阵分别表示为

和对应于量子比特模式。接下来，将构造变换来去掉比特模式和其他模式之间的电感耦合，也即磁通算符之间的耦合。
首先，构造
其中
M0通过W1变换之后可得M1
可以看出模式1和其他模式的电感耦合被消掉了。
类似的，可以迭代的定义一系列维数为NJ×NJ的变换矩阵Wf，满足对角元都是1，非对角元里面除了矩阵下三角部分第f列如下的元素为
其余元素都是0。其中，从Mf-1到Mf的递推关系为
总的变换为
因此，变换之后的电容和电感矩阵分别为

M＝WM0WT
其中M是对角矩阵。变换之后的哈密顿量为
模式NJ对应于Fluxonium量子比特模式。忽略(2)式中除了模式NJ之外的其他模式，得到Fluxonium等效哈密顿量
图7是根据本发明可选实施方式提供的Fluxonium量子比特的等效电路模型的示意图，如图7所示，从(2)式到(3)式的简化，对应于从图6的全电路模型到图7的等效电路模型的简化。因此，可以得到图7电路模型的等效电容为
在上述可选实施方式中，首先对Fluxonium量子比特芯片设计版图进行静电场模拟，得到Fluxonium全电路模型，然后构造一系列的等价变换分离出比特模式对应的等效哈密顿量，最后从哈密顿量中提取出Fluxonium量子比特的电容。整个流程从实际的版图设计精确的确定Fluxonium比特电容。
通过上述可选实施方式，可以实现以下有益效果：
(1)在本可选实施方式中，通过采用表面积分方程方法对Fluxonium量子比特芯片全版图进行模拟。由于需要通过模拟微米尺度的约瑟夫森结，以及其他几百微米尺度的超导元件，横跨超过两个数量级，计算较为复杂。表面积分方程方法对体系进行二维网格剖分，相比采用的三维网格剖分的有限元方法计算量更小，而且计算结果也更精确。
(2)在本可选实施方式中，通过静电场模拟得到的实际的Fluxonium全电路模型，然后构造等价变换提取出Fluxonium量子比特的电容。该方法适用于一般性的芯片版图设计，不需要假设有任何的对称性和均匀性，从而可以精确的确定量子比特的电容。相对于相关技术中得到比特电容的方法里面假设了串联约瑟夫森结的均匀性，也就是说每个结都完全相同，并且对地电容也相同，而真实的版图设计里面每个结对地的电容是不同的。所以采用本可选实施方式的方法可以得到更精确的比特电容。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本发明所必须的。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本发明的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个计算机可读存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本发明各个实施例的方法。
实施例3
根据本发明实施例，还提供了一种用于实施上述等效电容的确定方法一的装置，图7是根据本发明实施例的等效电容的确定装置一的框架图，如图8所示，该装置包括：第一确定模块802、第一处理模块804、第二处理模块806，第一获取模块808,第三处理模块810和第二确定模块812。下面分别说明。
第一确定模块802，用于确定Fluxonium量子比特的全电路的哈密顿量，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，Fluxonium量子比特的哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；第一处理模块804，连接至上述第一确定模块802，用于对初始电容矩阵进行变换， 得到首行首列的非对角元均为零的第一电容矩阵；第二处理模块806，连接至上述第一处理模块804，用于去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；第一获取模块808，连接至上述第二处理模块806，用于获取用于将目标电感矩阵对角化的第一变换矩阵；第三处理模块810，连接至上述第一获取模块808，将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；第二确定模块812，连接至上述第三处理模块810，用于基于目标电容矩阵确定Fluxonium量子比特的等效电容。
此处需要说明的是，上述第一确定模块802、第一处理模块804、第二处理模块806，第一获取模块808,第三处理模块810和第二确定模块812对应于实施例1中的步骤S202至步骤S212，几个模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以运行在实施例1提供的计算机终端10中。
根据本发明实施例，还提供了一种用于实施上述等效电容的确定方法二的装置，图9是根据本发明实施例的等效电容的确定装置二的框架图，如图9所示，该装置包括：第一显示模块902、第二获取模块904和第二显示模块906。下面分别说明。
第一显示模块902，用于在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，Fluxonium量子比特的哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；第二获取模块904，连接至上述第一显示模块902，用于响应于对等效电容确定控件的操作，获取Fluxonium量子比特的等效电容，其中，等效电容基于目标电容矩阵得到，目标电容矩阵由第一变换矩阵对第二电容矩阵进行变换得到，第二电容矩阵为去掉第一电容矩阵中的首行首列后得到的矩阵，第一电容矩阵的首行首列的非对角元均为零，第一电容矩阵由初始电容矩阵进行变换得到，第一变换矩阵为将目标电感矩阵对角化的矩阵，目标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；第二显示模块960，连接至上述第二获取模块904，用于在显示界面上显示等效电容。
此处需要说明的是，上述第一显示模块902、第二获取模块904和第二显示模块906对应于实施例1中的步骤S302至步骤S306，几个模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以运行在实施例1提供的计算机终端10中。
根据本发明实施例，还提供了一种用于实施上述等效电容的确定方法三的装置，图10是根据本发明实施例的等效电容的确定装置三的框架图，如图10所示，该装置包括：第三确定模块1002、第四处理模块1004和第四确定模块1006。下面分别说明。
第三确定模块1002，用于确定Fluxonium量子比特对应的电路的哈密顿量，其中，哈密顿量包括电容耦合项和电感耦合项，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；第四处理模块1004，连接至上述第三确定模块1002，用于基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵；第四确定模块1006，连接至上述第四处理模块1004，用于基于目标电容矩阵确定Fluxonium量子比特的等效电容。
此处需要说明的是，上述第三确定模块1002、第四处理模块1004和第三确定模块1006对应于实施例1中的步骤S402至步骤S406，几个模块与对应的步骤所实现的实例和应用场景相同，但不限于上述实施例1所公开的内容。需要说明的是，上述模块作为装置的一部分可以运行在实施例1提供的计算机终端10中。
实施例3
本发明的实施例还提供了一种计算机可读存储介质。可选地，在本实施例中，上述计算机可读存储介质可以用于保存上述实施例1所提供的等效电容的确定方法所执行的程序代码。
可选地，在本实施例中，上述计算机可读存储介质可以位于计算机网络中计算机终端群中的任意一个计算机终端中，或者位于移动终端群中的任意一个移动终端中。
可选地，在本实施例中，计算机可读存储介质被设置为存储用于执行以下步骤的程序代码：确定Fluxonium量子比特的全电路的哈密顿量，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；基于目标电容矩阵确定Fluxonium量子比特的等效电容。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵，包括：构造第二变换矩阵，其中，初始电感矩阵在第二变换矩阵的作用下保持不变；将第二变换矩阵作对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：获取用于将目标电感矩阵对角化的第一变换矩阵，包括：获取用于将目标电感矩 阵中的第一行第一列非对角元置零的第一变换子矩阵；获取用于将目标电感矩阵中的第二行第二列非对角元置零的第二变换子矩阵；依次操作，直到得到用于将目标电感矩阵中的第n行第n列非对角元置零的第n变换子矩阵，其中，n*n为目标电感矩阵的维数；将第一变换子矩阵，第二变换子矩阵，直到第n变换子矩阵连乘，得到第一变换矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于目标电容矩阵确定Fluxonium量子比特的等效电容，包括：获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵元，确定Fluxonium量子比特的等效电容。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于目标矩阵元，确定Fluxonium量子比特的等效电容，包括：确定目标矩阵元的倒数为Fluxonium量子比特的等效电容。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：通过以下方式，确定初始电容矩阵：确定约瑟夫森结阵列中多个约瑟夫森结的寄生电容，以及单个约瑟夫森结的并联电容，以及模式对应节点的对地电容，其中，约瑟夫森结阵列中包括的模式对应节点的数量为模式数量加一；基于寄生电容，并联电容以及对地电容，构造初始电容矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：通过以下方式，确定初始电感矩阵：获取约瑟夫森结阵列中串联的多个约瑟夫森结的线性电感；基于线性电感，构造首行和首列均为零的初始电感矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：在基于目标电容矩阵确定Fluxonium量子比特的等效电容之后，还包括：检测得到的等效电容是否为目标等效电容；在检测结果为得到的等效电容不为目标等效电容的情况下，多次调整Fluxonium量子比特中单个约瑟夫森结的两个超导金属板的尺寸和位置的设计参数，直到得到的等效电容为目标等效电容，并确定等效电容为目标等效电容对应的设计参数为两个超导金属板的尺寸和位置的设计参数。
可选地，在本实施例中，计算机可读存储介质被设置为存储用于执行以下步骤的程序代码：在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；响应于对等效电容确定控件的操作，获取Fluxonium量子比特的等效电容，其中，等效电容基于目标电容矩阵得到，目标电容矩阵由第一变换矩阵对第二电容矩阵进行变换得到，第二电容矩阵为去掉第一电 容矩阵中的首行首列后得到的矩阵，第一电容矩阵的首行首列的非对角元均为零，第一电容矩阵由初始电容矩阵进行变换得到，第一变换矩阵为将目标电感矩阵对角化的矩阵，目标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；在显示界面上显示等效电容。
可选地，在本实施例中，计算机可读存储介质被设置为存储用于执行以下步骤的程序代码：确定Fluxonium量子比特对应的电路的哈密顿量，其中，哈密顿量包括电容耦合项和电感耦合项，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵，其中，目标电容矩阵中；基于目标电容矩阵确定Fluxonium量子比特的等效电容。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵，包括：基于初始电感矩阵，获取第一变换矩阵；基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于初始电感矩阵，获取第一变换矩阵，包括：去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵，包括：对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵。
可选地，在本实施例中，计算机可读存储介质还被设置为存储用于执行以下步骤的程序代码：基于目标电容矩阵确定Fluxonium量子比特的等效电容，包括：获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵元，确定Fluxonium量子比特的等效电容。
本发明的实施例可以提供一种计算机设备，该计算机设备可以是计算机终端群中的任意一个计算机终端设备。可选地，在本实施例中，上述计算机终端也可以替换为移动终端等终端设备。
可选地，在本实施例中，上述计算机设备可以位于计算机网络的多个网络设备中的至少一个网络设备。
在本实施例中，上述计算机设备可以执行应用程序的等效电感的确定方法中以下步骤的程序代码：确定Fluxonium量子比特的全电路的哈密顿量，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，哈密顿量包括电容耦合项和电感耦 合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；基于目标电容矩阵确定Fluxonium量子比特的等效电容。
可选地，图11是根据本发明实施例的一种计算机设备的结构框图。如图11所示，该计算机设备可以包括：一个或多个(图中仅示出一个)处理器1102、存储器1104等。
其中，存储器1104可用于存储软件程序以及模块，如本发明实施例中的搜索处理方法和装置对应的程序指令/模块，处理器1102通过运行存储在存储器1104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的搜索处理方法。存储器1104可包括高速随机存储器1104，还可以包括非易失性存储器1104，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器1104。在一些实例中，存储器1104可进一步包括相对于处理器1102远程设置的存储器1104，这些远程存储器1104可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
处理器1102可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：确定Fluxonium量子比特的全电路的哈密顿量，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵；基于目标电容矩阵确定Fluxonium量子比特的等效电容。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵，包括：构造第二变换矩阵，其中，初始电感矩阵在第二变换矩阵的作用下保持不变；将第二变换矩阵作对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：获取用于将目标电感矩阵对角化的第一变换矩阵，包括：获取用于将目标电感矩阵中的第一行第一列非对角元置零的第一变换子矩阵；获取用于将目标电感矩阵中的第二行第二列非对角元置零的第二变换子矩阵；依次操作，直到得到用于将目标电感矩阵中的 第n行第n列非对角元置零的第n变换子矩阵，其中，n*n为目标电感矩阵的维数；将第一变换子矩阵，第二变换子矩阵，直到第n变换子矩阵连乘，得到第一变换矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于目标电容矩阵确定Fluxonium量子比特的等效电容，包括：获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵元，确定Fluxonium量子比特的等效电容。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于目标矩阵元，确定Fluxonium量子比特的等效电容，包括：确定目标矩阵元的倒数为Fluxonium量子比特的等效电容。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：通过以下方式，确定初始电容矩阵：确定约瑟夫森结阵列中多个约瑟夫森结的寄生电容，以及单个约瑟夫森结的并联电容，以及模式对应节点的对地电容，其中，约瑟夫森结阵列中包括的模式对应节点的数量为模式数量加一；基于寄生电容，并联电容以及对地电容，构造初始电容矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：通过以下方式，确定初始电感矩阵：获取约瑟夫森结阵列中串联的多个约瑟夫森结的线性电感；基于线性电感，构造首行和首列均为零的初始电感矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：在基于目标电容矩阵确定Fluxonium量子比特的等效电容之后，还包括：检测得到的等效电容是否为目标等效电容；在检测结果为得到的等效电容不为目标等效电容的情况下，多次调整Fluxonium量子比特中单个约瑟夫森结的两个超导金属板的尺寸和位置的设计参数，直到得到的等效电容为目标等效电容，并确定等效电容为目标等效电容对应的设计参数为两个超导金属板的尺寸和位置的设计参数。
处理器1102可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，约瑟夫森结阵列由多个约瑟夫森结串联得到，多个约瑟夫森结对应多个模式，哈密顿量包括电容耦合项和电感耦合项，其中，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；响应于对等效电容确定控件的操作，获取Fluxonium量子比特的等效电容，其中，等效电容基于目标电容矩阵得到，目标电容矩阵由第一变换矩阵对第二电容矩阵进行变换得到，第二电容矩阵为去掉第一电容矩阵中的首行首列后得到的矩阵，第一电容矩阵的首行首列的非对角元均为零，第一电容矩阵由初始电容矩阵进行变换得到，第一变换矩阵为将目标电感矩阵对角化的矩阵，目 标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；在显示界面上显示等效电容。
处理器1102可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：确定Fluxonium量子比特对应的电路的哈密顿量，其中，哈密顿量包括电容耦合项和电感耦合项，电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵，其中，目标电容矩阵中；基于目标电容矩阵确定Fluxonium量子比特的等效电容。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于初始电感矩阵和初始电容矩阵，得到目标电容矩阵，包括：基于初始电感矩阵，获取第一变换矩阵；基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于初始电感矩阵，获取第一变换矩阵，包括：去掉初始电感矩阵中均为零的首行首列，得到目标电感矩阵；获取用于将目标电感矩阵对角化的第一变换矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于初始电容矩阵和第一变换矩阵，得到目标电容矩阵，包括：对初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；去掉第一电容矩阵中的首行首列，得到第二电容矩阵；将第一变换矩阵作用于第二电容矩阵，得到目标电容矩阵。
处理器1102还可以通过传输装置调用存储器1104存储的信息及应用程序，以执行下述步骤：基于目标电容矩阵确定Fluxonium量子比特的等效电容，包括：获取目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；基于目标矩阵元，确定Fluxonium量子比特的等效电容。
本领域普通技术人员可以理解，图11所示的结构仅为示意，计算机终端也可以是智能手机(如Android手机、iOS手机等)、平板电脑、掌声电脑以及移动互联网设备(Mobile Internet Devices，MID)、PAD等终端设备。图11其并不对上述电子装置的结构造成限定。例如，计算机终端还可包括比图11中所示更多或者更少的组件(如网络接口、显示装置等)，或者具有与图11所示不同的配置。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令终端设备相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，计算机可读存储介质可以包括：闪存盘、只读存储器(Read-Only Memory，ROM)、随机存取器(Random Access Memory，RAM)、磁盘或光盘等。
上述本发明实施例序号仅仅为了描述，不代表实施例的优劣。
在本发明的上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述 的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的技术内容，可通过其它的方式实现。其中，以上所描述的装置实施例仅仅是示意性的，例如单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，单元或模块的间接耦合或通信连接，可以是电性或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个计算机可读存储介质中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本发明各个实施例方法的全部或部分步骤。而前述的计算机可读存储介质包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
以上仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (15)

  1. 一种等效电容的确定方法，其特征在于，包括：
    确定Fluxonium量子比特的全电路的哈密顿量，其中，所述Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，所述约瑟夫森结阵列由多个约瑟夫森结串联得到，所述多个约瑟夫森结对应多个模式，所述哈密顿量包括电容耦合项和电感耦合项，其中，所述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；
    对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；
    去掉所述第一电容矩阵中的首行首列，得到第二电容矩阵，以及去掉所述初始电感矩阵中均为零的首行首列，得到目标电感矩阵；
    获取用于将所述目标电感矩阵对角化的第一变换矩阵；
    将所述第一变换矩阵作用于所述第二电容矩阵，得到目标电容矩阵；
    基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容。
  2. 根据权利要求1所述的方法，其特征在于，所述对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵，包括：
    构造第二变换矩阵，其中，所述初始电感矩阵在所述第二变换矩阵的作用下保持不变；
    将所述第二变换矩阵作对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的所述第一电容矩阵。
  3. 根据权利要求1所述的方法，其特征在于，所述获取用于将所述目标电感矩阵对角化的第一变换矩阵，包括：
    获取用于将所述目标电感矩阵中的第一行第一列非对角元置零的第一变换子矩阵；
    获取用于将所述目标电感矩阵中的第二行第二列非对角元置零的第二变换子矩阵；
    依次操作，直到得到用于将所述目标电感矩阵中的第n行第n列非对角元置零的第n变换子矩阵，其中，n*n为所述目标电感矩阵的维数；
    将所述第一变换子矩阵，第二变换子矩阵，直到所述第n变换子矩阵连乘，得 到所述第一变换矩阵。
  4. 根据权利要求1所述的方法，其特征在于，所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容，包括：
    获取所述目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；
    基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容。
  5. 根据权利要求4所述的方法，其特征在于，所述基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容，包括：
    确定所述目标矩阵元的倒数为所述Fluxonium量子比特的所述等效电容。
  6. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    通过以下方式，确定所述初始电容矩阵：
    确定所述约瑟夫森结阵列中多个约瑟夫森结的寄生电容，以及所述单个约瑟夫森结的并联电容，以及所述模式对应节点的对地电容，其中，所述约瑟夫森结阵列中包括的模式对应节点的数量为模式数量加一；
    基于所述寄生电容，所述并联电容以及所述对地电容，构造所述初始电容矩阵。
  7. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    通过以下方式，确定所述初始电感矩阵：
    获取所述约瑟夫森结阵列中串联的所述多个约瑟夫森结的线性电感；
    基于所述线性电感，构造首行和首列均为零的所述初始电感矩阵。
  8. 根据权利要求1至7中任一项所述的方法，其特征在于，在所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容之后，还包括：
    检测得到的等效电容是否为目标等效电容；
    在检测结果为得到的所述等效电容不为所述目标等效电容的情况下，多次调整所述Fluxonium量子比特中所述单个约瑟夫森结的两个超导金属板的尺寸和位置的设计参数，直到得到的等效电容为所述目标等效电容，并确定等效电容为所述目标等效电容对应的设计参数为所述两个超导金属板的尺寸和位置的设计参数。
  9. 一种等效电容的确定方法，其特征在于，包括：
    在显示界面上显示Fluxonium量子比特以及等效电容确定控件，其中，所述Fluxonium量子比特的全电路由约瑟夫森结阵列，电容以及单个约瑟夫森结并联形成，所述约瑟夫森结阵列由多个约瑟夫森结串联得到，所述多个约瑟夫森结对应多个模式，所述Fluxonium量子比特的哈密顿量包括电容耦合项和电感耦合项，其中，所 述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征；
    响应于对所述等效电容确定控件的操作，获取所述Fluxonium量子比特的等效电容，其中，所述等效电容基于目标电容矩阵得到，所述目标电容矩阵由第一变换矩阵对第二电容矩阵进行变换得到，所述第二电容矩阵为去掉第一电容矩阵中的首行首列后得到的矩阵，所述第一电容矩阵的首行首列的非对角元均为零，所述第一电容矩阵由所述初始电容矩阵进行变换得到，所述第一变换矩阵为将目标电感矩阵对角化的矩阵，所述目标电感矩阵为去掉初始电感矩阵中的首行首列后得到的矩阵；
    在所述显示界面上显示所述等效电容。
  10. 一种等效电容的确定方法，其特征在于，包括：
    确定Fluxonium量子比特对应的电路的哈密顿量，其中，所述哈密顿量包括电容耦合项和电感耦合项，所述电容耦合项采用初始电容矩阵和模式对应节点的电荷算符表征，所述电感耦合项采用初始电感矩阵和模式对应节点的磁通算符表征，所述Fluxonium量子比特中与电容和单个约瑟夫森结并联的多个约瑟夫森结对应于多个模式；
    基于所述初始电感矩阵和所述初始电容矩阵，得到目标电容矩阵，其中，所述目标电容矩阵中；
    基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容。
  11. 根据权利要求10所述的方法，其特征在于，所述基于所述初始电感矩阵和所述初始电容矩阵，得到目标电容矩阵，包括：
    基于所述初始电感矩阵，获取第一变换矩阵；
    基于所述初始电容矩阵和所述第一变换矩阵，得到所述目标电容矩阵。
  12. 根据权利要求11所述的方法，其特征在于，所述基于所述初始电感矩阵，获取第一变换矩阵，包括：
    去掉所述初始电感矩阵中均为零的首行首列，得到目标电感矩阵；
    获取用于将所述目标电感矩阵对角化的所述第一变换矩阵。
  13. 根据权利要求12所述的方法，其特征在于，所述基于所述初始电容矩阵和所述第一变换矩阵，得到所述目标电容矩阵，包括：
    对所述初始电容矩阵进行变换，得到首行首列的非对角元均为零的第一电容矩阵；
    去掉所述第一电容矩阵中的首行首列，得到第二电容矩阵；
    将所述第一变换矩阵作用于所述第二电容矩阵，得到目标电容矩阵。
  14. 根据权利要求10至13中任一项所述的方法，其特征在于，所述基于所述目标电容矩阵确定所述Fluxonium量子比特的等效电容，包括：
    获取所述目标电容矩阵的逆矩阵中最后一行最后一列所对应的目标矩阵元；
    基于所述目标矩阵元，确定所述Fluxonium量子比特的等效电容。
  15. 一种计算机设备，其特征在于，包括：存储器和处理器，
    所述存储器存储有计算机程序；
    所述处理器，用于执行所述存储器中存储的计算机程序，所述计算机程序运行时使得所述处理器执行权利要求1至14中任意一项所述的等效电容的确定方法。
PCT/CN2023/133098 2022-12-07 2023-11-21 等效电容的确定方法及计算机设备 WO2024120188A1 (zh)

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