WO2024119710A1 - 光传感器读出电路以及芯片 - Google Patents

光传感器读出电路以及芯片 Download PDF

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Publication number
WO2024119710A1
WO2024119710A1 PCT/CN2023/092685 CN2023092685W WO2024119710A1 WO 2024119710 A1 WO2024119710 A1 WO 2024119710A1 CN 2023092685 W CN2023092685 W CN 2023092685W WO 2024119710 A1 WO2024119710 A1 WO 2024119710A1
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WIPO (PCT)
Prior art keywords
switch
module
trigger
charge
output
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PCT/CN2023/092685
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English (en)
French (fr)
Inventor
姜珲
王欢
权锐
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武汉市聚芯微电子有限责任公司
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Publication of WO2024119710A1 publication Critical patent/WO2024119710A1/zh

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00—Photometry, e.g. photographic exposure meter
    • G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
    • G01J1/44—Electric circuits

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular to a light sensor readout circuit and a chip including the light sensor readout circuit.
  • Light sensors can sense the intensity of ambient light and tell the processing chip to automatically adjust the display backlight brightness to reduce the power consumption of the product. For example, in mobile applications such as mobile phones, notebooks, and tablets, the screen consumes up to 30% of the total battery power. Using light sensors to collect ambient light intensity and adjust the screen brightness can not only maximize the battery life, but also make the screen brightness change with the ambient brightness, which is conducive to providing a soft picture on the screen. However, the light-generated current of the light sensor is small, and it is difficult to detect the current through conventional current detection methods.
  • the present application provides a light sensor readout circuit and chip, aiming to solve the current technical problem that the light sensor current is small and difficult to detect.
  • the present application provides a light sensor readout circuit for reading out the current of a light sensor module, comprising:
  • the oscillating module is used to output an oscillating signal
  • a comparison module which is used to compare the reference signal with the oscillation signal and output a comparison signal
  • a charge output module the charge output module is used to output the charge according to the comparison signal
  • An integration module the integration module is used to change the oscillation frequency of the oscillation module according to the charge output by the charge output module;
  • the amount of charge output by the charge output module is equal to the amount of charge passing through the light sensing module.
  • control end of the charge output module is connected to the output end of the comparison module, and the charge output module is used to output the charge alternately according to the comparison signal;
  • the input end of the integration module is connected to the charge output module.
  • the output end of the charge output module is connected, the output end of the integration module is connected to the control end of the oscillation module, and the integration module is used to change the oscillation frequency of the oscillation module according to the charge output by the charge output module;
  • the optical sensing module is connected to the integration module; wherein, after the integration module receives the charge output by the charge output module, the integration module outputs the charge to the optical sensing module, and the charge amount output by the charge output module is equal to the charge amount passing through the optical sensing module.
  • the charge output module outputs the charge alternately according to the comparison signal
  • the integration module alternately controls the oscillation frequency of the oscillation module to increase or decrease according to the charges alternately output by the charge output module;
  • the integration module After the integration module receives the charge output by the charge output module, the integration module outputs the charge to the light sensing module.
  • the charge output module has a first working state and a second working state, and the charge output module switches back and forth between the first working state and the second working state based on the comparison signal;
  • the charge output module When the charge output module is in the first working state, the charge output module provides charge to the integration module, and the integration module controls the oscillation module to increase the oscillation frequency based on the accumulated charge;
  • the charge output module stops providing charges to the integration module, and the integration module releases charges to the light sensing module.
  • the light sensing module is connected to the charge output module, and when the charge output module is in a first working state, the charge output module provides charge to the integration module and the light sensing module simultaneously;
  • the charge output module stops providing charges to the integration module and the light sensing module.
  • the integration module includes an integrator, and the light sensing module includes a photodiode;
  • the inverting input terminal of the integrator is connected to the cathode of the photodiode, the non-inverting input terminal of the integrator is used to access the first preset voltage, the output terminal of the integrator is connected to the oscillation module, and the anode of the photodiode is used to be grounded.
  • the charge output module includes a control switch
  • control switch One end of the control switch is connected to the inverting input end of the integrator, and the other end is used to access a fixed current source.
  • the control end of the control switch is used to access a comparison signal and change the switch state based on the comparison signal, so that the charge output module switches back and forth between the first working state and the second working state.
  • I1 is the current of the light sensing module
  • I2 is the current of the charge output module
  • T1 is the time when the control switch is closed
  • T2 is the time when the control switch is opened.
  • the comparison module includes a phase comparison submodule and a pulse width adjustment submodule
  • the phase comparison submodule is used to compare the phase difference between the reference signal and the oscillation signal, and output a signal to be processed, the pulse width of the signal to be processed is equal to the phase difference between the oscillation signal and the reference signal;
  • the pulse width adjustment submodule is used to adjust the pulse width of the signal to be processed to generate a comparison signal with a fixed pulse width.
  • I1 is the current of the light sensing module
  • I2 is the current of the charge output module
  • T is the fixed pulse width of the comparison signal
  • N is the number of times the control switch is closed per unit time.
  • the phase comparison submodule includes a first trigger, a second trigger, a first AND gate, and a first delay device
  • the pulse width adjustment submodule includes a pulse generator
  • the control terminal of the first trigger is used to access the reference signal, the input terminal of the first trigger is used to access the working voltage, and the output terminal of the first trigger is connected to the first input terminal of the first AND gate;
  • the control end of the second trigger is used to access the oscillation signal, the input end of the second trigger is used to access the working voltage, and the output end of the first trigger is connected to the second input end of the first AND gate;
  • An input terminal of the first delay device is connected to an output terminal of the first AND gate, and a reset terminal of the first trigger and a reset terminal of the second trigger are connected to an output terminal of the delay device;
  • the input end of the pulse generator is connected to the output end of the first trigger or the second trigger, and the output end of the pulse generator is connected to the control end of the control switch.
  • the integration module includes an integrator, and the light sensing module includes a photodiode;
  • the charge output module includes a first sub-switch and a second sub-switch;
  • the in-phase input terminal of the integrator is used to access the first preset voltage, and the output terminal of the integrator is connected to the oscillation module;
  • One end of the second sub-switch is connected to the inverting input end of the integrator, and the other end is connected to the cathode of the photodiode, and the anode of the photodiode is grounded;
  • One end of the first sub-switch is used to access the working voltage, and the other end is connected to a third node between the second sub-switch and the inverting input end of the integrator;
  • the control terminal of the first sub-switch is used to access the comparison signal and change the switch state based on the comparison signal, and the switch state of the first sub-switch is opposite to the switch state of the second sub-switch.
  • I1 is the current of the light sensing module
  • I2 is the current of the charge output module
  • t01 is the time when the first sub-switch is closed
  • t02 is the time when the second sub-switch is opened.
  • the comparison module includes a first trigger, a second trigger, a first AND gate, and a first delay device;
  • the control terminal of the first trigger is used to access the reference signal, the input terminal of the first trigger is used to access the working voltage, and the output terminal of the first trigger is connected to the first input terminal of the first AND gate;
  • the control end of the second trigger is used to access the oscillation signal, the input end of the second trigger is used to access the working voltage, and the output end of the first trigger is connected to the second input end of the first AND gate;
  • An input terminal of the first delay device is connected to an output terminal of the first AND gate, and a reset terminal of the first trigger and a reset terminal of the second trigger are connected to an output terminal of the delay device;
  • the control end of the first sub-switch is connected to the output end of the first trigger.
  • the ratio of the current of the light sensing module to the current of the charge output module ranges from 1:5000 to 1:100.
  • the charge output module includes a first switch, a second switch, a third switch, a fourth switch, and a control capacitor;
  • One end of the first switch is connected to the first end of the control capacitor, and the other end is used to connect to the second preset voltage;
  • One end of the second switch is connected to the second end of the control capacitor, and the other end is connected to the inverting input end of the integrator;
  • One end of the third switch is connected to the first node between the first switch and the control capacitor, and the other end is grounded;
  • One end of the fourth switch is connected to the second node between the second switch and the control capacitor, and the other end is used for the first preset voltage
  • control ends of the first switch and the second switch are used to access the comparison signal and change the switch state based on the comparison signal;
  • the control ends of the third switch and the fourth switch are used to access the control signal that is inverted with the comparison signal and change the switch state based on the control signal.
  • I1 is the current of the light sensor module
  • Cc is the capacitance value of the control capacitor
  • V1 is the first preset voltage
  • V2 is the second preset voltage
  • N is the number of times the second switch is closed per unit time.
  • the comparison module includes a first trigger, a second trigger, a first AND gate, a first delay device, and a first inverter;
  • the control terminal of the first trigger is used to access the reference signal, the input terminal of the first trigger is used to access the working voltage, and the output terminal of the first trigger is connected to the first input terminal of the first AND gate;
  • the control end of the second trigger is used to access the oscillation signal, the input end of the second trigger is used to access the working voltage, and the output end of the first trigger is connected to the second input end of the first AND gate;
  • An input terminal of the first delay device is connected to an output terminal of the first AND gate, and a reset terminal of the first trigger and a reset terminal of the second trigger are connected to an output terminal of the delay device;
  • An input terminal of the first inverter is connected to an output terminal of the first trigger
  • the control ends of the first switch and the second switch are connected to the output end of the first trigger, and the control ends of the third switch and the fourth switch are connected to the output end of the first inverter.
  • the comparison module includes a first resistor, a first comparator, an equivalent capacitor, a fifth switch, and a sixth switch;
  • the first resistor, the fifth switch and the equivalent capacitor are connected in series in sequence, an end of the first resistor away from the fifth switch is used to connect to the working voltage, and an end of the equivalent capacitor away from the fifth switch is used to be grounded;
  • One end of the sixth switch is connected to the fourth node between the fifth switch and the equivalent capacitor, and the other end is grounded;
  • the inverting input terminal of the first comparator is used to access the third preset voltage, the non-inverting input terminal of the first comparator is connected to the fifth node between the first resistor and the fifth switch, and the output terminal of the first comparator is used to output a comparison signal;
  • control end of the fifth switch is used to access the oscillation signal and change the switch state based on the oscillation signal, and the switch state of the sixth switch is opposite to the switch state of the fifth switch.
  • the oscillation module includes a ring oscillator and an acceleration switch
  • the ring oscillator includes a plurality of inverters connected in series in a ring shape, and the control end of the acceleration switch is connected to the output end of the integrator;
  • One end of the acceleration switch is used to access the working voltage, and the other end is connected to the power supply end of the inverter.
  • the present application provides a chip comprising the light sensor readout circuit as described in the first aspect.
  • the present application utilizes a comparison module to compare a reference signal with an oscillation signal and generate a comparison signal, through which the charge output module alternately outputs charges, and the integration module can alternately control the oscillation frequency of the oscillation module to increase or decrease according to the changing amount of charge.
  • the comparison module can continuously output the comparison signal. Since the average amount of charge flowing into the integration module is equal to 0 when the oscillation frequency of the oscillation module is dynamically changed, the amount of charge output by the charge output module is equal to the amount of charge passing through the light sensor module. Therefore, it is only necessary to use the comparison signal (for example, the product of the high level time of the comparison signal and the current of the light sensor module) to realize the cumulative measurement of the amount of charge flowing through the light sensor module, and calculate the current of the light sensor module, and finally obtain the light intensity through the relationship between the current of the light sensor module and the light intensity.
  • the comparison signal for example, the product of the high level time of the comparison signal and the current of the light sensor module
  • FIG1 is a schematic diagram of a module structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG2 is a schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG3 is another schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG4 is a pulse signal timing diagram of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG5 is a pulse signal timing diagram of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG6 is a pulse signal timing diagram of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG7 is a schematic diagram of a high level time measurement of a comparison signal provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of a module structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG9 is another schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of a module structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG12 is another schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG13 is another pulse signal timing diagram of the optical sensor readout circuit provided in an embodiment of the present application.
  • FIG14 is another schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG15 is another pulse signal timing diagram of the optical sensor readout circuit provided in an embodiment of the present application.
  • FIG16 is another schematic diagram of a circuit structure of a light sensor readout circuit provided in an embodiment of the present application.
  • FIG. 17 is another schematic diagram of the circuit structure of the optical sensor readout circuit provided in an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the said features.
  • “multiple” means two or more, unless otherwise specified. Specify specific limitations.
  • the embodiments of the present application provide a light sensor readout circuit and a chip, which are described in detail below.
  • FIG. 1 shows a schematic diagram of a module structure of a light sensor readout circuit in an embodiment of the present application.
  • the light sensor readout circuit is used to read out the current of the light sensor module 50, wherein the light sensor readout circuit includes:
  • An oscillation module 10 the oscillation module 10 is used to output an oscillation signal F RET ;
  • a comparison module 20 the comparison module 20 is used to compare the reference signal F REF with the oscillation signal F RET and output a comparison signal Dout;
  • An integration module 40 wherein the input end of the integration module 40 is connected to the output end of the charge output module 30, and the output end of the integration module 40 is connected to the control end of the oscillation module 10, and the integration module 40 is used to alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the charges alternately output by the charge output module 30;
  • a light sensing module 50 the light sensing module 50 is connected to the integration module 40;
  • the integration module 40 After receiving the charge output from the charge output module 30 , the integration module 40 outputs the charge to the light sensing module 50 , and the amount of charge output by the charge output module 30 is equal to the amount of charge passing through the light sensing module 50 .
  • the oscillation module 10 is used to convert a DC voltage signal into an AC voltage signal with a certain frequency (such as a sine wave or square wave signal).
  • the oscillation frequency of the oscillation module 10 can be controlled and changed by the integration module 40, so that the phase difference between the oscillation signal F RET output by the oscillation module 10 and the reference signal F REF changes.
  • the oscillation excitation mode of the oscillation module 10 can be a self-excited oscillation mode
  • the externally excited oscillation mode for example, the oscillation module 10 may include a resistor-capacitor oscillator, an inductor-capacitor oscillator, a crystal oscillator, a tuning fork oscillator, and the like.
  • the comparison module 20 is used to compare the reference signal F REF with the oscillation signal F RET and output the comparison signal Dout, so that the charge output module 30 outputs the charge alternately according to the comparison signal Dout.
  • the comparison module 20 can compare the phase difference between the reference signal F REF and the oscillation signal F RET .
  • the comparison module 20 can compare the frequency of the reference signal F REF with the oscillation signal F RET .
  • the comparison module 20 can include a frequency detector, a gate detector, or a three-state detector.
  • the first input terminal of the comparison module 20 is used to access the reference signal F REF
  • the second input terminal is connected to the output terminal of the oscillation module to facilitate access to the oscillation signal F RET .
  • the reference signal F REF can also be generated by the comparison module 20 itself, for example, using an oscillator to generate the reference signal.
  • the charge output module 30 is used to alternately output the charge according to the comparison signal Dout, so that the integration module 40 alternately controls the oscillation frequency of the oscillation module 10 to increase or decrease according to the changed charge amount.
  • the charge output module 30 has a first working state and a second working state, and the charge output module 30 switches back and forth between the first working state and the second working state based on the comparison signal Dout, so that the charge output module 30 alternately outputs the charge.
  • the alternating switching between the first working state and the second working state of the charge output module 30 can be achieved by a switch, for example, a fixed current source is provided, when the switch is closed, the charge output module 30 inputs the charge to the integration module 40; and when the switch is in the closed state, the charge output module 30 stops inputting the charge to the integration module 40, and the charge amount output by the charge output module 30 can be calculated by multiplying the fixed current by the switch closing time.
  • a switch for example, a fixed current source is provided, when the switch is closed, the charge output module 30 inputs the charge to the integration module 40; and when the switch is in the closed state, the charge output module 30 stops inputting the charge to the integration module 40, and the charge amount output by the charge output module 30 can be calculated by multiplying the fixed current by the switch closing time.
  • the charge output module 30 may also control a current source with a changing current value through a switch, and calculate the corresponding charge amount by integrating the changing current.
  • the integration module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the changing amount of charge. Specifically, the integration module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the charge alternately output by the charge output module 30. After the integration module 40 receives the charge output by the charge output module 30, the integration module 40 outputs the charge to the light sensing module 50. In some embodiments of the present application, for example, for an embodiment in which the charge output module 30 has a first working state and a second working state, when the charge output module 30 is in the first working state, the charge output module 30 outputs the charge to the integration module 10.
  • the submodule 40 provides charge, and the integration module 40 controls the oscillation module 10 to increase the oscillation frequency based on the accumulated charge; when the charge output module 30 is in the second working state, the charge output module 30 stops providing charge to the integration module 40, and the integration module 40 releases charge to the light sensing module 50, and the integration module 40 controls the oscillation module 10 to reduce the oscillation frequency based on the released charge.
  • the comparison module can compare the phase difference between the reference signal F REF and the oscillation signal F RET
  • the charge output module 30 when the charge output module 30 is in the first working state, the charge output module 30 provides charge to the integration module 40, and the integration module 40 controls the oscillation module 10 to increase the oscillation frequency based on the accumulated charge to reduce the phase difference between the input signal F REF and the feedback signal F RET ;
  • the charge output module 30 stops providing charge to the integration module 40, and the integration module 40 releases charge to the light sensing module 50, and the integration module 40 controls the oscillation module 10 to reduce the oscillation frequency based on the released charge to expand the phase difference between the input signal F REF and the feedback signal F RET .
  • the input signal F REF and the feedback signal F RET maintain a corresponding phase difference, so that the comparison module 20 continuously outputs the comparison signal Dout associated with the phase difference, ensuring that the optical sensor readout circuit performs current measurement in a non-steady state.
  • the amount of charges accumulated by the charge output module 30 to the integration module 40 during multiple alternations between the first working state and the second working state is equal to the charges released by the integration module 40 to the light sensing module 50.
  • Figure 2 shows a circuit structure diagram of the optical sensor readout circuit in an embodiment of the present application, wherein the integration module 40 includes a capacitor C, one end of which is connected to the charge output module 30, and the other end is connected to the oscillation module 10.
  • the charge output module 30 When the charge output module 30 charges the capacitor C, the plate at one end of the capacitor accumulates charge, and the voltage of the plate at the other end gradually decreases and controls the oscillation module 10 to increase the oscillation frequency, thereby reducing the phase difference between the reference signal F REF and the oscillation signal F RET ; and when the charge output module 30 stops charging the capacitor C, the charge accumulated on the plate at one end of the capacitor is released to the optical sensor module 50, and the voltage of the plate at the other end gradually increases and controls the oscillation module 10 to reduce the oscillation frequency, thereby increasing the phase difference between the reference signal F REF and the oscillation signal F RET .
  • the comparison module 20 is used to compare the reference signal F REF with the oscillation signal F RET and generate a comparison signal Dout.
  • the comparison signal Dout causes the charge output module 30 to alternately output the charge.
  • the integral module 40 can alternately control the oscillation frequency of the oscillation module 10 to increase or decrease according to the changed charge amount.
  • the comparison module 20 can continuously output the comparison signal Dout. Furthermore, since the average amount of charge flowing into the integration module 40 is equal to 0 when the oscillation frequency of the oscillation module 10 is dynamically changed, the amount of charge output by the charge output module 30 is equal to the amount of charge passing through the light sensor module 50. Therefore, the cumulative measurement of the amount of charge flowing through the light sensor module 50 can be achieved only based on the comparison signal Dout (for example, the product of the high level time of the comparison signal Dout and the fixed current of the charge output module 30), and the current of the light sensor module 50 can be calculated. Finally, the light intensity is obtained through the relationship between the current of the light sensor module 50 and the light intensity.
  • Figure 3 shows another circuit structure schematic diagram of the light sensor readout circuit in the embodiment of the present application
  • Figure 4 shows a pulse signal timing diagram of the light sensor readout circuit in the embodiment of the present application, wherein the light sensing module 50 is connected between the charge output module 30 and the integration module 40, that is, the light sensing module 50 is connected to the output end of the charge output module 30 and to the input end of the integration module 40.
  • the charge output module 30 When the charge output module 30 is in the first working state, the charge output module 30 simultaneously provides charge to the integration module 40 and the light sensing module 50; when the charge output module 30 is in the second working state, the charge output module 30 stops providing charge to the integration module 40 and the light sensing module 50.
  • the charge output module 30 provides the charge amount Q1 and the charge amount Q2 to the light sensor module 50 and the integration module 40 respectively, while in the second working state, the charge amount Q2 accumulated by the integration module 40 flows to the light sensor module 50. Therefore, the accumulated charge amount Q output by the charge output module 30 is equal to the charge amount flowing through the light sensor module 50, that is, equal to the sum of the charge amount Q1 and the charge amount Q2.
  • the integration module 40 includes an integrator IN1
  • the light sensing module 50 includes a photodiode PD.
  • the inverting input terminal of the integrator IN1 is connected to the cathode of the photodiode PD
  • the non-inverting input terminal of the integrator IN1 is used to access the first preset voltage V1
  • the output terminal of the integrator IN1 is connected to the oscillation module 10
  • the anode of the photodiode PD is used to be grounded.
  • the integration module 40 uses an integrator IN1.
  • the positive input terminal and the negative input terminal of the integrator IN1 have equal voltages due to the virtual short characteristic, so the voltage of the photodiode PD can be guaranteed to be stable, avoiding the phenomenon that the photocurrent of the photodiode PD changes due to voltage fluctuations.
  • the capacitor C0 of the integrator IN1 cannot pass charges, ensuring that the amount of charge output by the charge output module 30 is equal to the current flowing through the photodiode PD.
  • the integrator IN1 outputs a linear voltage signal Vout due to the change in the amount of charge on the capacitor C0, thereby facilitating the control of the oscillation module 10 to increase the oscillation frequency or reduce the oscillation frequency.
  • the light sensing module 50 may also be a semiconductor device made of the same photoelectric effect as the photodiode PD, and is not limited to the photodiode.
  • the charge output module 30 includes a control switch Sc, one end of the control switch Sc is connected to the inverting input end of the integrator IN1, and the other end is used to access a fixed current source, and the control end of the control switch Sc is used to access a comparison signal Dout and change the switch state based on the comparison signal Dout, so that the charge output module 30 switches back and forth between the first working state and the second working state.
  • control switch Sc may be a MOS tube, and the control end of the control switch Sc is the gate of the MOS tube.
  • the control switch Sc is an NMOS tube
  • the control switch Sc when the comparison signal Dout is at a high level, the control switch Sc is closed, that is, the charge output module 30 is in the first working state, and when the comparison signal Dout is at a low level, the control switch Sc is disconnected, that is, the charge output module 30 is in the second working state.
  • the control switch Sc may also be an electronic component with a switch function, such as a PMOS tube or an IGBT.
  • the charge output module 30 when the charge output module 30 is in the first working state, it provides charges to the integration module 40 and the light sensing module 50 at the same time.
  • the control switch Sc when the control switch Sc is closed, the charge output module 30 provides charges to the integration module 40 and the light sensing module 50 at the same time, and after the control switch Sc is disconnected, only the integration module 40 provides charges to the light sensing module 50, and the currents of the charge output module 30 and the light sensing module 50 are stable.
  • I1 is the current of the light sensing module 50, that is, the fixed current output by the fixed current source
  • I2 is the current of the charge output module 30
  • T1 is the closing time of the control switch Sc
  • T2 is the opening time of the control switch Sc.
  • the time T2 when the control switch Sc is disconnected refers to the time corresponding to the disconnection of the control switch Sc in the working state, and does not include the time corresponding to the disconnection of the control switch Sc when the entire circuit is not in the working state.
  • the time T1 when the control switch Sc is closed refers to the high level time of the comparison signal Dout
  • the time T2 when the control switch Sc is opened refers to the low level time of the comparison signal Dout.
  • control switch Sc can also be connected to a current source with a variable current magnitude, and the amount of charge output after the control switch Sc is closed can be obtained by integration.
  • FIG. 5 shows another pulse signal timing diagram of the optical sensor readout circuit in an embodiment of the present application. Since the phase difference between the reference signal F REF and the oscillation signal F RET is usually not a fixed value and there is an extremely small phase difference, in some embodiments of the present application, the comparison module 20 can filter out smaller phase differences to avoid the comparison signal Dout frequently causing the control switch Sc to open or close.
  • Figure 6 shows another pulse signal timing diagram of the optical sensor readout circuit in the embodiment of the present application
  • Figure 7 shows a schematic diagram of the high-level time measurement of the comparison signal Dout in the embodiment of the present application.
  • the phase difference between the reference signal F REF and the oscillation signal F RET is usually not a fixed value (for example, the phase difference t1, t2, t3 shown in Figure 6)
  • a high-frequency reference signal with a fixed period can be compared with the comparison signal Dout, and the number of pulses of the high-frequency reference signal corresponding to the high-level time of the comparison signal Dout is measured by a counter (for example, N1, N2, N3 as shown in Figure 7), and the high-level time of the comparison signal Dout can be obtained by multiplying the number of pulses by the fixed period of the high-frequency reference signal, that is, the time T1 when the control switch Sc is closed or the time T2 when the control switch Sc is opened.
  • the above method of measuring the pulse number of the high-frequency reference signal may cause a certain error in measuring the high-level time of the comparison signal Dout because the pulse number of the high-frequency reference signal corresponding to the high-level time of the comparison signal Dout may not be a complete number.
  • Figure 8 shows another module structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application
  • Figure 9 shows another circuit structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application
  • Figure 10 shows another pulse signal timing diagram of the optical sensor readout circuit in the embodiment of the present application
  • the comparison module 20 includes a phase comparison submodule 21 and a pulse width adjustment submodule 22.
  • the phase comparison submodule 21 is used to compare the phase difference between the reference signal F REF and the oscillation signal F RET , and output a signal to be processed out, the pulse width of the signal to be processed out is equal to the phase difference between the oscillation signal F RET and the reference signal F REF .
  • the pulse width adjustment submodule 22 is used to adjust the pulse width of the signal to be processed out to generate a comparison signal Dout with a fixed pulse width T.
  • a counter can be used to measure the number of pulses of the comparison signal Dout and calculate the value of the comparison signal Dout.
  • the product of the number of pulses and the corresponding fixed pulse width can be used to obtain the closing time T1 of the control switch Sc, thereby accurately measuring the high level time of the comparison signal Dout and ensuring the accuracy of the current measurement of the photodiode PD.
  • the comparison module 20 includes a phase comparison submodule 21 and a pulse width adjustment submodule 22
  • I1 is the current of the light sensor module 50
  • I2 is the current of the charge output module 30
  • T is the fixed pulse width of the comparison signal Dout
  • N is the number of times the control switch Sc is closed within a unit time (eg, 1 second).
  • the number of times N that the control switch Sc is closed can be obtained by counting the number of pulses of the comparison signal Dout through a counter. It can be understood that the pulse width adjustment submodule 22 adjusts the high level time of the comparison signal Dout. For some embodiments of the present application, for example, for an embodiment in which the control switch Sc is a PMOS tube, the pulse width adjustment submodule 22 can also adjust the low level time of the comparison signal Dout.
  • the phase comparison submodule 21 includes a first trigger DT1, a second trigger DT2, a first AND gate AND1, and a first delay device De
  • the pulse width adjustment submodule 22 includes a pulse generator PR.
  • the control end of the first trigger DT1 is used to access the reference signal F REF
  • the input end of the first trigger DT1 is used to access the working voltage VDD
  • the output end of the first trigger DT1 is connected to the first input end of the first AND gate AND1.
  • the control end of the second trigger DT2 is used to access the oscillation signal F RET , the input end of the second trigger DT2 is used to access the working voltage VDD, and the output end of the first trigger DT1 is connected to the second input end of the first AND gate AND1.
  • the input end of the first delay device De is connected to the output end of the first AND gate AND1, and the reset end of the first trigger DT1 and the reset end of the second trigger DT2 are connected to the output end of the delay device.
  • the input end of the pulse generator PR is connected to the output end of the first trigger DT1 or the second trigger DT2, and the output end of the pulse generator PR is connected to the control end of the control switch Sc.
  • the first AND gate AND1 when there is a time difference (i.e., phase difference) between the rising edges of the signals inputted into the first trigger DT1 and the second trigger DT2, the first AND gate AND1 will control the reset ends of the first trigger DT1 and the second trigger DT2 to reset the trigger states, so that the first trigger DT1 generates a high-level signal corresponding to the signal to be processed out. From the state of the first trigger DT1 to the next rising edge, it corresponds to the low level signal of the signal to be processed out, thereby generating the signal to be processed out associated with the phase difference between the oscillation signal F RET and the reference signal F REF .
  • the first delay device De can delay the time when the output signal of the first AND gate AND1 controls the reset state of the first trigger DT1 and the second trigger DT2, so that a small phase difference can be filtered out to avoid the phenomenon of frequent system response.
  • the signal to be processed out is a signal output from the output terminal of the first trigger DT1.
  • the signal to be processed out can also be a signal output from the output terminal of the second trigger DT2.
  • the charge output module 30 can only provide charge to the integration module 40 in the first working state.
  • Figure 11 shows another module structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application
  • Figure 12 shows another circuit structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application
  • Figure 13 shows another pulse signal timing diagram of the optical sensor readout circuit in the embodiment of the present application.
  • the integration module 40 includes an integrator IN1
  • the optical sensor module 50 includes a photodiode PD.
  • the charge output module 30 includes a first sub-switch S01 and a second sub-switch S02.
  • the in-phase input terminal of the integrator IN1 is used to access the first preset voltage V1, and the output terminal of the integrator IN1 is connected to the oscillation module 10.
  • One end of the second sub-switch S02 is connected to the inverting input terminal of the integrator IN1, and the other end is connected to the negative electrode of the photodiode PD, and the positive electrode of the photodiode PD is used for grounding.
  • One end of the first sub-switch S01 is used to access the working voltage VDD, and the other end is connected to the third node M3 between the second sub-switch S02 and the inverting input terminal of the integrator IN1.
  • the control end of the first sub-switch S01 is used to access the comparison signal Dout and change the switch state based on the comparison signal Dout, and the switch state of the first sub-switch S01 is opposite to the switch state of the second sub-switch S02.
  • the switching state of the first sub-switch S01 is opposite to the switching state of the second sub-switch S02
  • the charge output module 30 when the charge output module 30 is in the first working state, only the charge amount Q is provided to the integration module 40, and when the charge output module 30 is in the second working state, the integration module 40 provides the same amount of charge Q to the light sensor module 50.
  • the charge amount output by the charge output module 30 is still equal to the charge amount flowing through the light sensor module 50.
  • I1 is the current of the light sensing module 50
  • I2 is the current of the charge output module 30
  • t01 is the time when the first sub-switch S01 is closed
  • t02 is the time when the second sub-switch S02 is opened.
  • the closing time of the first sub-switch S01 and the opening time of the second sub-switch S02 are both t01
  • the opening time of the first sub-switch S01 and the closing time of the second sub-switch S02 are both t02
  • t01 can refer to the high level time of the comparison signal Dout
  • t02 can refer to the low level time of the comparison signal Dout
  • the first sub-switch S01 and the second sub-switch S02 can be MOS tubes, such as PMOS tubes or NMOS tubes.
  • the comparison module 20 includes a first trigger DT1, a second trigger DT2, a first AND gate AND1 and a first delay device De.
  • the control end of the first trigger DT1 is used to access the reference signal F REF
  • the input end of the first trigger DT1 is used to access the working voltage VDD
  • the output end of the first trigger DT1 is connected to the first input end of the first AND gate AND1.
  • the control end of the second trigger DT2 is used to access the oscillation signal F RET
  • the input end of the second trigger DT2 is used to access the working voltage VDD
  • the output end of the first trigger DT1 is connected to the second input end of the first AND gate AND1.
  • the input end of the first delay device De is connected to the output end of the first AND gate AND1, and the reset end of the first trigger DT1 and the reset end of the second trigger DT2 are connected to the output end of the delay device.
  • the control end of the first sub-switch S01 is connected to the output end of the first trigger DT1.
  • the second sub-switch S02 can be controlled by inverting the comparison signal Dout using an inverter. Under the control of the signal output by the first trigger DT1, the switching states of the first sub-switch S01 and the second sub-switch S02 are opposite, that is, when one is open, the other is closed.
  • one of the first sub-switch S01 and the second sub-switch S02 can be an NMOS tube and the other can be a PMOS tube, that is, the output signal of only one of the first trigger DT1 and the second trigger DT2 can be used to simultaneously control the first sub-switch S01 and the second sub-switch S02.
  • the current ratio of the light sensing module 50 to the charge output module 30 ranges from 1:5000 to 1:100, so as to use the current of the charge output module 30 with a larger current value to measure the current of the light sensing module 50 with a smaller current value.
  • FIG. 14 shows another circuit structure diagram of the light sensor readout circuit in the embodiment of the present application
  • FIG. 15 shows another pulse signal timing diagram of the light sensor readout circuit in the embodiment of the present application, wherein the charge output module 30 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a control capacitor Cc.
  • One end of the first switch S1 is connected to the control capacitor Cc. The first end is connected, and the other end is used to access the second preset voltage V2.
  • One end of the second switch S2 is connected to the second end of the control capacitor Cc, and the other end is connected to the inverting input end of the integrator IN1.
  • One end of the third switch S3 is connected to the first node M1 between the first switch S1 and the control capacitor Cc, and the other end is used for grounding.
  • One end of the fourth switch S4 is connected to the second node M2 between the second switch S2 and the control capacitor Cc, and the other end is used to access the first preset voltage V1.
  • control ends of the first switch S1 and the second switch S2 are used to access the comparison signal Dout, and change the switch state based on the comparison signal Dout;
  • control ends of the third switch S3 and the fourth switch S4 are used to access the control signal Dout2 which is inverted with the comparison signal Dout, and change the switch state based on the control signal Dout2.
  • I1 is the current of the light sensor module 50
  • Cc is the capacitance value of the control capacitor Cc
  • V1 is the first preset voltage V1
  • V2 is the second preset voltage V2
  • N is the number of times the second switch S2 is closed within a unit time (eg, 1 second).
  • the number of times the second switch S2 is closed can be obtained by counting the number of pulses of the comparison signal Dout by a counter.
  • the comparison module 20 includes a first trigger DT1, a second trigger DT2, a first AND gate AND1, a first delay device De, and a first inverter PI0.
  • the control end of the first trigger DT1 is used to access the reference signal F REF
  • the input end of the first trigger DT1 is used to access the working voltage VDD
  • the output end of the first trigger DT1 is connected to the first input end of the first AND gate AND1.
  • the control end of the second trigger DT2 is used to access the oscillation signal F RET , the input end of the second trigger DT2 is used to access the working voltage VDD, and the output end of the first trigger DT1 is connected to the second input end of the first AND gate AND1.
  • the input end of the first delay device De is connected to the output end of the first AND gate AND1, and the reset end of the first trigger DT1 and the reset end of the second trigger DT2 are connected to the output end of the delay device.
  • the input end of the first inverter PI0 is connected to the first trigger DT2.
  • the control ends of the first switch S1 and the second switch S2 are connected to the output end of the first trigger DT1, and the control ends of the third switch S3 and the fourth switch S4 are connected to the output end of the first inverter PI0.
  • the signals controlling the switching states of the first switch S1 and the second switch S2 and the third switch S3 and the fourth switch S4 are inverted, when the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are all PMOS tubes or NMOS tubes, under the control of the signals output by the first trigger DT1 and the second trigger DT2, the switching states of the first switch S1 and the second switch S2 are opposite to the switching states of the third switch S3 and the fourth switch S4.
  • first switch S1 and the second switch S2 can also use NMOS tubes, while the third switch S3 and the fourth switch S4 can use PMOS tubes, and the control ends of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 can be connected to the output end of the first trigger DT1.
  • the rising edge of the control signal Dout2 and the falling edge of the comparison signal Dout are not at the same time, and the falling edge of the control signal Dout2 and the rising edge of the comparison signal Dout are not at the same time, so as to avoid the phenomenon of simultaneously turning on or off the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.
  • FIG. 16 shows another circuit structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application
  • FIG. 17 shows another circuit structure schematic diagram of the optical sensor readout circuit in the embodiment of the present application, wherein the comparison module includes a first resistor R1, a first comparator op, an equivalent capacitor Ct, a fifth switch S5, and a sixth switch S6.
  • the first resistor R1, the fifth switch S5, and the equivalent capacitor Ct are connected in series in sequence, and the end of the first resistor R1 away from the fifth switch S5 is used to access the working voltage, and the end of the equivalent capacitor Ct away from the fifth switch S5 is used to ground.
  • One end of the sixth switch S6 is connected to the fourth node M4 between the fifth switch S5 and the equivalent capacitor Ct, and the other end is used to ground.
  • the inverting input end of the first comparator op is used to access the third preset voltage V div , the non-inverting input end of the first comparator op is connected to the fifth node M5 between the first resistor R1 and the fifth switch S5, and the output end of the first comparator op is used to output a comparison signal.
  • the control end of the fifth switch S5 is used to access the oscillation signal FRET and change the switch state based on the oscillation signal FRET .
  • the switch state of the sixth switch S6 is opposite to the switch state of the fifth switch S5.
  • the equivalent capacitor Ct, the fifth switch S5 and the sixth switch S6 form an equivalent resistor
  • the third preset voltage Vdiv is the reference signal.
  • the in-phase of the first comparator op is The lower the input voltage V f2v , when the voltage at the non-inverting input terminal of the first comparator op is lower than the third preset voltage V div , the first comparator op outputs a low level signal; conversely, when the frequency of the oscillation signal is lower, the higher the non-inverting input voltage V f2v of the first comparator op, when the voltage at the non-inverting input terminal of the first comparator op is higher than the third preset voltage Vdiv , the first comparator op outputs a low level signal or a high level signal.
  • the comparison signal Dout output by the first comparator op can directly control the control switch Sc to change the switch state.
  • the comparison signal Dout output by the first comparator op can directly control the first switch S1, the second switch S2, the second switch S3, and the third switch S4.
  • the fifth switch S5 and the sixth switch S6 can both be PMOS tubes or NMOS tubes, and the oscillation signal F RET controls the first switch S5, and the oscillation signal F RET is inverted to control the sixth switch S6, so that the fifth switch S5 and the sixth switch S6 are inverted.
  • the third preset voltage V div can be generated by dividing the first resistor R1 and the resistor RT as shown in Figure 16 or Figure 17, or it can be generated by other methods, such as providing a power supply voltage separately.
  • the above embodiment uses an equivalent capacitor Ct, the fifth switch S5 and the sixth switch S6 to form an equivalent resistor for voltage comparison.
  • the equivalent capacitor Ct, the fifth switch S5 and the sixth switch S6 can also be used to form an equivalent resistor for current comparison to output the comparison signal Dout.
  • the oscillation module 10 includes a ring oscillator and an acceleration switch Sv.
  • the ring oscillator includes a plurality of inverters PI connected in series in a ring shape, and the control end of the acceleration switch Sv is connected to the output end of the integrator IN1.
  • One end of the acceleration switch Sv is used to access the working voltage VDD, and the other end is connected to the power supply end of the inverter PI.
  • the acceleration switch Sv When the acceleration switch Sv is turned on, the charging rate of the capacitors between the inverters PI is increased, so that the plurality of inverters PI connected in series in a ring shape accelerate the oscillation and increase the oscillation frequency of the oscillation signal F RET ; and when the acceleration switch Sv is turned off, the charging rate of the capacitors between the inverters PI is reduced, which correspondingly causes the plurality of inverters PI connected in series in a ring shape to reduce the oscillation frequency and reduce the oscillation frequency of the oscillation signal F RET .
  • the acceleration switch Sv is a PMOS tube.
  • the oscillation module 10 can also include a level converter LS to convert the high level voltage of the signal output by the ring oscillator into the working voltage VDD.
  • control capacitor Cc and the capacitor C0 of the integrator can be Variable capacitance to facilitate current measurement for different types of photodiodes.
  • control capacitor Cc and the capacitor C0 of the integrator adopt fixed capacitors; for example, the acceleration switch Sv adopts an NMOS tube or an IGBT tube.
  • the present application also provides a chip, the chip includes the optical sensor readout circuit described in any of the above embodiments. Since the chip in the embodiment of the present application includes the optical sensor readout circuit in the above embodiment, it has all the beneficial effects of the optical sensor readout circuit in the above embodiment, which will not be repeated here.
  • the present application uses specific words to describe the embodiments of the present application.
  • “one embodiment”, “an embodiment”, and/or “some embodiments” refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that “one embodiment” or “an embodiment” or “an alternative embodiment” mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment.
  • some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.
  • numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the words “approximately”, “approximately” or “substantially” in some examples. Unless otherwise stated, “about”, “approximately” or “substantially” indicates that the number is allowed to vary by ⁇ 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may vary according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the settings of such numerical values are as accurate as possible within the feasible range.

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Abstract

一种光传感器读出电路以及芯片，用于读出光传感模块(50)的电流，光传感器读出电路包括震荡模块(10)、比较模块(20)、电荷输出模块(30)以及积分模块(40)，震荡模块(10)用于输出震荡信号(F RET)，比较模块(20)用于比较参考信号(F REF)与震荡信号(F RET)并输出比较信号(Dout)，电荷输出模块(30)用于根据比较信号(Dout)输出电荷，积分模块(40)用于根据电荷输出模块(30)输出的电荷改变震荡模块(10)的震荡频率，其中电荷输出模块(30)输出的电荷量等于通过光传感模块(50)的电荷量，光传感器读出电路可以准确地计量光传感模块(50)的电流，克服了光传感模块(50)光生电流较小而难以通过常规的电流检测方法进行检测的难题。

Description

光传感器读出电路以及芯片 技术领域
本申请涉及集成电路技术领域，具体涉及一种光传感器读出电路以及包括光传感器读出电路的芯片。
背景技术
光传感器可以感知周围光线的强度，并告知处理芯片自动调节显示器背光亮度，降低产品的功耗。例如，在手机、笔记本、平板电脑等移动应用中，屏幕消耗的电量高达电池总电量的30％，采用光传感器采集环境光强度并调节屏幕的亮度，不仅可以最大限度地延长电池的工作时间，同时使得屏幕亮度随环境亮度改变，有利于使屏幕提供柔和的画面。然而，光传感器光生电流较小，难以通过常规的电流检测方法检测电流。
发明内容
本申请提供一种光传感器读出电路以及芯片，旨在解决目前光传感器电流较小难以检测的技术问题。
第一方面，本申请提供一种光传感器读出电路，用于读出光传感模块的电流，包括：
震荡模块，震荡模块用于输出震荡信号；
比较模块，比较模块用于比较参考信号与震荡信号并输出比较信号；
电荷输出模块，电荷输出模块用于根据所述比较信号输出电荷；
积分模块，积分模块用于根据所述电荷输出模块输出的电荷改变所述震荡模块的震荡频率；
其中，所述电荷输出模块输出的电荷量等于通过所述光传感模块的电荷量。
在一些实施例中，电荷输出模块的控制端与比较模块的输出端连接，电荷输出模块用于根据比较信号交替地输出电荷；积分模块的输入端与电荷输 出模块的输出端连接，积分模块的输出端与震荡模块的控制端连接，积分模块用于根据电荷输出模块输出的电荷改变震荡模块的震荡频率；光传感模块与积分模块连接；其中，在积分模块接收到电荷输出模块输出的电荷后，积分模块输出电荷至光传感模块，且电荷输出模块输出的电荷量等于通过光传感模块的电荷量。
在一些实施例中，电荷输出模块根据比较信号交替地输出电荷；
积分模块根据电荷输出模块交替输出的电荷交替地控制震荡模块的震荡频率增大或减小；
其中，在积分模块接收到电荷输出模块输出的电荷后，积分模块输出电荷至光传感模块。
在一些实施例中，电荷输出模块具有第一工作状态以及第二工作状态，电荷输出模块基于比较信号在第一工作状态与第二工作状态之间来回切换；
当电荷输出模块处于第一工作状态时，电荷输出模块向积分模块提供电荷，积分模块基于积累的电荷控制震荡模块提高震荡频率；
当电荷输出模块处于第二工作状态时，电荷输出模块停止向积分模块提供电荷，且积分模块向光传感模块释放电荷。
在一些实施例中，光传感模块与电荷输出模块连接，当电荷输出模块处于第一工作状态时，电荷输出模块同时向积分模块和光传感模块提供电荷；
当电荷输出模块处于第二工作状态时，电荷输出模块停止向积分模块和光传感模块提供电荷。
在一些实施例中，积分模块包括积分器，光传感模块包括光电二极管；
积分器的反相输入端与光电二极管的负极连接，积分器的同相输入端用于接入第一预设电压，积分器的输出端与震荡模块连接，光电二极管的正极用于接地。
在一些实施例中，电荷输出模块包括控制开关；
控制开关的一端与积分器的反相输入端连接，另外一端用于接入固定电流源，控制开关的控制端用于接入比较信号并基于比较信号改变开关状态，以使得电荷输出模块在第一工作状态于第二工作状态之间来回切换。
在一些实施例中，光传感模块的电流满足如下关系式：
I1＝I2*T1/(T1+T2)
其中，I1为光传感模块的电流，I2为电荷输出模块的电流，T1为控制开关闭合的时间，T2为控制开关断开的时间。
在一些实施例中，比较模块包括相位比较子模块以及脉冲宽度调整子模块；
相位比较子模块用于比较参考信号与震荡信号的相位差，并输出待处理信号，待处理信号的脉冲宽度等于震荡信号与参考信号的相位差；
脉冲宽度调整子模块用于调节待处理信号的脉冲宽度，以生成具有固定脉冲宽度的比较信号。
在一些实施例中，光传感模块的电流满足如下关系式：
I1＝I2*T*N
其中，I1为光传感模块的电流，I2为电荷输出模块的电流，T为比较信号的固定脉冲宽度，N为单位时间内控制开关闭合的次数。
在一些实施例中，相位比较子模块包括第一触发器、第二触发器、第一与门以及第一延时器，脉冲宽度调整子模块包括脉冲发生器；
第一触发器的控制端用于接入参考信号，第一触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第一输入端连接；
第二触发器的控制端用于接入震荡信号，第二触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第二输入端连接；
第一延时器的输入端与第一与门的输出端连接，第一触发器的重置端和第二触发器的重置端与延时器的输出端连接；
脉冲发生器的输入端与第一触发器或者第二触发器的输出端连接，脉冲发生器的输出端与控制开关的控制端连接。
在一些实施例中，积分模块包括积分器，光传感模块包括光电二极管；
电荷输出模块包括第一子开关以及第二子开关；
积分器的同相输入端用于接入第一预设电压，积分器的输出端与震荡模块连接；
第二子开关的一端与积分器的反相输入端连接，另外一端与光电二极管的负极连接，光电二极管的正极用于接地；
第一子开关的一端用于接入工作电压，另外一端连接于第二子开关与积分器的反相输入端之间的第三节点；
其中，第一子开关的控制端用于接入比较信号并基于比较信号改变开关状态，且第一子开关的开关状态与第二子开关的开关状态相反。
在一些实施例中，光传感模块的电流满足如下关系式：
I1＝I2*t01/t02
其中，I1为光传感模块的电流，I2为电荷输出模块的电流，t01为第一子开关闭合的时间，t02为第二子开关断开的时间。
在一些实施例中，比较模块包括第一触发器、第二触发器、第一与门以及第一延时器；
第一触发器的控制端用于接入参考信号，第一触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第一输入端连接；
第二触发器的控制端用于接入震荡信号，第二触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第二输入端连接；
第一延时器的输入端与第一与门的输出端连接，第一触发器的重置端和第二触发器的重置端与延时器的输出端连接；
第一子开关的控制端与第一触发器的输出端连接。
在一些实施例中，其特征在于，光传感模块的电流与电荷输出模块的电流比值范围为1:5000至1:100。
在一些实施例中，电荷输出模块包括第一开关、第二开关、第三开关、第四开关以及控制电容；
第一开关的一端与控制电容的第一端连接，另外一端用于接入第二预设电压；
第二开关的一端与控制电容的第二端连接，另外一端与积分器的反相输入端连接；
第三开关的一端连接于第一开关与控制电容之间的第一节点，另外一端用于接地；
第四开关的一端连接于第二开关与控制电容之间的第二节点，另外一端用于第一预设电压；
其中，第一开关和第二开关的控制端用于接入比较信号，并基于比较信号改变开关状态；第三开关和第四开关的控制端用于接入与比较信号反相的控制信号，并基于控制信号改变开关状态。
在一些实施例中，光传感模块的电流满足如下关系式：
I1＝Cc*V2*N
其中，I1为光传感模块的电流，Cc为控制电容的电容值，V1为第一预设电压，V2为第二预设电压，N为单位时间内第二开关闭合的次数。
在一些实施例中，比较模块包括第一触发器、第二触发器、第一与门、第一延时器以及第一反相器；
第一触发器的控制端用于接入参考信号，第一触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第一输入端连接；
第二触发器的控制端用于接入震荡信号，第二触发器的输入端用于接入工作电压，第一触发器的输出端与第一与门的第二输入端连接；
第一延时器的输入端与第一与门的输出端连接，第一触发器的重置端和第二触发器的重置端与延时器的输出端连接；
第一反相器的输入端与第一触发器的输出端连接；
第一开关和第二开关的控制端与第一触发器的输出端连接，第三开关和第四开关的控制端与第一反相器的输出端连接。
在一些实施例中，比较模块包括第一电阻、第一比较器、等效电容、第五开关、第六开关；
第一电阻、第五开关以及等效电容依次串联，第一电阻背离第五开关的一端用于接入工作电压，等效电容背离第五开关的一端用于接地；
第六开关的一端连接于第五开关与等效电容之间的第四节点，另外一端用于接地；
第一比较器的反相输入端用于接入第三预设电压，第一比较器的同相输入端连接于第一电阻与第五开关之间的第五节点，第一比较器的输出端用于输出比较信号；
其中，第五开关的控制端用于接入震荡信号，并基于震荡信号改变开关状态，第六开关的开关状态与第五开关的开关状态相反。
在一些实施例中，震荡模块包括环形震荡器以及加速开关；
环形震荡器包括多个环形串接的反相器，加速开关的控制端与积分器的输出端连接；
加速开关的一端用于接入工作电压，另外一端与反相器的电源端连接。
第二方面，本申请提供一种芯片，包括如第一方面所述的光传感器读出电路。
本申请利用比较模块比较参考信号与震荡信号并生成比较信号，通过比较信号使得电荷输出模块交替地输出电荷，而积分模块则可以根据变化的电荷量交替地控制震荡模块的震荡频率增大或减小。
由于在上述交替过程中参考信号以及震荡信号动态平衡，因此比较模块能够持续地输出比较信号，又由于积分模块在动态改变震荡模块的震荡频率时其平均流入的电荷量等于0，从而使得电荷输出模块输出的电荷量等于通过光传感模块的电荷量，因此只需根据比较信号(例如比较信号的高电平时间与光传感模块电流的乘积)即可实现对流过光传感模块电荷量的累计计量，并计算出光传感模块的电流，最终通过光传感模块的电流与光强度的关系得到光线强度。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例中提供的光传感器读出电路的一种模块结构示意图；
图2是本申请实施例中提供的光传感器读出电路的一种电路结构示意图；
图3是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图；
图4是本申请实施例中提供的光传感器读出电路的一种脉冲信号时序图；
图5是本申请实施例中提供的光传感器读出电路的一种脉冲信号时序图；
图6是本申请实施例中提供的光传感器读出电路的一种脉冲信号时序图；
图7是本申请实施例中提供的比较信号的高电平时间计量的一种示意图；
图8是本申请实施例中提供的光传感器读出电路的一种模块结构示意图；
图9是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图；
图10是本申请实施例中提供的光传感器读出电路的另一种脉冲信号时 序图；
图11是本申请实施例中提供的光传感器读出电路的一种模块结构示意图；
图12是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图；
图13是本申请实施例中提供的光传感器读出电路的另一种脉冲信号时序图；
图14是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图；
图15是本申请实施例中提供的光传感器读出电路的另一种脉冲信号时序图；
图16是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图；
图17是本申请实施例中提供的光传感器读出电路的另一种电路结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有 明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本发明，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本发明。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本发明的描述变得晦涩。因此，本发明并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
本申请实施例提供一种光传感器读出电路以及芯片，以下分别进行详细说明。
首先，参阅图1，图1示出了本申请实施例中光传感器读出电路的一种模块结构示意图，光传感器读出电路用于读出光传感模块50的电流，其中光传感器读出电路包括：
震荡模块10，震荡模块10用于输出震荡信号FRET；
比较模块20，比较模块20用于比较参考信号FREF与震荡信号FRET并输出比较信号Dout；
电荷输出模块30，电荷输出模块30的控制端与比较模块20的输出端连接，电荷输出模块30用于根据比较信号Dout交替地输出电荷；
积分模块40，积分模块40的输入端与电荷输出模块30的输出端连接，积分模块40的输出端与震荡模块10的控制端连接，积分模块40用于根据电荷输出模块30交替输出的电荷交替地控制震荡模块10的震荡频率增大或减小；
光传感模块50，光传感模块50与积分模块40连接；
其中，积分模块40接收到电荷输出模块30输出的电荷后，积分模块40输出电荷至光传感模块50，且电荷输出模块30输出的电荷量等于通过光传感模块50的电荷量。
具体地，震荡模块10用于将直流电压信号转换为具有一定频率的交流电压信号(例如正弦波或方波信号)，震荡模块10的震荡频率可以被积分模块40控制并改变，从而使得震荡模块10输出的震荡信号FRET与参考信号FREF的相位差改变。示例性地，震荡模块10的震荡激励方式可以为自激震荡方式、 他激震荡方式，例如震荡模块10可以包括阻容震荡器、电感电容震荡器、晶体震荡器、音叉震荡器等。
比较模块20用于比较参考信号FREF与震荡信号FRET并输出比较信号Dout，以便于电荷输出模块30根据比较信号Dout交替地输出电荷。在本申请的一些实施例中，比较模块20可以比较参考信号FREF与震荡信号FRET的相位差。在本申请的另外一些实施例中，比较模块20可以比较参考信号FREF与震荡信号FRET的频率。示例性地，比较模块20可以包括鉴频鉴相器、门鉴相器或三态鉴相器等。
在本申请的一些实施例中，比较模块20的第一输入端用于接入参考信号FREF，第二输入端与震荡模块的输出端连接，以便于接入震荡信号FRET。可以理解地，参考信号FREF也可以为比较模块20自身所产生的，例如采用震荡器产生该参考信号。
电荷输出模块30用于根据比较信号Dout交替地输出电荷，以使得积分模块40根据变化的电荷量交替地控制震荡模块10的震荡频率增大或减小。在本申请的一些实施例中，电荷输出模块30具有第一工作状态以及第二工作状态，电荷输出模块30基于比较信号Dout在第一工作状态与第二工作状态之间来回切换，从而使得电荷输出模块30交替地输出电荷。示例性地，电荷输出模块30的第一工作状与第二工作状态之间的交替切换可以通过开关实现，例如提供一固定电流源，当开关闭合时，电荷输出模块30向积分模块40输入电荷；而当开关处于关闭状态时，电荷输出模块30则停止向积分模块40输入电荷，通过固定电流与开关闭合时间的乘积即可计算电荷输出模块30输出的电荷量。
可以理解地，电荷输出模块30也可以通过一开关控制电流值变化的电流源，通过对变化的电流积分从而计算得到对应的电荷量。
积分模块40可以根据变化的电荷量交替地控制震荡模块10的震荡频率增大或减小。具体地，积分模块40可以根据电荷输出模块30交替输出的电荷交替地控制震荡模块10的震荡频率增大或减小，在积分模块40接收到电荷输出模块30输出的电荷后，积分模块40输出电荷至光传感模块50。在本申请的一些实施例中，例如对于电荷输出模块30具有第一工作状态以及第二工作状态的实施例，当电荷输出模块30处于第一工作状态时，电荷输出模块30向积 分模块40提供电荷，积分模块40基于积累的电荷控制震荡模块10提高震荡频率；当电荷输出模块30处于第二工作状态时，电荷输出模块30停止向积分模块40提供电荷，且积分模块40向光传感模块50释放电荷，积分模块40基于释放的电荷控制震荡模块10减小震荡频率。
在本申请的一些实施例中，例如对于比较模块可以比较参考信号FREF与震荡信号FRET的相位差的实施例，当电荷输出模块30处于第一工作状态时，电荷输出模块30向积分模块40提供电荷，积分模块40基于积累的电荷控制震荡模块10提高震荡频率，以减小输入信号FREF与反馈信号FRET的相位差；当电荷输出模块30处于第二工作状态时，电荷输出模块30停止向积分模块40提供电荷，且积分模块40向光传感模块50释放电荷，积分模块40基于释放的电荷控制震荡模块10减小震荡频率，以扩大输入信号FREF与反馈信号FRET的相位差。
在上述过程中，由于震荡模块10的震荡频率交替地增大或减小，使得输入信号FREF与反馈信号FRET保持对应的相位差，从而使得比较模块20持续地输出与相位差关联的比较信号Dout，保证光传感器读出电路在非稳态的情况下进行电流计量。
需要说明的是，积分模块40在上述第一工作状态和第二工作状态工作过程中，由于其不能流过电荷，因此在多次第一工作状态和第二工作状态交替过程中电荷输出模块30累计向积分模块40输出的电荷量等于积分模块40向光传感模块50释放的电荷。
作为一示例性地，参阅图2，图2示出了本申请实施例中光传感器读出电路的一种电路结构示意图，其中，积分模块40包括电容C，其一端与电荷输出模块30连接，另外一端与震荡模块10，在电荷输出模块30向电容C充电时，电容一端极板积累电荷，另外一端极板电压逐渐降低并控制震荡模块10提高震荡频率，从而使得参考信号FREF与震荡信号FRET相位差减小；而在电荷输出模块30停止向电容C充电时，电容一端极板积累的电荷则向光传感模块50释放，而另外一端极板电压逐渐升高并控制震荡模块10降低震荡频率，从而使得参考信号FREF与震荡信号FRET相位差增大。
在本申请实施例中，利用比较模块20比较参考信号FREF与震荡信号FRET并生成比较信号Dout，通过比较信号Dout使得电荷输出模块30交替地输出电 荷，而积分模块40则可以根据变化的电荷量交替地控制震荡模块10的震荡频率增大或减小。
由于在上述交替过程中参考信号FREF以及震荡信号FRET动态平衡，因此比较模块20能够持续地输出比较信号Dout，又由于积分模块40在动态改变震荡模块10的震荡频率时其平均流入的电荷量等于0，从而使得电荷输出模块30输出的电荷量等于通过光传感模块50的电荷量，因此只需根据比较信号Dout(例如比较信号Dout的高电平时间与电荷输出模块30固定电流的乘积)即可实现对流过光传感模块50电荷量的累计计量，并计算出光传感模块50的电流，最终通过光传感模块50的电流与光强度的关系得到光线强度。
在本申请的一些实施例中，参阅图1、图3以及图4，图3示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，图4示出了本申请实施例中光传感器读出电路的一种脉冲信号时序图，其中，光传感模块50连接于电荷输出模块30与积分模块40之间，即光传感模块50与电荷输出模块30的输出端连接，并与积分模块40的输入端连接，当电荷输出模块30处于第一工作状态时，电荷输出模块30同时向积分模块40和光传感模块50提供电荷；当电荷输出模块30处于第二工作状态时，电荷输出模块30停止向积分模块40和光传感模块50提供电荷。也就是说，在第一工作状态时电荷输出模块30分别向光传感模块50和积分模块40提供电荷量Q1和电荷量Q2，而在第二工作状态时积分模块40累计的电荷量Q2则流向了光传感模块50，因此电荷输出模块30输出的累计电荷量Q等于流过光传感模块50的电荷量，即等于电荷量Q1和电荷量Q2之和。
在本申请的一些实施例中，例如对于光传感模块50连接于电荷输出模块30与积分模块40之间的实施例，继续参阅图1、图3以及图4，积分模块40包括积分器IN1，光传感模块50包括光电二极管PD。积分器IN1的反相输入端与光电二极管PD的负极连接，积分器IN1的同相输入端用于接入第一预设电压V1，积分器IN1的输出端与震荡模块10连接，光电二极管PD的正极用于接地。
需要说明的是，积分模块40采用积分器IN1，第一方面积分器IN1的正相输入端和反相输入端由于虚短特性电压相等，因此可以保证光电二极管PD的电压稳定，避免光电二极管PD由于电压波动而导致光生电流产生变化的现 象，第二方面积分器IN1的电容C0不能通过电荷，保证电荷输出模块30输出的电荷量等于光电二极管PD流过的电流，同时在第三方面，积分器IN1受到电容C0电荷量的变化输出线性的电压信号Vout，从而便于控制震荡模块10提高震荡频率或者而减小震荡频率。
可以理解地，光传感模块50还可以采用与光电二极管PD相同光电效应制成的半导体器件，并不局限于光电二极管。
进一步地，在本申请的一些实施例中，继续参阅图1、图3以及图4，电荷输出模块30包括控制开关Sc，控制开关Sc的一端与积分器IN1的反相输入端连接，另外一端用于接入固定电流源，控制开关Sc的控制端用于接入比较信号Dout并基于比较信号Dout改变开关状态，以使得电荷输出模块30在第一工作状态与第二工作状态之间来回切换。
示例性地，控制开关Sc可以为MOS管，控制开关Sc的控制端即MOS管的栅极，例如，当控制开关Sc为NMOS管时，比较信号Dout为高电平时则使得控制开关Sc闭合，即电荷输出模块30处于第一工作状态，而当比较信号Dout为低电平时则使得控制开关Sc断开，即电荷输出模块30处于第二工作状态。可以理解地，控制开关Sc还可以为PMOS管或者IGBT等具有开关功能的电子元件。
在本申请的一些实施例中，例如对于当电荷输出模块30处于第一工作状态时其同时向积分模块40和光传感模块50提供电荷的实施例，继续参阅图1、图3以及图4，由于在控制开关Sc闭合时，电荷输出模块30同时向积分模块40和光传感模块50提供电荷，而在控制开关Sc断开后，仅有积分模块40向光传感模块50提供电荷，同时电荷输出模块30和光传感模块50的电流稳定，根据电荷守恒原理光传感模块50的电流满足如下关系式：
I1＝I2*T1/(T1+T2)       (1)
其中，I1为光传感模块50的电流，即固定电流源输出的固定电流大小，I2为电荷输出模块30的电流，T1为控制开关Sc闭合的时间，T2为控制开关Sc断开的时间。
需要说明的是，控制开关Sc断开的时间T2是指工作状态下控制开关Sc断开所对应的时间，并不包含整体电路非工作状态时控制开关Sc断开所对应的时间。对于本申请的一些实施例中，例如对于控制开关Sc为NMOS管的实 施例，控制开关Sc闭合的时间T1是指比较信号Dout的高电平时间，控制开关Sc断开的时间T2是指比较信号Dout的低电平时间。
可以理解地，控制开关Sc也可以接入电流大小变化的电流源，通过积分得到控制开关Sc闭合后所输出的电荷量。
进一步地，参阅图5，图5示出了本申请实施例中光传感器读出电路的另一种脉冲信号时序图，由于参考信号FREF与震荡信号FRET的相位差通常不是固定值，且存在极小的相位差，在本申请的一些实施例中，比较模块20可以滤除较小的相位差，以避免比较信号Dout频繁地使控制开关Sc断开或闭合。
进一步地，继续参阅图6以及图7，图6示出了本申请实施例中光传感器读出电路的另一种脉冲信号时序图，图7示出了本申请实施例中比较信号Dout的高电平时间计量的一种示意图，对于参考信号FREF与震荡信号FRET的相位差通常不是固定值的情况(例如如图6所示相位差t1、t2、t3)，可以将具有固定周期的高频参考信号与比较信号Dout进行比对，通过计数器计量比较信号Dout高电平时间内对应的高频参考信号的脉冲次数(例如如图7所示的N1、N2、N3)，并将该脉冲次数与高频参考信号的固定周期乘积即可得到比较信号Dout的高电平时间，也即控制开关Sc闭合的时间T1或控制开关Sc断开的时间T2。
然而，上述计量高频参考信号的脉冲次数的方式，由于比较信号Dout高电平时间内对应的高频参考信号的脉冲次数可能并非完整的个数，从而使得比较信号Dout高电平时间计量存在一定的误差。
为此，进一步参阅图8、9以及图10，图8示出了本申请实施例中光传感器读出电路的另一种模块结构示意图，图9示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，图10示出了本申请实施例中光传感器读出电路的另一种脉冲信号时序图，其中，比较模块20包括相位比较子模块21以及脉冲宽度调整子模块22。相位比较子模块21用于比较参考信号FREF与震荡信号FRET的相位差，并输出待处理信号out，待处理信号out的脉冲宽度等于震荡信号FRET与参考信号FREF的相位差。脉冲宽度调整子模块22用于调节待处理信号out的脉冲宽度，以生成具有固定脉冲宽度T的比较信号Dout。
需要说明的是，由于脉冲宽度调整子模块22生成了具有固定脉冲宽度的比较信号Dout，因此可以进采用计数器计量比较信号Dout的脉冲次数，并将 该脉冲次数与对应固定脉冲宽度乘积即可得到控制开关Sc闭合的时间T1，进而使得比较信号Dout高电平时间计量准确，保证光电二极管PD电流测量的准确性。
进一步地，在本申请的一些实施例中，例如对于比较模块20包括相位比较子模块21以及脉冲宽度调整子模块22的实施例，光传感模块50的电流满足如下关系式：
I1＝I2*T*N    (2)
其中，I1为光传感模块50的电流，I2为电荷输出模块30的电流，T为比较信号Dout的固定脉冲宽度，N为单位时间(例如1秒)内控制开关Sc闭合的次数。
需要说明的是，控制开关Sc闭合的次数N可以通过计数器计量比较信号Dout的脉冲次数得到。可以理解地，上述脉冲宽度调整子模块22调整的是比较信号Dout的高电平时间，对于本申请的一些实施例中，例如对于控制开关Sc为PMOS管的实施例，脉冲宽度调整子模块22还可以调整比较信号Dout的低电平时间。
进一步地，在本申请的一些实施例中，继续参阅图9以及图10，其中，相位比较子模块21包括第一触发器DT1、第二触发器DT2、第一与门AND1以及第一延时器De，脉冲宽度调整子模块22包括脉冲发生器PR。第一触发器DT1的控制端用于接入参考信号FREF，第一触发器DT1的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第一输入端连接。第二触发器DT2的控制端用于接入震荡信号FRET，第二触发器DT2的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第二输入端连接。第一延时器De的输入端与第一与门AND1的输出端连接，第一触发器DT1的重置端和第二触发器DT2的重置端与延时器的输出端连接。脉冲发生器PR的输入端与第一触发器DT1或者第二触发器DT2的输出端连接，脉冲发生器PR的输出端与控制开关Sc的控制端连接。
需要说明的是，由于第一与门AND1的存在，在第一触发器DT1和第二触发器DT2输入的信号上升沿存在时间差(即相位差)时，第一与门AND1将控制第一触发器DT1和第二触发器DT2的重置端重置触发器状态，从而第一触发器DT1对应产生了对应待处理信号out的高电平信号，在重置第一触发 器DT1状态后至下一上升沿到来前，则对应了待处理信号out的低电平信号，从而产生了震荡信号FRET与参考信号FREF的相位差关联的待处理信号out。而第一延时器De可以延迟第一与门AND1输出信号控制第一触发器DT1和第二触发器DT2重置状态的时间，因此可以滤除较小的相位差，避免系统频繁响应的现象。
可以理解地，在上述实施例中待处理信号out为第一触发器DT1输出端输出的信号，实际上，对于本申请的一些实施例，例如对于控制开关Sc为PMOS管的实施例，待处理信号out还可以为第二触发器DT2输出端输出的信号。
在本申请的另外一些实施例中，电荷输出模块30在第一工作状态可以仅向积分模块40提供电荷，例如参阅图11、图12以及图13，图11示出了本申请实施例中光传感器读出电路的另一种模块结构示意图，图12示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，图13示出了本申请实施例中光传感器读出电路的另一种脉冲信号时序图，积分模块40包括积分器IN1，光传感模块50包括光电二极管PD。电荷输出模块30包括第一子开关S01以及第二子开关S02。积分器IN1的同相输入端用于接入第一预设电压V1，积分器IN1的输出端与震荡模块10连接。第二子开关S02的一端与积分器IN1的反相输入端连接，另外一端与光电二极管PD的负极连接，光电二极管PD的正极用于接地。第一子开关S01的一端用于接入工作电压VDD，另外一端连接于第二子开关S02与积分器IN1的反相输入端之间的第三节点M3。其中，第一子开关S01的控制端用于接入比较信号Dout并基于比较信号Dout改变开关状态，且第一子开关S01的开关状态与第二子开关S02的开关状态相反。
需要说明的是，在上述实施例中，由于第一子开关S01的开关状态与第二子开关S02的开关状态相反，因此在电荷输出模块30处于第一工作状态时仅向积分模块40提供电荷量Q，而电荷输出模块30处于第二工作状态时，则积分模块40向光传感模块50提供等量的电荷量Q，在该电路结构下，电荷输出模块30输出的电荷量依然等于流过光传感模块50的电荷量，同时，光传感模块50的电流满足如下关系式：
I1＝I2*t01/t02    (3)
其中，I1为光传感模块50的电流，I2为电荷输出模块30的电流，t01为第一子开关S01闭合的时间，t02为第二子开关S02断开的时间。
可以理解地，第一子开关S01闭合的时间和第二子开关S02的断开的时间均为t01，第一子开关S01断开的时间和第二子开关S02的闭合的时间均为t02，t01可以是指比较信号Dout的高电平时间，t02可以是指比较信号Dout的低电平时间，第一子开关S01与第二子开关S02可以为MOS管，例如PMOS管或者NMOS管。
进一步地，继续参阅图11、图12以及图13，比较模块20包括第一触发器DT1、第二触发器DT2、第一与门AND1以及第一延时器De。第一触发器DT1的控制端用于接入参考信号FREF，第一触发器DT1的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第一输入端连接。第二触发器DT2的控制端用于接入震荡信号FRET，第二触发器DT2的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第二输入端连接。第一延时器De的输入端与第一与门AND1的输出端连接，第一触发器DT1的重置端和第二触发器DT2的重置端与延时器的输出端连接。第一子开关S01的控制端与第一触发器DT1的输出端连接。
需要说明的是，在第一子开关S01和第二子开关S02同为NMOS管或PMOS管时，只需采用反相器将比较信号Dout反相即可控制第二子开关S02，在第一触发器DT1输出的信号的控制下，第一子开关S01与第二子开关S02的开关状态相反，即一者断开时另外一者闭合。
可以理解地，第一子开关S01与第二子开关S02还可以一者为NMOS管，而另外一者为PMOS管，即可以只采用第一触发器DT1与第二触发器DT2中一者的输出信号同时控制第一子开关S01与第二子开关S02。
在本申请的一些实施例中，光传感模块50的电流与电荷输出模块30的电流比值范围为1:5000至1:100，以便于利用电流值较大的电荷输出模块30的电流测量电流值较小的光传感模块50的电流。
在本申请的一些实施例中，例如对于当电荷输出模块30处于第一工作状态时电荷输出模块30同时向积分模块40和光传感模块50提供电荷的实施例，参阅图14以及图15，图14示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，图15示出了本申请实施例中光传感器读出电路的另一种脉冲信号时序图，其中，电荷输出模块30包括第一开关S1、第二开关S2、第三开关S3、第四开关S4以及控制电容Cc。第一开关S1的一端与控制电容Cc的 第一端连接，另外一端用于接入第二预设电压V2。第二开关S2的一端与控制电容Cc的第二端连接，另外一端与积分器IN1的反相输入端连接。第三开关S3的一端连接于第一开关S1与控制电容Cc之间的第一节点M1，另外一端用于接地。第四开关S4的一端连接于第二开关S2与控制电容Cc之间的第二节点M2，另外一端用于接入第一预设电压V1。其中，第一开关S1和第二开关S2的控制端用于接入比较信号Dout，并基于比较信号Dout改变开关状态；第三开关S3和第四开关S4的控制端用于接入与比较信号Dout反相的控制信号Dout2，并基于控制信号Dout2改变开关状态。
需要说明的是，当电荷输出模块30处于第二工作状态时，第一开关S1和第二开关S2处于断开状态，而第三开关S3和第四开关S4处于闭合状态，控制电容Cc邻近第二开关S2的极板积累电荷量为：-Cc*V1，而当电荷输出模块30处于第一工作状态时，第一开关S1和第二开关S2处于闭合状态，而第三开关S3和第四开关S4处于断开状态，控制电容Cc邻近第二开关S2的极板所积累电荷量为：Cc*(V2-V1)，从而使得电荷输出模块30输出的电荷量为：Cc*V2，因此光传感模块50的电流满足如下关系式：
I1＝Cc*V2*N    (4)
其中，I1为光传感模块50的电流，Cc为控制电容Cc的电容值，V1为第一预设电压V1，V2为第二预设电压V2，N为单位时间(例如1秒)内第二开关S2闭合的次数。
可以理解地，第二开关S2闭合的次数可以通过计数器计量比较信号Dout的脉冲次数即可得到。
进一步地，在本申请的一些实施例中，继续参阅图14以及图15，其中，比较模块20包括第一触发器DT1、第二触发器DT2、第一与门AND1、第一延时器De以及第一反相器PI0。第一触发器DT1的控制端用于接入参考信号FREF，第一触发器DT1的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第一输入端连接。第二触发器DT2的控制端用于接入震荡信号FRET，第二触发器DT2的输入端用于接入工作电压VDD，第一触发器DT1的输出端与第一与门AND1的第二输入端连接。第一延时器De的输入端与第一与门AND1的输出端连接，第一触发器DT1的重置端和第二触发器DT2的重置端与延时器的输出端连接。第一反相器PI0的输入端与第一触 发器DT1的输出端连接。第一开关S1和第二开关S2的控制端与第一触发器DT1的输出端连接，第三开关S3和第四开关S4的控制端与第一反相器PI0的输出端连接。
需要说明的是，由于控制第一开关S1和第二开关S2与第三开关S3和第四开关S4开关状态的信号反相，因此在第一开关S1、第二开关S2、第三开关S3、第四开关S4同为PMOS管或者NMOS管时，在第一触发器DT1和第二触发器DT2输出的信号的控制下，第一开关S1和第二开关S2的开关状态与第三开关S3和第四开关S4的开关状态相反。
可以理解地，第一开关S1和第二开关S2还可以采用NMOS管，而第三开关S3和第四开关S4和第四开关S4采用PMOS管，并将第一开关S1、第二开关S2第三开关S3和第四开关S4的控制端与第一触发器DT1的输出端连接即可。
在本申请的一些实施例中，控制信号Dout2的上升沿与比较信号Dout的下降沿不处于同一时刻，控制信号Dout2的下降沿与比较信号Dout的上升沿不处于同一时刻，以避免同时开启或关闭第一开关S1、第二开关S2、第三开关S3和第四开关S4的现象。
在本申请的一些实施例中，例如对于比较模块20可以比较参考信号FREF与震荡信号FRET的频率的实施例，参阅图16以及图17，图16示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，图17示出了本申请实施例中光传感器读出电路的另一种电路结构示意图，其中，比较模块包括第一电阻R1、第一比较器op、等效电容Ct、第五开关S5、第六开关S6。第一电阻R1、第五开关S5以及等效电容Ct依次串联，第一电阻R1背离第五开关S5的一端用于接入工作电压，等效电容Ct背离第五开关S5的一端用于接地。第六开关S6的一端连接于第五开关S5与等效电容Ct之间的第四节点M4，另外一端用于接地。第一比较器op的反相输入端用于接入第三预设电压Vdiv，第一比较器op的同相输入端连接于第一电阻R1与第五开关S5之间的第五节点M5，第一比较器op的输出端用于输出比较信号。其中，第五开关S5的控制端用于接入震荡信号FRET，并基于震荡信号FRET改变开关状态，第六开关S6的开关状态与第五开关S5的开关状态相反。
具体地，等效电容Ct、第五开关S5以及第六开关S6组成等效电阻，第三预设电压Vdiv即参考信号，当震荡信号的频率越高时，第一比较器op的同相 输入端电压Vf2v越低，当第一比较器op同相输入端的电压低于第三预设电压Vdiv时，则第一比较器op输出低电平信号；反之，当震荡信号的频率越低时，第一比较器op的同相输入端电压Vf2v越高，第一比较器op同相输入端的电压高于第三预设电压Vdiv时，则第一比较器op输出低电平信号输出高电平信号。
在本申请的一些实施例中，例如对于电荷输出模块30包括控制开关Sc的实施例，参阅图16，第一比较器op输出的比较信号Dout可以直接控制该控制开关Sc改变开关状态。在本申请的另外一些实施例中，例如对于电荷输出模块30包括控制电容Cc的实施例，参阅图17，第一比较器op输出的比较信号Dout可以直接控制第一开关S1、第二开关S2、第二开关S3以及第三开关S4。
可以理解地，第五开关S5、第六开关S6可以同为PMOS管或NMOS管，将震荡信号FRET控制第一开关S5，而将震荡信号FRET反相控制第六开关S6，即可使得第五开关S5以及第六开关S6反相。此外，第三预设电压Vdiv可以如图16或图17所示由第一电阻R1与电阻RT分压产生，也可以通过其他方式产生，例如单独提供电源电压。
需要说明的是，上述实施例采用等效电容Ct、第五开关S5以及第六开关S6组成等效电阻进行电压比较，实际上，还可以采用等效电容Ct、第五开关S5以及第六开关S6组成等效电阻进行电流比较等方式输出比较信号Dout。
在本申请的一些实施例中，参阅图2、图3或图12，震荡模块10包括环形震荡器以及加速开关Sv。环形震荡器包括多个环形串接的反相器PI，加速开关Sv的控制端与积分器IN1的输出端连接。加速开关Sv的一端用于接入工作电压VDD，另外一端与反相器PI的电源端连接。当加速开关Sv被导通，反相器PI之间的电容充电速率提高，从而使得多个环形串接的反相器PI加速震荡并提高震荡信号FRET的震荡频率；而加速开关Sv被断开后，反相器PI之间的电容充电速率降低，则对应使得多个环形串接的反相器PI降低震荡频率并降低震荡信号FRET的震荡频率。
示例性地，加速开关Sv为PMOS管，当积分器的输出信号Vout电压降低后，加速开关Sv则被导通，反之则加速开关Sv则被断开。可以理解地，震荡模块10还可以包括电平转换器LS，以便于将环形震荡器输出的信号高电平电压转换为工作电压VDD。
在本申请的一些实施例中，控制电容Cc以及积分器的电容C0可以采用可 变电容，以便于针对不同型号的光电二极管进行电流测量。
值得注意的是，上述关于光传感器读出电路的内容旨在清楚说明本申请的实施验证过程，本领域技术人员在本申请的指导下可以做出等同的修改设计，控制电容Cc以及积分器的电容C0采用固定电容；又例如，加速开关Sv采用NMOS管或者IGBT管。
进一步地，为了更好的实施本申请实施例中的光传感器读出电路，在光传感器读出电路的基础上，本申请还提供一种芯片，芯片包括上述任一实施例所述的光传感器读出电路。由于本申请实施例中的芯片包含上述实施例中的光传感器读出电路，因此具备上述实施例中光传感器读出电路的全部有益效果，在此不再赘述。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。
上文已对基本概念做了描述，显然，对于本领域技术人员来说，上述详细披露仅仅作为示例，而并不构成对本申请的限定。虽然此处并没有明确说明，本领域技术人员可能会对本申请进行各种修改、改进和修正。该类修改、改进和修正在本申请中被建议，所以该类修改、改进、修正仍属于本申请示范实施例的精神和范围。
同时，本申请使用了特定词语来描述本申请的实施例。如“一个实施例”、“一实施例”、和/或“一些实施例”意指与本申请至少一个实施例相关的某一特征、结构或特点。因此，应强调并注意的是，本说明书中在不同位置两次或多次提及的“一实施例”或“一个实施例”或“一个替代性实施例”并不一定是指同一实施例。此外，本申请的一个或多个实施例中的某些特征、结构或特点可以进行适当的组合。
同理，应当注意的是，为了简化本申请披露的表述，从而帮助对一个或多个发明实施例的理解，前文对本申请实施例的描述中，有时会将多种特征归并至一个实施例、附图或对其的描述中。但是，这种披露方法并不意味着本申请对象所需要的特征比权利要求中提及的特征多。实际上，实施例的特征要少于上述披露的单个实施例的全部特征。
一些实施例中使用了描述成分、属性数量的数字，应当理解的是，此类用于实施例描述的数字，在一些示例中使用了修饰词“大约”、“近似”或“大体 上”来修饰。除非另外说明，“大约”、“近似”或“大体上”表明所述数字允许有±20％的变化。相应地，在一些实施例中，说明书和权利要求中使用的数值参数均为近似值，该近似值根据个别实施例所需特点可以发生改变。在一些实施例中，数值参数应考虑规定的有效数位并采用一般位数保留的方法。尽管本申请一些实施例中用于确认其范围广度的数值域和参数为近似值，在具体实施例中，此类数值的设定在可行范围内尽可能精确。
针对本申请引用的每个专利、专利申请、专利申请公开物和其他材料，如文章、书籍、说明书、出版物、文档等，特此将其全部内容并入本申请作为参考，但与本申请内容不一致或产生冲突的申请历史文件除外，对本申请权利要求最广范围有限制的文件(当前或之后附加于本申请中的)也除外。需要说明的是，如果本申请附属材料中的描述、定义、和/或术语的使用与本申请所述内容有不一致或冲突的地方，以本申请的描述、定义和/或术语的使用为准。
以上对本申请实施例所提供的一种光传感器读出电路以及芯片进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种光传感器读出电路，用于读出光传感模块的电流，所述光传感器读出电路包括：
    震荡模块，用于输出震荡信号；
    比较模块，用于比较参考信号与所述震荡信号并输出比较信号；
    电荷输出模块，用于根据所述比较信号输出电荷；
    积分模块，用于根据所述电荷输出模块输出的电荷改变所述震荡模块的震荡频率，
    其中，所述电荷输出模块输出的电荷量等于通过所述光传感模块的电荷量。
  2. 如权利要求1所述的光传感器读出电路，其中，所述电荷输出模块根据所述比较信号交替地输出电荷；
    所述积分模块根据所述电荷输出模块交替输出的电荷交替地控制所述震荡模块的震荡频率增大或减小；
    所述积分模块在所述电荷输出模块输出电荷期间积累电荷，并在所述电荷输出模块停止输出电荷期间经所述光传感模块释放所积累的电荷。
  3. 如权利要求2所述的光传感器读出电路，其中，所述电荷输出模块具有第一工作状态以及第二工作状态，所述电荷输出模块基于所述比较信号在所述第一工作状态与所述第二工作状态之间来回切换；
    当所述电荷输出模块处于第一工作状态时，所述电荷输出模块向所述积分模块提供电荷，所述积分模块基于积累的电荷控制所述震荡模块提高震荡频率；
    当所述电荷输出模块处于第二工作状态时，所述电荷输出模块停止向所述积分模块提供电荷，且所述积分模块向所述光传感模块释放电荷，所述积分模块基于释放的电荷控制所述震荡模块减小震荡频率。
  4. 如权利要求3所述的光传感器读出电路，其中，所述光传感模块与所 述电荷输出模块的输出端连接，当所述电荷输出模块处于第一工作状态时，所述电荷输出模块同时向所述积分模块和所述光传感模块提供电荷；
    当所述电荷输出模块处于第二工作状态时，所述电荷输出模块停止向所述积分模块和所述光传感模块提供电荷。
  5. 如权利要求4所述的光传感器读出电路，其中，所述积分模块包括积分器，所述光传感模块包括光电二极管；
    所述积分器的反相输入端与所述光电二极管的负极连接，所述积分器的同相输入端用于接入第一预设电压，所述积分器的输出端与所述震荡模块连接，所述光电二极管的正极用于接地。
  6. 如权利要求5所述的光传感器读出电路，其中，所述电荷输出模块包括控制开关；
    所述控制开关的一端与所述积分器的反相输入端连接，另外一端用于接入固定电流源，所述控制开关的控制端用于接入所述比较信号并基于所述比较信号改变开关状态，以使得所述电荷输出模块在所述第一工作状态于所述第二工作状态之间来回切换。
  7. 如权利要求6所述的光传感器读出电路，其中，所述光传感模块的电流满足如下关系式：
    I1＝I2*T1/(T1+T2)
    其中，I1为所述光传感模块的电流，I2为所述电荷输出模块的电流，T1为所述控制开关闭合的时间，T2为所述控制开关断开的时间。
  8. 如权利要求6所述的光传感器读出电路，其中，所述比较模块包括相位比较子模块以及脉冲宽度调整子模块；
    所述相位比较子模块用于比较所述参考信号与所述震荡信号的相位差，并输出待处理信号，所述待处理信号的脉冲宽度等于所述震荡信号与所述参考信号的相位差；
    所述脉冲宽度调整子模块用于调节所述待处理信号的脉冲宽度，以生成 具有固定脉冲宽度的比较信号。
  9. 如权利要求8所述的光传感器读出电路，其中，所述光传感模块的电流满足如下关系式：
    I1＝I2*T*N
    其中，I1为所述光传感模块的电流，I2为所述电荷输出模块的电流，T为所述比较信号的固定脉冲宽度，N为单位时间内所述控制开关闭合的次数。
  10. 如权利要求8所述的光传感器读出电路，其中，所述相位比较子模块包括第一触发器、第二触发器、第一与门以及第一延时器，所述脉冲宽度调整子模块包括脉冲发生器；
    所述第一触发器的控制端用于接入所述参考信号，所述第一触发器的输入端用于接入所述工作电压，所述第一触发器的输出端与所述第一与门的第一输入端连接；
    所述第二触发器的控制端用于接入所述震荡信号，所述第二触发器的输入端用于接入所述工作电压，所述第一触发器的输出端与所述第一与门的第二输入端连接；
    所述第一延时器的输入端与所述第一与门的输出端连接，所述第一触发器的重置端和所述第二触发器的重置端与所述延时器的输出端连接；
    所述脉冲发生器的输入端与所述第一触发器或者所述第二触发器的输出端连接，所述脉冲发生器的输出端与所述控制开关的控制端连接。
  11. 如权利要求3所述的光传感器读出电路，其中，所述积分模块包括积分器，所述光传感模块包括光电二极管；
    所述电荷输出模块包括第一子开关以及第二子开关；
    所述积分器的同相输入端用于接入第一预设电压，所述积分器的输出端与所述震荡模块连接；
    所述第二子开关的一端与所述积分器的反相输入端连接，另外一端与所述光电二极管的负极连接，所述光电二极管的正极用于接地；
    所述第一子开关的一端用于接入工作电压，另外一端连接于所述第二子 开关与所述积分器的反相输入端之间的第三节点；
    其中，所述第一子开关的控制端用于接入所述比较信号并基于所述比较信号改变开关状态，且所述第一子开关的开关状态与所述第二子开关的开关状态相反。
  12. 如权利要求11所述的光传感器读出电路，其中，所述光传感模块的电流满足如下关系式：
    I1＝I2*t01/t02
    其中，I1为所述光传感模块的电流，I2为所述电荷输出模块的电流，t01为所述第一子开关闭合的时间，t02为所述第二子开关断开的时间。
  13. 如权利要求12所述的光传感器读出电路，其中，所述比较模块包括第一触发器、第二触发器、第一与门以及第一延时器；
    所述第一触发器的控制端用于接入所述参考信号，所述第一触发器的输入端用于接入所述工作电压，所述第一触发器的输出端与所述第一与门的第一输入端连接；
    所述第二触发器的控制端用于接入所述震荡信号，所述第二触发器的输入端用于接入所述工作电压，所述第一触发器的输出端与所述第一与门的第二输入端连接；
    所述第一延时器的输入端与所述第一与门的输出端连接，所述第一触发器的重置端和所述第二触发器的重置端与所述延时器的输出端连接；
    所述第一子开关的控制端与所述第一触发器的输出端连接。
  14. 如权利要求7、9或12任一项所述的光传感器读出电路，其中，所述光传感模块的电流与所述电荷输出模块的电流比值范围为1：5000至1:100。
  15. 如权利要求5所述的光传感器读出电路，其中，所述电荷输出模块包括第一开关、第二开关、第三开关、第四开关以及控制电容；
    所述第一开关的一端与所述控制电容的第一端连接，另外一端用于接入第二预设电压；
    所述第二开关的一端与所述控制电容的第二端连接，另外一端与所述积分器的反相输入端连接；
    所述第三开关的一端连接于所述第一开关与所述控制电容之间的第一节点，另外一端用于接地；
    所述第四开关的一端连接于所述第二开关与所述控制电容之间的第二节点，另外一端用于第一预设电压；
    其中，所述第一开关和所述第二开关的控制端用于接入所述比较信号，并基于所述比较信号改变开关状态；所述第三开关和所述第四开关的控制端用于接入与所述比较信号反相的控制信号，并基于所述控制信号改变开关状态。
  16. 如权利要求15所述的光传感器读出电路，其中，所述光传感模块的电流满足如下关系式：
    I1＝Cc*V2*N
    其中，I1为所述光传感模块的电流，Cc为所述控制电容的电容值，V2为所述第二预设电压，N为单位时间内所述第二开关闭合的次数。
  17. 如权利要求15所述的光传感器读出电路，其中，所述比较模块包括第一触发器、第二触发器、第一与门、第一延时器以及第一反相器；
    所述第一触发器的控制端用于接入所述参考信号，所述第一触发器的输入端用于接入工作电压，所述第一触发器的输出端与所述第一与门的第一输入端连接；
    所述第二触发器的控制端用于接入所述震荡信号，所述第二触发器的输入端用于接入工作电压，所述第一触发器的输出端与所述第一与门的第二输入端连接；
    所述第一延时器的输入端与所述第一与门的输出端连接，所述第一触发器的重置端和所述第二触发器的重置端与所述延时器的输出端连接；
    所述第一反相器的输入端与所述第一触发器的输出端连接；
    所述第一开关和所述第二开关的控制端与所述第一触发器的输出端连接，所述第三开关和所述第四开关的控制端与所述第一反相器的输出端连接。
  18. 如权利要求4所述的光传感器读出电路，其中，所述比较模块包括第一电阻、第一比较器、等效电容、第五开关、第六开关；
    所述第一电阻、所述第五开关以及所述等效电容依次串联，所述第一电阻背离所述第五开关的一端用于接入工作电压，所述等效电容背离所述第五开关的一端用于接地；
    所述第六开关的一端连接于所述第五开关与所述等效电容之间的第四节点，另外一端用于接地；
    所述第一比较器的反相输入端用于接入第三预设电压，所述第一比较器的同相输入端连接于所述第一电阻与所述第五开关之间的第五节点，所述第一比较器的输出端用于输出所述比较信号；
    其中，所述第五开关的控制端用于接入所述震荡信号，并基于所述震荡信号改变开关状态，所述第六开关的开关状态与所述第五开关的开关状态相反。
  19. 如权利要求5或11所述的光传感器读出电路，其中，所述震荡模块包括环形震荡器以及加速开关；
    所述环形震荡器包括多个环形串接的反相器，所述加速开关的控制端与所述积分器的输出端连接；
    所述加速开关的一端用于接入所述工作电压，另外一端与所述反相器的电源端连接。
  20. 一种芯片，包括如权利要求1至19任一项所述的光传感器读出电路。
PCT/CN2023/092685 2022-12-05 2023-05-08 光传感器读出电路以及芯片 WO2024119710A1 (zh)

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