WO2024119709A1 - 支持tws耳机双向通讯的单芯片充电仓电路方法及设备 - Google Patents

支持tws耳机双向通讯的单芯片充电仓电路方法及设备 Download PDF

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Publication number
WO2024119709A1
WO2024119709A1 PCT/CN2023/092593 CN2023092593W WO2024119709A1 WO 2024119709 A1 WO2024119709 A1 WO 2024119709A1 CN 2023092593 W CN2023092593 W CN 2023092593W WO 2024119709 A1 WO2024119709 A1 WO 2024119709A1
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Prior art keywords
soc chip
charging
pin
chip
pins
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PCT/CN2023/092593
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English (en)
French (fr)
Inventor
林俊盛
黄悦
伍博
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深圳英集芯科技股份有限公司
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Publication of WO2024119709A1 publication Critical patent/WO2024119709A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R1/00—Details of transducers, loudspeakers or microphones
    • H04R1/10—Earpieces; Attachments therefor ; Earphones; Monophonic headphones
    • H04R1/1041—Mechanical or electronic switches, or control elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R3/00—Circuits for transducers, loudspeakers or microphones
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
    • H04R2420/00—Details of connection covered by H04R, not provided for in its groups
    • H04R2420/05—Detection of connection of loudspeakers or headphones to amplifiers

Definitions

  • the present invention relates to the field of electronic devices, and in particular to a single-chip charging case circuit method and device that supports two-way communication of TWS headsets.
  • the TWS charging compartment circuit is mainly composed of a charging module, a main control module, and a discharge module, which are used to realize the basic functions of charging the compartment and storing energy, and discharging the headset.
  • a charging module a main control module
  • a discharge module which are used to realize the basic functions of charging the compartment and storing energy, and discharging the headset.
  • many designs use a circuit design of 1 main control chip with 1 charging and discharging function "2" in "1" chip, or a circuit design of 1 main control chip with charging function and 1 boost discharge chip.
  • This charging compartment circuit that uses 2 chips to realize basic functions will occupy more PCB area, increase design difficulty, and increase manufacturing cost.
  • the embodiments of the present invention provide a single-chip charging case circuit and control method that support two-way communication of TWS headphones, which can improve the reliability, integration and communication efficiency of the case and have the advantage of reducing costs.
  • an embodiment of the present invention provides a single-chip charging compartment circuit supporting two-way communication of TWS headsets, including: a SOC chip, a battery, a Hall module, and a button module.
  • the single-chip charging compartment circuit supporting two-way communication of TWS headsets also includes: an inductor and a pair of headphone interfaces; wherein,
  • the LX pin of the SOC chip is connected to one end of the inductor, and the other end of the inductor is connected to the battery.
  • the inductor is used to provide a boost signal
  • the power output VOUT pin of the SOC chip is connected to the positive electrodes of the earphone L and the earphone R respectively, providing charging voltage and communication level for the earphone L and the earphone R, the negative electrode of the earphone L is connected to one end of the pull-down resistor L, and the other end of the pull-down resistor L is grounded, the negative electrode of the earphone R is connected to one end of the pull-down resistor R, and the other end of the pull-down resistor R is grounded, the negative electrode of the earphone L is connected to the PH_L pin of the SOC chip and to one end of the current limiting resistor L, and the other end of the current limiting resistor L is the output signal IO_L port, the negative electrode of the earphone R is connected to the PH_R pin of the SOC chip R and to one end of the current limiting resistor R, and the other end of the current limiting resistor R is the output signal IO_R port;
  • the VIN pin of the SOC chip is connected to the charging input port
  • the BAT pin of the SOC chip is connected to the positive pole of the battery
  • the negative pole of the battery is grounded
  • the inductor is also connected to the positive pole of the battery.
  • a control method for the single-chip charging compartment circuit supporting two-way communication of TWS headsets provided in the first aspect comprising:
  • the power SOC chip controls the combination state of the VOUT, PH_L, PH_R, IO_L, and IO_R pins to provide the headset with an open cover timing to wake up the headset; when it is detected that the charging case lid switches from the open state to the closed state, the power SOC chip controls the combination state of the VOUT, PH_L, PH_R, IO_L, and IO_R pins to provide the headset with a closed cover timing, turn off the headset Bluetooth, and then discharge the headset.
  • an electronic device comprising the single-chip charging case circuit supporting two-way communication of TWS headphones according to the first aspect.
  • a computer-readable storage medium wherein a computer program is stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the method provided in the first aspect is executed.
  • the technical solution provided in this application supports the charging case circuit for two-way communication of TWS earphones. It has a built-in linear charging function, does not require an external charging chip, can dynamically adjust the charging current, and meet the needs of segmented current control in various scenarios; it has a built-in 5V boost function, does not require an external boost chip, and can realize the function of discharging the earphones.
  • the boost and case charging paths are separated and will not affect each other; the two contacts of the earphones are reused to achieve flexible switching between 5V charging and 3.3V ⁇ 1.8V communication levels, reduce the number of openings for the earphones and the charging case, reduce the path for interference introduction, and improve overall reliability; the use of 3.3V ⁇ 1.8V communication levels can be compatible with SOC chips with wider operating voltages, and no boost is required during the communication process, reducing losses; the SOC chip can directly switch to output 3.3V ⁇ 1.8V communication levels in the 5V output path, does not require an external MOS as a path management, and does not require an external LDO to assist in providing a constant communication level; it has a built-in programmable unit, which can achieve deep customization of power control, communication, and display.
  • the present invention has a high integration level, can save PCB area and components, greatly reduce product costs, and at the same time increase the product's two-way communication function and ensure overall performance.
  • FIG1 is a schematic diagram of the structure of a single-chip charging compartment circuit supporting two-way communication of TWS headsets provided by the present application;
  • FIG2 is a schematic diagram of the structure of a single-chip charging compartment circuit supporting two-way communication of TWS headsets provided by the present application;
  • FIG3 is a connection circuit diagram of a Hall switch provided by the present application.
  • FIG4 is a circuit diagram of a headphone jack connection provided for the present application.
  • FIG5 is a schematic diagram of a light display control circuit provided by the present application.
  • FIG6 is a schematic diagram illustrating waveforms at both ends of the right earphone in two-way communication after the charging case cover is opened provided in the present application.
  • the charging bin will be referred to as “bin” in the following embodiments.
  • the single-chip charging compartment circuit supporting two-way communication of TWS headsets includes: a power SOC chip (hereinafter referred to as SOC chip), a battery, a Hall module, and a button module.
  • SOC chip a power SOC chip
  • the circuit may further include: an inductor and a pair of headphone jacks.
  • LX is a pin of the power SOC chip, which is responsible for providing the input of the boost signal in conjunction with the inductor
  • BAT is a pin of the power SOC chip, which is responsible for providing the battery interface of the charging compartment
  • VIN is a pin of the power SOC chip, which is responsible for the input of the 5V charging voltage
  • IO is a group of pins of the power SOC chip, which can be used for digital signal input, output and analog-to-digital conversion.
  • KEY is a pin of the power SOC chip, which is responsible for parsing the key signal
  • EN is a pin of the power SOC chip, which is responsible for parsing the Hall signal
  • VOUT is a pin of the power SOC chip, which is responsible for providing the charging voltage and communication level to the positive electrode of the earphone
  • PH_L and PH_R are pins of the power SOC chip, which are interfaces of the negative electrodes of the earphone L and the earphone R, and are responsible for the charging path switch and current sampling of the earphone
  • IO_L and IO_R are pins of the power SOC chip or internal interfaces that can be mapped to PH_L and PH_R, which are responsible for sending and receiving two-way communications in the compartment
  • GND is a pin of the power SOC chip, which is connected to the ground of the system.
  • the LX pin of the SOC chip is connected to one end of the inductor, and the other end of the inductor is connected to the battery.
  • the inductor is used to provide a boost signal.
  • the power output VOUT pin of the SOC chip (i.e., the positive electrode interface of a pair of headphone interfaces) is connected to the positive electrodes of the headphone L and the headphone R respectively, providing charging voltage and communication level for the headphone L and the headphone R, the negative electrode of the headphone L is connected to one end of the pull-down resistor L, and the other end of the pull-down resistor L is grounded, the negative electrode of the headphone R is connected to one end of the pull-down resistor R, and the other end of the pull-down resistor R is grounded, the negative electrode of the headphone L is connected to the PH_L pin of the SOC chip (i.e., a negative electrode interface of a pair of headphone interfaces) and connected to one end of the current limiting resistor L, and the other end of the current limiting resistor L is the output signal IO_L port, the negative electrode of the headphone R is connected to the PH_R pin of the SOC chip (i.e., a negative electrode interface of
  • the VIN pin of the SOC chip is connected to the charging input (5V)
  • the BAT pin of the SOC chip is connected to the positive pole of the battery
  • the negative pole of the battery is grounded
  • the inductor is also connected to the positive pole of the battery.
  • the technical solution of the charging bin supporting two-way communication of TWS headsets with the circuit structure shown in FIG. 1 may specifically include:
  • the battery powers it through the BAT pin.
  • inserting VIN can also power the chip to keep it in working condition.
  • the linear charging function will control the current size of the 5V charging input and charge the charging compartment through BAT.
  • the pin supplies power to the battery.
  • the current size of the above constant current charging stage can be realized in real time by configuring the register of the power SOC chip, without the need for external resistors. Since the linear charging function inside the power SOC chip does not need to pass through the inductor circuit, the 5V input will not affect the output voltage of the VOUT pin. If there is no 5V charging input, the linear charging function is turned off.
  • the signal of the EN pin of the power SOC chip is detected, the current state of the charging compartment cover is identified according to the signal provided by the Hall module, and the change of the state of the charging compartment cover is determined.
  • the charging compartment provides the headset with the relevant opening timing through the combination of the power SOC chip VOUT, PH_L, PH_R, IO_L, and IO_R pins to wake up the headset. Then, two-way communication or discharge of the headset can be carried out according to customized requirements. If it is recognized that the lid of the charging compartment switches from the open state to the closed state, the headset is provided with the relevant closing timing, the headset Bluetooth is turned off, and then the headset is discharged.
  • the register of the power SOC chip is configured to start the built-in synchronous rectification boost function, without the need for an external boost chip.
  • the battery voltage is connected from the LX pin of the power SOC chip through the inductor to the synchronous rectification boost circuit inside the power SOC chip as the boost input, and the boost result is output from the VOUT pin of the power SOC chip to the positive contacts of the earphones L and R.
  • the IO_L and IO_R pins remain in a high-impedance state, and the PH_L and PH_R pins pass through the power SOC chip to provide a ground loop. Based on this, earphones L and R recognize 5V.
  • the warehouse needs to provide a high level of communication to the headset, first configure the register of the power SOC chip, change the output voltage of the VOUT pin, and output a high level of communication (3.3V ⁇ 1.8V).
  • the output voltage of the VOUT pin can be adjusted in steps from 3.3V to 1.8V, so the interface between the charging warehouse and the headset does not require an external level conversion circuit.
  • the PH_L and PH_R pins remain in a high-impedance state.
  • IO_L and IO_R pins output low level.
  • earphones L and R can recognize the communication high level sent by the warehouse. This mode is often used in the process of sending communication data from the warehouse to the earphone.
  • IO_L and IO_R pins are configured as high-impedance input state, and the pull-down resistors L and R provide a path to ground.
  • the equivalent impedance of the earphone and the pull-down resistor voltage divider value exceed the communication high level recognition
  • earphones L and R recognize the communication high level sent by the warehouse.
  • the communication high level voltage at both ends of the earphones in mode 2 is lower than that in mode 1, but the IO_L and IO_R pins can be configured as input states, so they can be used for the subsequent analysis process of earphone reply data and communication idle state.
  • Method 21 configure the register of the power SOC chip, turn off the VOUT output, and keep the PH_L, PH_R, IO_L, and IO_R pins in a high-impedance state.
  • Method 1 is often used to provide 0V to the headset when the charging case is in sleep mode.
  • Mode 22 configure the register of the power SOC chip, turn off the 5V output of VOUT, switch the output to a communication high level, keep the PH_L and PH_R pins in a high impedance state, and output a communication high level on the IO_L and IO_R pins.
  • Mode 2 outputs 0V faster than Mode 1, so it is often used in this application to provide 0V to the headset as a low level during the two-way communication process.
  • the PH_L and PH_R pins and the IO_L and IO_R pin states corresponding to earphones L and R can be operated simultaneously or separately in time division. For example, only the PH_L and IO_L pins associated with earphone L are operated this time; at the next time point, only the PH_R and IO_R pins associated with earphone R are operated.
  • the warehouse After the warehouse sends communication data to the corresponding headset and needs to wait for the headset to reply, the warehouse enters the idle state. At this time, method 12 is used to provide a communication high level to the headset. At the same time, the input logic level judgment threshold is configured according to the amplitude of the communication high level.
  • the headset when the warehouse is idle, the headset responds before the information sent by the warehouse times out, and the warehouse's IO_L and IO_R pins parse the headset's response.
  • the parsing of the data replied by the left headset is taken as an example.
  • the left ear replies to a low level the voltage difference between the two ends of the left ear contact is about 0V, so the voltage at the PH_L pin is the communication high level voltage output by VOUT.
  • IO_L recognizes a high level. In the program, by judging that IO_L is a high level, it is determined that the headset replies to a low level.
  • the left ear replies to a high level
  • the voltage difference between the two ends of the left ear contact is about the communication high level, so the voltage at the PH_L pin is lower than the low level recognition threshold of the communication level.
  • IO_L recognizes a low level.
  • the headset replies to a high level.
  • the reply series levels are parsed to obtain the reply data of the headset, and the parsing of the data replied by the right headset is the same.
  • the signal of the KEY pin of the power SOC chip is detected, and according to the signal provided by the key module, the change of the key is identified, such as single click, long press, and multiple clicks, and a response is made.
  • the light display module can output a light display control signal according to the charging state, discharging state, switch cover state, button state, communication state, and earphone state obtained through communication.
  • the peripheral control module can be used to measure temperature, drive sound-generating devices, control wireless charging, and other functions.
  • the power SOC chip uses IP5518, IP6818, and IP5518H from Ingenic Technology.
  • the IO_L and IO_R internal interfaces have a current limiting function to prevent the two ends of the headset from being short-circuited during communication. Otherwise, it is necessary to connect a current limiting resistor in series with the IO_L and IO_R pins and then connect them to the PH_L and PH_R pins.
  • IO_L and IO_R are internal interfaces. If the internal interface has a current limiting function, it can be directly mapped to the PH_L and PH_R pins through SW_L and SW_R respectively, without the need to additionally encapsulate the IO_L and IO_R pins, thus saving costs.
  • the technical solution provided in this application supports the charging case circuit for two-way communication of TWS earphones. It has a built-in linear charging function, does not require an external charging chip, can dynamically adjust the charging current, and meet the needs of segmented current control in various scenarios; it has a built-in 5V boost function, does not require an external boost chip, and can realize the function of discharging the earphones.
  • the boost and case charging paths are separated and will not affect each other; the two contacts of the earphones are reused to achieve flexible switching between 5V charging and 3.3V ⁇ 1.8V communication levels, reduce the number of openings for the earphones and the charging case, reduce the path for interference introduction, and improve overall reliability; the use of 3.3V ⁇ 1.8V communication levels can be compatible with SOC chips with wider operating voltages, and no boost is required during the communication process, reducing losses; the SOC chip can directly switch to output 3.3V ⁇ 1.8V communication levels in the 5V output path, does not require an external MOS as a path management, and does not require an external LDO to assist in providing a constant communication level; it has a built-in programmable unit, which can achieve deep customization of power control, communication, and display.
  • the present invention has a high integration level, can save PCB area and components, greatly reduce product costs, and at the same time increase the product's two-way communication function and ensure overall performance.
  • FIG 2 is a circuit structure diagram of a single-chip charging case circuit that supports two-way communication of TWS headphones provided by this application.
  • the power SOC chip U1 shown in Figure 2 uses IP6818 from Ingenic Technology
  • the Hall switch U2 uses a single N-pole Hall device (the connection diagram of the Hall device is shown in Figure 3).
  • the headphone interface connection circuit diagram is shown in Figure 4; the light display control circuit diagram is shown in Figure 5, the inductor L1 uses 2.2uH, and the temperature measurement NTC resistor uses 100k ⁇ @25°C.
  • BAT and CSIN are the pins of the power SOC chip IP6818, which are connected to the positive electrode BAT+ and the negative electrode It is responsible for supplying power to the charging compartment and is also the path for charging the battery.
  • GND is the EPAD of the power SOC chip IP6818, connected to the negative electrode BAT- of the battery, as the ground of the system.
  • a filter capacitor C2 of the battery interface stabilizes the battery voltage.
  • LX is a pin of the power SOC chip IP6818, responsible for providing the input and control of the boost signal with the inductor L1.
  • VIN is a pin of the power SOC chip IP6818, responsible for the input of the 5V charging voltage.
  • a filter capacitor C3 stabilizes the 5V charging input voltage.
  • VCC is a pin of the power SOC chip IP6818, responsible for the output of the system reference voltage.
  • a filter capacitor C4 stabilizes the system reference voltage.
  • the NTC resistor R2 changes its resistance according to the ambient temperature, and the resistor R1 is responsible for limiting the size of the parallel equivalent resistance with R2.
  • GPIO3 is a pin of the power SOC chip IP6818, which can output current to R2 and R1, and measure the voltage on the pin, responsible for temperature measurement.
  • GPIO4, GPIO5, and GPIO12 are pins of the power SOC chip IP6818, which are responsible for controlling the LED light display.
  • R11, R12, and R14 are current limiting resistors that can limit the brightness of the LED light; D1, D2, and D3 are white, orange, and green LED lights, respectively, responsible for displaying various states.
  • KEY is a pin of the power SOC chip IP6818, responsible for parsing key signals.
  • a current limiting resistor R9 is used to protect the KEY pin.
  • EN_P is a pin of the power SOC chip IP6818, which is connected to the output pin of the Hall switch U2 through R10 and is responsible for parsing the Hall signal.
  • the R6 resistor is responsible for pull-down, and the R7 and R10 resistors are used for current limiting.
  • Current limiting resistors R3 and R4 are used to protect the IO_L and IO_R pins; pull-down resistors R5 and R8 are used to provide a pull-down circuit when the charging path of PH1_L and PH2_R is closed.
  • the power SOC chip IP6818 is connected in the above circuit manner, and the battery supplies power to it through the BAT pin.
  • the current temperature is identified by detecting the voltage of the GPIO3 pin.
  • the GPIO3 pin will output a 20uA current and is configured as an ADC function.
  • the resistance of the NTC resistor R2 is different, and the resistance in parallel with the R1 resistor is different.
  • the 20uA fixed current generates different voltages on the changing resistance.
  • IP6818 analyzes the voltage ADC value of the GPIO3 pin to determine the current temperature range, providing a basis for the system's temperature protection function.
  • the charging interface J3 has a 5V charging input.
  • IP6818 detects that the VIN pin has 5V, it determines that there is a charging connection at this time.
  • the temperature measurement result is determined to be 0°C ⁇ 15°C, configure the linear charging
  • the constant current value of the battery is 75mA; when the temperature measurement result is judged to be 15°C ⁇ 45°C, the constant current value is configured to be 350mA; less than 0°C is considered as a low temperature protection area, and the charging function is not turned on; greater than 45°C is considered as a high temperature protection area, and the charging function is not turned on.
  • the charging function is turned off.
  • the constant current value is adjustable from 0 to 500mA in steps of 25mA. It can be flexibly configured in the program according to different battery and temperature requirements, and no external identification resistor is required.
  • the EN_P pin signal of the power SOC chip IP6818 is detected.
  • the EN_P pin recognizes the low level output by the Hall switch U2 through its pin 3; when the charging compartment lid is opened, the EN_P pin recognizes the high level output by the Hall switch U2 through its pin 3.
  • the change in the state of the charging compartment lid can be determined.
  • the lid opening sequence is started to wake up the headset.
  • the IO_L and IO_R pins of the power SOC chip IP6818 are set to high impedance, and the charging path inside the PH1_L and PH2_R pins is opened to provide a ground loop.
  • the built-in synchronous rectification 5V boost function of the power SOC chip IP6818 is started, and 5V is output from the VOUT pin and maintained for 600ms.
  • the headset recognizes 600ms of 5V.
  • the IO_L and IO_R pins are configured to a high-impedance state and maintained for 200ms. Since the equivalent impedance of the earphone in the non-5V state is much larger than the pull-down resistors R8 and R9, the earphone can recognize the 200ms communication level and successfully enter the state of waiting to receive the charging case communication command.
  • the IO_R pin starts to send Bluex open cover status related instructions to the right earphone PHONE_R.
  • the instructions of the Bluex earphone adopt the serial port format of 9600 baud rate.
  • 9600 baud rate 9600 baud rate.
  • only one byte 0x55 is selected to describe the data sending process.
  • the sending process of the remaining bytes is the same.
  • Send 0x55 data including start bit 0, data 0x55, stop bit 1, and the data is sent from the low bit, so the data bits sent in sequence are 0 (start bit) ⁇ 1 (BIT0) ⁇ 0 (BIT1) ⁇ 1 (BIT2) ⁇ 0 (BIT3) ⁇ 1 (BIT4) ⁇ 0 (BIT5) ⁇ 1 (BIT6) ⁇ 0 (BIT7) ⁇ 1 (stop bit), and the stay time of each data bit is 104us.
  • the IO_R pin is set to output and outputs a low level.
  • the lamp effect impedance of the earphone is much larger than the parallel value of the pull-down resistor R5 and the current limiting resistor R4, so the right earphone PHONE_R can recognize the communication level, that is, data bit 1.
  • the IO_R pin is set to output and outputs the communication level.
  • the right earphone PHONE_R can recognize the low level, that is, the data bit 0.
  • the IO_R pin switches to the high-impedance input state to continue to provide the communication level to the earphone, and waits for the right earphone to parse the reply data of the sent instruction.
  • the IO_R pin recognizes the low level.
  • the low level recognized by the IO_R pin is maintained for 104us, it can be determined that the data bit replied by the earphone is 1.
  • the voltage on the pull-down resistor R5 is the communication level output by VOUT, and the IO_R pin recognizes the high level.
  • the communication of the right ear is ended. After the charging case IO_R pin sends data, if it fails to receive a complete response from the headset within the specified time, such as 150ms, the communication of the right ear is also terminated. After the communication of the right ear is completed, the IO_R pin maintains a high impedance state.
  • the control process of the right earphone can be seen in Figure 6.
  • the IO_L pin starts to send BlueXun cover opening status related instructions to the left earphone PHONE_L.
  • the IO_L pin is set to output and outputs a low level for 104us.
  • the left earphone PHONE_L can recognize the communication level, that is, data bit 1.
  • the IO_L pin is set to output and outputs the communication level.
  • the left earphone PHONE_L can recognize the low level, that is, data bit 0.
  • the IO_L pin switches to a high-impedance input state to continue to provide the earphone with a communication level, and waits for the left earphone to parse the reply data to the sent instruction.
  • the IO_L pin recognizes a low level.
  • the low level recognized by the IO_L pin is maintained for 104us, it can be determined that the data bit replied by the earphone is 1.
  • the voltage on the pull-down resistor R8 is the communication level of the VOUT output, and the IO_L pin recognizes a high level.
  • the IO_L pin When the high level recognized by the IO_L pin is maintained for 104us, it can be determined that the data bit replied by the earphone is 0. When the power SOC chip IP6818 parses the data replied by the earphone and determines that the complete data has been received, the communication of the left ear is terminated. When the IO_L pin of the charging compartment sends the data, if the complete response of the earphone is not received within the specified time, such as 150ms, the communication of the left ear is also terminated. After the communication of the left ear is completed, the IO_L pin maintains a high impedance state.
  • the interaction of the left ear can be started first, and then the interaction of the right ear can be started.
  • the lid closing sequence is started after the communication ends.
  • the VOUT output voltage is 3V communication level
  • the charging path inside the PH1_L and PH2_R pins is closed
  • the IO_L and IO_R pins are configured to high impedance state for 200ms.
  • the headset can recognize the 200ms communication level and wait to receive the lid closing related instructions sent by the charging case.
  • the right ear and the left ear interact with the cover closing command respectively, and the switching method of the IO_L and IO_R pins during the interaction process is the same as the cover opening command.
  • IO_L and IO_R switch to high-impedance state, VOUT outputs 5V voltage, the charging path inside the PH1_L and PH2_R pins is opened, and the earphones start charging.
  • the earphones when the earphones are in the closed lid charging state, and the charging case needs to switch to the communication state for interaction, if the earphones are fully charged or the NTC resistance is detected to exceed the range that allows the charging case to discharge normally, a shutdown code is sent to the earphones or other command scenarios are sent, the VOUT output voltage is configured to 3V, and the charging path inside the PH1_L and PH2_R pins is turned off, and the IO_L and IO_R pins are configured to a high-impedance state for 200ms to make the earphones enter the closed lid communication state, and then the right ear and the left ear interact with the relevant commands respectively.
  • the switching method of the IO_L and IO_R pins in the interaction process is the same as the open lid to send commands.
  • the case can choose to return to the 5V state to continue charging the earphones; it can also choose to turn off the VOUT output; it can also choose to enter low-power sleep to end the discharge of the earphones.
  • VOUT is configured to output 3V
  • the charging path inside the PH1_L and PH2_R pins is closed, and the IO_L and IO_R pins are configured to high impedance.
  • the warehouse can provide communication voltage to the headset in sleep mode to prevent the headset from turning on. If the headset receives the shutdown code and recognizes that the voltage at both ends is 0V, it will not turn on.
  • the VOUT output can be completely turned off before sleep, that is, the output is 0V.
  • the charging case in sleep mode, can be woken up by charging, pressing a button, or changing the lid.
  • the KEY pin of the power SOC chip IP6818 is a continuous low-load square wave when the button S1 is not pressed.
  • the button S1 When the button S1 is pressed, the KEY pin signal is pulled down to 0V, and the button can be recognized at this time.
  • the time and number of times the button is pressed are identified, and the corresponding display and communication can be triggered after the identification is completed.
  • both ears are in the warehouse, long press for 3 seconds to realize the communication interaction of exchanging the MAC addresses of both ears, and long press for 6 seconds to realize the communication interaction of clearing pairing and other functions.
  • the waveform diagram of both ends of the earphones that realizes two-way communication of the right earphone after opening the cover is shown in Figure 6.
  • the GPIO4, GPIO5, and GPIO12 pins of the power SOC chip IP6818 can control the LED lights to indicate the system status, such as displaying the power level of the headset, displaying the team status of the headset, and displaying the pairing status of the headset according to the result of communication with the headset.
  • Changes in the lid, changes in the battery level of the charging compartment, buttons, charging and discharging status, etc. can all be displayed through different LED display rules, which can display more status than the charging compartment design with one-way communication.
  • An embodiment of the present application also provides an electronic device, which includes the single-chip charging case circuit supporting two-way communication of TWS headphones as shown in FIG1 .

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Abstract

本申请提供一种支持TWS耳机双向通讯的单芯片充电仓电路方法及设备，该支持TWS耳机双向通讯的单芯片充电仓电路包括：SOC芯片、电池、霍尔模块、按键模块，所述支持TWS耳机双向通讯的单芯片充电仓电路还包括：电感、一对耳机接口。本申请提供的技术方案具有提高仓的可靠性、集成度和通讯效率，降低成本的优点。

Description

支持TWS耳机双向通讯的单芯片充电仓电路方法及设备
本申请要求于2022年12月5日提交中国专利局、申请号为2022115478839，申请名称为“支持TWS耳机双向通讯的单芯片充电仓电路方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及电子设备领域，具体涉及一种支持TWS耳机双向通讯的单芯片充电仓电路方法及设备。
背景技术
TWS(英文：True Wireless Stereo，真无线立体声耳机)，TWS充电仓电路主要由充电模块、主控模块、和放电模块组成，用于实现对仓充电储能、和对耳机放电的基础功能。目前许多设计采用1颗主控芯片搭配1颗充放电功能“2”合“1”芯片的电路设计，或者采用1颗具备充电功能的主控芯片搭配1颗升压放电芯片的电路设计，这种选用2颗芯片实现基本功能的充电仓电路会占用更多的PCB面积，增加设计难度，提升制造成本。
发明内容
本发明实施例提供了一种支持TWS耳机双向通讯的单芯片充电仓电路及控制方法，可以提高仓的可靠性、集成度和通讯效率，具有降低成本的优点。
第一方面，本发明实施例提供一种支持TWS耳机双向通讯的单芯片充电仓电路，包括：SOC芯片、电池、霍尔模块、按键模块，所述支持TWS耳机双向通讯的单芯片充电仓电路还包括：电感、一对耳机接口；其中，
SOC芯片的LX引脚连接电感的一端，电感另一端连接电池，所述电感用于提供升压信号；
SOC芯片的电源输出VOUT引脚分别连接耳机L和耳机R的正极，为耳机L和耳机R提供充电电压和通讯电平，耳机L负极连接下拉电阻L的一端，下拉电阻L的另一端接地，耳机R负极连接下拉电阻R的一端，下拉电阻R的另一端接地，耳机L负极与SOC芯片的PH_L引脚连接以及连接限流电阻L的一端，限流电阻L的另一端为输出信号IO_L端口，耳机R负极与SOC芯R的PH_R引脚连接以及连接限流电阻R的一端，限流电阻R的另一端为输出信号IO_R端口；
SOC芯片的VIN引脚连连接充电输入端口，SOC芯片的BAT引脚连接电池的正极，电池的负极接地，电感也与电池的正极连接。
第二方面，提供一种第一方面提供的所述支持TWS耳机双向通讯的单芯片充电仓电路的控制方法，所述方法包括：
在检测到充电仓处于关盖状态切换开盖状态，电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供开盖时序，唤醒耳机；在检测到充电仓盖子从开盖状态切换到关盖状态，则电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供关盖时序，关闭耳机蓝牙，之后对耳机放电。
第三方面，提供一种电子设备，所述电子设备包括第一方面提供的支持TWS耳机双向通讯的单芯片充电仓电路。
第四方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，执行第一方面提供的方法。
实施本发明实施例，具有如下有益效果：
本申请提供的技术方案支持TWS耳机双向通讯的充电仓电路，具有内置线性充电功能，无需外挂充电芯片，可以动态调节充电电流，满足多种场景下的分段电流调控需求；具有内置5V升压功能，无需外挂升压芯片，可实现对耳机放电的功能，同时升压与仓充电路径分开，不会相互影响；复用耳机的2个触点，实现5V充电与3.3V～1.8V通讯电平的灵活切换，减少耳机和充电仓开孔数量，减少干扰引入的路径，提升整体的可靠性；采用3.3V～1.8V通讯电平可以兼容更宽工作电压的SOC芯片，通讯过程不需要进行升压，减少了损耗；SOC芯片可直接在5V的输出路径直接切换输出3.3V～1.8V通讯电平，不需要外挂MOS作为路径管理，也不需要外挂LDO协助提供恒定的通讯电平；具有内置可编程单元，可以实现功率控制、通讯、显示的深度定制。本发明的集成度高，可以节省PCB面积和元器件，极大降低产品成本的同时增加了产品双向通讯的功能并保障了整体性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还 可以根据这些附图获得其他的附图。
图1是本申请提供的一种支持TWS耳机双向通讯的单芯片充电仓电路的结构示意图；
图2为是本申请提供的一种支持TWS耳机双向通讯的单芯片充电仓电路的结构示意图；
图3本申请提供的霍尔开关的连接电路图；
图4是为本申请提供的耳机接口连接电路图；
图5是本申请提供的灯显控制电路示意图；
图6是本申请提供的充电仓开盖后右耳机双向通讯的耳机两端波形说明示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结果或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
为了描述的方便，下述实施例中将充电仓简称为“仓”。
参阅图1，图1为本申请提供的支持TWS耳机双向通讯的单芯片充电仓电路的结构示意图，如图1所示，该支持TWS耳机双向通讯的单芯片充电仓电路包括：电源SOC芯片(以下简称SOC芯片)、电池、霍尔模块、按键模块，该 电路还可以包括：电感、一对耳机接口。
SOC芯片各引脚如下：LX是电源SOC芯片的一个引脚，负责配合电感提供升压信号的输入；BAT是电源SOC芯片的一个引脚，负责提供充电仓电池接口；VIN是电源SOC芯片的一个引脚，负责5V充电电压的输入；IO是电源SOC芯片的一组引脚，可以作为数字信号输入、输出以及模数转换用途，本发明中选用其中若干个引脚用于灯显的输出，其他的预留用于处理温控等其他外设需求；KEY是电源SOC芯片的一个引脚，负责解析按键信号；EN是电源SOC芯片的一个引脚，负责解析霍尔信号；VOUT是电源SOC芯片的一个引脚，负责向耳机正极提供充电电压和通讯电平；PH_L、PH_R是电源SOC芯片的引脚，是耳机L和耳机R负极的接口，负责耳机的充电路径开关、电流采样；IO_L、IO_R是电源SOC芯片的引脚或者是可映射到PH_L、PH_R的内部接口，负责仓双向通讯的发送与接收；GND是电源SOC芯片的一个引脚，连接系统的地。
其中，SOC芯片的LX引脚连接电感的一端，电感另一端连接电池，所述电感用于提供升压信号；
SOC芯片的电源输出VOUT引脚(即一对耳机接口的正极接口)分别连接耳机L和耳机R的正极，为耳机L和耳机R提供充电电压和通讯电平，耳机L负极连接下拉电阻L的一端，下拉电阻L的另一端接地，耳机R负极连接下拉电阻R的一端，下拉电阻R的另一端接地，耳机L负极与SOC芯片的PH_L引脚(即一对耳机接口的一个负极接口)连接以及连接限流电阻L的一端，限流电阻L的另一端为输出信号IO_L端口，耳机R负极与SOC芯片的PH_R引脚(即一对耳机接口的一个负极接口)连接以及连接限流电阻R的一端，限流电阻R的另一端为输出信号IO_R端口；
SOC芯片的VIN引脚连连接充电输入(5V)，SOC芯片的BAT引脚连接电池的正极，电池的负极接地，电感也与电池的正极连接。
上述如图1所示的电路结构支持TWS耳机双向通讯的充电仓的技术方案具体可以包括：
电池通过BAT引脚为其供电。当BAT电压不足时，插入VIN也能为芯片供电，令其维持在工作状态。检测电源SOC芯片VIN引脚的信号，识别是否有5V充电输入。如果有5V充电输入，则开启电源SOC芯片内部的线性充电功能对充电仓进行充电，线性充电功能会控制5V充电输入的电流大小，并通过BAT 引脚将电能提供给电池。
上述恒流充电段的电流大小，可以通过配置电源SOC芯片的寄存器实时实现，不需要外置电阻。由于电源SOC芯片内部的线性充电功能不需要经过电感回路，因此5V的输入不会影响VOUT引脚的输出电压，如果没有5V充电输入，则关闭线性充电功能。
示例的，检测电源SOC芯片EN引脚的信号，根据霍尔模块提供的信号识别当前充电仓盖子的状态，判断充电仓盖子状态的变化。
如果识别到充电仓盖子从关盖状态切换开盖状态，则充电仓通过电源SOC芯片VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供相关的开盖时序，唤醒耳机，然后，根据定制需求可以进行双向通讯或者对耳机放电。如果识别到充电仓盖子从开盖状态切换到关盖状态，则向耳机提供相关的关盖时序，关闭耳机蓝牙，之后对耳机放电。
示例的，当仓需要对耳机提供5V，用于对耳机放电或者作为组合时序中的一部分时，配置电源SOC芯片的寄存器启动内置同步整流升压功能，无需外挂升压芯片。电池电压经过电感从电源SOC芯片的LX引脚连接电源SOC芯片内部的同步整流升压电路做为升压的输入，升压的结果从电源SOC芯片的VOUT引脚输出到耳机L和耳机R的正端触点。在耳机的负端触点处，IO_L、和IO_R引脚保持高阻状态，PH_L、PH_R引脚经过电源SOC芯片，提供对地回路。基于此，耳机L、耳机R识别到5V。
示例的，当仓需要对耳机提供通讯高电平时，首先配置电源SOC芯片的寄存器，改变VOUT引脚的输出电压，输出通讯高电平(3.3V～1.8V)。除放电5V外，VOUT引脚输出电压从3.3V至1.8V步进可配，因此充电仓与耳机的接口可以不用外接电平转换电路。在耳机的负端(也可以称为负极)触点处，PH_L和PH_R引脚保持高阻状态。上述操作之后，有两种方式可令耳机识别到通讯高电平。
方式11，IO_L和IO_R引脚输出低电平，当耳机的等效阻抗与(限流电阻//下拉电阻)的分压值超过通讯高电平的识别阈值时，耳机L、耳机R可识别到仓发送的通讯高电平，该方式常用在仓向耳机发送通讯数据的过程。
方式12，IO_L和IO_R引脚配置为高阻输入状态，由下拉电阻L、下拉电阻R提供对地路径，当耳机的等效阻抗与下拉电阻分压值超过通讯高电平的识 别阈值时，耳机L、耳机R识别到仓发送的通讯高电平。方式2中耳机两端的通讯高电平电压相比方式1低，但IO_L和IO_R引脚可配置为输入状态，因此可用于后续的耳机回复数据的解析过程以及通讯空闲状态。
示例的，当仓需要对耳机提供0V时，有两种方式可用于实现。
方式21，配置电源SOC芯片的寄存器，关闭VOUT输出，PH_L、PH_R、IO_L、IO_R引脚均保持高阻状态。方式1常用于充电仓在休眠状态下提供0V给耳机。
方式22，配置电源SOC芯片的寄存器，关闭VOUT的5V输出，切换输出为通讯高电平，PH_L和PH_R引脚保持高阻状态，IO_L和IO_R引脚输出通讯高电平。此时，耳机的正端和负端没有电压差，耳机识别此时的状态为0V，方式2输出0V的速度较方式1快，所以在本申请中常用于在双向通讯过程向耳机提供0V，作为低电平。
示例的，根据实际控制的需要，耳机L、耳机R所对应的PH_L和PH_R引脚以及IO_L和IO_R引脚状态，可以同时操作，亦可分时单独操作，例如本次仅操作耳机L关联的PH_L和IO_L引脚；下个时间点仅操作耳机R关联的PH_R和IO_R引脚。
示例的，当仓给对应的耳机发送完通讯数据后，需要等待耳机回复时，仓进入空闲状态，此时采用方式12对耳机提供通讯高电平，同时根据通讯高电平的幅值，配置输入逻辑电平判断阈值。
示例的，仓空闲状态下，耳机在仓发送的信息超时前进行应答，仓的IO_L和IO_R引脚对耳机的应答进行解析。此处以解析左耳机回复的数据为例，当左耳回复低电平时，左耳触点2端的压差约为0V，所以PH_L引脚处的电压为VOUT输出的通讯高电平电压，此时IO_L识别到高电平，在程序中，通过判断IO_L为高电平，判定耳机回复低电平。当左耳回复高电平时，左耳触点2端的压差约为通讯高电平，因此PH_L引脚处的电压低于通讯电平的低电平识别阈值，此时IO_L识别到低电平，在程序中，通过判断IO_L为低电平，判定耳机回复高电平。按照仓与耳机约定的高低电平组合规则，对回复的系列电平进行解析，可得出耳机的回复数据，解析右耳机回复的数据同理。
示例的，检测电源SOC芯片KEY引脚的信号，根据按键模块提供的信号，识别按键的变化，如单击、长按、多击并进行响应。
示例的，灯显模块可以根据充电状态、放电状态、开关盖状态、按键状态、通讯状态以及经过通讯获得的耳机状态等状态进行灯显控制信号的输出。
示例的，外设控制模块可以用于测量温度、驱动发声器件、控制无线充电等功能。
示例的，电源SOC芯片选用英集芯科技的IP5518、IP6818、IP5518H。
示例的，IO_L、IO_R内部接口自带限流功能，可预防在通讯过程中耳机两端被短路。否则，需要在IO_L、IO_R引脚串接限流电阻，再连接到PH_L、PH_R引脚。
示例的，IO_L、IO_R为内部接口，若内部接口自带限流功能，可分别通过SW_L、SW_R直接映射到PH_L、PH_R引脚，不需要额外封装出IO_L、IO_R引脚，节约成本。
本申请提供的技术方案支持TWS耳机双向通讯的充电仓电路，具有内置线性充电功能，无需外挂充电芯片，可以动态调节充电电流，满足多种场景下的分段电流调控需求；具有内置5V升压功能，无需外挂升压芯片，可实现对耳机放电的功能，同时升压与仓充电路径分开，不会相互影响；复用耳机的2个触点，实现5V充电与3.3V～1.8V通讯电平的灵活切换，减少耳机和充电仓开孔数量，减少干扰引入的路径，提升整体的可靠性；采用3.3V～1.8V通讯电平可以兼容更宽工作电压的SOC芯片，通讯过程不需要进行升压，减少了损耗；SOC芯片可直接在5V的输出路径直接切换输出3.3V～1.8V通讯电平，不需要外挂MOS作为路径管理，也不需要外挂LDO协助提供恒定的通讯电平；具有内置可编程单元，可以实现功率控制、通讯、显示的深度定制。本发明的集成度高，可以节省PCB面积和元器件，极大降低产品成本的同时增加了产品双向通讯的功能并保障了整体性能。
以支持蓝讯TWS耳机双向通讯的单芯片充电仓电路为例，参见图2，图2为本申请提供的一种支持TWS耳机双向通讯的单芯片充电仓电路结构图，同时，如图2所示的电源SOC芯片U1选用英集芯科技的IP6818，霍尔开关U2选用单N极霍尔器件(霍尔器件的连接示意图如图3所示)，耳机接口连接电路图如图4所示；灯显控制电路示意图如图5所示，电感L1选用2.2uH，测温NTC电阻选用100kΩ@25℃。
BAT、CSIN是电源SOC芯片IP6818的引脚，连接电池的正极BAT+，负 责为充电仓供电，同时也是电池充电的路径。GND是电源SOC芯片IP6818的EPAD，连接电池的负极BAT-，作为系统的地。一个电池接口的滤波电容C2，使电池电压稳定。LX是电源SOC芯片IP6818的一个引脚，负责配合电感L1提供升压信号的输入与控制。VIN是电源SOC芯片IP6818的一个引脚，负责5V充电电压的输入。一个滤波电容C3，使5V充电输入电压稳定。VCC是电源SOC芯片IP6818的引脚，负责系统基准电压的输出。一个滤波电容C4，使系统基准电压稳定。NTC电阻R2根据环境温度变化阻值，电阻R1负责限制与R2的并联等效阻值大小。GPIO3是电源SOC芯片IP6818的引脚，可以输出电流到R2、R1上，并测量引脚上的电压大小，负责温度的测量。GPIO4、GPIO5、GPIO12是电源SOC芯片IP6818的引脚，负责LED灯显的控制。R11、R12、R14是限流电阻，可限制LED灯的亮度；D1、D2、D3分别是白色、橙色、绿色LED灯，负责各种状态的显示。KEY是电源SOC芯片IP6818的一个引脚，负责解析按键信号。一个限流电阻R9，用于保护KEY引脚。EN_P是电源SOC芯片IP6818的一个引脚，经过R10连接霍尔开关U2的输出引脚，负责解析霍尔信号。R6电阻负责下拉，R7、R10电阻用于限流。VOUT是电源SOC芯片IP6818的一个引脚，负责向耳机正极提供充电电压和通讯电平。一个滤波电容C1，使耳机正端的电压更稳定。PH1_L、PH2_R是电源SOC芯片IP6818的引脚，连接耳机L(PHONE_L)和耳机R(PHONE_R)负极的接口，负责耳机的充电路径开关、电流采样。IO_L、IO_R是电源SOC芯片IP6818的引脚，负责仓双向通讯的发送与接收。限流电阻R3、R4，用于保护IO_L、IO_R引脚；下拉电阻R5、R8，用于PH1_L、PH2_R的充电路径关闭时，提供下拉回路。
示例的，电源SOC芯片IP6818按照上述的电路连接方式，电池通过BAT引脚为其供电。
示例的，电源SOC芯片IP6818启动后，通过检测GPIO3引脚电压识别当前温度。GPIO3引脚会输出20uA电流，并配置为ADC功能，不同温度下，NTC电阻R2的阻值不同，与R1电阻并联的阻值不同，20uA固定电流在变化的阻值上产生不同的电压。IP6818对GPIO3引脚的电压ADC值进行解析，可判断出当前所处的温度区间，为系统的温度保护功能提供依据。
示例的，检测充电接口J3是否有5V充电输入。当IP6818检测到VIN引脚有5V时，判定此时有充电接入。当测温结果判定为0℃～15℃时，配置线性充 电的恒流电流值为75mA；当测温结果判定为15℃～45℃时，配置恒流电流值为350mA；小于0℃视为低温保护区域，不开启充电功能；大于45℃视为高温保护区域，不开启充电功能。当没有5V充电输入时，关闭充电功能。IP6818内置的线性充电电路开启充电时，不会影响VOUT输出电压，同时恒流电流值从0～500mA每25mA步进可调，根据不同的电池和温度需求，可以在程序中灵活配置，不需要外置识别电阻。
示例的，检测电源SOC芯片IP6818的EN_P引脚信号，当充电仓盖子合上时，EN_P引脚识别到霍尔开关U2通过其引脚3输出的低电平；当充电仓盖子打开时，EN_P引脚识别到霍尔开关U2通过其引脚3输出的高电平，由此，可判断出充电仓盖子状态的变化。
示例的，如果充电仓盖子的状态从关闭切换为打开，则启动开盖时序，唤醒耳机。首先，设置电源SOC芯片IP6818的IO_L和IO_R引脚为高阻状态，PH1_L、PH2_R引脚内部的充电路径打开，提供对地回路。然后，启动电源SOC芯片IP6818内置的同步整流5V升压功能，从VOUT引脚输出5V，并维持600ms，此时耳机识别到600ms的5V。接着，调整VOUT输出电压为3V通讯电平，关闭PH1_L、PH2_R引脚内部的充电路径，IO_L和IO_R引脚设置为输出模式，并输出3V电压，并维持200ms，此时耳机识别到200ms的0V。若蓝讯耳机在仓，则会被600ms 5V+200ms 0V的组合时序唤醒，为后续的双向通讯做准备。
示例的，IO_L和IO_R引脚配置为高阻状态，维持200ms，由于耳机在非5V状态下等效阻抗远大于下拉电阻R8、R9，所以耳机可识别到200ms通讯电平，并顺利进入等待接收充电仓通讯命令状态。
示例的，IO_R引脚开始向右耳机PHONE_R发送蓝讯开盖状态相关指令。蓝讯耳机的指令采用的9600波特率的串口格式，此处仅节选其中1个字节0x55描述数据发送的过程，其余字节的发送过程相同。发送0x55数据，包含起始位0，数据0x55，停止位1，数据从低位开始发送，所以依次发送的数据位为0(起始位)→1(BIT0)→0(BIT1)→1(BIT2)→0(BIT3)→1(BIT4)→0(BIT5)→1(BIT6)→0(BIT7)→1(停止位)，每个数据位停留的时间为104us。当需要发送给耳机的数据位为1时，IO_R引脚设置为输出，并输出低电平，此时耳机的灯效阻抗远大于下拉电阻R5与限流电阻R4的并联值，所以右耳机PHONE_R可识别到通讯电平，即数据位1。当需要发送给耳机的数据位为0时， IO_R引脚设置为输出，并输出通讯电平，此时耳机两端没有压差，所以右耳机PHONE_R可识别到低电平，即数据位0。发送完1个字节之后，继续按照上述方法发送指令中的剩余字节。当最后一个字节的停止位发送结束后，IO_R引脚切换为高阻输入状态继续给耳机提供通讯电平，并等待解析右耳机对已发送指令的回复数据。当右耳机回复数据位1时，IO_R引脚识别到低电平，当IO_R引脚识别到的低电平维持104us时，可判定耳机回复的数据位为1。当右耳机回复数据位0时，右耳机两端没有电压差，此时下拉电阻R5上的电压为VOUT输出的通讯电平，IO_R引脚识别到高电平，当IO_R引脚识别到的高电平维持104us时，可判定耳机回复的数据位为0。当电源SOC芯片IP6818解析耳机回复的数据，判定已接收到完整的数据时，结束本次右耳的通讯。当充电仓IO_R引脚发送完数据后，在规定的时间内，如150ms，未能收到耳机的完整回复，亦结束本次右耳的通讯。右耳的通讯结束后，IO_R引脚维持高阻状态。上述右耳机的控制过程，可参见附图6。
示例的，右耳通讯结束后，IO_L引脚开始向左耳机PHONE_L发送蓝讯开盖状态相关指令。当需要发送给耳机的数据位为1时，IO_L引脚设置为输出，并输出低电平104us，此时左耳机PHONE_L可识别到通讯电平，即数据位1。当需要发送给耳机的数据位为0时，IO_L引脚设置为输出，并输出通讯电平，此时左耳机PHONE_L可识别到低电平，即数据位0。发送完1个字节之后，继续按照上述方法发送指令中的剩余字节。当最后一个字节的停止位发送结束后，IO_L引脚切换为高阻输入状态继续给耳机提供通讯电平，并等待解析左耳机对已发送指令的回复数据。当左耳机回复数据位1时，IO_L引脚识别到低电平，当IO_L引脚识别到的低电平维持104us时，可判定耳机回复的数据位为1。当左耳机回复数据位0时，此时下拉电阻R8上的电压为VOUT输出的通讯电平，IO_L引脚识别到高电平，当IO_L引脚识别到的高电平维持104us时，可判定耳机回复的数据位为0。当电源SOC芯片IP6818解析耳机回复的数据，判定已接收到完整的数据时，结束本次左耳的通讯。当充电仓IO_L引脚发送完数据后，在规定的时间内，如150ms，未能收到耳机的完整回复，亦结束本次左耳的通讯。左耳的通讯结束后，IO_L引脚维持高阻状态。
示例的，右耳和左耳分别通讯结束后，如果需要重发或者发送新的指令，则重新开始启动右耳指令的交互，再启动左耳指令的交互，右耳加上左耳的交 互为一次完整的双向通讯过程，在实际控制中，亦可先启动左耳的交互，再启动右耳的交互。
示例的，如果充电仓盖子的状态从打开切换为关闭，则在当次通讯结束之后，启动关盖时序。VOUT输出电压为3V通讯电平，关闭PH1_L、PH2_R引脚内部的充电路径，IO_L和IO_R引脚配置为高阻状态，维持200ms。耳机可识别到200ms通讯电平，并等待接收充电仓发送的关盖相关指令。
示例的，右耳、左耳分别进行关盖指令的交互，IO_L和IO_R引脚在交互过程的切换方法同开盖发送指令。
示例的，关盖指令交互结束后，IO_L和IO_R切换为高阻状态，VOUT输出5V电压，PH1_L、PH2_R引脚内部的充电路径打开，耳机开始充电。
示例的，当耳机在关盖充电状态，充电仓要切换到通讯状态进行交互时，如耳机充饱或检测到NTC电阻超过允许充电仓正常放电的范围，给耳机发送关机码或者发送其他指令场景，VOUT输出电压配置为3V，并关闭PH1_L、PH2_R引脚内部的充电路径，IO_L和IO_R引脚配置为高阻状态，维持200ms令耳机进入关盖通讯状态，之后右耳、左耳分别进行相关指令的交互，IO_L和IO_R引脚在交互过程的切换方法同开盖发送指令。通讯结束后，仓可以选择重新回到5V状态，继续给耳机充电；还可选择关闭VOUT输出；亦可选择进入低功耗休眠，结束对耳机放电。
示例的，若有NTC电阻从过温状态解除，则仓重新进入5V放电状态。
示例的，若仓准备进入休眠，则VOUT配置输出3V，PH1_L、PH2_R引脚内部的充电路径关闭，IO_L和IO_R引脚配置为高阻状态。基于此配置，仓在休眠状态下可提供通讯电平给耳机，防止耳机开机。若耳机接收关机码后，识别到两端电压为0V不会开机，可在睡眠前完全关闭VOUT输出，即输出0V。
示例的，休眠状态下，接入充电、按键、盖子变化，均可唤醒充电仓。
示例的，电源SOC芯片IP6818KEY引脚，在按键S1未按下时，是持续的低负载能力方波，当按键S1按下后，KEY引脚信号被下拉至0V，此时可识别到按键按下。对按键按下的时间和次数进行识别，识别结束后可触发对应显示以及通讯，例如双耳在仓时，长按3秒实现双耳的MAC地址交换的通讯交互，长按6秒实现清除配对等功能的通讯交互。上述实现开盖后右耳机双向通讯的耳机两端波形图如图6所示。
示例的，电源SOC芯片IP6818的GPIO4、GPIO5、GPIO12引脚可分别控制LED灯指示系统状态，例如根据与耳机通讯的结果，显示耳机的电量、显示耳机的组队状态、显示耳机的配对状态。盖子的变化、充电仓电池电量的变化、按键、充放电等状态，均可通过不同的LED显示规律进行展示，较单向通讯的充电仓设计，可以展示更多的状态。
本申请实施例还提供一种电子设备，所述电子设备包括上述如图1所示的支持TWS耳机双向通讯的单芯片充电仓电路。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明并不受所描述的动作顺序的限制，因为依据本发明，某些步骤可以接收其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于可选实施例，所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。
以上对本发明实施例进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (10)

  1. 一种支持TWS耳机双向通讯的单芯片充电仓电路，包括：SOC芯片、电池、霍尔模块、按键模块，其特征在于，所述支持TWS耳机双向通讯的单芯片充电仓电路还包括：电感、一对耳机接口；其中，
    SOC芯片的LX引脚连接电感的一端，电感另一端连接电池，所述电感用于提供升压信号；
    SOC芯片的电源输出VOUT引脚分别连接耳机L和耳机R的正极，为耳机L和耳机R提供充电电压和通讯电平，耳机L负极连接下拉电阻L的一端，下拉电阻L的另一端接地，耳机R负极连接下拉电阻R的一端，下拉电阻R的另一端接地，耳机L负极与SOC芯片的PH_L引脚连接以及连接限流电阻L的一端，限流电阻L的另一端为输出信号IO_L端口，耳机R负极与SOC芯片的PH_R引脚连接以及连接限流电阻R的一端，限流电阻R的另一端为输出信号IO_R端口；
    SOC芯片的VIN引脚连连接充电输入端口，SOC芯片的BAT引脚连接电池的正极，电池的负极接地，电感也与电池的正极连接。
  2. 根据权利要求1所述的一种支持TWS耳机双向通讯的单芯片充电仓电路，其特征在于，所述支持TWS耳机双向通讯的单芯片充电仓电路还包括：灯显与外设控制模块，所述灯显与外设控制模块一端与SOC芯片的IO引脚连接，所述灯显与外设控制模块的另一端接地。
  3. 根据权利要求1所述的一种支持TWS耳机双向通讯的单芯片充电仓电路，其特征在于，所述支持TWS耳机双向通讯的单芯片充电仓电路还包括：按键模块，所述按键模块的一端连接SOC芯片的KEY引脚，所述按键模块的另一端接地。
  4. 根据权利要求1-3任意一项所述支持TWS耳机双向通讯的单芯片充电仓电路的控制方法，其特征在于，所述方法包括：
    在检测到充电仓处于关盖状态切换开盖状态，电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供开盖时序，唤醒耳机。
  5. 根据权利要求4所述的方法，其特征在于，所述方法还包括：
    在检测到充电仓盖子从开盖状态切换到关盖状态，则电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供关盖时序，关闭耳机蓝牙，之后对耳机放电。
  6. 根据权利要求5所述的方法，其特征在于，电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供关盖时序具体包括：
    电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供5V电压，具体包括：
    配置电源SOC芯片的寄存器启动内置同步整流升压功能，电池电压经过电感从电源SOC芯片的LX引脚连接电源SOC芯片内部的同步整流升压电路做为升压的输入，升压的结果从电源SOC芯片的VOUT引脚输出到耳机L和耳机R的正端触点，在耳机的负端触点处，IO_L、和IO_R引脚保持高阻状态，PH_L、PH_R引脚经过电源SOC芯片，提供对地回路。
  7. 根据权利要求5所述的方法，其特征在于，电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供关盖时序具体包括：
    电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供通讯高电平，具体包括：
    配置电源SOC芯片的寄存器，改变VOUT引脚的输出电压，输出通讯高电平。
  8. 根据权利要求5所述的方法，其特征在于，电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供关盖时序具体包括：
    电源SOC芯片控制VOUT、PH_L、PH_R、IO_L、IO_R引脚的组合状态向耳机提供0V，具体包括：
    配置电源SOC芯片的寄存器，关闭VOUT输出，PH_L、PH_R、IO_L、IO_R引脚均保持高阻状态；
    或配置电源SOC芯片的寄存器，关闭VOUT的5V输出，切换输出为通讯 高电平，PH_L和PH_R引脚保持高阻状态，IO_L和IO_R引脚输出通讯高电平。
  9. 一种电子设备，其特征在于，所述电子设备包括权利要求1-3任意一项所述支持TWS耳机双向通讯的单芯片充电仓电路。
  10. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，当其在计算机上运行时，执行如权利要求4-8任意一项的支持TWS耳机双向通讯的单芯片充电仓电路的控制方法。
PCT/CN2023/092593 2022-12-05 2023-05-06 支持tws耳机双向通讯的单芯片充电仓电路方法及设备 WO2024119709A1 (zh)

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