WO2024114264A1

WO2024114264A1 - Encryption and decryption architecture, method, processor, and server

Info

Publication number: WO2024114264A1
Application number: PCT/CN2023/128627
Authority: WO
Inventors: 赵新宇; 孙旭; 周玉龙; 刘刚
Original assignee: 苏州元脑智能科技有限公司
Priority date: 2022-11-28
Filing date: 2023-10-31
Publication date: 2024-06-06
Also published as: CN115549911A; CN115549911B

Abstract

The present application relates to an encryption and decryption architecture, a method, a processor, and a server. According to the encryption and decryption architecture, a controller is connected to a data stream control module and transmits data to be operated to the data stream control module; the data stream control module groups said data and sends same to an algorithm engine core module; an SM4 algorithm engine and an AES algorithm engine capable of independently completing respective algorithm operations are integrated in the algorithm engine core module; after determining the type of an algorithm to be performed, the data stream control module controls the algorithm engine core module to start the corresponding algorithm engine; the algorithm engine core module performs encryption and decryption operations by using said data provided by the data stream control module, and keys and initial vectors that are required by the encryption and decryption operations and configured in a register file module and feeds back the operation results to the data stream control module; and the data stream control module outputs operation result data by means of the controller. Thus, encryption and decryption processing integrating an SM4 algorithm and an AES algorithm is achieved.

Description

An encryption and decryption architecture, method, processor and server

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to the Chinese patent application filed with the China Patent Office on November 28, 2022, with application number 202211496168.7 and application name “An encryption and decryption architecture, method, processor and server”, all contents of which are incorporated by reference in this application.

Technical Field

The present application relates to the field of encryption and decryption architecture design, and in particular to an encryption and decryption architecture, method, processor and server.

Background technique

The existing BMC chip supports multiple symmetric algorithms, such as AES, DES and RC4, and multiple algorithm working modes, such as ECB, CBC, CTR, OFB, etc. The external interface is connected to the AHB bus and supports independent configuration of the algorithm. The software configures the relevant parameters required by the algorithm before the algorithm operation starts, such as the key, initial vector, etc., and finally starts the operation. After the operation is completed, the interrupt, interrupt status and related instruction registers are cleared. The same operation is performed before the next operation. Repetitive configuration is required before each operation, and the algorithm operation cannot be started before the parameters are configured. The internal encryption and decryption module of the existing BMC chip is based on the cryptographic algorithm. From the perspective of algorithm security, the DES algorithm and the RC4 algorithm cannot resist replay attacks, and the key is easy to be cracked. From the perspective of computing efficiency, the computing speed of the DES algorithm and the RC4 algorithm is lower than the mainstream level in the industry; the national secret algorithm such as SM4 has a higher computing speed and security than the DES algorithm and the RC4 algorithm, but the existing BMC chip does not support SM4 or other national secret algorithms. If a replay attack is carried out on them, it may cause the leakage of privacy data or even national secrets, which greatly threatens the data security of users and the country.

Summary of the invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides an encryption and decryption architecture, method, processor and server.

In the first aspect, the present application provides an encryption and decryption architecture, including: a controller, which is connected to the outside through a bus and is used to communicate with the outside through the bus; a data flow control module, which is connected to the controller; an algorithm engine core module, which is connected to the data flow control module; and a register stack module, which is connected to the outside through a bus and is also connected to the data flow control module; wherein the algorithm engine core module uses the grouped data to be operated provided by the data flow control module and the key and initial vector required for the encryption and decryption operation configured in the register stack module to perform encryption and decryption operations and feed back the operation result data of the encryption and decryption operations to the data flow control module, and the data flow control module outputs the operation result data through the controller.

In some embodiments of the present application, the algorithm engine core module integrates the SM4 algorithm engine and the AES algorithm engine which can independently complete their respective algorithm operations.

In some embodiments of the present application, the SM4 algorithm engine includes an SM4 byte replacement unit, an SM4 encryption/decryption operation unit, and an SM4 key expansion unit. The SM4 byte replacement unit is used to perform a byte replacement operation, and replaces the input data with the corresponding data in bytes by searching the first lookup table and outputs it; the SM4 encryption/decryption operation unit integrates a 32-level pipeline round function, which can realize the input and output of a single clock cycle, and the round key generated by the SM4 key expansion module is used for the SM4 encryption/decryption operation unit. The AES algorithm engine unit integrates the three independent AES encryption/decryption operation units and AES key expansion units of AES-128, AES-192 and AES-256 algorithms, AES column obfuscation unit and AES byte replacement unit. The AES byte replacement unit is mainly used for byte replacement operations. By looking up the second lookup table, the input data is replaced with the corresponding data in bytes and output. The state matrix of the AES column obfuscation unit after row shifting is multiplied with the fixed matrix to obtain the obfuscated state matrix to implement column obfuscation transformation.

In some embodiments of the present application, the controller internally integrates a DMA register and a DMA read-write data flow control unit; the DMA register is connected to the AHB bus via an AHB slave interface; the DMA read-write data flow control unit is connected to the AHB bus via an AHB master interface, and the DMA read-write data flow control unit is connected to the data flow control module; the DMA read-write data flow control unit obtains the data to be calculated through the AHB bus according to the configuration in the DMA register and transmits it to the data flow control module.

In some embodiments of the present application, the register stack module is connected to the externally connected AHB bus through an AHB slave interface, and the register stack module is connected to the data flow control module via an internal bus; the register stack module configures the first key register and the first initial vector register for the AES algorithm implemented by the algorithm engine core module, and the register stack module configures the second key register and the second initial vector register for the SM4 algorithm implemented by the algorithm engine core module; the register stack module configures multiple groups of channel status registers for recording the operation status; the register stack module configures a group of instruction registers.

In some embodiments of the present application, the AHB slave interface corresponding to the register stack module and the DMA register is connected to the CPU of the corresponding AHB master interface via the AHB bus.

In some embodiments of the present application, the data flow control module includes an internal cache and a flow control unit; wherein the internal cache includes an input FIFO cache and an output FIFO cache, the input FIFO cache is used to cache the data to be calculated read by the controller using the bus, and the output FIFO is used to cache the calculation result data output by the algorithm engine core module to the data to be calculated; the flow control unit includes: a serial-to-parallel conversion logic circuit for serial-to-parallel conversion of data in the input FIFO cache, a parallel-to-serial conversion logic circuit for parallel-to-serial conversion of the calculation result data, an instruction decoder for decoding instructions in an instruction register, an instruction parser for parsing instructions, a flow controller for controlling the reading and writing of controller data according to the data cache status in the internal cache, a data sending and recycling interface for interacting with the algorithm engine core module, a debug tracking signal output interface connected to the register stack module, a state machine FSM state output interface and a channel state monitor, a data register for temporarily storing data less than one packet in the data to be calculated, and a timeout detector for detecting whether the waiting data of a packet length in the internal cache has timed out.

In some embodiments of the present application, the flow control unit implements a state machine FSM, which starts the algorithm engine corresponding to the algorithm engine core module according to the type of algorithm. The state machine FSM controls the reading of data in the input FIFO cache, and after serial-to-parallel conversion by the serial-to-parallel conversion logic circuit, writes it into the algorithm engine core module through the data sending and recovery interface for encryption and decryption business operations. After the operation is completed, the state machine FSM obtains the operation result data and recovers it to the flow control unit through the data sending and recovery interface, and writes it into the output FIFO cache after parallel-to-serial conversion to wait for the controller to read it from the output FIFO cache.

In some embodiments of the present application, the flow controller requests the controller to read the output FIFO buffer when there is data in the output FIFO buffer, and generates a read enable for the output FIFO buffer according to the response signal of the controller; the flow control unit generates a pulse to start the read enable of the input FIFO buffer when the input FIFO buffer is not empty, and reads the data in the input FIFO buffer; when the data in the input FIFO buffer is full, the flow controller sends a stop data reading to the DMA read-write data flow control unit of the controller. Information.

In some embodiments of the present application, when the data received by the flow control unit cannot form a group, the data buffer temporarily stores the data that is less than a group. When the flow control unit receives subsequent data, it extracts the temporarily stored data and combines it with the subsequent data into a group.

In a second aspect, the present application provides an encryption and decryption control method, which is applied to an encryption and decryption architecture, including:

Configure the controller and register file modules;

Detect whether the encryption and decryption architecture is idle; if idle, start the controller, and the controller obtains the data to be calculated according to the configuration of the controller and transmits it to the data flow control module;

The data flow control module determines the algorithm type according to the configuration of the register stack module. The data flow control module controls the serial-to-parallel conversion of the data to be operated and writes it into the algorithm engine core module through the data sending and recovery interface to perform encryption and decryption business operations corresponding to the corresponding algorithm type; the data flow control module recovers the operation result data of the algorithm engine core module and sends it to the controller after parallel-to-serial conversion. The controller outputs the operation result data to the corresponding storage location according to the configuration of the controller.

In some embodiments of the present application, the configuration of the controller includes: configuring the data starting address register, data length register, data flag register, operation result starting address register and DMA start register in the DMA register of the controller; the controller is started according to the start indication of the DMA start register, and the controller obtains the data to be calculated through the bus according to the data starting address of the data starting address register and the data length of the data length register; when the calculation is completed, the controller obtains the calculation result data after the calculation from the data flow control module according to the address of the calculation result starting address register and writes it back to the corresponding storage address through the AHB master interface output channel.

In some embodiments of the present application, the configuration of the register stack module includes: configuring the first key register, the first initial vector register, the second key register, the second initial vector register and the instruction register of the register stack module, configuring the key and the initial vector required for the SM4 algorithm and the AES algorithm in the first key register, the first initial vector register, the second key register and the second initial vector register; configuring the number of encryption and decryption operations, the type of algorithm used, the algorithm mode and the algorithm start bit in the instruction register.

In some embodiments of the present application, detecting whether the encryption and decryption architecture is idle includes: the data flow control module configures a debug trace signal output interface, a state machine FSM state output interface and a channel status monitor connected to a channel status register in a register stack module, outputs the debug trace signal state machine FSM state and the channel status to the channel status register, and obtains the channel status monitor data in the channel status register to detect whether the encryption and decryption architecture is idle.

In some embodiments of the present application, the flow control unit of the data flow control module determines whether the algorithm needs key expansion based on the configuration of the register stack module. If key expansion is required, key expansion is performed first and then encryption and decryption processing is performed.

In some embodiments of the present application, the flow controller of the flow control unit of the data flow control module requests the controller to read the output FIFO cache when there is data in the output FIFO cache, and generates a read enable for the output FIFO cache based on a response signal from the controller; the flow control unit generates a pulse to start the read enable of the input FIFO cache and read the data in the input FIFO cache when the input FIFO cache is not empty; when the input FIFO cache is full of data, the flow controller sends information to stop reading data to the DMA read-write data flow control unit of the controller.

In some embodiments of the present application, the flow control unit of the data flow control module treats the operation data according to the set data length. The data that cannot form a complete group is temporarily stored in the data buffer to wait for subsequent data, and the waiting group data is timed by the timeout detector.

In some embodiments of the present application, the flow control unit of the data flow control module monitors errors and packet data timeouts during the processing of operation data and key processing and generates corresponding interrupts.

In a third aspect, the present application provides a processor, wherein the processor configuration includes an encryption and decryption architecture.

In a fourth aspect, the present application provides a server, the server comprising: at least one CPU, at least one processor configured with an encryption and decryption architecture, the processor being connected to the CPU via an AHB bus.

The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

The controller of this application is connected to the data flow control module, and the controller starts and transmits the data to be calculated to the data flow control module according to the configuration in the DMA register; the data flow control module sends the data to be calculated to the algorithm engine core module in groups according to the AES and/or SM4 encryption algorithm. The algorithm engine core module integrates the SM4 algorithm engine and the AES algorithm engine that can independently complete their respective algorithm operations. After the data flow control module determines the type of algorithm to be executed, it controls the algorithm engine core module to start the corresponding algorithm engine. The algorithm engine core module uses the data to be calculated provided by the data flow control module and the key and initial vector required for the encryption and decryption operation configured in the register stack module to perform encryption and decryption operations, and feeds back the operation result data to the data flow control module. The data flow control module outputs the operation result data through the controller, and the controller outputs the operation result data to the specified storage location according to the configuration in the DMA register. The encryption and decryption architecture can automatically perform encryption and decryption processing on the data to be calculated under the CPU configuration, supporting both the SM4 algorithm and the AES algorithm. When the encryption and decryption architecture of this application is connected to the CPU, the CPU only needs to configure the encryption and decryption architecture to perform calculations, without the CPU participating in the calculation process, liberating the CPU's computing power and enhancing the competitiveness of the product.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

FIG1 is a schematic diagram of an encryption and decryption architecture provided in an embodiment of the present application;

FIG2 is a schematic diagram of the architecture of a controller provided in an embodiment of the present application;

FIG3 is a schematic diagram of the architecture of a register file module provided in an embodiment of the present application;

FIG4 is a schematic diagram of the architecture of a data flow control module provided in an embodiment of the present application;

FIG5 is a schematic diagram of the architecture of the algorithm engine core module provided in an embodiment of the present application;

FIG6 is a schematic diagram of the states, state transitions, and state transition conditions of a state machine FSM provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are the embodiments of the present application. All other embodiments obtained by ordinary technicians in this field based on the embodiments in this application without creative work are within the scope of protection of this application.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Referring to FIG. 1 , in some embodiments of the present application, an encryption and decryption architecture is provided, including: a controller, a register stack module, an algorithm engine core module, and a data flow control module. The controller is connected to the outside through a bus and the controller is connected to the data flow control module, and the controller transmits the data to be operated to the data flow control module; the data flow control module sends the data to be operated to the algorithm engine core module in groups according to the grouping method of the AES and/or SM4 encryption algorithm, and the algorithm engine core module integrates the SM4 algorithm engine and the AES algorithm engine that can independently complete their respective algorithm operations. After the data flow control module determines the type of algorithm to be executed, it controls the algorithm engine core module to start the corresponding algorithm engine, and the algorithm engine core module uses the data to be operated provided by the data flow control module and the key and initial vector required for the encryption and decryption operation configured in the register stack module to perform encryption and decryption operations and feeds back the operation results to the data flow control module, and the data flow control module outputs the operation result data through the controller.

As shown in FIG. 2 , the controller internally integrates a DMA register and a DMA read/write data flow control unit; the DMA register is connected to the AHB bus via an AHB slave interface; and the DMA read/write data flow control unit is connected to the AHB bus via an AHB master interface. After DMA is started, the DMA read/write data flow control unit of the controller reads the corresponding storage address to the data to the internal cache of the data flow control module through the AHB master interface input channel according to the configuration in the DMA register. When the operation is completed, the DMA read/write data flow control unit of the controller obtains the encrypted or decrypted data after the operation from the internal cache, and writes the encrypted or decrypted data after the operation back to the corresponding storage address through the AHB master interface output channel. The DMA register includes a data start address register for recording the start bit of the data to be operated, a data length register for recording the length of the data to be operated, a data flag register, a calculation result start address register for recording the start bit of the calculation result data, and a DMA start register for starting the controller. In the specific implementation process, the CPU configures the corresponding AHB master interface corresponding to the AHB slave interface of the DMA register, and the CPU controls the controller by configuring the DMA register through the AHB bus. The configuration of the controller by the CPU includes: configuring the data starting address register, the data length register, the data flag register in the DMA register of the controller, the operation result starting address register and the DMA start register to start the controller; the controller starts according to the start indication of the DMA start register, and the controller obtains the data to be operated through the bus according to the data starting address of the data starting address register and the data length of the data length register; when the operation is completed, the controller obtains the encrypted or decrypted data after the operation from the data flow control module according to the address of the operation result starting address register, and writes the operation result data back to the corresponding storage address through the AHB master interface output channel.

As shown in Figure 3, the register stack module is connected to the AHB bus based on the AHB slave interface, and the CPU configures the corresponding AHB master interface corresponding to the AHB slave interface of the register stack module, which is used by the CPU to configure the key and initial vector required for encryption and decryption operations in the register stack module, and the CPU obtains the operation status from the register stack module. In order to meet the requirements of running the AES algorithm and the SM4 algorithm in a single configuration, the register stack module configures the first key register and the first initial vector register for the AES algorithm, and the register The stack module configures the second key register and the second initial vector register for the SM4 algorithm; the register stack module provides multiple groups of channel status registers for recording the operation status. The CPU can access the channel status registers through the AHB bus to obtain the operation status. The operation status includes the completion status of the encryption and decryption business, the interrupt status, the channel abnormal status and the debugging and tracking status information; the register stack module provides a group of shared instruction registers. The instruction registers are used to provide the data flow control module with algorithm instructions that distinguish the algorithm type. The data flow control module controls the algorithm engine core module to start the corresponding algorithm engine according to the identified algorithm type. Specifically, the instruction register configures the number of encryption and decryption operations, the type of algorithm used, the algorithm mode, and starts the encryption and decryption business through the algorithm start bit.

Referring to FIG. 4 , the data flow control module includes an internal cache and a flow control unit. The internal cache includes an input FIFO cache and an output FIFO cache. The input FIFO cache is used to cache the data to be calculated read by the controller from the AHB bus, and the output FIFO is used to cache the calculation results of the data to be calculated. The flow control unit includes a serial-to-parallel conversion logic circuit for serial-to-parallel conversion of the data in the input FIFO cache, a parallel-to-serial conversion logic circuit for parallel-to-serial conversion of the calculation result data in the output FIFO cache, an instruction decoder for decoding instructions in the instruction register, an instruction parser for parsing instructions, a flow controller for controlling the reading and writing of controller data according to the data cache state in the internal cache, a data sending and recycling interface for interacting with the algorithm engine core module, a debug tracking signal output interface connected to the channel status register, a state machine FSM state output interface and a channel status monitor, a data temporary register for temporarily storing data less than one packet in the calculation data, and a timeout detector for detecting whether the data waiting for a packet length in the internal cache has timed out.

During the specific implementation process, the flow controller requests the controller to read the output FIFO buffer when there is data in the output FIFO buffer, and generates a read enable for the output FIFO buffer according to the response signal of the controller; when the data in the input FIFO buffer is full, the flow controller sends information to stop data reading to the DMA read-write data flow control unit of the controller; when the input FIFO buffer is not empty, the flow control unit generates a pulse to start the read enable of the input FIFO buffer and read the data in the input FIFO buffer. The flow control unit of the data flow control module groups the data to be operated according to the set data length, temporarily stores the data that cannot form a complete group through the data register to wait for subsequent data, and times the waiting group data through the timeout detector. The flow control unit of the data flow control module monitors errors and group data timeouts during the operation data and key processing and generates corresponding interrupts.

To realize the above control process, as shown in FIG6 , the flow control unit realizes the state machine FSM, which controls the reading of the data in the input FIFO buffer, and after the serial-to-parallel conversion by the serial-to-parallel conversion logic circuit, writes it into the algorithm engine core module through the data sending and recycling interface for encryption and decryption business operation. After the operation is completed, the state machine FSM obtains the operation result data and recycles it to the flow control unit through the data sending and recycling interface, and writes it into the output FIFO buffer after the parallel-to-serial conversion to wait for the controller to read it from the output FIFO buffer. Under the control of the state machine FSM, the data storage situation in the input FIFO buffer is monitored by the flow controller. When the data in the input FIFO buffer is full, the flow controller sends a message to stop data reading to the DMA read-write data flow control unit of the controller. The DMA read-write data flow control unit of the controller responds to the message to stop data reading and stops reading the data to be operated, thereby realizing flow control. The SM4 algorithm and the AES algorithm are block cipher algorithms. For example, the block length of the SM4 algorithm is 128 bits. The SM4 encryption algorithm and the key expansion algorithm both adopt 32 rounds of nonlinear iterative structure, and perform encryption operations in units of words (32 bits). Each iterative operation is a round of transformation function F. The structure of the SM4 algorithm encryption/decryption algorithm is the same, but the round keys used are opposite. The decryption round key is the reverse order of the encryption round key. The interface sends the packet data to the algorithm engine core module. Under the control of the state machine FSM, the data buffer temporarily stores data that is less than a packet. When the flow control unit receives subsequent data, it extracts the temporarily stored data and combines it with the subsequent data into a packet.

During the specific implementation process, the states, state transitions, and state transition conditions of the state machine FSM are as follows:

In the specific implementation process, referring to FIG5 , the SM4 algorithm engine internally includes an SM4 byte replacement unit, an SM4 encryption/decryption operation unit, and an SM4 key expansion unit. The SM4 byte replacement unit is used to perform a byte replacement operation, and replaces the input data with the corresponding data in bytes by searching the first lookup table and outputs the data; the SM4 encryption/decryption operation unit internally includes an SM4 byte replacement unit, an SM4 encryption/decryption operation unit, and an SM4 key expansion unit. It forms a 32-stage pipeline round function, which can realize the input and output of a single clock cycle. The round key generated by the SM4 key expansion module is used by the SM4 encryption/decryption operation unit; the AES algorithm engine unit integrates the three independent AES encryption/decryption operation units and AES key expansion units of AES-128, AES-192, and AES-256 algorithms, AES column confusion unit, and AES byte replacement unit. The AES byte replacement unit is mainly used for byte replacement operations. By looking up the second lookup table, the input data is replaced with the corresponding data in bytes and output. The state matrix of the AES column confusion unit after row shifting is multiplied with the fixed matrix to obtain the confused state matrix to implement column confusion transformation.

In some embodiments of the present application, there is also provided an encryption and decryption control method, which is applied to an encryption and decryption architecture, including:

The controller and register stack module are configured. In the specific implementation process, the configuration of the controller includes: configuring the data starting address register, data length register, data flag register, operation result starting address register and DMA start register in the controller's DMA register; the controller starts according to the start indication of the DMA start register, and the controller obtains the data to be operated through the bus according to the data starting address of the data starting address register and the data length of the data length register; when the operation is completed, the controller obtains the encrypted or decrypted data after the operation from the data flow control module according to the address of the operation result starting address register, and writes the operation result data back to the corresponding storage address through the AHB master interface output channel. The configuration of the register stack module includes: configuring the first key register, the first initial vector register, the second key register, the second initial vector register and the instruction register of the register stack module, configuring the key and initial vector required by the SM4 algorithm and the AES algorithm in the first key register, the first initial vector register, the second key register and the second initial vector register; configuring the number of encryption and decryption operations, the type of algorithm used, the algorithm mode and the algorithm start bit in the instruction register.

Detect whether the encryption and decryption architecture is idle; if idle, start the controller, and the controller obtains the data to be calculated and transmits it to the data flow control module according to the configuration of the controller. In the specific implementation process, detecting whether the encryption and decryption architecture is idle includes: the data flow control module configures the debug tracking signal output interface, the state machine FSM state output interface and the channel state monitor connected to the channel state register in the register stack module, outputs the debug tracking signal state machine FSM state and the channel state to the channel state register, and obtains the channel state monitor data in the channel state register to detect whether the encryption and decryption architecture is idle.

The data flow control module determines the algorithm type according to the configuration of the register stack module. The data flow control module controls the serial-to-parallel conversion of the data to be operated and writes it into the algorithm engine core module through the data sending and recycling interface to perform encryption and decryption business operations corresponding to the corresponding algorithm type. In the specific implementation process, the flow control unit of the data flow control module determines whether the algorithm needs key expansion based on the configuration of the register stack module. If key expansion is required, key expansion is performed first and then encryption and decryption processing is performed.

When the data flow control module processes the data to be calculated, the flow controller of the flow control unit of the data flow control module requests the controller to read the output FIFO buffer when there is data in the output FIFO buffer, and generates a read enable of the output FIFO buffer according to the response signal of the controller; the flow control unit generates a pulse to start the read enable of the input FIFO buffer when the input FIFO buffer is not empty, and reads the data in the input FIFO buffer; when the data in the input FIFO buffer is full, the flow controller sends a message to stop data reading to the DMA read-write data flow control unit of the controller. The flow control unit of the data flow control module groups the data to be calculated according to the set data length, temporarily stores the data that cannot form a complete group through the data temporary register to wait for subsequent data, and times the waiting grouped data through the timeout detector. The flow control unit of the data flow control module monitors errors and grouped data timeouts in the process of processing the calculated data and the key, and generates corresponding interrupts.

During the specific implementation process, the data flow control module realizes the processing of the data to be calculated and/or the key through the state machine FSM of Example 1.

The data flow control module recycles the operation result data of the algorithm engine core module and sends it to the controller after parallel-to-serial conversion. The controller outputs the operation result data to the corresponding storage location according to the configuration of the controller.

In some embodiments of the present application, a processor is provided, and an encryption and decryption architecture configured by the processor performs SM4 algorithm or AES algorithm encryption and decryption operations on data at a set storage location and returns the result. In the specific implementation process, the processor of this embodiment can be a BMC or an FPGA.

In some embodiments of the present application, a server compatible with AES and SM4 encryption algorithms is also provided, including at least one CPU and at least one processor configured with an encryption and decryption architecture. In the server, a feasible processor uses a BMC.

During the specific implementation process, the processor is connected to the CPU via the AHB bus. Specifically, the CPU is connected to the DMA register of the controller via the AHB bus, and the CPU is connected to the first key register, the second key register, the first initial vector register, the second initial vector register and the instruction register of the register stack module via the AHB bus. The CPU controls the processor to implement encryption and decryption business operations: the CPU queries the channel status register. If the data monitored by the channel status monitor in the channel status register shows that the channel status is idle, it executes: the CPU configures the DMA register, including the data starting address register, data length register, data flag register, and operation result starting address register in the DMA register, and finally configures the DMA start register to start the controller. Configure the first key register and/or the second key register, the first initial vector register and/or the second initial vector register, and prepare the key or initial vector required for the operation. The CPU configures the instruction register to determine the number of encryption and decryption operations, the type of algorithm used, the algorithm mode, and start the encryption and decryption business. The controller obtains the data to be calculated according to the values of the data start address register and the data length register. The data flow control module controls the algorithm engine core module to perform the corresponding operation according to the applicable algorithm type provided by the instruction register, and recovers the operation result data calculated by the algorithm engine core module, and then transmits it to the controller. After the encryption and decryption business operation result data is transmitted to the controller, the controller writes the data to the corresponding position according to the previously configured operation result start address, and issues an interrupt to inform the CPU after the write-back is completed. After receiving the interrupt, the CPU clears the interrupt and obtains the operation result data at the corresponding address.

In the several embodiments provided in the present application, it should be understood that the disclosed modules and units can be implemented in other ways. For example, the structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, systems or units, which can be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

Although the present application has been described in detail with reference to the accompanying drawings and in conjunction with the preferred embodiments, the present application is not limited to Hereby. Without departing from the spirit and essence of this application, ordinary technicians in this field can make various equivalent modifications or substitutions to the embodiments of this application, and these modifications or substitutions should be within the scope of this application. Any technician familiar with this technical field can easily think of changes or substitutions within the technical scope disclosed in this application, which should be included in the protection scope of this application. Therefore, the protection scope of this application shall be based on the protection scope of the claims.

Claims

A cryptographic architecture, characterized in that it comprises: a controller, which is connected to the outside through a bus to achieve communication with the outside; a data flow control module, which is connected to the controller; an algorithm engine core module, which is connected to the data flow control module; and a register stack module, which is connected to the outside through a bus and is also connected to the data flow control module; wherein the algorithm engine core module performs cryptographic operations using the grouped data to be operated provided by the data flow control module and the key and initial vector required for the cryptographic operations configured in the register stack module, and feeds back the operation result data of the cryptographic operations to the data flow control module, and the data flow control module outputs the operation result data through the controller.
According to the encryption and decryption architecture of claim 1, it is characterized in that the algorithm engine core module integrates an SM4 algorithm engine and an AES algorithm engine that can independently complete their respective algorithm operations.
According to the encryption and decryption architecture of claim 2, it is characterized in that the SM4 algorithm engine internally includes an SM4 byte replacement unit, an SM4 encryption/decryption operation unit and an SM4 key expansion unit, the SM4 byte replacement unit is used to perform byte replacement operations, and the input data is replaced with corresponding data in bytes by searching the first lookup table and output; the SM4 encryption/decryption operation unit internally integrates a 32-level pipeline round function, which can realize the input and output of a single clock cycle, and the round key generated by the SM4 key expansion module is used by the SM4 encryption/decryption operation unit; the AES algorithm engine unit integrates three independent AES encryption/decryption operation units and AES key expansion units of AES-128, AES-192, and AES-256 algorithms, an AES column confusion unit, and an AES byte replacement unit. The AES byte replacement unit is mainly used to perform byte replacement operations, and the input data is replaced with corresponding data in bytes by searching the second lookup table and output, and the state matrix of the AES column confusion unit after row shifting is multiplied by a fixed matrix to obtain the obfuscated state matrix to implement column obfuscation transformation.
According to the encryption and decryption architecture of claim 1, it is characterized in that the controller internally integrates a DMA register and a DMA read-write data flow control unit; the DMA register is connected to the AHB bus via an AHB slave interface; the DMA read-write data flow control unit is connected to the AHB bus via an AHB master interface, and the DMA read-write data flow control unit is connected to the data flow control module; the DMA read-write data flow control unit obtains the data to be calculated through the AHB bus according to the configuration in the DMA register and transmits it to the data flow control module.
The encryption and decryption architecture according to claim 1 is characterized in that the register stack module is connected to the AHB bus connected to the outside through an AHB slave interface, and the register stack module is connected to the data flow control module through the internal bus; the register stack module configures the first key register and the first initial vector register for the AES algorithm implemented by the algorithm engine core module, and the register stack module configures the second key register and the second initial vector register for the SM4 algorithm implemented by the algorithm engine core module; the register stack module configures multiple groups of channel status registers for recording the operation status; the register The stack module configures a set of instruction registers.
The encryption and decryption architecture according to claim 4 or 5 is characterized in that the AHB slave interface corresponding to the register stack module and the DMA register is connected to the CPU of the corresponding AHB master interface via the AHB bus.
The encryption and decryption architecture according to claim 1 is characterized in that the data flow control module includes an internal cache and a flow control unit; wherein the internal cache includes an input FIFO cache and an output FIFO cache, the input FIFO cache is used to cache the data to be calculated read by the controller using the bus, and the output FIFO is used to cache the calculation result data output by the algorithm engine core module to the data to be calculated; the flow control unit includes: a serial-to-parallel conversion logic circuit for serial-to-parallel conversion of data in the input FIFO cache, a parallel-to-serial conversion logic circuit for parallel-to-serial conversion of the calculation result data, an instruction decoder for decoding instructions in the instruction register, an instruction parser for parsing instructions, a flow controller for controlling the reading and writing of controller data according to the data cache state in the internal cache, a data sending and recovery interface for interacting with the algorithm engine core module, a debug tracking signal output interface connected to the register stack module, a state machine FSM state output interface and a channel state monitor, a data temporary register for temporarily storing data less than one packet in the data to be calculated, and a timeout detector for detecting whether the waiting data of one packet length in the internal cache has timed out.
According to the encryption and decryption architecture of claim 7, it is characterized in that the flow control unit implements a state machine FSM, the state machine FSM starts the algorithm engine corresponding to the algorithm engine core module according to the algorithm type, the state machine FSM controls the reading of data in the input FIFO cache, and after serial-to-parallel conversion by the serial-to-parallel conversion logic circuit, writes it into the algorithm engine core module through the data sending and recycling interface to perform encryption and decryption business operations, after the operation is completed, the state machine FSM obtains the operation result data and recovers it to the flow control unit through the data sending and recycling interface, and writes it into the output FIFO cache after parallel-to-serial conversion to wait for the controller to read it from the output FIFO cache.
According to the encryption and decryption architecture of claim 7, it is characterized in that the flow controller requests the controller to read the output FIFO cache when there is data in the output FIFO cache, and generates a read enable of the output FIFO cache according to the response signal of the controller; the flow control unit generates a pulse to start the read enable of the input FIFO cache when the input FIFO cache is not empty, and reads the data in the input FIFO cache; when the data in the input FIFO cache is full, the flow controller sends a message to stop data reading to the DMA read and write data flow control unit of the controller.
According to the encryption and decryption architecture of claim 7, it is characterized in that when the data received by the flow control unit cannot realize a group, the data temporary storage will temporarily store the data that is less than a group, and when the flow control unit receives subsequent data, it extracts the temporarily stored data and combines it with the subsequent data into a group.
An encryption and decryption control method, applied to the encryption and decryption architecture according to any one of claims 1 to 10, characterized in that it comprises:

Configure the controller and register file modules;

Detect whether the encryption and decryption architecture is idle; if idle, start the controller, and the controller obtains the waiting state according to the configuration of the controller. The calculation data is transmitted to the data flow control module;

The data flow control module determines the algorithm type according to the configuration of the register stack module. The data flow control module controls the serial-to-parallel conversion of the data to be operated and writes it into the algorithm engine core module through the data sending and recovery interface to perform encryption and decryption business operations corresponding to the corresponding algorithm type; the data flow control module recovers the operation result data of the algorithm engine core module and sends it to the controller after parallel-to-serial conversion. The controller outputs the operation result data to the corresponding storage location according to the configuration of the controller.
According to the encryption and decryption control method of claim 11, it is characterized in that the configuration of the controller includes: configuring the data starting address register, data length register, data flag register, operation result starting address register and DMA start register in the DMA register of the controller; the controller is started according to the start indication of the DMA start register, and the controller obtains the data to be operated through the bus according to the data starting address of the data starting address register and the data length of the data length register; when the operation is completed, the controller obtains the operation result data after the operation from the data flow control module according to the address of the operation result starting address register and writes it back to the corresponding storage address through the AHB master interface output channel.
According to the encryption and decryption control method of claim 11, it is characterized in that the configuration of the register stack module includes: configuring the first key register, the first initial vector register, the second key register, the second initial vector register and the instruction register of the register stack module, configuring the key and initial vector required for the SM4 algorithm and the AES algorithm in the first key register, the first initial vector register, the second key register and the second initial vector register; configuring the number of encryption and decryption operations, the type of algorithm used, the algorithm mode and the algorithm start bit in the instruction register.
According to the encryption and decryption control method of claim 11, it is characterized in that detecting whether the encryption and decryption architecture is idle includes: the data flow control module configures a debug trace signal output interface, a state machine FSM state output interface and a channel status monitor connected to the channel status register in the register stack module, outputs the debug trace signal state machine FSM state and the channel status to the channel status register, and obtains the channel status monitor data in the channel status register to detect whether the encryption and decryption architecture is idle.
According to the encryption and decryption control method of claim 11, it is characterized in that the flow control unit of the data flow control module determines whether the algorithm needs to perform key expansion based on the configuration of the register stack module. If key expansion is required, key expansion is performed first and then encryption and decryption processing is performed.
The encryption and decryption control method according to claim 10 is characterized in that the flow controller of the flow control unit of the data flow control module requests the controller to read the output FIFO buffer when there is data in the output FIFO buffer, and generates a read enable of the output FIFO buffer according to the response signal of the controller; the flow control unit generates a pulse to start the read enable of the input FIFO buffer when the input FIFO buffer is not empty, and reads the data in the input FIFO buffer; when the data in the input FIFO buffer is full, the flow controller sends a signal to stop data reading to the DMA read-write data flow control unit of the controller. interest.
According to the encryption and decryption control method of claim 10, it is characterized in that the flow control unit of the data flow control module groups the data to be operated according to the set data length, temporarily stores the data that cannot form a complete group through the data buffer to wait for subsequent data, and times the waiting group data through the timeout detector.
According to the encryption and decryption control method of claim 17, it is characterized in that the flow control unit of the data flow control module monitors errors and packet data timeouts during the processing of operation data and key and generates corresponding interrupts.
A processor, characterized in that the processor is configured with the encryption and decryption architecture as described in any one of claims 1-10.
A server, characterized in that the server comprises: at least one CPU, at least one processor configured with the encryption and decryption architecture as described in any one of claims 1-10, and the processor is connected to the CPU via an AHB bus.