WO2024109624A1 - 一种数据处理的方法以及计算机设备 - Google Patents

一种数据处理的方法以及计算机设备 Download PDF

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Publication number
WO2024109624A1
WO2024109624A1 PCT/CN2023/132084 CN2023132084W WO2024109624A1 WO 2024109624 A1 WO2024109624 A1 WO 2024109624A1 CN 2023132084 W CN2023132084 W CN 2023132084W WO 2024109624 A1 WO2024109624 A1 WO 2024109624A1
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Prior art keywords
interrupt
processor
identifier
data queue
data
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PCT/CN2023/132084
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English (en)
French (fr)
Inventor
章新豪
万波
蒋毅飞
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华为技术有限公司
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Publication of WO2024109624A1 publication Critical patent/WO2024109624A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication

Definitions

  • the present application relates to the field of computers, and more specifically, to a data processing method and a computer device.
  • IO virtualization technology provides virtual machines with the ability to reuse physical devices.
  • the worker thread needs to poll the data queues shared by all devices and virtual machines to obtain IO data, but not all shared data queues contain IO data that needs to be processed.
  • the data queue polled by the worker thread is empty, the tail delay of processing IO data will increase.
  • the frequency of IO requests sent by different devices and virtual machines is different, and the amount of data requested by IO and the time for device processing are also different, which leads to load imbalance of the worker threads bound to the data queue, reducing the overall peak bandwidth of the system.
  • An embodiment of the present application provides a data processing method and a computer device.
  • the interrupt controller can determine the data queue identifier based on the interrupt request and add the data queue identifier to the memory.
  • the interrupt controller can directly obtain the data queue identifier from the memory and send it to the processor, so that the processor can process without polling all data queues, thereby reducing the tail delay of processing IO data and the overall peak bandwidth of the system.
  • a method for data processing is provided, which is applied to a computer device, wherein the computer device includes an interrupt controller, a first processor and a memory, wherein the memory is used to store a data queue identifier, and the processor is used to process data in the data queue, the method comprising: the interrupt controller obtains first interrupt request information, wherein the first interrupt request information is used to indicate a first data queue identifier; the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory; the processor sends a first interrupt processing request to the interrupt controller according to the first interrupt notification; the interrupt controller sends the first data queue identifier to the processor according to the first interrupt processing request and moves the first data queue identifier out of the memory; the processor processes the data of the first data queue, wherein the first data queue is a data queue corresponding to the first data queue identifier.
  • the interrupt controller when there is an interrupt request, can determine the data queue identifier based on the interrupt request and add the data queue identifier to the memory.
  • the interrupt controller can directly obtain the data queue identifier from the memory and send the data queue identifier to the processor.
  • the data queue corresponding to the data queue identifier includes data to be processed, so that the processor does not need to poll all data queues, which can reduce the tail delay of processing IO data and the overall peak band of the system.
  • the method also includes: when the processor detects that there is unprocessed data in the first data queue, it sends a first counter-request to the interrupt controller to instruct the interrupt controller to resend the interrupt notification for processing the first data queue.
  • the processor when there is still unprocessed data in the data queue, the processor can re-request the interrupt processor to send a corresponding interrupt notification through a counter-request, so as to process the data queue again.
  • the computer device includes a queue of data to be processed, which is used to store the first data queue identifier.
  • the method also includes: the processor sends first load request information to the interrupt controller; the interrupt controller adds a processor identifier or a first work thread identifier to the load request queue according to the first load request information, wherein the processor identifier is used to indicate the processor, the first work thread identifier is used to indicate the first work thread, and the first work thread runs on the processor.
  • the computer device includes a to-be-processed data queue, the to-be-processed data queue is used to store a data queue identifier, and before the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory, the method further includes: the processor sends first load request information to the interrupt controller; the interrupt controller The controller adds a processor identifier or a first work thread identifier to a load request queue according to the first load request information, wherein the processor identifier is used to indicate the processor, and the first work thread identifier is used to indicate the first work thread; the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory, including: the interrupt controller adds the first data queue identifier to a queue of data to be processed; the interrupt controller determines the processor identifier and the first data queue identifier according to the load request queue and the queue of data to be processed, and sends
  • the interrupt controller includes a work thread routing table, which is used to indicate the correspondence between the work thread and the processor identifier, and the interrupt controller adds the processor identifier or the first work thread identifier to the load request queue according to the first load request information, including: the interrupt controller adds the first work thread identifier to the load request queue according to the first load request information; the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory, including: the interrupt controller determines the processor identifier based on the work thread routing table and the first work thread identifier; the interrupt controller obtains the first data queue identifier from the data queue to be processed, and sends the first interrupt notification to the processor according to the processor identifier and adds the first data queue identifier to the memory.
  • the interrupt controller includes a work thread routing table, which is used to indicate the correspondence between the work thread and the processor identifier, and the interrupt controller adds the processor identifier or the first work thread identifier to the load request queue according to the first load request information, including: the interrupt controller adds the first work thread identifier to the load request queue according to the first load request information; the interrupt controller determines the processor identifier and the first data queue identifier based on the load request queue and the pending data queue, and sends the first interrupt notification to the processor based on the processor identifier and adds the first data queue identifier to the memory, including: the interrupt controller determines the processor identifier based on the work thread routing table and the first work thread identifier; the interrupt controller determines the first data queue identifier based on the pending data queue, and sends the first interrupt notification to the processor based on the processor identifier and adds the first data queue identifier to the memory.
  • the interrupt controller determines the processor identifier based on the work thread routing table
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between a data queue identifier and a processor identifier, and the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory, including: the interrupt controller determines a processor identifier based on the interrupt routing table and the first data queue identifier, and the processor identifier is used to indicate the processor; the interrupt controller sends the first interrupt notification to the processor based on the processor identifier and adds the first data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between a data queue identifier and a processor routing table address, the processing routing table address is used to point to the processor routing table, the interrupt controller sends a first interrupt notification to the processor and adds the first data queue identifier to the memory, including: the interrupt controller determines the first processor routing table address based on the interrupt routing table and the first data queue identifier; the interrupt controller determines the first processor index and the first processor routing table size based on the first processor routing table address; the interrupt controller determines the processor identifier based on the first processor index and the first processor routing table size, the processor identifier is used to indicate the processor; the interrupt controller sends the first interrupt notification to the processor based on the processor identifier and adds the first data queue identifier to the memory.
  • the method further includes: the first working thread is registered with a user-mode interrupt, and the first interrupt notification is a user-mode interrupt.
  • multiple worker threads and idle worker threads run on the processor, the idle worker thread is registered with a user state interrupt, the multiple worker threads are used to process data in a data queue, the multiple worker threads include the first worker thread, and when the multiple worker threads do not process the data in the data queue, the method also includes: the processor idle-loops the idle worker thread to put the processor in user state.
  • the processor is provided with a first user-state interrupt processing flag, and the first user-state interrupt processing flag is used to indicate whether the processor is processing a user-state interrupt.
  • the method also includes: when the processor processes data in the first data queue, the first user-state interrupt processing flag is set to indicate that a user-state interrupt is being processed.
  • a method for data processing is provided, characterized in that the method is applied to a computer device, the computer device includes an interrupt controller, a processor and a memory, the memory is used to store a data queue identifier, the processor runs a second working thread, the second working thread is used to process data in the data queue, the processor is provided with a user-mode interrupt pending flag and a user-mode interrupt enable flag, the user-mode interrupt pending flag is used to indicate whether the processor has a pending user-mode interrupt, and the user-mode interrupt enable flag is used to indicate whether the processor is enabled to process the user-mode interrupt, the method comprising: the interrupt controller obtains second interrupt request information; the interrupt controller determines a second data queue identifier according to the second interrupt request information; the interrupt controller sends a second interrupt request to the processor A second interrupt notification is sent and the second data queue identifier is added to the memory, the second interrupt notification is the user-state interrupt; the processor sets the user-state interrupt pending flag to the first state of the user-
  • the interrupt controller when there is an interrupt request, can determine the data queue identifier based on the interrupt request and add the data queue identifier to the memory, and the processor is provided with a user-state interrupt pending identification bit and a user-state interrupt enable identification bit.
  • the processor can send an interrupt processing request to the interrupt controller to obtain the data queue identifier.
  • the interrupt controller can directly obtain the data queue identifier from the memory and send the data queue identifier to the processor, without the need for the processor to poll all data queues, thereby reducing the tail delay of processing IO data and the overall peak bandwidth of the system.
  • the method further includes: when the processor detects that there is unprocessed data in the second data queue, it sends a second counter-request to the interrupt controller to instruct the interrupt controller to resend the interrupt notification for processing the second data queue.
  • the processor when there is still unprocessed data in the data queue, the processor can re-request the interrupt processor to send a corresponding interrupt notification through a counter-request, so as to process the data queue again.
  • the computer device includes a queue of data to be processed, which is used to store the second data queue identifier.
  • the method also includes: the processor sends second load request information to the interrupt controller; the interrupt controller adds a processor identifier or a second work thread identifier to the load request queue according to the second load request information, wherein the processor identifier is used to indicate the processor, and the second work thread identifier is used to indicate the second work thread.
  • the interrupt controller sends a second interrupt notification to the processor and adds the second data queue identifier to the memory, including: the interrupt controller adds the second data queue identifier to the data queue to be processed; the processor sends second load request information to the interrupt controller; the interrupt controller adds the processor identifier or the second work thread identifier to the load request queue according to the second load request information, wherein the processor identifier is used to indicate the processor, and the second work thread identifier is used to indicate the second work thread; the interrupt controller determines the second processing identifier and the second data queue identifier based on the load request queue and the data queue to be processed, and sends the second interrupt notification to the processor based on the processor identifier and adds the second data queue identifier to the memory.
  • the interrupt controller includes a work thread routing table, which is used to indicate the correspondence between the work thread and the processor identifier, and the interrupt controller adds the processor identifier or the second work thread identifier to the load request queue according to the second load request information, including: the interrupt controller adds the second work thread identifier to the load request queue according to the second load request information; the interrupt controller determines the second processing identifier and the second data queue identifier based on the load request queue and the data queue to be processed, and sends the second interrupt notification to the processor based on the processor identifier and adds the second data queue identifier to the memory, including: the interrupt controller determines the processor identifier based on the work thread routing table and the second work thread identifier; the interrupt controller determines the second data queue identifier based on the data queue to be processed, and sends the second interrupt notification to the processor based on the processor identifier and adds the second data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between a data queue identifier and a processor identifier, and the interrupt controller sends a second interrupt notification to the processor and adds the second data queue identifier to the memory, including: the interrupt controller determines a processor identifier based on the interrupt routing table and the first data queue identifier, and the processor identifier is used to indicate the processor; the interrupt controller sends the second interrupt notification to the processor based on the processor identifier and adds the second data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, the interrupt routing table is used to indicate the correspondence between the data queue identifier and the processor routing table address, the processing routing table address is used to point to the processor routing table, the interrupt controller sends a second interrupt notification to the processor and adds the second data queue identifier to the memory, including: the interrupt controller determines the second processor routing table address according to the interrupt routing table and the second data queue identifier; the interrupt controller determines the second processor index and the second processor routing table size according to the second processor routing table address; the interrupt controller determines the second processor index according to the second processor index and the second processor routing table size to determine a processor identifier, where the processor identifier is used to indicate the processor; the interrupt controller sends the second interrupt notification to the processor according to the processor identifier and adds the second data queue identifier to the memory.
  • the processor is provided with a second user-state interrupt processing flag, and the second user-state interrupt processing flag is used to indicate whether the processor is processing a user-state interrupt.
  • the method also includes: when the processor processes data in the second data queue, the second user-state interrupt processing flag is set to indicate that a user-state interrupt is being processed.
  • the processor also runs a business thread, which is used to handle business other than processing data queues.
  • the interrupt controller is set with a blocking flag, which is used to indicate the status of the second working thread.
  • the method also includes: when the processor determines that the data queue is not processed, the processor adjusts the second working thread to a sleep state and sets the blocking flag to indicate that the state of the second working thread is the sleep state.
  • a computer device which includes an interrupt controller, a processor and a memory, wherein the memory is used to store a data queue identifier, and the processor is used to process data in the data queue, wherein the interrupt controller is used to obtain first interrupt request information, and the first interrupt request information indicates a first data queue identifier; the interrupt controller is also used to send a first interrupt notification to the processor and add the first data queue identifier to the memory; the processor is used to send a first interrupt processing request to the interrupt controller according to the first interrupt notification; the interrupt controller is also used to send the first data queue identifier to the processor according to the first interrupt processing request and move the first data queue identifier out of the memory; the processor is also used to process the data of the first data queue, and the first data queue is a data queue corresponding to the first data queue identifier.
  • the processor is further used to send a first counter-request to the interrupt controller to instruct the interrupt controller to resend the interrupt notification for processing the first data queue when it is detected that there is unprocessed data in the first data queue.
  • the computer device includes a queue of data to be processed, and the interrupt controller is further used to add the first data queue identifier to the queue of data to be processed;
  • the processor is further used to send first load request information to the interrupt controller before the interrupt controller sends a first interrupt notification to the first processor and adds the first data queue identifier to the memory;
  • the interrupt controller is further used to add a processor identifier or a first working thread identifier to the load request queue according to the first load request information, wherein the processor identifier is used to indicate the processor, and the first working thread identifier is used to indicate the first working thread;
  • the interrupt controller is specifically used to determine the processor identifier and the first data queue identifier according to the load request queue and the queue of data to be processed, and send the first interrupt notification to the processor according to the processor identifier and add the first data queue identifier to the memory.
  • the interrupt controller includes a work thread routing table, which is used to indicate the correspondence between the work thread and the processor identifier, wherein the interrupt controller is specifically used to add the first work thread identifier to the load request queue according to the first load request information; the interrupt controller is also used to determine the processor identifier according to the work thread routing table and the first work thread identifier; the interrupt controller is specifically used to determine the first data queue identifier according to the data queue to be processed, and send the first interrupt notification to the processor according to the processor identifier and add the first data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between the data queue identifier and the processor identifier, wherein the interrupt controller is also used to determine the processor identifier based on the interrupt routing table and the first data queue identifier, and the processor identifier is used to indicate the processor; the interrupt controller is specifically used to send the first interrupt notification to the processor based on the processor identifier and add the first data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between the data queue identifier and the processor routing table address, and the processor routing table address is used to point to the processor routing table, wherein the interrupt controller is also used to determine the first processor routing table address based on the interrupt routing table and the first data queue identifier; the interrupt controller is also used to determine the first processor index and the first processor routing table size based on the first processor routing table address; the interrupt controller is also used to determine the processor identifier based on the first processor index and the first processor routing table size, and the processor identifier is used to indicate the processor; the interrupt controller is specifically used to send the first interrupt notification to the processor based on the processor identifier and add the first data queue identifier to the memory.
  • an interrupt routing table which is used to indicate the correspondence between the data queue identifier and the processor routing table address, and the processor routing table address is used to point to the processor routing table, wherein the interrupt controller is also used to determine the first processor routing table address based on the interrupt routing table and the first data
  • the first working thread is registered with a user-mode interrupt
  • the first interrupt notification is a user-mode interrupt
  • the processor runs multiple working threads and an idle working thread, the idle working thread is registered with a user state interrupt, the multiple working threads are used to process data in the data queue, and the multiple working threads include the The first working thread, when the multiple working threads are not processing the data in the data queue, the processor is also used to idle-loop the idle working thread to put the processor in user mode.
  • the processor is provided with a first user-state interrupt processing flag, and the first user-state interrupt processing flag is used to indicate whether the processor is processing a user-state interrupt.
  • the processor is also used to set the first user-state interrupt processing flag to indicate that a user-state interrupt is being processed when processing data in the first data queue.
  • a computer device comprising an interrupt controller, a processor and a memory, the memory being used to store a data queue identifier, the processor running a second working thread, the second working thread being used to process data in the data queue, the processor being provided with a user state interrupt pending identification bit and a user state interrupt enable identification bit, the user state interrupt pending identification bit being used to indicate whether the processor has a pending user state interrupt, the user state interrupt enable identification bit being used to indicate whether the processor is enabled to process the user state interrupt, wherein the interrupt controller is used to obtain second interrupt request information, the second interrupt request information indicating a second data queue identifier; the interrupt controller is further used to send a second interrupt notification to the processor and add the second data queue identifier to the memory, the second interrupt notification being the user state interrupt; The processor is used to set the user-state interrupt pending flag to the first state of the user-state interrupt pending flag according to the second interrupt notification, the first state of the user-state interrupt pending flag indicating
  • the processor is further used to send a second counter-reply request to the interrupt controller to instruct the interrupt controller to resend the interrupt notification for processing the second data queue when detecting that there is unprocessed data in the second data queue.
  • the interrupt controller is further used to add the second data queue identifier to the queue of data to be processed; the processor is further used to send second load request information to the interrupt controller; the interrupt controller is further used to add the processor identifier or the second work thread identifier to the load request queue according to the second load request information, wherein the processor identifier is used to indicate the processor, and the second work thread identifier is used to indicate the second work thread; the interrupt controller is specifically used to send the second interrupt notification to the processor according to the load request queue and the queue of data to be processed and add the second data queue identifier to the memory.
  • the interrupt controller includes a work thread routing table, which is used to indicate the correspondence between the work thread and the processor identifier, wherein the interrupt controller is specifically used to add the second work thread identifier to the load request queue according to the second load request information; the interrupt controller is also used to determine the processor identifier based on the work thread routing table and the second work thread identifier.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between the data queue identifier and the processor identifier, wherein the interrupt controller is also used to determine the processor identifier based on the interrupt routing table and the first data queue identifier, and the processor identifier is used to indicate the processor; the interrupt controller is specifically used to send the second interrupt notification to the processor based on the processor identifier and add the second data queue identifier to the memory.
  • the interrupt controller includes an interrupt routing table, which is used to indicate the correspondence between the data queue identifier and the processor routing table address, and the processor routing table address is used to point to the processor routing table, wherein the interrupt controller is also used to determine the second processor routing table address based on the interrupt routing table and the second data queue identifier; the interrupt controller is also used to determine the second processor index and the second processor routing table size based on the second processor routing table address; the interrupt controller is also used to determine the processor identifier based on the second processor index and the second processor routing table size, and the processor identifier is used to indicate the processor; the interrupt controller is specifically used to send the second interrupt notification to the processor based on the processor identifier and add the second data queue identifier to the memory.
  • an interrupt routing table which is used to indicate the correspondence between the data queue identifier and the processor routing table address, and the processor routing table address is used to point to the processor routing table, wherein the interrupt controller is also used to determine the second processor routing table address based on the interrupt routing table and the second data
  • the processor is provided with a second user-state interrupt processing flag, and the second user-state interrupt processing flag is used to indicate whether the processor is processing a user-state interrupt.
  • the processor is also used to set the second user-state interrupt processing flag to indicate that a user-state interrupt is being processed when processing data in the second data queue.
  • the processor also runs a service thread, the service thread is used to process services other than processing the data queue, the interrupt controller is provided with a blocking flag, the blocking flag is used to indicate the state of the second working thread, wherein the processor is further used to adjust the second working thread to a dormant state and The blocking flag is set to indicate that the state of the second working thread is the dormant state.
  • the fifth aspect is a chip of an embodiment of the present application, which is coupled to a memory in an electronic device and is used to call a computer program stored in the memory and execute the above-mentioned aspects of the embodiment of the present application and any possible design of the above-mentioned aspects of the embodiment of the present application; "coupling" in the embodiment of the present application refers to the direct or indirect combination of two components with each other.
  • the sixth aspect is a computer-readable storage medium of an embodiment of the present application, which includes a computer program.
  • the computer program runs on an electronic device, the electronic device executes a technical solution such as the above aspect and any possible design of the above aspect.
  • the seventh aspect is a computer program according to an embodiment of the present application, which includes instructions.
  • the instructions When the instructions are executed on a computer, the computer executes a technical solution such as the above aspect and any possible design of the above aspect.
  • FIG1 is a schematic diagram of the structure of a computer device provided in an embodiment of the present application.
  • FIG. 2 is a schematic flow chart of a method for virtual IO processing.
  • FIG. 3 is a schematic structural diagram of an interrupt controller provided in an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an interruption collection device provided in an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an interrupt routing device provided in an embodiment of the present application.
  • FIG6 is a schematic structural diagram of an interrupt delivery device provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an interrupt interaction device provided in an embodiment of the present application.
  • FIG8 is a schematic diagram of data flow of an interrupt controller provided in an embodiment of the present application.
  • FIG. 9 is a diagram of a work thread scheduling framework provided in an embodiment of the present application.
  • FIG10 is a framework diagram of a work thread provided in an embodiment of the present application during operation.
  • FIG. 11 is a schematic diagram of another data plane processing model provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another data plane processing model provided in an embodiment of the present application.
  • FIG. 13 is a schematic flow chart of a data processing method provided in an embodiment of the present application.
  • FIG. 14 is a schematic flow chart of a data processing method provided in an embodiment of the present application.
  • FIG. 15 is a schematic flowchart of a data processing method provided in an embodiment of the present application.
  • a and/or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.
  • the character "/” generally indicates that the objects associated before and after are in an "or” relationship.
  • references to "one embodiment” or “some embodiments” etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application.
  • the phrases “in one embodiment”, “in some embodiments”, “in some other embodiments”, “in some other embodiments”, etc. appearing in different places in this specification do not necessarily all refer to the same embodiment, but mean “one or more but not all embodiments", unless otherwise specifically emphasized in other ways.
  • the terms “including”, “comprising”, “having” and their variations all mean “including but not limited to”, unless otherwise specifically emphasized in other ways.
  • Virtualization is the process of virtualizing the hardware resources (e.g., processors, memory, and network resources) in the hardware layer of a computer device and sharing them with one or more virtual computers.
  • a virtual computer is a general term for the operating environment virtualized by software in all types of virtualized devices. Virtual computers can include virtual machines and containers.
  • the computer device 100 includes a hardware layer 101, a host machine layer 102 and a virtualization layer 103, wherein the virtualization layer 103 may include one or more virtual machines, such as virtual machine 104 and virtual machine 105, the hardware layer includes a processor system 106, a memory 107, a communication interface 108, and an interrupt controller 109, and the processor system includes one or more processors, such as processor 110 and processor 111.
  • the virtualization layer 103 may include one or more virtual machines, such as virtual machine 104 and virtual machine 105
  • the hardware layer includes a processor system 106, a memory 107, a communication interface 108, and an interrupt controller 109
  • the processor system includes one or more processors, such as processor 110 and processor 111.
  • FIG. 1 only takes the example that the virtualization layer includes virtual machines 104 and 105 , and the processor system 106 includes processors 110 and 111 , but the embodiments of the present application are not limited thereto.
  • a virtual machine is one or more virtual computers simulated on a computer device through virtualization software.
  • a virtual machine can run in a completely isolated environment and work just like a real computer.
  • a guest operating system (guest OS) can be installed on the virtual machine (i.e., 104 and 105 in FIG. 1 ), and one or more applications can run on the guest OS.
  • the virtual machine can also access network resources. For applications running in a virtual machine, it is like working in a real computer.
  • the virtual machine privilege level which includes the user state of the virtual machine and the kernel state of the virtual machine.
  • the division of the kernel state of the virtual machine and the user state of the virtual machine is to divide the virtual machine as a real computer.
  • the virtual address space can be divided into kernel space and user space.
  • the kernel space can also be called kernel state virtual address space
  • the user space can also be called user state virtual address space.
  • the process or thread running in the user space can be called the process or thread in the user state
  • the process or thread running in the kernel space can be called the process or thread in the kernel state.
  • a virtual machine may include a virtual processor, which may be understood as a physical processing unit provided to a virtual machine in a shared or slicing manner under virtualization technology, such as a virtual central processing unit (VCPU).
  • a virtual machine may have one or more virtual processors. When there are multiple virtual processors, one virtual processor may be selected as the primary virtual processor and the others as secondary virtual processors.
  • a virtual machine may also include other virtual hardware resources such as virtual memory, but they are not shown in FIG1 . It should be understood that a virtual machine is equivalent to an independent computer, so the execution of an action by a virtual machine may also be considered as the execution of the action by a virtual processor.
  • a virtual processor is virtualized by virtualization software, and its operation is actually realized by the processor or physical core of the host machine reading and running a software program, for example, a physical core reads a software program and runs the software program in a specific mode of hardware-assisted virtualization of the physical core to realize a virtual processor.
  • Multiple virtual processors of a virtual machine may be located on different physical cores.
  • Virtual processor trap-in and VCPU trap-out The virtualization system includes two modes: host mode and guest mode.
  • Host mode can also be called the privilege level of the host, such as the user state of the host or the kernel state of the host.
  • Guest mode can also be called the privilege level of the virtual machine, such as the user state of the virtual machine or the kernel state of the virtual machine.
  • trap-in virtual
  • trap-out virtual
  • the physical processor will temporarily not execute the code of the virtual processor, so at this time it can be understood that the virtual processor is not running.
  • a physical processor For a physical processor, if the virtual processor running on it is trapped, it can be considered that the physical processor is in guest mode and runs the code of the virtual processor. When the virtual processor running on it traps out to host mode, it can be considered that the physical processor is in host mode and runs host-related code, such as the virtual machine monitor.
  • the host layer 102 is used as a management layer to complete the management and allocation of hardware resources, present a virtual hardware platform to the virtual machine, and realize the scheduling and isolation of the virtual machine.
  • the host layer 102 may include a host operating system and a virtual monitoring device, such as a virtual machine monitor 110 (virtual machine monitor, VMM).
  • the virtual machine monitor can be deployed within the host operating system or outside the host operating system.
  • the virtual monitoring device can also be called a hypervisor or other types of virtual monitoring devices.
  • the virtual hardware platform provides various hardware resources, such as virtual processors, virtual memory, virtual disks, virtual network cards, etc., to each virtual machine running on it.
  • the virtual machine runs on the virtual hardware platform prepared for it by the host layer.
  • the host layer 102 can also be called a virtualization platform or a host.
  • the privilege level of the host includes user state and kernel state.
  • Hardware layer 103 Hardware platform for virtualized environment operation.
  • the hardware layer may include a variety of hardware. As shown in FIG. 1 , the hardware layer may include a processor system 106 and a memory 107. It may also include a communication interface 108, such as a network interface card (NIC); it may also include an interrupt controller 109, input/output (I/O) devices, etc. In the embodiment of the present application, the input/output devices may be referred to as devices.
  • the processor system 106 may include one or more processors, such as the processor 110 and the processor 111 listed in FIG. 1 . Each processor may include multiple physical cores, and the processor may also include multiple registers, such as general registers, floating-point registers, etc.
  • Processor system 106 is sometimes referred to as a physical processor.
  • a physical core represents the smallest processing unit in a processor, and the number of cores contained in each processor may be the same or different.
  • a processor with one core is called a single-core processor, and a processor with multiple physical cores is called a multi-core processor.
  • the core architecture is the same, it can be divided into homogeneous multi-core and heterogeneous multi-core.
  • the virtual processor and the physical core may be in a binding relationship, that is, a virtual processor is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is a bound core; a virtual processor can be scheduled to run on different physical cores as needed, then the virtual processor is a non-bound core.
  • Interrupt controller 109 mainly used to collect interrupt requests generated by various devices, processors, and virtual machines, and send the interrupt requests to the processor so that the processor can process the interrupt requests.
  • the description of the interrupt controller 109 provided in the embodiment of the present application can be found in the following description, which will not be described in detail here.
  • Interruption refers to the instruction to suspend the current program and execute the interrupt service program instead.
  • Interrupt service routine A program used to handle interrupt requests.
  • An interrupt service routine can also be called an interrupt handling function.
  • the processor receives an interrupt request, it can pause the execution of the current program's instructions and instead execute the interrupt service routine corresponding to the interrupt request.
  • Interrupt request refers to an event generated by hardware (such as I/O devices, processors) or virtual machines.
  • hardware such as I/O devices, processors
  • virtual machines When the processor receives an interrupt request, it temporarily stops the execution of the current program and executes the program corresponding to the event instead.
  • the hardware may generate an interrupt request, which may be triggered by the hardware itself or by software. Interrupt requests are sometimes also called interrupts.
  • the computer device 100 may be a physical device, such as a server or an electronic device.
  • the electronic device may be a handheld device with a wireless connection function, or other processing device connected to a wireless modem.
  • it may be a mobile phone, a personal computer (PC), a tablet computer, a personal digital assistant (PDA), a mobile Internet device (MID), a wearable device, and an e-book reader, etc.; it may also be a portable, pocket-sized, handheld, computer-built-in, or vehicle-mounted mobile device.
  • IO virtualization in virtualization technology can provide virtual machines with the ability to reuse devices in computers.
  • the virtual machine can send IO requests, and the host machine drives the processor to poll and process the IO requests.
  • Figure 2 shows a schematic flow chart of a method for virtual IO processing. As shown in Figure 2, the method includes:
  • Virtual machines and devices can share data queues through the data plane development kit (DPDK).
  • DPDK data plane development kit
  • Virtual machines and devices can transfer IO data through shared data queues.
  • Each virtual machine and device can bind multiple data queues, that is, share multiple data queues.
  • DPDK can create N worker threads, N>0 and is an integer, bound to run on N reserved physical cores, and the worker threads poll and traverse the IO data on the data queue to obtain and process the IO data.
  • Each worker thread processes the data in the bound data queue.
  • S202 The virtual machine sends IO data to a data queue.
  • the virtual machine When the virtual machine needs to send IO data to the device, it can first send the IO data to the data queue shared with the device
  • the working thread polls the data queue to obtain IO data.
  • the worker thread can poll the data queue bound to it to obtain IO data.
  • the working thread sends IO data to the device.
  • the working thread can send the IO data to the device, thereby realizing the sending of IO data to the device from the perspective of the virtual machine.
  • the device can also send IO data to the data queue shared with the virtual machine. After the working thread polls the data queue to obtain the IO data, it can send the IO data to the virtual machine, so as to send IO data to the virtual machine from the perspective of the device.
  • an embodiment of the present application provides a data processing method that can reduce the tail delay of IO processing, and can distribute data according to the load of the working thread, ensuring the load balance of IO data.
  • the interrupt controller 109 provided in the embodiment of the present application will be described in detail below.
  • FIG. 3 shows a schematic structural diagram of the interrupt controller 109 provided in an embodiment of the present application.
  • the interrupt controller 109 includes an interrupt collection device 1091, an interrupt routing device 1092, an interrupt delivery device 1093, and an interrupt interaction device 1094, wherein the interrupt collection device 1091 is used to collect interrupt requests from devices, virtual machines and processors, the interrupt routing device 1092 is used to select a working thread as an interrupt request delivery target, the interrupt delivery device 1093 is used to deliver the interrupt request to the processor, and the interrupt interaction device 1094 is used to collect processor load information, pass the processor load request to the interrupt routing device 1093, and manage the life cycle of the interrupt request.
  • the interrupt collection device 1091 is used to collect interrupt requests from devices, virtual machines and processors
  • the interrupt routing device 1092 is used to select a working thread as an interrupt request delivery target
  • the interrupt delivery device 1093 is used to deliver the interrupt request to the processor
  • the interrupt interaction device 1094 is used to collect processor load information, pass the processor load request to the interrupt routing device 1093, and manage the
  • Figure 4 shows a schematic structural diagram of the interrupt collection device 1091 provided in an embodiment of the present application.
  • the interrupt collection device 1091 includes an interrupt-data queue mapping table register and a data queue identifier table register, wherein the interrupt-data queue mapping table register stores an interrupt-data queue mapping table address, the interrupt-data queue mapping table can be configured by the host machine, and the data queue identifier table register stores a data queue identifier table address.
  • the device may send an interrupt request message, which includes a device interrupt identifier, which is used to indicate the device requesting an interrupt.
  • the interrupt-data queue mapping table is used to indicate the interrupt request and the data queue. According to the mapping relationship of the queues, the interrupt-data queue mapping table entry may include a device interrupt identifier and a data queue identifier.
  • the interrupt collection device 1091 collects the interrupt request information, it may determine the data queue identifier corresponding to the interrupt request information based on the device interrupt identifier in the interrupt request information and the interrupt-data queue mapping table.
  • the virtual machine after the virtual machine sends IO data to the data queue, it can send an interrupt request information, which includes a virtual machine identifier and a virtual event interrupt identifier.
  • the virtual machine identifier is used for the virtual machine requesting the interrupt
  • the virtual event interrupt identifier is used to indicate the virtual event requesting the interrupt.
  • the interrupt-data queue mapping table is used to indicate the mapping relationship between the interrupt request and the data queue.
  • the interrupt-data queue mapping table entry can include a virtual event interrupt identifier, a virtual machine identifier, and a data queue identifier.
  • the interrupt collection device 1091 collects the interrupt request information, it can determine the data queue identifier corresponding to the interrupt request information according to the virtual event interrupt identifier and the virtual machine identifier in the interrupt request information and the interrupt-data queue mapping table.
  • the processor after the processor sends IO data to the data queue, it can send an interrupt request information, and the interrupt request information includes a processor interrupt identifier, and the device interrupt identifier is used to indicate the processor requesting the interrupt.
  • the interrupt-data queue mapping table is used to indicate the mapping relationship between the interrupt request and the data queue.
  • the interrupt-data queue mapping table entry can include a processor interrupt identifier and a data queue identifier.
  • the interrupt collection device 1091 collects the interrupt request information, it can determine the data queue identifier corresponding to the interrupt request information according to the processor interrupt identifier in the interrupt request information and the interrupt-data queue mapping table.
  • the data queue identifier table is used to indicate the state of the data queue, wherein the state of the data queue includes being processed and not being processed.
  • each bit in the data queue identifier table can be used to identify the state of a data queue
  • the position of each bit in the data queue identifier table can correspond to a data queue
  • the value of the bit can be used to indicate the state of the data queue.
  • bit value of 0 can indicate that the data queue is not processed
  • bit value of 1 can indicate that the data queue is being processed
  • the interrupt collection device 1091 After the interrupt collection device 1091 collects the interrupt request information, it can determine the data queue identifier corresponding to the interrupt request information based on the interrupt request information, and determine whether the data queue is being processed based on the data identification identifier table. If the data queue is not being processed, the interrupt collection device 1091 can send the data queue identifier to the interrupt routing device 1092, and set the bit value corresponding to the data queue identifier from 0 to 1.
  • the interruption routing device 1092 can determine the delivery target of the interruption request.
  • the interruption routing device 1092 will be described in detail below.
  • the interrupt routing device 1092 may include a ring queue and a decision device, and the decision device is used to determine a routing distribution strategy.
  • the ring queue includes size register #1, size register #2, base register #1, base register #2, head register #1, head register #2, tail register #1, tail register #2, wherein size register #1 is used to store the number of entries in the pending data queue, size register #2 is used to store the number of entries in the load request queue, base register #1 is used to store the address of the pending data queue, base register #2 is used to store the address of the load request queue, head register #1 is used to store the head index of the pending data queue, head register #2 is used to store the head index of the load request queue, tail register #1 is used to store the tail index of the pending data queue, and tail register #2 is used to store the tail index of the load request queue.
  • the pending data queue is used to store the data queue identifier received from the interrupt collection device 1091, and the load request queue is used to store the processor identifier of the requesting load.
  • the value of head register #1 can be increased by 1.
  • the value of head register #1 increases to 0x10000, it means that the queue of data to be processed contains 16 entries, that is, the queue of data to be processed is full. At this time, the value of tail register #1 is 0x00000.
  • the values of head register #1 and tail register #1 can be reset to 0.
  • the description of size register #2, base register #2, head register #2, and tail register #2 can refer to the description of size register #1, base register #1, head register #1, and tail register #1.
  • the embodiment of the present application does not limit the storage location of the queue of data to be processed and the load request queue.
  • the queue of data to be processed and the load request queue can be stored in an interrupt routing device.
  • interrupt routing device 1092 perform routing distribution according to the queue of data to be processed and the queue of load request.
  • the interrupt routing device 1092 may perform routing distribution according to the order of the data queue identifiers entering the queue for data to be processed and the processor identifiers entering the load request queue.
  • the interrupt routing device 1092 may select a data queue identifier with the longest addition time from the to-be-processed data queue, select a processor identifier with the longest addition time from the load request queue, and then send the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the interrupt routing device 1092 may perform routing distribution based on the principle of "first in, first out".
  • the interrupt routing device 1092 may perform routing distribution according to priority.
  • the priority of a data queue can be defined, and the interrupt routing device 1092 selects a data queue identifier of a data queue with the highest priority from the data queue to be processed, selects a processor identifier with the longest addition time from the load request queue, and then sends the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the priority of the processor can be defined, and the interrupt routing device 1092 selects the data queue identifier with the longest addition time from the data queue to be processed, selects the processor identifier corresponding to the processor with the highest priority from the load request queue, and then sends the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the priority of the data queue and the priority of the processor can be defined, and the interrupt routing device 1092 selects the data queue identifier with the longest addition time from the data queue to be processed, selects the processor identifier corresponding to the processor with the highest priority from the load request queue, and then sends the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the interrupt routing device 1092 may randomly select a data queue identifier in the to-be-processed data queue and a processor identifier in the load request queue, and then send the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the interrupt routing device 1092 may select a processor identifier according to the workload of the processor when selecting the processor identifier according to the load request queue.
  • the processor can send the workload to the interrupt routing device 1092, so that the interrupt routing device 1092 selects the data queue identifier with the longest addition time from the data queue to be processed, selects the processor identifier of the processor with a low workload from the load request queue, and then sends the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • the processor can send the workload to the interrupt routing device 1092, so that the interrupt routing device 1092 selects the data queue identifier of the data queue with the highest priority from the data queue to be processed, selects the processor identifier of the processor with a low workload from the load request queue, and then sends the data queue identifier to the interrupt delivery device 1093 corresponding to the processor identifier.
  • interrupt routing device 1092 performs routing distribution according to the pending data queue and the load request queue is only an example and should not be understood as a limitation on the present application.
  • the interrupt routing device 1092 selects the data queue identifier in the pending data queue and the processor identifier in the load request queue for routing distribution by other methods, which should also fall within the scope of protection of the present application.
  • the interrupt routing device 1092 may include an interrupt routing table register, the interrupt routing table register may point to an interrupt routing table, and the table entry of the interrupt routing table includes a data queue identifier and a processor identifier.
  • the interrupt routing table may be configured by the host machine so that each data queue identifier may correspond to a processor identifier.
  • the interruption collection device 101 After the interruption collection device 101 collects the interruption request information, it can determine the data queue identifier corresponding to the interruption request according to the interruption request information, and then send the data queue identifier to the interruption routing device 1092.
  • the interruption routing device 1092 detects the interruption routing table according to the data queue identifier to obtain the processor identifier.
  • the interrupt routing device 1092 After the interrupt routing device 1092 obtains the data queue identifier and the processor identifier, it can update the data queue identifier to the interrupt delivery device 1093 of the processor corresponding to the processor identifier.
  • the interrupt routing device 1092 may include an interrupt routing table register, the interrupt router register may point to an interrupt routing table, and the interrupt routing table entry may include a data queue identifier and a processor routing table address.
  • the processor routing table address may point to a processor routing table, the header of which may include a processor index and a processor routing table size, and the entry may include a processor identifier.
  • the interruption collection device 1091 After the interruption collection device 1091 collects the interruption request information, it can determine the data queue identifier corresponding to the interruption request information according to the interruption request information, and then send the data queue identifier to the interruption routing device 1092.
  • the interruption routing device 1092 retrieves the interruption routing table according to the data queue identifier, and can determine the processor routing table address corresponding to the data queue identifier.
  • the interruption routing device 1092 obtains the processor index and the processor routing table size from the header of the processor routing table according to the processor routing table address.
  • the interruption routing device 1092 then retrieves the processor routing table entry according to the processor index to obtain the processor identifier.
  • the interruption routing device 1092 can update the data queue identifier to the interruption delivery device 1093 of the processor corresponding to the processor identifier.
  • the interrupt routing device 1092 may also update the processor index after updating the data queue identifier to the interrupt delivery device 1093.
  • y is the updated processor index
  • x is the original processor index
  • m is the size of the processor routing table.
  • the interrupt routing device 1092 sends the data queue identifier to the interrupt delivery device 1093.
  • Each processor may correspond to an interrupt delivery device 1093, and the interrupt delivery device 1093 may send the data queue identifier to the processor.
  • the interrupt delivery device 1093 may store the data queue identifier of the data queue to be processed and the data queue identifier of the data queue being processed.
  • the interrupt routing device includes a ring queue, a decision device and a routing table address register, wherein the description of the ring queue and the decision device can be found above and will not be repeated here for the sake of brevity.
  • the load request queue in the interrupt routing device shown in (d) of FIG. 5 stores a working thread identifier instead of a processor identifier.
  • the routing table address register can point to the working thread routing table, and the working thread routing table entry includes a working thread identifier and a processor identifier.
  • the working thread routing table can be configured and updated by the host machine.
  • the corresponding interrupt delivery device 1093 can include a thread identifier register, which stores the working thread identifier. For details, please refer to the description of (c) in Figure 6 below.
  • the interrupt routing device 1092 can determine the data queue identifier and the work thread identifier based on the pending data queue and the load request queue, and then index the work thread routing table according to the work thread identifier to obtain the processor identifier, and then update the data queue identifier to the interrupt delivery device 1093 of the processor corresponding to the processor identifier.
  • the description of the interrupt routing device determining the data queue identifier and the work thread identifier based on the pending data queue and the load request queue is similar to the description of the interrupt routing device determining the data queue identifier and the processor identifier based on the pending data queue and the load request queue. For the sake of brevity, it will not be repeated here.
  • Figure 6 shows a schematic structural diagram of the interrupt delivery device 1093.
  • the interrupt delivery device 1093 includes a pending register and a processing register, wherein the pending register is used to store a data queue identifier waiting to be processed by the processor, and the processing register is used to store a data queue identifier being processed by the processor.
  • the interrupt delivery device 1093 further includes an interrupt type register, which is used to store the interrupt type, wherein the interrupt type includes a kernel mode interrupt and a user mode interrupt.
  • the embodiment of the present application does not limit the manner in which the interrupt delivery device 1093 stores the data queue identifier.
  • the interrupt delivery device 1093 may use a register to store the data queue identifier and the interrupt type.
  • the interrupt delivery device 1093 may also use a memory to store the data queue identifier and the interrupt type.
  • the interrupt delivery device 1093 when the interrupt routing device 1092 sends a data queue identifier to the interrupt delivery device 1093, the data queue identifier can be updated to the pending register of the interrupt delivery device 1093.
  • the interrupt delivery device 1093 can send an interrupt request to the processor.
  • the interrupt delivery device 1093 can obtain the data queue identifier from the pending register, update the data queue identifier to the processing register, and send the data queue identifier to the processor.
  • the interrupt delivery device 1093 may send an interrupt request to the processor according to the interrupt type in the interrupt type register.
  • FIG6(b) shows a schematic structural diagram of another interrupt delivery device 1093.
  • the interrupt delivery device 1093 no longer stores the identifier of the data queue to be processed, that is, the interrupt delivery device no longer includes the pending register, but adds a size register, a base register, a head register, and a tail register to store the entry data, address, head index, and tail index of the processor's pending data queue, respectively, wherein the processor's pending data queue can be stored in a device other than the interrupt delivery device, such as the memory of a computer device.
  • processor's pending data queue is not the same as the pending data queue routed and distributed by the interrupt routing device 1092.
  • the processor's pending data queue stores the data queue identifier that has been routed and distributed to the processor, and the pending data queue stores the pending data queue collected by the interrupt collection device 1091.
  • the interrupt delivery device 1093 shown in (b) of FIG. 6 when the interrupt routing device 1092 sends a data queue identifier to the interrupt delivery device 1093, the data queue identifier can be loaded into the processor to-be-processed data queue, so that the interrupt delivery device 1093 can update
  • the interrupt delivery device 1093 can send an interrupt request to the processor when the processor's pending data queue is not empty, and obtain a data queue identifier from the processor's pending data queue, update the data queue identifier to the processing register, and send the data queue identifier to the processor.
  • the interrupt delivery device 1093 includes a pending register, a processing register, an interrupt type register and a thread identifier register.
  • the description of the pending register, the processing register and the interrupt type register can be found above and will not be repeated here for the sake of brevity.
  • Each processor may correspond to an interrupt delivery device 1093, and the thread identifier register may store the identifier of the working thread running on the processor.
  • the processor accesses the load request interface of the interrupt interaction device 1094 through the working thread, it may instruct the interrupt delivery device 1093 to add the working thread identifier in the thread identifier register to the load request queue.
  • the interruption collection device 1091, the interruption routing device 1092 and the interruption delivery device 1093 are introduced above, and the interruption interaction device 1094 will be introduced below.
  • the interrupt interaction device 1094 can obtain the workload of the processor, and the processor can request the load from the interrupt routing device 1092 through the interrupt interaction device 1094.
  • the interrupt interaction device 1094 can also manage the interrupt life cycle.
  • Each processor can correspond to an interrupt interaction device 1094.
  • the interrupt interaction device 1094 can include multiple interfaces for implementing the above functions.
  • FIG7 shows a schematic structural diagram of an interrupt interaction device 1094.
  • the interrupt interaction device 1094 includes a load request interface, an interrupt processing interface, and an interrupt end interface, wherein the working thread in the processor can add the processor identifier or the working thread identifier to the load request queue through the load request interface; the working thread in the processor can obtain the data queue identifier being processed from the interrupt delivery device 1093 through the interrupt processing interface; the working thread in the processor can reset the bit of the data queue corresponding to the data queue identifier table in the interrupt collection device 1091 to 0 through the interrupt end interface after completing the data queue processing.
  • the interrupt interaction device 1094 may also include an interrupt reverse filling interface.
  • the processor processes an IO request through a working thread, it will only process a fixed number of IO data in the data queue. If there is still IO data in the data queue that has not been processed in this processing, the processor can call the interrupt reverse filling interface in the interrupt interaction device 1094 through the working thread, so that the data queue identifier is re-added to the queue of data to be processed in the interrupt routing device 1092 and the bit position corresponding to the data queue in the data queue identifier table in the interrupt collection device 1091 is 1, thereby ensuring that the remaining IO data in the data queue can also be quickly processed.
  • the interrupt routing device 1092 is the structure shown in (d) in Figure 5
  • the interrupt delivery device is the structure shown in (c) in Figure 6
  • the interrupt delivery device 1093 corresponding to the processor can obtain the working thread identifier from the thread identifier register, and then add the working thread identifier to the load request queue.
  • the interrupt routing device 1092 is the structure shown in (d) in Figure 5
  • the interrupt delivery device is the structure shown in (c) in Figure 6
  • the interrupt interaction device 1094 corresponding to the processor can communicate with the interrupt delivery device 1093 to obtain the working thread identifier from the thread identifier register, and then add the working thread identifier to the load request queue.
  • each processor may correspond to an interrupt delivery device and an interrupt interaction device.
  • the interrupt delivery device and the interrupt interaction device may be integrated into the same device. In other embodiments, the interrupt delivery device and the interrupt interaction device may be two separate devices.
  • the above describes the interrupt controller 109 provided in the embodiment of the present application.
  • the following describes the data flow when the interrupt controller 109 processes an interrupt request in conjunction with FIG. 8 .
  • FIG8 is a schematic diagram showing the data flow of an interrupt controller provided in an embodiment of the present application.
  • the interrupt collection device 1091 can collect interrupt request messages from processors, devices, and virtual machines, and determine the data queue identifier based on the interrupt request information. For specific instructions, please refer to the description of the interrupt collection device 1091 above. After the interrupt collection device 1091 determines the data queue identifier, it can determine whether the data queue corresponding to the data queue identifier is being processed. If the data queue corresponding to the data queue identifier is not being processed, the interrupt collection device 1091 can pass the data queue identifier to the data queue to be processed of the interrupt routing device 1092, and set the identification position corresponding to the data queue identifier to 1.
  • the processor may send a load request message to the interrupt interaction device 1094, where the load request message is used to request the interrupt router 1092 to route and distribute the data queue identifier, and the load request message may include a processor identifier.
  • the interrupt routing device 1092 may add the processor identifier in the load request message to the load request queue.
  • the interrupt routing device 1092 may determine a data queue identifier from the to-be-processed data queue, determine a processor identifier from the load request queue, and add the data queue identifier to the processor identifier.
  • the interrupt delivery device 1093 may send an interrupt request to the processor according to the interrupt type stored in the interrupt type register. For example, if the interrupt type stored in the interrupt type register is a user-mode interrupt, the interrupt delivery device 1093 may send a user-mode interrupt to the processor.
  • the processor After the processor receives the interrupt request, it can send the interrupt processing request through the interrupt processing interface of the interrupt interaction device 1094. After the interrupt delivery device 1093 receives the interrupt processing request, it can update the data queue identifier in the pending register to the processing register and send the data queue identifier to the processor so that the processor can process the data queue according to the data queue identifier.
  • the processor since the amount of data processed by the processor is certain when the processor processes the data queue, there may be IO data in the processed data queue that has not been processed.
  • the processor detects whether there is still IO data in the data queue. If there is still IO data, the processor can send a counter-completion request to the interrupt delivery device 1093 through the interrupt counter-completion interface of the interrupt interaction device 1094.
  • the interrupt delivery device 1093 can re-add the data queue identifier of the data queue being processed in the register to the queue of data to be processed of the interrupt routing device 1092 and set the identification position corresponding to the data queue identifier in the interrupt collection device 1091 to 1, so that the data queue can be processed again.
  • the processor can send an interruption end request through the interruption end interface of the interruption interaction device 1094.
  • the interruption collection device 1091 can reset the identification bit corresponding to the data queue identifier of the processed data queue to 0 to indicate that the data queue is not being processed.
  • FIG9 shows a work thread scheduling framework diagram
  • FIG10 shows a framework diagram of the work thread when it is running.
  • the processor corresponding to the data plane can bind M work threads, where M>0 and is an integer, and the M work threads can access the data queue shared by the device and the virtual machine.
  • the processor can schedule the M work threads to process the data queue through the thread scheduling management module.
  • the processor corresponding to the data plane can be bound to M working threads, which can be understood as the physical core of the processor is bound to M working threads.
  • the processor can be a single-core processor or a multi-core processor. If the processor is a multi-core processor, one physical core in the processor can be bound to the M working threads.
  • FIG9 shows another work thread scheduling framework diagram.
  • the processor corresponding to the data plane can bind not only M work threads but also 1 idle work thread.
  • the M work threads and the idle work thread can access the data queue shared by the device and the virtual machine, wherein the M work threads can be used to process the data queue, process services other than the data queue, and execute an idle loop, and the idle work thread can execute an idle loop and process the data queue.
  • the processor can schedule the above threads to process various services through the thread scheduling management module.
  • the processor corresponding to the data plane can be bound to M working threads and 1 idle working thread, which can be understood as the physical core of the processor is bound to M working threads and 1 idle working thread.
  • the processor can be a single-core processor or a multi-core processor. If the processor is a multi-core processor, one physical core in the processor can be bound to the M working threads and 1 working thread.
  • the M working threads and the idle working thread can register user state interrupts, so that the user state interrupts can be directly responded to in the user state.
  • the processor can be made to run in the user state through the idle working thread, and when the processor receives the user state interrupt, the interrupt request can be directly processed.
  • the interrupt routing device 1092 in the interrupt controller 109 can take out the data queue identifier from the to-be-processed data queue, take out the processor identifier from the load request queue, load the data queue identifier into the to-be-processed register of the interrupt delivery device of the processor corresponding to the processor identifier, and send an interrupt notification to the processor.
  • the processor receives an interrupt request, the processor can interrupt the work thread #1 to process the business #1 and schedule the work thread #1 to process the data queue, and the interrupt context management module can switch the running environment of the work thread #1 to the interrupt context.
  • the work thread #1 may be in an idling state, and the processor can also schedule the work thread #1 to process the data queue.
  • the work thread #1 can be any one of the M work threads.
  • the processor can switch the privilege level according to the type of the interrupt request.
  • the processor may process the interrupt request after adjusting from kernel mode to user mode.
  • the processor may process the interrupt request after adjusting from the user-mode to the kernel-mode.
  • the processor may directly process the interrupt request.
  • the processor may directly process the interrupt request.
  • the interrupt routing device 1092 in the interrupt controller 109 can take out the data queue identifier from the pending data queue, take out the processor identifier from the load request queue, load the data queue identifier into the pending register of the interrupt delivery device of the processor corresponding to the processor identifier, and send a user-mode interrupt notification to the processor.
  • the processor receives a user-mode interrupt request
  • the processor can interrupt the work thread #1 to process the business #1 and schedule the work thread #1 to process the data queue
  • the interrupt context management module can switch the operating environment of the work thread #1 to the user-mode interrupt context.
  • the work thread #1 may be in an idling state, and the processor may also schedule the work thread #1 to process the data queue.
  • the work thread #1 can be any one of the M work threads, or it can be an idling work thread.
  • service #1 may be a non-delay-sensitive service.
  • the worker thread is processing service #1 and is interrupted by a user-mode interrupt, the service demand of service #1 will not be affected.
  • the priority of the idle working thread is lower than the priority of the M working threads, and when the processor needs to process the data queue, the M working threads can be scheduled first.
  • the processor can schedule the idle working thread through the thread scheduling module, so that the processor bound to the idle working thread runs in the user state, ensuring that the processor can directly process the user state interrupt request when receiving the user state interrupt request.
  • a flag bit is provided in the processor for indicating the processing of a user-state interrupt, and the flag bit is used to indicate that the processor is processing a user-state interrupt, and the flag bit may be referred to as a flag bit in the user-state interrupt processing.
  • the embodiment of the present application does not limit the storage method of the flag bit in the user-state interrupt processing, for example, a register may be added to store the flag bit in the user-state interrupt processing, or a free domain in an existing register may be reused to store the flag bit in the user-state interrupt processing.
  • the flag bit in the user-state interrupt processing may be set to 1.
  • the kernel is making a scheduling decision, it may determine whether the processor is processing a user-state interrupt based on the flag bit in the user-state interrupt processing. If the processor is processing a user-state interrupt, kernel scheduling may be prohibited.
  • FIG. 11 shows a schematic diagram of another data plane processing model provided in an embodiment of the present application.
  • the processor corresponding to the data plane can be bound to one working thread, and the working thread can poll the processor's user-mode interrupt pending flag, and the user-mode interrupt pending flag can indicate whether the processor has a pending user-mode interrupt.
  • the user-mode interrupt pending flag is 0, it indicates that the processor has no pending user-mode interrupt, and if the user-mode interrupt pending flag is 1, it indicates that the processor has a pending user-mode interrupt.
  • the processor also includes a user-mode interrupt enable flag, which can indicate whether the processor can handle user-mode interrupts.
  • a user-mode interrupt enable flag can indicate whether the processor can handle user-mode interrupts.
  • the processor prohibits user-mode interrupts when running; when the user-mode interrupt enable flag is 1, the processor can respond to user-mode interrupts when running.
  • the interrupt routing device 1092 may add the data queue identifier to the pending register of the interrupt delivery device 1093 corresponding to the processor.
  • the interrupt delivery device 1093 may send a user-mode interrupt to the processor. After receiving the user-mode interrupt, the processor may set the user-mode interrupt pending flag from 0 to 1 and the user-mode interrupt enable flag from 0 to 1.
  • the processor can also switch the working thread to the interrupt processing function entry to process the user-mode interrupt.
  • the processor polls the user-mode interrupt pending flag through the working thread.
  • the processor can obtain the data queue identifier in the interrupt delivery device 1093 through the interrupt interaction device 1094 and process the data queue corresponding to the data queue identifier.
  • the flag corresponding to the data queue identifier in the data queue identifier in the interrupt collection device 1091 can be reset to 0 through the interrupt interaction device 1094.
  • the processor can also detect whether there is still data in the data queue. If there is still data in the data queue, the processor can also send a reverse replenishment request to the interrupt delivery device 1093 through the interrupt reverse replenishment interface of the interrupt interaction device 1094. After receiving the reverse replenishment request, the interrupt delivery device 1093 can re-add the data queue identifier of the data queue in the register being processed to the queue of data to be processed in the interrupt routing device 1092 and set the identification position corresponding to the data queue identifier in the interrupt collection device 1091 to 1, so that the data queue can be processed again.
  • FIG. 12 shows a schematic diagram of another data plane processing model provided in an embodiment of the present application.
  • the interrupt delivery device 1093 also includes a blocking flag register, and the processor corresponding to the data plane can not only bind the working thread, but also bind other threads for processing different businesses, hereinafter referred to as other threads or business threads.
  • the priority of the worker thread is higher than that of other threads.
  • the processor can prioritize the data queue.
  • the processor includes a user-mode interrupt pending flag.
  • the processor includes a user mode interrupt enable flag.
  • the interrupt routing device 1092 may add the data queue identifier to the pending register of the interrupt delivery device 1093 corresponding to the processor.
  • the interrupt delivery device 1093 may send a user-mode interrupt to the processor.
  • the interrupt delivery device 1093 may send a user-mode interrupt to the processor.
  • the processor may set the user-mode interrupt pending flag from 0 to 1 and the user-mode interrupt enable flag from 0 to 1.
  • the working thread can always process the data queue, that is, the processor can process the data queue without transferring the working thread to the interrupt processing function entry.
  • the processor can poll the user state interrupt pending flag through the working thread. When it is determined that the user state interrupt pending flag is 1, the processor can obtain the data queue identifier in the interrupt delivery device 1093 through the interrupt interaction device 1094 and process the data queue corresponding to the data queue identifier.
  • the flag corresponding to the data queue identifier in the data queue identifier in the interrupt collection device 1091 can be reset to 0 through the interrupt interaction device 1094.
  • the processor can also detect whether there is still data in the data queue. If there is still data in the data queue, the processor can also send a reverse replenishment request to the interrupt delivery device 1093 through the interrupt reverse replenishment interface of the interrupt interaction device 1094. After receiving the reverse replenishment request, the interrupt delivery device 1093 can re-add the data queue identifier of the data queue being processed and stored to the queue of data to be processed by the interrupt routing device 1092 and set the identification position corresponding to the data queue identifier in the interrupt collection device 1091 to 1, so that the data queue can be processed again.
  • the processor can set the blocking flag of the interrupt delivery device 1093 to 1 through the working thread, and put the working thread into a dormant state. After the working thread enters the dormant state, the processor can process other services through other threads.
  • the interrupt delivery device 1093 sends a user-mode interrupt to the processor again, if the blocking flag is 1, the interrupt delivery device 1093 can send a doorbell interrupt to the processor. After the processor receives the doorbell interrupt, it can wake up the working thread and reset the blocking flag to 0. Since the priority of the working thread is higher than that of other threads, the processor can process the data queue first.
  • the user-state interrupt pending flag and the user-state interrupt enable flag are set in the processor, and the processor can manage the user-state interrupt pending flag and the user-state interrupt enable flag, but the embodiments of the present application are not limited to this. In other embodiments of the present application, the user-state interrupt pending flag and the user-state interrupt enable flag can also be set in the interrupt controller or other devices.
  • the above introduces the hardware and software models of the data processing method provided in the embodiment of the present application.
  • the following will introduce the data processing method provided in the embodiment of the present application.
  • the data processing method provided in the embodiment of the present application can be used for data plane processing.
  • FIG13 shows a schematic flow chart of a data processing method provided by an embodiment of the present application.
  • the method is applied to a computer device, which includes an interrupt controller, a first processor, and a first memory for storing a data queue identifier.
  • the data queue corresponding to the data queue identifier stored in the first memory is a data queue to be processed.
  • the data queue to be processed can be understood as a data queue in which data exists.
  • the first processor runs a first working thread, and the first working thread is used to process the data queue.
  • the method includes:
  • the interrupt controller obtains first interrupt request information.
  • the interrupt controller may obtain first interrupt request information through the interrupt collection device, where the first interrupt request information indicates a first data queue identifier.
  • the interrupt controller After the interrupt controller obtains the first interrupt request information, since an interrupt-data queue mapping table is stored in the interrupt collection device of the interrupt controller, and the interrupt-data queue mapping table can be configured by the host machine, and the interrupt-data queue mapping table includes the correspondence between the interrupt request information and the data queue identifier, the interrupt controller can determine the first data queue identifier corresponding to the first interrupt request information based on the first interrupt request information.
  • the first interrupt request information is sent by a device, and the first interrupt request information includes a device interrupt identifier.
  • the interrupt controller can determine the first data queue identifier according to the device interrupt identifier.
  • the first interrupt request information is sent by a virtual machine, and the first interrupt request information includes a virtual machine identifier and a virtual event interrupt identifier.
  • the interrupt controller can determine the first data queue identifier according to the virtual machine identifier and the virtual event interrupt identifier.
  • the first interrupt request is sent by a processor, and the first interrupt request information includes a processor identifier, an interrupt control
  • the processor may determine the first data queue identifier based on the processor identifier.
  • the interrupt controller sends a first interrupt notification to the first processor.
  • the first processor receives the first interrupt notification sent by the interrupt controller.
  • the interrupt controller can send a first interrupt notification to the first processor and add a first data queue identifier to a first memory, which can be a pending register of an interrupt delivery device corresponding to the first processor, as shown in (a) in Figure 6, or the first memory can be a memory of a computer device, as shown in (b) in Figure 6.
  • a first memory which can be a pending register of an interrupt delivery device corresponding to the first processor, as shown in (a) in Figure 6, or the first memory can be a memory of a computer device, as shown in (b) in Figure 6.
  • the interrupt controller may send the first interrupt notification to the first processor in the following ways.
  • the interrupt controller determines the first data queue identifier according to the first interrupt request information
  • the first data queue identifier is added to the queue of data to be processed.
  • the first processor accesses the load request interface of the corresponding interrupt interaction device through the first working thread to send the first load request information, and the first load request information is used to request the data queue identifier.
  • the interrupt controller adds the first processor identifier or the first working thread identifier to the load request queue according to the first load request information, wherein the first processor identifier is used to indicate the first processor, and the first working thread identifier is used to indicate the first working thread.
  • the first processor can access the load request interface of its corresponding interrupt interaction device through the working thread to send first load request information, where the first load request information includes a first processor identifier, and the interrupt interaction device adds the first processor identifier to a load request queue.
  • the first processor can access the load request interface of its corresponding interrupt interaction device through the working thread to send the first load request information, and the interrupt interaction device can instruct the interrupt delivery device corresponding to the first processor to add the first working thread identifier in the thread identifier register to the load request queue.
  • the first working thread identifier is used to indicate the first working thread running on the first processor.
  • the interrupt controller can determine the first processor identifier and the first data queue identifier according to the load request queue and the queue of data to be processed. After the interrupt controller determines the first processor identifier, that is, determines to deliver the first data queue identifier to the first processor, the interrupt controller can send a first interrupt notification to the first processor and add the first data queue identifier to the first memory.
  • the interrupt controller determines the processor identifier and the data queue identifier based on the load request queue and the pending data queue, and then sends an interrupt notification to the processor and adds the data queue identifier to the pending register or to the processor pending queue stored in the computer memory.
  • the interrupt controller includes a work thread routing table, which indicates the correspondence between the work thread and the processor identifier, and the interrupt controller adds the first work thread identifier to the load request queue according to the first load request information.
  • the interrupt controller can determine the first processor identifier corresponding to the first work thread identifier according to the first work thread identifier and the interrupt routing table.
  • the interrupt controller determines the first data queue identifier according to the queue of data to be processed, and sends a first interrupt notification to the first processor according to the first processor identifier and adds the first data queue identifier to the first memory.
  • the interrupt controller determines the working thread identifier and the data queue identifier based on the load request queue and the pending data queue, and then determines the processor identifier based on the working thread identifier and the working thread routing table, and then sends an interrupt notification to the processor based on the processor identifier, and adds the data queue identifier to the pending register, or adds it to the processor pending queue stored in the computer memory.
  • the interrupt controller includes an interrupt routing table, the interrupt routing table is used to indicate the correspondence between the data queue identifier and the processor identifier, the interrupt controller determines the first processor identifier according to the interrupt routing table and the first data queue identifier, the first processor identifier is used to indicate the first processor, and the interrupt controller sends a first interrupt notification to the first processor according to the first processor identifier and adds the first data queue identifier to the first memory.
  • the interrupt controller determines the processor identifier based on the data queue identifier and the interrupt routing table, then sends an interrupt notification to the processor based on the processor identifier, and adds the data queue identifier to a pending register, or to a processor pending queue stored in the computer memory.
  • the interrupt controller includes an interrupt routing table, the interrupt routing table is used to indicate the correspondence between the data queue identifier and the processor routing table address, the processing routing table address is used to point to the processor routing table, the interrupt controller determines the first processor routing table address according to the interrupt routing table and the first data queue identifier; the interrupt controller determines the first processor index and the first processor routing table size according to the first processor routing table address; the interrupt controller determines the first processor identifier according to the first processor index and the first processor routing table size; the interrupt controller sends a first interrupt notification to the first processor according to the first processor identifier and adds the first data queue identifier to the first memory.
  • the interrupt controller determines the processor routing table address based on the data queue identifier and the interrupt routing table, and then A processor index and a routing table size are determined according to the processor routing table address, and a processor identifier is determined according to the processor index and the routing table size, and then an interrupt notification is sent to the processor according to the processor identifier, and a data queue identifier is added to a pending register or to a processor pending queue stored in a computer memory.
  • the first processor sends a first interrupt processing request to the interrupt controller.
  • the interrupt controller receives the interrupt processing request sent by the first processor.
  • the first working thread running on the first processor may respond to the first interrupt notification and access the interrupt processing interface of the first interrupt interaction device through the working thread to send a first interrupt processing request.
  • S1304 The interrupt controller sends a first data queue identifier to the first processor.
  • the first processor receives the first data queue identifier sent by the interrupt controller.
  • the first interrupt delivery device in the interrupt controller can send the first data queue identifier to the first processor according to the interrupt processing request, and move the first data queue identifier out of the first storage device after sending the first data queue identifier.
  • S1305 The first processor processes the data in the first data queue.
  • the working thread may process the data in the first data queue, where the first data queue is a data queue corresponding to the first data queue identifier.
  • the method further comprises:
  • the first processor sends a first counter-fill request to the interrupt controller.
  • the interrupt controller receives the first counter-completion request sent by the first processor.
  • the first processor When the first processor processes the data in the data queue, the amount of data processed is certain. If it is detected that there is still unprocessed data in the first data queue, the first processor can send a first counter-reply request to the interrupt controller through the working thread to instruct the interrupt controller to resend the interrupt notification for processing the first data queue.
  • the structure of the interrupt routing device is as shown in (a) and (d) in Figure 5, after the interrupt controller receives the counter-reply request sent by the first processor, it can obtain the first data queue identifier from the processing register in the first interrupt delivery device, and then re-add the first data queue identifier to the queue of data to be processed, and then route and distribute the first data queue identifier.
  • the interrupt routing device routes and distributes the first data queue identifier again, it can be sent to the first processor or to other routers.
  • the first working thread is registered with a user-mode interrupt, and the first interrupt notification is a user-mode interrupt, then the first working thread can directly respond to the first interrupt notification.
  • the first processor runs multiple working threads and idle working threads, the multiple working threads include a first working thread, when the multiple working threads do not process the ear data in the data queue, the first processor can idle loop and idle working display to put the first processor in user state.
  • the first processor is provided with a first user-state interrupt processing flag, and the first user-state interrupt processing flag is used to indicate whether the first processor is processing a user-state interrupt.
  • the first user-state interrupt processing flag is set to indicate that a user-state interrupt is being processed.
  • FIG. 14 shows a schematic flow chart of the data processing method provided by the embodiment of the present application. As shown in FIG. 14, the method includes:
  • a working thread running on the first processor may respond to an interrupt, which may be a user-mode interrupt or a kernel-mode interrupt.
  • a working thread or an idle working thread running on the first processor may respond to an interrupt.
  • the working thread and the idle working thread can register the user state interrupt, and then can directly respond to the user state interrupt in the user state.
  • the idle working thread can execute an empty loop to make the first processor run in the user state, so that it can directly respond to the user state interrupt.
  • the first processor further includes a user-mode interrupt processing flag, which is used to indicate whether the first processor is processing a user-mode interrupt.
  • the first processor may set the user-mode interrupt processing flag to indicate that the first processor is processing the user-mode interrupt.
  • the data queue identifier can be obtained through the interrupt controller.
  • the working thread or the idle working thread After the working thread or the idle working thread responds to the interrupt and obtains the data queue identifier, it can also send a load request message to add the data queue identifier of the next data queue to be processed to the pending register of the first interrupt delivery device corresponding to the first processor, or add it to the processor pending queue.
  • the worker thread or the idle worker thread mobilizes the driver to process the data in the data queue.
  • the driver can be a DPDK driver, a storage performance development kit (SPDK) driver, etc.
  • the driver may be the DPDK driver or SPDK driver mentioned above, or other drivers for processing data in the data queue.
  • the working thread or the idle working thread may determine whether there is any unprocessed data in the first data queue. If there is any unprocessed data, S1407 is performed; if there is no unprocessed data, S1408 is performed.
  • the working thread or the idle working thread may send a counter-fill request to the interrupt controller when determining that there is still unprocessed data in the first data queue.
  • S1408 determine whether there is a data queue to be processed.
  • the working thread or the idle working thread can access the pending register in the first interrupt delivery device, or access the processor pending queue to determine whether there are data queues to be processed. If there are data queues to be processed, perform S1403; if there are no data queues to be processed, perform S1409.
  • the interrupt processing context may be switched to the context of the interrupted thread to continue executing the interrupted thread.
  • FIG15 shows a schematic flow chart of a method for data processing provided by an embodiment of the present application, the method being applied to a computer device, the computer device comprising an interrupt controller, a second processor and a second memory, the second memory being used to store a data queue identifier to be processed by the second processor, the second processor running a second working thread, the second working thread being used to process data in the data queue, the second processor being provided with a user-mode interrupt pending identification bit and a user-mode interrupt enable identification bit, the user-mode interrupt pending identification bit being used to indicate whether there is a user-mode interrupt to be processed by the second processor, the user-mode interrupt enable identification bit being used to indicate whether the second processor is allowed to process a user-mode interrupt, as shown in FIG15 , the method comprising:
  • S1501 The interrupt controller obtains second interrupt request information.
  • the second interrupt request is a user mode interrupt, and the second interrupt request information indicates a second data queue identifier.
  • the interrupt controller sends a second interrupt notification to the second processor.
  • the interrupt controller sends a second interrupt notification to the second processor and adds a second data queue identifier to the second memory.
  • the second processor sets a user-mode interrupt pending flag bit and a user-mode interrupt enable bit.
  • the second processor After the second processor receives the second interrupt notification sent by the interrupt controller, it can determine that the second interrupt request is a user state interrupt, and then set the user state interrupt pending flag bit to the first state and the user state interrupt enable flag bit to the first state to indicate that there is a user state interrupt to be processed and that the user state interrupt can be processed.
  • the value of the user-mode interrupt pending flag can be 0 when there is no user-mode interrupt. After the second processor receives the second interrupt notification, it can set the user-mode interrupt pending flag to 1 to indicate that there is a user-mode interrupt to be processed. Similarly, the initial state value of the user-mode interrupt enable flag is 0. After the second processor receives the second interrupt notification, it can set the user-mode interrupt enable flag to 1 to indicate that the user-mode interrupt can be processed.
  • S1504 The second processor sends a second interrupt processing request to the interrupt controller.
  • the interrupt controller receives the second interrupt processing request sent by the second processor.
  • the second processor determines that there is a user-mode interrupt to be processed, and can access the interrupt processing interface of the interrupt interaction device through the working thread to send a second interrupt processing request.
  • the second processor configures the second working thread so that the second working thread polls the user state interrupt pending flag When the user-mode interrupt pending flag is in the first state and the user-mode interrupt enable flag is in the first state, a second interrupt processing request is sent.
  • S1505 The interrupt controller sends a second data queue identifier to the second processor.
  • the second processor receives the second data queue identifier sent by the interrupt controller.
  • the interrupt delivery device in the interrupt controller may send the second data queue identifier to the second processor and move the second data queue identifier out of the second memory.
  • S1506 The second processor processes the data in the second data queue.
  • the second processor may process the data in the second data queue, where the second data queue is the data queue corresponding to the second data queue identifier.
  • the method further comprises:
  • the first processor sends a second counter-completion request to the interrupt controller.
  • the second processor is provided with an identification bit in the second user-state interrupt processing.
  • the description of the identification bit in the second user-state interrupt processing can refer to the description of the identification bit in the first user-state interrupt processor, and for the sake of brevity, it is not repeated here.
  • the second processor further runs a service thread, which is used to process services other than the data queue, the priority of the work thread is higher than the priority of the service thread, and a blocking flag is further provided on the computer device, which is used to indicate the state of the second work thread.
  • the second processor determines that there is no data queue to be processed, it adjusts the state of the working thread to a dormant state so that the service thread processes services other than processing the data queue, and sets the blocking flag through the working thread to indicate that the working thread is in a dormant state.
  • the computer device includes a hardware structure and/or software module corresponding to each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.
  • the embodiment of the present application also provides a computer device, including: one or more processors, one or more memories, an interrupt controller, and one or more computer programs.
  • the above-mentioned devices can be connected through one or more communication buses.
  • the one or more computer programs are stored in the above-mentioned memories and are configured to be executed by the one or more processors, and the one or more computer programs include instructions, and the above-mentioned instructions can be used to enable the data plane processing method described in any possible implementation method in the above text to be executed.
  • the processor may specifically be the processor 110 shown in FIG. 1
  • the memory may specifically be the internal memory 120 shown in FIG. 1 and/or an external memory connected to the electronic device.
  • An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is used to receive a signal and transmit the signal to the processor, and the processor processes the signal so that the data plane processing method described in any possible implementation method in the foregoing text is executed.
  • This embodiment also provides a computer-readable storage medium, in which computer instructions are stored.
  • the computer instructions When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the data plane processing method in the above-mentioned embodiment.
  • This embodiment further provides a computer program product.
  • the computer program product When the computer program product is run on a computer, the computer is enabled to execute the above-mentioned related steps to implement the data plane processing method in the above-mentioned embodiment.
  • the term “when" or “after" may be interpreted to mean “if" or “after" or “in response to determining" or “in response to detecting", depending on the context.
  • the phrase “upon determining" or “if (the stated condition or event) is detected” may be interpreted to mean “if determining" or “in response to determining" or “upon detecting (the stated condition or event)” or “in response to detecting (the stated condition or event)", depending on the context.
  • the disclosed systems, devices and methods can be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
  • Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art.
  • the computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

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Abstract

本申请提供了一种数据处理的方法，方法应用于计算机设备，计算机设备包括中断控制器、处理器以及存储器，存储器用于存储数据队列标识符，处理器运行有工作线程，工作线程用于处理数据队列的数据，中断控制器获取中断请求信息后，可以根据中断请求信息确定数据队列标识符，并且在处理器请求处理时，可以直接将数据队列标识符发送给处理器，无需处理器轮询所有数据队列，能够降低数据处理的尾延迟和系统整体峰值带宽。

Description

一种数据处理的方法以及计算机设备
本申请要求于2022年11月23日提交中国专利局、申请号为202211474450.5、申请名称为“一种数据处理的方法以及计算机设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，并且更具体地，涉及一种数据处理的方法以及计算机设备。
背景技术
IO虚拟化技术为虚拟机提供了复用物理设备的能力，目前工作线程需要轮询所有设备与虚拟机共享的数据队列以获取IO数据，但并不是所有共享的数据队列中均有需要处理的IO数据，当工作线程轮询的数据队列为空时，会增加处理IO数据的尾延迟，此外不同设备和虚拟机发送的IO请求的频率不同，以及IO请求的数据量和设备处理的时间也会不相同，从而导致绑定数据队列的工作线程存在负载不均衡的情况，降低了系统整体峰值带宽。
发明内容
本申请实施例提供一种数据处理的方法以及计算机设备，当存在中断时，中断控制器可以根据中断请求确定数据队列标识符并将数据队列标识符添加到存储器中，当处理器向中断控制器发送中断处理请求时，中断控制器可以直接从存储器得到数据队列标识符并发送给处理器，从而处理器无需轮询所有数据队列就可以进行处理，降低了处理IO数据的尾延迟和系统整体峰值带宽。
第一方面，提供了一种数据处理的方法，该方法应用于计算机设备，该计算机设备包括中断控制器、第一处理器以及存储器，该存储器用于存储数据队列标识符，该处理器用于处理数据队列的数据，该方法包括：该中断控制器获取第一中断请求信息，该第一中断请求信息用于指示第一数据队列标识符；该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中；该处理器根据该第一中断通知向该中断控制器发送第一中断处理请求；该中断控制器根据该第一中断处理请求向该处理器发送该第一数据队列标识符并将该第一数据队列标识符移出该存储器；该处理器处理该第一数据队列的数据，该第一数据队列为该第一数据队列标识符对应的数据队列。
本申请实施例中，当存在中断请求时，中断控制器可以根据中断请求确定数据队列标识符并将数据队列标识符添加到存储器中，当处理器向中断控制器发送中断处理请求时，中断控制器可以直接从存储器中得到数据队列标识符并将数据队列标识符发送给处理器，该数据队列标识符对应的数据队列中包括有待处理的数据，从而处理器无需轮询所有数据队列，能够降低处理IO数据的尾延迟和系统整体峰值带。
结合第一方面，在第一方面的某些实现方式中，该方法还包括：该处理器在检测到该第一数据队列存在未处理的数据时向该中断控制器发送第一反补请求以指示该中断控制器重新发送用于处理该第一数据队列的中断通知。
本申请实施例中，当数据队列中仍存在未处理的数据时，处理器可以通过反补请求重新请求中断处理器发送对应的中断通知，从而再次处理该数据队列。
结合第一方面，在第一方面的某些实现方式中，该计算机设备包括待处理数据队列，该待处理数据队列用于存储该第一数据队列标识符，在该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中之前，该方法还包括：该处理器向该中断控制器发送第一负载请求信息；该中断控制器根据该第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，其中，该处理器标识符用于指示该处理器，该第一工作线程标识符用于指示该第一工作线程，该第一工作线程运行于该处理器。
结合第一方面，在第一方面的某些实现方式中，该计算机设备包括待处理数据队列，该待处理数据队列用于存储数据队列标识符，在该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中之前，该方法还包括：该处理器向该中断控制器发送第一负载请求信息；该中断控 制器根据该第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，其中，该处理器标识符用于指示该处理器，该第一工作线程标识符用于指示该第一工作线程；该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中，包括：该中断控制器将该第一数据队列标识符添加到待处理数据队列；该中断控制器根据该负载请求队列和该待处理数据队列确定该处理器标识符和该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第一方面，在第一方面的某些实现方式中，该中断控制器包括工作线程路由表，该工作线程路由表用于指示工作线程和处理器标识符的对应关系，该中断控制器根据该第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，包括：该中断控制器根据该第一负载请求信息将该第一工作线程标识符添加到该负载请求队列；该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中，包括：该中断控制器根据该工作线程路由表和该第一工作线程标识符确定该处理器标识符；该中断控制器从该待处理数据队列得到该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第一方面，在第一方面的某些实现方式中，该中断控制器包括工作线程路由表，该工作线程路由表用于指示工作线程和处理器标识符的对应关系，该中断控制器根据该第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，包括：该中断控制器根据该第一负载请求信息将该第一工作线程标识符添加到该负载请求队列；该中断控制器根据该负载请求队列和该待处理数据队列确定该处理器标识符和该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中，包括：该中断控制器根据该工作线程路由表和该第一工作线程标识符确定该处理器标识符；该中断控制器根据该待处理数据队列确定该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第一方面，在第一方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器标识符的对应关系，该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中，包括：该中断控制器根据该中断路由表和该第一数据队列标识符确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第一方面，在第一方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，该处理路由表地址用于指向处理器路由表，该中断控制器向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中，包括：该中断控制器根据该中断路由表和该第一数据队列标识符确定第一处理器路由表地址；该中断控制器根据该第一处理器路由表地址确定第一处理器索引和第一处理器路由表大小；该中断控制器根据该第一处理器索引和该第一处理器路由表大小确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第一方面，在第一方面的某些实现方式中，该方法还包括：该第一工作线程注册有用户态中断，该第一中断通知为用户态中断。
结合第一方面，在第一方面的某些实现方式中，该处理器上运行多个工作线程和空转工作线程，该空转工作线程注册有用户态中断，该多个工作线程用于处理数据队列中的数据，该多个工作线程包括该第一工作线程，当该多个工作线程未处理数据队列中的数据时，该方法还包括：该处理器空循环该空转工作线程以使该处理器处于用户态。
结合第一方面，在第一方面的某些实现方式中，该处理器设置有第一用户态中断处理中标识位，该第一用户态中断处理中标识位用于指示该处理器是否正在处理用户态中断，该方法还包括：该处理器处理该第一数据队列的数据时，设置该第一用户态中断处理中标识位以指示正在处理用户态中断。
第二方面，提供了一种数据处理的方法，其特征在于，该方法应用于计算机设备，该计算机设备包括中断控制器、处理器以及存储器，该存储器用于存储数据队列标识符，该处理器运行有第二工作线程，该第二工作线程用于处理数据队列中的数据，该处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，该用户态中断待处理标识位用于指示该处理器是否存在待处理的用户态中断，该用户态中断使能标识位用于指示该处理器是否使能处理该用户态中断，该方法包括：该中断控制器获取第二中断请求信息；该中断控制器根据该第二中断请求信息确定第二数据队列标识符；该中断控制器向该处理器 发送第二中断通知并将该第二数据队列标识符添加到该存储器中，该第二中断通知为该用户态中断；该处理器根据该第二中断通知设置该用户态中断待处理标识位为该用户态中断待处理标识位的第一状态，该用户态中断待处理标识位的第一状态指示存在该用户态中断待处理，以及设置该用户态中断使能标识位为该用户态中断使能标识位的第一状态，该用户态中断使能标识位的第一状态指示该处理器使能处理该用户态中断；在存在用户态中断待处理的情况下，该处理器向该中断控制器发送第二中断处理请求；该中断控制器根据该第二中断处理请求向该处理器发送该第二数据队列标识符并将该第二数据队列标识符移出该存储器；该处理器处理该第二数据队列的数据，该第二数据队列为该第二数据队列标识符对应的数据队列。
本申请实施例中，当存在中断请求时，中断控制器可以根据中断请求确定数据队列标识符并将数据队列标识符添加到存储器中，且处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，在存在用户态中断时，处理器可以向中断控制器发送中断处理请求以获取数据队列标识符，中断控制器可以直接从存储器中得到数据队列标识符并将数据队列标识符发送给处理器，无需处理器轮询所有数据队列，降低了处理IO数据的尾延迟和系统整体峰值带宽。
结合第二方面，在第二方面的某些实现方式中，该方法还包括：该处理器在检测到第二数据队列存在未处理的数据时向该中断控制器发送第二反补请求以指示中断控制器重新发送用于处理第二数据队列的中断通知。
本申请实施例中，当数据队列中仍存在未处理的数据时，处理器可以通过反补请求重新请求中断处理器发送对应的中断通知，从而再次处理该数据队列。
结合第二方面，在第二方面的某些实现方式中，该计算机设备包括待处理数据队列，该待处理数据队列用于存储该第二数据队列标识符，在该中断控制器向该处理器发送第二中断通知并将该第二数据队列标识符添加到该存储器中之前，该方法还包括：该处理器向该中断控制器发送第二负载请求信息；该中断控制器根据该第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，其中，该处理器标识符用于指示该处理器，该第二工作线程标识符用于指示该第二工作线程。
结合第二方面，在第二方面的某些实现方式中，该中断控制器向该处理器发送第二中断通知并将该第二数据队列标识符添加到该存储器中，包括：该中断控制器将该第二数据队列标识符添加到待处理数据队列；该处理器向该中断控制器发送第二负载请求信息；该中断控制器根据该第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，其中该处理器标识符用于指示该处理器，该第二工作线程标识符用于指示该第二工作线程；该中断控制器根据该负载请求队列和该待处理数据队列确定该第二处理标识符和该第二数据队列标识符，并根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第二方面，在第二方面的某些实现方式中，该中断控制器包括工作线程路由表，该工作线程路由表用于指示工作线程和处理器标识符的对应关系，该中断控制器根据该第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，包括：该中断控制器根据该第二负载请求信息将该第二工作线程标识符添加到该负载请求队列；该中断控制器根据该负载请求队列和该待处理数据队列确定该第二处理标识符和该第二数据队列标识符，并根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中，包括：该中断控制器根据该工作线程路由表和该第二工作线程标识符确定该处理器标识符；该中断控制器根据该待处理数据队列确定该第二数据队列标识符，并根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第二方面，在第二方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器标识符的对应关系，该中断控制器向该处理器发送第二中断通知并将该第二数据队列标识符添加到该存储器中，包括：该中断控制器根据该中断路由表和该第一数据队列标识符确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第二方面，在第二方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，该处理路由表地址用于指向处理器路由表，该中断控制器向该处理器发送第二中断通知并将该第二数据队列标识符添加到该存储器中，包括：该中断控制器根据该中断路由表和该第二数据队列标识符确定第二处理器路由表地址；该中断控制器根据该第二处理器路由表地址确定第二处理器索引和第二处理器路由表大小；该中断控制器根据该第二处理器索引 和该第二处理器路由表大小确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第二方面，在第二方面的某些实现方式中，该处理器设置有第二用户态中断处理中标识位，该第二用户态中断处理中标识位用于指示该处理器是否正在处理用户态中断，该方法还包括：该处理器处理该第二数据队列的数据时，设置该第二用户态中断处理中标识位以指示正在处理用户态中断。
结合第二方面，在第二方面的某些实现方式中，该处理器还运行有业务线程，该业务线程用于处理除处理数据队列以外的业务，该中断控制器设置有阻塞标识位，该阻塞标识位用于指示该第二工作线程的状态，该方法还包括：该处理器在确定未有该数据队列处理时，将该第二工作线程调整为休眠状态并设置该阻塞标识位以指示该第二工作线程的状态为该休眠状态。
第三方面，提供了一种计算机设备，该计算机设备包括中断控制器、处理器以及存储器，该存储器用于存储数据队列标识符，该处理器用于处理数据队列的数据，其中，该中断控制器，用于获取第一中断请求信息，该第一中断请求信息指示第一数据队列标识符；该中断控制器，还用于向该处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中；该处理器，用于根据该第一中断通知向该中断控制器发送第一中断处理请求；该中断控制器，还用于根据该第一中断处理请求向该处理器发送该第一数据队列标识符并将该第一数据队列标识符移出该存储器；该处理器，还用于处理该第一数据队列的数据，该第一数据队列为该第一数据队列标识符对应的数据队列。
结合第三方面，在第三方面的某些实现方式中，该处理器，还用于在检测到第一数据队列存在未处理的数据时向该中断控制器发送第一反补请求以指示该中断控制器重新发送用于处理该第一数据队列的中断通知。
结合第三方面，在第三方面的某些实现方式中，该计算机设备包括待处理数据队列，该中断控制器，还用于将该第一数据队列标识符添加到待处理数据队列；该处理器，还用于在该中断控制器向该第一处理器发送第一中断通知并将该第一数据队列标识符添加到该存储器中之前，向该中断控制器发送第一负载请求信息；该中断控制器，还用于根据该第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，其中该处理器标识符用于指示该处理器，该第一工作线程标识符用于指示该第一工作线程；该中断控制器，具体用于根据该负载请求队列和该待处理数据队列确定该处理器标识符和该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第三方面，在第三方面的某些实现方式中，该中断控制器包括工作线程路由表，该工作线程路由表用于指示工作线程和处理器标识符的对应关系，其中，该中断控制器，具体用于根据该第一负载请求信息将该第一工作线程标识符添加到该负载请求队列；该中断控制器，还用于根据该工作线程路由表和该第一工作线程标识符确定该处理器标识符；该中断控制器，具体用于根据该待处理数据队列确定该第一数据队列标识符，并根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中
结合第三方面，在第三方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器标识符的对应关系，其中，该中断控制器，还用于根据该中断路由表和该第一数据队列标识符确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器，具体用于根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第三方面，在第三方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，该处理路由表地址用于指向处理器路由表，其中，该中断控制器，还用于根据该中断路由表和该第一数据队列标识符确定第一处理器路由表地址；该中断控制器，还用于根据该第一处理器路由表地址确定第一处理器索引和第一处理器路由表大小；该中断控制器，还用于根据该第一处理器索引和该第一处理器路由表大小确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器，具体用于根据该处理器标识符向该处理器发送该第一中断通知并将该第一数据队列标识符添加到该存储器中。
结合第三方面，在第三方面的某些实现方式中，该第一工作线程注册有用户态中断，该第一中断通知为用户态中断。
结合第三方面，在第三方面的某些实现方式中，该处理器上运行多个工作线程和空转工作线程，该空转工作线程注册有用户态中断，该多个工作线程用于处理数据队列中的数据，该多个工作线程包括该 第一工作线程，当该多个工作线程未处理数据队列中的数据时，该处理器，还用于空循环该空转工作线程以使该处理器处于用户态。
结合第三方面，在第三方面的某些实现方式中，该处理器设置有第一用户态中断处理中标识位，该第一用户态中断处理中标识位用于指示该处理器是否正在处理用户态中断，该处理器，还用于处理该第一数据队列的数据时，设置该第一用户态中断处理中标识位以指示正在处理用户态中断。
第四方面，提供了一种计算机设备，该计算机设备包括中断控制器、处理器以及存储器，该存储器用于存储数据队列标识符，该处理器运行有第二工作线程，该第二工作线程用于处理数据队列中的数据，该处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，该用户态中断待处理标识位用于指示该处理器是否存在待处理的用户态中断，该用户态中断使能标识位用于指示该处理器是否使能处理该用户态中断，其中，该中断控制器，用于获取第二中断请求信息，该第二中断请求信息指示第二数据队列标识符；该中断控制器，还用于向该处理器发送第二中断通知并将该第二数据队列标识符添加到该存储器中，该第二中断通知为该用户态中断；该处理器，用于根据该第二中断通知设置该用户态中断待处理标识位为该用户态中断待处理标识位的第一状态，该用户态中断待处理标识位的第一状态指示存在该用户态中断待处理，以及设置该用户态中断使能标识位为该用户态中断使能标识位的第一状态，该用户态中断使能标识位的第一状态指示该处理器使能处理该用户态中断；在存在用户态中断待处理的情况下，该处理器，向该中断控制器发送第二中断处理请求；该中断控制器，还用于根据该第二中断处理请求向该处理器发送该第二数据队列标识符并将该第二数据队列标识符移出该存储器；该处理器，还用于处理该第二数据队列的数据，该第二数据队列为该第二数据队列标识符对应的数据队列。
结合第四方面，在第四方面的某些实现方式中，处理器，还用于在检测到第二数据队列存在未处理的数据时向该中断控制器发送第二反补请求以指示中断控制器重新发送用于处理第二数据队列的中断通知。
结合第四方面，在第四方面的某些实现方式中，该中断控制器，还用于将该第二数据队列标识符添加到待处理数据队列；该处理器，还用于向该中断控制器发送第二负载请求信息；该中断控制器，还用于根据该第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，其中该处理器标识符用于指示该处理器，该第二工作线程标识符用于指示该第二工作线程；该中断控制器，具体用于根据该负载请求队列和该待处理数据队列向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第四方面，在第四方面的某些实现方式中，该中断控制器包括工作线程路由表，该工作线程路由表用于指示工作线程和处理器标识符的对应关系，其中，该中断控制器，具体用于根据该第二负载请求信息将该第二工作线程标识符添加到该负载请求队列；该中断控制器，还用于根据该工作线程路由表和该第二工作线程标识符确定该处理器标识符。
结合第四方面，在第四方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器标识符的对应关系，其中，该中断控制器，还用于根据该中断路由表和该第一数据队列标识符确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器，具体用于根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第四方面，在第四方面的某些实现方式中，该中断控制器包括中断路由表，该中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，该处理路由表地址用于指向处理器路由表，其中，该中断控制器，还用于根据该中断路由表和该第二数据队列标识符确定第二处理器路由表地址；该中断控制器，还用于根据该第二处理器路由表地址确定第二处理器索引和第二处理器路由表大小；该中断控制器，还用于根据该第二处理器索引和该第二处理器路由表大小确定处理器标识符，该处理器标识符用于指示该处理器；该中断控制器，具体用于根据该处理器标识符向该处理器发送该第二中断通知并将该第二数据队列标识符添加到该存储器中。
结合第四方面，在第四方面的某些实现方式中，该处理器设置有第二用户态中断处理中标识位，该第二用户态中断处理中标识位用于指示该处理器是否正在处理用户态中断，该处理器，还用于处理该第二数据队列的数据时，设置该第二用户态中断处理中标识位以指示正在处理用户态中断。
结合第四方面，在第四方面的某些实现方式中，该处理器还运行有业务线程，该业务线程用于处理除处理数据队列以外的业务，该中断控制器设置有阻塞标识位，该阻塞标识位用于指示该第二工作线程的状态，其中，该处理器，还用于在确定未有该数据队列处理时，将该第二工作线程调整为休眠状态并 设置该阻塞标识位以指示该第二工作线程的状态为该休眠状态。
第五方面，为本申请实施例的一种芯片，该芯片与电子设备中的存储器耦合，用于调用存储器中存储的计算机程序并执行本申请实施例上述方面及其上述方面任一可能设计的技术方案；本申请实施例中“耦合”是指两个部件彼此直接或间接地结合。
第六方面，为本申请实施例的一种计算机可读存储介质，该计算机可读存储介质包括计算机程序，当计算机程序在电子设备上运行时，使得该电子设备执行如上述方面及其上述方面任一可能设计的技术方案。
第七方面，为本申请实施例的一种计算机程序，该计算机程序包括指令，当该指令在计算机上运行时，使得该计算机执行如上述方面及其上述方面任一可能设计的技术方案。
其中，第三方面至第七方面的有益效果，请参见第一方面或第二方面的有益效果，不重复赘述。
附图说明
图1是本申请实施例提供计算机设备的结构示意图。
图2是一种虚拟IO处理的方法的示意性流程图。
图3是本申请实施例提供的中断控制器的示意性结构图。
图4是本申请实施例提供的中断收集装置的示意性结构图。
图5是本申请实施例提供的中断路由装置的示意性结构图。
图6是本申请实施例提供的中断投递装置的示意性结构图。
图7是本申请实施例提供的中断交互装置的示意性结构图。
图8是本申请实施例提供的中断控制器的数据流向示意图。
图9是本申请实施例提供的工作线程调度框架图。
图10是本申请实施例提供的工作线程运行时的框架图。
图11是本申请实施例提供的另一种数据面处理模型示意图。
图12是本申请实施例提供的另一种数据面处理模型示意图。
图13是本申请实施例提供的数据处理方法的示意性流程图。
图14是本申请实施例提供的数据处理方法的示意性流程图。
图15是本申请实施例提供的数据处理的方法的示意性流程图。
具体实施方式
以下实施例中所使用的术语只是为了描述特定实施例的目的，而并非旨在作为对本申请的限制。如在本申请的说明书和所附权利要求书中所使用的那样，单数表达形式“一个”、“一种”、“所述”、“上述”、“该”和“这一”旨在也包括例如“一个或多个”这种表达形式，除非其上下文中明确地有相反指示。还应当理解，在本申请以下各实施例中，“至少一个”、“一个或多个”是指一个、两个或两个以上。术语“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系；例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A、B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在本说明书中描述的参考“一个实施例”或“一些实施例”等意味着在本申请的一个或多个实施例中包括结合该实施例描述的特定特征、结构或特点。由此，在本说明书中的不同之处出现的语句“在一个实施例中”、“在一些实施例中”、“在其他一些实施例中”、“在另外一些实施例中”等不是必然都参考相同的实施例，而是意味着“一个或多个但不是所有的实施例”，除非是以其他方式另外特别强调。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
在介绍本申请实施例之前，首先介绍本申请实施例引入的几个概念。
虚拟化：虚拟化是将计算机设备的硬件层中的硬件资源(例如处理器、存储器、网络资源)虚拟化后共享给一个或多个虚拟计算机使用。虚拟计算机可以是所有类型的虚拟化设备中通过软件虚拟出来的运行环境的统称。虚拟计算机可以包括虚拟机和容器。
如图1所示，计算机设备100包括硬件层101、宿主机层102和虚拟化层103，其中虚拟化层103可以包括一个或多个虚拟机，例如虚拟机104和虚拟机105，硬件层包括处理器系统106、存储器107、通信接口108、中断控制器109，处理器系统包括一个或多个处理器，例如处理器110、处理器111。
需要说明的是，图1中仅以虚拟化层包括虚拟机104和虚拟机105，以及处理器系统106包括处理器110和处理器111为例，但本申请实施例并不限定于此。
虚拟机(virtual machine,VM)是通过虚拟化软件在计算机设备上模拟出的一台或者多台虚拟计算机。虚拟机可以运行在完全隔离的环境中，就像真正的计算机那样进行工作。虚拟机(即图1中104和105)上可以安装客户操作系统(guest operating system,guest OS)，客户操作系统上可以运行有一个或多个应用程序。虚拟机还可访问网络资源。对于在虚拟机中运行的应用程序而言，就像是在真正的计算机中工作。
虚拟机在运行时会涉及到虚拟机特权级，该虚拟机特权级包括虚拟机的用户态和虚拟机的内核态。虚拟机的内核态和虚拟机的用户态的划分是将虚拟机当做真正的计算机来划分的。在计算机系统中，可以将虚拟地址空间划分为内核空间和用户空间，内核空间还可以称为内核态虚拟地址空间，用户空间还可以称为用户态虚拟地址空间。内核空间和用户空间对应有寄存器，寄存器中存储有对应空间的独立的页表基地址。运行在用户空间的进程或线程可以称为用户态的进程或线程，运行在内核空间的进程或线程可以称为内核态的进程或线程。
如图1所示，虚拟机可以包括虚拟处理器，虚拟处理器可以理解为在虚拟化技术下，代表以共享或者分片方式提供给虚拟机使用的物理处理单元，例如虚拟处理器(virtual central processing unit,VCPU)。虚拟机可以有一个或多个虚拟处理器，当存在多个虚拟处理器时，可以选择一个虚拟处理器为主虚拟处理器,其他为从虚拟处理器。此外，虚拟机还可以包括虚拟存储器等其他虚拟硬件资源，但未在图1中未示出。应理解，虚拟机相当于一台独立的计算机，所以虚拟机执行动作也可以认为是虚拟处理器执行该动作。虚拟处理器是通过虚拟化软件虚拟出的，它的运行实际是宿主机的处理器或物理核读取并运行软件程序实现的，例如一个物理核读取软件程序并在该物理核的硬件辅助虚拟化的特定模式下运行该软件程序以实现一个虚拟处理器。一个虚拟机的多个虚拟处理器可以位于不同的物理核上。
虚拟处理器陷入(trap in)和VCPU陷出(trap out)：虚拟化系统包括两种模式：宿主模式(host mode)与客户模式(guest mode)。宿主模式也可以称为是host的特权级，如：host的用户态或host的内核态，客户模式也可以称为是虚拟机的特权级，如：虚拟机的用户态或虚拟机的内核态。当一个虚拟处理器进入客户模式，叫做陷入(虚拟)；当该虚拟处理器离开客户模式，叫陷出(虚拟)。虚拟处理器陷出后物理处理器将暂时不执行该虚拟处理器的代码，所以此时可以理解为虚拟处理器没有运行。针对一个物理处理器而言，其上运行的虚拟处理器陷入，则可以认为该物理处理器处于客户模式，运行虚拟处理器的代码，当其上运行的虚拟处理器陷出到宿主模式，则可以认为该物理处理器处于宿主模式，运行宿主机相关的代码，比如虚拟机监视器。
宿主机(host)层102作为管理层，用以完成硬件资源的管理、分配，为虚拟机呈现虚拟硬件平台，实现虚拟机的调度和隔离等。在一些实现方式下，宿主机层102可以包括宿主机操作系统和虚拟监控装置，例如虚拟机监视器110(virtual machine monitor,VMM)。其中虚拟机监视器可部署在宿主机操作系统之内，也可以部署在宿主机操作系统之外。在另一些虚拟化架构中虚拟监控装置还可以称为hypervisor或其他类型的虚拟监控装置。虚拟硬件平台对其上运行的各个虚拟机提供各种硬件资源，如虚拟处理器、虚拟内存、虚拟磁盘、虚拟网卡等。虚拟机则运行在宿主机层为其准备的虚拟硬件平台上。宿主机层102还可以称为虚拟化平台或宿主机。宿主机的特权级包括用户态和内核态。
硬件层103：虚拟化环境运行的硬件平台。其中，硬件层可包括多种硬件，如图1所示，硬件层可包括处理器系统106和存储器107，还可以包括通信接口108，例如网卡(network interface card，NIC)；还可以包括中断控制器109、输入/输出(input/output,I/O)设备等，本申请实施例中可以将输入/输出设备简称为设备。其中处理器系统106可以包括一个或多个处理器，如图1中列举的处理器110和处理器111。每个处理器中可包括多个物理核，处理器中还可以包括多个寄存器，如：通用寄存器、浮点寄存器等。
处理器系统106，有时称为物理处理器。物理核代表处理器中最小处理单元，各个处理器包含的核的个数可以相同，也可以不同。具有一个核的处理器称为单核处理，具有多个物理核的处理器被称为多核处理器。按照内核架构是否相同，可以分为同构多核与异构多核。虚拟处理器和物理核可以是绑定的关系，即一个虚拟处理器固定在某个物理核上运行，不能被调度到其他物理核上运行，则该虚拟处理器为绑核；一个虚拟处理器可以根据需要被调度到不同的物理核上运行，则该虚拟处理器为非绑核。
中断控制器109：主要用于收集各个设备、处理器、虚拟机产生的中断请求，并将中断请求发送给处理器以使处理器可以处理中断请求。针对本申请实施例提供的中断控制器109的描述可以参见后文说明，在此不展开叙述。
中断(interruption)：是指暂停当前程序的指令转而执行中断服务程序。
中断服务程序：用于处理中断请求的程序。中断服务程序也可以称为中断处理函数。当处理器接收到中断请求时，可以暂停执行当前程序的指令转而执行该中断请求对应的中断服务程序。
中断请求(interrupt request)：中断请求指的是硬件(例如I/0设备、处理器)或虚拟机产生的一种事件。当处理器接收到中断请求时，暂时停止当前程序的执行转而执行该事件对应的程序。硬件产生中断请求可能是硬件自己触发的，也可能是软件触发硬件产生的。中断请求有时也可以称为中断。
计算机设备100可以为物理设备，例如服务器或电子设备。电子设备可以是具有无线连接功能的手持式设备、或连接到无线调制解调器的其他处理设备。例如，可以为移动电话、计算机(personal computer，PC)、平板电脑、个人数码助理(personal digital assistant，PDA)、移动互联网设备(mobile Internet device，MID)、可穿戴设备和电子书阅读器(e-book reader)等；也可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动设备。
虚拟化技术中的IO虚拟化可以为虚拟机提供复用计算机中的设备的能力。虚拟机可以发送IO请求，宿主机驱动处理器轮询处理IO请求。图2示出了一种虚拟IO处理的方法的示意性流程图，如图2所示，该方法包括：
S201，虚拟机与设备共享数据队列。
虚拟机和设备可以通过数据平面开发包(data plane development kit，DPDK)共享数据队列。虚拟机和设备可以通过共享的数据队列传递IO数据。每一个虚拟机和设备可以绑定多个数据队列，即共享多个数据队列。DPDK可以创建N个工作线程，N＞0且为整数，绑定运行在N个预留物理核上，工作线程通过轮询遍历数据队列上的IO数据以获取并处理IO数据。每一个工作线程固定处理绑定的数据队列中的数据。
S202，虚拟机向数据队列发送IO数据。
当虚拟机需要向设备发送IO数据时，可以先将该IO数据发送到与设备共享的数据队列
S203，工作线程轮询数据队列以获取IO数据。
工作线程可以轮询与其绑定的数据队列以获取IO数据。
S204，工作线程向设备发送IO数据。
工作线程接收到虚拟机发送的IO数据后，可以将该IO数据发送设备，从而实现了从虚拟机角度向设备发送IO数据。
类似的，设备也可以向与虚拟机共享的数据队列发送IO数据，工作线程轮询数据队列获取到该IO数据后可以向虚拟机发送该IO数据，以实现从设备角度想虚拟机发送IO数据。
由上述描述可知，工作线程需要轮询所有设备与虚拟机共享的数据队列以获取IO数据，但并不是所有共享的数据队列中均有需要处理的IO数据，当工作线程轮询的数据队列为空时，会增加处理IO数据的尾延迟，此外不同设备和虚拟机发送的IO请求的频率不同，以及IO请求的数据量和设备处理的时间也会不相同，从而导致绑定数据队列的工作线程存在负载不均衡的情况，降低了系统整体峰值带宽。基于此，本申请实施例提供了一种数据处理方法，可以降低IO处理的尾延迟，且可以根据工作线程的负载分发数据，保证了IO数据的负载均衡。
下面将详细介绍本申请实施例提供的中断控制器109。
图3示出了本申请实施例提供的中断控制器109的示意性结构图，如图3所示，中断控制器109包括中断收集装置1091、中断路由装置1092、中断投递装置1093、中断交互装置1094，其中中断收集装置1091用于收集设备、虚拟机和处理器的中断请求，中断路由装置1092用于选择工作线程作为中断请求投递目标，中断投递装置1093用于将中断请求投递给处理器，中断交互装置1094用于收集处理器的负载信息、向中断路由装置1093传递处理器的负载请求以及管理中断请求的生命周期，下面将介绍中断控制器109中的各个装置。
图4示出了本申请实施例提供的中断收集装置1091的示意性结构图，如图4所示，中断收集装置1091包括中断-数据队列映射表寄存器和数据队列标识符表寄存器，其中中断-数据队列映射表寄存器中存储有中断-数据队列映射表地址，该中断-数据队列映射表可以由宿主机配置，数据队列标识符表寄存器存储是有数据队列标识符表地址。
以设备为例，设备向数据队列发送IO数据后，可以发送中断请求信息，该中断请求信息中包括设备中断标识符，该设备中断标识符用于指示请求中断的设备。中断-数据队列映射表用于指示中断请求与数 据队列的映射关系，该中断-数据队列映射表表项可以包括设备中断标识符和数据队列标识符，中断收集装置1091收集到该中断请求信息后，可以根据中断请求信息中的设备中断标识符和中断-数据队列映射表确定该中断请求信息对应的数据队列标识符。
再以虚拟机为例，虚拟机向数据队列发送IO数据后，可以发送中断请求信息，该中断请求信息中包括虚拟机标识符和虚拟事件中断标识符，该虚拟机标识符用于请求中断的虚拟机，该虚拟事件中断标识符用于指示请求中断的虚拟事件。中断-数据队列映射表用于指示中断请求与数据队列的映射关系，该中断-数据队列映射表表项可以包括虚拟事件中断标识符、虚拟机标识符和数据队列标识符，中断收集装置1091收集到该中断请求信息后，可以根据中断请求信息中的虚拟事件中断标识符和虚拟机标识符以及中断-数据队列映射表确定该中断请求信息对应的数据队列标识符。
再以处理器为例，处理器向数据队列发送IO数据后，可以发送中断请求信息，该中断请求信息中包括处理器中断标识符，该设备中断标识符用于指示请求中断的处理器。中断-数据队列映射表用于指示中断请求与数据队列的映射关系，该中断-数据队列映射表表项可以包括处理器中断标识符和数据队列标识符，中断收集装置1091收集到该中断请求信息后，可以根据中断请求信息中的处理器中断标识符和中断-数据队列映射表确定该中断请求信息对应的数据队列标识符。
数据队列标识符表用于指示数据队列的状态，其中数据队列的状态包括正在被处理和未被处理。示例性的，可以使用数据队列标识符表中的每一个比特位标识一个数据队列的状态，数据队列标识符表中的每一个比特位的位置可以对应一个数据队列，比特位的值可以用于指示数据队列的状态。
需要说明的是，下文在介绍时，本申请实施例中以比特位的值为0指示数据队列未被处理，以比特位的值为1指示数据队列正在被处理为例进行说明，但不应理解为对本申请实施例的限定，在另一些实施例中，可以以比特位的值为1指示数据队列未被处理，以比特位的值为0指示数据队列正在被处理。
中断收集装置1091收集中断请求信息后，可以根据中断请求信息确定该中断请求信息对应的数据队列标识符，并根据数据标识标识符表确定该数据队列是否正在被处理，若该数据队列未被处理，中断收集装置1091可以将该数据队列标识符发送给中断路由装置1092，并将该数据队列标识符对应的比特位的值由0置为1。
中断收集装置1091将数据队列标识符发送给中断路由装置1092后，中断路由装置102可以确定中断请求的投递目标，下面将详细介绍中断路由装置1092。
在一些实施例中，如图5中的(a)示出的一种中断路由装置的示意性结构图，中断路由装置1092可以包括环形队列和决策装置，决策装置用于确定路由分发的策略。
环形队列包括size寄存器#1、size寄存器#2、base寄存器#1、base寄存器#2、head寄存器#1、head寄存器#2、tail寄存器#1、tail寄存器#2，其中size寄存器#1用于存储待处理数据队列的条目数量，size寄存器#2用于存储负载请求队列的条目数量，base寄存器#1用于存储待处理数据队列的地址，base寄存器#2用于存储负载请求队列的地址、head寄存器#1用于存储待处理数据队列的头索引，head寄存器#2用于存储负载请求队列的头索引，tail寄存器#1用于存储待处理数据队列的尾索引，tail寄存器#2用于存储负载请求队列的尾索引。待处理数据队列用于存储从中断收集装置1091接收的数据队列标识符，负载请求队列用于存储请求负载的处理器标识符。
以size寄存器#1的值为4为例，待处理数据队列的条目数量可以满足24＝16。初始状态下，待处理数据队列为空，则head#1寄存器的值为0，tail寄存器#1的值为0，即head#1＝＝tail#1。当中断路由装置1092每一次接收到中断收集装置1091发送的数据队列标识符后，head寄存器#1的值可以增加1，当head寄存器#1的值增加至0x10000时，表示待处理数据队列包含了16个条目，即待处理数据队列已满。此时tail寄存器#1的值为0x00000。由上述描述，head寄存器#1的0-4位和tail寄存器#1的0-4位相同，且第五位不同，即可以表示为head[size-1:0]＝＝tail[size-1:0]&&head[size]！＝tail[size]。当head寄存器#1和tail寄存器#1更新溢出时，head寄存器#1和tail寄存器#1的值可以重置为0。类似的，针对size寄存器#2、base寄存器#2、head寄存器#2、tail寄存器#2的描述可以参见针对size寄存器#1、base寄存器#1、head寄存器#1、tail寄存器#1的描述。通过环形队列，中断路由装置1092可以获知待处理数据队列和负载请求队列的信息，无需工作线程轮询待处理数据队列，而是在待处理数据队列和负载请求队列不为空时，根据待处理数据队列和负载请求队列进行路由分发。
本申请实施例对于待处理数据队列和负载请求队列的存储位置不作限定，例如，待处理数据队列和负载请求队列可以存储在中断路由装置中。
下面将介绍几种中断路由装置1092根据待处理数据队列和负载请求队列进行路由分发的方法。
在一些实施例中，中断路由装置1092可以根据进入待处理数据队列的数据队列标识和进入负载请求队列的处理器标识符的顺序进行路由分发。
例如，中断路由装置1092可以从待处理数据队列选择添加时间最长的数据队列标识符，从负载请求队列选择添加时间最长的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。换句话说，中断路由装置1092可以基于“先进先出”的原则进行路由分发。
在一些实施例中，中断路由装置1092可以根据优先级进行路由分发。
例如，本申请实施例中可以定义数据队列的优先级，中断路由装置1092从待处理数据队列中选择优先级最高的数据队列的数据队列标识符，从负载请求队列选择添加时间最长的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
再例如，本申请实施例中可以定义处理器的优先级，中断路由装置1092从待处理数据队列选择添加时间最长的数据队列标识符，从负载请求队列选择优先级最高的处理器对应的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
再例如，本申请实施例中可以定义数据队列的优先级和处理器的优先级，中断路由装置1092从待处理数据队列选择添加时间最长的数据队列标识符，从负载请求队列选择优先级最高的处理器对应的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
在一些实施例中，中断路由装置1092可以随机选取待处理数据队列中的数据队列标识符和负载请求队列中的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
在一些实施例中，中断路由装置1092在根据负载请求队列选择处理器标识符时可以根据处理器的工作负载量选择处理器标识符。
例如，处理器可以向中断路由装置1092发送工作负载量，从而中断路由装置1092从待处理数据队列中选择添加时间最长的数据队列标识符，从负载请求队列选择工作负载量低的处理器的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
再例如，处理器可以向中断路由装置1092发送工作负载量，从而中断路由装置1092从待处理数据队列中选择优先级最高的数据队列的数据队列标识符，从负载请求队列选择工作负载量低的处理器的处理器标识符，然后将该数据队列标识符发送到该处理器标识符对应的中断投递装置1093中。
需要说明的是，上述中断路由装置1092根据待处理数据队列和负载请求队列进行路由分发的方式仅为示例，不应理解为对于本申请的限定，中断路由装置1092通过其他方法选择待处理数据队列的中的数据队列标识符和负载请求队列中的处理器标识符进行路由分发也应落入本申请的保护范围之内。
在一些实施例中，如图5中的(b)示出的一种中断路由装置1092的示意性结构图，中断路由装置1092可以包括中断路由表寄存器，该中断路由表寄存器可以指向中断路由表，该中断路由表的表项包括数据队列标识符和处理器标识符。该中断路由表可以由宿主机配置，使得每一个数据队列标识符可以对应有处理器标识符。
中断收集装置101收集中断请求信息后，可以根据中断请求信息确定该中断请求对应的数据队列标识符，然后将该数据队列标识符发送给中断路由装置1092。中断路由装置1092根据数据队列标识符检测中断路由表以获取处理器标识符，
中断路由装置1092获取到数据队列标识符和处理器标识符后，可以将该数据队列标识符更新到该处理器标识符对应的处理器的中断投递装置1093中。
在另一些实施例中，如图5中的(c)示出的一种中断路由装置1092的示意性结构图，中断路由装置1092可以包括中断路由表寄存器，该中断路由器寄存器可以指向中断路由表，该中断路由表表项包括数据队列标识符和处理器路由表地址。处理器路由表地址可以指向处理器路由表，该处理器路由表的表头包括处理器索引和处理器路由表大小，表项包括处理器标识符。
中断收集装置1091收集中断请求信息后，可以根据中断请求信息确定该中断请求信息对应的数据队列标识符，然后将该数据队列标识符发送给中断路由装置1092。中断路由装置1092根据该数据队列标识符检索中断路由表，可以确定该数据队列标识符对应的处理器路由表地址。中断路由装置1092根据处理器路由表地址从该处理器路由表的表头获取处理器索引和处理器路由表大小。中断路由装置1092再根据处理器索引检索处理器路由表表项以获取处理器标识符。中断路由装置1092在获取到数据队列标识符和处理器标识符后，可以将该数据队列标识符更新到该处理器标识符对应的处理器的中断投递装置1093中。
在一些实施例中，中断路由装置1092在将数据队列标识符更新到中断投递装置1093后，还可以更新处理器索引。示例性的，中断路由装置1092可以根据公式(1)更新处理器索引。
y＝(x+1)mod(m)              (1)
其中，y为更新后的处理器索引，x为原处理器索引，m为处理器路由表大小。
中断路由装置1092将数据队列标识符发送给中断投递装置1093，每一个处理器可以对应有一个中断投递装置1093，中断投递装置1093可以向该处理器发送数据队列标识符。中断投递装置1093可以存储有待处理数据队列的数据队列标识符和正在处理数据队列的数据队列标识符。
在一些实施例中，如图5中的(d)示出的中断路由装置1092的示意性结构图，中断路由装置包括环形队列、决策装置和路由表地址寄存器，其中针对环形队列和决策装置的描述可以参见上文，为了简洁，在此不再赘述。
需要说明的是，与上文所述的负载请求队列不同的是，图5中的(d)所示的中断路由装置中的负载请求队列存储的是工作线程标识符，而不是处理器标识符。
路由表地址寄存器可以指向工作线程路由表，该工作线程路由表表项包括工作线程标识符和处理器标识符，该工作线程路由表可以由宿主机配置并更新，对应的中断投递装置1093可以包括线程标识符寄存器，该线程标识符寄存器存储有工作线程标识符，具体可以参见下文针对图6中的(c)的描述。
中断路由装置1092可以在待处理数据队列和负载请求队列都不为空时，根据待处理数据队列和负载请求队列确定数据队列标识符和工作线程标识符，然后根据工作线程标识符索引工作线程路由表以获取处理器标识符，然后将该数据队列标识符更新到处理器标识符对应的处理器的中断投递装置1093中。
应理解，针对中断路由装置根据待处理数据队列和负载请求队列确定数据队列标识符和工作线程标识符的描述类似于中断路由装置根据待处理数据队列和负载请求队列确定数据队列标识符和处理器标识符，为了简洁，在此不再赘述。
图6示出了中断投递装置1093的示意性结构图，如图6中的(a)所示，中断投递装置1093包括待处理寄存器和正在处理寄存器，其中待处理寄存器用于存储等待处理器处理的数据队列标识符，正在处理寄存器用于存储处理器正在处理的数据队列标识符。
在一些实施例中，中断投递装置1093还包括中断类型寄存器，该中断类型寄存器用于存储中断类型，其中中断类型包括内核态中断和用户态中断。
需要说明的是，本申请实施例中并不限定中断投递装置1093存储数据队列标识符的方式。例如，如图6中的(a)所示，中断投递装置1093可以使用寄存器存储数据队列标识符和中断类型。再例如，中断投递装置1093还可以使用内存存储数据队列标识符和中断类型。
以图6中的(a)所示的中断投递装置1093为例，中断路由装置1092向中断投递装置1093发送数据队列标识符时，可以将数据队列标识符更新到中断投递装置1093的待处理寄存器中。中断投递装置1093可以向处理器发送中断请求。当处理器请求处理数据队列时，中断投递装置1093可以从待处理寄存器中获取数据队列标识符，将该数据队列标识符更新到正在处理寄存器中，并将该数据队列标识符发送给处理器。
在一些实施例中，中断投递装置1093在发送中断请求时，可以根据中断类型寄存器中的中断类型向处理器发送中断请求。
图6中的(b)示出了另一种中断投递装置1093的示意性结构图，与图6中的(a)所示的中断投递装置1093不同的是，中断投递装置1093不再存储待处理的数据队列标识符，即中断投递装置中不再包括待处理寄存器，而是新增size寄存器、base寄存器、head寄存器、tail寄存器分别存储处理器待处理数据队列的条目数据，地址、头索引和尾索引，其中该处理器待处理数据队列可以存储在除中断投递装置以外的装置中，例如计算机设备的内存中。当head＝＝tail时，该处理器待处理数据队列为空，当head[size-1:0]—tail[size-1:0]&&head[size]！＝tail[size]时，该处理器待处理数据队列为满。当该处理器待处理数据队列添加一个元素时，head值加1，当该处理器待处理数据队列取出元素时，tail值加1。
需要说明的是，处理器待处理数据队列与中断路由装置1092路由分发的待处理数据队列并不相同，处理器待处理数据队列存储的是已路由分发到处理器的数据队列标识符，待处理数据队列存储的是中断收集装置1091收集的待处理的数据队列。
以图6中的(b)所示的中断投递装置1093为例，中断路由装置1092向中断投递装置1093发送数据队列标识符时，可以将数据队列标识符加载到处理器待处理数据队列，从而中断投递装置1093可以更新 上述寄存器。中断投递装置1093可以向处理器待处理数据队列不为空时向处理器发送中断请求，以及从处理器待处理数据队列获取数据队列标识符，将该数据队列标识符更新到正在处理寄存器中，并将该数据队列标识符发送给处理器。
以如图6中的(c)所示的中断投递装置1093为例，中断投递装置1093包括待处理寄存器、正在处理寄存器、中断类型寄存器和线程标识符寄存器，针对待处理寄存器、正在处理寄存器、中断类型寄存器的描述可以参见上文，为了简洁在此不再赘述。
每个处理器可以对应一个中断投递装置1093，该线程标识符寄存器可以存储有运行在处理器上的工作线程的标识符。当处理器通过工作线程访问中断交互装置1094的负载请求接口时可以指示中断投递装置1093可以将线程标识符寄存器中的工作线程标识符添加到负载请求队列中。
上面介绍了中断收集装置1091、中断路由装置1092和中断投递装置1093，下面将介绍中断交互装置1094。
中断交互装置1094可以获取处理器的工作负载量，处理器可以通过中断交互装置1094向中断路由装置1092请求负载。中断交互装置1094还可以管理中断生命周期。每一个处理器可以对应一个中断交互装置1094。中断交互装置1094可以包括多个接口用于实现上述功能。
图7示出了一种中断交互装置1094的示意性结构图。如图7所示，中断交互装置1094包括负载请求接口、中断处理接口和中断结束接口，其中，处理器中的工作线程可以通过负载请求接口使得处理器标识符或工作线程标识符添加到负载请求队列；处理器中的工作线程可以通过中断处理接口从中断投递装置1093获取正在处理的数据队列标识符；处理器中的工作线程可以完成数据队列处理后通过中断结束接口使得中断收集装置1091中的数据队列标识符表对应的数据队列的比特位重置为0。
在一些实施例中，中断交互装置1094还可以包括中断反补接口。处理器通过工作线程处理IO请求时，只会处理数据队列中的固定数量的IO数据。若数据队列中还有IO数据在本次处理中未被处理，处理器可以通过工作线程调用中断交互装置1094中的中断反补接口，使得该数据队列标识符重新加入到中断路由装置1092的待处理数据队列中以及中断收集装置1091中的数据队列标识符表的该数据队列对应的比特位置为1，从而保证了该数据队列中的剩余IO数据也可以快速被处理。
在一些实施例中，若中断路由装置1092为图5中的(d)所示的结构，中断投递装置为图6中的(c)所示的结构，当运行在处理器的工作线程访问负载请求接口时，该处理器对应的中断投递装置1093可以从线程标识符寄存器中获取工作线程标识符，然后将工作线程标识符添加到负载请求队列中。
在另一些实施例中，若中断路由装置1092为图5中的(d)所示的结构，中断投递装置为图6中的(c)所示的结构，当运行在处理器的工作线程访问负载请求接口时，该处理器对应的中断交互装置1094可以与中断投递装置1093通信以从线程标识符寄存器中获取工作线程标识符，然后将工作线程标识符添加到负载请求队列中。
需要说明的是，本申请实施例中每一个处理器可以对应一个中断投递装置和一个中断交互装置，在一些实施例中，中断投递装置和中断交互装置可以是集成在同一个装置中。在另一些实施例中，中断投递装置和中断交互装置可以是单独的两个装置。
上面介绍了本申请实施例提供的中断控制器109，下面将结合图8介绍通过中断控制器109处理中断请求时的数据流向。
图8示出了本申请实施例提供的中断控制器的数据流向示意图。
如图8所示为中断控制器与处理的数据流向，需要说明的是，部分数据流向未在图中示出。如图8所示，中断收集装置1091可以收集处理器、设备、虚拟机的中断请求消息，并根据中断请求信息确定数据队列标识符，具体说明请参见上文针对中断收集装置1091的描述。中断收集装置1091确定数据队列标识符后，可以确定该数据队列标识符对应的数据队列是否正在被处理，若该数据队列标识符对应的数据队列未被处理，则中断收集装置1091可以将该数据队列标识符传递到中断路由装置1092的待处理数据队列，并将该数据队列标识符对应的标识位置为1。
处理器可以向中断交互装置1094发送负载请求信息，该负载请求信息用于向中断路由器1092请求路由分发数据队列标识符，该负载请求信息可以包括处理器标识符。中断路由装置1092接收到负载请求信息后，可以将负载请求信息中的处理器标识符添加到负载请求队列中。
中断路由装置1092可以在待处理数据队列和负载请求队列都不为空时，从待处理数据队列中确定一个数据队列标识符，从负载请求队列中确定一个处理器标识符，将该数据队列标识符添加到该处理器标 识符对应的中断投递装置1093的待处理寄存器中。针对中断路由装置1092根据待处理数据队列和负载请求队列确定数据队列标识符和处理器标识符的方法可以参见上文说明。中断投递装置1093可以根据中断类型寄存器存储的中断类型向处理器发送中断请求。例如，中断类型寄存器中存储的中断类型为用户态中断，则中断投递装置1093可以向处理器发送用户态中断。
处理器接收到中断请求后，可以通过中断交互装置1094的中断处理接口发送中断处理请求，中断投递装置1093接收到中断处理请求后，可以将待处理寄存器中的数据队列标识符更新到正在处理寄存器中，并向处理器发送数据队列标识符，以使处理器可以根据数据队列标识符处理数据队列。
在一些实施例中，由于处理器在处理数据队列时，处理器处理的数据量是一定的，则被处理的数据队列中可能会有IO数据未被处理。综上，处理器在处理完数据队列后，检测该数据队列中是否还存在IO数据，若仍存在IO数据，处理器可以通过中断交互装置1094的中断反补接口向中断投递装置1093发送反补请求。中断投递装置1093接收到反补请求后，可以将正在处理寄存中的该数据队列的数据队列标识符重新加入到中断路由装置1092的待处理数据队列中以及将中断收集装置1091中的该数据队列标识符对应的标识位置为1，以使该数据队列可以再次被处理。
在一些实施例中，处理器处理完数据队列后，可以通过中断交互装置1094的中断结束接口发送中断结束请求。中断收集装置1091接收到该中断结束请求后，可以将被处理的数据队列的数据队列标识符对应的标识位重置为0，以指示该数据队列未正在处理。
上面介绍了中断控制器和处理器之间的数据流向，下面将介绍本申请实施例提供的数据面处理模型。下面将结合图9-图12介绍本申请实施例提供的几种数据面处理模型。
图9示出了工作线程调度框架图，图10示出了工作线程运行时的框架示意图。如图9中的(a)示出的一种工作线程调度框架图，数据面对应的处理器可以绑定M个工作线程，其中M＞0且为整数，该M个工作线程可以访问设备与虚拟机共享的数据队列。处理器可以通过线程调度管理模块调度该M个工作线程以处理数据队列。
数据面对应的处理器可以绑定M个工作线程可以理解为处理器的物理核绑定M个工作线程，该处理器可以是单核处理器，也可以是多核处理器，若该处理器是多核处理器，则可以是该处理器中的一个物理核绑定该M个工作线程。
图9中的(b)示出了另一种工作线程调度框架图，相较于图9中的(a)示出的工作线程调度框架图，数据面对应的处理器不仅可以绑定M个工作线程还可以绑定1个空转工作线程，该M个工作线程和空转工作线程可以访问设备与虚拟机共享的数据队列，其中该M个工作线程可以用于处理数据队列、处理除数据队列以外的业务和执行空循环，空转工作线程可以执行空循环和处理数据队列。处理器可以通过线程调度管理模块调度上述线程处理各项业务。
数据面对应的处理器可以绑定M个工作线程和1个空转工作线程可以理解为处理器的物理核绑定M个工作线程和1个空转工作线程，该处理器可以是单核处理器，也可以是多核处理器，若该处理器是多核处理器，则可以是该处理器中的一个物理核绑定该M个工作线程和1个工作线程。
在一些实施例中，该M个工作线程和空转工作线程可以注册用户态中断，从而可以在用户态直接响应用户态中断。针对图9中的(b)示出的工作线程调度框架图，可以通过空转工作线程使得处理器运行在用户态，则当处理器接收到用户态中断时，可以直接处理该中断请求。
以图9中的(a)示出的工作线程调度框架图为例，结合图10示出的工作线程运行时的框架示意图，中断控制器109中的中断路由装置1092可以从待处理数据队列取出数据队列标识符，从负载请求队列取出处理器标识符，将数据队列标识符加载到处理器标识符对应的处理器的中断投递装置的待处理寄存器中，并向该处理器发送中断通知。处理器接收到中断请求时，处理器可以中断工作线程#1处理业务#1而调度工作线程#1处理数据队列，中断上下文管理模块可以将工作线程#1的运行环境切换到中断上下文中。在另一些实施例中，工作线程#1可能处于空转状态，处理器也可以调度该工作线程#1处理数据队列。工作线程#1可以是M个工作线程中的任意一个工作线程。处理器在处理中断请求时，可以根据中断请求的类型切换特权级。
示例性的，若中断请求为用户态中断请求且处理器在内核态，则处理器可以由内核态调整为用户态后处理该中断请求。
示例性的，若中断请求为内核态中断请求且处理器在用户态，则处理器可以由用户态调整为内核态后处理该中断请求。
示例性的，若中断请求为用户态中断请求且处理器在用户态，则处理器可以直接处理该中断请求。
示例性的，若中断请求为内核态中断请求且处理器在内核态，则处理器可以直接处理该中断请求。
以图9中的(b)示出的工作线程调度框架图为例，结合图10示出的工作线程运行时的框架示意图，中断控制器109中的中断路由装置1092可以从待处理数据队列取出数据队列标识符，从负载请求队列取出处理器标识符，将数据队列标识符加载到处理器标识符对应的处理器的中断投递装置的待处理寄存器中，并向该处理器发送用户态中断通知。处理器接收到用户态中断请求时，处理器可以中断工作线程#1处理业务#1而调度该工作线程#1处理数据队列，中断上下文管理模块可以将工作线程#1的运行环境切换到用户态中断上下文中。在另一些实施例中，工作线程#1可能处于空转状态，处理器也可以调度该工作线程#1处理数据队列。工作线程#1可以是M个工作线程中的任意一个工作线程，也可以是空转工作线程。
示例性的，业务#1可以是非延迟敏感型业务，工作线程处理业务#1时被用户态中断打断，不会影响业务#1的业务诉求。
在一些实施例中，空转工作线程的优先级低于M个工作线程的优先级，则处理器需要处理数据队列时，可以优先调度该M个工作线程。此外，当该M个工作线程都处理完业务后，处理器可以通过线程调度模块调度运行空转工作线程，使得该空转工作线程绑定的处理器运行在用户态，保证了该处理器在接收到用户态中断请求时可以直接处理该用户态中断请求。
在一些实施例中，处理器中设置有用于指示处理用户态中断的标识位，该标识位用于指示该处理器正在处理用户态中断，该标识位可以称为用户态中断处理中标识位。本申请实施例对于该用户态中断处理中标识位的存储方式不作限定，例如可以通过增加一个寄存器用于存储该用户态中断处理中标识位，或复用已有寄存器中的空闲域存储该用户态中断处理中标识位。当处理器处理用户态中断时，可以将该用户态中断处理中标识位置为1。当内核在进行调度决策时，可以根据该用户态中断处理中标识位判断该处理器是否正在处理用户态中断，若该处理器正在处理用户态中断，则可以禁止发生内核调度。
图11示出了本申请实施例提供的另一种数据面处理模型示意图。
如图11所示，数据面对应的处理器可以绑定1个工作线程，该工作线程可以轮询处理器的用户态中断待处理标识位，该用户态中断待处理标识位可以指示处理器是否存在待处理的用户态中断。示例性的，若用户态中断待处理标识位为0指示处理器未有待处理的用户态中断，若用户态中断待处理标识位为1指示处理器有待处理的用户态中断。
在一些实施例中，处理器中还包括用户态中断使能标识位，该用户态中断使能标识位可以指示处理器是否可以处理用户态中断。示例性的，当该用户态中断使能标识位为0时，处理器运行时禁止用户态中断；当该用户态中断使能标识位为1时，处理器运行时可以响应用户态中断。
中断路由装置1092可以将数据队列标识符添加到处理器对应的中断投递装置1093的待处理寄存器中。中断投递装置1093可以向处理器发送用户态中断。处理器接收到该用户态中断后，可以将用户态中断待处理标识位由0置为1以及用户态中断使能标识位由0至1。
由于将用户态中断使能标识位由0置为1，处理器在接收到用户态中断后，还可以将工作线程切换到中断处理函数入口以处理该用户态中断。此外，处理器通过工作线程轮询用户态中断待处理标识位，当确定该用户态中断待处理标识位为1时，处理器可以通过中断交互装置1094获取中断投递装置1093中的该数据队列标识符并处理该数据队列标识符对应的数据队列。当处理器通过工作线程处理完该数据队列时，可以通过中断交互装置1094将中断收集装置1091中的数据队列标识符中的该数据队列标识符对应的标志位重置为0。
在一些实施例中，处理器通过工作线程在处理完该数据队列后，还可以检测该数据队列中是否还存在数据，若该数据队列中还存在数据，处理器还可以通过中断交互装置1094的中断反补接口向中断投递装置1093发送反补请求。中断投递装置1093接收到反补请求后，可以将正在处理寄存器中的该数据队列的数据队列标识符重新加入到中断路由装置1092的待处理数据队列中以及将中断收集装置1091中的该数据队列标识符对应的标识位置为1，以使该数据队列可以再次被处理。
图12示出了本申请实施例提供的另一种数据面处理模型示意图。
在图12示出的数据面处理模型中，中断投递装置1093还包括阻塞标识位寄存器，以及数据面对应的处理器不仅可以绑定工作线程，还可以绑定其他用于处理不同业务的线程，以下简称为其他线程或业务线程。
在一些实施例中，工作线程的优先级高于其他线程。由于工作线程的优先级高于其他线程，则处理 器可以优先处理数据队列。
在一些实施例中，处理器包括用户态中断待处理标识位。
在一些实施例中，处理器包括用户态中断使能标识位。
应理解，针对用户态中断待处理标识位和用户态中断使能标识位的描述可以参见上文，为了简洁，在此不再赘述。
中断路由装置1092可以将数据队列标识符添加到处理器对应的中断投递装置1093的待处理寄存器中。中断投递装置1093可以向处理器发送用户态中断。中断投递装置1093可以向处理器发送用户态中断。处理器接收到该用户态中断后，可以将用户态中断待处理标识位由0置为1以及用户态中断使能标识位由0至1。
与图11所示的数据面处理模型不同的是，由于工作线程的优先级高于其他线程，从而工作线程可以一直处理数据队列，即处理器无需将工作线程转到中断处理函数入口就可以处理数据队列。处理器可以通过工作线程轮询用户态中断待处理标识位，当确定该用户态中断待处理标识位为1时，处理器可以通过中断交互装置1094获取中断投递装置1093中的该数据队列标识符并处理该数据队列标识符对应的数据队列。当处理器通过工作线程处理完该数据队列时，可以通过中断交互装置1094将中断收集装置1091中的数据队列标识符中的该数据队列标识符对应的标志位重置为0。
在一些实施例中，处理器通过工作线程在处理完该数据队列后，还可以检测该数据队列中是否还存在数据，若该数据队列中还存在数据，处理器还可以通过中断交互装置1094的中断反补接口向中断投递装置1093发送反补请求。中断投递装置1093接收到反补请求后，可以将正在处理寄存中的该数据队列的数据队列标识符重新加入到中断路由装置1092的待处理数据队列中以及将中断收集装置1091中的该数据队列标识符对应的标识位置为1，以使该数据队列可以再次被处理。
在一些实施例中，当处理器处理完数据队列后，即不存在需要处理的用户态中断时，处理器可以通过工作线程将中断投递装置1093的阻塞标识位置为1，并使得工作线程进入休眠状态。工作线程进入休眠状态后，处理器可以通过其他线程处理其他业务。当中断投递装置1093再次向处理器发送用户态中断，若阻塞标识位为1，则中断投递装置1093可以向处理器发送门铃(doorbell)中断，处理器接收到该门铃中断后，可以唤醒工作线程，并将阻塞标识位重置为0，由于工作线程的优先级高于其他线程，处理器可以优先处理数据队列。
需要说明的是，上述实施例中，用户态中断待处理标识位和用户态中断使能标识位设置在处理器中，则处理器可以管理用户态中断待处理标识为和用户态中断使能标识位，但本申请实施例并不限定于此，在本申请另一些实施例中，用户态中断待处理标识位和用户态中断使能位也可以设置在中断控制器或其他设备中。
上面介绍了本申请实施例提供的数据处理方法的硬件以及软件模型，下面将介绍本申请实施例提供的数据处理的方法，本申请实施例提供的数据处理方法可以用于数据面的处理。
图13示出了本申请实施例提供的数据处理方法的示意性流程图，该方法应用于计算机设备，该计算机设备包括中断控制器、第一处理器以及用于存储数据队列标识符的第一存储器，第一存储器存储的数据队列标识符对应的数据队列是待处理的数据队列，待处理的数据队列可以理解为该数据队列中存在数据，第一处理器运行有第一工作线程，该第一工作线程用于处理数据队列，如图13所示，该方法包括：
S1301，中断控制器获取第一中断请求信息。
中断控制器可以通过中断收集装置获取第一中断请求信息，该第一中断请求信息指示第一数据队列标识符。
中断控制器获取到第一中断请求信息后，由于中断控制器的中断收集装置中存储有中断-数据队列映射表，该中断-数据队列映射表可以由宿主机配置，该中断-数据队列映射表包括中断请求信息与数据队列标识符的对应关系，因此中断控制器可以根据第一中断请求信息确定该第一中断请求信息对应的第一数据队列标识符。
例如，该第一中断请求信息是由设备发送的，该第一中断请求信息中包括设备中断标识符，中断控制器可以根据设备中断标识符确定第一数据队列标识符。
再例如，该第一中断请求信息是由虚拟机发送的，该第一中断请求信息中包括虚拟机标识符和虚拟事件中断标识符，中断控制器可以根据虚拟机标识符和虚拟事件中断标识符确定第一数据队列标识符。
再例如，该第一中断请求是由处理器发送的，该第一中断请求信息中包括处理器标识符，中断控制 器可以根据处理器标识符确定第一数据队列标识符。
S1302，中断控制器向第一处理器发送第一中断通知。
对应的，第一处理器接收中断控制器发送的第一中断通知。
中断控制器可以向第一处理器发送第一中断通知并将第一数据队列标识符添加到第一存储器中，该第一存储器可以是第一处理器对应的中断投递装置的待处理寄存器，即如图6中的(a)所示，或该第一存储器可以是计算机设备的内存，即如图6中的(b)所示。
中断控制器可以通过以下几种方式向第一处理器发送第一中断通知。
一种可能的实现方式，中断控制器根据第一中断请求信息确定第一数据队列标识符后，将第一数据队列标识符添加到待处理数据队列。第一处理器通过第一工作线程访问其对应的中断交互装置的负载请求接口以发送第一负载请求信息，该第一负载请求信息用于请求数据队列标识符。中断控制器根据所述第一负载请求信息将第一处理器标识符或第一工作线程标识符添加到负载请求队列，其中第一处理器标识符用于指示第一处理器，第一工作线程标识符用于指示第一工作线程。
第一处理器可以通过工作线程访问其对应的中断交互装置的负载请求接口以发送第一负载请求信息，该第一负载请求信息包括第一处理器标识符，中断交互装置将第一处理器标识符添加到负载请求队列。
第一处理器可以通过工作线程访问其对应的中断交互装置的负载请求接口以发送第一负载请求信息，中断交互装置可以指示第一处理器对应的中断投递装置将线程标识符寄存器中的第一工作线程标识符添加到负载请求队列中。第一工作线程标识符用于指示运行在第一处理器的第一工作线程。
中断控制器可以根据负载请求队列和待处理数据队列确定第一处理器标识符和第一数据队列标识符。中断控制器确定第一处理器标识符后，即确定将第一数据队列标识符投递到第一处理器中，则中断控制器可以向第一处理器发送第一中断通知，并将第一数据队列标识符添加到第一存储器中。
示例性的，如图5中的(a)和(d)所示，中断控制器根据负载请求队列和待处理数据队列中确定处理器标识符和数据队列标识符，然后向处理器发送中断通知，并将数据队列标识符添加到待处理寄存器中，或添加到存储在计算机内存的处理器待处理队列中。
需要说明的是，在该种可能的实现方式中，中断控制器将第一数据队列标识符添加到待处理数据队列和第一处理器向中断控制器发送第一负载请求信息并没有实际的先后顺序。
进一步的，中断控制器包括工作线程路由表，该工作线程路由表指示工作线程与处理器标识符的对应关系，中断控制器根据第一负载请求信息将第一工作线程标识符添加到负载请求队列。中断控制器可以根据第一工作线程标识符和中断路由表确定该第一工作线程标识符对应的第一处理器标识符。中断控制器根据待处理数据队列确定第一数据队列标识符，并根据第一处理器标识符向第一处理器发送第一中断通知并将第一数据队列标识符添加到第一存储器中。
如图5中的(d)所示，中断控制器根据负载请求队列和待处理数据队列中确定工作线程标识符和数据队列标识符，然后根据工作线程标识符和工作线程路由表确定处理器标识符，然后根据处理器标识符向处理器发送中断通知，并将数据队列标识符添加到待处理寄存器中，或添加到存储在计算机内存的处理器待处理队列中。
一种可能的实现方式，中断控制器包括中断路由表，中断路由表用于指示数据队列标识符与处理器标识符的对应关系，中断控制器根据中断路由表和第一数据队列标识符确定第一处理器标识符，第一处理器标识符用于指示第一处理器。中断控制器，根据所述第一处理器标识符向第一处理器发送第一中断通知并将第一数据队列标识符添加到第一存储器中。
如图5中的(b)所示，中断控制器根据数据队列标识符和中断路由表确定处理器标识符，然后根据处理器标识符向处理器发送中断通知，并将数据队列标识符添加到待处理寄存器中，或添加到存储在计算机内存的处理器待处理队列中。
一种可能的实现方式，中断控制器包括中断路由表，中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，处理路由表地址用于指向处理器路由表，中断控制器根据中断路由表和第一数据队列标识符确定第一处理器路由表地址；中断控制器根据第一处理器路由表地址确定第一处理器索引和第一处理器路由表大小；中断控制器根据第一处理器索引和第一处理器路由表大小确定第一处理器标识符；中断控制器根据第一处理器标识符向第一处理器发送第一中断通知并将第一数据队列标识符添加到第一存储器中。
如图5中的(c)所示，中断控制器根据数据队列标识符和中断路由表确定处理器路由表地址，然后 根据处理器路由表地址确定处理器索引和路由表大小，并根据处理器索引和路由表大小确定处理器标识符，然后根据处理器标识符向处理器发送中断通知，并将数据队列标识符添加到待处理寄存器中，或添加到存储在计算机内存的处理器待处理队列中。
S1303，第一处理器向中断控制器发送第一中断处理请求。
对应的，中断控制器接收第一处理器发送的中断处理请求。
第一处理器接收到第一中断通知后，运行在第一处理器的第一工作线程可以响应该第一中断通知，并且通过工作线程访问第一中断交互装置的中断处理接口以发送第一中断处理请求。
S1304，中断控制器向第一处理器发送第一数据队列标识符。
对应的，第一处理器接收中断控制器发送的第一数据队列标识符。
中断控制器接收到中断处理请求后，中断控制器中的第一中断投递装置可以根据中断处理请求向第一处理器发送第一数据队列标识符，并在发送第一数据队列标识符后将第一数据队列标识符移出第一存储设备中。
S1305，第一处理器处理第一数据队列的数据。
第一处理器接收到第一数据队列标识符后，工作线程可以处理第一数据队列的数据，其中第一数据队列为第一数据队列标识符对应的数据队列。
可选的，在一些实施例中，该方法还包括：
若检测到第一数据队列中存在未处理的数据，第一处理器向中断控制器发送第一反补请求。
对应的，中断控制器接收第一处理器发送的第一反补请求。
第一处理器在处理数据队列中的数据时，处理的数据量是一定的，若检测到第一数据队列中还存在未处理的数据，第一处理器可以通过工作线程向中断控制器发送第一反补请求以指示中断控制器重新发送用于处理第一数据队列的中断通知。示例性的，若中断路由装置的结构如图5中的(a)和(d)所示，中断控制器接收到第一处理器发送的反补请求后，可以从第一中断投递装置中的正在处理寄存器中获取第一数据队列标识符，然后将第一数据队列标识符重新添加到待处理数据队列中，然后再路由分发该第一数据队列标识符。
可以理解的是，中断路由装置再次路由分发第一数据队列标识符时，可以向第一处理器发送，也可以向其他路由器发送。可选的，在一些实施中，第一工作线程注册有用户态中断，第一中断通知为用户态中断，则第一工作线程可以直接响应该第一中断通知。
可选的，在一些实施中，第一处理器运行有多个工作线程和空转工线程，该多个工作线程包括第一工线线程，当多个工作线程未处理数据队列中耳朵数据时，第一处理器可以空循环空转工作显示以使第一处理器处于用户态。
可选的，在一些实施中，第一处理器设置有第一用户态中断处理中标识位，第一用户态中断处理中标识位用于指示第一处理器是否正在处理用户态中断，第一处理器在处理第一数据队列的数据时，设置第一用户态中断处理中标识位以指示正在处理用户态中断。
上文介绍了本申请实施例提供的数据面处理方法，下面将结合图14详细介绍第一处理器处理数据的方法，图14示出了本申请实施例提供的数据处理方法的示意性流程图，如图14所示，该方法包括：
S1401，响应中断。
在一些实施例中，如图9中的(a)所示的数据面处理模型，运行在第一处理器的工作线程可以响应中断，该中断可以是用户态中断或内核态中断。
在一些实施例中，如图9中的(b)所示的数据面处理模型，运行在第一处理器的工作线程或空转工作线程可以响应中断。
进一步的，如图9中的(b)所示的数据面处理模型，工作线程和空转工作线程可以注册用户态中断，则可以在用户态直接响应用户态中断。在一些实施例中，空转工作线程可以执行空循环以使第一处理器运行在用户态，从而可以直接响应用户态中断。
可选的，在一些实施例中，第一处理器还包括用户态中断处理中标识位，该用户态中断处理中标识位用于指示第一处理器是否正在处理用户态中断。当工作线程或空转工作线程响应用户态中断时，第一处理器可以设置用户态中断处理中标识位以指示第一处理器正在处理用户态中断。
S1402，切换上下文。
工作线程或空转工作线程响应中断后，可以保存被中断线程的上下文并切换到中断处理上下文。
S1403，获取数据队列标识符。
工作线程或空转工作线程响应中断后，可以通过中断控制器获取数据队列标识符。
S1404，发送负载请求。
工作线程或空转工作线程响应中断且获取到数据队列标识符后，还可以发送负载请求信息以将下一个待处理的数据队列的数据队列标识符添加到第一处理器对应的第一中断投递装置的待处理寄存器中，或添加到处理器待处理队列中。
S1405，处理数据队列中的数据。
工作线程或空转工作线程调动驱动处理数据队列中的数据。示例性的，驱动可以是DPDK驱动、高性能存储开发包(storage performance development kit，SPDK)驱动等。
需要说明的是，本申请实施例对于处理数据队列中的数据的驱动不作任何限定，驱动可以是上文提到的DPDK驱动、SPDK驱动，还可以是其他用于处理数据队列中的数据的驱动。
S1406，判断数据队列中是否还有数据未处理。
工作线程或空转工作线程可以判断第一数据队列中是否还有数据未处理，若有数据未处理，则进行S1407，若未有数据未处理，则进行S1408。
S1407，发送反补请求。
工作线程或空转工作线程可以在判断第一数据队列中还有数据未处理时，向中断控制器发送反补请求。
S1408，判断是否存在待处理的数据队列。
工作线程或空转工作线程可以访问第一中断投递装置中的待处理寄存器，或访问处理器待处理队列以判断是否还有数据队列待处理，若还有数据队列待处理，则进行S1403，若未有数据队列待处理，则进行S1409。
S1409，切换上下文。
当工作线程或空转工作线程确定未有数据队列待处理时，可以由中断处理上下文切换到被中断线程的上下文以继续执行被中断的线程。
图15示出了本申请实施例提供的数据处理的方法的示意性流程图，该方法应用于计算机设备，计算机设备包括中断控制器、第二处理器以及第二存储器，该第二存储器用于存储待第二处理器处理的数据队列标识符，第二处理器运行有第二工作线程，第二工作线程用于处理数据队列中的数据，第二处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，所用户态中断待处理标识位可以指示第二处理器是否存在待处理的用户态中断，用户态中断使能标识位用于指述第二处理器是否允许处理用户态中断，如图15所示，该方法包括：
S1501，中断控制器获取第二中断请求信息。
该第二中断请求为用户态中断，该第二中断请求信息指示第二数据队列标识符，
S1502，中断控制器向第二处理器发送第二中断通知。
中断控制器向第二处理器发送第二中断通知并将第二数据队列标识符添加到第二存储器中。
应理解，针对S1501-S1502的描述可以参见针对S1301-S1302的描述，为了简洁，在此不再赘述。
S1503，第二处理器设置用户态中断待处理标识位和用户态中断使能位。
第二处理器接收到中断控制器发送的第二中断通知后，可以确定该第二中断请求为用户态中断，则可以设置用户态中断待处理标识位为第一状态和用户态中断使能标识位为第一状态以指示存在用户态中断待处理和可以处理用户态中断。
示例性的，用户态中断待处理标识位在未有用户态中断时的值可以为0，第二处理器接收到第二中断通知后，可以将用户态中断待处理标识位置1以指示存在用户态中断待处理。类似的，用户态中断使能标识位的初始状态的值为0，第二处理器接收到第二中断通知后，可以将用户态中断使能标识位置1以指示可以处理用户态中断。
S1504，第二处理器向中断控制器发送第二中断处理请求。
对应的，中断控制器接收第二处理器发送的第二中断处理请求。
第第二处理器确定存在用户态中断待处理，可以通过工作线程访问中断交互装置的中断处理接口以发送第二中断处理请求。
一种可能的实现方式，第二处理器配置第二工作线程以使第二工作线程轮询用户态中断待处理标识 位和用户态中断使能标识位，当用户态中断待处理标识位为第一状态和用户态中断使能标识位为第一状态的情况下，发送第二中断处理请求。S1505，中断控制器向第二处理器发送第二数据队列标识符。
对应的，第二处理器接收中断控制器发送的第二数据队列标识符。
中断控制器接收到中断处理请求后，中断控制器中的中断投递装置可以向第二处理器发送第二数据队列标识符，并将第二数据队列标识符移出第二存储器中。
S1506，第二处理器处理第二数据队列的数据。
第二处理器接收到第二数据队列标识符后，可以处理第二数据队列的数据，其中第二数据队列为第二数据队列标识符对应的数据队列。
可选的，在一些实施例中，该方法还包括：
若检测到第二数据队列中存在未处理的数据，第一处理器向中断控制器发送第二反补请求。
应理解，针对第二反补请求的描述，可以参见上文，为了简洁，在此不再赘述。
可选的，第二处理器设置有第二用户态中断处理中标识位，针对第二用户态中断处理中标识位的描述可以参见针对第一用户态中断处理器中标识位的描述，为了简洁，在此不再赘述。
可选的，在一些实施例中，第二处理器还运行有业务线程，该业务线程用于处理除数据队列以外的业务，工作线程的优先级高于业务线程的优先级，该计算机设备上还设置有阻塞标识位，阻塞标识位用于指示第二工作线程的状态，
第二处理器确定未有数据队列待处理时，将工作线程的状态调整为休眠状态以使该业务线程处理除处理数据队列以外的业务，并通过工作线程设置该阻塞标识位以指示该工作线程处于休眠状态。
上述主要从计算机设备的角度对本申请实施例提供的一种数据面处理的方法进行了介绍。可以理解的是，计算机设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例还提供了一种计算机设备，包括：一个或多个处理器、一个或多个存储器、中断控制器以及一个或多个计算机程序。上述各器件可以通过一个或多个通信总线连接。其中，该一个或多个计算机程序被存储在上述存储器中并被配置为被该一个或多个处理器执行，该一个或多个计算机程序包括指令，上述指令可以用于使得前文中任一种可能的实现方式中所述的数据面处理的方法被执行。
示例性的，上述处理器具体可以为图1所示的处理器110，上述存储器具体可以为图1所示的内部存储器120和/或与电子设备连接的外部存储器。
本申请实施例还提供一种芯片，所述芯片包括处理器和通信接口，所述通信接口用于接收信号，并将所述信号传输至所述处理器，所述处理器处理所述信号，使得如前文中任一种可能的实现方式中所述的数据面处理的方法被执行。
本实施例还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当该计算机指令在电子设备上运行时，使得电子设备执行上述相关方法步骤实现上述实施例中的数据面处理的方法。
本实施例还提供了一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行上述相关步骤，以实现上述实施例中的数据面处理的方法。
以上实施例中所用，根据上下文，术语“当…时”或“当…后”可以被解释为意思是“如果…”或“在…后”或“响应于确定…”或“响应于检测到…”。类似地，根据上下文，短语“在确定…时”或“如果检测到(所陈述的条件或事件)”可以被解释为意思是“如果确定…”或“响应于确定…”或“在检测到(所陈述的条件或事件)时”或“响应于检测到(所陈述的条件或事件)”。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (34)

  1. 一种数据处理的方法，所述方法应用于计算机设备，所述计算机设备包括中断控制器、处理器以及存储器，所述存储器用于存储数据队列标识符，所述处理器用于处理数据队列的数据，所述方法包括：
    所述中断控制器获取第一中断请求信息，所述第一中断请求信息指示第一数据队列标识符；
    所述中断控制器向所述处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中；
    所述处理器根据所述第一中断通知向所述中断控制器发送第一中断处理请求；
    所述中断控制器根据所述第一中断处理请求向所述处理器发送所述第一数据队列标识符并将所述第一数据队列标识符移出所述存储器；
    所述处理器处理所述第一数据队列的数据，所述第一数据队列为所述第一数据队列标识符对应的数据队列。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    所述处理器在检测到所述第一数据队列存在未处理的数据时向所述中断控制器发送第一反补请求，所述第一反补请求用于指示所述中断控制器重新发送用于处理所述第一数据队列的中断通知。
  3. 根据权利要求1或2所述的方法，其特征在于，所述计算机设备包括待处理数据队列，所述待处理数据队列用于存储所述第一数据队列标识符，在所述中断控制器向所述处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中之前，所述方法还包括：
    所述处理器向所述中断控制器发送第一负载请求信息；
    所述中断控制器根据所述第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，其中，所述处理器标识符用于指示所述处理器，所述第一工作线程标识符用于指示所述第一工作线程，所述第一工作线程运行于所述处理器。
  4. 根据权利要求3所述的方法，其特征在于，所述中断控制器包括工作线程路由表，所述工作线程路由表用于指示工作线程和处理器标识符的对应关系，所述中断控制器根据所述第一负载请求信息将处理器标识符或第一工作线程标识符添加到负载请求队列，包括：
    所述中断控制器根据所述第一负载请求信息将所述第一工作线程标识符添加到所述负载请求队列；
    所述中断控制器向所述处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述工作线程路由表和所述第一工作线程标识符确定所述处理器标识符；
    所述中断控制器从所述待处理数据队列得到所述第一数据队列标识符，并根据所述处理器标识符向所述处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  5. 根据权利要求1或2所述的方法，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器标识符的对应关系，所述中断控制器向所述处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述中断路由表和所述第一数据队列标识符确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器根据所述处理器标识符向所述处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  6. 根据权利要求1或2所述的方法，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，所述处理路由表地址用于指向处理器路由表，所述中断控制器向所述处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述中断路由表和所述第一数据队列标识符确定第一处理器路由表地址；
    所述中断控制器根据所述第一处理器路由表地址确定第一处理器索引和第一处理器路由表大小；
    所述中断控制器根据所述第一处理器索引和所述第一处理器路由表大小确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器根据所述处理器标识符向所述处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  7. 根据权利要求1至6中任一项所述的方法，其特征在于，所述方法还包括：所述第一工作线程注册有用户态中断，所述第一中断通知为用户态中断。
  8. 根据权利要求7所述的方法，其特征在于，所述处理器上运行多个工作线程和空转工作线程，所述空转工作线程注册有用户态中断，所述多个工作线程用于处理数据队列中的数据，所述多个工作线程包括所述第一工作线程，当所述多个工作线程未处理数据队列中的数据时，所述方法还包括：
    所述处理器空循环所述空转工作线程以使所述处理器处于用户态。
  9. 根据权利要求7或8所述的方法，其特征在于，所述处理器设置有第一用户态中断处理中标识位，所述第一用户态中断处理中标识位用于指示所述处理器是否正在处理用户态中断，所述方法还包括：
    所述处理器处理所述第一数据队列的数据时，设置所述第一用户态中断处理中标识位以指示正在处理用户态中断。
  10. 一种数据处理的方法，其特征在于，所述方法应用于计算机设备，所述计算机设备包括中断控制器、处理器以及存储器，所述存储器用于存储数据队列标识符，所述处理器运行有工作线程，所述工作线程用于处理数据队列中的数据，所述处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，所述用户态中断待处理标识位用于指示所述处理器是否存在待处理的用户态中断，所述用户态中断使能标识位用于指示所述处理器是否使能处理所述用户态中断，所述方法包括：
    所述中断控制器获取第二中断请求信息；
    所述中断控制器根据所述第二中断请求信息确定第二数据队列标识符；
    所述中断控制器向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中，所述第二中断通知为所述用户态中断；
    所述处理器根据所述第二中断通知设置所述用户态中断待处理标识位为所述用户态中断待处理标识位的第一状态，所述用户态中断待处理标识位的第一状态指示存在所述用户态中断待处理，以及设置所述用户态中断使能标识位为所述用户态中断使能标识位的第一状态，所述用户态中断使能标识位的第一状态指示所述处理器使能处理所述用户态中断；
    在存在用户态中断待处理的情况下，所述处理器向所述中断控制器发送第二中断处理请求；
    所述中断控制器根据所述第二中断处理请求向所述处理器发送所述第二数据队列标识符并将所述第二数据队列标识符移出所述存储器；
    所述处理器处理所述第二数据队列的数据，所述第二数据队列为所述第二数据队列标识符对应的数据队列。
  11. 根据权利要求10所述的方法，其特征在于，所述方法还包括：所述处理器在检测到第二数据队列存在未处理的数据时向所述中断控制器发送第二反补请求，所述第二反补请求用于指示中断控制器重新发送用于处理第二数据队列的中断通知。
  12. 根据权利要求10或11所述的方法，其特征在于，所述计算机设备包括待处理数据队列，所述待处理数据队列用于存储所述第二数据队列标识符，在所述中断控制器向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中之前，所述方法还包括：
    所述处理器向所述中断控制器发送第二负载请求信息；
    所述中断控制器根据所述第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，其中，所述处理器标识符用于指示所述处理器，所述第二工作线程标识符用于指示所述第二工作线程。
  13. 根据权利要求12所述的方法，其特征在于，所述中断控制器包括工作线程路由表，所述工作线程路由表用于指示工作线程和处理器标识符的对应关系，所述中断控制器根据所述第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，包括：
    所述中断控制器根据所述第二负载请求信息将所述第二工作线程标识符添加到所述负载请求队列；
    所述中断控制器向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述工作线程路由表和所述第二工作线程标识符确定所述处理器标识符；
    所述中断控制器从所述待处理数据队列得到所述第二数据队列标识符，并根据所述处理器标识符向所述处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述第二存储器中。
  14. 根据权利要求10或11所述的方法，其特征在于，所述中断控制器包括中断路由表，所述中断 路由表用于指示数据队列标识符与处理器标识符的对应关系，所述中断控制器向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述中断路由表和所述第二数据队列标识符确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器根据所述处理器标识符向所述处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述存储器中。
  15. 根据权利要求10或11所述的方法，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，所述处理路由表地址用于指向处理器路由表，所述中断控制器向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中，包括：
    所述中断控制器根据所述中断路由表和所述第二数据队列标识符确定第二处理器路由表地址；
    所述中断控制器根据所述第二处理器路由表地址确定第二处理器索引和第二处理器路由表大小；
    所述中断控制器根据所述第二处理器索引和所述第二处理器路由表大小确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器根据所述处理器标识符向所述处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述存储器中。
  16. 根据权利要求10至15中任一项所述的方法，其特征在于，所述处理器设置有第二用户态中断处理中标识位，所述第二用户态中断处理中标识位用于指示所述处理器是否正在处理用户态中断，所述方法还包括：
    所述处理器处理所述第二数据队列的数据时，设置所述第二用户态中断处理中标识位以指示正在处理用户态中断。
  17. 根据权利要求10至16中任一项所述的方法，其特征在于，所述处理器还运行有业务线程，所述业务线程用于处理除处理数据队列以外的业务，所述中断控制器设置有阻塞标识位，所述阻塞标识位用于指示所述第二工作线程的状态，所述方法还包括：
    所述处理器在确定未有所述数据队列处理时，将所述第二工作线程调整为休眠状态并设置所述阻塞标识位以指示所述第二工作线程的状态为所述休眠状态。
  18. 一种计算机设备，所述计算机设备包括中断控制器、处理器以及存储器，所述存储器用于存储数据队列标识符，所述处理器用于处理数据队列的数据，其中，
    所述中断控制器，用于获取第一中断请求信息，所述第一中断请求信息指示第一数据队列标识符；
    所述中断控制器，还用于向所述第一处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中；
    所述处理器，用于根据所述第一中断通知向所述中断控制器发送第一中断处理请求；
    所述中断控制器，还用于根据所述第一中断处理请求向所述处理器发送所述第一数据队列标识符并将所述第一数据队列标识符移出所述存储器；
    所述处理器，还用于处理所述第一数据队列的数据，所述第一数据队列为所述第一数据队列标识符对应的数据队列。
  19. 根据权利要求18所述的计算机设备，其特征在于，所述处理器，还用于在检测到第一数据队列存在未处理的数据时向所述中断控制器发送第一反补请求，所述第一反补请求用于指示所述中断控制器重新发送用于处理所述第一数据队列的中断通知。
  20. 根据权利要求18或19所述的计算机设备，其特征在于，所述计算机设备包括待处理数据队列，所述中断控制器，还用于将所述第一数据队列标识符添加到待处理数据队列；
    所述第一处理器，还用于在所述中断控制器向所述第一处理器发送第一中断通知并将所述第一数据队列标识符添加到所述存储器中之前，向所述中断控制器发送第一负载请求信息；
    所述中断控制器，还用于根据所述第一负载请求信息将第一处理器标识符或第一工作线程标识符添加到负载请求队列，其中所述第一处理器标识符用于指示所述第一处理器，所述第一工作线程标识符用于指示所述第一工作线程；
    所述中断控制器，具体用于根据所述负载请求队列和所述待处理数据队列确定所述第一处理器标识符和所述第一数据队列标识符，并根据所述第一处理器标识符向所述第一处理器发送所述第一中断通知 并将所述第一数据队列标识符添加到所述存储器中。
  21. 根据权利要求20所述的计算机设备，其特征在于，所述中断控制器包括工作线程路由表，所述工作线程路由表用于指示工作线程和处理器标识符的对应关系，其中，
    所述中断控制器，具体用于根据所述第一负载请求信息将所述第一工作线程标识符添加到所述负载请求队列；
    所述中断控制器，还用于根据所述工作线程路由表和所述第一工作线程标识符确定所述第一处理器标识符；
    所述中断控制器，具体用于根据所述待处理数据队列确定所述第一数据队列标识符，并根据所述第一处理器标识符向所述第一处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  22. 根据权利要求18或19所述的计算机设备，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器标识符的对应关系，其中，
    所述中断控制器，还用于根据所述中断路由表和所述第一数据队列标识符确定处理器标识符，所述处理器标识符用于指示所述第一处理器；
    所述中断控制器，具体用于根据所述处理器标识符向所述处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  23. 根据权利要求18或19所述的计算机设备，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，所述处理路由表地址用于指向处理器路由表，其中，
    所述中断控制器，还用于根据所述中断路由表和所述第一数据队列标识符确定第一处理器路由表地址；
    所述中断控制器，还用于根据所述第一处理器路由表地址确定第一处理器索引和第一处理器路由表大小；
    所述中断控制器，还用于根据所述第一处理器索引和所述第一处理器路由表大小确定处理器标识符，所述处理器标识符用于指示所述第一处理器；
    所述中断控制器，具体用于根据所述处理器标识符向所述处理器发送所述第一中断通知并将所述第一数据队列标识符添加到所述存储器中。
  24. 根据权利要求18至23中任一项所述的计算机设备，其特征在于，所述第一工作线程注册有用户态中断，所述第一中断通知为用户态中断。
  25. 根据权利要求24所述的计算机设备，其特征在于，所述处理器上运行多个工作线程和空转工作线程，所述空转工作线程注册有用户态中断，所述多个工作线程用于处理数据队列中的数据，所述多个工作线程包括所述第一工作线程，当所述多个工作线程未处理数据队列中的数据时，所述第处理器，还用于空循环所述空转工作线程以使所述第一处理器处于用户态。
  26. 根据权利要求24或25所述的计算机设备，其特征在于，所述处理器设置有第一用户态中断处理中标识位，所述第一用户态中断处理中标识位用于指示所述处理器是否正在处理用户态中断，所述处理器，还用于处理所述第一数据队列的数据时，设置所述第一用户态中断处理中标识位以指示正在处理用户态中断。
  27. 一种计算机设备，所述计算机设备包括中断控制器、处理器以及存储器，所述存储器用于数据队列标识符，所述处理器运行有第二工作线程，所述第二工作线程用于处理数据队列中的数据，所述处理器中设置有用户态中断待处理标识位和用户态中断使能标识位，所述用户态中断待处理标识位用于指示所述处理器是否存在待处理的用户态中断，所述用户态中断使能标识位用于指示所述处理器是否使能处理所述用户态中断，其中，
    所述中断控制器，用于获取第二中断请求信息，所述第二中断请求信息指示第二数据队列标识符；
    所述中断控制器，还用于向所述处理器发送第二中断通知并将所述第二数据队列标识符添加到所述存储器中，所述第二中断通知为所述用户态中断；
    所述处理器，用于根据所述第二中断通知设置所述用户态中断待处理标识位为所述用户态中断待处理标识位的第一状态，所述用户态中断待处理标识位的第一状态指示存在所述用户态中断待处理，以及设置所述用户态中断使能标识位为所述用户态中断使能标识位的第一状态，所述用户态中断使能标识位 的第一状态指示所述处理器使能处理所述用户态中断；
    在存在用户态中断待处理的情况下，所述处理器，还用于向所述中断控制器发送第二中断处理请求；
    所述中断控制器，还用于根据所述第二中断处理请求向所述处理器发送所述第二数据队列标识符并将所述第二数据队列标识符移出所述存储器；
    所述处理器，还用于处理所述第二数据队列的数据，所述第二数据队列为所述第二数据队列标识符对应的数据队列。
  28. 根据权利要求27所述的计算机设备，其特征在于，处理器，还用于在检测到第二数据队列存在未处理的数据时向所述中断控制器发送第二反补请求以指示中断控制器重新发送用于处理第二数据队列的中断通知。
  29. 根据权利要求27或28所述的计算机设备，其特征在于，所述中断控制器，还用于将所述第二数据队列标识符添加到待处理数据队列；
    所述处理器，还用于向所述中断控制器发送第二负载请求信息；
    所述中断控制器，还用于根据所述第二负载请求信息将处理器标识符或第二工作线程标识符添加到负载请求队列，其中所述处理器标识符用于指示所述处理器，所述第二工作线程标识符用于指示所述第二工作线程；
    所述中断控制器，具体用于根据所述负载请求队列和所述待处理数据队列向所述第一处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述存储器中。
  30. 根据权利要求29所述的计算机设备，其特征在于，所述中断控制器包括工作线程路由表，所述工作线程路由表用于指示工作线程和处理器标识符的对应关系，其中，
    所述中断控制器，具体用于根据所述第二负载请求信息将所述第二工作线程标识符添加到所述负载请求队列；
    所述中断控制器，还用于根据所述工作线程路由表和所述第二工作线程标识符确定所述处理器标识符。
  31. 根据权利要求27或28所述的计算机设备，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器标识符的对应关系，其中，
    所述中断控制器，还用于根据所述中断路由表和所述第二数据队列标识符确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器，具体用于根据所述处理器标识符向所述处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述存储器中。
  32. 根据权利要求27或28所述的计算机设备，其特征在于，所述中断控制器包括中断路由表，所述中断路由表用于指示数据队列标识符与处理器路由表地址的对应关系，所述处理路由表地址用于指向处理器路由表，其中，
    所述中断控制器，还用于根据所述中断路由表和所述第二数据队列标识符确定第二处理器路由表地址；
    所述中断控制器，还用于根据所述第二处理器路由表地址确定第二处理器索引和第二处理器路由表大小；
    所述中断控制器，还用于根据所述第二处理器索引和所述第二处理器路由表大小确定处理器标识符，所述处理器标识符用于指示所述处理器；
    所述中断控制器，具体用于根据所述处理器标识符向所述处理器发送所述第二中断通知并将所述第二数据队列标识符添加到所述存储器中。
  33. 根据权利要求27至32中任一项所述的计算机设备，其特征在于，所述处理器设置有第二用户态中断处理中标识位，所述第二用户态中断处理中标识位用于指示所述处理器是否正在处理用户态中断，所述处理器，还用于处理所述第二数据队列的数据时，设置所述第二用户态中断处理中标识位以指示正在处理用户态中断。
  34. 根据权利要求27至33中任一项所述的计算机设备，其特征在于，所述处理器还运行有业务线程，所述业务线程用于处理除处理数据队列以外的业务，所述中断控制器设置有阻塞标识位，所述阻塞标识位用于指示所述第二工作线程的状态，其中，
    所述处理器，还用于在确定未有所述数据队列处理时，将所述第二工作线程调整为休眠状态并设置 所述阻塞标识位以指示所述第二工作线程的状态为所述休眠状态。
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