WO2024109434A1

WO2024109434A1 - Gan device packaging structure and packaging method therefor

Info

Publication number: WO2024109434A1
Application number: PCT/CN2023/126707
Authority: WO
Inventors: 杨洋
Original assignee: 无锡华润华晶微电子有限公司
Priority date: 2022-11-25
Filing date: 2023-10-26
Publication date: 2024-05-30
Also published as: CN118099152A

Abstract

The present invention provides a GaN device packaging structure and a packaging method therefor. The GaN device packaging structure comprises a packaging substrate, a chip layer, a conductive clip, a solder layer, and a packaging layer, wherein the packaging substrate comprises a dielectric layer, a conductive layer, and a conductive pillar, and the conductive layer located on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region; the chip layer is located above the packaging substrate and comprises a GaN HEMT chip and a MOS chip arranged at an interval, and the front surfaces of the GaN HEMT chip and the MOS chip are each provided with a first gate, a first source, a first drain, a second gate, and a second source which are respectively electrically connected to the corresponding electrode region of the conductive layer by means of the solder layer; the conductive clip is electrically connected to the cascade electrode region and the second drain by means of the solder layer; the packaging layer covers the exposed surface of the chip layer. According to the present invention, a device electrode is led out by combining the packaging substrate and the conductive clip, thereby improving the heat dissipation capability and the current capability of the packaging structure.

Description

A GaN device packaging structure and packaging method thereof

Technical Field

The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a GaN device packaging structure and a packaging method thereof.

Background technique

Power semiconductors are the core components of power electronics power conversion and circuit control. In recent years, power devices such as metal oxide semiconductor field effect transistors (MOSFET) have developed rapidly towards high power density, but silicon-based devices have their upper limit. Since the third-generation semiconductor gallium nitride (GaN) has the characteristics of high breakdown electric field, high saturation electron velocity, high thermal conductivity, high electron density, and high mobility, it has broad application prospects in the field of high temperature, high voltage, high frequency and high power electronic power devices.

GaN high electron mobility transistor (HEMT) devices are one of the future development directions to replace silicon-based MOSFETs due to their high power conversion efficiency. Currently, there are two development directions: enhancement-mode GaN HEMT and depletion-mode GaN HEMT. The enhancement-mode GaN HEMT has a low threshold (VTH), which may cause false start-up and low reliability in actual use. Although the depletion-mode GaN HEMT has high reliability, it is a normally-on device and cannot be used in actual circuits. It needs to be matched with a low-voltage silicon-based MOSFET (hereinafter referred to as MOS) to form a common-source and common-gate cascade structure (Cascode) GaN device to meet actual use.

At present, the packaging of GaN devices with a common source and common gate cascade structure (Cascode) is usually packaged by wire bonding packaging. As shown in Figure 1, it is a schematic diagram of the packaging structure of GaN devices with wire bonding packaging, including substrate 01, dielectric layer 011, conductive layer 012, chip layer 02, GaN HEMT chip 021, MOS chip 022 and metal leads 03. However, during the packaging process, the precision of the wire bonding process is low, which does not meet the requirements of some high-reliability application environments, and the packaging resistance of the packaged structure after packaging is high, which is not suitable for high-current use environments. Its heat dissipation performance is also poor, which does not meet the heat dissipation requirements of high-power devices. In addition, due to the large number of metal leads and their dense distribution, the packaging structure of the wire bonding package has high inductance and mutual inductance, which cannot be used at high frequencies, affecting the working efficiency of the entire machine.

Therefore, there is an urgent need to find a GaN device packaging structure that improves the reliability of the packaging structure and reduces the packaging resistance, inductance and mutual inductance of the packaging structure.

Summary of the invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a GaN device packaging structure and a packaging method thereof, so as to solve the problems of low process precision, high packaging resistance, high inductance and high mutual inductance of the GaN device packaging structure in the prior art.

To achieve the above objectives and other related objectives, the present invention provides a GaN device packaging structure, including:

A packaging substrate, comprising a dielectric layer, conductive layers located on the upper and lower surfaces of the dielectric layer, and conductive pillars penetrating the dielectric layer and electrically connected to the conductive layer, wherein the conductive layer located on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region;

a chip layer, located above the packaging substrate, comprising at least one GaN HEMT chip and at least one MOS chip arranged at intervals, wherein the front side of the GaN HEMT chip is provided with a first gate located above the first gate region, a first source located above the cascade electrode region, and a first drain located above the drain region, the front side of the MOS chip is provided with a second gate located above the second gate region, a second source located above the source region, and a second drain located at the back side of the MOS chip;

A conductive clip, two ends of which are located above the second drain and the cascade electrode region;

The welding layers are respectively located between the first gate region and the first gate, the cascade electrode region and the first source, the first drain and the drain region, the second gate region and the second gate, the source region and the second source, the second drain and the conductive clip, and the conductive clip and the cascade electrode region, and form an electrical connection structure;

The packaging layer covers the chip layer and the exposed surface of the packaging substrate.

Optionally, the packaging substrate includes a direct copper-bonded ceramic substrate or a direct copper-plated ceramic substrate.

Optionally, the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region and a third electrode region.

Optionally, the first gate region is electrically connected to the first electrode region through the conductive column, the source region is electrically connected to the first electrode region through the conductive column, the first drain region is electrically connected to the second electrode region through the conductive column, and the second gate region is electrically connected to the third electrode region through the conductive column.

Optionally, the material of the welding layer includes at least one of gold, silver, tin, lead and indium.

Optionally, the GaN HEMT chip is also provided with integrated passive devices and lead-out electrodes for leading out the passive devices; and the conductive layer on the upper surface of the dielectric layer is also provided with a transfer electrode area.

Optionally, the welding layer is provided on the upper surface of the transfer electrode area, the conductive clip is located above the welding layer on the transfer electrode area, the lead-out electrode is located above the welding layer on the transfer electrode area, and the conductive clip forms an electrical connection structure with the lead-out electrode through the welding layer and the transfer electrode area.

The present invention also provides a packaging method for a GaN device packaging structure, comprising the following steps:

A packaging substrate is provided, the packaging substrate comprising a dielectric layer, conductive layers located on the upper and lower surfaces of the dielectric layer, and conductive pillars penetrating the dielectric layer and electrically connected to the conductive layer, the conductive layer located on the upper surface of the dielectric layer comprising a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region;

A chip layer is provided, wherein the chip layer includes at least one GaN HEMT chip and at least one MOS chip, wherein the front surface of the GaN HEMT chip is provided with a first gate, a first source and a first drain, and the front surface of the MOS chip is provided with a second gate. A second drain is provided on the back of the MOS chip;

forming a welding layer on the upper surfaces of the first gate region, the source region, the drain region, the second gate region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain;

The GaN HEMT chip and the MOS chip are placed on the upper surface of the packaging substrate at intervals, the first gate is located above the welding layer on the first gate region, the first source is located above the welding layer on the cascade electrode region, the first drain is located above the welding layer on the drain region, the second gate is located above the welding layer on the second gate region, and the second source is located above the welding layer on the source region;

forming a conductive clip above the MOS chip, with two ends respectively located above the second drain and the welding layer on the cascade electrode region, and processing the packaging structure after forming the conductive clip to form an electrical connection structure;

A packaging layer is formed to cover the upper surface of the packaging substrate and the exposed surface of the chip layer.

Optionally, the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region and a third electrode region, the first gate region is electrically connected to the first electrode region through the conductive column, the source region is electrically connected to the first electrode region through the conductive column, the drain region is electrically connected to the second electrode region through the conductive column, and the second gate region is electrically connected to the third electrode region through the conductive column.

Optionally, the GaN HEMT chip is further provided with integrated passive devices and lead-out electrodes for leading out passive devices; a transfer electrode area is further provided in the conductive layer on the upper surface of the dielectric layer, the welding layer is formed on the upper surface of the transfer electrode area, the conductive clip is in contact with the upper surface of the welding layer on the transfer electrode area, the lead-out electrode is in contact with the upper surface of the welding layer on the transfer electrode area, and the conductive clip forms an electrical connection structure with the lead-out electrode through the welding layer and the transfer electrode area.

As described above, the GaN device packaging structure and packaging method of the present invention lead out the electrodes of the packaging structure through the combination of the packaging substrate and the conductive clip, and use the conductive clip to replace the metal lead, thereby avoiding the bonding damage and cold welding caused by the wire bonding packaging process, reducing the packaging resistance of the packaging structure, and improving the current capacity and reliability of the device. At the same time, there is no need to weld dense metal leads, reducing the inductance and mutual inductance of the packaging structure, and improving the application frequency of the packaging structure, so that the packaging structure meets the working requirements of the high-frequency application end, and improves the working efficiency of the application end. In addition, since the heating area of the chip layer is in close contact with the conductive layer on the upper surface of the dielectric layer, the thermal conductivity of the conductive layer and the dielectric layer is higher than that of the packaging layer, which improves the heat dissipation capacity of the packaging structure. In addition, during the packaging process, the welding layer is formed on the exposed surface of each electrode of the chip layer and the upper surface of the first gate region, the source region, the drain region, the second gate region and the cascade electrode region, respectively, and the welding layer is used to achieve the effect of automatic alignment after curing, so as to realize high-precision packaging, and the welding layer is formed on the two contact surfaces at the electrical connection, which reduces the curing process of the welding layer. The welding voids in the packaging structure are reduced, which reduces the packaging stress during the packaging process. Since the packaging substrate leads the electrodes of the packaging structure to the lower surface of the packaging substrate through the conductive pillars, it is compatible with patch packaging. The size of the packaging structure and the position of the electrodes on the lower surface of the packaging substrate can be adjusted according to the client's needs, which meets the needs of the client and has high industrial utilization value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a GaN device packaging structure of a wire bonding package in the prior art.

FIG. 2 is a process flow chart showing a packaging method of a GaN device packaging structure of the present invention.

FIG. 3 is a schematic diagram showing the three-dimensional structure of a packaging substrate of a packaging method for a GaN device packaging structure of the present invention.

FIG. 4 is a schematic diagram showing a cross-sectional structure of a packaging substrate along the Y direction in a packaging method of a GaN device packaging structure of the present invention.

FIG. 5 is a schematic structural diagram of a dielectric layer of a packaging method for a GaN device packaging structure of the present invention.

FIG. 6 is a schematic structural diagram showing the upper surface of a packaging substrate in a packaging method for a GaN device packaging structure of the present invention.

FIG. 7 is a schematic structural diagram showing the lower surface of a packaging substrate in a packaging method for a GaN device packaging structure of the present invention.

FIG. 8 is a schematic structural diagram showing a packaging method of a GaN device packaging structure according to the present invention after a welding layer is formed on the upper surface of a packaging substrate.

FIG. 9 is a schematic diagram showing a cross-sectional structure along the Y direction after a welding layer is formed on the upper surface of a packaging substrate in the packaging method of the GaN device packaging structure of the present invention.

FIG. 10 is a schematic structural diagram showing a packaging method of a GaN device packaging structure according to the present invention after a welding layer is formed on the exposed surface of the second drain electrode.

FIG. 11 is a schematic diagram showing a cross-sectional structure along the Y direction after a welding layer is formed on the exposed surface of the second drain electrode in the packaging method of the GaN device packaging structure of the present invention.

FIG. 12 is a schematic structural diagram showing a packaging method of a GaN device packaging structure of the present invention after forming a conductive clip.

FIG. 13 is a schematic diagram showing a cross-sectional structure along the Y direction after forming a conductive clip in the packaging method of the GaN device packaging structure of the present invention.

FIG. 14 is a schematic diagram showing a cross-sectional structure along the X direction after forming a conductive clip in the packaging method of the GaN device packaging structure of the present invention.

FIG. 15 is a schematic structural diagram showing a packaging method of a GaN device packaging structure of the present invention after forming a packaging layer.

Description of Figure Numbers
01 Substrate
011 Dielectric layer
012 Conductive layer
02 Chip layer
021 GaN HEMT chip
022 MOS chip
03 Metal lead
1 Package substrate
11 Dielectric layer
12 Conductive layer
121 first gate region
122 Source region
123 Drain region
124 second gate region
125 Cascade electrode area
13 Conductive column
14 Through Holes
15. First electrode region
16. Second electrode area
17. Third electrode area
18 Transfer electrode area
2 Chip layer
21 GaN HEMT chip
22 MOS chip
3 Conductive clip
4 Welding layer
5 Encapsulation layer

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can understand the present invention from the disclosure of this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figures 2 to 15. It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the drawings only show components related to the present invention rather than the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

Embodiment 1

This embodiment provides a packaging method for a GaN device packaging structure, as shown in FIG2 , which is a process flow chart of the packaging method for the GaN device packaging structure, including the following steps:

S1: providing a packaging substrate, the packaging substrate comprising a dielectric layer, conductive layers located on the upper and lower surfaces of the dielectric layer, and conductive pillars penetrating the dielectric layer and electrically connected to the conductive layer, the conductive layer located on the upper surface of the dielectric layer comprising a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region;

S2: providing a chip layer, the chip layer comprising at least one GaN HEMT chip and at least one MOS chip, the front side of the GaN HEMT chip being provided with a first gate, a first source and a first drain, the front side of the MOS chip being provided with a second gate and a second source, and the back side of the MOS chip being provided with a second drain;

S3: forming a welding layer on the upper surfaces of the first gate region, the source region, the drain region, the second gate region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain;

S4: placing the GaN HEMT chip and the MOS chip on the upper surface of the packaging substrate at intervals, the first gate is located above the welding layer on the first gate region, the first source is located above the welding layer on the cascade electrode region, the first drain is located above the welding layer on the drain region, the second gate is located above the welding layer on the second gate region, and the second source is located above the welding layer on the source region;

S5: forming a conductive clip above the MOS chip with two opposite ends respectively located above the second drain and the welding layer on the cascade electrode region, and processing the packaging structure after the conductive clip is formed to form an electrical connection structure;

S6: forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer.

Please refer to FIG. 3 to FIG. 7 , and perform the step S1 and the step S2: provide a package substrate 1, the package substrate 1 includes a dielectric layer 11, a conductive layer 12 located on the upper and lower surfaces of the dielectric layer 11, and a conductive layer 12 penetrating the dielectric layer 11 and connected to the conductive layer 12. The present invention relates to a method for manufacturing a semiconductor device for manufacturing a semiconductor device for manufacturing a semiconductor device of the present invention. The method comprises: providing a conductive column electrically connected to the conductive layer 12, wherein the conductive layer 12 located on the upper surface of the dielectric layer 11 comprises a first gate region 121, a source region 122, a drain region 123, a second gate region 124, and a cascade electrode region 125; and providing a chip layer, wherein the chip layer comprises at least one GaN HEMT chip 21 and at least one MOS chip 22, wherein the front side of the GaN HEMT chip 21 is provided with a first gate, a first source and a first drain, the front side of the MOS chip 22 is provided with a second gate and a second source, and the back side of the MOS chip 22 is provided with a second drain.

Specifically, as shown in Figures 3 and 4, they are respectively a schematic diagram of the three-dimensional structure of the packaging substrate 4 and a schematic diagram of the cross-sectional structure of the packaging substrate 1 along the Y direction. The packaging substrate 1 includes a direct copper-clad ceramic substrate, a direct copper-plated ceramic substrate or other suitable substrates.

Specifically, as shown in FIG. 5 , it is a schematic diagram of the structure of the dielectric layer 11 . The material of the dielectric layer 11 includes ceramic or other suitable dielectric materials.

Specifically, as shown in FIG6 and FIG7, which are schematic diagrams of the structure of the upper surface of the package substrate 1 and the schematic diagram of the structure of the lower surface of the package substrate 1, respectively, the material of the conductive layer 12 includes copper, gold, silver, titanium or other suitable conductive materials, that is, the material of the first gate region 121 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the source region 122 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the drain region 123 includes copper, gold, silver, titanium or other suitable conductive materials, the material of the second gate region 124 includes copper, gold, silver, titanium or other suitable conductive materials, and the material of the cascade electrode region 125 includes copper, gold, silver, titanium or other suitable conductive materials. In this embodiment, a copper layer is used as the conductive layer 12.

As an example, the conductive layer 12 located on the lower surface of the dielectric layer 11 includes a first electrode region 15, a second electrode region 16 and a third electrode region 17, the first gate region 121 is electrically connected to the first electrode region 15 through the conductive column 13, the source region 122 is electrically connected to the first electrode region 15 through the conductive column 13, the drain region 123 is electrically connected to the second electrode region 16 through the conductive column 13, and the second gate region 124 is electrically connected to the third electrode region 17 through the conductive column 13.

Specifically, under the condition of ensuring the performance of the packaging structure, the number of the conductive pillars 13 electrically connecting the first electrode area 15 and the first gate area 121 can be selected according to actual conditions and is no longer restricted here; the number of the conductive pillars 13 electrically connecting the source area 122 and the first electrode area 15 can be selected according to actual conditions and is no longer restricted here; the number of the conductive pillars 13 electrically connecting the second electrode area 16 and the drain area 123 can be selected according to actual conditions and is no longer restricted here; the number of the conductive pillars 13 electrically connecting the third electrode area 17 and the second gate area 124 can be selected according to actual conditions and is no longer restricted here.

Specifically, under the condition of ensuring the performance of the packaging structure, the transverse cross-sectional size and transverse cross-sectional shape of the conductive pillar 13 can be selected according to actual conditions, and no limitation is imposed here. The transverse cross-sectional area here refers to the area parallel to the lower surface of the dielectric layer. cross section.

Specifically, the material of the first gate includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the first source includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the first drain includes gold, titanium, nickel, silver, copper or other suitable conductive materials.

Specifically, the material of the second gate includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the second source includes gold, titanium, nickel, silver, copper or other suitable conductive materials; the material of the second drain includes gold, titanium, nickel, silver, copper or other suitable conductive materials.

Please refer to Figures 8 to 14 again, and perform the steps S3, S4 and S5: forming a welding layer 4 on the upper surfaces of the first gate area 121, the source area 122, the drain area 123, the second gate area 124 and the cascade electrode area 125, and forming the welding layer 4 on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain; placing the GaN HEMT chip 21 and the MOS chip 22 on the upper surface of the packaging substrate 1 at intervals, with the first gate located in the first gate area 121. The first source is located above the welding layer 4 on the cascade electrode area 125, the first drain is located above the welding layer 4 on the drain area 123, the second gate is located above the welding layer 4 on the second gate area 124, and the second source is located above the welding layer 4 on the source area 122; a conductive clip 3 is formed above the MOS chip 22, with its two ends respectively located above the second drain and the welding layer 4 on the cascade electrode area 125, and the packaging structure after the conductive clip 3 is formed is processed to form an electrical connection structure.

Specifically, before forming the welding layer 4 on the packaging substrate 1 , the packaging substrate 1 needs to be placed in a dedicated fixture to facilitate process operations.

Specifically, as shown in Figures 8 and 9, they are respectively a schematic diagram of the structure after the welding layer 4 is formed on the packaging substrate 1 and a schematic diagram of the cross-sectional structure along the Y direction after the welding layer 4 is formed on the packaging substrate 1. The method of forming the welding layer 4 includes coating or other suitable methods.

Specifically, as shown in Figures 10 and 11, they are respectively a schematic diagram of the structure after the welding layer 4 is formed on the exposed surface of the second drain and a schematic diagram of the cross-sectional structure along the Y direction after the welding layer 4 is formed on the exposed surface of the second drain. The formation of the welding layer 4 includes the following steps: forming the welding layer 4 on the upper surfaces of the first gate region 121, the source region 122, the drain region 123, the second gate region 124 and the cascade electrode region 125; forming the welding layer 4 on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain, respectively, and placing the GaN HEMT chip 21 and the MOS chip 22 at corresponding positions of the packaging substrate 1, respectively.

Specifically, the method of placing the GaN HEMT chip 21 on the packaging substrate 1 includes manual placement, machine placement or other suitable placement methods; the method of placing the MOS chip 22 on the packaging substrate 1 includes manual placement, machine placement or other suitable placement methods.

Specifically, as shown in Figures 12, 13 and 14, they are respectively a schematic diagram of the structure after the conductive clip 3 is formed, a schematic diagram of the cross-sectional structure along the Y direction after the conductive clip 3 is formed, and a schematic diagram of the cross-sectional structure along the X direction after the conductive clip 3 is formed. The method of placing the conductive clip 3 above the welding layer 4 on the second drain and the cascade electrode area 125 includes manual placement, machine placement or other suitable placement methods.

Specifically, since the welding layer 4 is formed on the upper surfaces of the first gate region 121, the source region 122, the drain region 123, the second gate region 124 and the cascade electrode region 125, the welding layer 4 is also formed on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain, that is, the welding layer 4 is formed on the conductive layer 12 and the GaN HEMT chip 21 and the MOS chip 22. Placing the chip layer 2 (that is, the GaN HEMT chip 21 and the MOS chip 22) at corresponding positions of the packaging substrate 1 and curing the welding layer 4 can achieve the characteristics of self-alignment effect and realize high-precision packaging.

As an example, the GaN HEMT chip 21 is also provided with an integrated passive device (not shown) and a lead-out electrode (not shown) for leading out the passive device; a transfer electrode area 18 is also provided in the conductive layer 12 on the upper surface of the dielectric layer 11, the welding layer 4 is formed on the upper surface of the transfer electrode area 18, the conductive clip 3 is in contact with the upper surface of the welding layer 4 on the transfer electrode area 18, the lead-out electrode is in contact with the upper surface of the welding layer 4 on the transfer electrode area 18, and the conductive clip 3 forms an electrical connection structure with the lead-out electrode through the welding layer 4 and the transfer electrode area 18.

Specifically, after the welding layer 4 is formed on the upper surface of the transfer electrode area 18 and the exposed surface of the lead-out electrode, the GaN HEMT chip 21 is placed on the packaging substrate 1.

Specifically, the transfer electrode area 18 is spaced apart from the cascade electrode area 125 by a preset distance, and the distance between the transfer electrode area 18 and the cascade electrode area 125 can be selected according to actual conditions while ensuring the performance of the packaged device, and is not limited here.

Specifically, the switching electrode region 18 and the cascade electrode region 125 are only attached to the upper surface of the dielectric layer 11 , and are not electrically connected to the conductive layer 12 on the lower surface of the dielectric layer 11 .

As an example, a method for processing the packaging structure after forming the conductive clip 3 includes reflow soldering, curing or other suitable methods.

Specifically, the packaging structure after the conductive clip 3 is formed is processed so that the first gate forms a firm electrical connection structure with the first gate region 121 through the welding layer 4, the first source forms a firm electrical connection structure with the cascade electrode region 125 through the welding layer 4, and the first drain forms a firm electrical connection structure with the drain region 125 through the welding layer 4. 123 forms a firm electrical connection structure, the second gate forms a firm electrical connection structure with the second gate region 124 through the welding layer 4, the second source forms a firm electrical connection structure with the source region 122 through the welding layer 4, and the conductive clip 3 forms a firm electrical connection structure with the second drain and the cascade electrode region 125 through the welding layer 4.

Please refer to FIG. 15 , the step S6 is performed: forming a packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer 2 .

Specifically, the method of forming the encapsulation layer 5 includes coating or other suitable methods.

Specifically, the exposed surface of the dielectric layer 11 is further provided with a through hole 14 penetrating the dielectric layer 11 , that is, the through hole 14 is located in the area not covered by the chip layer 2 , the conductive layer 12 and the conductive clip 3 .

Specifically, under the condition of ensuring the performance of the packaging structure, the opening size and shape of the through hole 14 can be selected according to actual conditions and are not limited here.

Specifically, while the packaging layer 5 covering the upper surface of the packaging substrate and the exposed surface of the chip layer 2 is formed, since the packaging layer 5 is in a flowing liquid state, the packaging layer 5 fills the through hole 14 and flows into the gap between the lower surface of the packaging substrate 1 and the process platform through the through hole 14, that is, the packaging layer 5 covers the exposed surface of the lower surface of the dielectric layer 11, and the packaging layer 5 connected as a whole is formed on both sides, thereby improving the airtightness and reliability of the packaging.

Specifically, after the encapsulation layer 5 is formed, a curing step is also included.

Specifically, after the packaging layer 5 is cured, a step is also included to form an anti-oxidation layer (not shown) on the exposed surface of the conductive layer 12 located on the lower surface of the dielectric layer 11 to prevent the exposed conductive layer 12 from oxidizing and affecting the performance of the packaging structure, while facilitating welding by the client.

Specifically, the packaging structure after the anti-oxidation layer is formed is diced and trimmed to separate the packaging structure into individual GaN device packaging structures, and the appearance is trimmed to remove appearance problems caused by dicing or packaging. In this embodiment, the redundant packaging layer 5 in the GaN device packaging structure is mainly removed.

Specifically, the method of forming the anti-oxidation layer includes tin plating or other suitable methods.

Specifically, the method of slicing the packaging structure forming the anti-oxidation layer includes mechanical cutting, laser cutting or other suitable methods.

Specifically, after the GaN device packaging structure is formed, the method further includes the steps of testing the GaN device packaging structure and packaging the GaN device packaging structure that passes the test.

Specifically, since testing the package structure and packaging the package structure that passes the test are conventional process steps, they will not be described in detail here.

Specifically, since the thermal conductivity of the dielectric layer 11 is high, the thermal conductivity of the conductive layer 12 is also high. The heat generating area of the chip layer 2 is in close contact with the conductive layer 11, thereby improving the heat dissipation capability of the packaging structure.

Specifically, during the packaging process, the welding layer 4 is formed on both contact surfaces at the electrical connection, thereby reducing welding voids during the solidification process of the welding layer 4 and reducing packaging stress during the packaging process.

Specifically, since the packaging substrate 1 leads the electrodes of the packaging structure to the lower surface of the packaging substrate 1 through the conductive pillars 13, it is compatible with patch-type packaging, and the size of the packaging structure and the position of the electrodes located on the lower surface of the packaging substrate can be adjusted according to client needs, thereby meeting client needs.

The packaging method of the GaN device packaging structure of the present embodiment utilizes the high thermal conductivity of the dielectric layer 11 and the conductive layer 12 in the packaging substrate 1, and the heating area of the chip layer 2 is in close contact with the conductive layer 12, thereby improving the heat dissipation capacity of the packaging structure; the welding layer 4 is formed on the exposed surfaces of the electrodes of the GaN HEMT chip 21 and the MOS chip 22, and the welding layer 4 is formed on the upper surfaces of the first gate area 121, the source area 122, the drain area 123, the second gate area 124 and the cascade electrode area 125, and the welding layer 4 is used to achieve the effect of automatic alignment after solidification to realize high-precision packaging, and at the same time, the welding layer 4 is formed on both contact surfaces at the electrical connection, thereby reducing the welding voids during the solidification process of the welding layer 4 and reducing the packaging stress during the packaging process; because the packaging substrate 1 leads the electrodes of the packaging structure to the lower surface of the packaging substrate 1 through the conductive pillars 13, it is compatible with patch packaging, and the size of the packaging structure can be adjusted according to the position of the electrodes located on the lower surface of the packaging substrate according to the needs of the client, thereby meeting the needs of the client.

Embodiment 2

The present embodiment provides a GaN device packaging structure, as shown in FIG12 and FIG15, which are respectively a schematic diagram of the structure of the GaN device packaging structure without a packaging layer and a schematic diagram of the cross-sectional structure of the GaN device packaging structure, comprising a packaging substrate 1, a chip layer 2, a conductive clip 3, a welding layer 4 and a packaging layer 5, wherein the packaging substrate comprises a dielectric layer 11, a conductive layer 12 located on the upper and lower surfaces of the dielectric layer 11, and a conductive column 13 penetrating the dielectric layer 11 and electrically connected to the conductive layer 12, the conductive layer 12 located on the upper surface of the dielectric layer 11 comprises a first gate region 121, a source region 122, a drain region 123, a second gate region 124, and a cascade electrode region 125; the chip layer 2 is located above the packaging substrate 1, and comprises at least one GaN HEMT chip 21 and at least one MOS chip 22 arranged at intervals, the GaN The front side of the HEMT chip 21 is provided with a first gate (not shown) located above the first gate region 121, a first source (not shown) located above the cascade electrode region 125, and a first drain (not shown) located above the drain region 123. The front side of the MOS chip 22 is provided with a second gate (not shown) located above the second gate region 124, a second source (not shown) located above the source region 122, and a second drain (not shown) is provided on the back side of the MOS chip 22. The two ends of the conductive clip 3 are located above the second drain and the cascade electrode region 125. The welding layer 4 is respectively located between the first gate region 121 and the first gate, the cascade electrode region 125 and the first source, the first drain and the drain region 123, The second gate region 124 and the second gate, the source region 122 and the second source, the second drain and the conductive clip 3, and the conductive clip 4 and the cascade electrode region 125 form an electrical connection structure; the packaging layer 5 covers the exposed surface of the chip layer 2 and the packaging substrate 1.

As an example, the package substrate 1 includes a direct copper-bonded ceramic substrate, a direct copper-plated ceramic substrate or other suitable substrates.

Specifically, under the condition of ensuring the performance of the packaging structure, the thickness of the dielectric layer 11 can be selected according to actual conditions and is not limited here.

Specifically, under the condition of ensuring the performance of the packaging structure, the thickness of the conductive layer 12 can be selected according to actual conditions and is not limited here.

Specifically, under the condition of ensuring that the first gate is located above the first gate region 121 and the performance of the packaged device is guaranteed, the size and shape of the first gate region 121 can be selected according to actual conditions and are not limited here.

Specifically, under the condition of ensuring that the second source is located above the source region 122 and the performance of the packaged device is guaranteed, the size and shape of the second source region 122 can be selected according to actual conditions and are not limited here.

Specifically, under the condition of ensuring that the first drain is located above the drain region 124 and the performance of the packaged device is guaranteed, the size and shape of the drain region 124 can be selected according to actual conditions and are not limited here.

Specifically, under the condition of ensuring that the second gate is located above the second gate region 123 and the performance of the packaged device is guaranteed, the size and shape of the second gate region 123 can be selected according to actual conditions and are not limited here.

Specifically, under the condition that the first source is located above the cascade electrode region 125 and a portion of the cascade electrode region 125 is exposed, the size and shape of the cascade electrode region 125 can be selected according to actual conditions and are not limited here.

Specifically, while ensuring the performance of the packaging structure and the correspondence between the chip layer 2 and the conductive layer 12, the number and size of the GaN HEMT chips 21 in the chip layer 2 can be selected according to actual conditions and are no longer restricted here; the number and size of the MOS chips 22 in the chip layer 2 can be selected according to actual conditions and are no longer restricted here.

Specifically, while ensuring that the first gate, the first source and the first drain are located on the front side of the GaN HEMT chip 21 and the packaging structure performance is met, the size and position of the first gate can be selected according to actual conditions and are no longer restricted here; the size and position of the first source can be selected according to actual conditions and are no longer restricted here; the size and position of the first drain can be selected according to actual conditions and are no longer restricted here.

Specifically, under the condition that the second gate and the second source are located on the front side of the MOS chip 22, the second drain is located on the back side of the MOS chip 22 and the packaging structure performance is ensured, the size and position of the second gate can be selected according to actual conditions, and are not limited here; the size and position of the second source can be selected according to actual conditions. The size and position of the second drain can be selected according to the actual situation and are not limited here.

As an example, the conductive layer 12 located on the lower surface of the dielectric layer 11 includes a first electrode region 15 , a second electrode region 16 and a third electrode region 17 .

As an example, the first gate region 121 is electrically connected to the first electrode region 15 through the conductive column 13, the source region 122 is electrically connected to the first electrode region 15 through the conductive column 13, the first drain region 123 is electrically connected to the second electrode region 16 through the conductive column 13, and the second gate region 124 is electrically connected to the third electrode region 17 through the conductive column 13.

Specifically, since the first gate region 121 and the source region 122 are electrically connected to the first electrode region 15 through the conductive column 13, the first gate and the second source are electrically connected to the conductive layer 12 through the conductive column 13, that is, the gate of the GaN HEMT chip 21 is electrically connected to the source of the MOS chip 22.

Specifically, the first electrode region 15 , the second electrode region 16 , and the third electrode region 17 are used to connect to an external circuit to supply power to the packaging structure.

Specifically, while ensuring the performance of the packaging structure, the thickness, shape, size and position of the first electrode area 15 can be selected according to actual conditions and are no longer restricted here; the thickness, shape, size and position of the second electrode area 16 can be selected according to actual conditions and are no longer restricted here; the thickness, shape, size and position of the third electrode area 17 can be selected according to actual conditions and are no longer restricted here.

Specifically, since the lower surface of the dielectric layer 11 only has the first electrode area 15, the second electrode area 16 and the third electrode area 17, the lead frame can be set according to the customer's application requirements and the size of the packaging structure to meet the customer's needs.

As an example, the material of the welding layer 4 includes at least one of gold, silver, tin, lead, and indium, and may also be other suitable welding materials.

Specifically, while ensuring the performance of the packaged device, the thickness, size and material of the welding layer 4 can be selected according to actual conditions, and are no longer restricted here, that is, the materials of the welding layer 4 located between the first gate area 121 and the first gate, the cascade electrode area 125 and the first source, the first drain and the drain area 123, the second gate area 124 and the second gate, the source area 122 and the second source, the second drain and the conductive clip 3, and the conductive clip 3 and the cascade electrode area 125 can be different or the same.

Specifically, the first gate region 121 is electrically connected to the first gate through the welding layer 4, the cascade electrode region 125 is electrically connected to the first source through the welding layer 4, the first drain is electrically connected to the drain region 123 through the welding layer 4, and the second gate region 124 is electrically connected to the second gate through the welding layer 4. Electrical connection, the source region 122 is electrically connected to the second source through the welding layer 4, the second drain is electrically connected to the conductive clip 3 through the welding layer 4, and the conductive clip 3 is electrically connected to the cascade electrode region 125 through the welding layer 4.

Specifically, the conductive clip 3 is made of gold, silver, copper, aluminum, titanium or other suitable conductive materials.

As an example, the GaN HEMT chip 21 is also provided with an integrated passive device (not shown) and an extraction electrode (not shown) for extracting the passive device; the conductive layer 12 on the upper surface of the dielectric layer 11 is also provided with a transfer electrode area 18.

Specifically, the passive device integrated in the GaN HEMT chip 21 includes a capacitor, an inductor, a resistor or other suitable passive devices. In this embodiment, the passive device integrated in the GaN HEMT chip 21 is a resistor, and its resistance value is set according to actual needs.

Specifically, inside the GaN HEMT chip 21, the passive device is electrically connected to the first gate, that is, the terminal integrated inside the passive device is electrically connected to the first electrode area 15 through the first gate, so as to protect the GaN HEMT chip 21 and prevent the GaN HEMT chip 21 from burning.

As an example, the welding layer 4 is provided on the upper surface of the transfer electrode area 18, the conductive clip 3 is located above the welding layer 4 on the transfer electrode area 18, and the lead-out electrode is located above the welding layer 4 on the transfer electrode area 18. The conductive clip 3 forms an electrical connection structure with the lead-out electrode through the welding layer 4 and the transfer electrode area 18, that is, the conductive clip 3 is electrically connected to the lead-out electrode through the transfer electrode area 18.

Specifically, under the condition that the performance of the packaging structure is guaranteed and the lead-out electrode and the conductive clip 3 are located above the transfer electrode area 18, the position, size and shape of the transfer electrode area 18 can be selected according to actual conditions and are not limited here.

Specifically, the conductive clip 3 is located above the second drain, the cascade electrode area 125 and the transfer electrode area 18, and is electrically connected to the second drain, the cascade electrode area 125 and the transfer electrode area 18 through the pad layer 4, that is, the second drain, the first source and the lead-out electrode are electrically connected through the conductive clip 3.

Specifically, while ensuring that the conductive clip 3 forms electrical connection with the second drain, the cascade electrode area 125 and the transfer electrode area 18 respectively and the packaging structure performance, the shape, size and thickness of the conductive clip 3 can be selected according to actual conditions and are not limited here.

Specifically, the material of the encapsulation layer 5 includes epoxy resin, polyimide, silica gel, polymaleimide triazine resin, polyphenylene ether, polytetrafluoroethylene or other suitable dielectric materials. In this embodiment, an epoxy resin layer is used as the encapsulation layer 5 .

Specifically, under the condition of ensuring the performance of the packaged device, the thickness of the package layer 5 can be selected according to actual conditions and is not limited here.

Specifically, the dielectric layer 11 is further provided with at least one through hole 14 penetrating the dielectric layer 11 , the encapsulation layer 5 fills the through hole 14 , and the encapsulation layer 5 also covers the exposed surface of the lower surface of the dielectric layer 11 .

Specifically, by providing the through hole 14 , the packaging layer 5 located on the lower surface of the dielectric layer 11 is connected to the packaging layer 5 located on the upper surface of the dielectric layer 11 , thereby enhancing the airtightness and reliability of the packaging structure.

Specifically, since the current capacity of the conductive clip 3 is stronger than the current capacity of the metal lead in the wire bonding package, the conductive clip 3 electrically connecting the second drain and the first source is provided on the back side of the MOS chip 22, thereby improving the current capacity of the packaging structure. At the same time, by utilizing the combination of the conductive layer 12 and the conductive column 13, the electrode of the packaging structure is led out, thereby avoiding the bonding damage and cold solder joint problems caused by the wire bonding process, thereby improving the reliability and performance of the packaging structure.

Specifically, an anti-oxidation layer (not shown) is further provided on the exposed surface of the conductive layer 12 on the lower surface of the dielectric layer 11 to prevent oxidation of the conductive layer 12 .

Specifically, the material of the anti-oxidation layer includes tin or other suitable anti-oxidation materials.

Specifically, during the operation of the packaging structure, the MOS chip 22 provides a bias voltage to the GaN HEMT chip 21 to control the shutdown of the GaN HEMT chip 21. The MOS chip 22 serves as a switch manager for the entire device, and the GaN HEMT chip 21 serves as a main working device.

Specifically, since the conductive clip 3 is used to replace the metal leads in the wire bonding package, and the packaging substrate 1 is combined with the conductive clip for packaging, the distribution of dense metal leads in the packaging structure is avoided, the inductance and mutual inductance of the packaging structure are reduced, and the frequency of application of the packaging structure is increased, so that the packaging structure meets the working requirements of the high-frequency application end and the working efficiency of the application end is improved.

The GaN device packaging structure of the present embodiment replaces the metal leads in the wire bonding package with the conductive clip 3 and combines it with the packaging substrate 1, utilizing the fact that the current capacity of the conductive clip 3 is stronger than that of the metal leads, thereby improving the current capacity of the packaging structure. At the same time, the dense distribution of metal leads is avoided in the packaging structure, thereby reducing the inductance and mutual inductance of the packaging structure, and increasing the application frequency of the packaging structure, so that the packaging structure meets the working requirements of the high-frequency application end and improves the working efficiency of the application end. The electrodes of the packaging structure are led out by combining the conductive layer 12 with the conductive column 13, thereby avoiding the bonding damage and cold solder joint problems caused by the wire bonding packaging process, reducing the packaging resistance of the packaging structure, and improving the reliability and performance of the device.

In summary, the GaN device packaging structure and packaging method of the present invention lead out the electrodes of the packaging structure through the combination of the packaging substrate and the conductive clip, thereby avoiding the packaging method of wire bonding, and then avoiding the bonding damage and cold solder joint problems caused by the wire bonding packaging process, reducing the packaging resistance of the packaging structure, and improving the reliability and performance of the device. In addition, since the heating area of the chip layer is in close contact with the conductive layer, the thermal conductivity of the conductive layer and the dielectric layer is higher than that of the packaging layer, thereby improving the heat dissipation capacity of the packaging structure; using the conductive clip instead of the metal lead improves the current capacity of the packaging structure, and at the same time, there is no need to weld densely distributed metal wires. The lead wires are used to reduce the inductance and mutual inductance of the packaging structure, increase the application frequency of the packaging structure, enable the packaging structure to meet the working requirements of the high-frequency application end, and improve the working efficiency of the application end. In addition, during the packaging process, welding layers are formed on the exposed surfaces of each electrode of the chip layer and the upper surfaces of the first gate area, the source area, the drain area, the second gate area, and the cascade electrode area, respectively. After the welding layer is solidified, the effect of automatic alignment is achieved to achieve high-precision packaging. The two contact surfaces at the electrical connection are used to form welding layers respectively, which reduces the welding voids during the solidification of the welding layer and reduces the packaging stress during the packaging process. Since the packaging substrate leads the electrodes of the packaging structure to the lower surface of the packaging substrate through the conductive columns, it can be compatible with patch packaging, and the size of the packaging structure can be adjusted according to the client's needs and the position of the electrodes located on the lower surface of the packaging substrate, which meets the needs of the client. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

A GaN device packaging structure, characterized by comprising:

A packaging substrate, comprising a dielectric layer, conductive layers located on the upper and lower surfaces of the dielectric layer, and conductive pillars penetrating the dielectric layer and electrically connected to the conductive layer, wherein the conductive layer located on the upper surface of the dielectric layer comprises a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region;

a chip layer, located above the packaging substrate, comprising at least one GaN HEMT chip and at least one MOS chip arranged at intervals, wherein the front side of the GaN HEMT chip is provided with a first gate located above the first gate region, a first source located above the cascade electrode region, and a first drain located above the drain region, the front side of the MOS chip is provided with a second gate located above the second gate region, a second source located above the source region, and a second drain located at the back side of the MOS chip;

A conductive clip, two ends of which are located above the second drain and the cascade electrode region;

The welding layers are respectively located between the first gate region and the first gate, the cascade electrode region and the first source, the first drain and the drain region, the second gate region and the second gate, the source region and the second source, the second drain and the conductive clip, and the conductive clip and the cascade electrode region, and form an electrical connection structure;

The packaging layer covers the chip layer and the exposed surface of the packaging substrate.
The GaN device packaging structure according to claim 1 is characterized in that the packaging substrate comprises a direct copper-bonded ceramic substrate or a direct copper-plated ceramic substrate.
The GaN device packaging structure according to claim 1 is characterized in that the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region and a third electrode region.
The GaN device packaging structure according to claim 3 is characterized in that: the first gate region is electrically connected to the first electrode region through the conductive column, the source region is electrically connected to the first electrode region through the conductive column, the first drain region is electrically connected to the second electrode region through the conductive column, and the second gate region is electrically connected to the third electrode region through the conductive column.
The GaN device packaging structure according to claim 1 is characterized in that the material of the welding layer includes at least one of gold, silver, tin, lead and indium.
The GaN device packaging structure according to claim 1 is characterized in that: the GaN HEMT chip is also provided with integrated passive devices and lead-out electrodes for leading out the passive devices; and the conductive layer on the upper surface of the dielectric layer is also provided with a transfer electrode area.
The GaN device packaging structure according to claim 6, wherein the passive device is electrically connected to the first gate.
The GaN device packaging structure according to claim 6 is characterized in that: the welding layer is provided on the upper surface of the transfer electrode area, the conductive clip is located above the welding layer on the transfer electrode area, the lead-out electrode is located above the welding layer on the transfer electrode area, and the conductive clip forms an electrical connection structure with the lead-out electrode through the welding layer and the transfer electrode area.
The GaN device packaging structure according to claim 1 is characterized in that: the dielectric layer is further provided with at least one through hole penetrating the dielectric layer.
The GaN device packaging structure according to claim 9 is characterized in that: the packaging layer fills the through hole, and the packaging layer also covers the exposed surface of the lower surface of the dielectric layer.
A packaging method for a GaN device packaging structure, characterized by comprising the following steps:

A packaging substrate is provided, the packaging substrate comprising a dielectric layer, conductive layers located on the upper and lower surfaces of the dielectric layer, and conductive pillars penetrating the dielectric layer and electrically connected to the conductive layer, the conductive layer located on the upper surface of the dielectric layer comprising a first gate region, a source region, a drain region, a second gate region, and a cascade electrode region;

A chip layer is provided, wherein the chip layer includes at least one GaN HEMT chip and at least one MOS chip, wherein a first gate, a first source and a first drain are provided on the front side of the GaN HEMT chip, a second gate and a second source are provided on the front side of the MOS chip, and a second drain is provided on the back side of the MOS chip;

forming a welding layer on the upper surfaces of the first gate region, the source region, the drain region, the second gate region and the cascade electrode region, and forming the welding layer on the exposed surfaces of the first gate, the first source, the first drain, the second gate, the second source and the second drain;

The GaN HEMT chip and the MOS chip are placed on the upper surface of the package substrate at intervals, the first gate is located above the welding layer on the first gate area, and the first source is located in the cascade electrode area. The first drain is located above the welding layer on the drain region, the second gate is located above the welding layer on the second gate region, and the second source is located above the welding layer on the source region;

forming a conductive clip above the MOS chip, with two ends respectively located above the second drain and the welding layer on the cascade electrode region, and processing the packaging structure after forming the conductive clip to form an electrical connection structure;

A packaging layer is formed to cover the upper surface of the packaging substrate and the exposed surface of the chip layer.
The packaging method of the GaN device packaging structure according to claim 11 is characterized in that: the conductive layer located on the lower surface of the dielectric layer includes a first electrode region, a second electrode region and a third electrode region, the first gate region is electrically connected to the first electrode region through the conductive column, the source region is electrically connected to the first electrode region through the conductive column, the drain region is electrically connected to the second electrode region through the conductive column, and the second gate region is electrically connected to the third electrode region through the conductive column.
According to the packaging method of the GaN device packaging structure described in claim 11, it is characterized in that: the GaN HEMT chip is also provided with an integrated passive device and a lead-out electrode for leading out the passive device; a transfer electrode area is also provided in the conductive layer on the upper surface of the dielectric layer, the welding layer is formed on the upper surface of the transfer electrode area, the conductive clip is in contact with the upper surface of the welding layer on the transfer electrode area, the lead-out electrode is in contact with the upper surface of the welding layer on the transfer electrode area, and the conductive clip forms an electrical connection structure with the lead-out electrode through the welding layer and the transfer electrode area.
The packaging method of the GaN device packaging structure according to claim 11 is characterized in that: the dielectric layer is also provided with at least one through hole penetrating the dielectric layer.
The packaging method of the GaN device packaging structure according to claim 14 is characterized in that: while forming the packaging layer covering the upper surface of the packaging substrate and the exposed surface of the chip layer, the packaging layer fills the through hole.