WO2024108940A1 - 一种性能监管方法、装置、系统、设备和介质 - Google Patents

一种性能监管方法、装置、系统、设备和介质 Download PDF

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Publication number
WO2024108940A1
WO2024108940A1 PCT/CN2023/095878 CN2023095878W WO2024108940A1 WO 2024108940 A1 WO2024108940 A1 WO 2024108940A1 CN 2023095878 W CN2023095878 W CN 2023095878W WO 2024108940 A1 WO2024108940 A1 WO 2024108940A1
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data
task
processed
address information
command
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PCT/CN2023/095878
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English (en)
French (fr)
Inventor
陈超凡
赵凤鸣
刘金明
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苏州元脑智能科技有限公司
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Publication of WO2024108940A1 publication Critical patent/WO2024108940A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents

Definitions

  • the present application relates to the field of server technology, and in particular to a performance monitoring method, apparatus, system, device and computer non-volatile readable storage medium.
  • the temperature of the CPU (Central Processing Unit/Processor) needs to be monitored in real time during the operation of the server so that the cooling system can adjust the cooling strategy and ensure that the system operates normally within the preset temperature range.
  • a serious unrecoverable error occurs inside the CPU during the operation of the server, such as an IERR error caused by CATERR, the server will crash.
  • CATERR Central Processing Unit/Processor
  • the related technology is to obtain the CPU temperature and collect key register information through the ME (Management Engine) in the PCH (Platform Controller Hub), and then send this data to the BMC (Baseboard Management Controller) for further processing.
  • ME Management Engine
  • PCH Plate Controller Hub
  • BMC Baseboard Management Controller
  • the purpose of the embodiments of the present application is to provide a performance monitoring method, apparatus, system, device and computer non-volatile readable storage medium, which can improve the monitoring efficiency of the server.
  • an embodiment of the present application provides a performance supervision method, including:
  • the data carried by the task to be processed is converted into waveform data that can be recognized by the central processing unit;
  • converting the data carried by the task to be processed into waveform data recognizable by the central processor includes:
  • the command type, command parameters and address information contained in the task to be processed are extracted;
  • the address information is converted into real address information that can be recognized by the central processing unit;
  • converting the address information into real address information recognizable by the central processing unit includes:
  • the real address information matching the address information is searched from the set address conversion list; wherein the address conversion list records each I2C protocol address information and its corresponding address information recognizable by the central processing unit.
  • converting the command type, command parameters, and real address information into waveform data includes:
  • the target command waveform and the information waveform are combined as waveform data.
  • converting the response data into valid data that meets the data transmission format requirements includes:
  • the verification information and the initial valid data are parsed from the response data
  • the initial valid data is converted into valid data matching the data format corresponding to the read request.
  • converting the initial valid data into valid data matching a data format corresponding to the read request includes:
  • converting the response data into valid data that meets the data transmission format requirements, and feeding back the valid data to the baseboard management controller includes:
  • connection flag in the character string corresponding to the connection task is set to a connection success flag
  • the character string for setting the connection success mark is fed back to the baseboard management controller as valid data.
  • the response data when the task to be processed is to read the temperature information of the target central processor, the response data includes the temperature information of the target central processor; when the task to be processed is to read the target register information in the target central processor, the response data includes the register information of the target register.
  • an embodiment of the present application further provides a performance monitoring device, which is applicable to a complex programmable logic device, and the device includes a first receiving unit, a first conversion unit, a transmission unit, a second receiving unit, a second conversion unit and a feedback unit;
  • a first receiving unit configured to receive a task to be processed transmitted by a baseboard management controller
  • a first conversion unit configured to convert the data carried by the task to be processed into waveform data recognizable by the central processing unit according to a set data conversion rule
  • a transmission unit configured to transmit the waveform data to a central processing unit
  • a second receiving unit is configured to receive response data fed back by a target CPU; wherein the target CPU is a CPU matched by the address information carried in the task to be processed;
  • a second conversion unit configured to convert the response data into valid data that meets the data transmission format requirements
  • the feedback unit is configured to feed back valid data to the baseboard management controller.
  • the first conversion unit includes an extraction subunit, an address conversion subunit, and a waveform conversion subunit;
  • the extraction subunit is configured to extract the command type, command parameters and address information contained in the task to be processed according to a set data format
  • An address conversion subunit configured to convert address information into real address information recognizable by a central processing unit according to a set address conversion rule
  • the waveform conversion subunit is configured to convert the command type, command parameters and real address information into waveform data.
  • the address conversion subunit is configured to query the real address information matching the address information from a set address conversion list; wherein the address conversion list records each I2C protocol address information and its corresponding address information recognizable by the central processor.
  • the waveform conversion subunit is configured to query a target command waveform matching the command type from pre-stored command waveforms; convert command parameters and real address information into an information waveform; and merge the target command waveform and the information waveform as waveform data.
  • the second conversion unit includes a parsing subunit, a checking subunit, and a format conversion subunit;
  • the parsing subunit is configured to parse the verification information and the initial valid data from the response data according to the data transmission format corresponding to the central processor;
  • a verification subunit configured to verify the response data using the verification information
  • the format conversion subunit is configured to convert the initial valid data into valid data matching the data format corresponding to the read request when the response data passes the verification and receives the read request transmitted by the baseboard management controller.
  • the format conversion subunit is configured to set the read/write operation identification bit in the character string corresponding to the read request to the read identification; and fill the initial valid data into the free fields adjacent to the read identification in the character string in sequence to obtain valid data.
  • the second conversion unit when the task to be processed is a connection task, is configured to set the connection flag in the character string corresponding to the connection task to a connection success flag when the response data is a response information of successful connection;
  • the feedback unit is configured to feed back the character string for setting the connection success mark as valid data to the baseboard management controller.
  • the response data when the task to be processed is to read the temperature information of the target central processor, the response data includes the temperature information of the target central processor; when the task to be processed is to read the target register information in the target central processor, the response data includes the register information of the target register.
  • an embodiment of the present application further provides a performance monitoring method, applicable to a baseboard management controller, the method comprising:
  • transmitting a task to be processed to a complex programmable logic device includes:
  • the command code, address information and command parameters are converted into the task to be processed.
  • an embodiment of the present application further provides a performance monitoring device, which is applicable to a baseboard management controller, and the device includes a transmission unit, a receiving unit, and an extraction unit;
  • a transmission unit configured to transmit the task to be processed to the complex programmable logic device
  • the receiving unit is configured to receive valid data fed back by the complex programmable logic device; wherein the valid data is the response data fed back by the central processor converted into valid data that meets the data transmission format requirements after the complex programmable logic device converts the data carried by the task to be processed into waveform data recognizable by the central processor according to the set data conversion rules;
  • the extraction unit is configured to extract required data from the valid data.
  • an embodiment of the present application further provides a performance monitoring method applicable to a central processing unit, the method comprising:
  • the waveform data When receiving waveform data transmitted by a complex programmable logic device, the waveform data is parsed to obtain real address information and task information; wherein the waveform data is the data carried by the task to be processed transmitted by the baseboard management controller received by the complex programmable logic device according to the set data conversion rules, converted into waveform data recognizable by the central processing unit;
  • response data corresponding to the task information is fed back to the complex programmable logic device.
  • an embodiment of the present application further provides a performance monitoring device, applicable to a central processing unit, the device comprising a parsing unit and a feedback unit;
  • the parsing unit is configured to parse the waveform data to obtain real address information and task information when receiving the waveform data transmitted by the complex programmable logic device; wherein the waveform data is the waveform data that the complex programmable logic device converts the data carried by the task to be processed transmitted by the baseboard management controller received according to the set data conversion rules into the waveform data recognizable by the central processing unit;
  • the feedback unit is configured to feed back response data corresponding to the task information to the complex programmable logic device when the real address information matches the own address.
  • an embodiment of the present application further provides a performance monitoring system, including a baseboard management controller, a central processing unit, and a complex programmable logic device connected to the baseboard management controller and the central processing unit respectively;
  • the baseboard management controller is used to transmit tasks to be processed to the complex programmable logic device; receive valid data fed back by the complex programmable logic device; and extract required data from the valid data;
  • a complex programmable logic device is used to receive a task to be processed transmitted by a baseboard management controller; according to a set data conversion rule, convert the data carried by the task to be processed into waveform data recognizable by a central processing unit; transmit the waveform data to the central processing unit; receive response data fed back by a target central processing unit; wherein the target central processing unit is a central processing unit matched with the address information carried in the task to be processed; convert the response data into valid data that meets the data transmission format requirements, and feed the valid data back to the baseboard management controller;
  • the central processing unit is used to parse the waveform data to obtain the real address information and task information when receiving the waveform data transmitted by the complex programmable logic device; when the real address information matches the own address, the central processing unit sends the waveform data to the complex programmable logic device.
  • the programming logic device feeds back response data corresponding to the task information.
  • the baseboard management controller is used to convert the control command to be sent into a command code; and convert the command code, address information and command parameters into a task to be processed according to the data format corresponding to the command code.
  • the baseboard management controller extracts required data from valid data including:
  • the baseboard management controller extracts data corresponding to the valid data field from the valid data according to the data format corresponding to the command code.
  • the baseboard management controller is connected to the complex programmable logic device through an I2C bus, and the complex programmable logic device is connected to the central processing unit through a general purpose input and output interface.
  • an embodiment of the present application further provides an electronic device, including:
  • a processor is used to execute a computer program to implement the steps of the above performance supervision method.
  • an embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned performance monitoring method are implemented.
  • the task to be processed transmitted by the baseboard management controller is received; according to the set data conversion rules, the data carried by the task to be processed is converted into waveform data recognizable by the central processing unit; the waveform data is transmitted to the central processing unit; the response data fed back by the target central processing unit is received; wherein the target central processing unit is the central processing unit matched with the address information carried in the task to be processed; the response data is converted into valid data that meets the data transmission format requirements, and the valid data is fed back to the baseboard management controller.
  • the above operations can be performed by a complex programmable logic device, which is a component originally included in the server system and does not increase the hardware cost of server performance supervision.
  • a platform environment control channel can be built between the baseboard management controller and the central processing unit.
  • the baseboard management controller needs to obtain relevant data of a certain or certain central processing units, it can directly send the task to be processed to the complex programmable logic device, and the complex programmable logic device can interact with the central processing unit to obtain the required valid data and feed the valid data back to the baseboard management controller.
  • This implementation process makes full use of the strong real-time processing capabilities of complex programmable logic devices to realize monitoring and management of data on the central processing unit, significantly improving the success rate of central processing unit information collection in the server system, and solving the problem of low overall management and control capabilities and efficiency of the server when relying on the ME channel to obtain central processing unit related information in the traditional way.
  • it can also eliminate the controller design specifically for platform management and control functions in the baseboard management controller, further reducing chip costs.
  • FIG1 is a flow chart of a performance monitoring method provided by some embodiments of the present application.
  • FIG2 is a message format diagram of a BMC initiating a write command to a CPLD via an I2C bus provided by some embodiments of the present application;
  • FIG3 is a message format of a BMC initiating a read command to a CPLD via an I2C bus provided by some embodiments of the present application;
  • FIG4 is a system block diagram of a CPLD-based platform environment control link provided in some embodiments of the present application.
  • FIG5 is a schematic diagram of the structure of a performance monitoring device provided in some embodiments of the present application.
  • FIG6 is a schematic diagram of the structure of a performance monitoring system provided in some embodiments of the present application.
  • FIG. 7 is a structural diagram of an electronic device provided in some embodiments of the present application.
  • FIG1 is a flow chart of a performance monitoring method provided by an embodiment of the present application, the method comprising:
  • S101 receiving a task to be processed transmitted by a baseboard management controller.
  • the tasks to be processed can be varied, including connection establishment tasks, read tasks, and write tasks. Based on different management requirements, each task can also contain different subtasks.
  • a read task can include reading the temperature of the CPU or reading register information.
  • the above operations can be performed by a CPLD (Complex Programmable Logic Device), which is a component originally included in the server system and does not increase the hardware cost of server performance monitoring.
  • the CPLD can interact with the BMC and the CPU respectively.
  • the CPLD and the BMC can communicate based on the I2C bus, and the CPLD and the CPU can communicate based on the GPIO (General-purpose input/output) interface.
  • GPIO General-purpose input/output
  • the pending tasks transmitted by the BMC to the CPLD may include the task type, address information for indicating the CPU to be accessed, and command parameters required to execute the task.
  • Common platform environment control commands may include connection commands (Ping), get bitmap commands (GetDIB), and get file directory commands (GetTemp).
  • the data exchanged between BMC and CPLD needs to comply with the I2C protocol, so when BMC transmits the task to be processed to CPLD, it can convert the information used to characterize the task type into a command code that meets the transmission requirements.
  • 5-bit data can completely cover all task types, so in the embodiment of the present application, 5-bit data can be used to record the command code.
  • a byte contains 8 bits.
  • the command code occupies 5 bits and the address information occupies 3 bits.
  • the command code and address information can be written into the same byte.
  • the command parameters are written into the subsequent bytes adjacent to the byte, thereby forming a task to be processed and transmitted to the CPLD.
  • CPLD communicates with BMC based on I2C bus
  • CPLD communicates with CPU based on GPIO interface.
  • the data transmission formats supported by the two are different. Therefore, after CPLD receives the pending task transmitted by BMC, it needs to extract the command type, command parameters and address information contained in the pending task according to the data format set between BMC and CPLD.
  • the address information transmitted by the BMC is not in an address format that can be recognized by the CPU, it is necessary to convert the address information into real address information that can be recognized by the CPU according to the set address conversion rules.
  • the CPU address information involved can be summarized to establish an address conversion list, wherein the address conversion list records each I2C protocol address information and its corresponding address information recognizable by the central processing unit.
  • the address information recognizable by the central processing unit can be referred to as real address information.
  • the CPLD can query the real address information that matches the address information from the set address conversion list.
  • the I2C protocol address refers to the platform environment control address in the I2C protocol, which is presented in binary form.
  • the real address is presented in hexadecimal form.
  • GPIO can be used to transmit waveform data. Therefore, after CPLD extracts the command type, command parameters and address information contained in the task to be processed and converts the address information into real address information recognizable by the central processing unit, it can convert the command type, command parameters and real address information into waveform data.
  • the waveform data is an analog signal supported by the platform environment control bus of the central processing unit.
  • the number of command types is limited, and each command type is fixed information.
  • the waveforms corresponding to different command types can be pre-stored.
  • the waveform corresponding to the command type can be called a command waveform
  • the waveform corresponding to specific data such as command parameters, address information, etc. can be called an information waveform.
  • the CPLD can query a target command waveform matching the command type from pre-stored command waveforms; convert command parameters and real address information into an information waveform; and merge the target command waveform and the information waveform as waveform data.
  • the CPLD is equipped with a GPIO interface, and the CPU will be allocated a corresponding platform environment control port, which is connected to the GPIO interface through the platform environment control bus.
  • the server system contains a large number of CPUs, and the CPLD can transmit waveform data to all CPUs through the platform environment control bus.
  • S104 Receive response data fed back by the target central processor.
  • the target CPU is the CPU matched by the address information carried in the task to be processed.
  • Each CPU can analyze the waveform data and parse out the command type, command parameters, and real address information. Each CPU will compare the real address information carried by the waveform data with its own address information. If the real address information carried by the waveform data is consistent with its own address information, it will feedback the corresponding response data to the CPLD based on the command type and command parameters. For example, if the command type is to read register information and the command parameters contain the register identifier, the CPU can rely on the identifier to determine the specific corresponding register, thereby reading the information recorded in the register and feeding the read register information back to the CPLD as response data.
  • the response data when the task to be processed is to read the temperature information of the target CPU, the response data may include the temperature information of the target CPU; when the task to be processed is to read the target register information in the target CPU, the response data may include the register information of the target register.
  • S105 Convert the response data into valid data that meets the data transmission format requirements, and feed the valid data back to the baseboard management controller.
  • the response data fed back by the CPU to the CPLD often carries verification information.
  • the CPLD can parse the check information and the initial valid data from the response data according to the data transmission format corresponding to the central processor.
  • the response data is checked using the check information.
  • the initial valid data is converted into valid data that matches the data format corresponding to the read request.
  • the check information can be CRC (Cyclic Redundancy Check).
  • an I2C-based platform environment control transmission protocol can be set, which is used to complete the I2C-based platform environment control command interaction and data receiving and sending functions between the BMC and the CPLD.
  • this transmission protocol the message format of the BMC initiating a write command to the CPLD via the I2C bus is shown in Figure 2, and the message format of the BMC initiating a read command to the CPLD via the I2C bus is shown in Figure 3.
  • the slave address in Figure 2 indicates the address of the CPLD; It is a read/write operation identification bit. When its value is 0, it indicates a write operation. When its value is 1, it indicates a read operation.
  • the confirmation signal (ACK) set between each byte in Figure 2 is a signal that needs to be filled in by the CPLD.
  • the 5 bits from B7 to B3 in Figure 2 can be used to record the command code.
  • the 3 bits from B2 to B0 are used to record the platform environment control address.
  • the platform environment control address refers to the address of the CPU to be accessed.
  • the platform environment control command parameters can be filled in the subsequent bytes in sequence.
  • the CPLD can set the read/write operation flag in the string corresponding to the read request to the read flag; fill the initial valid data into the free fields adjacent to the read flag in the string in sequence to obtain valid data.
  • the read command carries two slave addresses, both of which represent the addresses of the CPLD. Indicates BMC write command code and platform environment control address. The second slave address is recorded after Indicates valid data returned by the CPLD.
  • command mapping module and valid data extraction module can be set in BMC.
  • Command matching module, waveform trigger module and valid data analysis module can be set in CPLD.
  • Platform environment control port can be set on each CPU to realize interaction with CPLD through platform environment control bus.
  • FIG4 is a system block diagram of a CPLD-based platform environment control link provided in an embodiment of the present application, wherein the BMC and the CPLD are connected via an I2C bus, and the CPLD and the CPU are connected via a platform environment control bus.
  • FIG4 takes two CPUs as an example, namely CPU0 and CPU1. In actual applications, more CPUs may be included.
  • the connection task sent by the BMC to the CPLD can use the Ping command.
  • the BMC first converts the Ping command into a command code through the command mapping module.
  • the command codes corresponding to different commands can be customized.
  • the command code corresponding to the Ping command is 5 bits of data: 5'b00001.
  • the command mapping module also completes the bit-byte splicing function of the command code and the platform environment control address.
  • the platform environment control address is 3 bits of data: 3'b000.
  • the client addresses of CPU0 and CPU1 are 0x30 and 0x31 respectively.
  • the command code occupies the upper 5 bits of the byte
  • the platform environment control address occupies the lower 3 bits of the byte.
  • the splicing form can be seen in Figure 2, which will not be repeated here.
  • the BMC After the BMC generates the concatenated bytes of the command code and the platform environment control address, it confirms the slave address of the CPLD, the platform environment control command parameter 1...platform environment control command parameter N.
  • the platform environment control command parameters that need to be carried include the two bytes of Write Length and Read Length, and then data is transmitted through the I2C channel between the BMC and the CPLD according to the message command format shown in Figure 2.
  • CPLD After receiving the data sent by BMC through the I2C channel, CPLD extracts the command code and platform environment control address through the command matching module, and then compares them with the local command list to identify that the command sent by BMC is a Ping command.
  • the local command list can be based on the command types corresponding to different command codes.
  • the CPLD After the CPLD recognizes the Ping command, it first converts the platform environment control address to the real platform environment control address according to Table 1 above, assuming that the converted address is 0x30. Then the waveform trigger module is started to generate a matching Ping command waveform and send it to the platform environment control bus through the GPIO pin.
  • the platform environment control ports of CPU0 and CPU1 listen to the status of the platform environment control bus. When they "sense" that there is request data on the bus, they first parse the Ping command waveform and get the address of 0x30. At this time, CPU0 and CPU1 compare their own platform environment control addresses respectively. If CPU1 finds that it does not match its own address, it will not respond; if CPU0 finds that it matches its own address, it will send the response data of the Ping command (the response data of the Ping command can be a byte of CRC check information, defined as a frame check sequence (FCS)) to the platform environment control bus.
  • FCS frame check sequence
  • CPLD receives the response data of CPU from the platform environment control bus through GPIO pins, and parses the verification information carried by the response data through the valid data parsing module.
  • the valid data parsing module first needs to perform CRC check on the response data. If the check passes, the response data except FCS data is extracted as the valid data after parsing.
  • the valid data parsed by the CPLD needs to be format converted before it can be fed back to the BMC.
  • the valid data before the format conversion can be called initial valid data.
  • the CPLD When the CPLD receives the response information of successful connection fed back by the CPU, it can set the connection flag in the character string corresponding to the connection task as the connection success flag; and feed back the character string with the connection success flag as valid data to the base station. Board Management Controller.
  • the function may be implemented using the return valid data 1 in FIG. 3 .
  • the value is 0x0, it indicates that the Ping command cannot ping the 0x30 device.
  • the value is 0x1, it indicates that the Ping command can ping the 0x30 device.
  • the BMC initiates a platform environment control command read operation to the CPLD through the I2C bus according to the message format of Figure 3, and the CPLD returns valid data to the I2C bus. Then the BMC receives the valid data returned from the CPLD through the I2C channel, and extracts the valid data through the valid data extraction module. Finally, the BMC processes the extracted valid data. Taking the Ping command as an example, the BMC processes the extracted valid data to determine whether the valid data is 0x1. If so, it means that there is a client device with an address of 0x30 on the platform environment control bus. If it is other platform environment control commands (commands other than the Ping command), the valid data returned by the corresponding number of bytes is extracted according to the control protocol specification for other processing.
  • the functional modules involving BMC can be implemented by the firmware of BMC, and the implementation code is usually stored in the external flash storage medium of the BMC chip.
  • the functional modules involving CPLD can be implemented by the firmware of CPLD, and the firmware of CPLD is generally stored in the non-volatile storage medium inside CPLD.
  • the task to be processed transmitted by the baseboard management controller is received; according to the set data conversion rules, the data carried by the task to be processed is converted into waveform data recognizable by the central processing unit; the waveform data is transmitted to the central processing unit; the response data fed back by the target central processing unit is received; wherein the target central processing unit is the central processing unit matched by the address information carried in the task to be processed; the response data is converted into valid data that meets the data transmission format requirements, and the valid data is fed back to the baseboard management controller.
  • the above operations can be performed by a complex programmable logic device, which is a component originally included in the server system and does not increase the hardware cost of server performance supervision.
  • a platform environment control channel can be built between the baseboard management controller and the central processing unit.
  • the baseboard management controller needs to obtain relevant data of a certain or certain central processing units, it can directly send the task to be processed to the complex programmable logic device, and the complex programmable logic device can interact with the central processing unit to obtain the required valid data and feed the valid data back to the baseboard management controller.
  • This implementation process makes full use of the strong real-time processing capabilities of complex programmable logic devices to realize monitoring and management of data on the central processing unit, significantly improving the success rate of central processing unit information collection in the server system, and solving the problem of low overall management and control capabilities and efficiency of the server when relying on the ME channel to obtain central processing unit related information in the traditional way.
  • it can also eliminate the controller design specifically for platform management and control functions in the baseboard management controller, further reducing chip costs.
  • FIG5 is a schematic diagram of the structure of a performance monitoring device provided in an embodiment of the present application, which is applicable to complex programmable logic devices.
  • the device includes a first receiving unit 51, a first conversion unit 52, a transmission unit 53, a second receiving unit 54, a second conversion unit 55 and a feedback unit 56;
  • a first receiving unit 51 is configured to receive a task to be processed transmitted by a baseboard management controller
  • the first conversion unit 52 is configured to convert the data carried by the task to be processed into waveform data recognizable by the central processing unit according to a set data conversion rule;
  • a transmission unit 53 configured to transmit the waveform data to a central processing unit
  • the second receiving unit 54 is configured to receive response data fed back by the target CPU; wherein the target CPU is the CPU matched by the address information carried in the task to be processed;
  • a second conversion unit 55 is configured to convert the response data into valid data that meets the data transmission format requirements
  • the feedback unit 56 is configured to feed back valid data to the baseboard management controller.
  • the first conversion unit includes an extraction subunit, an address conversion subunit, and a waveform conversion subunit;
  • the extraction subunit is configured to extract the command type, command parameters and address information contained in the task to be processed according to a set data format
  • An address conversion subunit configured to convert address information into real address information recognizable by a central processing unit according to a set address conversion rule
  • the waveform conversion subunit is configured to convert the command type, command parameters and real address information into waveform data.
  • the address conversion subunit is configured to query the real address information matching the address information from a set address conversion list; wherein the address conversion list records each I2C protocol address information and its corresponding address information recognizable by the central processor.
  • the waveform conversion subunit is configured to query a target command waveform matching the command type from pre-stored command waveforms; convert command parameters and real address information into an information waveform; and merge the target command waveform and the information waveform as waveform data.
  • the second conversion unit includes a parsing subunit, a checking subunit, and a format conversion subunit;
  • the parsing subunit is configured to parse the verification information and the initial valid data from the response data according to the data transmission format corresponding to the central processing unit;
  • a verification subunit configured to verify the response data using the verification information
  • the format conversion subunit is configured to convert the initial valid data into valid data matching the data format corresponding to the read request when the response data passes the verification and receives the read request transmitted by the baseboard management controller.
  • the format conversion subunit is configured to set the read/write operation identification bit in the character string corresponding to the read request to the read identification; and fill the initial valid data into the free fields adjacent to the read identification in the character string in sequence to obtain valid data.
  • the second conversion unit when the task to be processed is a connection task, is configured to set the connection flag in the character string corresponding to the connection task to a connection success flag when the response data is a response information of successful connection;
  • the feedback unit is configured to feed back the character string for setting the connection success mark as valid data to the baseboard management controller.
  • the response data when the task to be processed is to read the temperature information of the target central processor, the response data includes the temperature information of the target central processor; when the task to be processed is to read the target register information in the target central processor, the response data includes the register information of the target register.
  • the tasks to be processed transmitted by the baseboard management controller are received; according to the set data conversion rules, the data carried by the tasks to be processed are converted into waveform data recognizable by the central processing unit; the waveform data is transmitted to the central processing unit; the response data fed back by the target central processing unit is received; wherein the target central processing unit is the central processing unit matched with the address information carried in the tasks to be processed; the response data is converted into valid data that meets the data transmission format requirements, and the valid data is fed back to the baseboard management controller.
  • complex programmable logic devices can be used to perform In the above operations, the complex programmable logic device is a component originally included in the server system and will not increase the hardware cost of server performance monitoring.
  • a platform environment control channel can be built between the baseboard management controller and the central processing unit.
  • the baseboard management controller needs to obtain relevant data of a certain or certain central processing units, it can directly send tasks to be processed to the complex programmable logic device.
  • the complex programmable logic device can interact with the central processing unit to obtain the required valid data and feed back the valid data to the baseboard management controller.
  • This implementation process makes full use of the strong real-time processing characteristics of the complex programmable logic device to realize the monitoring and management of data on the central processing unit, significantly improves the success rate of central processing unit information collection in the server system, and solves the problem of low overall management and control capabilities and efficiency of the server when relying on the ME channel to obtain relevant information about the central processing unit in the traditional way.
  • it can also save the controller design specifically used for platform management and control functions in the baseboard management controller, further reducing chip costs.
  • the present application also provides a performance monitoring method applicable to a baseboard management controller, the method comprising:
  • transmitting a task to be processed to a complex programmable logic device includes:
  • the command code, address information and command parameters are converted into the task to be processed.
  • the embodiment of the present application also provides a performance monitoring device, which is applicable to a baseboard management controller, and the device includes a transmission unit, a receiving unit and an extraction unit;
  • a transmission unit configured to transmit the task to be processed to the complex programmable logic device
  • the receiving unit is configured to receive valid data fed back by the complex programmable logic device; wherein the valid data is the response data fed back by the central processor converted into valid data that meets the data transmission format requirements after the complex programmable logic device converts the data carried by the task to be processed into waveform data recognizable by the central processor according to the set data conversion rules;
  • the extraction unit is configured to extract required data from the valid data.
  • the present application also provides a performance monitoring method applicable to a central processing unit, the method comprising:
  • the waveform data When receiving waveform data transmitted by a complex programmable logic device, the waveform data is parsed to obtain real address information and task information; wherein the waveform data is the data carried by the task to be processed transmitted by the baseboard management controller received by the complex programmable logic device according to the set data conversion rules, converted into waveform data recognizable by the central processing unit;
  • response data corresponding to the task information is fed back to the complex programmable logic device.
  • the embodiment of the present application also provides a performance monitoring device, which is applicable to a central processing unit, and the device includes a parsing unit and a feedback unit;
  • the parsing unit is configured to parse the waveform data to obtain real address information and task information when receiving the waveform data transmitted by the complex programmable logic device; wherein the waveform data is the waveform data that the complex programmable logic device converts the data carried by the task to be processed transmitted by the baseboard management controller received according to the set data conversion rules into the waveform data recognizable by the central processing unit;
  • the feedback unit is configured to feed back response data corresponding to the task information to the complex programmable logic device when the real address information matches the own address.
  • Figure 6 is a structural schematic diagram of a performance monitoring system provided in an embodiment of the present application, including a baseboard management controller 61, a central processing unit 62, and a complex programmable logic device 63 connected to the baseboard management controller 61 and the central processing unit 62 respectively; there can be multiple central processing units 62, and three are taken as an example in Figure 6. In actual applications, there can be more or fewer central processing units 62.
  • the baseboard management controller 61 is used to transmit the tasks to be processed to the complex programmable logic device 63; receive the valid data fed back by the complex programmable logic device 63; and extract the required data from the valid data;
  • the complex programmable logic device 63 is used to receive the task to be processed transmitted by the baseboard management controller 61; according to the set data conversion rules, the data carried by the task to be processed is converted into waveform data recognizable by the central processing unit 62; the waveform data is transmitted to the central processing unit 62; the response data fed back by the target central processing unit 62 is received; wherein the target central processing unit 62 is the central processing unit 62 matched with the address information carried in the task to be processed; the response data is converted into valid data that meets the data transmission format requirements, and the valid data is fed back to the baseboard management controller 61;
  • the central processing unit 62 is used to parse the waveform data transmitted by the complex programmable logic device 63 to obtain the real address information and task information when the waveform data is received; when the real address information matches its own address, it feeds back the response data corresponding to the task information to the complex programmable logic device 63.
  • the baseboard management controller is used to convert the control command to be sent into a command code; and convert the command code, address information and command parameters into a task to be processed according to a data format corresponding to the command code.
  • the baseboard management controller extracts required data from valid data including:
  • the baseboard management controller extracts data corresponding to the valid data field from the valid data according to the data format corresponding to the command code.
  • the baseboard management controller is connected to the complex programmable logic device through an I2C bus, and the complex programmable logic device is connected to the central processing unit through a general purpose input and output interface.
  • the task to be processed transmitted by the baseboard management controller is received; according to the set data conversion rules, the data carried by the task to be processed is converted into waveform data recognizable by the central processing unit; the waveform data is transmitted to the central processing unit; the response data fed back by the target central processing unit is received; wherein the target central processing unit is the central processing unit matched by the address information carried in the task to be processed; the response data is converted into valid data that meets the data transmission format requirements, and the valid data is fed back to the baseboard management controller.
  • the above operations can be performed by a complex programmable logic device, which is a component originally included in the server system and will not increase the hardware cost of server performance supervision.
  • a platform environment control channel can be built between the baseboard management controller and the central processing unit.
  • the baseboard management controller needs to obtain relevant data of a certain or certain central processing units, it can directly send the task to be processed to the complex programmable logic device, and the complex programmable logic device can interact with the central processing unit to obtain the required valid data and feed the valid data back to the baseboard management controller.
  • This implementation process makes full use of the strong real-time processing capabilities of complex programmable logic devices to realize the monitoring and management of data on the central processing unit, significantly improving the success rate of central processing unit information collection in the server system, and solving the problem of low overall management and control capabilities and efficiency of the server when relying on the ME channel to obtain central processing unit related information in the traditional way.
  • it can also eliminate the controller design specifically for platform management and control functions in the baseboard management controller, further reducing chip costs.
  • FIG. 7 is a structural diagram of an electronic device provided in an embodiment of the present application. As shown in FIG. 7 , the electronic device includes: a memory 20 for storing a computer program;
  • the processor 21 is used to implement the steps of the performance monitoring method in the above embodiment when executing a computer program.
  • the electronic device may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.
  • the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc.
  • the processor 21 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array).
  • the processor 21 may also include a main processor and a coprocessor.
  • the main processor is a processor for processing data in the awake state, also known as CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state.
  • the processor 21 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen.
  • the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.
  • AI Artificial Intelligence
  • the memory 20 may include one or more computer non-volatile readable storage media, which may be non-transitory.
  • the memory 20 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices.
  • the memory 20 is at least used to store the following computer program 201, wherein, after the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the performance supervision method disclosed in any of the aforementioned embodiments.
  • the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage.
  • the operating system 202 may include Windows, Unix, Linux, etc.
  • Data 203 may include but is not limited to data conversion rules, data transmission format requirements, etc.
  • the electronic device may further include a display screen 22 , an input/output interface 23 , a communication interface 24 , a power source 25 , and a communication bus 26 .
  • FIG. 7 does not limit the electronic device and may include more or fewer components than those shown in the figure.
  • the performance supervision method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.
  • the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, magnetic disk or optical disk and other media that can store program codes.
  • an embodiment of the present application further provides a computer non-volatile readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned performance monitoring method are implemented.

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Abstract

本申请涉及服务器技术领域，公开了一种性能监管方法、装置、系统、设备和介质，接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。

Description

一种性能监管方法、装置、系统、设备和介质
相关申请的交叉引用
本申请要求于2022年11月25日提交中国专利局，申请号为202211487121.4，申请名称为“一种性能监管方法、装置、系统、设备和介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及服务器技术领域，特别是涉及一种性能监管方法、装置、系统、设备和计算机非易失性可读存储介质。
背景技术
近年来随着云服务、AI(Artificial Intelligence，机器智能)、大数据及高性能计算等技术领域的快速发展，对服务器系统的性能与管控能力提出了更高的要求。特别地，服务器的散热处理和故障诊断功能成为影响服务器性能及运营管理的重要方面。
为了保持散热系统最佳的运行状态，服务器运行过程中需要实时监控CPU(Central Processing Unit/Processor，中央处理器)的温度，以供散热系统进行散热策略调整，保证系统在预设的温度区间正常运行。此外，服务器在运行过程中，当CPU内部出现不可恢复的严重错误，如由CATERR引起的IERR错误时将会引起服务器宕机。为了能够通过故障诊断技术对系统故障原因进行宕机后的定位分析，需要在宕机前对CPU内关键寄存器信息进行“快速收集”。
相关技术是通过PCH(Platform Controller Hub，南桥)中的ME(Management Engine，管理引擎)实现对CPU温度的获取及关键寄存器信息收集，然后将这些数据发给BMC(Baseboard Management Controller，基板管理控制器)进行下一步处理。由于ME本身承担着服务器管理的多项复杂任务，经常发生CPU温度获取及寄存器信息收集被其他任务打断的情况。同时，当服务器出现系统宕机时，ME同样会大概率受到影响而无法工作。因此，相关技术存在信息收集效率低下，甚至会出现无法成功获取温度及寄存器信息的问题，严重影响服务器整体的管理监控效率。
可见，如何提升服务器的监控效率，是本领域技术人员需要解决的问题。
发明内容
本申请实施例的目的是提供一种性能监管方法、装置、系统、设备和计算机非易失性可读存储介质，可以提升服务器的监控效率。
为解决上述技术问题，根据第一方面，本申请实施例提供一种性能监管方法，包括：
接收基板管理控制器传输的待处理任务；
按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；
将波形数据传输至中央处理器；
接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；
将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制 器。
在本申请的一些实施例中，按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据包括：
根据设定的数据格式，从待处理任务中提取出包含的命令类型、命令参数以及地址信息；
依据设定的地址转换规则，将地址信息转换为中央处理器可识别的真实地址信息；
将命令类型、命令参数以及真实地址信息转换为波形数据。
在本申请的一些实施例中，依据设定的地址转换规则，将地址信息转换为中央处理器可识别的真实地址信息包括：
从设定的地址转换列表中查询与地址信息匹配的真实地址信息；其中，地址转换列表中记录有各I2C协议地址信息及其各自对应的中央处理器可识别的地址信息。
在本申请的一些实施例中，将命令类型、命令参数以及真实地址信息转换为波形数据包括：
从预先存储的命令波形中查询与命令类型匹配的目标命令波形；
将命令参数与真实地址信息转换为信息波形；
将目标命令波形与信息波形合并作为波形数据。
在本申请的一些实施例中，将响应数据转换为符合数据传输格式要求的有效数据包括：
按照中央处理器对应的数据传输格式，从响应数据中解析出校验信息和初始有效数据；
利用校验信息对响应数据进行校验；
在响应数据通过校验并且接收到基板管理控制器传输的读取请求的情况下，将初始有效数据转换为与读取请求对应的数据格式匹配的有效数据。
在本申请的一些实施例中，将初始有效数据转换为与读取请求对应的数据格式匹配的有效数据包括：
将读取请求对应的字符串中读写操作标识位设置为读标识；
将初始有效数据依次填写至字符串中与读标识相邻的空闲字段，以得到有效数据。
在本申请的一些实施例中，在待处理任务为连接任务的情况下，将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器包括：
在响应数据为连通成功的响应信息的情况下，将连接任务对应的字符串中连通标识位设置为连通成功标识；
将设置连通成功标识的字符串作为有效数据反馈至基板管理控制器。
在本申请的一些实施例中，在待处理任务为读取目标中央处理器的温度信息的情况下，相应的，响应数据包括目标中央处理器的温度信息；在待处理任务为读取目标中央处理器中目标寄存器信息的情况下，相应的，响应数据包括目标寄存器的寄存器信息。
根据第二方面，本申请实施例还提供了一种性能监管装置，适用于复杂可编程逻辑器件，装置包括第一接收单元、第一转换单元、传输单元、第二接收单元、第二转换单元和反馈单元；
第一接收单元，设置为接收基板管理控制器传输的待处理任务；
第一转换单元，设置为按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；
传输单元，设置为将波形数据传输至中央处理器；
第二接收单元，设置为接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；
第二转换单元，设置为将响应数据转换为符合数据传输格式要求的有效数据；
反馈单元，设置为将有效数据反馈至基板管理控制器。
在本申请的一些实施例中，第一转换单元包括提取子单元、地址转换子单元和波形转换子单元；
提取子单元，设置为根据设定的数据格式，从待处理任务中提取出包含的命令类型、命令参数以及地址信息；
地址转换子单元，设置为依据设定的地址转换规则，将地址信息转换为中央处理器可识别的真实地址信息；
波形转换子单元，设置为将命令类型、命令参数以及真实地址信息转换为波形数据。
在本申请的一些实施例中，地址转换子单元设置为从设定的地址转换列表中查询与地址信息匹配的真实地址信息；其中，地址转换列表中记录有各I2C协议地址信息及其各自对应的中央处理器可识别的地址信息。
在本申请的一些实施例中，波形转换子单元设置为从预先存储的命令波形中查询与命令类型匹配的目标命令波形；将命令参数与真实地址信息转换为信息波形；将目标命令波形与信息波形合并作为波形数据。
在本申请的一些实施例中，第二转换单元包括解析子单元、校验子单元和格式转换子单元；
解析子单元，设置为按照中央处理器对应的数据传输格式，从响应数据中解析出校验信息和初始有效数据；
校验子单元，设置为利用校验信息对响应数据进行校验；
格式转换子单元，设置为在响应数据通过校验并且接收到基板管理控制器传输的读取请求的情况下，将初始有效数据转换为与读取请求对应的数据格式匹配的有效数据。
在本申请的一些实施例中，格式转换子单元设置为将读取请求对应的字符串中读写操作标识位设置为读标识；将初始有效数据依次填写至字符串中与读标识相邻的空闲字段，以得到有效数据。
在本申请的一些实施例中，在待处理任务为连接任务的情况下，第二转换单元设置为在响应数据为连通成功的响应信息的情况下，将连接任务对应的字符串中连通标识位设置为连通成功标识；
反馈单元设置为将设置连通成功标识的字符串作为有效数据反馈至基板管理控制器。
在本申请的一些实施例中，在待处理任务为读取目标中央处理器的温度信息的情况下，相应的，响应数据包括目标中央处理器的温度信息；在待处理任务为读取目标中央处理器中目标寄存器信息的情况下，相应的，响应数据包括目标寄存器的寄存器信息。
根据第三方面，本申请实施例还提供了一种性能监管方法，适用于基板管理控制器，方法包括：
向复杂可编程逻辑器件传输待处理任务；
接收复杂可编程逻辑器件反馈的有效数据；其中，有效数据为复杂可编程逻辑器件按照 设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据后，将中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
从有效数据中提取出所需的数据。
在本申请的一些实施例中，向复杂可编程逻辑器件传输待处理任务包括：
将待发送的控制命令转换为命令码；
按照命令码对应的数据格式，将命令码、地址信息和命令参数转换为待处理任务。
根据第四方面，本申请实施例还提供了一种性能监管装置，适用于基板管理控制器，装置包括传输单元、接收单元和提取单元；
传输单元，设置为向复杂可编程逻辑器件传输待处理任务；
接收单元，设置为接收复杂可编程逻辑器件反馈的有效数据；其中，有效数据为复杂可编程逻辑器件按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据后，将中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
提取单元，设置为从有效数据中提取出所需的数据。
根据第五方面，本申请实施例还提供了一种性能监管方法，适用于中央处理器，方法包括：
在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；其中，波形数据为复杂可编程逻辑器件按照设定的数据转换规则，将接收到的基板管理控制器传输的待处理任务携带的数据转换为中央处理器可识别的波形数据；
在真实地址信息与自身地址匹配的情况下，向复杂可编程逻辑器件反馈任务信息对应的响应数据。
根据第六方面，本申请实施例还提供了一种性能监管装置，适用于中央处理器，装置包括解析单元和反馈单元；
解析单元，设置为在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；其中，波形数据为复杂可编程逻辑器件按照设定的数据转换规则，将接收到的基板管理控制器传输的待处理任务携带的数据转换为中央处理器可识别的波形数据；
反馈单元，设置为在真实地址信息与自身地址匹配的情况下，向复杂可编程逻辑器件反馈任务信息对应的响应数据。
根据第七方面，本申请实施例还提供了一种性能监管系统，包括基板管理控制器，中央处理器，分别与基板管理控制器以及中央处理器连接的复杂可编程逻辑器件；
基板管理控制器，用于向复杂可编程逻辑器件传输待处理任务；接收复杂可编程逻辑器件反馈的有效数据；从有效数据中提取出所需的数据；
复杂可编程逻辑器件，用于接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器；
中央处理器，用于在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；在真实地址信息与自身地址匹配的情况下，向复杂可 编程逻辑器件反馈任务信息对应的响应数据。
在本申请的一些实施例中，基板管理控制器用于将待发送的控制命令转换为命令码；按照命令码对应的数据格式，将命令码、地址信息和命令参数转换为待处理任务。
在本申请的一些实施例中，基板管理控制器从有效数据中提取出所需的数据包括：
基板管理控制器按照命令码对应的数据格式，从有效数据中提取出有效数据字段对应的数据。
在本申请的一些实施例中，基板管理控制器与复杂可编程逻辑器件通过I2C总线连接，复杂可编程逻辑器件与中央处理器通过通用输入输出接口连接。
根据第八方面，本申请实施例还提供了一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序以实现如上述性能监管方法的步骤。
根据第九方面，本申请实施例还提供了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上述性能监管方法的步骤。
由上述技术方案可以看出，接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。在该技术方案中，可以由复杂可编程逻辑器件执行上述操作，复杂可编程逻辑器件属于服务器系统中原本包含的部件，不会增加服务器性能监管的硬件成本。基于复杂可编程逻辑器件可以在基板管理控制器与中央处理器间构建一条平台环境控制通道。基板管理控制器需要获取某台或某些中央处理器的相关数据时，可以直接向复杂可编程逻辑器件发送待处理任务，复杂可编程逻辑器件可以实现与中央处理器的交互，从而获取到所需的有效数据，将有效数据反馈至基板管理控制器。该实现过程充分利用了复杂可编程逻辑器件处理实时性强的特点，实现对中央处理器上数据的监控管理，显著提升了服务器系统中中央处理器信息收集的成功率，解决了传统方式中依赖ME通道获取中央处理器相关信息时造成服务器整体管理控制能力及效率低下的问题，同时还可以省去基板管理控制器中专门用于平台管理控制功能的控制器设计，进一步降低了芯片成本。
附图说明
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一些实施例提供的一种性能监管方法的流程图；
图2为本申请一些实施例提供的一种BMC通过I2C总线向CPLD发起写命令的消息格式图；
图3为本申请一些实施例提供的一种BMC通过I2C总线向CPLD发起读命令的消息格式；
图4为本申请一些实施例提供的一种基于CPLD的平台环境控制链路的系统框图；
图5为本申请一些实施例提供的一种性能监管装置的结构示意图；
图6为本申请一些实施例提供的一种性能监管系统的结构示意图；
图7为本申请一些实施例提供的一种电子设备的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下，所获得的所有其他实施例，都属于本申请保护范围。
本申请的说明书和权利要求书及上述附图中的术语“包括”和“具有”，以及与“包括”和“具有”相关的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可包括没有列出的步骤或单元。
为了使本技术领域的人员更好地理解本申请方案，下面结合附图和具体实施方式对本申请作进一步的详细说明。
接下来，详细介绍本申请实施例所提供的一种性能监管方法。图1为本申请实施例提供的一种性能监管方法的流程图，该方法包括：
S101：接收基板管理控制器传输的待处理任务。
待处理任务可以多种多样，可以包括建立连接任务、读任务、写任务。基于不同的管理需求，每种任务下也可以包含不同的子任务，例如，读任务可以包括读取中央处理器的温度或者是读取寄存器信息等。
在本申请实施例中，可以由CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)执行上述操作，复杂可编程逻辑器件属于服务器系统中原本包含的部件，不会增加服务器性能监管的硬件成本。CPLD可以分别与BMC以及CPU进行交互。在实际应用中，CPLD和BMC之间可以基于I2C总线进行通信，CPLD和CPU可以基于GPIO(General-purpose input/output，通用输入输出)接口进行通信。
BMC向CPLD传输的待处理任务可以包括任务类型、用于指示所需访问的CPU的地址信息、以及执行任务所需的命令参数等。常见的平台环境控制命令可以包括连接命令(Ping)，获取位图命令(GetDIB)和获取文件目录命令(GetTemp)等。
BMC和CPLD交互的数据需要符合I2C协议，因此BMC在向CPLD传输待处理任务时，可以将用于表征任务类型的信息转换为符合传输要求的命令码。结合实际应用中所需执行的任务类型，采用5比特的数据可以完全覆盖所有的任务类型，因此在本申请实施例中，可以采用5比特数据记录命令码。
考虑到实际应用中，服务器系统包含的CPU个数一般不超过8台，因此可以采用3比特数据表征不同CPU的地址信息。当然在实际应用中，当CPU数量增多时，也可以分配更多比特的数据用于记录CPU的地址信息，3比特仅为举例说明，并不作为对CPU地址信息长度的限定。
一个字节包含8比特，以命令码占用5比特，地址信息占用3比特为例，可以将命令码和地址信息写入到同一个字节中。将命令参数写入到与该字节相邻的后续字节中，从而构成待处理任务传输至CPLD。
S102：按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的 波形数据。
在实际应用中，CPLD与BMC基于I2C总线通信，CPLD与CPU基于GPIO接口进行通信，两者所支持的数据传输格式并不相同，因此CPLD在接收到BMC传输的待处理任务之后，需要按照BMC和CPLD之间设定的数据格式，从待处理任务中提取出包含的命令类型、命令参数以及地址信息。
由于BMC传输的地址信息并非是CPU能识别的地址格式，因此需要依据设定的地址转换规则，将地址信息转换为CPU可识别的真实地址信息。
在实际应用中，可以将所涉及的CPU地址信息进行汇总，建立地址转换列表，其中，地址转换列表中记录有各I2C协议地址信息及其各自对应的中央处理器可识别的地址信息。在本申请实施例中，可以将中央处理器可识别的地址信息称作真实地址信息。
相应的，CPLD在解析出地址信息之后，可以从设定的地址转换列表中查询与地址信息匹配的真实地址信息。
如下表1为地址转换列表，表1中序号用于区分不同的地址信息，I2C协议地址指的是I2C协议中平台环境控制地址，其以二进制的形式呈现。真实地址以十六进制的形式呈现。
表1
GPIO可以用于传输波形数据，因此CPLD在从待处理任务中提取出包含的命令类型、命令参数以及地址信息，并将地址信息转换为中央处理器可识别的真实地址信息之后，可以将命令类型、命令参数以及真实地址信息转换为波形数据。
波形数据为中央处理器的平台环境控制总线所支持的模拟信号。
命令类型的数量有限，并且每种命令类型属于固定信息，为了提升波形数据的转换效率，可以预先存储不同命令类型各自对应的波形。为了便于区分，可以将命令类型对应的波形称作命令波形，将具体数据如命令参数、地址信息等对应的波形称作信息波形。
在具体实现中，CPLD可以从预先存储的命令波形中查询与命令类型匹配的目标命令波形；将命令参数与真实地址信息转换为信息波形；将目标命令波形与信息波形合并作为波形数据。
S103：将波形数据传输至中央处理器。
CPLD设置有GPIO接口，CPU上会分配相应的平台环境控制专口，通过平台环境控制总线实现与GPIO接口的连接。在实际应用中，服务器系统包含的CPU数量较多，CPLD通过平台环境控制总线可以将波形数据传输至所有CPU。
S104：接收目标中央处理器反馈的响应数据。
其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器。
每台CPU均可以对波形数据进行分析，解析出命令类型、命令参数和真实地址信息。每台CPU会将波形数据携带的真实地址信息与自身的地址信息进行比较，若波形数据携带的真实地址信息与自身的地址信息一致，则基于命令类型和命令参数，向CPLD反馈对应的响应数据。例如，命令类型为读取寄存器信息，命令参数中包含了寄存器的标识，则CPU可以依赖该标识确定具体对应的寄存器，从而将该寄存器中记录的信息读取出来，将读取出的寄存器信息作为响应数据反馈至CPLD。
举例说明，待处理任务为读取目标中央处理器的温度信息的情况下，响应数据可以包括目标中央处理器的温度信息；在待处理任务为读取目标中央处理器中目标寄存器信息的情况下，响应数据可以包括目标寄存器的寄存器信息。
S105：将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。
在实际应用中，为了保证数据传输的准确性，CPU向CPLD反馈的响应数据往往会携带校验信息。
CPLD在获取到响应数据之后，可以按照中央处理器对应的数据传输格式，从响应数据中解析出校验信息和初始有效数据。利用校验信息对响应数据进行校验。在响应数据通过校验并且接收到基板管理控制器传输的读取请求的情况下，将初始有效数据转换为与读取请求对应的数据格式匹配的有效数据。其中，校验信息可以是CRC(Cyclic Redundancy Check，循环冗余校验码)。
在本申请实施例中，可以设置基于I2C的平台环境控制传输协议，该协议用于完成BMC与CPLD间基于I2C的平台环境控制命令交互及数据收发功能。基于该传输协议，BMC通过I2C总线向CPLD发起写命令的消息格式如图2所示，BMC通过I2C总线向CPLD发起读命令的消息格式如图3所示。
图2中slave地址表示CPLD的地址；是读写操作标识位，其取值为0时表示写操作，其取值为1时表示读操作。图2中每个字节之间设置的确认信号(ACK)为需要CPLD填写的信号。图2中B7至B3这5比特可以用于记录命令码。B2至B0这3比特用于记录平台环境控制地址，平台环境控制地址指的是所需访问的CPU的地址。平台环境控制命令参数可以依次填写至后续的字节中。
以BMC向CPLD下发读任务为例，在实际应用中，CPLD可以将读取请求对应的字符串中读写操作标识位设置为读标识；将初始有效数据依次填写至字符串中与读标识相邻的空闲字段，以得到有效数据。
图3中读命令中携带有两个slave地址，这两个slave地址均是表示CPLD的地址。第一个slave地址后面记录的表示BMC写入命令码和平台环境控制地址。第二个slave地址后面记录的表示由CPLD返回的有效数据。
结合上述介绍可知，本申请实施例中，通过CPLD与BMC以及CPU的交互，可以及时快速的向BMC反馈CPU的温度数据、寄存器信息等，以便于BMC实现对CPU的监管。
根据BMC、CPLD所需实现的功能，可以在BMC中设置命令映射模块和有效数据提取模块。在CPLD中设置命令匹配模块、波形触发模块和有效数据解析模块。在各CPU上可以设置平台环境控制专口，以通过平台环境控制总线实现与CPLD的交互。
图4为本申请实施例提供的一种基于CPLD的平台环境控制链路的系统框图，BMC和CPLD之间通过I2C总线连接，CPLD和CPU之间通过平台环境控制总线连接。图4中是以两台CPU为例，分别为CPU0和CPU1。在实际应用中，可以包含更多台CPU。
以BMC向CPLD下发连接任务为例，BMC向CPLD下发的连接任务可以采用Ping命令。BMC首先通过命令映射模块将Ping命令转换为命令码。其中，不同命令对应的命令码可自定义。假设Ping命令对应的命令码为5比特数据：5’b00001。值得注意的是，命令映射模块除了将Ping命令转换为命令码，同时完成对命令码及平台环境控制地址的比特字节拼接功能。假设平台环境控制地址为3比特数据：3’b000。CPU0与CPU1的client地址分别为0x30和0x31。拼接后的字节中命令码占字节的高5比特，平台环境控制地址占字节的低3比特，拼接形式可以参见图2，在此不做赘述。
BMC生成命令码与平台环境控制地址的拼接字节后，确认CPLD的slave地址、平台环境控制命令参数1……平台环境控制命令参数N。对于Ping命令而言，需要携带的平台环境控制命令参数包括Write Length和Read Length两个字节，紧接着依据图2所示的消息命令格式通过BMC与CPLD间的I2C通道进行数据传输。
CPLD通过I2C通道接收到BMC发来的数据后，通过命令匹配模块提取命令码与平台环境控制地址，然后与本地命令列表对比，即可识别BMC下发的是Ping命令。其中，本地命令列表中可以基于不同命令码各自对应的命令类型。
CPLD识别到Ping命令后，首先根据上述表1将平台环境控制地址转换为真实的平台环境控制地址，假设转换后的地址为0x30。随后启动波形触发模块，产生匹配的Ping命令波形，并通过GPIO引脚发送至平台环境控制总线。
CPU0与CPU1的平台环境控制专口侦听平台环境控制总线状态，当“感知”到总线存在请求数据时，首先对Ping命令波形进行解析，得到地址为0x30。这时CPU0与CPU1分别与自身的平台环境控制地址进行对比。CPU1发现与自己地址不匹配，则不响应；CPU0发现与自己地址匹配，则发送Ping命令的响应数据(Ping命令的响应数据可以为一个字节大小的CRC校验信息，定义为帧校验序列(Frame Check Sequence，FCS))至平台环境控制总线。
CPLD通过GPIO引脚从平台环境控制总线上接收CPU的响应数据，并通过有效数据解析模块解析出响应数据携带的校验信息。有效数据解析模块首先需要对响应数据进行CRC校验，若校验通过则提取除FCS数据以外的响应数据作为解析后的有效数据。
需要说明的是，CPLD解析后的有效数据还需要进行格式转换才能反馈给BMC，为了便于区分，可以将格式转换前的有效数据称作初始有效数据。
在实际应用中，为了后续告知BMC在平台环境控制总线上是否存在地址为0x30的client设备，可以回复一个字节的有效数据。
CPLD在接收到CPU反馈的连通成功的响应信息的情况下，可以将连接任务对应的字符串中连通标识位设置为连通成功标识；将设置连通成功标识的字符串作为有效数据反馈至基 板管理控制器。
例如，可以使用图3的返回有效数据1实现该功能，当其值为0x0时表示Ping命令无法Ping通0x30设备，值为0x1时表示Ping命令可以Ping通0x30设备。
BMC通过I2C总线依据图3的消息格式向CPLD发起平台环境控制命令读操作，CPLD将返回有效数据至I2C总线。然后BMC通过I2C通道接收来自CPLD返回的有效数据，并通过有效数据提取模块对有效数据进行提取。最后BMC对提取的有效数据进行处理。以Ping命令为例，BMC对提取的有效数据进行处理可以是判断有效数据是否是0x1。如果是，则表示平台环境控制总线上存在地址为0x30的client设备。若是其他平台环境控制命令(Ping命令以外的命令)，则依据控制协议规范提取对应字节数返回的有效数据，用于其他处理。
对于上述提及的操作，涉及BMC的功能模块可以由BMC的固件实现，通常实现代码存放于BMC芯片的外部flash存储介质中，涉及CPLD的功能模块可以由CPLD的固件实现，CPLD的固件一般存储于CPLD内部的非易失性存储介质中。
对于图4所示的基于CPLD的平台环境控制链路的系统，在BMC及CPLD工作正常的情况下，总能实现由BMC至CPU的可靠通路，相比任务繁多且极有可能失效的ME通路，本申请提供的系统极大地提升了CPU温度获取及寄存器收集的成功率，解决了ME通道获取CPU温度及寄存器信息时造成服务器整体管理控制能力及效率低下的问题。
由上述技术方案可以看出，接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。在该技术方案中，可以由复杂可编程逻辑器件执行上述操作，复杂可编程逻辑器件属于服务器系统中原本包含的部件，不会增加服务器性能监管的硬件成本。基于复杂可编程逻辑器件可以在基板管理控制器与中央处理器间构建一条平台环境控制通道。基板管理控制器需要获取某台或某些中央处理器的相关数据时，可以直接向复杂可编程逻辑器件发送待处理任务，复杂可编程逻辑器件可以实现与中央处理器的交互，从而获取到所需的有效数据，将有效数据反馈至基板管理控制器。该实现过程充分利用了复杂可编程逻辑器件处理实时性强的特点，实现对中央处理器上数据的监控管理，显著提升了服务器系统中中央处理器信息收集的成功率，解决了传统方式中依赖ME通道获取中央处理器相关信息时造成服务器整体管理控制能力及效率低下的问题，同时还可以省去基板管理控制器中专门用于平台管理控制功能的控制器设计，进一步降低了芯片成本。
图5为本申请实施例提供的一种性能监管装置的结构示意图，适用于复杂可编程逻辑器件，装置包括第一接收单元51、第一转换单元52、传输单元53、第二接收单元54、第二转换单元55和反馈单元56；
第一接收单元51，设置为接收基板管理控制器传输的待处理任务；
第一转换单元52，设置为按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；
传输单元53，设置为将波形数据传输至中央处理器；
第二接收单元54，设置为接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；
第二转换单元55，设置为将响应数据转换为符合数据传输格式要求的有效数据；
反馈单元56，设置为将有效数据反馈至基板管理控制器。
在本申请的一些实施例中，第一转换单元包括提取子单元、地址转换子单元和波形转换子单元；
提取子单元，设置为根据设定的数据格式，从待处理任务中提取出包含的命令类型、命令参数以及地址信息；
地址转换子单元，设置为依据设定的地址转换规则，将地址信息转换为中央处理器可识别的真实地址信息；
波形转换子单元，设置为将命令类型、命令参数以及真实地址信息转换为波形数据。
在本申请的一些实施例中，地址转换子单元设置为从设定的地址转换列表中查询与地址信息匹配的真实地址信息；其中，地址转换列表中记录有各I2C协议地址信息及其各自对应的中央处理器可识别的地址信息。
在本申请的一些实施例中，波形转换子单元设置为从预先存储的命令波形中查询与命令类型匹配的目标命令波形；将命令参数与真实地址信息转换为信息波形；将目标命令波形与信息波形合并作为波形数据。
在本申请的一些实施例中，第二转换单元包括解析子单元、校验子单元和格式转换子单元；
解析子单元，设置为按照中央处理器对应的数据传输格式，从响应数据中解析出校验信息和初始有效数据；
校验子单元，设置为利用校验信息对响应数据进行校验；
格式转换子单元，设置为在响应数据通过校验并且接收到基板管理控制器传输的读取请求的情况下，将初始有效数据转换为与读取请求对应的数据格式匹配的有效数据。
在本申请的一些实施例中，格式转换子单元设置为将读取请求对应的字符串中读写操作标识位设置为读标识；将初始有效数据依次填写至字符串中与读标识相邻的空闲字段，以得到有效数据。
在本申请的一些实施例中，在待处理任务为连接任务的情况下，第二转换单元设置为在响应数据为连通成功的响应信息的情况下，将连接任务对应的字符串中连通标识位设置为连通成功标识；
反馈单元设置为将设置连通成功标识的字符串作为有效数据反馈至基板管理控制器。
在本申请的一些实施例中，在待处理任务为读取目标中央处理器的温度信息的情况下，相应的，响应数据包括目标中央处理器的温度信息；在待处理任务为读取目标中央处理器中目标寄存器信息的情况下，相应的，响应数据包括目标寄存器的寄存器信息。
图5所对应实施例中特征的说明可以参见图1所对应实施例的相关说明，这里不再一一赘述。
由上述技术方案可以看出，接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。在该技术方案中，可以由复杂可编程逻辑器件执行 上述操作，复杂可编程逻辑器件属于服务器系统中原本包含的部件，不会增加服务器性能监管的硬件成本。基于复杂可编程逻辑器件可以在基板管理控制器与中央处理器间构建一条平台环境控制通道。基板管理控制器需要获取某台或某些中央处理器的相关数据时，可以直接向复杂可编程逻辑器件发送待处理任务，复杂可编程逻辑器件可以实现与中央处理器的交互，从而获取到所需的有效数据，将有效数据反馈至基板管理控制器。该实现过程充分利用了复杂可编程逻辑器件处理实时性强的特点，实现对中央处理器上数据的监控管理，显著提升了服务器系统中中央处理器信息收集的成功率，解决了传统方式中依赖ME通道获取中央处理器相关信息时造成服务器整体管理控制能力及效率低下的问题，同时还可以省去基板管理控制器中专门用于平台管理控制功能的控制器设计，进一步降低了芯片成本。
本申请实施例还提供了一种性能监管方法，适用于基板管理控制器，方法包括：
向复杂可编程逻辑器件传输待处理任务；
接收复杂可编程逻辑器件反馈的有效数据；其中，有效数据为复杂可编程逻辑器件按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据后，将中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
从有效数据中提取出所需的数据。
在本申请的一些实施例中，向复杂可编程逻辑器件传输待处理任务包括：
将待发送的控制命令转换为命令码；
按照命令码对应的数据格式，将命令码、地址信息和命令参数转换为待处理任务。
本申请实施例还提供了一种性能监管装置，适用于基板管理控制器，装置包括传输单元、接收单元和提取单元；
传输单元，设置为向复杂可编程逻辑器件传输待处理任务；
接收单元，设置为接收复杂可编程逻辑器件反馈的有效数据；其中，有效数据为复杂可编程逻辑器件按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据后，将中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
提取单元，设置为从有效数据中提取出所需的数据。
本申请实施例还提供了一种性能监管方法，适用于中央处理器，方法包括：
在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；其中，波形数据为复杂可编程逻辑器件按照设定的数据转换规则，将接收到的基板管理控制器传输的待处理任务携带的数据转换为中央处理器可识别的波形数据；
在真实地址信息与自身地址匹配的情况下，向复杂可编程逻辑器件反馈任务信息对应的响应数据。
本申请实施例还提供了一种性能监管装置，适用于中央处理器，装置包括解析单元和反馈单元；
解析单元，设置为在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；其中，波形数据为复杂可编程逻辑器件按照设定的数据转换规则，将接收到的基板管理控制器传输的待处理任务携带的数据转换为中央处理器可识别的波形数据；
反馈单元，设置为在真实地址信息与自身地址匹配的情况下，向复杂可编程逻辑器件反馈任务信息对应的响应数据。
图6为本申请实施例提供的一种性能监管系统的结构示意图，包括基板管理控制器61，中央处理器62，分别与基板管理控制器61以及中央处理器62连接的复杂可编程逻辑器件63；中央处理器62的个数可以有多个，图6中以三个为例，在实际应用中可以有更多或更少个中央处理器62。
基板管理控制器61，用于向复杂可编程逻辑器件63传输待处理任务；接收复杂可编程逻辑器件63反馈的有效数据；从有效数据中提取出所需的数据；
复杂可编程逻辑器件63，用于接收基板管理控制器61传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器62可识别的波形数据；将波形数据传输至中央处理器62；接收目标中央处理器62反馈的响应数据；其中，目标中央处理器62为待处理任务中携带的地址信息所匹配的中央处理器62；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器61；
中央处理器62，用于在接收到复杂可编程逻辑器件63传输的波形数据的情况下，解析波形数据，以获取真实地址信息和任务信息；在真实地址信息与自身地址匹配的情况下，向复杂可编程逻辑器件63反馈任务信息对应的响应数据。
在本申请的一些实施例中，基板管理控制器用于将待发送的控制命令转换为命令码；按照命令码对应的数据格式，将命令码、地址信息和命令参数转换为待处理任务。
在本申请的一些实施例中，基板管理控制器从有效数据中提取出所需的数据包括：
基板管理控制器按照命令码对应的数据格式，从有效数据中提取出有效数据字段对应的数据。
在本申请的一些实施例中，基板管理控制器与复杂可编程逻辑器件通过I2C总线连接，复杂可编程逻辑器件与中央处理器通过通用输入输出接口连接。
图6所对应实施例中特征的说明可以参见图1所对应实施例的相关说明，这里不再一一赘述。
由上述技术方案可以看出，接收基板管理控制器传输的待处理任务；按照设定的数据转换规则，将待处理任务携带的数据转换为中央处理器可识别的波形数据；将波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，目标中央处理器为待处理任务中携带的地址信息所匹配的中央处理器；将响应数据转换为符合数据传输格式要求的有效数据，将有效数据反馈至基板管理控制器。在该技术方案中，可以由复杂可编程逻辑器件执行上述操作，复杂可编程逻辑器件属于服务器系统中原本包含的部件，不会增加服务器性能监管的硬件成本。基于复杂可编程逻辑器件可以在基板管理控制器与中央处理器间构建一条平台环境控制通道。基板管理控制器需要获取某台或某些中央处理器的相关数据时，可以直接向复杂可编程逻辑器件发送待处理任务，复杂可编程逻辑器件可以实现与中央处理器的交互，从而获取到所需的有效数据，将有效数据反馈至基板管理控制器。该实现过程充分利用了复杂可编程逻辑器件处理实时性强的特点，实现对中央处理器上数据的监控管理，显著提升了服务器系统中中央处理器信息收集的成功率，解决了传统方式中依赖ME通道获取中央处理器相关信息时造成服务器整体管理控制能力及效率低下的问题，同时还可以省去基板管理控制器中专门用于平台管理控制功能的控制器设计，进一步降低了芯片成本。
图7为本申请实施例提供的一种电子设备的结构图，如图7所示，电子设备包括：存储器20，用于存储计算机程序；
处理器21，用于执行计算机程序时实现如上述实施例性能监管方法的步骤。
本申请实施例提供的电子设备可以包括但不限于智能手机、平板电脑、笔记本电脑或台式电脑等。
其中，处理器21可以包括一个或多个处理核心，比如4核心处理器、8核心处理器等。处理器21可以采用DSP(Digital Signal Processing，数字信号处理)、FPGA(Field-Programmable Gate Array，现场可编程门阵列)、PLA(Programmable Logic Array，可编程逻辑阵列)中的至少一种硬件形式来实现。处理器21也可以包括主处理器和协处理器，主处理器是用于对在唤醒状态下的数据进行处理的处理器，也称CPU(Central Processing Unit，中央处理器)；协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中，处理器21可以在集成有GPU(Graphics Processing Unit，图像处理器)，GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中，处理器21还可以包括AI(Artificial Intelligence，人工智能)处理器，该AI处理器用于处理有关机器学习的计算操作。
存储器20可以包括一个或多个计算机非易失性可读存储介质，该计算机非易失性可读存储介质可以是非暂态的。存储器20还可包括高速随机存取存储器，以及非易失性存储器，比如一个或多个磁盘存储设备、闪存存储设备。本申请实施例中，存储器20至少用于存储以下计算机程序201，其中，该计算机程序被处理器21加载并执行之后，能够实现前述任一实施例公开的性能监管方法的相关步骤。另外，存储器20所存储的资源还可以包括操作系统202和数据203等，存储方式可以是短暂存储或者永久存储。其中，操作系统202可以包括Windows、Unix、Linux等。数据203可以包括但不限于数据转换规则、数据传输格式要求等。
在一些实施例中，电子设备还可包括有显示屏22、输入输出接口23、通信接口24、电源25以及通信总线26。
本领域技术人员可以理解，图7中示出的结构并不构成对电子设备的限定，可以包括比图示更多或更少的组件。
可以理解的是，如果上述实施例中的性能监管方法以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，执行本申请各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、电可擦除可编程ROM、寄存器、硬盘、可移动磁盘、CD-ROM、磁碟或者光盘等各种可以存储程序代码的介质。
基于此，本申请实施例还提供了一种计算机非易失性可读存储介质，计算机非易失性可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述性能监管方法的步骤。
以上对本申请实施例所提供的一种性能监管方法、装置、系统、设备和计算机非易失性可读存储介质进行了详细介绍。说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实 施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
以上对本申请所提供的一种性能监管方法、装置、系统、设备和计算机非易失性可读存储介质进行了详细介绍。本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。

Claims (20)

  1. 一种性能监管方法，包括：
    接收基板管理控制器传输的待处理任务；
    按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波形数据；
    将所述波形数据传输至中央处理器；
    接收目标中央处理器反馈的响应数据；其中，所述目标中央处理器为所述待处理任务中携带的地址信息所匹配的中央处理器；
    将所述响应数据转换为符合数据传输格式要求的有效数据，将所述有效数据反馈至所述基板管理控制器。
  2. 根据权利要求1所述的性能监管方法，其中，所述按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波形数据包括：
    根据设定的数据格式，从所述待处理任务中提取出包含的命令类型、命令参数以及地址信息；
    依据设定的地址转换规则，将所述地址信息转换为中央处理器可识别的真实地址信息；
    将所述命令类型、所述命令参数以及所述真实地址信息转换为波形数据。
  3. 根据权利要求2所述的性能监管方法，其中，所述依据设定的地址转换规则，将所述地址信息转换为中央处理器可识别的真实地址信息包括：
    从设定的地址转换列表中查询与所述地址信息匹配的真实地址信息；其中，所述地址转换列表中记录有各I2C协议地址信息及其各自对应的中央处理器可识别的地址信息。
  4. 根据权利要求2所述的性能监管方法，其中，所述将所述命令类型、所述命令参数以及所述真实地址信息转换为波形数据包括：
    从预先存储的命令波形中查询与所述命令类型匹配的目标命令波形；
    将所述命令参数与所述真实地址信息转换为信息波形；
    将所述目标命令波形与所述信息波形合并作为波形数据。
  5. 根据权利要求2所述的性能监管方法，其中，所述将所述响应数据转换为符合数据传输格式要求的有效数据包括：
    按照所述中央处理器对应的数据传输格式，从所述响应数据中解析出校验信息和初始有效数据；
    利用所述校验信息对所述响应数据进行校验；
    在所述响应数据通过校验并且接收到所述基板管理控制器传输的读取请求的情况下，将所述初始有效数据转换为与所述读取请求对应的数据格式匹配的有效数据。
  6. 根据权利要求5所述的性能监管方法，其中，所述将所述初始有效数据转换为与所述读取请求对应的数据格式匹配的有效数据包括：
    将所述读取请求对应的字符串中读写操作标识位设置为读标识；
    将所述初始有效数据依次填写至所述字符串中与所述读标识相邻的空闲字段，以得到有效数据。
  7. 根据权利要求1所述的性能监管方法，其中，在所述待处理任务为连接任务的情况下，所述将所述响应数据转换为符合数据传输格式要求的有效数据，将所述有效数据反馈至所述基板管理控制器包括：
    在所述响应数据为连通成功的响应信息的情况下，将所述连接任务对应的字符串中连通标识位设置为连通成功标识；
    将设置连通成功标识的字符串作为有效数据反馈至所述基板管理控制器。
  8. 根据权利要求1至7任意一项所述的性能监管方法，其中，在所述待处理任务为读取目标中央处理器的温度信息的情况下，相应的，所述响应数据包括所述目标中央处理器的温度信息；在所述待处理任务为读取目标中央处理器中目标寄存器信息的情况下，相应的，所述响应数据包括所述目标寄存器的寄存器信息。
  9. 一种性能监管装置，适用于复杂可编程逻辑器件，所述装置包括第一接收单元、第一转换单元、传输单元、第二接收单元、第二转换单元和反馈单元；
    所述第一接收单元，设置为接收基板管理控制器传输的待处理任务；
    所述第一转换单元，设置为按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波形数据；
    所述传输单元，设置为将所述波形数据传输至中央处理器；
    所述第二接收单元，设置为接收目标中央处理器反馈的响应数据；其中，所述目标中央处理器为所述待处理任务中携带的地址信息所匹配的中央处理器；
    所述第二转换单元，设置为将所述响应数据转换为符合数据传输格式要求的有效数据；
    所述反馈单元，设置为将所述有效数据反馈至所述基板管理控制器。
  10. 一种性能监管方法，适用于基板管理控制器，所述方法包括：
    向复杂可编程逻辑器件传输待处理任务；
    接收所述复杂可编程逻辑器件反馈的有效数据；其中，所述有效数据为所述复杂可编程逻辑器件按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波形数据后，将所述中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
    从所述有效数据中提取出所需的数据。
  11. 根据权利要求10所述的性能监管方法，其中，所述向复杂可编程逻辑器件传输待处理任务包括：
    将待发送的控制命令转换为命令码；
    按照所述命令码对应的数据格式，将所述命令码、地址信息和命令参数转换为待处理任务。
  12. 一种性能监管装置，适用于基板管理控制器，所述装置包括传输单元、接收单元和提取单元；
    所述传输单元，设置为向复杂可编程逻辑器件传输待处理任务；
    所述接收单元，设置为接收所述复杂可编程逻辑器件反馈的有效数据；其中，所述有效数据为所述复杂可编程逻辑器件按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波形数据后，将所述中央处理器反馈的响应数据转换为符合数据传输格式要求的有效数据；
    所述提取单元，设置为从所述有效数据中提取出所需的数据。
  13. 一种性能监管方法，适用于中央处理器，所述方法包括：
    在接收到复杂可编程逻辑器件传输的波形数据的情况下，解析所述波形数据，以获取真实地址信息和任务信息；其中，所述波形数据为所述复杂可编程逻辑器件按照设定的数据转换规则，将接收到的基板管理控制器传输的待处理任务携带的数据转换为所述中央处理器可识别的波形数据；
    在所述真实地址信息与自身地址匹配的情况下，向所述复杂可编程逻辑器件反馈所述任务信息对应的响应数据。
  14. 一种性能监管系统，包括基板管理控制器，中央处理器，分别与所述基板管理控制器以及所述中央处理器连接的复杂可编程逻辑器件；
    所述基板管理控制器，用于向所述复杂可编程逻辑器件传输待处理任务；接收所述复杂可编程逻辑器件反馈的有效数据；从所述有效数据中提取出所需的数据；
    所述复杂可编程逻辑器件，用于接收所述基板管理控制器传输的所述待处理任务；按照设定的数据转换规则，将所述待处理任务携带的数据转换为中央处理器可识别的波 形数据；将所述波形数据传输至中央处理器；接收目标中央处理器反馈的响应数据；其中，所述目标中央处理器为所述待处理任务中携带的地址信息所匹配的中央处理器；将所述响应数据转换为符合数据传输格式要求的有效数据，将所述有效数据反馈至所述基板管理控制器；
    所述中央处理器，用于在接收到所述复杂可编程逻辑器件传输的波形数据的情况下，解析所述波形数据，以获取真实地址信息和任务信息；在所述真实地址信息与自身地址匹配的情况下，向所述复杂可编程逻辑器件反馈所述任务信息对应的响应数据。
  15. 根据权利要求14所述的性能监管系统，其中，所述基板管理控制器用于将待发送的控制命令转换为命令码；按照所述命令码对应的数据格式，将所述命令码、地址信息和命令参数转换为待处理任务。
  16. 根据权利要求15所述的性能监管系统，其中，所述基板管理控制器从所述有效数据中提取出所需的数据包括：
    所述基板管理控制器按照所述命令码对应的数据格式，从所述有效数据中提取出有效数据字段对应的数据。
  17. 根据权利要求14所述的性能监管系统，其中，所述基板管理控制器与所述复杂可编程逻辑器件通过I2C总线连接，所述复杂可编程逻辑器件与所述中央处理器通过通用输入输出接口连接。
  18. 根据权利要求14所述的性能监管系统，其中，所述复杂可编程逻辑器件用于根据设定的数据格式，从所述待处理任务中提取出包含的命令类型、命令参数以及地址信息；依据设定的地址转换规则，将所述地址信息转换为中央处理器可识别的真实地址信息；将所述命令类型、所述命令参数以及所述真实地址信息转换为波形数据。
  19. 一种电子设备，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序以实现如权利要求1至8任意一项所述性能监管方法的步骤。
  20. 一种计算机非易失性可读存储介质，所述计算机非易失性可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至8任意一项所述性能监管方法的步骤。
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