WO2024108891A1 - Governor and governor control method - Google Patents

Abstract

A governor and a governor control method. The governor comprises: two control circuits, each control circuit comprising two processors, the four processors being connected to each other, and the types of two processors in a same control circuit being different. When a processor in a master control circuit (11) fails, the failed processor in the master control circuit (11) sends synchronization information to a first target processor in a slave control circuit (12), so that the first target processor is connected to a second target processor to form a target data transmission channel so as to achieve data transmission. The first target processor is a processor in the slave control circuit (12) having the same type as the failed processor, and the types of the second target processor and the first target processor are different. By using the governor, a system failure caused by a single point of failure can be avoided.

Description

Speed governor and speed governor control method

Related Applications

This application claims priority to Chinese patent application number 202211463523.0, filed on November 22, 2022, and entitled “Speed Regulator and Control Method of Speed Regulator”, the entire text of which is hereby incorporated by reference.

Technical Field

The present application relates to the technical field of nuclear power plant speed equipment control, and in particular to a speed governor and a speed governor control method.

Background technique

In the design of nuclear power plant process system, the feedwater flow control system controls the water demand of the secondary circuit of the entire nuclear power plant. The feedwater flow control system changes the water supply flow and pressure based on the speed regulation of the steam-driven main feedwater pump to supply water to the three steam generators, while eliminating the feedwater coupling phenomenon between the three steam generators, to ensure that the pressure difference between the steam generator feedwater main pipe and the steam main pipe is equal to a set value that changes with the unit load. Therefore, the speed regulation of the steam-driven main feedwater pump plays a vital role in maintaining the water level of the steam generator and ensuring the safety of the unit.

Currently, the speed governor of steam turbines is mostly controlled by electronic speed governors or a single control system. The system reliability is low and shutdowns are often caused by single-point failures.

Summary of the invention

Based on this, it is necessary to provide a speed regulator and a control method for the speed regulator with a high degree of redundancy that can avoid single point failures in order to address the above technical problems.

In order to achieve the above-mentioned and other purposes, one aspect of the present application provides a speed regulator, comprising: two control circuits, each of the control circuits comprising two processors, the four processors being connected to each other, and the two processors in the same control circuit being of different types;

When a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor is connected to the second target processor to form a target data transmission path to achieve data transmission;

Among them, the first target processor is a processor in the slave control circuit that is of the same type as the fault processor, the second target processor is of a different type from the first target processor, the master control circuit is one of the two control circuits, and the slave control circuit is the other of the two control circuits.

In one embodiment, when one processor in the main control circuit fails, the second target processor is a normal processor in the main control circuit; when both processors in the main control circuit fail, the second target processor is a processor in the slave control circuit.

In one embodiment, the processor to be diagnosed in the main control circuit sends inspection information to the other three processors respectively, so that the other three processors generate diagnostic information according to the inspection information;

The speed regulator also includes:

an arbitration module, connected to the four processors respectively, for determining whether the processor to be diagnosed is faulty according to the diagnostic information output by the other three processors, and outputting the diagnostic result of the processor to be diagnosed to the other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

In one embodiment, the arbitration module includes four arbitration circuits, each of the processors to be diagnosed is configured with one arbitration circuit, each of the arbitration circuits is connected to the other three processors respectively, and the other three processors are processors other than the processor to be diagnosed configured with the arbitration circuit; the arbitration circuit includes: three arbitration circuits Unit, two input ends of each arbitration unit are respectively connected to two processors of the other three processors, the output end of each arbitration unit is respectively connected to the other three processors, and one input end of every two arbitration units is connected to the same processor, each arbitration unit comprises: a NAND gate and an inverter, wherein,

The two input ends of the NAND gate are respectively connected to two processors among the other three processors, and the output end of the NAND gate is connected to the input end of the inverter;

The output ends of the inverter are connected to the other three processors respectively.

In one embodiment, the speed regulator further includes a first isolation circuit, and the two processors in the master control circuit are respectively connected to the two processors of the slave control circuit via the first isolation circuit; the first isolation circuit includes:

a first isolation unit, connected to the first processor of the master control circuit and the first processor of the slave control circuit respectively;

a second isolation unit, connected to the first processor of the master control circuit and the second processor of the slave control circuit respectively;

A third isolation unit is connected to the second processor of the master control circuit and the first processor of the slave control circuit respectively; and

a fourth isolation unit, connected to the second processor of the master control circuit and the second processor of the slave control circuit respectively; wherein the first processor of the master control circuit and the first processor of the slave control circuit are of the same type;

When the diagnosis result shows that the processor to be diagnosed is a faulty processor, the other three processors respectively control the isolation units connected to the faulty processor according to the diagnosis result to disconnect the data transmission paths connected to the faulty processor respectively.

In one embodiment, the speed regulator further comprises:

a first input acquisition circuit, connected to the master control circuit and the slave control circuit respectively, for acquiring and processing received analog input signals, and transmitting the processed analog input signals to a target control circuit;

a first output processing circuit, connected to the master control circuit and the slave control circuit respectively, and used for receiving and processing the analog output signal from the target control circuit;

a second input acquisition circuit, connected to the master control circuit and the slave control circuit respectively, for acquiring and processing received switch input signals, and transmitting the processed switch input signals to the target control circuit; and,

The second output processing circuit is connected to the main control circuit and the slave control circuit respectively, and is used to receive and process the switch output signal from the target control circuit; wherein the target control circuit is one of the two control circuits.

In one embodiment, the first input acquisition circuit includes an analog-to-digital converter, and the first output processing circuit includes a digital-to-analog converter.

In one embodiment, the speed regulator further comprises:

A second isolation circuit is connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the main control circuit respectively; and,

a third isolation circuit, connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the slave control circuit, respectively; wherein the second processor of the master control circuit is of the same type as the second processor of the slave control circuit;

When the processor in the main control circuit has no fault, the main control circuit controls the third isolation circuit to be in a locked state;

When the second processor in the main control circuit fails, the main control circuit controls the second isolation circuit to be in a locked state.

In one embodiment, the second input acquisition circuit includes a first photoelectric isolator for isolating the acquired switch input signal; the second output processing circuit includes a second photoelectric isolator for isolating the received switch output signal; the second isolation circuit includes:

A first magnetic isolator is connected to the first input acquisition circuit and the second processor of the main control circuit respectively;

A second magnetic isolator is connected to the first output processing circuit and the second processor of the main control circuit respectively; and

A third magnetic isolator is connected to the first photoelectric isolator, the second photoelectric isolator, and the second processor of the main control circuit respectively;

The third isolation circuit comprises:

a fourth magnetic isolator, connected to the first input acquisition circuit and the second processor of the slave control circuit respectively;

a fifth magnetic isolator connected to the first output processing circuit and the second processor of the slave control circuit respectively; and

The sixth magnetic isolator is connected to the first photoelectric isolator, the second photoelectric isolator, and the second processor of the slave control circuit respectively.

In one embodiment, the speed regulator further comprises:

a power supply module, connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and each of the control circuits, respectively, and used to provide a power supply voltage;

Wherein, the power module comprises:

An inverter unit, used for receiving an external power supply voltage and performing voltage drop processing on the power supply voltage to obtain a voltage drop voltage;

a first system power supply unit, connected to the inverter unit, for rectifying, regulating and filtering the voltage drop voltage to obtain a first power supply voltage, and outputting the first power supply voltage to the main control circuit;

a second system power supply unit connected to the inverter unit, for rectifying, regulating and filtering the voltage drop voltage to obtain a second power supply voltage, and outputting the second power supply voltage to the slave control circuit; and,

An interface power supply unit is connected to the inverter unit, and is used to rectify, regulate, and filter the voltage drop voltage to obtain a third power supply voltage, and output it to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, and the second output processing circuit.

In one of the embodiments, when a processor in a main control circuit fails, the faulty processor in the main control circuit sends synchronization information to a first target processor in a slave control circuit, so that the first target processor is connected to a second target processor in the main control circuit via another processor in the slave control circuit to form a target data transmission path, thereby realizing data transmission.

In one embodiment, the speed regulator further comprises:

A verification module, connected to the four processors respectively, for determining whether the processor to be diagnosed is faulty and outputting the diagnosis result of the processor to be diagnosed to the other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.

In one of the embodiments, the speed regulator further includes a human-machine interface.

In one embodiment, the master control circuit includes a first CPU and a first FPGA, and the slave control circuit includes a second CPU and a second FPGA.

Another aspect of the present application provides a control method for a speed regulator, which is applied to the speed regulator as described in any one of the above embodiments, and the method includes:

Acquire the temperature value according to the signal to be started to determine the start state;

When the startup state is a hot startup state, controlling the speed of the steam turbine to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed;

When the startup state is a cold start state, the speed of the steam turbine is controlled to increase at a second preset rate until the real-time speed of the steam turbine is greater than or equal to the second preset speed and then enters a warm-up state; after a preset time, the speed of the steam turbine is controlled to continue to increase at the second preset rate until the real-time speed of the steam turbine is greater than or equal to a third preset speed, and then the speed of the steam turbine is controlled to increase at the first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed; and,

The speed of the steam turbine is adjusted according to the set speed based on the startup completion signal.

The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without paying any creative work.

FIG1 is a structural block diagram of a speed regulator provided in a first embodiment of the present application;

FIG2 is a structural block diagram of a speed regulator provided in a second embodiment of the present application;

FIG3 is a schematic diagram of the structure of a first arbitration circuit provided in an embodiment of the present application;

FIG4 is a structural block diagram of a speed regulator provided in a third embodiment of the present application;

FIG5 is a structural block diagram of a speed regulator provided in a fourth embodiment of the present application;

FIG6 is a schematic diagram of a first input acquisition circuit provided in an embodiment of the present application;

FIG7 is a schematic diagram of a first output processing circuit provided in an embodiment of the present application;

FIG8 is a schematic diagram of a second input acquisition circuit provided in an embodiment of the present application;

FIG9 is a schematic diagram of a second output processing circuit provided in an embodiment of the present application;

FIG10 is a structural block diagram of a speed regulator provided in a fifth embodiment of the present application;

FIG11 is a structural block diagram of a power supply module provided in an embodiment of the present application;

FIG. 12 is a structural block diagram of a speed regulator provided in the sixth embodiment of the present application.

FIG. 13 is a flow chart of a method for controlling a speed regulator provided in an embodiment of the present application.

Description of reference numerals:

10. Speed regulator; 11. Main control circuit; 111. First processor; 112. Second processor; 12. Slave control circuit; 121. Third processor; 122. Fourth processor; 13. Arbitration module; 131. Arbitration circuit; 1311. First arbitration unit; 1312. Second arbitration unit; 1313. Third arbitration unit; 132. NAND gate; 133. Inverter; 14. First isolation circuit; 141. First isolation unit; 142. Second isolation unit; 143. Third isolation unit; 144. Fourth isolation unit; 15. First input acquisition circuit; 151. Analog-to-digital converter; 152. First field effect transistor; 153. Voltage divider circuit; 154. First operational amplifier; 155. Voltage follower; 16. First output processing circuit; 16 1. Digital-to-analog converter; 162. Second operational amplifier; 163. Third operational amplifier; 164. Fourth operational amplifier; 165. Fifth operational amplifier; 166. Second field effect transistor; 167. Third field effect transistor; 17. Second input acquisition circuit; 171. First photoelectric isolator; 18. Second output processing circuit; 181. Second photoelectric isolator; 19. Second isolation circuit; 191. First magnetic isolator; 192. Second magnetic isolator; 193. Third magnetic isolator; 20. Third isolation circuit; 201. Fourth magnetic isolator; 202. Fifth magnetic isolator; 203. Sixth magnetic isolator; 21. Power supply module; 211. Inverter unit; 212. First system power supply unit; 213. Second system power supply unit; 214. Interface power supply unit.

Detailed ways

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.

It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

As shown in FIG. 1 , in one embodiment, a speed regulator 10 is provided. The speed regulator 10 includes two control circuits. Each control circuit includes two processors. The four processors are connected to each other. The types of the two processors in the same control circuit are different.

The two processors in the main control circuit 11 are of different types, the two processors in the slave control circuit 12 are of different types, and the two processors in the slave control circuit 12 are of the same type as the two processors in the main control circuit 11. For example, the first processor in the main control circuit 11 is of the same type as the first processor in the slave control circuit 12, and the second processor in the main control circuit 11 is of the same type as the second processor in the slave control circuit 12. The processor includes at least a central processing unit (CPU) and a field programmable gate array (FPGA).

Exemplarily, the two processors in the main control circuit 11 can be used as the first processor 111 and the second processor 112 of the speed regulator 10, respectively, and the two processors in the slave control circuit 12 can be used as the third processor 121 and the fourth processor 122 of the speed regulator 10, respectively. The first processor 111 can be a first CPU, and the second processor 112 can be a first FPGA; the third processor 121 can be a second CPU, and the fourth processor 122 can be a second FPGA. The first CPU is connected to the first FPGA, the second CPU, and the second FPGA respectively; the first FPGA is connected to the second CPU and the second FPGA respectively; the second CPU is connected to the second FPGA.

When the system starts to operate, the main control circuit 11 includes a target data transmission path, that is, the first CPU is connected to the first FPGA to form a target data transmission path to achieve data transmission. The slave control circuit 12 may also include a target data transmission path, that is, the second CPU is connected to the second FPGA to form a target data transmission path to achieve data transmission.

Optionally, when a processor in the main control circuit 11 fails, the faulty processor in the main control circuit 11 sends synchronization information to the first target processor in the slave control circuit 12, so that the first target processor is connected to the second target processor in the main control circuit 11 via another processor in the slave control circuit 12 to form a target data transmission path to achieve data transmission.

Taking the main control circuit 11 as the target data transmission path as an example, when the processor in the main control circuit 11 fails, the faulty processor in the main control circuit 11 sends synchronization information to the first target processor in the slave control circuit 12, so that the first target processor is connected to the second target processor to form a target data transmission path to realize data transmission.

The first target processor is a processor of the same type as the fault processor in the slave control circuit 12, and the second target processor is of a different type from the first target processor. Synchronization information is information that can characterize the data processed or transmitted by the fault processor before the fault. Among the four processors, since only synchronization information needs to be transmitted between two of the same type, serial communication is used for communication; since data transmission needs to be realized between two processors of different types and the amount of data transmitted is large, in order to ensure data transmission efficiency, parallel communication is used for communication.

Optionally, when a processor in the main control circuit 11 fails, the second target processor becomes a normal processor in the main control circuit 11. For example, when the first CPU fails, the first target processor is the second CPU, the second target processor is the first FPGA, and the first CPU sends synchronization information to the second CPU in the slave control circuit 12, so that the second CPU is connected to the first FPGA to form a target data transmission path to achieve data transmission; when the first FPGA fails, the first target processor is the second FPGA, the second target processor is the first CPU, and the first FPGA sends synchronization information to the second FPGA in the slave control circuit 12, so that the first CPU is connected to the second FPGA to form a target data transmission path to achieve data transmission.

Optionally, when both processors in the main control circuit 11 fail, the second target processor is the processor in the slave control circuit 12. For example, when both the first CPU and the first FPGA fail, the first CPU sends synchronization information to the second CPU, and the first FPGA sends synchronization information to the second FPGA, so that the second CPU is connected to the second FPGA to form a target data transmission path to achieve data transmission.

In the speed regulator 10, two different types of processors in the main control circuit 11 realize data transmission through parallel port communication. Through the setting of the slave control circuit 12, when the processor in the main control circuit 11 fails, the faulty processor transmits synchronization information to the processor of the same type as the faulty processor in the slave control circuit 12 through serial communication, and is replaced by the processor of the same type as the faulty processor in the slave control circuit 12, and continues to process the data to be processed by the faulty processor, and realizes data transmission with the processor without fault in the main control circuit 11. If all the processors in the main control circuit 11 fail, data processing and transmission are performed through the two processors of the slave control circuit 12. The design of the dual control circuit avoids the occurrence of system failures caused by single point failures.

As shown in FIG2 , in one embodiment, the speed regulator 10 further includes an arbitration module 13, which is respectively connected to four processors. The blanking module includes four arbitration circuits, each processor to be diagnosed is configured with an arbitration circuit, each arbitration circuit is respectively connected to the other three processors, and the other three processors are processors other than the processor to be diagnosed configured with the arbitration circuit. The arbitration circuit includes three arbitration units, the two input ends of each arbitration unit are respectively connected to two processors of the other three processors, the output ends of each arbitration unit are respectively connected to the other three processors, and one input end of every two arbitration units is connected to the same processor, and each arbitration unit includes a NAND gate 132 and an inverter 133.

Taking the first processor 111 as the processor to be diagnosed, the first processor 111 in the main control circuit 11 sends inspection information to the second processor 112, the third processor 121 and the fourth processor 122 respectively, and the second processor 112, the third processor 121 and the fourth processor 122 generate diagnostic information according to the inspection information. The arbitration circuit 131 configured by the first processor 111 is shown in FIG3. If the diagnosis result of the other three processors for the first processor 111 is a fault, a high level is output. The NAND gate 132 in the first arbitration unit 1311 is connected to the second processor 112 and the fourth processor 122 respectively, the NAND gate 132 in the second arbitration unit 1312 is connected to the second processor 112 and the third processor 121 respectively, and the NAND gate 132 in the third arbitration unit 1313 is connected to the third processor 121 and the fourth processor 122 respectively. The three arbitration circuits 131 use a two-out-of-three method to determine whether the first processor 111 is faulty. For example, if the second processor 112, the third processor 121, and the fourth processor 122 are all judged to be normal and output a low level, then in the first arbitration circuit 131, the second arbitration circuit 131, and the third arbitration circuit 131, the NAND gate 132 outputs a high level, the inverter 133 outputs a low level, and finally the first arbitration circuit 131 outputs a low level, and the first processor 111 has no fault; if the second processor 112 and the third processor 121 are judged to be normal and output a low level, and the fourth processor 122 is judged to be faulty and output a high level, then in the first arbitration circuit 131, the second arbitration circuit 131, and the third arbitration circuit 131, The NAND gate 132 outputs a high level, the inverter 133 outputs a low level, and finally the first arbitration circuit 131 outputs a low level, and the first processor 111 has no fault; if the second processor 112 and the third processor 121 judge that they are faulty and output a high level, and the fourth processor 122 judges that they are normal and outputs a low level, then the NAND gate 132 in the first arbitration circuit 131 and the third arbitration circuit 131 outputs a high level, and the inverter 133 outputs a low level, but the NAND gate 132 in the second arbitration circuit 131 outputs a low level, and the inverter 133 outputs a high level, and finally the first arbitration circuit 131 outputs a high level, and the first processor 111 fails. That is, among the other three processors except the processor to be diagnosed, if two of them judge that the processor to be diagnosed is faulty, the processor to be diagnosed is faulty.

After fault detection, the arbitration module 13 outputs the diagnosis result of the first processor 111 to the second processor 112, the third processor 121 and the fourth processor 122. If the diagnosis result is that the first processor 111 is faulty, the third processor 121 is the first target processor, the second processor 112 is the second target processor, the first processor 111 sends synchronization information to the third processor 121, and the third processor 121 is connected to the second processor 112 according to the synchronization information to form a target data transmission path to achieve data transmission.

When the master control circuit 11 includes a target data transmission path, the first processor 111 and the second processor 112 can both serve as processors to be diagnosed; when the slave control circuit 12 includes a target data transmission path, the third processor 121 and the fourth processor 122 can both serve as processors to be diagnosed.

Optionally, the speed regulator 10 also includes a verification module for determining whether the processor to be diagnosed is faulty and outputting the diagnosis result of the processor to be diagnosed to the other three processors, where the processor to be diagnosed is each processor in the main control circuit 11; when the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends synchronization information to the first target processor.

In the speed regulator 10, the processor to be diagnosed sends verification information to the other three processors, and the other three processors determine whether the processor to be diagnosed is faulty based on the verification information, and transmit the diagnostic information to the arbitration module 13 to generate a diagnostic result according to the method of taking two out of three. Taking two out of three can avoid the processor that originally has a fault in the other three processors from confusing the processor to be diagnosed. If the processor to be diagnosed fails, synchronization information is sent to the same type of processor in the slave control circuit 12, so that the first target processor and the second target processor form a new target data transmission path, thereby avoiding the situation where the system cannot operate due to a single point failure of the processor to be diagnosed.

As shown in FIG4 , in one embodiment, the speed regulator 10 further includes a first isolation circuit 14, and the two processors in the main control circuit 11 are respectively connected to the two processors of the slave control circuit 12 via the first isolation circuit 14. The first isolation circuit 14 includes a first isolation unit 141, a second isolation unit 142, a third isolation unit 143 and a fourth isolation unit 144. The first isolation unit 141 is respectively connected to the first processor of the main control circuit 11 and the first processor of the slave control circuit 12; the second isolation unit 142 is respectively connected to the first processor of the main control circuit 11 and the second processor of the slave control circuit 12; the third isolation unit 143 is respectively connected to the second processor of the main control circuit 11 and the first processor of the slave control circuit 12; the fourth isolation unit 144 is respectively connected to the second processor of the main control circuit 11 and the second processor of the slave control circuit 12; wherein the first processor of the main control circuit 11 and the first processor of the slave control circuit 12 are of the same type. The first isolation unit 141, the second isolation unit 142, the third isolation unit 143 and the fourth isolation unit 144 respectively include at least one magnetic isolator.

Exemplarily, the first processor 111 is connected to the third processor 121 via the first isolation unit 141, the first processor 111 is connected to the fourth processor 122 via the second isolation unit 142, the second processor 112 is connected to the third processor 121 via the third isolation unit 143, and the second processor 112 is connected to the fourth processor 122 via the fourth isolation unit 144. For example, when the first processor 111 is a processor to be diagnosed, if the diagnosis result is that the first processor 111 is faulty, the third processor 121 controls the first isolation unit 141 to be disconnected according to the diagnosis result after receiving the synchronization information, and the fourth processor 122 controls the second isolation unit 142 to be disconnected according to the diagnosis result; when the second processor 112 is a processor to be diagnosed, if the diagnosis result is that the second processor 112 is faulty, the fourth processor 122 controls the fourth isolation unit 144 to be disconnected according to the diagnosis result after receiving the synchronization information, and the third processor 121 controls the third isolation unit 143 to be disconnected according to the diagnosis result.

Optionally, the connection path between the first processor 111 and the fourth processor 122, and the connection path between the second processor 112 and the third processor 121 may include the same magnetic isolator; the magnetic isolator in the connection path between the first processor 111 and the fourth processor 122, and the magnetic isolator in the connection path between the second processor 112 and the third processor 121 may be different, and there is no limitation here.

The speed regulator 10 above prevents the system from being confused by the erroneous information output by the faulty processor by cutting off the output of the isolation unit connecting the other three processors to the faulty processor to be diagnosed.

As shown in FIG. 5 , in one embodiment, the speed regulator 10 further includes a first input acquisition circuit 15 , a first output processing circuit 16 , a second input acquisition circuit 17 , a second output processing circuit 18 , a second isolation circuit 19 and a third isolation circuit 20 .

The first input acquisition circuit 15 is connected to the main control unit via the first magnetic isolator 191 in the second isolation circuit 19, and is connected to the slave control unit via the fourth magnetic isolator 201 in the third isolation circuit 20, and is used to collect and process the received analog input signal, and transmit the processed analog input signal to the target control circuit. The circuit schematic diagram of the first input acquisition circuit 15 is shown in FIG6. The first input acquisition circuit 15 includes an analog-to-digital converter 151, and the analog input signal includes a current signal. After the current signal input from the printed circuit board passes through the first field effect transistor 152, it forms a voltage signal through the voltage divider circuit 153. After the voltage signal is conditioned by the first operational amplifier 154, the robustness and load capacity of the voltage signal are improved through the voltage follower 155, which is convenient for subsequent sampling, and finally enters the analog-to-digital converter 151 for analog-to-digital conversion to generate a digital signal, and the digital signal is transmitted to the target control circuit through the SPI interface of the analog-to-digital converter 151.

Exemplarily, when the main control circuit 11 is the target data transmission path, if the first processor 111 and the second processor 112 have no faults, the first magnetic isolator 191 is not locked, the fourth magnetic isolator 201 is in a locked state, and the digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 via the SPI bus for processing; if only the first processor 111 fails, the third processor 121 serves as the first target processor and the second processor 112 serves as the second target processor, then the first magnetic isolator 191 is not locked, the fourth magnetic isolator 201 is in a locked state, and the digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 via the SPI bus for processing; if only the second processor 112 fails, the fourth processor 122 serves as the first target processor and the first processor 111 serves as the second target processor, then the fourth magnetic isolator 201 is not locked, the first magnetic isolator 191 is locked, and the digital signal output by the first input acquisition circuit 15 is transmitted to the second processor 112 via the SPI bus for processing. The bus is transmitted to the fourth processor 122 for processing; if both the first processor 111 and the second processor 112 fail, the fourth magnetic isolator 201 is not locked, the first magnetic isolator 191 is locked, and the digital signal output by the first input acquisition circuit 15 is transmitted to the fourth processor 122 for processing via the SPI bus.

The first output processing circuit 16 is connected to the main control unit via the second magnetic isolator 192 in the second isolation circuit 19, and is connected to the slave control unit via the fifth magnetic isolator 202 in the third isolation circuit 20, and is used to receive and process the analog output signal from the target control circuit. The circuit schematic diagram of the first output processing circuit 16 is shown in FIG7, and the first output circuit includes a digital-to-analog converter 161. The digital-to-analog conversion instruction generated by the second processor 112 of the target control circuit is sent to the digital-to-analog converter 161 via the SPI bus to form an initial signal for digital-to-analog conversion. The initial signal is processed by the second operational amplifier 162 to generate a common voltage for current and voltage output. A part of the common voltage is processed by the fourth operational amplifier 164, the fifth operational amplifier 165, the second field effect transistor 166 and the third field effect transistor 167 to generate a standard current signal, and the other part of the common voltage is processed by the third operational amplifier 163 to generate a standard voltage signal. The standard current signal and the standard voltage signal are output from the wiring terminal of the printed circuit board as the analog output signal output by the first output processing circuit 16.

Exemplarily, when the main control circuit 11 is the target data transmission path, if the first processor 111 and the second processor 112 are not faulty, the second magnetic isolator 192 is not locked, the fifth magnetic isolator 202 is in a locked state, and the digital-to-analog conversion instruction output by the second processor 112 is input to the first output processing circuit 16 via the SPI bus; if only the first processor 111 fails, the third processor 121 serves as the first target processor and the second processor 112 serves as the second target processor, then the second magnetic isolator 192 is not locked, the fifth magnetic isolator 202 is in a locked state, and the digital-to-analog conversion instruction output by the second processor 112 is input to the first output processing circuit 16 via the SPI bus. The bus is input to the first output processing circuit 16; if only the second processor 112 fails, the fourth processor 122 serves as the first target processor, and the first processor 111 serves as the second target processor, then the fifth magnetic isolator 202 is not locked, the second magnetic isolator 192 is locked, and the digital-to-analog conversion instruction output by the fourth processor 122 is input to the first output processing circuit 16 via the SPI bus; if both the first processor 111 and the second processor 112 fail, then the fifth magnetic isolator 202 is not locked, the second magnetic isolator 192 is locked, and the digital-to-analog conversion instruction output by the fourth processor 122 is input to the first output processing circuit 16 via the SPI bus.

The second input acquisition circuit 17 is connected to the main control unit via the third magnetic isolator 193 in the second isolation circuit 19, and is connected to the slave control circuit 12 via the sixth magnetic isolator 203 in the third isolation circuit 20, and is used to collect and process the received switch input signal, and transmit the processed switch input signal to the target control circuit. The circuit schematic diagram of the second input acquisition circuit 17 is shown in FIG8 , and the second input acquisition circuit 17 includes a first photoelectric isolator 171.

The second output processing circuit 18 is connected to the main control unit via the third magnetic isolator 193 in the second isolation circuit 19, and is connected to the slave control circuit 12 via the sixth magnetic isolator 203 in the third isolation circuit 20, and is used to receive and process the switch output signal from the target control circuit; wherein the target control circuit is one of the two control circuits. The circuit schematic diagram of the second output processing circuit 18 is shown in FIG9, and the second input acquisition circuit 17 includes a second photoelectric isolator 181.

In the speed regulator 10, when the first processor 111 and the second processor 112 are used as target data transmission paths, the first processor 111 outputs a low level to control the third isolation unit 143 to be locked, so that the magnetic isolator in the third isolation unit 143 cannot output, thereby enabling the first input acquisition circuit 15, the first output processing circuit 16 to exchange information with the second processor 112; when the first processor 111 and the fourth processor 122 are used as target data transmission paths, the first processor 111 outputs a low level to control the locking of the second isolation unit 142, so that the magnetic isolator in the second isolation unit 142 cannot output, thereby enabling the first input acquisition circuit 15, the first output processing circuit 16 to exchange information with the fourth processor 122. By controlling the second isolation unit 142 and the third isolation unit 143, SPI bus authority conflicts are avoided.

As shown in Figures 10 and 11, in one embodiment, the speed regulator 10 also includes a power module 21, and the power module 21 includes an inverter unit 211, a first system power unit 212, a second system power unit 213 and an interface power unit 214. The schematic diagram of the power module 21 is shown in Figure 11. The inverter unit 211 is used to receive an external power supply voltage and perform a voltage drop process on the power supply voltage to obtain a voltage drop voltage; the first system power unit 212 is connected to the inverter unit 211, and is used to rectify, regulate, and filter the voltage drop voltage to obtain a first power supply voltage, and output it to the main control circuit 11; the second system power unit 213 is connected to the inverter unit 211, and is used to rectify, regulate, and filter the voltage drop voltage to obtain a second power supply voltage, and output it to the slave control circuit 12; the interface power unit 214 is connected to the inverter unit 211, and is used to rectify, regulate, and filter the voltage drop voltage to obtain a third power supply voltage, and output it to the first input acquisition circuit 15, the second ... An output processing circuit 16 , a second input acquisition circuit 17 , and a second output processing circuit 18 .

The above-mentioned speed regulator 10 realizes redundancy of system working power supply and interface power supply by setting the first system power supply to power the main control circuit 11, the second system power supply to power the slave control circuit 12, and the interface power supply unit 214 to power the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18. When one of the system power supplies fails, the other system power supply powers the control circuit that has not failed, so that the control circuit that has not failed can be used as the target transmission path to realize data transmission.

As shown in FIG. 12 , in one embodiment, the speed regulator 10 further includes a human-machine interface (HMI), the main control circuit 11 includes a first CPU and a first FPGA, and the slave control circuit 12 includes a second CPU and a second FPGA. The first input acquisition circuit 15 includes an analog-to-digital converter 151 (ADC), and the first output processing circuit 16 includes a digital-to-analog conversion 161 (DAC). The second input acquisition circuit 17 includes a first photoelectric isolator 171 for primary isolation, and the second output processing circuit 18 includes a second photoelectric isolator 181 for primary isolation. The first system power supply unit 212 supplies power to the first CPU and the first FPGA, the second system power supply unit 213 supplies power to the second CPU and the second FPGA, and the interface power supply unit 214 supplies power to the first input acquisition circuit 15, the first output processing circuit 16, the second input acquisition circuit 17, and the second output processing circuit 18. Since the first CPU, the second CPU and the second FPGA use different system power supplies, the first CPU is connected to the second CPU and the first FPGA through a magnetic isolator; since the first FPGA, the second CPU and the second FPGA use different system power supplies, the first FPGA is connected to the second CPU and the second FPGA through a magnetic isolator; since the first CPU and the first FPGA, the second CPU and the second FPGA use the same system power supply, the first CPU is directly connected to the first FPGA, and the second CPU is directly connected to the second FPGA.

When the system is powered on, taking the main control circuit 11 as the target control circuit as an example, the first CPU sends verification information to the second CPU, the first FPGA, and the second FPGA, and the arbitration circuit uses the diagnostic information generated by the other three to take two out of three to diagnose whether the first CPU is faulty; the first FPGA sends verification information to the first CPU, the second CPU, and the second FPGA, and the arbitration circuit uses the diagnostic information generated by the other three to take two out of three to diagnose whether the first FPGA is faulty.

If the first CPU fails, the first CPU sends synchronization information to the second CPU via serial communication, so that the second CPU can transmit target data with the first FPGA via parallel port communication; if the first FPGA fails, the first FPGA sends synchronization information to the second FPGA via serial communication, so that the second FPGA can transmit target data with the first CPU via parallel port communication; if both the first CPU and the first FPGA are not faulty, the first CPU outputs a low level to control the third isolation circuit 20 to lock, thereby avoiding bus manipulation authority conflicts, and transmitting target data between the first CPU and the first FPGA; if both the first CPU and the first FPGA fail, the first CPU sends synchronization information to the second CPU via serial communication, and the first FPGA sends synchronization information to the second FPGA via serial communication, so that the second CPU can transmit target data with the second FPGA via parallel port communication.

In the speed regulator 10, two different types of processors in the main control circuit 11 realize data transmission. Through the setting of the slave control circuit 12, when the processor in the main control circuit 11 fails, a processor of the same type as the failed processor in the slave control circuit 12 is used to replace it, and continues to process the data to be processed by the failed processor, and realizes data transmission with the processor without failure in the main control circuit 11. If all the processors in the main control circuit 11 fail, data processing and transmission are performed by the two processors of the slave control circuit 12. The design of the dual control circuit avoids the situation where a single point failure causes a system failure.

As shown in FIG13 , in one embodiment, a control method for a speed regulator is provided, which is applied to the speed regulator in any of the above embodiments, and the method includes:

Step S100: obtaining a temperature value according to a signal to be started to determine a start-up state.

The waiting start signal is a signal indicating that the speed regulator starts working, the temperature value is the external environment temperature value, and the start state includes a hot start state and a cold start state. When the temperature value is greater than or equal to the preset temperature value, it is a hot start state; when the temperature value is less than the preset temperature value, it is a cold start state.

When the speed regulator is powered on, it first performs a self-check and determines whether the current state meets the state requirements. If so, the temperature value is obtained according to the start-up signal to determine the start-up state of the speed regulator.

Step S210: When the startup state is a hot start state, the speed of the steam turbine is controlled to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed.

Among them, the first preset rate may be 500 rpm/min, and the first preset rotation speed may be 4440 rpm.

When it is determined to be in hot start state, the governor outputs an opening signal to control the opening of the turbine's regulating valve to control the speed of the turbine, and controls the speed of the turbine to increase by 500 rpm per minute until the turbine speed reaches 4440 rpm, and the start-up is completed.

Step S220: When the startup state is a cold start state, the speed of the steam turbine is controlled to increase at a second preset rate until the real-time speed of the steam turbine is greater than or equal to the second preset speed and then enters a warm-up state, and after a preset time, the speed of the steam turbine is controlled to continue to increase at the second preset rate until the real-time speed of the steam turbine is greater than or equal to a third preset speed. The speed of the steam turbine is controlled to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed.

Among them, the second preset rate may be 125 rpm/min, the second preset rotation speed may be 700 rpm, the third preset rotation speed may be 3100 rpm, and the preset time may be 10 min.

When it is judged to be a cold start state, the speed governor outputs an opening signal to control the opening of the turbine's regulating valve and thus controls the speed of the turbine. The speed of the turbine is controlled to increase at 125rpm per minute until the turbine speed reaches 700rpm. The speed governor enters the warm-up state. After 10 minutes, the speed governor continues to control the speed of the turbine to increase at 125rpm per minute until the turbine speed reaches 300rpm. The speed governor controls the speed of the turbine to increase at 500rpm per minute until the turbine speed reaches 4440rpm, and the start-up is completed.

Step S300: adjusting the speed of the steam turbine according to the set speed based on the startup completion signal.

The set speed is a speed set manually.

In the control method of the above-mentioned speed regulator, two different types of processors in the main control circuit realize data transmission. Through the setting of the slave control circuit, when the processor in the main control circuit fails, a processor of the same type as the failed processor in the slave control circuit is used to replace it, and the data to be processed by the failed processor is continued to be processed, and data transmission is realized with the processor without fault in the main control circuit. If the processors in the main control circuit are all faulty, data processing and transmission are performed through the two processors of the slave control circuit. The design of the dual control circuit avoids the occurrence of system failure caused by single point failure. The speed regulator can normally input and output signals to control the speed regulation of the steam turbine, and change the speed regulation method according to the temperature to better control the speed regulation of the steam turbine.

It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flow chart may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims (15)

1. A speed regulator, characterized in that it comprises: two control circuits, each of the control circuits comprises two processors, the four processors are connected to each other, and the types of the two processors in the same control circuit are different;

   When a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor is connected to the second target processor to form a target data transmission path to achieve data transmission;

   Among them, the first target processor is a processor in the slave control circuit that is of the same type as the fault processor, the second target processor is of a different type from the first target processor, the master control circuit is one of the two control circuits, and the slave control circuit is the other of the two control circuits.
2. The speed regulator according to claim 1 is characterized in that when one processor in the main control circuit fails, the second target processor is a normal processor in the main control circuit; when both processors in the main control circuit fail, the second target processor is a processor in the slave control circuit.
3. The speed regulator according to claim 1, characterized in that the processor to be diagnosed in the main control circuit sends inspection information to the other three processors respectively, so that the other three processors generate diagnostic information according to the inspection information;

   The speed regulator also includes:

   an arbitration module, connected to the four processors respectively, for determining whether the processor to be diagnosed is faulty according to the diagnostic information output by the other three processors, and outputting the diagnostic result of the processor to be diagnosed to the other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

   When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.
4. The speed regulator according to claim 3 is characterized in that the arbitration module includes four arbitration circuits, each of the processors to be diagnosed is configured with one arbitration circuit, each of the arbitration circuits is respectively connected to the other three processors, and the other three processors are processors other than the processor to be diagnosed configured by the arbitration circuit; the arbitration circuit includes: three arbitration units, two input ends of each arbitration unit are respectively connected to two processors of the other three processors, the output end of each arbitration unit is respectively connected to the other three processors, and one input end of every two arbitration units is connected to the same processor, and each arbitration unit includes: a NAND gate and an inverter, wherein,

   The two input ends of the NAND gate are respectively connected to two processors among the other three processors, and the output end of the NAND gate is connected to the input end of the inverter;

   The output ends of the inverter are connected to the other three processors respectively.
5. The speed regulator according to claim 3 is characterized in that the speed regulator further comprises a first isolation circuit, and the two processors in the master control circuit are respectively connected to the two processors of the slave control circuit via the first isolation circuit; the first isolation circuit comprises:

   a first isolation unit, connected to the first processor of the master control circuit and the first processor of the slave control circuit respectively;

   a second isolation unit, connected to the first processor of the master control circuit and the second processor of the slave control circuit respectively;

   A third isolation unit is connected to the second processor of the master control circuit and the first processor of the slave control circuit respectively; and

   a fourth isolation unit, connected to the second processor of the master control circuit and the second processor of the slave control circuit respectively; wherein the first processor of the master control circuit and the first processor of the slave control circuit are of the same type;

   When the diagnosis result shows that the processor to be diagnosed is a faulty processor, the other three processors respectively control the isolation units connected to the faulty processor according to the diagnosis result to disconnect the data transmission paths connected to the faulty processor respectively.
6. The speed regulator according to claim 1, characterized in that the speed regulator further comprises:

   a first input acquisition circuit, connected to the master control circuit and the slave control circuit respectively, for acquiring and processing received analog input signals, and transmitting the processed analog input signals to a target control circuit;

   a first output processing circuit, connected to the master control circuit and the slave control circuit respectively, and used for receiving and processing the analog output signal from the target control circuit;

   a second input acquisition circuit, connected to the master control circuit and the slave control circuit respectively, for acquiring and processing received switch input signals, and transmitting the processed switch input signals to the target control circuit; and,

   The second output processing circuit is connected to the main control circuit and the slave control circuit respectively, and is used to receive and process the switch output signal from the target control circuit; wherein the target control circuit is one of the two control circuits.
7. The speed regulator according to claim 6 is characterized in that the first input acquisition circuit includes an analog-to-digital converter, and the first output processing circuit includes a digital-to-analog converter.
8. The speed regulator according to claim 6, characterized in that the speed regulator further comprises:

   A second isolation circuit is connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the main control circuit respectively; and,

   a third isolation circuit, connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and the second processor of the slave control circuit, respectively; wherein the second processor of the master control circuit is of the same type as the second processor of the slave control circuit;

   When the processor in the main control circuit has no fault, the main control circuit controls the third isolation circuit to be in a locked state;

   When the second processor in the main control circuit fails, the main control circuit controls the second isolation circuit to be in a locked state.
9. The speed regulator according to claim 8 is characterized in that the second input acquisition circuit includes a first photoelectric isolator for isolating the collected switch input signal; the second output processing circuit includes a second photoelectric isolator for isolating the received switch output signal; the second isolation circuit includes:

   A first magnetic isolator is connected to the first input acquisition circuit and the second processor of the main control circuit respectively;

   A second magnetic isolator is connected to the first output processing circuit and the second processor of the main control circuit respectively; and

   A third magnetic isolator is connected to the first photoelectric isolator, the second photoelectric isolator, and the second processor of the main control circuit respectively;

   The third isolation circuit comprises:

   a fourth magnetic isolator, connected to the first input acquisition circuit and the second processor of the slave control circuit respectively;

   a fifth magnetic isolator connected to the first output processing circuit and the second processor of the slave control circuit respectively; and

   The sixth magnetic isolator is connected to the first photoelectric isolator, the second photoelectric isolator, and the second processor of the slave control circuit respectively.
10. The speed regulator according to claim 6, characterized in that the speed regulator further comprises:

    a power supply module, connected to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, the second output processing circuit, and each of the control circuits, respectively, and used to provide a power supply voltage;

    Wherein, the power module comprises:

    An inverter unit, used for receiving an external power supply voltage and performing voltage drop processing on the power supply voltage to obtain a voltage drop voltage;

    a first system power supply unit, connected to the inverter unit, for rectifying, regulating and filtering the voltage drop voltage to obtain a first power supply voltage, and outputting the first power supply voltage to the main control circuit;

    a second system power supply unit connected to the inverter unit, for rectifying, regulating and filtering the voltage drop voltage to obtain a second power supply voltage, and outputting the second power supply voltage to the slave control circuit; and,

    An interface power supply unit is connected to the inverter unit and is used to rectify, regulate and filter the voltage drop. The third power supply voltage is obtained by processing and outputted to the first input acquisition circuit, the first output processing circuit, the second input acquisition circuit, and the second output processing circuit.
11. The speed regulator according to claim 1 is characterized in that when a processor in the main control circuit fails, the faulty processor in the main control circuit sends synchronization information to the first target processor in the slave control circuit, so that the first target processor is connected to the second target processor in the main control circuit via another processor in the slave control circuit to form a target data transmission path to achieve data transmission.
12. The speed regulator according to claim 1, characterized in that the speed regulator further comprises:

    A verification module, connected to the four processors respectively, for determining whether the processor to be diagnosed is faulty and outputting the diagnosis result of the processor to be diagnosed to the other three processors, wherein the processor to be diagnosed is each processor in the main control circuit;

    When the diagnosis result is that the processor to be diagnosed is a faulty processor, the faulty processor sends the synchronization information to the first target processor.
13. The speed regulator according to claim 1 is characterized in that the speed regulator also includes a human-machine interface.
14. The speed regulator according to claim 1 is characterized in that the master control circuit includes a first CPU and a first FPGA, and the slave control circuit includes a second CPU and a second FPGA.
15. A control method for a speed regulator, characterized in that it is applied to the speed regulator according to any one of claims 1 to 14, and the method comprises:

    Acquire the temperature value according to the signal to be started to determine the start state;

    When the startup state is a hot startup state, controlling the speed of the steam turbine to increase at a first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed;

    When the startup state is a cold start state, the speed of the steam turbine is controlled to increase at a second preset rate until the real-time speed of the steam turbine is greater than or equal to the second preset speed and then enters a warm-up state; after a preset time, the speed of the steam turbine is controlled to continue to increase at the second preset rate until the real-time speed of the steam turbine is greater than or equal to a third preset speed, and then the speed of the steam turbine is controlled to increase at the first preset rate until the real-time speed of the steam turbine is greater than or equal to the first preset speed; and,

    The speed of the steam turbine is adjusted according to the set speed based on the startup completion signal.